Semiconductor device and method for manufacturing semiconductor device

Abstract

In the present invention, a semiconductor device comprises a gallium-containing first nitride semiconductor layer, and a gallium-containing second nitride semiconductor layer that is formed on the first nitride semiconductor layer, the second nitride semiconductor layer having a plurality of third nitride semiconductor layers and fourth nitride semiconductor layers that are alternatingly laminated on the first nitride semiconductor layer. The third nitride semiconductor layer contains an impurity of a first conductivity type in a first concentration, and the fourth nitride semiconductor layer contains an impurity of the first conductivity type in a second concentration that is higher than the first concentration, the first concentration being at least 1×1020cm-3.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] This application claims priority based on Japanese Application No. 2022-096882 filed on June 15, 2022, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] 2. Description of the Related Art In order to reduce contact resistance and the like in semiconductor devices using nitride semiconductors, a structure has been proposed in which a nitride semiconductor layer containing a high concentration of impurities is regrown.

[0004] Japanese Patent Publication No. 2008-270749 Japanese Patent Publication No. 2019-041113 Japanese Patent Publication No. 2017-059671

[0005] Applied Physics Express, 2 (2009) 051001

[0006] A semiconductor device according to the present disclosure includes a first nitride semiconductor layer containing gallium, and a second nitride semiconductor layer containing gallium formed on the first nitride semiconductor layer, the second nitride semiconductor layer including a plurality of third nitride semiconductor layers and a fourth nitride semiconductor layer alternately stacked on the first nitride semiconductor layer, the third nitride semiconductor layer containing a first conductivity type impurity at a first concentration, the fourth nitride semiconductor layer containing the first conductivity type impurity at a second concentration higher than the first concentration, and the first concentration being 1×10 ２０ cm －３ That's all.

[0007] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing an n-type GaN layer according to the first embodiment. FIG. 3 is a diagram showing the relationship between the depth from the surface of the n-type GaN layer and the impurity concentration according to the first embodiment. FIG. 4 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view (part 6) showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 10 is a timing chart showing a method for forming an n-type GaN layer according to the first embodiment. FIG. 11 is a cross-sectional view (part 1) showing a method for forming an n-type GaN layer according to the first embodiment. FIG. 12 is a cross-sectional view (part 2) showing a method for forming an n-type GaN layer according to the first embodiment. FIG. 13 is a cross-sectional view (part 3) illustrating a method for forming an n-type GaN layer in the first embodiment. FIG. 14 is a cross-sectional view (part 4) illustrating a method for forming an n-type GaN layer in the first embodiment. FIG. 15 is a cross-sectional view (part 5) illustrating a method for forming an n-type GaN layer in the first embodiment. FIG. 16 is a diagram illustrating another example of the relationship between the depth from the surface of the n-type GaN layer and the impurity concentration in the first embodiment. FIG. 17 is a diagram illustrating the relationship between the continuous supply time of Ga, the droplet size L1, and the difference between the migration length L2 and the droplet size L1. FIG. 18 is a cross-sectional view (part 1) illustrating a phenomenon that occurs when the continuous supply time of Ga is too long. FIG. 19 is a cross-sectional view (part 2) illustrating a phenomenon that occurs when the continuous supply time of Ga is too long. FIG. 20 is a cross-sectional view of a semiconductor device according to the second embodiment. FIG. 21 is a cross-sectional view of an n-type GaN layer in the second embodiment. FIG. 22 is a cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to the second embodiment. Fig. 23 is a cross-sectional view (part 2) showing the method for manufacturing a semiconductor device according to the second embodiment, Fig. 24 is a cross-sectional view (part 3) showing the method for manufacturing a semiconductor device according to the second embodiment, and Fig. 25 is a cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the second embodiment.26 and 27 are cross-sectional views (part 4 and part 5) illustrating the method for manufacturing a semiconductor device according to the second embodiment.

[0008] [Problem to be Solved by the Present Disclosure] In conventional semiconductor devices, there is a risk that the electrical characteristics may be degraded due to the precipitation of impurity elements.

[0009] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress degradation of electrical characteristics due to precipitation of impurity elements.

[0010] Effect of the Present Disclosure According to the present disclosure, it is possible to suppress the deterioration of electrical characteristics due to the precipitation of impurity elements.

[0011] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0012] [1] A semiconductor device according to one aspect of the present disclosure includes a first nitride semiconductor layer containing gallium, and a second nitride semiconductor layer containing gallium formed on the first nitride semiconductor layer, the second nitride semiconductor layer including a plurality of third nitride semiconductor layers and a fourth nitride semiconductor layer alternately stacked on the first nitride semiconductor layer, the third nitride semiconductor layer containing a first conductivity type impurity at a first concentration, the fourth nitride semiconductor layer containing the first conductivity type impurity at a second concentration higher than the first concentration, and the first concentration being 1×10 ２０ cm －３ That's all.

[0013] The third nitride semiconductor layer contains 1×10 impurities of the first conductivity type. ２０ cm －３The third nitride semiconductor layer contains the first conductivity type impurity at a first concentration or higher, and the fourth nitride semiconductor layer contains the first conductivity type impurity at a second concentration higher than the first concentration. Therefore, it is possible to suppress deterioration of electrical characteristics due to precipitation of the impurity element. Furthermore, because the third nitride semiconductor layer and the fourth nitride semiconductor layer having different impurity concentrations are alternately stacked, good crystallinity can be obtained despite the high impurity concentration. Furthermore, the third nitride semiconductor layer and the fourth nitride semiconductor layer can be formed by, for example, physical vapor deposition. In other words, it is possible to form the third nitride semiconductor layer and the fourth nitride semiconductor layer having good crystallinity using an existing film formation apparatus.

[0014] [2] In the structure of [1], the third nitride semiconductor layer and the fourth nitride semiconductor layer may be stacked at a period of 8 nm or less. The smaller this period, the easier it is to obtain good crystallinity in the second nitride semiconductor layer.

[0015] [3] In [1] or [2], the difference between the first concentration and the second concentration is 1×10 ２０ cm －３ 7 x 10 or more ２０ cm －３ If this concentration difference is too small or too large, it may be difficult to obtain good crystallinity in the second nitride semiconductor layer.

[0016] [4] In any one of [1] to [3], the impurity may be germanium or silicon. When the impurity is germanium or silicon, low electrical resistance is easily obtained in the second nitride semiconductor layer.

[0017] [5] In any one of [1] to [4], an ohmic electrode may be formed on the second nitride semiconductor layer, in which case low electrical resistance is obtained between the first nitride semiconductor layer and the ohmic electrode.

[0018] [6] In any one of [1] to [5], the surface of the first nitride semiconductor layer in contact with the lower surface of the second nitride semiconductor layer may be a nitrogen-polar surface. In this case, low resistance can be easily achieved.

[0019] [7] In [6], the first nitride semiconductor layer may have a barrier layer and a channel layer provided above the barrier layer. In this case, low resistance can be easily achieved.

[0020] [8] In the device of [6] or [7], an insulating layer may be formed on the first nitride semiconductor layer, an opening exposing the first nitride semiconductor layer may be formed in the insulating layer, and the second nitride semiconductor layer may be formed in the opening. In this case, low resistance can be easily achieved while protecting the first nitride semiconductor layer with the insulating layer.

[0021] [9] In any one of [1] to [5], the surface of the first nitride semiconductor layer in contact with the lower surface of the second nitride semiconductor layer may be a gallium-polar surface, which facilitates growth of the first nitride semiconductor layer and facilitates obtaining good etching resistance on the upper surface of the first nitride semiconductor layer.

[0022]

[10] In the configuration of [9], the first nitride semiconductor layer may have a channel layer and a barrier layer provided above the channel layer. In this case, the first nitride semiconductor layer is easily grown and good etching resistance is easily obtained on the upper surface of the first nitride semiconductor layer.

[0023]

[11] In the structure of [9] or

[10] , a recess may be formed in the first nitride semiconductor layer, and the second nitride semiconductor layer may be formed in the recess. In this case, low resistance can be easily achieved.

[0024]

[12] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes forming a second nitride semiconductor layer containing gallium on a first nitride semiconductor layer containing gallium by physical vapor deposition, wherein the forming of the second nitride semiconductor layer includes repeating the following steps: forming a third nitride semiconductor layer containing an impurity of a first conductivity type at a first concentration, and forming droplets of an alloy of gallium and the impurity on a surface of the third nitride semiconductor layer; and evaporating a portion of the gallium from the droplets and nitriding another portion of the gallium in the droplets while incorporating the impurity in the droplets, thereby forming a fourth nitride semiconductor layer containing the impurity of the first conductivity type at a second concentration higher than the first concentration.

[0025] When forming the second nitride semiconductor layer by physical vapor deposition, the formation of a third nitride semiconductor layer and the formation of a fourth nitride semiconductor layer are repeated. When forming the third nitride semiconductor layer, droplets of an alloy of gallium and impurities are formed on the surface of the third nitride semiconductor layer, and when forming the fourth nitride semiconductor layer, part of the gallium is evaporated from the droplets, and the impurities in the droplets are taken in while the other part of the gallium in the droplets is nitrided. Therefore, the third nitride semiconductor layer can be formed to a thickness of, for example, 1×10 ２０ cm －３ Even when the third nitride semiconductor layer and the fourth nitride semiconductor layer contain the first conductivity type impurity at such a high concentration, good crystallinity can be obtained, which prevents the impurity from remaining on the surface of the second nitride semiconductor layer and prevents the deterioration of electrical characteristics caused by the precipitates.

[0026]

[13] In the method of

[12] , the droplets may be removed in the step of forming the fourth nitride semiconductor layer. If the droplets remain, the crystallinity of the fourth nitride semiconductor layer may be reduced.

[0027]

[14] In the method of

[12] or

[13] , the step of forming the fourth nitride semiconductor layer may take longer than the step of forming the third nitride semiconductor layer. In this case, the droplets are more likely to disappear.

[0028]

[15] In any one of

[12] to

[14] , the third nitride semiconductor layer and the fourth nitride semiconductor layer may be formed in a chamber, and in the steps of forming the third nitride semiconductor layer and the fourth nitride semiconductor layer, a saturated vapor pressure of gallium at a temperature in the chamber may be lower than a pressure in the chamber. In this case, droplets containing gallium are likely to be formed stably.

[0029]

[16] In any of

[12] to

[15] , the first nitride semiconductor layer may be formed on a substrate, and the temperature of the substrate when forming the third nitride semiconductor layer and the fourth nitride semiconductor layer may be 200° C. or higher and 650° C. or lower. If the substrate temperature is too low, it may be difficult to form the third nitride semiconductor layer and the fourth nitride semiconductor layer, and if the substrate temperature is too high, there is a risk of damage to the first nitride semiconductor layer and the like that has already been formed.

[0030] [Details of the Embodiments of the Present Disclosure] The following describes in detail the embodiments of the present disclosure, but the present disclosure is not limited thereto. Note that in this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description.

[0031] First Embodiment First, a first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0032] As shown in FIG. 1 , the semiconductor device 100 according to the first embodiment mainly includes a substrate 101, a nitride semiconductor layer 110, an insulating layer 121, an n-type GaN (gallium nitride) layer 131S, an n-type GaN layer 131D, a gate electrode 141, a source electrode 132S, a drain electrode 132D, and an insulating layer 142.

[0033] The substrate 101 is, for example, a substrate for growing a GaN-based semiconductor, and in one example, is a semi-insulating SiC (silicon carbide) substrate. When the substrate 101 is a SiC substrate, the surface of the substrate 101 is a carbon (C) polarity plane. When the surface of the substrate 101 is a C polarity plane, the nitride semiconductor layer 110 can be grown as a crystal with the nitrogen (N) polarity plane as the growth plane. A sapphire substrate may also be used as the substrate for growing a GaN-based semiconductor. The substrate 101 does not have to be a substrate for crystal growth. In this case, the substrate 101 may be removed from the nitride semiconductor layer 110 grown on another substrate, and the substrate 101 may be bonded to the nitride semiconductor layer 110. In this case, a semi-insulating substrate made of various materials may be used as the substrate 101, and examples thereof include a sapphire substrate, a Si (silicon) substrate, a SiC substrate, an AlN (aluminum nitride) substrate, and a sintered body.

[0034] The nitride semiconductor layer 110 includes a buffer layer 111, a barrier layer 112, and a channel layer 113. The nitride semiconductor layer 110 is an example of a first nitride semiconductor layer.

[0035] The buffer layer 111 is, for example, an AlN layer. The thickness of the AlN layer is, for example, 5 nm or more and 100 nm or less. The buffer layer 111 may include an AlN layer and a GaN layer or an AlGaN (aluminum gallium nitride) layer on the AlN layer. The thickness of the GaN layer or AlGaN layer is, for example, 300 nm or more and 2000 nm or less.

[0036] The barrier layer 112 is, for example, an AlGaN layer. The band gap of the barrier layer 112 is larger than the band gap of the channel layer 113 described later. The thickness of the barrier layer 112 is, for example, in the range of 5 nm to 50 nm, and in one embodiment, is 30 nm. ｘ Ga １－ｘ In the case of an N layer, the Al composition x is, for example, 0.15 to 0.55, inclusive, and in one embodiment, 0.35. The conductivity type of the barrier layer 112 is, for example, n-type or undoped (i-type). Instead of the AlGaN layer, an InAlN layer (indium aluminum nitride) or an InAlGaN (indium aluminum gallium nitride) layer may be used.

[0037] The channel layer 113 is, for example, a GaN layer. The band gap of the channel layer 113 is smaller than the band gap of the barrier layer 112. The thickness of the channel layer 113 is, for example, 5 nm to 30 nm, and in one embodiment, 9 nm. Strain occurs between the channel layer 113 and the barrier layer 112 due to the difference in their lattice constants. This strain induces piezoelectric charges at the interface between the two layers. As a result, a two-dimensional electron gas (2DEG) is generated in the region of the channel layer 113 facing the barrier layer 112, forming a channel region 113c. The conductivity type of the channel layer 113 is, for example, n-type or undoped (i-type). The surface of the channel layer 113 constitutes the surface 110A of the nitride semiconductor layer 110. A spacer layer may also be formed between the barrier layer 112 and the channel layer 113. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, in the range of 0.5 nm to 3.0 nm, inclusive, and in one embodiment is 1.0 nm.

[0038] On the C-polar surface of the SiC substrate, the buffer layer 111, the barrier layer 112, and the channel layer 113 are grown as crystals with the N-polar surface as the growth surface. Therefore, the surfaces of the buffer layer 111, the barrier layer 112, and the channel layer 113 opposite to the substrate 101 side are N-polar surfaces, and the back surfaces facing the substrate 101 are gallium (Ga)-polar surfaces.

[0039] The insulating layer 121 is in contact with the surface 110A of the nitride semiconductor layer 110. The insulating layer 121 is, for example, a silicon nitride (SiN) layer. Openings 121S and 121D are formed in the insulating layer 121. A part of the nitride semiconductor layer 110 is exposed from the opening 121S, and another part of the nitride semiconductor layer 110 is exposed from the opening 121D.

[0040] An n-type GaN layer 131S is formed on the nitride semiconductor layer 110 within the opening 121S. An n-type GaN layer 131D is formed on the nitride semiconductor layer 110 within the opening 121D. The n-type GaN layers 131S and 131D contain Ge (germanium) or Si as an n-type impurity. The n-type GaN layers 131S and 131D are examples of second nitride semiconductor layers.

[0041] Here, the n-type GaN layers 131S and 131D will be described in detail. Fig. 2 is a cross-sectional view showing the n-type GaN layers 131S and 131D in the first embodiment. Fig. 3 is a diagram showing the relationship between the depth from the surface of the n-type GaN layers 131S and 131D and the impurity concentration in the first embodiment.

[0042] 2, the n-type GaN layers 131S and 131D, which are an example of the second nitride semiconductor layer, have a plurality of n-type GaN layers 150 and a plurality of n-type GaN layers 160. The n-type GaN layers 150 and 160 are alternately stacked on the nitride semiconductor layer 110. For example, the n-type GaN layers 150 and 160 are stacked on the nitride semiconductor layer 110 at a period of 8 nm or less. The n-type GaN layer 150 is doped with n-type impurities at a concentration of 1×10 ２０ cm －３ The n-type GaN layer 150 contains n-type impurities at a first concentration of, for example, 3×10 ２０ cm －３ The n-type GaN layer 160 contains the n-type impurity at a first concentration of, for example, 9×10 ２０ cm －３ In this example, the difference between the first concentration and the second concentration is 6×10 ２０ cm －３ 3, the impurity concentration varies periodically in the depth direction in the n-type GaN layers 131S and 131D. The n-type GaN layers 131S and 131D each have, for example, an n-type GaN layer 150 as the bottom layer and an n-type GaN layer 160 as the top layer. The n-type GaN layer 150 is an example of a third nitride semiconductor layer, and the n-type GaN layer 160 is an example of a fourth nitride semiconductor layer.

[0043] 1 , the source electrode 132S is formed on the n-type GaN layer 131S, and the drain electrode 132D is formed on the n-type GaN layer 131D. The source electrode 132S and the drain electrode 132D include, for example, a stack of a Ta (tantalum) film, an Al film, and a Ta film stacked in this order. The source electrode 132S and the drain electrode 132D may include, for example, a stack of a Ti (titanium) film, an Al film, and a Ti film stacked in this order, or a stack of a Ni (nickel) film and an Au (gold) film stacked in this order. The source electrode 132S and the drain electrode 132D are examples of ohmic electrodes.

[0044] A gate electrode 141 is formed on the insulating layer 121 between the source electrode 132S and the drain electrode 132D. The gate electrode 141 includes, for example, a stack of a Ni film, a Pd (palladium) film, and an Au film, which are stacked in this order. The insulating layer 142 is formed on the insulating layer 121 and covers the gate electrode 141.

[0045] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 4 to 9 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0046] First, as shown in Fig. 4, a nitride semiconductor layer 110 is formed on a substrate 101 by, for example, metal organic chemical vapor deposition (MOCVD). In forming the nitride semiconductor layer 110, a buffer layer 111, a barrier layer 112, and a channel layer 113 are formed in this order. Distortion occurs between the channel layer 113 and the barrier layer 112 due to the difference in their lattice constants, and this distortion induces piezoelectric charges at the interface between the two. As a result, a 2DEG is generated in the region of the channel layer 113 on the barrier layer 112 side, and a channel region 113c is formed.

[0047] 5, an insulating layer 121 is formed in contact with the surface 110A of the nitride semiconductor layer 110. The insulating layer 121 can be formed by, for example, a low-pressure CVD (LPCVD) method. The insulating layer 121 may also be formed by, for example, a MOCVD method continuously on the buffer layer 111, the barrier layer 112, and the channel layer 113 without exposing the surface of the channel layer 113 to the atmosphere.

[0048] 6, openings 121S and 121D are formed in the insulating layer 121. The openings 121S and 121D can be formed by reactive ion etching (RIE) using a resist pattern (not shown) as a mask, for example. In RIE, a fluorine-based gas is used as a reactive gas, for example.

[0049] Next, as shown in FIG. 7 , an n-type GaN layer 131S is formed on the nitride semiconductor layer 110 within the opening 121S, and an n-type GaN layer 131D is formed on the nitride semiconductor layer 110 within the opening 121D. The top surfaces of the n-type GaN layers 131S and 131D may or may not be flush with the top surface of the insulating layer 121. The n-type GaN layers 131S and 131D can be formed by a physical vapor deposition (PVD) method, such as evaporation, sputtering, or molecular beam epitaxy (MBE). When forming the n-type GaN layers 131S and 131D, for example, film formation is performed using a growth mask (not shown) having openings formed in the regions where the n-type GaN layers 131S and 131D will be formed, and then the growth mask is removed together with the n-type GaN layer (not shown) formed thereon. In other words, lift-off is performed. The method for forming the n-type GaN layers 131S and 131D will be described in detail later.

[0050] 8, a source electrode 132S is formed on the n-type GaN layer 131S, and a drain electrode 132D is formed on the n-type GaN layer 131D. To form the source electrode 132S and the drain electrode 132D, a metal layer (not shown) that constitutes the source electrode 132S and the drain electrode 132D is first formed. When forming the metal layer, for example, a growth mask (not shown) having an opening formed in the region where the metal layer is to be formed is used for film formation, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, lift-off is performed.

[0051] Next, as shown in FIG. 9 , a gate electrode 141 is formed on the insulating layer 121 between the source electrode 132S and the drain electrode 132D. When forming the gate electrode 141, for example, a metal layer is formed using a growth mask (not shown) having an opening formed in the area where the gate electrode 141 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, lift-off is performed. After forming the gate electrode 141, an insulating layer 142 is formed on the insulating layer 121 by, for example, plasma CVD, and the gate electrode 141 is covered with the insulating layer 142.

[0052] In this manner, the semiconductor device 100 can be manufactured.

[0053] Next, a method for forming the n-type GaN layers 131S and 131D will be described. Here, the n-type GaN layers 131S and 131D are formed by sputtering. Ge is used as the n-type impurity. FIG. 10 is a timing chart showing a method for forming the n-type GaN layers 131S and 131D. FIG. 10 shows whether or not Ga, Ge, and N radicals are supplied to the nitride semiconductor layer 110 during the formation of the n-type GaN layers 131S and 131D. "ON" in FIG. 10 indicates that there is supply, and "OFF" indicates that there is no supply. FIGS. 11 to 15 are cross-sectional views showing a method for forming the n-type GaN layers 131S and 131D.

[0054] After the substrate 101 on which the nitride semiconductor layer 110 and the like are formed is placed in a film formation chamber, the temperature and pressure in the film formation chamber are set to a predetermined temperature and a predetermined pressure, respectively. The predetermined temperature and pressure are selected so that the saturated vapor pressure of Ga at the predetermined temperature is lower than the predetermined pressure. For example, the predetermined temperature is 600°C, and the predetermined pressure is higher than the saturated vapor pressure of Ga at 600°C. Note that the saturated vapor pressure of Ge is lower than the saturated vapor pressure of Ga.

[0055] When the temperature and pressure in the chamber are stabilized at predetermined temperatures and pressures, respectively, the supply of N radicals 152 to the nitride semiconductor layer 110 is started at time t11, and the supply of N radicals 152 is stopped at time t12. The supply of N radicals 152 from time t11 to time t12 purifies the surface of the nitride semiconductor layer 110. For example, the N radicals 152 are generated by inductively coupled plasma (ICP).

[0056] At a subsequent time t1, the supply of Ga, Ge, and N radicals 152 to the nitride semiconductor layer 110 is started, and at a subsequent time t2, the supply of Ga and Ge is stopped while the supply of N radicals 152 is continued. By the supply of Ga, Ge, and N radicals 152 from time t1 to time t2, an n-type GaN layer 150 is formed as shown in FIG. 11 . Furthermore, along with the formation of the n-type GaN layer 150, droplets 151 of an alloy of Ga and Ge are formed on the surface of the n-type GaN layer 150. For example, Ga is supplied by RF (radio frequency) sputtering, and Ge is supplied by direct current (DC) pulse sputtering. The time from time t1 to time t2 is, for example, 10 seconds or more and 30 seconds or less, and preferably 20 seconds or more and 30 seconds or less.

[0057] For example, the number density of the droplets 151 is 6.1×10 ４ cm －２ The droplets 151 have an average diameter of about 300 nm and a height of about 57 nm.

[0058] At time t3 thereafter, similarly to time t1, the supply of N radicals 152 is continued while the supply of Ga and Ge is started.

[0059] During the period from time t2 to time t3, the supply of Ga is stopped, and therefore, as shown in FIG. 12 , a portion of Ga evaporates from droplet 151 as gaseous Ga 153. Meanwhile, although the supply of Ge is also stopped, the saturated vapor pressure of Ge is lower than that of Ga, and therefore, Ge remains in droplet 151. Furthermore, since the supply of N radicals 152 continues, Ga in droplet 151 is nitrided while incorporating Ge. As a result, an n-type GaN layer 160 is formed, as shown in FIG. 13 . During the formation of the n-type GaN layer 160, Ge remains in droplet 151, and a portion of Ga evaporates as gaseous Ga 153. Therefore, the ratio of Ge to the total amount of Ga and Ge in droplet 151 becomes higher than the ratio of Ge to the total amount of Ga and Ge in n-type GaN layer 150. Therefore, n-type GaN layer 160 formed from droplet 151 from which Ga has evaporated contains Ge at a higher concentration than n-type GaN layer 150. The time from time t2 to time t3 is, for example, not less than 15 seconds and not more than 120 seconds.

[0060] Furthermore, even if the proportion of Ge in droplets 151 increases with the evaporation of Ga, Ge does not aggregate to the extent that a critical nucleus is formed. Even if minute elemental Ge atoms are temporarily generated, the supply of Ge is stopped during the period from time t2 to time t3, so the elemental Ge atoms decompose before growing to a critical nucleus. Therefore, no Ge precipitates are formed during the formation of n-type GaN layer 160.

[0061] At time t2, the supply of Ga and Ge is stopped while the supply of N radicals continues. By supplying Ga, Ge, and N radicals from time t3 (t1) to time t2, an n-type GaN layer 150 is newly formed, and droplets 151 of an alloy of Ga and Ge are formed on the surface of the n-type GaN layer 150, as shown in FIG.

[0062] Thereafter, the process from time t1 to time t3 is repeated. As a result, n-type GaN layers 131S and 131D are formed in which n-type GaN layers 150 and 160 are alternately stacked, as shown in Fig. 15. Each of the n-type GaN layers 150 and 160 may be in direct contact with the nitride semiconductor layer 110, for example.

[0063] In the semiconductor device 100 according to the first embodiment, the n-type GaN layer 150 contains n-type impurities such as Ge at a concentration of 1×10 ２０ cm －３ The n-type GaN layer 131S and 131D contain an n-type impurity such as Ge at a first concentration higher than the first concentration, and the n-type GaN layer 160 contains an n-type impurity such as Ge at a second concentration higher than the first concentration. Therefore, the electrical resistance of the n-type GaN layers 131S and 131D can be sufficiently reduced. The thickness of the n-type GaN layers 131S and 131D is preferably 20 nm or more and 100 nm or less, more preferably 30 nm or more and 100 nm or less, and even more preferably 40 nm or more and 100 nm or less.

[0064] Furthermore, because the n-type GaN layers 150 and 160, each containing a different concentration of n-type impurities, are alternately stacked, good crystallinity can be achieved despite the high concentration of n-type impurities. Furthermore, the n-type GaN layers 150 and 160 can be formed by PVD at a low temperature, which does not damage the nitride semiconductor layer 110 formed prior to their formation. Furthermore, droplets 151 are formed during the formation of the n-type GaN layer 150, and these droplets 151 are used to form the n-type GaN layer 160. Therefore, Ge precipitates are unlikely to remain on the outermost surfaces of the n-type GaN layers 131S and 131D. When a GaN layer containing a high concentration of Ge is formed by pulse sputtering, Ge precipitates are likely to remain on the surface of the GaN layer. However, according to this embodiment, the remaining Ge precipitates can be suppressed, thereby suppressing degradation of electrical properties due to these precipitates. Lowering the temperature at which the n-type GaN layers 150 and 160 are formed also has the effect of improving throughput and reducing greenhouse gas emissions.

[0065] In the first embodiment, the surface of the nitride semiconductor layer 110 that contacts the lower surfaces of the n-type GaN layers 131S and 131D is an N-polar surface, and the channel layer 113 is located above the barrier layer 112. This makes it easy to shorten the distance between the channel region 113c and the source electrode 132S and the drain electrode 132D, and to achieve low resistance. Furthermore, the n-type GaN layers 131S and 131D are formed in the openings 121S and 121D, respectively, formed in the insulating layer 121, so that the insulating layer 121 can protect the nitride semiconductor layer 110 while also making it easy to achieve low resistance.

[0066] The period of the n-type GaN layers 150 and 160 in the thickness direction is preferably 8 nm or less, more preferably 6 nm or less, and even more preferably 4 nm or less. The smaller the period of the n-type GaN layers 150 and 160, the easier it is to obtain good crystallinity in the n-type GaN layers 131S and 131D. For example, if the n-type GaN layer 150 is too thick, large droplets 151 are formed during the formation of the n-type GaN layer 150. The n-type GaN layer 160 is formed through the migration of Ga atoms in the droplets 151 on the surface of the n-type GaN layer 150. However, if large droplets 151 are formed, Ga nitridation may occur at a stage when Ga atom migration is insufficient. In this case, it may be difficult to obtain a good n-type GaN layer 160.

[0067] The difference between the first concentration and the second concentration is preferably 1×10 ２０ cm －３ 7 x 10 or more ２０ cm －３ More preferably, it is 2×10 or less. ２０ cm －３ 6 x 10 or more ２０ cm －３ or less, and more preferably 3×10 ２０ cm －３ 5x10 or more ２０ cm －３ If this concentration difference is too small or too large, it may be difficult to obtain good crystallinity in the n-type GaN layers 131S and 131D.

[0068] The n-type impurity is not particularly limited, but if it is Ge or Si, it is easy to obtain low electrical resistance in the n-type GaN layers 150 and 160 .

[0069] The concentrations of impurities such as Ge and Si contained in the n-type GaN layers 131S and 131D can be measured by secondary ion mass spectrometry (SIMS). While the impurity concentrations vary in a rectangular wave pattern in Fig. 3, the measurement results of the impurity concentrations may vary in a sinusoidal wave pattern as shown in Fig. 16. In this case, the ranges of the n-type GaN layers 150 and 160 can be identified by approximating the impurity concentration profile to a rectangular wave.

[0070] When forming the n-type GaN layer 160, it is preferable to remove the droplets 151 formed on the surface of the n-type GaN layer 150 by evaporation, nitridation, or the like. This is because if the droplets 151 remain, the crystallinity of the n-type GaN layer 160 may be reduced. Some of the Ga in the droplets 151 may be incorporated into the n-type GaN layer 150.

[0071] The time from time t2 to time t3 is preferably longer than the time from time t1 to time t2. In other words, the time for subsequently continuing the supply of N radicals 152 to form n-type GaN layer 160 is preferably longer than the time for forming n-type GaN layer 150. This is because droplets 151 are more likely to disappear.

[0072] The temperature of substrate 101 when forming n-type GaN layers 150 and 160 is preferably 200° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and even more preferably 300° C. or higher and 550° C. or lower. If the temperature of substrate 101 is too low, n-type GaN layers 150 and 160 are difficult to form, whereas if the temperature is too high, there is a risk of damage to nitride semiconductor layer 110 and the like that has already been formed.

[0073] If the time from time t1 to time t2, i.e., the continuous supply time of Ga, is too long, large droplets 151 are formed. FIG. 17 is a diagram showing the relationship between the continuous supply time of Ga and the droplet size L1. FIG. 17 also shows the relationship between the continuous supply time of Ga and the difference (L2 - L1) between the migration length L2 and the droplet size L1. The horizontal axis of FIG. 17 represents the continuous supply time of Ga, the vertical axis on the left represents L1, and the vertical axis on the right represents L2 - L1. Furthermore, FIGS. 18 and 19 are cross-sectional views showing the phenomenon that occurs when the continuous supply time of Ga is too long.

[0074] As described above, the n-type GaN layer 160 is formed through the migration of Ga atoms in the droplet 151. Although it depends on conditions such as temperature and pressure during the period from time t2 to time t1, the migration length L2 is generally 1 μm or more and 3 μm or less. Here, the migration length L2 refers to the distance that the Ga atoms travel from when they start to migrate until they are deactivated. Furthermore, the droplet size L1 refers to the length of the shortest path from the top of the droplet to the surface of the n-type GaN layer when the droplet shape is approximated to an ellipsoid.

[0075] If the continuous supply time of Ga is too long, as shown in FIG. 18 , a thick n-type GaN layer 150X is formed instead of the n-type GaN layer 150, and large droplets 151X of a Ga and Ge alloy are formed on the surface of the n-type GaN layer 150X. In this case, the droplet size L1 may be larger than the migration length L2 (L2-L1<0). If the droplet size L1 is larger than the migration length L2, nitridation occurs before the Ga atoms in the droplets 151X spread to the surface of the n-type GaN layer 150X. As shown in FIG. 19 , the surface of the droplets 151X is covered with the n-type GaN layer 160X before the droplets 151X disappear. If the surface of the droplets 151X is covered with the n-type GaN layer 160X, it becomes difficult to obtain good flatness. For example, if the time from time t1 to time t2 is about 600 seconds, the size L1 of the droplet will be about 3.5 μm, and the surface of the droplet 151X may be covered with the n-type GaN layer 160X.

[0076] On the other hand, if the time from time t1 to time t2 is between 10 seconds and 30 seconds, the droplet size L1 is approximately 0.15 μm, which is smaller than the migration length L2 (L2-L1>0), and a good n-type GaN layer 160 can be formed.

[0077] Second Embodiment Next, a second embodiment will be described. The second embodiment relates to a semiconductor device including a GaN-based HEMT. Fig. 20 is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0078] As shown in FIG. 20 , the semiconductor device 200 according to the second embodiment mainly includes a substrate 201, a nitride semiconductor layer 210, an insulating layer 121, an n-type GaN layer 231S, an n-type GaN layer 231D, a gate electrode 141, a source electrode 132S, a drain electrode 132D, and an insulating layer 142.

[0079] The substrate 201 is, for example, a substrate for growing a GaN-based semiconductor, and one example is a semi-insulating SiC substrate. When the substrate 201 is a SiC substrate, the surface of the substrate 201 is a silicon (Si) polar surface. When the surface of the substrate 201 is a Si polar surface, the nitride semiconductor layer 210 can grow as a crystal with the Ga polar surface as the growth surface.

[0080] The nitride semiconductor layer 210 includes a channel layer 211, a barrier layer 212, and a cap layer 213. The nitride semiconductor layer 210 is an example of a first nitride semiconductor layer.

[0081] The channel layer 211 is, for example, a GaN layer. The thickness of the channel layer 211 is, for example, in the range of 200 nm to 2000 nm, and in one embodiment, is 1000 nm. A buffer layer may be present between the channel layer 211 and the substrate 201.

[0082] The barrier layer 212 is, for example, an AlGaN layer. The band gap of the barrier layer 212 is larger than the band gap of the channel layer 211. The thickness of the barrier layer 212 is, for example, in the range of 5 nm to 30 nm, and in one embodiment, is 15 nm. ｘ Ga １－ｘIn the case of an N layer, the Al composition x is, for example, 0.15 to 0.35, inclusive, and in one embodiment, 0.25. Strain occurs between the channel layer 211 and the barrier layer 212 due to the difference in their lattice constants, and this strain induces piezoelectric charges at the interface between them. This generates a 2DEG in the region of the channel layer 211 on the barrier layer 212 side, forming a channel region 211c. An InAlN layer or an InAlGaN layer may be used instead of the AlGaN layer. A spacer layer may also be provided between the channel layer 211 and the barrier layer 212. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, 0.5 nm to 3.0 nm, inclusive, and in one embodiment, is 1.0 nm.

[0083] The cap layer 213 is, for example, a GaN layer. The thickness of the cap layer 213 is, for example, in the range of 0 nm to 5 nm, and in one embodiment, is 2 nm. The surface of the cap layer 213 constitutes a surface 210A of the nitride semiconductor layer 210.

[0084] On the Si-polar surface of the SiC substrate, the channel layer 211, the barrier layer 212, and the cap layer 213 undergo crystal growth with the Ga-polar surface as the growth surface. Therefore, the surfaces of the channel layer 211, the barrier layer 212, and the cap layer 213 opposite to the substrate 201 side are Ga-polar surfaces, and the back surfaces facing the substrate 201 are N-polar surfaces.

[0085] Recesses 210S and 210D are formed in the nitride semiconductor layer 210. The recesses 210S and 210D are formed to a depth that penetrates the channel region 211c. In other words, the depth of the recesses 210S and 210D is greater than the depth of the channel region 211c, based on the surface 210A of the nitride semiconductor layer 210. The bottom surfaces of the recesses 210S and 210D may be located within the barrier layer 212.

[0086] The insulating layer 121 is in contact with the surface 210A of the nitride semiconductor layer 210. Openings 121S and 121D are formed in the insulating layer 121. The opening 121S is connected to the recess 210S, and the opening 121D is connected to the recess 210D.

[0087] An n-type GaN layer 231S is formed on the nitride semiconductor layer 210 within the recess 210S and the opening 121S. An n-type GaN layer 231D is formed on the nitride semiconductor layer 210 within the recess 210D and the opening 121D. The n-type GaN layers 231S and 231D contain Ge or Si as an n-type impurity. The n-type GaN layers 231S and 231D are examples of second nitride semiconductor layers.

[0088] Here, the n-type GaN layers 231S and 231D will be described in detail. Fig. 21 is a cross-sectional view showing the n-type GaN layers 231S and 231D in the second embodiment.

[0089] 21 , n-type GaN layers 231S and 231D, which are an example of the second nitride semiconductor layer, have a plurality of n-type GaN layers 250 and a plurality of n-type GaN layers 260. The n-type GaN layers 250 and 260 are alternately stacked on the nitride semiconductor layer 210. For example, the n-type GaN layers 250 and 260 are stacked on the nitride semiconductor layer 210 at a period of 8 nm or less. The n-type GaN layer 250 is doped with n-type impurities at a concentration of 1×10 ２０ cm －３ The n-type GaN layer 250 contains n-type impurities at a first concentration of, for example, 3×10 ２０ cm －３ The n-type GaN layer 260 contains n-type impurities at a first concentration of, for example, 9×10 ２０ cm －３ In this example, the difference between the first concentration and the second concentration is 6×10 ２０ cm －３ Therefore, in n-type GaN layers 231S and 231D, the impurity concentration changes periodically in the depth direction. N-type GaN layer 250 is an example of a third nitride semiconductor layer, and n-type GaN layer 260 is an example of a fourth nitride semiconductor layer.

[0090] As shown in FIG. 20, the source electrode 132S is formed on the n-type GaN layer 231S, and the drain electrode 132D is formed on the n-type GaN layer 231D.

[0091] An opening 121G is formed in the insulating layer 121 between the source electrode 132S and the drain electrode 132D. A part of the nitride semiconductor layer 210 is exposed from the opening 121G. The gate electrode 141 is formed on the insulating layer 121 so as to be in contact with the nitride semiconductor layer 210 through the opening 121G.

[0092] The other configurations are the same as those of the first embodiment.

[0093] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 22 to 27 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.

[0094] 22, a nitride semiconductor layer 210 is formed on a substrate 201 by, for example, MOCVD. In forming the nitride semiconductor layer 210, a channel layer 211, a barrier layer 212, and a cap layer 213 are formed in this order. Distortion occurs between the channel layer 211 and the barrier layer 212 due to the difference in their lattice constants, and this distortion induces piezoelectric charges at the interface between them. As a result, 2DEG is generated in the region of the channel layer 211 on the barrier layer 212 side, and a channel region 211c is formed.

[0095] 23 , an insulating layer 121 is formed in contact with the surface 210A of the nitride semiconductor layer 210. The insulating layer 121 can be formed by, for example, a low-pressure CVD method. The insulating layer 121 may also be formed by, for example, an MOCVD method, continuously on the channel layer 211, the barrier layer 212, and the cap layer 213, without exposing the surface of the cap layer 213 to the atmosphere.

[0096] 24 , openings 121S and 121D are formed in the insulating layer 121, and recesses 210S and 210D are formed in the nitride semiconductor layer 210. The openings 121S and 121D and the recesses 210S and 210D can be formed by RIE using, for example, a resist pattern (not shown) as a mask. For example, a fluorine-based gas is used as a reactive gas in the RIE of the insulating layer 121, and a chlorine-based gas is used as a reactive gas in the RIE of the nitride semiconductor layer 210.

[0097] 25 , an n-type GaN layer 231S is formed on the nitride semiconductor layer 210 within the opening 121S and the recess 210S, and an n-type GaN layer 231D is formed on the nitride semiconductor layer 210 within the opening 121D and the recess 210D. The top surfaces of the n-type GaN layers 231S and 231D may or may not be flush with the top surface of the insulating layer 121. The n-type GaN layers 231S and 231D can be formed in the same manner as the n-type GaN layers 131S and 131D. Each of the n-type GaN layers 250 and 260 may be in direct contact with the nitride semiconductor layer 110, for example.

[0098] Although droplets of an alloy of Ga and Ge are also formed when the n-type GaN layers 231S and 231D are formed, the density and size of the droplets are different in this embodiment from those in the first embodiment because the growth surface is different. For example, the number density of the droplets is 1.0×10 ７ cm －２ The average diameter of the droplets is about 60 nm to 100 nm, and the height of the droplets is about 20 nm.

[0099] 26, a source electrode 132S is formed on the n-type GaN layer 131S, and a drain electrode 132D is formed on the n-type GaN layer 131D. The source electrode 132S and the drain electrode 132D can be formed by the same method as in the first embodiment.

[0100] 27 , an opening 121G is formed in the insulating layer 121 between the source electrode 132S and the drain electrode 132D. A portion of the nitride semiconductor layer 210 is exposed from the opening 121G. Next, a gate electrode 141 is formed in contact with the nitride semiconductor layer 210 through the opening 121G. The gate electrode 141 can be formed by a method similar to that of the first embodiment.

[0101] In this manner, the semiconductor device 200 can be manufactured.

[0102] In the semiconductor device 200 according to the second embodiment, the n-type GaN layer 250 contains n-type impurities such as Ge at a concentration of 1×10 ２０ cm －３The n-type GaN layer 260 contains an n-type impurity such as Ge at a second concentration higher than the first concentration, thereby sufficiently reducing the electrical resistance of the n-type GaN layers 231S and 231D.

[0103] Furthermore, because the n-type GaN layers 250 and 260 having different concentrations of n-type impurities are alternately stacked, good crystallinity can be obtained despite the high concentration of n-type impurities. Furthermore, the n-type GaN layers 250 and 260 can be formed by PVD at a temperature that does not cause damage to the nitride semiconductor layer 210 formed before the n-type GaN layers 250 and 260. In other words, the n-type GaN layers 250 and 260 having good crystallinity can be formed using existing film formation equipment. Lowering the formation temperature of the n-type GaN layers 250 and 260 also has the effects of improving throughput and reducing greenhouse gas emissions.

[0104] In the second embodiment, the surface of the nitride semiconductor layer 210 that contacts the lower surfaces of the n-type GaN layers 231S and 231D is a Ga-polar surface, and the barrier layer 212 is located above the channel layer 211. This makes it easy to grow the nitride semiconductor layer 210 and also makes it easy to obtain good etching resistance on the upper surface of the nitride semiconductor layer 210. Furthermore, since the n-type GaN layers 231S and 231D are formed in the recesses 210S and 210D formed in the nitride semiconductor layer 210, respectively, it is easy to shorten the distance between the channel region 211c and the n-type GaN layers 231S and 231D, and it is easy to achieve low resistance.

[0105] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0106] 100, 200: semiconductor device 101, 201: substrate 110, 210: nitride semiconductor layer 110A, 210A: surface 111: buffer layer 112, 212: barrier layer 113, 211: channel layer 113c, 211c: channel region 121, 142: insulating layer 121D, 121G, 121S: opening 131D, 131S, 150, 150X, 160, 160X, 231D, 231S, 250, 260: n-type GaN layer 132D: drain electrode 132S: source electrode 141: gate electrode 151, 151X: droplet 152: N radical 153: gaseous Ga 210D, 210S: recess 213: cap layer

Claims

1. a first nitride semiconductor layer containing gallium; a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing gallium; having the second nitride semiconductor layer includes a plurality of third nitride semiconductor layers and a plurality of fourth nitride semiconductor layers alternately stacked on the first nitride semiconductor layer, the third nitride semiconductor layer contains a first conductivity type impurity at a first concentration; the fourth nitride semiconductor layer contains the first conductivity type impurity at a second concentration higher than the first concentration; The first concentration is 1×10 ２０ cm －３ The semiconductor device is as described above.

2. The semiconductor device according to claim 1 , wherein the third nitride semiconductor layer and the fourth nitride semiconductor layer are laminated at a period of 8 nm or less.

3. The difference between the first concentration and the second concentration is 1×10 ２０ cm －３ Above 7 x 10 ２０ cm －３ 3. The semiconductor device according to claim 1, wherein:

4. 3. The semiconductor device according to claim 1, wherein the impurity is germanium or silicon.

5. 3. The semiconductor device according to claim 1, further comprising an ohmic electrode formed on the second nitride semiconductor layer.

6. 3. The semiconductor device according to claim 1, wherein a surface of said first nitride semiconductor layer in contact with a lower surface of said second nitride semiconductor layer is a nitrogen polarity surface.

7. The first nitride semiconductor layer is A barrier layer; a channel layer provided above the barrier layer; The semiconductor device according to claim 6 , comprising:

8. an insulating layer formed on the first nitride semiconductor layer; an opening exposing the first nitride semiconductor layer is formed in the insulating layer; The semiconductor device according to claim 6 , wherein the second nitride semiconductor layer is formed in the opening.

9. 3. The semiconductor device according to claim 1, wherein a surface of said first nitride semiconductor layer in contact with a lower surface of said second nitride semiconductor layer is a surface of gallium polarity.

10. The first nitride semiconductor layer is A channel layer; a barrier layer provided above the channel layer; The semiconductor device according to claim 9 ,

11. a recess is formed in the first nitride semiconductor layer, The semiconductor device according to claim 9 , wherein the second nitride semiconductor layer is formed in the recess.

12. forming a second nitride semiconductor layer containing gallium on a first nitride semiconductor layer containing gallium by physical vapor deposition; The step of forming the second nitride semiconductor layer includes: forming a third nitride semiconductor layer containing a first conductivity type impurity at a first concentration and forming droplets of an alloy of gallium and the impurity on a surface of the third nitride semiconductor layer; forming a fourth nitride semiconductor layer containing the first conductivity type impurity at a second concentration higher than the first concentration by evaporating a portion of the gallium from the droplet and nitriding another portion of the gallium in the droplet while incorporating the impurity in the droplet; The method for manufacturing a semiconductor device includes repeating the steps of:

13. The method for manufacturing a semiconductor device according to claim 12 , wherein the droplets are made to disappear in the step of forming the fourth nitride semiconductor layer.

14. 14. The method for manufacturing a semiconductor device according to claim 12, wherein a time for the step of forming the fourth nitride semiconductor layer is longer than a time for the step of forming the third nitride semiconductor layer.

15. the third nitride semiconductor layer and the fourth nitride semiconductor layer are formed in a chamber; 14. The method for manufacturing a semiconductor device according to claim 12, wherein in the step of forming the third nitride semiconductor layer and the step of forming the fourth nitride semiconductor layer, a saturated vapor pressure of gallium at a temperature in the chamber is lower than a pressure in the chamber.

16. The first nitride semiconductor layer is formed on a substrate; 14. The method for manufacturing a semiconductor device according to claim 12, wherein a temperature of the substrate when the third nitride semiconductor layer and the fourth nitride semiconductor layer are formed is 200° C. or higher and 650° C. or lower.