Semiconductor device, semiconductor module, and semiconductor module mounting structure

Abstract

This semiconductor module comprises a plurality of semiconductor devices and a coupling part. The plurality of semiconductor devices each comprise: a semiconductor element; a sealing part that covers the semiconductor element; and a signal terminal that projects from the sealing part in the thickness direction of the sealing part and that is electrically connected to the semiconductor element. The coupling part couples the plurality of semiconductor devices with each other. The plurality of semiconductor devices include a first device and a second device adjacent with each other in a first direction orthogonal to the thickness direction. The coupling part includes a first connection section that is located between the first device and the second device in the first direction and that couples the first device and the second device with each other.

Description

Semiconductor device, semiconductor module, and mounting structure for semiconductor module

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and a mounting structure for the semiconductor module.

[0002] Conventionally, semiconductor devices including semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. For example, an inverter for driving a three-phase AC motor uses multiple semiconductor devices. Patent Document 1 (Patent Document 1) discloses an example of a semiconductor module including multiple semiconductor devices. The semiconductor module (intelligent power module) described in Patent Document 1 includes multiple semiconductor devices (power semiconductor modules). The semiconductor module described in Patent Document 1 also includes a cooler and a drive circuit unit. Each of the multiple semiconductor devices is bonded to the cooler. Each of the multiple semiconductor devices includes a seal and multiple lead terminals. In each semiconductor device, the seal seals the semiconductor element (semiconductor device). In each semiconductor device, the multiple lead terminals are bent upward and extend above the seal. The drive circuit unit includes a drive circuit board on which drive circuits for driving each semiconductor device are mounted, and is provided in common to the multiple semiconductor devices. The drive circuit unit is disposed above the multiple semiconductor devices. Multiple through holes are formed in the drive circuit unit. A plurality of lead terminals are individually inserted into the plurality of through holes. The semiconductor device (power module) disclosed in Patent Document 2 includes a semiconductor element (semiconductor chip), lead terminals, and a sealing body (package). The semiconductor device has the outer periphery of the semiconductor element, excluding the lead terminals, molded with the sealing body. The semiconductor device is also bonded (fixed) to a heat sink serving as a support member.

[0003] JP 2017-103380 A JP 2017-50374 A

[0004] In the semiconductor module described in Patent Document 1, if there is variation in the relative positional relationship between the multiple semiconductor devices, the positions of the multiple lead terminals will vary among the multiple semiconductor devices. Furthermore, if there is variation in the positions of the multiple lead terminals, the positional relationship between the multiple lead terminals and the multiple through holes provided in the drive circuit unit will not match, making it difficult to connect the drive circuit unit to the multiple semiconductor devices. Furthermore, the semiconductor device described in Patent Document 2 still has room for improvement in terms of fixing it to a support member.

[0005] In view of the above circumstances, an object of the present disclosure is to provide an improved semiconductor device, semiconductor module, and mounting structure for the semiconductor module. In particular, an object of the present disclosure is to provide a semiconductor module that can suppress variations in the relative positional relationship between multiple semiconductor devices. Another object of the present disclosure is to provide a semiconductor device (and semiconductor module) that can be easily fixed to a support member.

[0006] A semiconductor module provided by a first aspect of the present disclosure comprises a semiconductor element, a sealing portion covering the semiconductor element, a plurality of semiconductor devices each including a signal terminal protruding from the sealing portion in a thickness direction of the sealing portion and conducting to the semiconductor element, and a connecting portion connecting the plurality of semiconductor devices, wherein the plurality of semiconductor devices include a first device and a second device adjacent to each other in a first direction perpendicular to the thickness direction, and the connecting portion includes a first connection portion located between the first device and the second device in the first direction and connecting the first device and the second device.

[0007] A mounting structure for a semiconductor module provided by a second aspect of the present disclosure includes the semiconductor module provided by the first aspect, and a heat sink to which the semiconductor module is mounted and which contacts each of the plurality of semiconductor devices.

[0008] A semiconductor device provided by a third aspect of the present disclosure comprises a semiconductor element, a sealing resin covering the semiconductor element, a terminal conductive to the semiconductor element, and a plate non-conductive to the semiconductor element, wherein the sealing resin has a top surface and a bottom surface facing opposite each other in the thickness direction of the sealing resin, and a plurality of resin side surfaces each connected to the top surface, the terminal protruding from the sealing resin, and the plate protruding from one of the plurality of resin side surfaces.

[0009] A semiconductor module provided by a fourth aspect of the present disclosure includes the semiconductor device provided by the third aspect and a heat sink in contact with the bottom surface, and the plate is fixed to the heat sink.

[0010] According to the above configuration, it is possible to suppress variations in the relative positional relationship between multiple semiconductor devices in a semiconductor module. Furthermore, it is possible to improve the accuracy of positioning multiple semiconductor devices relative to a heat sink in a mounting structure for a semiconductor module. Furthermore, it is possible to easily fix the semiconductor devices to a support member. Furthermore, it is possible to properly fix the semiconductor devices to a heat sink as a support member in a semiconductor module.

[0011] FIG. 1 is a perspective view showing a semiconductor module according to the first embodiment. FIG. 2 is a plan view showing the semiconductor module according to the first embodiment. FIG. 3 is a view showing the sealing portion in the plan view of FIG. 2 by using imaginary lines. FIG. 4 is a plan view of a main portion of FIG. 3. FIG. 5 is a bottom view showing the semiconductor module according to the first embodiment. FIG. 6 is a front view showing the semiconductor module according to the first embodiment. FIG. 7 is a rear view showing the semiconductor module according to the first embodiment. FIG. 8 is a left side view showing the semiconductor module according to the first embodiment. FIG. 9 is a right side view showing the semiconductor module according to the first embodiment. FIG. 10 is a perspective view showing a semiconductor device (second device) of the semiconductor module according to the first embodiment. FIG. 11 is a plan view showing the semiconductor device (second device) of the semiconductor module according to the first embodiment. FIG. 12 is a view showing the sealing portion in imaginary lines in the plan view of FIG. 11. FIG. 13 is a view showing the sealing portion and second conductive member in the plan view of FIG. 12 by omitting the sealing portion. FIG. 14 is a view showing the plan view of FIG. 13 by omitting the first conductive member. FIG. 15 is a bottom view showing a semiconductor device (second device) of the semiconductor module according to the first embodiment. FIG. 16 is a cross-sectional view taken along line XIV-XIV in FIG. 12. FIG. 17 is a partially enlarged cross-sectional view showing a portion (near the first element) of FIG. 16. FIG. 18 is a partially enlarged cross-sectional view showing a portion (near the second element) of FIG. 16. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 12. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 12. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 12. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 12. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 12. FIG. 24 is a plan view showing a mounting structure for a semiconductor module according to the first embodiment. FIG. 25 is a view in which the wiring board is omitted from the plan view of FIG. 24. Fig. 26 is a front view showing the mounting structure for the semiconductor module according to the first embodiment. Fig. 27 is a left side view showing the mounting structure for the semiconductor module according to the first embodiment. Fig. 28 is a partially enlarged cross-sectional view of the mounting structure for the semiconductor module according to the first embodiment. Fig. 29 is a plan view showing a semiconductor module and a mounting structure for the semiconductor module according to a first modification of the first embodiment.FIG. 30 is a left side view showing a semiconductor module according to a first modified example of the first embodiment and a mounting structure for the semiconductor module. FIG. 31 is a cross-sectional view showing a semiconductor module according to a second modified example of the first embodiment, corresponding to the cross section of FIG. 23 . FIG. 32 is a plan view showing a semiconductor module according to the second embodiment. FIG. 33 is a plan view of a main portion of the semiconductor module according to the second embodiment. FIG. 34 is a cross-sectional view of a main portion of the semiconductor module according to the second embodiment. FIG. 35 is a plan view of a main portion of a semiconductor module according to a modified example of the second embodiment. FIG. 36 is a cross-sectional view of a main portion of a semiconductor module according to a modified example of the second embodiment, corresponding to the cross section of FIG. 21 . FIG. 37 is a cross-sectional view of a main portion of a semiconductor module according to a modified example of the second embodiment, corresponding to the cross section of FIG. 22 . FIG. 38 is a plan view showing a semiconductor module according to the third embodiment. FIG. 39 is a plan view showing a semiconductor module according to the fourth embodiment. FIG. 40 is a plan view showing a semiconductor module according to a first modified example of the fourth embodiment. FIG. 41 is a plan view showing a semiconductor module according to a second modified example of the fourth embodiment. FIG. 42 is a plan view showing a configuration example when the configuration of the second strip portion of the fourth embodiment is applied to the semiconductor module of the second embodiment. FIG. 43 is a perspective view showing a semiconductor device of the fifth embodiment. FIG. 44 is a plan view showing a semiconductor device of the fifth embodiment. FIG. 45 is a diagram showing the sealing resin in imaginary lines in the plan view of FIG. 44. FIG. 46 is a partial enlarged view of a part of FIG. 45. FIG. 47 is a diagram showing the first conductive member in imaginary lines in the plan view of FIG. 45, with the second conductive member, sealing resin, and plate omitted. FIG. 48 is a right side view showing a semiconductor device of the fifth embodiment. FIG. 49 is a bottom view showing a semiconductor device of the fifth embodiment. FIG. 50 is a cross-sectional view taken along line L-L in FIG. 45. FIG. 51 is a cross-sectional view taken along line LI-LI in FIG. 45. FIG. 52 is a partial enlarged view of the first element and its periphery shown in FIG. 51. FIG. 53 is a partial enlarged view of the second element and its periphery shown in FIG. 51. Fig. 54 is a cross-sectional view taken along line LIV-LIV in Fig. 45. Fig. 55 is a cross-sectional view taken along line LV-LV in Fig. 45.FIG. 56 is a plan view of a semiconductor module according to the present disclosure, showing a state in which a semiconductor device according to the fifth embodiment is attached to a heat sink. FIG. 57 is a front view of the semiconductor module shown in FIG. 56. FIG. 58 is a partially enlarged cross-sectional view of a wiring substrate of the semiconductor module shown in FIG. 56. FIG. 59 is a plan view of a semiconductor device according to a first modified example of the fifth embodiment, showing the sealing resin in imaginary lines. FIG. 60 is a cross-sectional view of a semiconductor device according to a second modified example of the fifth embodiment, corresponding to the cross section of FIG. 54. FIG. 61 is a cross-sectional view of a semiconductor device according to a third modified example of the fifth embodiment, corresponding to the cross section of FIG. 54. FIG. 62 is a plan view of a semiconductor device according to a fourth modified example of the fifth embodiment, showing the sealing resin in imaginary lines. FIG. 63 is a cross-sectional view of a semiconductor device according to a fifth modified example of the fifth embodiment, corresponding to the cross section of FIG. 54. FIG. 64 is a plan view of a semiconductor device according to the sixth embodiment, showing the sealing resin in imaginary lines. FIG. 65 is a cross-sectional view of a semiconductor device according to the sixth embodiment, corresponding to the cross section of FIG. 54. Fig. 66 is a cross-sectional view showing a semiconductor device according to a sixth embodiment, corresponding to the cross section of Fig. 55. Fig. 67 is a cross-sectional view showing a semiconductor device according to a seventh embodiment, corresponding to the cross section of Fig. 54. Fig. 68 is a cross-sectional view showing a semiconductor device according to the seventh embodiment, corresponding to the cross section of Fig. 55.

[0012] Preferred embodiments of the semiconductor module and mounting structure for the semiconductor module according to the present disclosure will be described below with reference to FIGS. 1 to 42. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign a rank to their respective objects. Preferred embodiments of semiconductor devices and semiconductor modules according to other aspects of the present disclosure will be described below with reference to FIGS. 43 to 68. Note that the reference numerals used in FIGS. 1 to 42 (first to fourth embodiments) and those used in FIGS. 43 to 68 (fifth to seventh embodiments) are independent of each other. For example, the same reference numerals may be used for different members (elements, etc.), and different reference numerals may be used for the same (or similar) members (elements, etc.).

[0013] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, "an object A (is made of) a certain material C" includes "an object A (is made of) a certain material C" and "an object A (is made of) a certain material C as its main component."

[0014] 1 to 9 show a semiconductor module A1 according to a first embodiment. The semiconductor module A1 is used, for example, in an inverter for driving a three-phase AC motor. As shown in FIGS. 1 to 9, the semiconductor module A1 includes a plurality of semiconductor devices B1, a connecting portion 71, and an extending portion 72. In the illustrated example, the semiconductor module A1 includes three semiconductor devices B1, but the number of semiconductor devices B1 is not limited to three. For example, if the semiconductor module A1 forms a full-bridge circuit, it includes two semiconductor devices B1.

[0015] In the following description, the mutually orthogonal thickness direction z, first direction x, and second direction y will be referred to. The thickness direction z corresponds to the thickness direction of the semiconductor module A1. Furthermore, "plan view" refers to the view in the thickness direction z. The first direction x is orthogonal to the thickness direction z. The second direction y is orthogonal to the thickness direction z and the first direction x. One side of the first direction x will be referred to as the x1 side of the first direction x, and the other side of the first direction x will be referred to as the x2 side of the first direction x. Furthermore, one side of the second direction y will be referred to as the y1 side of the second direction y, and the other side of the second direction y will be referred to as the y2 side of the second direction y. Furthermore, one side of the thickness direction z will be referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z will be referred to as the z2 side of the thickness direction z. Furthermore, the z1 side of the thickness direction z will be referred to as the upper side, and the z2 side of the thickness direction z will be referred to as the lower side. Note that terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each part in the thickness direction z, and are not necessarily terms that define the relationship with the direction of gravity.

[0016] As shown in FIGS. 1 to 5 , 8 , and 9 , the multiple semiconductor devices B1 are arranged at intervals along the first direction x. This interval may be the same or different for each pair of adjacent semiconductor devices B1 in the first direction x. As shown in FIGS. 1 to 9 , each of the multiple semiconductor devices B1 includes multiple power terminals 13, multiple signal terminals 17, multiple semiconductor elements 21, and a sealing portion 50. As shown in FIGS. 1 to 9 , in each of the multiple semiconductor devices B1, the multiple semiconductor elements 21 are covered by the sealing portion 50. The multiple power terminals 13 protrude in the second direction y from the side surfaces of the sealing portion 50. The multiple signal terminals 17 protrude in the thickness direction z from the upper surface (top surface 51 described below) of the sealing portion 50. Note that a detailed configuration example of each semiconductor device B1 will be described later.

[0017] In the illustrated example, the multiple semiconductor devices B1 include a first device B11, a second device B12, and a third device B13. The first device B11 and the second device B12 are adjacent to each other in the first direction x. The second device B12 is arranged on the x2 side of the first direction x relative to the first device B11. The second device B12 and the third device B13 are adjacent to each other in the first direction x. The third device B13 is arranged on the x2 side of the first direction x relative to the second device B12. Therefore, the third device B13 is arranged on the opposite side of the first device B11 in the first direction x, with the second device B12 in between.

[0018] The multiple semiconductor devices B1 include a first external device B21 and a second external device B22. The first external device B21 is located outermost on the x1 side of the first direction x among the multiple semiconductor devices B1. In the illustrated example, the first external device B21 corresponds to the first device B11. The second external device B22 is located outermost on the x2 side of the first direction x among the multiple semiconductor devices B1. In the illustrated example, the second external device B22 corresponds to the third device B13.

[0019] The coupling portion 71 couples two adjacent semiconductor devices B1 in the first direction x among the plurality of semiconductor devices B1. The coupling portion 71 includes a first connection portion 71A and a second connection portion 71B. The first connection portion 71A is located between the first device B11 and the second device B12 in the first direction x and couples the first device B11 and the second device B12 together. The second connection portion 71B is located between the second device B12 and the third device B13 in the first direction x and couples the second device B12 and the third device B13 together.

[0020] As shown in FIGS. 2 to 4 , the first connecting portion 71A and the second connecting portion 71B each include a first strip portion 711 and a second strip portion 712. The first strip portion 711 and the second strip portion 712 described below are common to the first connecting portion 71A and the second connecting portion 71B unless otherwise specified. The first strip portion 711 and the second strip portion 712 each have a longitudinal direction in the first direction x in a plan view. The first strip portion 711 and the second strip portion 712 are each a plate made of metal (for example, copper).

[0021] In each of the first connection portion 71A and the second connection portion 71B, the first strip portion 711 is electrically connected to each of the plurality of semiconductor elements 21 of each of the plurality of semiconductor devices B1. The first strip portion 711 of the first connection portion 71A is connected to one of the plurality of power terminals 13 (second power terminal 15 described below) of the first device B11 and one of the plurality of power terminals 13 (second power terminal 15 described below) of the second device B12. The first strip portion 711 of the second connection portion 71B is connected to one of the plurality of power terminals 13 (second power terminal 15 described below) of the second device B12 and one of the plurality of power terminals 13 (second power terminal 15 described below) of the third device B13.

[0022] In each of the first connection portion 71A and the second connection portion 71B, the second strip portion 712 is not electrically connected to any of the semiconductor elements 21 of each of the semiconductor devices B1. As shown in FIG. 4 , in each of the first connection portion 71A and the second connection portion 71B, the second strip portion 712 includes a covered portion 7121, a covered portion 7122, and an exposed portion 7123.

[0023] In the first connection portion 71A, the covering portion 7121 is covered by the sealing portion 50 of the first device B11, and the covering portion 7122 is covered by the sealing portion 50 of the second device B12. Furthermore, the exposed portion 7123 is exposed from each of the sealing portion 50 of the first device B11 and the sealing portion 50 of the second device B12. The exposed portion 7123 is interposed between the covering portion 7121 and the covering portion 7122 in the first direction x. The covering portion 7121, the covering portion 7122, and the exposed portion 7123 are examples of a "first covering portion," a "second covering portion," and an "exposed portion," respectively.

[0024] In the second connection portion 71B, the covering portion 7121 is covered by the sealing portion 50 of the second device B12, and the covering portion 7122 is covered by the sealing portion 50 of the third device B13. The exposed portion 7123 is exposed from each of the sealing portion 50 of the second device B12 and the sealing portion 50 of the third device B13. The exposed portion 7123 is interposed between the covering portion 7121 and the covering portion 7122 in the first direction x.

[0025] The extending portion 72 is not electrically connected to any of the plurality of semiconductor elements 21 of each of the plurality of semiconductor devices B1 (i.e., is non-conductive). As shown in FIGS. 2 to 4, the extending portion 72 has a first extending portion 721 and a second extending portion 722.

[0026] As shown in Figures 2 to 4, the first extending portion 721 protrudes from the first outer device B21 (first device B11) toward the x1 side in the first direction x. The first extending portion 721 is strip-shaped with the first direction x as its longitudinal direction. As shown in Figure 4, the first extending portion 721 includes a covering portion 7211 and an exposed portion 7212. The covering portion 7211 is covered by the sealing portion 50 of the first device B11. The exposed portion 7212 is connected to the covering portion 7211 and is exposed from the sealing portion 50 of the first device B11.

[0027] As shown in Figures 2 to 4, the second extending portion 722 protrudes from the second outer device B22 (third device B13) toward the x2 side in the first direction x. The second extending portion 722 is strip-shaped with the first direction x as its longitudinal direction. As shown in Figure 4, the second extending portion 722 includes a covering portion 7221 and an exposed portion 7222. The covering portion 7221 is covered by the sealing portion 50 of the third device B13. The exposed portion 7222 is connected to the covering portion 7221 and is exposed from the sealing portion 50 of the third device B13.

[0028] 3 to 5, the first extending portion 721 has a first through hole 7210. The first through hole 7210 is formed in an exposed portion 7212 of the first extending portion 721. The first through hole 7210 penetrates the first extending portion 721 in the thickness direction z.

[0029] 3 to 5, the second extending portion 722 has a second through hole 7220. The second through hole 7220 is formed in an exposed portion 7222 of the second extending portion 722. The second through hole 7220 penetrates the second extending portion 722 in the thickness direction z.

[0030] 3 to 5, the second strip-shaped portion 712 of the first connecting portion 71A and the second strip-shaped portion 712 of the second connecting portion 71B each have a third through hole 710. In each of the second strip-shaped portion 712 of the first connecting portion 71A and the second strip-shaped portion 712 of the second connecting portion 71B, the third through hole 710 is formed in the exposed portion 7123. The third through hole 710 penetrates the second strip-shaped portion 712 in the thickness direction z.

[0031] In the illustrated example, the first through hole 7210 opens into an elongated hole in a plan view, and the second through hole 7220 opens into a perfect circle in a plan view. Alternatively, the first through hole 7210 may open into a perfect circle in a plan view, and the second through hole 7220 may open into an elongated hole in a plan view. Also, in the illustrated example, the third through hole 710 in the second strip-shaped portion 712 of the first connecting portion 71A and the third through hole 710 in the second strip-shaped portion 712 of the second connecting portion 71B each open into an elongated hole in a plan view. Alternatively, either or both of the third through hole 710 in the first connecting portion 71A and the third through hole 710 in the second connecting portion 71B may open into a perfect circle in a plan view. The opening shape of each of the first through hole 7210, the second through hole 7220, and the third through holes 710 of the first connecting portion 71A and the second connecting portion 71B in a planar view may be either a perfect circle or an elongated hole.

[0032] Next, detailed configuration examples of each semiconductor device B1 will be described with reference to FIGS. 10 to 23. FIGS. 10 to 23 show enlarged views of the second device B12 among the multiple semiconductor devices B1. All of the multiple semiconductor devices B1 are identical. Therefore, the second device B12 will be described as an example with reference to FIGS. 10 to 23, but unless otherwise specified, the first device B11 and the third device B13 are also configured in the same way.

[0033] 10 to 23 , each semiconductor device B1 (each of the first device B11, second device B12, and third device B13) includes a support substrate 11, a plurality of power terminals 13, a plurality of signal terminals 17, a plurality of semiconductor elements 21, a thermistor 22, a first conductive member 31, a second conductive member 32, a plurality of wires, a sealing portion 50, and a pair of control wires 60. The plurality of power terminals 13 include a first power terminal 14, two second power terminals 15, and two third power terminals 16, and the plurality of signal terminals 17 include a first signal terminal 171, a second signal terminal 172, a third signal terminal 173, a fourth signal terminal 174, a fifth signal terminal 181, and a pair of sixth signal terminals 182. The plurality of wires include a plurality of first wires 41, a plurality of second wires 42, a plurality of third wires 43, and a fourth wire 44.

[0034] Each semiconductor device B1 converts a DC power supply voltage applied to a first power terminal 14 and two second power terminals 15 into AC power using a plurality of semiconductor elements 21. The converted AC power is input from two third power terminals 16 to a power supply target such as a motor.

[0035] As shown in Figures 14, 16 to 19, 21 and 22, the support substrate 11 supports a plurality of semiconductor elements 21 in the thickness direction z. The support substrate 11 is formed, for example, from a DBC (Direct Bonded Copper) substrate. As shown in Figures 13 to 23, the support substrate 11 includes an insulating layer 111, a first wiring layer 112 and a second wiring layer 113. As shown in Figures 15 to 23, the support substrate 11 is covered with a sealing portion 50 except for a portion of the second wiring layer 113.

[0036] 16 to 23, the insulating layer 111 includes a portion interposed between the first wiring layer 112 and the second wiring layer 113 in the thickness direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. For example, the insulating layer 111 is made of ceramics containing aluminum nitride (AlN). The insulating layer 111 may be made of an insulating resin sheet instead of ceramics.

[0037] As shown in FIGS. 13, 14, and 16 to 23, the first wiring layer 112 is located above (on the z1 side of) the insulating layer 111 in the thickness direction z. The first wiring layer 112 contains copper (Cu). As shown in FIGS. 13 and 14, the first wiring layer 112 is surrounded by the periphery of the insulating layer 111 in a plan view. As shown in FIGS. 13, 14, and 16 to 23, the first wiring layer 112 includes a first mounting portion 1121 and a second mounting portion 1122. The first mounting portion 1121 and the second mounting portion 1122 are each rectangular in a plan view. The first mounting portion 1121 and the second mounting portion 1122 are spaced apart from each other in the second direction y. Each of the multiple semiconductor elements 21 is bonded to either the first mounting portion 1121 or the second mounting portion 1122.

[0038] As shown in Figures 16 to 23, the second wiring layer 113 is located below (on the z2 side of) the insulating layer 111 in the thickness direction z. As shown in Figure 15, the second wiring layer 113 is exposed from the sealing portion 50. A heat sink 80, which will be described later, is bonded to the second wiring layer 113. The composition of the second wiring layer 113 includes copper. The second wiring layer 113 has a rectangular shape in a plan view. The second wiring layer 113 is surrounded by the periphery of the insulating layer 111 in a plan view.

[0039] As shown in FIGS. 14 and 16 to 19 , each of the multiple semiconductor elements 21 is mounted on either the first mounting portion 1121 or the second mounting portion 1122. Each semiconductor element 21 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, each semiconductor element 21 may be a switching element such as an insulated gate bipolar transistor (IGBT) or a diode. In the description of the semiconductor device B1, the semiconductor element 21 is an n-channel MOSFET with a vertical structure. The semiconductor element 21 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC) or silicon (Si).

[0040] 14 and 16 to 19, in each semiconductor device B1, the multiple semiconductor elements 21 include multiple first elements 21A and multiple second elements 21B. The structure of each of the multiple second elements 21B is the same as the structure of each of the multiple first elements 21A. The multiple first elements 21A are mounted on a first mounting portion 1121. The multiple first elements 21A are arranged along the first direction x. The multiple second elements 21B are mounted on a second mounting portion 1122. The multiple second elements 21B are arranged along the first direction x.

[0041] As shown in FIGS. 14, 17, and 18, the plurality of semiconductor elements 21 have a first electrode 211, a second electrode 212, a third electrode 213, and two fourth electrodes 214.

[0042] 17 and 18 , the first electrode 211 faces either the first mounting portion 1121 or the second mounting portion 1122. A current corresponding to the power before being converted by the semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the semiconductor element 21.

[0043] 14 , 17 , and 18 , the second electrode 212 is located on the opposite side of the first electrode 211 in the thickness direction z. A current corresponding to the power converted by the semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the semiconductor element 21.

[0044] 14 , the third electrode 213 is located on the same side as the second electrode 212 in the thickness direction z. A gate voltage for driving the semiconductor element 21 is applied to the third electrode 213. That is, the third electrode 213 corresponds to the gate electrode of the semiconductor element 21. As shown in FIG. 14 , the area of ​​the third electrode 213 is smaller than the area of ​​the second electrode 212 in a plan view.

[0045] 14 , 17 , and 18 , the two fourth electrodes 214 are located on the same side as the second electrode 212 in the thickness direction z and adjacent to the third electrode 213 in the first direction x. In the illustrated example, the two fourth electrodes 214 are arranged on both sides of the third electrode 213 in the first direction x, with the third electrode 213 sandwiched therebetween. The potential of each fourth electrode 214 is equal to the potential of the second electrode 212. Unlike the illustrated example, each semiconductor element 21 may include only one of the two fourth electrodes 214, or may include neither of the two fourth electrodes 214.

[0046] As shown in FIGS. 17 and 18 , the conductive bonding layer 23 is interposed between either the first mounting portion 1121 or the second mounting portion 1122 and the first electrode 211 of one of the multiple semiconductor elements 21. The conductive bonding layer 23 is, for example, solder. Alternatively, the conductive bonding layer 23 may include a sintered body of metal particles. The first electrodes 211 of the multiple first elements 21A are conductively bonded to the first mounting portion 1121 via the conductive bonding layer 23. As a result, the first electrodes 211 of the multiple first elements 21A are electrically connected to the first mounting portion 1121. The first electrodes 211 of the multiple second elements 21B are conductively bonded to the second mounting portion 1122 via the conductive bonding layer 23. As a result, the first electrodes 211 of the multiple second elements 21B are electrically connected to the second mounting portion 1122.

[0047] The plurality of power terminals 13 are electrically connected to the plurality of semiconductor elements 21, respectively. A current corresponding to the power before being converted by the plurality of semiconductor elements 21 or a current corresponding to the power after being converted by the plurality of semiconductor elements 21 flows through the plurality of power terminals 13. The plurality of power terminals 13 include a first power terminal 14, two second power terminals 15, and two third power terminals 16.

[0048] As shown in FIGS. 13 and 19 , the first power terminal 14 is joined to the first mounting portion 1121. This joining method is not limited to any particular method and may be performed using a conductive joining material (e.g., solder), laser welding, or crimping. The first power terminal 14 is electrically connected to the first electrodes 211 of the multiple first elements 21A via the first mounting portion 1121. The first power terminal 14 is a P terminal (positive electrode) to which a DC power supply voltage to be converted into power is applied. As shown in FIG. 13 , the first power terminal 14 is located on the opposite side of the second mounting portion 1122 in the second direction y, with the first mounting portion 1121 sandwiched therebetween. The first power terminal 14 extends from the first mounting portion 1121 to one side (y1 side) in the second direction y and protrudes from the sealing portion 50 to one side (y1 side) in the second direction y. 12 , the first power terminal 14 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In the first power terminal 14, the portion covered by the sealing portion 50 is joined to the first mounting portion 1121. In addition, in the first power terminal 14, the portion exposed from the sealing portion 50 is used as the aforementioned P terminal of each semiconductor device B1.

[0049] A second conductive member 32 is joined to the two second power terminals 15. The two second power terminals 15 are electrically connected to the second electrodes 212 of the multiple second elements 21B via the second conductive member 32. The two second power terminals 15 are N terminals (negative electrodes) to which a DC power supply voltage to be converted is applied. The two second power terminals 15 are spaced apart from each other in the first direction x. The first power terminal 14 is located between the two second power terminals 15. As shown in FIG. 13 , the two second power terminals 15 are located on the same side as the first power terminal 14 with respect to the first mounting portion 1121 and the second mounting portion 1122 in the second direction y. The two second power terminals 15 are spaced apart from the first mounting portion 1121 and the second mounting portion 1122. Each of the two second power terminals 15 extends in the second direction y and protrudes from the sealing portion 50 to one side in the second direction y (y1 side). As shown in Fig. 12, each of the two second power terminals 15 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In each second power terminal 15, a second conductive member 32 is joined to the portion covered by the sealing portion 50. In addition, in each second power terminal 15, the portion exposed from the sealing portion 50 is used as the aforementioned N terminal of each semiconductor device B1.

[0050] The first strip portion 711 of the first connection portion 71A described above is connected to the second power terminal 15 on the x2 side of the two second power terminals 15 of the first device B11 and the second power terminal 15 on the x1 side of the two second power terminals 15 of the second device B12, and is formed integrally therewith. The first strip portion 711 of the second connection portion 71B described above is connected to the second power terminal 15 on the x2 side of the two second power terminals 15 of the second device B12 and the second power terminal 15 on the x1 side of the two second power terminals 15 of the third device B13.

[0051] As shown in FIGS. 13 and 16 , the two third power terminals 16 are each joined to the second mounting portion 1122. This joining method is not limited to any particular method and may be performed using a conductive joining material (e.g., solder), laser welding, or crimping. Each of the two third power terminals 16 is electrically connected to the first electrodes 211 of the plurality of second elements 21B via the second mounting portion 1122. Each of the two third power terminals 16 is also electrically connected to the second electrodes 212 of the plurality of first elements 21A via the second mounting portion 1122 and the first conductive member 31. AC power converted by the plurality of semiconductor elements 21 (the plurality of first elements 21A and the plurality of second elements 21B) is output from the two third power terminals 16. In other words, each of the two third power terminals 16 is an output terminal for the AC power. The two third power terminals 16 are spaced apart from each other in the first direction x. As shown in FIG. 13 , the two third power terminals 16 are located on the opposite side of the first mounting portion 1121 in the second direction y, with the second mounting portion 1122 sandwiched between them. Each of the two third power terminals 16 extends from the second mounting portion 1122 toward the other side in the second direction y (y2 side) and protrudes from the sealing portion 50 toward the other side in the second direction y (y2 side). As shown in FIG. 12 , each of the two third power terminals 16 includes a portion covered by the sealing portion 50 and a portion exposed from the sealing portion 50. In each third power terminal 16, the portion covered by the sealing portion 50 is joined to the second mounting portion 1122. In addition, in each third power terminal 16, the portion exposed from the sealing portion 50 is used as the aforementioned output terminal of each semiconductor device B1.

[0052] The pair of control wirings 60 constitute part of the conductive paths between the multiple signal terminals 17 and the multiple semiconductor elements 21. As shown in FIGS. 13 and 14 , the pair of control wirings 60 includes a first wiring 601 and a second wiring 602. The first wiring 601 is located between the multiple first elements 21A and the first power terminal 14 and two second power terminals 15 in the second direction y. The first wiring 601 is bonded to the first mounting portion 1121 as shown in FIG. 20 . The second wiring 602 is located between the multiple second elements 21B and two third power terminals 16 in the second direction y. The second wiring 602 is bonded to the second mounting portion 1122 as shown in FIG. 23 . The pair of control wirings 60 includes an insulating layer 61, multiple wiring layers 62, a metal layer 63, and multiple sleeves 64. The pair of control wirings 60 is covered by the sealing portion 50 except for a portion of each of the multiple sleeves 64. Unless otherwise specified, the insulating layer 61, the multiple wiring layers 62, the metal layer 63, and the multiple sleeves 64 described below are common to the pair of control wirings 60 (first wiring 601 and second wiring 602).

[0053] 20 and 23 , the insulating layer 61 includes a portion interposed between the plurality of wiring layers 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 is made of, for example, ceramics. The insulating layer 61 may be made of an insulating resin sheet instead of ceramics.

[0054] 14 , 20 , and 23 , the multiple wiring layers 62 are located above the insulating layer 61 in the thickness direction z (on the z1 side). The multiple wiring layers 62 contain copper. As shown in FIG. 14 , the multiple wiring layers 62 include a first wiring layer 621, a second wiring layer 622, a third wiring layer 623, a fourth wiring layer 624, and a fifth wiring layer 625.

[0055] 20 and 23 , the metal layer 63 is located on the opposite side of the multiple wiring layers 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The metal layer 63 contains copper. The metal layer 63 of the first wiring 601 is bonded to the first mounting portion 1121 by an adhesive layer (not shown). The metal layer 63 of the second wiring 602 is bonded to the second mounting portion 1122 by an adhesive layer (not shown). These adhesive layers are made of materials that may or may not be conductive. For example, these adhesive layers are solder.

[0056] As shown in Figures 20 and 23, each of the multiple sleeves 64 is bonded to one of the multiple wiring layers 62 by a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of each of the multiple sleeves 64 (the edge on the z2 side in the thickness direction z) is conductively bonded to one of the multiple wiring layers 62. As shown in Figures 19, 20, and 23, the other end of each of the multiple sleeves 64 (the edge on the z1 side in the thickness direction z) is exposed from the sealing portion 50.

[0057] 13 , the thermistor 22 straddles the third wiring layer 623 of the second wiring 602 and the fifth wiring layer 625 of the second wiring 602 and is conductively joined to them. The thermistor 22 is, for example, an NTC (Negative Temperature Coefficient) thermistor. An NTC thermistor has the characteristic that its resistance decreases gradually with increasing temperature. The thermistor 22 is used as a temperature detection sensor for the semiconductor device B1.

[0058] As shown in FIG. 10 , each of the signal terminals 17 is a metal pin extending in the thickness direction z. The signal terminals 17 protrude from a top surface 51 (described later) of the sealing portion 50. The signal terminals 17 are individually press-fitted into the sleeves 64 of the pair of control wirings 60. As a result, each of the signal terminals 17 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62. The signal terminals 17 include a first signal terminal 171, a second signal terminal 172, a third signal terminal 173, a fourth signal terminal 174, a fifth signal terminal 181, and a pair of sixth signal terminals 182. Of these, the first signal terminal 171, the second signal terminal 172, the third signal terminal 173, the fourth signal terminal 174, and the fifth signal terminal 181 are electrically connected to one of the semiconductor elements 21. On the other hand, the pair of sixth signal terminals 182 are not electrically connected (non-conductive) to any of the plurality of semiconductor elements 21 .

[0059] 20 , the first signal terminal 171 is press-fitted into one of the multiple sleeves 64 that is joined to the first wiring layer 621 of the first wiring 601. As a result, the first signal terminal 171 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the first wiring 601. Furthermore, the first signal terminal 171 is electrically connected to the third electrodes 213 of the multiple first elements 21A. A gate voltage for driving the multiple first elements 21A is applied to the first signal terminal 171.

[0060] 23 , the second signal terminal 172 is press-fitted into one of the multiple sleeves 64 that is joined to the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 172 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the second wiring 602. Furthermore, the second signal terminal 172 is electrically connected to the third electrodes 213 of the multiple second elements 21B. A gate voltage for driving the multiple second elements 21B is applied to the second signal terminal 172.

[0061] 14 and 20 , the third signal terminal 173 is located next to the first signal terminal 171 in the first direction x. As shown in FIG. 20 , the third signal terminal 173 is press-fitted into one of the multiple sleeves 64 that is joined to the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 173 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the first wiring 601. Furthermore, the third signal terminal 173 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple first elements 21A is applied to the third signal terminal 173.

[0062] 14 and 23 , the fourth signal terminal 174 is located adjacent to the second signal terminal 172 in the first direction x. As shown in FIG. 23 , the fourth signal terminal 174 is press-fitted into one of the multiple sleeves 64 that is joined to the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 174 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the second wiring 602. Furthermore, the fourth signal terminal 174 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple second elements 21B is applied to the fourth signal terminal 174.

[0063] 14 and 20 , the fifth signal terminal 181 is located on the opposite side of the first signal terminal 171 in the first direction x, with the third signal terminal 173 sandwiched therebetween. As shown in FIG. 20 , the fifth signal terminal 181 is press-fitted into a sleeve 64 joined to the fifth wiring layer 625 of the first wiring 601. As a result, the fifth signal terminal 181 is supported by the sleeve 64 and is electrically connected to the fifth wiring layer 625 of the first wiring 601. Furthermore, the fifth signal terminal 181 is electrically connected to the first mounting portion 1121. A voltage equivalent to the DC power input to the first power terminal 14 is applied to the fifth signal terminal 181.

[0064] As shown in FIGS. 14 and 23 , the pair of sixth signal terminals 182 are located on the opposite side of the second signal terminal 172 in the first direction x, with the fourth signal terminal 174 sandwiched therebetween. The pair of sixth signal terminals 182 are adjacent to each other in the first direction x. As shown in FIG. 23 , the pair of sixth signal terminals 182 are individually press-fitted into a pair of sleeves 64 joined to the third wiring layer 623 of the second wiring 602 and the fifth wiring layer 625 of the second wiring 602. As a result, the pair of sixth signal terminals 182 are individually supported by the pair of sleeves 64 and are individually electrically connected to the third wiring layer 623 of the second wiring 602 and the fifth wiring layer 625 of the second wiring 602. Furthermore, the pair of sixth signal terminals 182 are electrically connected to the thermistor 22.

[0065] The plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 electrically connect portions spaced apart from one another. The plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 are each bonding wires. Note that the plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, and the fourth wire 44 are omitted in Figures 3, 4, 12, 16 to 20, and 23.

[0066] As shown in FIG. 14 , the multiple first wires 41 are conductively joined to the third electrodes 213 of the multiple first elements 21A and the fourth wiring layer 624 of the first wiring 601. As shown in FIG. 14 , the multiple third wires 43 are conductively joined to the fourth wiring layer 624 of the first wiring 601 and the first wiring layer 621 of the first wiring 601. This allows the first signal terminal 171 to be conductively connected to the third electrodes 213 of the multiple first elements 21A. The composition of the multiple first wires 41 and the multiple third wires 43 includes gold (Au). Alternatively, the composition of the multiple first wires 41 and the multiple third wires 43 may include copper or aluminum.

[0067] 14, the plurality of first wires 41 are conductively joined to the third electrodes 213 of the plurality of second elements 21B and the fourth wiring layer 624 of the second wiring 602. Furthermore, the plurality of third wires 43 are conductively joined to the fourth wiring layer 624 of the second wiring 602 and the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 172 is electrically connected to the third electrodes 213 of the plurality of second elements 21B.

[0068] As shown in FIG. 14 , the multiple second wires 42 are conductively bonded to one of the two fourth electrodes 214 of the multiple first elements 21A and the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 173 is electrically connected to one of the two fourth electrodes 214 of the multiple first elements 21A. Furthermore, as shown in FIG. 14 , the multiple second wires 42 are conductively bonded to one of the two fourth electrodes 214 of the multiple second elements 21B and the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 174 is electrically connected to one of the two fourth electrodes 214 of the multiple second elements 21B. The composition of the multiple second wires 42 includes gold. Alternatively, the composition of the multiple second wires 42 may include copper or aluminum. In addition, if each semiconductor element 21 (each of the multiple first elements 21A and the multiple second elements 21B) does not include either of the two fourth electrodes 214, the multiple second wires 42 are joined one by one to the second electrodes 212 of the multiple semiconductor elements 21.

[0069] 14 , the fourth wire 44 is conductively bonded to the fifth wiring layer 625 of the first wiring 601 and the first mounting portion 1121. As a result, the fifth signal terminal 181 is electrically connected to the first electrodes 211 of the multiple first elements 21A via the first mounting portion 1121. The composition of the fourth wire 44 includes gold. Alternatively, the composition of the fourth wire 44 may include copper or aluminum.

[0070] As shown in FIGS. 13 and 16 , the first conductive member 31 is conductively bonded to the second electrodes 212 of the plurality of first elements 21A and the second mounting portion 1122. This allows the second electrodes 212 of the plurality of first elements 21A to be electrically connected to the second mounting portion 1122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in FIGS. 13 and 16 , the first conductive member 31 has a main body 311, a plurality of first joint portions 312, and a plurality of second joint portions 313.

[0071] The main body portion 311 forms a major portion of the first conductive member 31. As shown in FIG. 13 , the main body portion 311 extends in the first direction x. As shown in FIGS. 13 and 16 , the main body portion 311 straddles the first mounting portion 1121 and the second mounting portion 1122. As shown in FIG. 13 , a plurality of through holes 310 are formed in the main body portion 311. Each of the plurality of through holes 310 penetrates the main body portion 311 in the thickness direction z. The plurality of through holes 310 overlap between the first mounting portion 1121 and the second mounting portion 1122 in a plan view. This allows the sealing portion 50 to flow smoothly downward in the thickness direction z of the main body portion 311 (toward the z2 side in the thickness direction z) during the formation of the sealing portion 50.

[0072] As shown in FIGS. 13 and 16 , the multiple first joints 312 are individually joined to the second electrodes 212 of the multiple first elements 21A. Each of the multiple first joints 312 faces one of the second electrodes 212 of the multiple first elements 21A. In a plan view, each first joint 312 extends from the main body 311 toward the y1 side in the second direction y. In the illustrated example, the multiple first joints 312 are bifurcated from the main body 311, but they do not necessarily need to be bifurcated. The base end of each first joint 312 (the end connected to the main body 311) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip of each first joint 312 (the end opposite to the end connected to the main body 311) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) from the main body 311 in the thickness direction z.

[0073] 13 and 16 , the multiple second joints 313 are joined to the second mounting portion 1122. Each of the multiple second joints 313 faces the second mounting portion 1122. In a plan view, each second joint 313 extends from the main body 311 toward the y2 side in the second direction y. The base end of each second joint 313 (the end connected to the main body 311) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip of each second joint 313 (the end opposite to the end connected to the main body 311) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) relative to the main body 311 in the thickness direction z.

[0074] 17 and 18, the semiconductor device B1 further includes a first conductive bonding layer 33. The first conductive bonding layer 33 is interposed between the second electrodes 212 of the plurality of first elements 21A and the plurality of first bonding portions 312. The first conductive bonding layer 33 conductively bonds the second electrodes 212 of the plurality of first elements 21A to the plurality of first bonding portions 312. The first conductive bonding layer 33 is, for example, solder. Alternatively, the first conductive bonding layer 33 may include a sintered body of metal particles.

[0075] 16, the semiconductor device B1 further includes a second conductive bonding layer 34. The second conductive bonding layer 34 is interposed between the second mounting portion 1122 and the second bonding portion 314. The second conductive bonding layer 34 conductively bonds the second mounting portion 1122 and the second bonding portion 314. The second conductive bonding layer 34 is, for example, solder. Alternatively, the second conductive bonding layer 34 may include a sintered body of metal particles.

[0076] As shown in FIG. 12 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second elements 21B and the two second power terminals 15. As a result, the second electrodes 212 of the plurality of second elements 21B are electrically connected to the two second power terminals 15. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in FIGS. 12 , 16 , and 19 to 22 , the second conductive member 32 has a pair of main body portions 321, a plurality of third joint portions 322, a pair of fourth joint portions 324, a plurality of intermediate portions 326, a plurality of horizontal beam portions 327, and a pair of hanging portions 328.

[0077] As shown in Fig. 12 , the pair of main body portions 321 are positioned apart from each other in the first direction x. The pair of main body portions 321 extend in the second direction y. As shown in Figs. 16 and 20 , the pair of main body portions 321 are disposed parallel to the upper surfaces of the first mounting portion 1121 and the second mounting portion 1122. The pair of main body portions 321 are positioned further away from the first mounting portion 1121 and the second mounting portion 1122 than the main body portion 311 of the first conductive member 31.

[0078] 12, 21, and 22, the intermediate portions 326 are spaced apart from one another in the first direction x and are located between the pair of main body portions 321 in the first direction x. The intermediate portions 326 extend in the second direction y.

[0079] As shown in FIGS. 12 and 22 , the third joints 322 are individually joined to the second electrodes 212 of the second elements 21B. Each of the third joints 322 faces one of the second electrodes 212 of the second elements 21B. In a plan view, the third joints 322 extend in the first direction x from the intermediate portions 326. The base end of each third joint 322 (the end connected to the intermediate portion 326) is bent downward in the thickness direction z (toward the z2 side in the thickness direction z). Therefore, the tip of each third joint 322 (the end opposite to the end connected to the intermediate portion 326) is located downward in the thickness direction z (toward the z2 side in the thickness direction z) from the intermediate portion 326 in the thickness direction z.

[0080] 12 and 16 , the pair of fourth joint portions 324 are individually joined to the two second power terminals 15. Each of the pair of fourth joint portions 324 faces a corresponding one of the two second power terminals 15.

[0081] As shown in Fig. 12 , the multiple cross beam portions 327 are arranged along the first direction x. In a plan view, the multiple cross beam portions 327 include regions that individually overlap the multiple first joint portions 312 of the first conductive member 31. As shown in Figs. 12 and 21 , one of the multiple cross beam portions 327 that is located at the center in the first direction x is connected on both sides in the first direction x to the multiple intermediate portions 326. The remaining two of the multiple cross beam portions 327 are connected on both sides in the first direction x to one of the pair of main body portions 321 and one of the multiple intermediate portions 326.

[0082] 12 and 21 , the pair of hanging portions 328 are individually connected to the pair of main body portions 321. As shown in FIG. 21 , each of the pair of hanging portions 328 extends downward in the thickness direction z (toward the z2 side in the thickness direction z) from a corresponding one of the pair of main body portions 321. Each of the pair of hanging portions 328 is connected to the outer edge of the corresponding one of the pair of main body portions 321 in the first direction x. In the illustrated example, the lower ends (edges on the z2 side in the thickness direction z) of the pair of hanging portions 328 overlap the first mounting portion 1121 when viewed along the second direction y.

[0083] 18 , the semiconductor device B1 further includes a third conductive bonding layer 35. The third conductive bonding layer 35 is interposed between the second electrodes 212 of the plurality of second elements 21B and the plurality of third bonding portions 322. The third conductive bonding layer 35 conductively bonds the second electrodes 212 of the plurality of second elements 21B to the plurality of third bonding portions 322. The third conductive bonding layer 35 is, for example, solder. Alternatively, the third conductive bonding layer 35 may include a sintered body of metal particles.

[0084] 16 , the semiconductor device B1 further includes a fourth conductive bonding layer 36. The fourth conductive bonding layer 36 is interposed between the two second power terminals 15 and the pair of fourth joints 324. The fourth conductive bonding layer 36 conductively bonds the two second power terminals 15 and the pair of fourth joints 324. The fourth conductive bonding layer 36 is, for example, solder. Alternatively, the fourth conductive bonding layer 36 may include a sintered body of metal particles.

[0085] As shown in FIGS. 10 to 23 , the sealing portion 50 covers the semiconductor elements 21, the first conductive members 31, the second conductive members 32, the first wires 41, the second wires 42, and the third wires 43. Furthermore, the sealing portion 50 covers a portion of each of the support substrate 11, the power terminals 13, and the signal terminals 17. The sealing portion 50 has electrical insulation properties. The sealing portion 50 contains, for example, a black epoxy resin. The sealing portion 50 is formed, for example, by molding. As shown in FIGS. 10 to 12 and 15 to 23 , the sealing portion 50 has a top surface 51, a bottom surface 52, a plurality of resin side surfaces 53, and a pair of recesses 55.

[0086] 16 and 19 to 23, the top surface 51 faces in the same direction in the thickness direction z as the upper surfaces of the first mounting portion 1121 and the second mounting portion 1122. As shown in Fig. 16 and 19 to 23, the bottom surface 52 faces the opposite side in the thickness direction z from the top surface 51. As shown in Fig. 15, the second wiring layer 113 of the support substrate 11 is exposed from the bottom surface 52.

[0087] The plurality of resin side surfaces 53 are connected to the top surface 51. The plurality of resin side surfaces 53 include a pair of first side surfaces 531 and a pair of second side surfaces 532.

[0088] 11 , 12 , 16 , and 19 , the pair of first side surfaces 531 are spaced apart from each other in the second direction y. The pair of first side surfaces 531 face the second direction y and extend in the first direction x. The pair of first side surfaces 531 are connected to the top surface 51. A first power terminal 14 and two second power terminals 15 protrude from the first side surface 531 on the y1 side in the second direction y of the pair of first side surfaces 531. Two third power terminals 16 protrude from the first side surface 531 on the y2 side in the second direction y of the pair of first side surfaces 531.

[0089] 11, 12, and 20 to 23, the pair of second side surfaces 532 are spaced apart from each other in the first direction x. The pair of second side surfaces 532 face opposite each other in the first direction x and extend in the second direction y. The pair of second side surfaces 532 are connected to the top surface 51 and the bottom surface 52.

[0090] 2, 3, 11, and 13, the first extending portion 721 protrudes from the second side surface 532 on the x1 side of the pair of second side surfaces 532 of the first device B11. The second band-shaped portion 712 of the first connecting portion 71A protrudes from the second side surface 532 on the x2 side of the pair of second side surfaces 532 of the first device B11, and also protrudes from the second side surface 532 on the x1 side of the pair of second side surfaces 532 of the second device B12. The second band-shaped portion 712 of the second connecting portion 71B protrudes from the second side surface 532 on the x2 side of the pair of second side surfaces 532 of the second device B12, and also protrudes from the second side surface 532 on the x1 side of the pair of second side surfaces 532 of the third device B13. The second extending portion 722 described above protrudes from the second side surface 532 on the x2 side of the pair of second side surfaces 532 of the third device B13.

[0091] 11 , the pair of recesses 55 are recessed in the second direction y from the first side surface 531 on the y1 side in the second direction y of the pair of first side surfaces 531. The pair of recesses 55 extend from the top surface 51 to the bottom surface 52 in the thickness direction z. The pair of recesses 55 are located on both sides of the first power terminal 14 in the second direction y.

[0092] Next, the mounting structure C1 for the semiconductor module A1 will be described with reference to Figures 24 to 28. The mounting structure C1 for the semiconductor module A1 includes the semiconductor module A1, a heat sink 80, a wiring board 81, a mounting member 84, a plurality of positioning pins 86, and a plurality of fastening members 87.

[0093] As shown in FIGS. 26 and 27 , the heat sink 80 supports the semiconductor module A1 (plurality of semiconductor devices B1). The heat sink 80 is located on the opposite side of the semiconductor elements 21 of the plurality of semiconductor devices B1 from the plurality of signal terminals 17 of the plurality of semiconductor devices B1. Therefore, the heat sink 80 faces each second wiring layer 113 of the plurality of semiconductor devices B1. The heat sink 80 is made of a material containing aluminum, for example. As shown in FIGS. 24 , 25 , and 27 , the plurality of semiconductor devices B1 are arranged on the heat sink 80 along the first direction x.

[0094] As shown in FIGS. 24 and 27 , the wiring board 81 is provided in common for the multiple semiconductor devices B1. Alternatively, multiple wiring boards 81 may be provided individually for the multiple semiconductor devices B1. As can be seen from FIGS. 24 and 27 , the signal terminals 17 of the multiple semiconductor devices B1 are inserted into the wiring board 81, respectively, and are electrically connected to each signal terminal 17. The wiring board 81 is, for example, a gate driver that controls the driving of each semiconductor element 21 of the multiple semiconductor devices B1. The wiring board 81 faces the top surface 51 of each sealing portion 50 of the multiple semiconductor devices B1. The wiring board 81 is located on the opposite side of the heat sink 80 from the multiple semiconductor devices B1. In a plan view, the wiring board 81 individually overlaps each sealing portion 50 of the multiple semiconductor devices B1.

[0095] 28 , the wiring board 81 has a substrate 811, main wiring 812, rear wiring 813, and internal wiring 814. The substrate 811 is provided with a plurality of through holes 811A that penetrate in the thickness direction z. The main wiring 812 is arranged on one side of the substrate 811 in the thickness direction z (the side opposite the semiconductor device B1 in the thickness direction z). The internal wiring 814 is arranged on the inner surface of the plurality of through holes 811A. The internal wiring 814 is connected to the main wiring 812 and the rear wiring 813. The main wiring 812 forms a path for mutual conduction between the internal wiring 814 and a circuit provided on any one of the plurality of wiring boards 81.

[0096] Each signal terminal 17 of the plurality of semiconductor devices B1 is inserted into a corresponding one of a plurality of through holes 811A of the plurality of wiring substrates 81. Fig. 28 shows a state in which one of the signal terminals 17 of the plurality of semiconductor devices B1 is inserted into a through hole 811A of the substrate 811. Note that all of the signal terminals 17 of the plurality of semiconductor devices B1 have the same configuration as that shown in Fig. 28.

[0097] 28 , each signal terminal 17 has a base 170A and a bulge 170B. One side of the base 170A in the thickness direction z is press-fitted into one of the multiple sleeves 64 of the multiple semiconductor devices B1. The bulge 170B is provided on one side (z1 side) of the base 170A in the thickness direction z. The bulge 170B bulges in a direction perpendicular to the thickness direction z.

[0098] 28 , each signal terminal 17 is press-fitted into one of the plurality of through holes 811A of the wiring board 81. As a result, the internal wiring 814 arranged in one of the plurality of through holes 811A is pressed into contact with the bulging portion 170B of the signal terminal 17 inserted into that through hole 811A. Therefore, by being press-fitted into the through hole 811A in the thickness direction z, each signal terminal 17 is electrically connected to the wiring board 81. By press-fitting each signal terminal 17 into a corresponding one of the plurality of through holes 811A, the wiring board 81 is supported by each signal terminal 17.

[0099] As shown in FIGS. 26 and 27 , the positioning pins 86 each extend from the upper surface (the surface facing the z1 side in the thickness direction z) of the heat sink 80 toward the z1 side in the thickness direction z. The positioning pins 86 may be formed integrally with the heat sink 80 or may be bonded to the heat sink 80. As shown in FIG. 25 , each of the positioning pins 86 is inserted through a corresponding one of the third through-hole 710 in the second strip-shaped portion 712 of the first connecting portion 71A (coupling portion 71), the third through-hole 710 in the second strip-shaped portion 712 of the second connecting portion 71B (coupling portion 71), the first through-hole 7210 in the first extending portion 721 (extending portion 72), and the second through-hole 7220 in the second extending portion 722 (extending portion 72). In the illustrated example, the tip (the edge on the z1 side in the thickness direction z) of each positioning pin 86 contacts the wiring board 81. As a result, the wiring board 81 is supported by the plurality of positioning pins 86. Alternatively, a plurality of support pillars (not shown) may be disposed on the heat sink 80 or on the sealing portion 50 of each semiconductor device B1, and the wiring board 81 may be supported by the plurality of support pillars. In this case, the tip of each positioning pin 86 does not need to be in contact with the wiring board 81.

[0100] As shown in FIGS. 25 to 27 , the mounting member 84 is used to restrain the semiconductor module A1 (multiple semiconductor devices B1) to the heat sink 80. The mounting member 84 is composed of, for example, a metal. The mounting member 84 contacts the top surface 51 of each sealing portion 50 of the multiple semiconductor devices B1. The mounting member 84 straddles the top surface 51 of each sealing portion 50 of the multiple semiconductor devices B1 in the first direction x. The mounting member 84 is, for example, a leaf spring. The mounting member 84 is positioned between the first signal terminal 171 and the second signal terminal 172 of each semiconductor device B1 in the second direction y. The mounting member 84 is positioned between the heat sink 80 and the wiring board 81 in the thickness direction z. The mounting member 84 is partially bent. The mounting member 84 contacts the heat sink 80 between two semiconductor devices B1 adjacent to each other in the first direction x. Furthermore, at least a portion of the region of the mounting member 84 that overlaps with each sealing portion 50 in a plan view contacts the top surface 51 of each sealing portion 50. A plurality of through holes 841 are formed in the mounting member 84. Each of the plurality of through holes 841 penetrates the mounting member 84 in the thickness direction z. Each of the plurality of through holes 841 is formed in a portion of the mounting member 84 that contacts the heat sink 80.

[0101] Each of the plurality of fastening members 87 is, for example, a male screw. As shown in FIGS. 25 to 27 , each of the plurality of fastening members 87 is inserted into a corresponding one of the plurality of through holes 841. Each of the plurality of fastening members 87 is fastened to a female-threaded hole (not shown) formed in the heat sink 80. In this way, the plurality of semiconductor devices B1 are restrained by the attachment member 84 and the plurality of fastening members 87.

[0102] The functions and effects of the semiconductor module A1 and the mounting structure C1 for the semiconductor module A1 are as follows.

[0103] The semiconductor module A1 includes multiple semiconductor devices B1 and a connecting portion 71. The multiple semiconductor devices B1 include a first device B11 and a second device B12. The connecting portion 71 includes a first connection portion 71A. The first connection portion 71A is located between the first device B11 and the second device B12 in the first direction x and connects the first device B11 and the second device B12. With this configuration, the first connection portion 71A can suppress variation in the relative positional relationship between the first device B11 and the second device B12. Therefore, the semiconductor module A1 can suppress variation in the position of the signal terminals 17 among the multiple semiconductor devices B1, allowing the wiring substrate 81 to be properly connected to the semiconductor module A1.

[0104] In the semiconductor module A1, the multiple semiconductor devices B1 include a first device B11, a second device B12, and a third device B13. The coupling portion 71 also includes a second connection portion 71B. The second connection portion 71B is located between the second device B12 and the third device B13 in the first direction x and connects the second device B12 and the third device B13. With this configuration, the second connection portion 71B can prevent variations in the relative positional relationship between the second device B12 and the third device B13. As can be seen from this configuration, the number of multiple semiconductor devices B1 in the semiconductor module of the present disclosure is not limited in any way.

[0105] The mounting structure C1 for the semiconductor module A1 includes the semiconductor module A1 and a heat sink 80. As described above, the semiconductor module A1 can suppress variations in the relative positional relationship between the multiple semiconductor devices B1, and therefore, the mounting structure C1 for the semiconductor module A1 can improve the accuracy of positioning the multiple semiconductor devices B1 with respect to the heat sink 80.

[0106] The semiconductor module A1 includes an extension portion 72. The extension portion 72 includes a first extension portion 721 protruding from the first external device B21 toward the x1 side in the first direction x and a second extension portion 722 protruding from the second external device B22 toward the x2 side in the first direction x. The first extension portion 721 has a first through hole 7210, and the second extension portion 722 has a second through hole 7220. The first through hole 7210 and the second through hole 7220 are each inserted into a corresponding one of a plurality of positioning pins 86 formed in the heat sink 80. This configuration can prevent misalignment of the semiconductor module A1 with respect to the heat sink 80. In other words, the mounting structure C1 for the semiconductor module A1 facilitates positioning of the plurality of semiconductor devices B1 on the heat sink 80. Furthermore, in the semiconductor module A1, the coupling portion 71 (each of the first connection portion 71A and the second connection portion 71B) includes a second strip portion 712. The second strip portion 712 of each of the first connection portion 71A and the second connection portion 71B has a third through hole 710. Each of the third through holes 710 is inserted into a corresponding one of the plurality of positioning pins 86 formed on the heat sink 80. This configuration can further suppress misalignment of the semiconductor module A1 with respect to the heat sink 80.

[0107] In the semiconductor module A1, either the first through hole 7210 or the second through hole 7220 opens into a perfect circle when viewed in the thickness direction z. In the illustrated example, the second through hole 7220 opens into a perfect circle. With this configuration, a positioning pin 86 is inserted into the perfect circle opening, thereby suppressing rotation and rattle of the semiconductor module A1 along the x-y plane. Furthermore, in the semiconductor module A1, the other of the first through hole 7210 or the second through hole 7220 opens into an elongated hole when viewed in the thickness direction z. In the illustrated example, the first through hole 7210 opens into an elongated hole. With this configuration, poor connection of the wiring substrate 81 to the semiconductor module A1 due to errors (manufacturing errors) during the manufacturing of each semiconductor device B1 is suppressed.

[0108] In the semiconductor module A1, the first connection portion 71A includes a first strip portion 711. The first strip portion 711 connects the second power terminals 15 of the first device B11 and the second device B12, which are adjacent in the first direction x. With this configuration, the second power terminal 15 of the first device B11 and the second power terminal 15 of the second device B12 are at the same potential. The second connection portion 71B also includes a first strip portion 711. The first strip portion 711 connects the second power terminals 15 of the second device B12 and the third device B13, which are adjacent in the first direction x. With this configuration, the second power terminal 15 of the second device B12 and the second power terminal 15 of the third device B13 are at the same potential. As a result, the semiconductor module A1 can share the low-potential side of the input power supply voltage.

[0109] In the semiconductor module A1, the coupling portion 71 includes a first connection portion 71A and a second connection portion 71B. The first connection portion 71A and the second connection portion 71B each include a first strip portion 711 and a second strip portion 712. In each of the first connection portion 71A and the second connection portion 71B, the first strip portion 711 is located on the y1 side in the second direction y relative to the second strip portion 712. This configuration can further reduce variation in the positional relationships between the multiple semiconductor devices B1.

[0110] Other embodiments and modifications of the semiconductor module and mounting structure for the semiconductor module of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other to the extent that no technical contradiction occurs.

[0111] 29 and 30 show a semiconductor module A11 and a mounting structure C11 for the semiconductor module A11 according to a first modification of the first embodiment. The semiconductor module A11 differs from the semiconductor module A1 in the following respects. Specifically, the second strip portions 712 of the first connection portion 71A and the second connection portion 71B of the coupling portion 71 have portions that are bent downward in the thickness direction z. Furthermore, the first extending portion 721 and the second extending portion 722 of the extending portion 72 are bent downward in the thickness direction z.

[0112] In the mounting structure C11 for the semiconductor module A11, each of the multiple fastening members 87 is inserted through a corresponding one of the third through-holes 710 of the first connecting portion 71A and the second connecting portion 71B, the first through-hole 7210 of the first extending portion 721, and the second through-hole 7220 of the second extending portion 722. This restrains the semiconductor module A11 to the heat sink 80.

[0113] The mounting structure C11 for the semiconductor module A11 also includes a plurality of support posts 88. Each of the support posts 88 is positioned between the semiconductor devices B1 and the wiring board 81 in the thickness direction z. In the example shown in FIG. 30 , each of the support posts 88 contacts the top surface 51 of the sealing portion 50 of one of the semiconductor devices B1 and also contacts the wiring board 81. In the example shown in FIG. 29 , four support posts 88 are arranged for each semiconductor device B1. In a plan view, the four support posts 88 are arranged at the four corners of the sealing portion 50 of the corresponding semiconductor device B1 that overlaps with the wiring board 81. The material of the support posts 88 may include either an insulating resin material or a metal material, but an insulating resin material is preferable to prevent unintended short circuits. Note that the arrangement and number of the support posts 88 are not limited to the example shown. For example, the support posts 88 may be arranged to contact the heat sink 80 rather than the semiconductor devices B1.

[0114] Similar to the semiconductor module A1, the semiconductor module A11 can suppress variations in the relative positions of the multiple semiconductor devices B1. Furthermore, in the mounting structure C11 for the semiconductor module A11, the semiconductor module A11 is constrained to the heat sink 80 using the connecting portion 71 and the extending portion 72, so no mounting member 84 is required. However, in order to more reliably constrain the semiconductor module A11 to the heat sink 80, the mounting structure C11 for the semiconductor module A11 may include the mounting member 84.

[0115] 31 shows a semiconductor module A12 according to a second modification of the first embodiment. The semiconductor module A12 differs from the semiconductor module A1 in the following respect: the second strip portions 712 and the extending portions 72 (first extending portions 721 and second extending portions 722) of the coupling portion 71 (first connecting portion 71A and second connecting portion 71B) are insulating.

[0116] In the semiconductor module A12, the second strip portions 712, the first extending portions 721, and the second extending portions 722 each include an insulating material, such as polycarbonate or glass epoxy resin. Because the second strip portions 712, the first extending portions 721, and the second extending portions 722 are insulating, they are joined to the second mounting portion 1122, as shown in FIG. 31 .

[0117] Similar to the semiconductor module A1, the semiconductor module A12 can prevent variations in the relative positions of the multiple semiconductor devices B1. Furthermore, in the semiconductor module A12, the second strip portions 712, the first extending portions 721, and the second extending portions 722 are bonded to the second mounting portions 1122 of the corresponding semiconductor devices B1, and therefore, these are prevented from coming out of the sealing portion 50.

[0118] 32 to 34 show a semiconductor module A2 according to the second embodiment. The semiconductor module A2 differs from the semiconductor module A1 in the configuration of each of the first strip portions 711 of the first connection portion 71A and the second connection portion 71B (coupling portion 71). The semiconductor module A2 is attached to the heat sink 80 in the same manner as the semiconductor module A1. In other words, the attachment structure of the semiconductor module A2 is configured in the same manner as the attachment structure C1 of the semiconductor module A1.

[0119] In the semiconductor module A2, each first strip portion 711 is not electrically connected to any of the semiconductor elements 21 of each of the semiconductor devices B1. Each first strip portion 711 of the first connection portion 71A and the second connection portion 71B includes a covered portion 7111, a covered portion 7112, and an exposed portion 7113, as shown in FIG.

[0120] In the first connection portion 71A, the covering portion 7111 is covered by the sealing portion 50 of the first device B11, and the covering portion 7112 is covered by the sealing portion 50 of the second device B12. The exposed portion 7113 is exposed from both the sealing portion 50 of the first device B11 and the sealing portion 50 of the second device B12. The exposed portion 7113 is interposed between the covering portion 7111 and the covering portion 7112 in the first direction x. A third through hole 710 is formed in the exposed portion 7113. In the illustrated example, the third through hole 710 opens into an elongated hole in a plan view, but may also open into a perfect circle. As shown in FIG. 34 , the covering portion 7111 of the first connection portion 71A is disposed between the support substrate 11 of the first device B11 and the main body portion 321 of the second conductive member 32 in the thickness direction z and is spaced apart therefrom. The covering portion 7111 extends until it overlaps with the hanging portion 328 of the second conductive member 32 of the first device B11 when viewed along the second direction y. The covering portion 7112 of the first connection portion 71A is disposed between the support substrate 11 of the second device B12 and the main body portion 321 of the second conductive member 32 and is spaced apart from them in the thickness direction z. The covering portion 7112 extends until it overlaps with the hanging portion 328 of the second conductive member 32 of the second device B12 when viewed along the second direction y.

[0121] In the second connection portion 71B, the covering portion 7111 is covered by the sealing portion 50 of the second device B12, and the covering portion 7112 is covered by the sealing portion 50 of the third device B13. The exposed portion 7113 is exposed from each of the sealing portions 50 of the second device B12 and the third device B13. The exposed portion 7113 is interposed between the covering portion 7111 and the covering portion 7112 in the first direction x. A third through hole 710 is formed in the exposed portion 7113. In the illustrated example, the third through hole 710 opens into an elongated hole in a plan view, but may also open into a perfect circle. The positional relationship between the second connection portion 71B and the second device B12 and the third device B13 is configured similarly to the positional relationship between the first connection portion 71A and the first device B11 and the second device B12. 34 , the covering portion 7111 of the second connection portion 71B is disposed between the support substrate 11 of the second device B12 and the main body portion 321 of the second conductive member 32 and is spaced apart from them in the thickness direction z. The covering portion 7111 extends to overlap with the hanging portion 328 of the second conductive member 32 of the second device B12 when viewed in the second direction y. The covering portion 7112 of the second connection portion 71B is disposed between the support substrate 11 of the third device B13 and the main body portion 321 of the second conductive member 32 and is spaced apart from them in the thickness direction z. The covering portion 7112 extends to overlap with the hanging portion 328 of the second conductive member 32 of the third device B13 when viewed in the second direction y.

[0122] Furthermore, in the semiconductor module A2, the covering portions 7121 and 7122 of each second strip portion 712 have a width that is wider in part on the inside of the sealing portion 50, as shown in FIG. 33 . This makes it possible to prevent each second strip portion 712 from coming off the sealing portion 50. Similarly, the covering portion 7211 of the first extending portion 721 and the covering portion 7221 of the second extending portion 722 also have a width that is wider in part on the inside of the sealing portion 50, as shown in FIG. 33 . This makes it possible to prevent each of the first extending portion 721 and the second extending portion 722 from coming off the sealing portion 50.

[0123] Similar to the semiconductor module A1, the semiconductor module A2 can prevent variations in the relative positions of the multiple semiconductor devices B1. As described above, the semiconductor module A2 can prevent each second strip portion 712, first extending portion 721, and second extending portion 722 from coming out of the sealing portion 50 of any of the multiple semiconductor devices B1. Furthermore, in the semiconductor module A2, the third through-holes 710 are also formed in each first strip portion 711, and thus, by inserting the positioning pins 86 into the third through-holes 710, rotation of the semiconductor module A2 along the x-y plane can be prevented.

[0124] 35 to 37 show a semiconductor module A21 according to a modification of the second embodiment. The semiconductor module A21 differs from the semiconductor module A2 in the configuration of the coupling portion 71 (first connection portion 71A and second connection portion 71B).

[0125] As shown in FIGS. 35 and 36 , in the semiconductor module A21, the first strip portion 711 of the first connection portion 71A and the first strip portion 711 of the second connection portion 71B are connected to each other and integrally formed inside the sealing portion 50 of the second device B12. For ease of explanation, this integrally formed portion is referred to as the first strip portion 711 of the linking portion 71. Thus, in this modification, the first strip portion 711 of the linking portion 71 extends in the first direction x from one of the pair of second side surfaces 532 of the sealing portion 50 of the second device B12 to the other. The first strip portion 711 of the linking portion 71 is located above the second conductive member 32 in the thickness direction z (on the z1 side in the thickness direction z). As shown in FIGS. 35 and 36 , the first strip portion 711 of the linking portion 71 overlaps the multiple cross beam portions 327 and the multiple first elements 21A in a plan view. In the illustrated example, an insulating sheet 791 is provided to prevent a short circuit between the first strip portion 711 of the connecting portion 71 and the second conductive member 32. The first strip portion 711 of the connecting portion 71 is disposed on the second conductive member 32 with the insulating sheet 791 sandwiched therebetween. Note that the insulating sheet 791 may be omitted if adequate insulation between the first strip portion 711 of the connecting portion 71 and the second conductive member 32 can be ensured. Although not illustrated, the first strip portion 711 of the first connecting portion 71A may similarly extend in the first direction x from one of the pair of second side surfaces 532 of the sealing portion 50 of the first device B11 to the other. Similarly, the first strip portion 711 of the second connecting portion 71B may similarly extend in the first direction x from one of the pair of second side surfaces 532 of the sealing portion 50 of the third device B13 to the other.

[0126] As shown in FIGS. 35 and 37 , in the semiconductor module A21, the second strip portion 712 of the first connection portion 71A and the second strip portion 712 of the second connection portion 71B are connected to each other and integrally formed inside the sealing portion 50 of the second device B12. For ease of explanation, this integrally formed portion is referred to as the second strip portion 712 of the linking portion 71. Thus, in this modification, the second strip portion 712 of the linking portion 71 extends in the first direction x from one of the pair of second side surfaces 532 of the sealing portion 50 of the second device B12 to the other. The second strip portion 712 of the linking portion 71 is located above the second conductive member 32 in the thickness direction z (on the z1 side in the thickness direction z). As shown in FIGS. 35 and 37 , the second strip portion 712 of the linking portion 71 overlaps the plurality of third joint portions 322 and the plurality of second elements 21B in a plan view. In the illustrated example, an insulating sheet 792 is provided to prevent a short circuit between the second strip portion 712 of the connecting portion 71 and the second conductive member 32. The second strip portion 712 of the connecting portion 71 is disposed on the second conductive member 32 with the insulating sheet 792 sandwiched therebetween. Note that the insulating sheet 792 may be omitted if adequate insulation between the second strip portion 712 of the connecting portion 71 and the second conductive member 32 can be ensured. Also, unlike the example shown in FIG. 37 , the insulating sheet 792 may be separated into multiple portions and disposed only in the region that contacts the second conductive member 32. Although not illustrated, the second strip portion 712 of the first connection portion 71A may extend in the first direction x from one of the pair of second side surfaces 532 of the sealing portion 50 of the first device B11 to the other. In this case, the second band-shaped portion 712 of the first connection portion 71A is connected to the first extending portion 721 inside the sealing portion 50 of the first device B11. Similarly, the second band-shaped portion 712 of the second connection portion 71B may extend in the first direction x from one of the pair of second side surfaces 532 of the sealing portion 50 of the third device B13 to the other. In this case, the second band-shaped portion 712 of the second connection portion 71B is connected to the second extending portion 722 inside the sealing portion 50 of the third device B13.

[0127] Like the semiconductor module A2, the semiconductor module A21 can suppress variations in the positional relationships of the multiple semiconductor devices B1. Note that in the semiconductor module A21, the first strip portion 711 and the second strip portion 712 of the connecting portion 71 may be integrally formed, and the connecting portion 71 may be a single wide plate material. Also, the first strip portion 711 and the second strip portion 712 of the connecting portion 71 may each be insulating.

[0128] In the first and second embodiments (including their modified examples), examples are shown in which the first connection portion 71A and the second connection portion 71B include a first band-shaped portion 711 and a second band-shaped portion 712, respectively, but each of the first connection portion 71A and the second connection portion 71B may also be configured to include only one of the first band-shaped portion 711 and the second band-shaped portion 712.

[0129] 38 shows a semiconductor module A3 according to the third embodiment. The semiconductor module A3 differs from the semiconductor module A2 in the configuration of the coupling portion 71 (first connection portion 71A and second connection portion 71B). The semiconductor module A3 is attached to the heat sink 80 in the same manner as the semiconductor module A1. In other words, the attachment structure of the semiconductor module A3 is configured in the same manner as the attachment structure C1 of the semiconductor module A1.

[0130] In the coupling portion 71 of the semiconductor module A3, the first connection portion 71A is formed integrally with the sealing portion 50 of the first device B11 and the sealing portion 50 of the second device B12. As shown in FIG. 38 , two third through holes 710 are formed in the first connection portion 71A. The two third through holes 710 penetrate the first connection portion 71A in the thickness direction z. The number of third through holes 710 formed in the first connection portion 71A is not limited to two. Furthermore, the second connection portion 71B is formed integrally with the sealing portion 50 of the second device B12 and the sealing portion 50 of the third device B13. As shown in FIG. 38 , two third through holes 710 are formed in the second connection portion 71B. The two third through holes 710 penetrate the second connection portion 71B in the thickness direction z. The number of third through holes 710 formed in the second connection portion 71B is not limited to two. In the connecting portion 71 of the semiconductor module A3, the first connecting portion 71A and the second connecting portion 71B are each made of the same material as the sealing portion 50 of each semiconductor device B1.

[0131] Like the semiconductor modules A1 and A2, the semiconductor module A3 can suppress variations in the relative positions of the multiple semiconductor devices B1. Furthermore, in the semiconductor module A3, the first connection portion 71A and the second connection portion 71B are integrally formed with the sealing portions 50 of the multiple semiconductor devices B1. This allows the multiple semiconductor devices B1 to be more firmly connected to each other. Furthermore, the first connection portion 71A and the second connection portion 71B are made of the same epoxy resin (an electrically insulating resin material) as the sealing portions 50. This prevents unintended short circuits from occurring among the multiple semiconductor devices B1.

[0132] 39 shows a semiconductor module A4 according to the fourth embodiment. The semiconductor module A4 differs from the semiconductor module A1 in the following respects. First, the third through-holes 710 are not formed in the second strip-shaped portion 712 of the first connection portion 71A (coupling portion 71). Second, the third through-holes 710 are not formed in the second strip-shaped portion 712 of the second connection portion 71B (coupling portion 71). The semiconductor module A4 is mounted to the heat sink 80 in the same manner as the semiconductor module A1. In other words, the mounting structure of the semiconductor module A4 is configured in the same manner as the mounting structure C1 of the semiconductor module A1. However, the mounting structure of the semiconductor module A4 does not include positioning pins 86 inserted into each of the third through-holes 710.

[0133] In the semiconductor module A4, similar to the semiconductor modules A1, A2, and A3, the connecting portion 71 can suppress variations in the positional relationship of the multiple semiconductor devices B1. Furthermore, in the semiconductor module A4, similar to the semiconductor modules A1, A2, and A3, the first through holes 7210 and the second through holes 7220 can suppress misalignment of the semiconductor module A4 with respect to the heat sink 80. Furthermore, in the semiconductor module A4, similar to the semiconductor modules A1, A2, and A3, one of the first through holes 7210 and the second through holes 7220 opens in a perfect circle when viewed in the thickness direction z, and the other opens in an elongated hole when viewed in the thickness direction z. This suppresses rotation and rattle along the x-y plane and suppresses connection failures to the wiring substrate 81.

[0134] 40 shows a semiconductor module A41 according to a first modified example of the fourth embodiment. The semiconductor module A41 differs from the semiconductor module A4 in the following respect. In the semiconductor module A41, a third through-hole 710 is formed in the second strip portion 712 of the first connection portion 71A. Unlike the illustrated example, the third through-hole 710 may be formed in the second strip portion 712 of the second connection portion 71B, rather than in the second strip portion 712 of the first connection portion 71A.

[0135] Like the semiconductor module A4, the semiconductor module A41 has the following advantages. First, the connecting portions 71 can prevent variations in the positional relationships of the multiple semiconductor devices B1. Second, the first through holes 7210 and the second through holes 7220 can prevent misalignment of the semiconductor module A41 with respect to the heat sink 80. Third, because one of the first through holes 7210 and the second through holes 7220 opens in a perfect circle when viewed in the thickness direction z, and the other opens in an elongated hole when viewed in the thickness direction z, rotation and rattle along the x-y plane can be prevented, and poor connection to the wiring substrate 81 can be prevented.

[0136] 41 shows a semiconductor module A42 according to a second modification of the fourth embodiment. The semiconductor module A42 differs from the semiconductor module A4 in the following respect: in the semiconductor module A42, the second strip-shaped portion 712 of each of the first connection portion 71A and the second connection portion 71B (coupling portion 71) has two third through-holes 710a, 710b.

[0137] In each of the first connecting portion 71A and the second connecting portion 71B, two third through holes 710a, 710b each penetrate the second band-shaped portion 712 in the thickness direction z. The two third through holes 710a, 710b are aligned in the first direction x. In the illustrated example, the third through hole 710a opens into an elongated hole in plan view, and the third through hole 710b opens into a perfect circle in plan view. Note that each of the third through holes 710a, 710b may open into either a perfect circle or an elongated hole in plan view.

[0138] The semiconductor module A42 achieves the same effects as the semiconductor modules A4 and A41. Furthermore, in the semiconductor module A42, two third through holes 710a, 710b are formed in the second strip portion 712 of each of the first connecting portion 71A and the second connecting portion 71B. This configuration allows for an increase in the number of positioning pins 86 formed in the heat sink 80, further reducing misalignment of the semiconductor module A42 relative to the heat sink 80. Furthermore, in the semiconductor module A42, the third through hole 710a, like the second through hole 7220, opens into an elongated hole when viewed in the thickness direction z, and the third through hole 710b, like the first through hole 7210, opens into a perfect circle when viewed in the thickness direction z. This configuration allows three semiconductor devices B1 having the same structure to be manufactured by cutting along the cutting line CL shown in FIG. 41 , for example. In other words, in this modification, it is possible to manufacture multiple semiconductor devices B1 as one module (semiconductor module A42), or to manufacture multiple semiconductor devices B1 as individual devices. Therefore, except for the process of cutting along the cutting lines CL, it is possible to standardize the manufacturing method of the semiconductor module A42 and the manufacturing method of the multiple semiconductor devices B1.

[0139] The configuration of the connecting portion 71 (second band portion 712) in the fourth embodiment (including these modifications) can be applied to the semiconductor modules A2 and A3 according to the second and third embodiments. For example, FIG. 42 shows an example in which the second band portion 712 of the semiconductor module 4 is applied to the semiconductor module A2. In this modification, as shown in FIG. 42 , the first band portion 711 is configured similarly to the second band portion 712. That is, in this modification, the third through-hole 710 is not formed in the first band portion 711 of each of the first connecting portion 71A and the second connecting portion 71B.

[0140] The semiconductor module and mounting structure for a semiconductor module according to the present disclosure are not limited to the above-described embodiments. The specific configurations of each part of the semiconductor module and mounting structure for a semiconductor module according to the present disclosure can be freely designed in a variety of ways. The present disclosure includes the embodiments described in Supplementary Notes 1A to 20A below. Supplementary Note 1A: A semiconductor module comprising: a plurality of semiconductor devices, each of which includes a semiconductor element, a sealing portion covering the semiconductor element, and a signal terminal protruding from the sealing portion in a thickness direction of the sealing portion and conducting to the semiconductor element; and a connecting portion connecting the plurality of semiconductor devices; wherein the plurality of semiconductor devices include a first device and a second device adjacent to each other in a first direction perpendicular to the thickness direction; and the connecting portion includes a first connection portion located between the first device and the second device in the first direction and connecting the first device and the second device. Supplementary Note 2A: Appendix 1A. The semiconductor module according to Appendix 1A, further comprising an extension portion that is not conductive to the semiconductor element of each of the plurality of semiconductor devices, wherein the plurality of semiconductor devices include a first outer device located outermost on one side in the first direction and a second outer device located outermost on the other side in the first direction, and the extension portion includes a first extension portion that protrudes from the first outer device to the one side in the first direction and a second extension portion that protrudes from the second outer device to the other side in the first direction. Appendix 3A. The semiconductor module according to Appendix 2A, wherein the first extension portion has a first through hole that penetrates in the thickness direction, and the second extension portion has a second through hole that penetrates in the thickness direction. Appendix 4A. The semiconductor module according to Appendix 3A, wherein one of the first through hole and the second through hole opens in a perfect circle when viewed in the thickness direction, and the other of the first through hole and the second through hole opens into an elongated hole when viewed in the thickness direction. Appendix 5A. The semiconductor module according to claim 3A or 4A, wherein the connecting portion has a third through hole penetrating in the thickness direction.Appendix 6A. The semiconductor module according to any one of Appendix 1A to Appendix 5A, wherein each of the plurality of semiconductor devices further includes a power terminal electrically connected to the semiconductor element, and in each of the plurality of semiconductor devices, the power terminal protrudes from the sealing portion in a second direction perpendicular to the thickness direction and the first direction. Appendix 7A. The semiconductor module according to Appendix 6A, wherein in each of the plurality of semiconductor devices, the semiconductor element includes a first element and a second element, and the power terminal includes a first power terminal electrically connected to the first element and a second power terminal electrically connected to the second element. Appendix 8A. The semiconductor module according to Appendix 7A, wherein each of the plurality of semiconductor devices includes a first mounting portion on which the first element is mounted and a second mounting portion on which the second element is mounted, and in each of the plurality of semiconductor devices, the first mounting portion is located on one side of the second mounting portion in the second direction, and the first power terminal and the second power terminal protrude from the sealing portion to the one side in the second direction. Appendix 9A. The semiconductor module according to Appendix 8A, further comprising a conductive member electrically connecting the second power terminal and the second element, wherein a portion of the conductive member extends, as viewed in the thickness direction, from an edge on one side in the second direction of the first mounting portion to an edge on the other side in the second direction. Appendix 10A. The semiconductor module according to Appendix 9A, wherein the coupling portion is not electrically connected to the semiconductor elements of each of the plurality of semiconductor devices. Appendix 11A. The semiconductor module according to Appendix 10A, wherein the coupling portion is made of a conductive material, and the first connection portion includes a first covering portion covered by the sealing portion of the first device and a second covering portion covered by the sealing portion of the second device. Appendix 12A. The semiconductor module according to Appendix 11A, wherein the first connection portion includes an exposed portion exposed from each of the sealing portion of the first device and the sealing portion of the second device, and the exposed portion is interposed between the first covering portion and the second covering portion in the first direction. Appendix 13A. The semiconductor module according to claim 10A, wherein the connecting portion is made of an insulating material. The semiconductor module according to claim 13A, wherein the connecting portion is integrally formed with the sealing portion of each of the plurality of semiconductor devices.Appendix 15A. The semiconductor module of Appendix 9A, wherein the coupling portion is electrically connected to the semiconductor element of each of the plurality of semiconductor devices, and the first connection portion extends along the first direction and is connected to the second power terminal of the first device and the second power terminal of the second device. Appendix 16A. The semiconductor module of Appendix 9A, wherein the first connection portion includes a first strip-shaped portion and a second strip-shaped portion spaced apart in the second direction, and the first strip-shaped portion is located on the one side in the second direction of the second strip-shaped portion. Appendix 17A. The semiconductor module of Appendix 16A, wherein the second strip-shaped portion is not electrically connected to the semiconductor element of each of the plurality of semiconductor devices, and the second strip-shaped portion overlaps the second mounting portion when viewed in the thickness direction but does not overlap the conductive member when viewed in the thickness direction. Appendix 18A. 19A. The semiconductor module according to any one of Supplements 1A to 18A, wherein the first strip portion is not conductive to the semiconductor elements of each of the plurality of semiconductor devices, the first strip portion overlaps the first mounting portion and the conductive member when viewed in the thickness direction, and is disposed between the first mounting portion and the conductive member in the thickness direction and spaced apart from the first mounting portion and the conductive member. 19A. The semiconductor module according to any one of Supplements 1A to 18A, wherein the plurality of semiconductor devices include a third device disposed on the opposite side of the first device with the second device sandwiched therebetween in the first direction, the second device and the third device being adjacent to each other in the first direction, and the coupling portion includes a second connection portion located between the second device and the third device in the first direction and connecting the second device and the third device. 19B. The semiconductor module according to any one of Supplements 1A to 19A, wherein the semiconductor module is mounted on a heat sink and is in contact with each of the plurality of semiconductor devices.

[0141] Next, fifth to seventh embodiments of the present disclosure will be described with reference to FIGS. 43 to 68. FIGS. 43 to 55 show a semiconductor device B10 according to the fifth embodiment. The semiconductor device B10 includes a support substrate 11, a first conductive layer 121, a second conductive layer 122, a plurality of power terminals, a plurality of signal terminals, a plurality of semiconductor elements 21, a pair of thermistors 22, a first conductive member 31, a second conductive member 32, a plurality of wires, a sealing resin 50, a pair of control wirings 60, and a plate 70. The plurality of power terminals includes a first input terminal 13, an output terminal 14, and a second input terminal 15, and the plurality of signal terminals includes a first signal terminal 161, a second signal terminal 162, a third signal terminal 171, a fourth signal terminal 172, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182, and a seventh signal terminal 19. The plurality of wires includes a plurality of first wires 41 , a plurality of second wires 42 , a plurality of third wires 43 , and a fourth wire 44 .

[0142] For ease of explanation, the thickness direction of the semiconductor device B10 (sealing resin 50) will be referred to as the "thickness direction z." In the following explanation, one side of the thickness direction z may be referred to as the upper side, and the other side as the lower side. Note that terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. Furthermore, "planar view" refers to the view in the thickness direction z. The direction perpendicular to the thickness direction z is referred to as the "first direction x." The direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y."

[0143] The semiconductor device B10 converts a DC power supply voltage applied to the first input terminal 13 and the second input terminal 15 into AC power using the semiconductor element 21. The converted AC power is input from the output terminal 14 to a power supply target such as a motor.

[0144] As shown in FIGS. 51 to 53 , the support substrate 11 is located on the opposite side of the semiconductor elements 21 in the thickness direction z, with the first conductive layer 121 and the second conductive layer 122 sandwiched therebetween. The support substrate 11 supports the first conductive layer 121 and the second conductive layer 122. In the semiconductor device B10, the support substrate 11 is made of a DBC (Direct Bonded Copper) substrate. As shown in FIGS. 51 to 53 , the support substrate 11 includes an insulating layer 111, an intermediate layer 112, and a heat dissipation layer 113. The support substrate 11 is covered with a sealing resin 50 except for a portion of the heat dissipation layer 113.

[0145] As shown in FIGS. 51 to 53 , the insulating layer 111 includes a portion interposed between the intermediate layer 112 and the heat dissipation layer 113 in the thickness direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. The insulating layer 111 is made of, for example, ceramics. The ceramics have a composition containing aluminum nitride (AlN). The insulating layer 111 may be made of an insulating resin sheet in addition to ceramics. The thickness of the insulating layer 111 is thinner than the thickness of each of the first conductive layer 121 and the second conductive layer 122.

[0146] 51 to 53, the intermediate layer 112 is located between the insulating layer 111 and the first and second conductive layers 121 and 122 in the thickness direction z. The intermediate layer 112 includes a pair of regions spaced apart from each other in the first direction x. The composition of the intermediate layer 112 includes copper (Cu). As shown in FIG. 47, the intermediate layer 112 is surrounded by the periphery of the insulating layer 111 in a plan view.

[0147] As shown in Figures 51 to 53, the heat dissipation layer 113 is located on the opposite side of the intermediate layer 112 in the thickness direction z, with the insulating layer 111 sandwiched therebetween. As shown in Figure 49, the heat dissipation layer 113 is exposed from the sealing resin 50. A support member (a heat sink 80 described later) that fixes the semiconductor device B10 is bonded to the heat dissipation layer 113. The heat dissipation layer 113 contains copper. The thickness of the heat dissipation layer 113 is greater than the thickness of the insulating layer 111. In a plan view, the heat dissipation layer 113 is surrounded by the periphery of the insulating layer 111.

[0148] As shown in FIGS. 51 to 53 , the first conductive layer 121 and the second conductive layer 122 are bonded to the support substrate 11. The first conductive layer 121 and the second conductive layer 122 contain copper. The first conductive layer 121 and the second conductive layer 122 are spaced apart in the first direction x. As shown in FIGS. 50 and 51 , the first conductive layer 121 has a first main surface 121A and a first back surface 121B facing opposite sides in the thickness direction z. As shown in FIG. 51 , the first main surface 121A faces some of the multiple semiconductor elements 21 (the multiple first elements 21A described below). As shown in FIG. 52 , the first back surface 121B is bonded to one of a pair of regions of the intermediate layer 112 via a first adhesive layer 123. The first adhesive layer 123 is, for example, a brazing material containing silver (Ag) in its composition. 50 and 51 , the second conductive layer 122 has a second main surface 122A and a second back surface 122B that face opposite each other in the thickness direction z. The second main surface 122A faces the same side as the first main surface 121A in the thickness direction z. As shown in FIG. 51 , the second main surface 122A faces some of the multiple semiconductor elements 21 (multiple second elements 21B, described below). As shown in FIG. 53 , the second back surface 122B is bonded to the other of the pair of regions of the intermediate layer 112 via a first adhesive layer 123.

[0149] As shown in FIGS. 47 and 51 , each of the multiple semiconductor elements 21 is mounted on either the first conductive layer 121 or the second conductive layer 122. Each semiconductor element 21 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, each semiconductor element 21 may be a switching element such as an insulated gate bipolar transistor (IGBT), or a diode. In the description of the semiconductor device B10, each semiconductor element 21 is an n-channel MOSFET with a vertical structure. Each semiconductor element 21 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).

[0150] 47 , in the semiconductor device B10, the multiple semiconductor elements 21 include multiple first elements 21A and multiple second elements 21B. The structure of each of the multiple second elements 21B is the same as the structure of each of the multiple first elements 21A. The multiple first elements 21A are mounted on a first main surface 121A of a first conductive layer 121. The multiple first elements 21A are arranged along the second direction y. The multiple second elements 21B are mounted on a second main surface 122A of a second conductive layer 122. The multiple second elements 21B are arranged along the second direction y.

[0151] 47, 52, and 53, the plurality of semiconductor elements 21 have a first electrode 211, a second electrode 212, a third electrode 213, and a fourth electrode 214. The first electrode 211, the second electrode 212, the third electrode 213, and the fourth electrode 214 described below are common to each semiconductor element 21 unless otherwise specified.

[0152] 52 and 53 , the first electrode 211 faces either the first conductive layer 121 or the second conductive layer 122. A current corresponding to the power before being converted by the semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the semiconductor element 21.

[0153] 52 and 53 , the second electrode 212 is located on the opposite side of the first electrode 211 in the thickness direction z. A current corresponding to the power converted by the semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the semiconductor element 21.

[0154] 52 and 53 , the third electrode 213 is located on the same side as the second electrode 212 in the thickness direction z. A gate voltage for driving the semiconductor element 21 is applied to the third electrode 213. That is, the third electrode 213 corresponds to the gate electrode of the semiconductor element 21. As shown in FIG. 47 , the area of ​​the third electrode 213 is smaller than the area of ​​the second electrode 212 in a plan view.

[0155] 47 , the fourth electrode 214 is located on the same side as the second electrode 212 in the thickness direction z, and is located next to the third electrode 213 in the second direction y. The potential of the fourth electrode 214 is equal to the potential of the second electrode 212.

[0156] As shown in FIGS. 52 and 53 , the conductive bonding layer 23 is interposed between either the first conductive layer 121 or the second conductive layer 122 and the first electrode 211 of one of the multiple semiconductor elements 21. The conductive bonding layer 23 is, for example, solder. Alternatively, the conductive bonding layer 23 may include a sintered body of metal particles. The first electrodes 211 of the multiple first elements 21A are conductively bonded to the first main surface 121A of the first conductive layer 121 via the conductive bonding layer 23. As a result, the first electrodes 211 of the multiple first elements 21A are electrically connected to the first conductive layer 121. The first electrodes 211 of the multiple second elements 21B are conductively bonded to the second main surface 122A of the second conductive layer 122 via the conductive bonding layer 23. As a result, the first electrodes 211 of the multiple second elements 21B are electrically connected to the second conductive layer 122.

[0157] The first input terminal 13, the output terminal 14, and the second input terminal 15 are electrically connected to a plurality of semiconductor elements 21. The first input terminal 13, the output terminal 14, and the second input terminal 15 are power terminals in the semiconductor device B10. The first input terminal 13, the output terminal 14, and the second input terminal 15 each contain copper. The first input terminal 13, the output terminal 14, and the second input terminal 15 may each contain a metal or metal alloy other than copper.

[0158] As shown in FIGS. 45 and 51 , the first input terminal 13 is located on the opposite side of the second conductive layer 122 in the first direction x, with the first conductive layer 121 sandwiched therebetween, and is connected to the first conductive layer 121. This allows the first input terminal 13 to be electrically connected to the first electrodes 211 of the multiple first elements 21A via the first conductive layer 121. The first input terminal 13 is a P terminal (positive electrode) to which a DC power supply voltage to be converted is applied. The first input terminal 13 extends from the first conductive layer 121 in the first direction x. The first input terminal 13 has a covering portion 13A and an exposed portion 13B. As shown in FIG. 51 , the covering portion 13A is connected to the first conductive layer 121 and is covered with a sealing resin 50. The covering portion 13A is flush with the first main surface 121A of the first conductive layer 121. The exposed portion 13B extends from the covered portion 13A in the first direction x and is exposed from the sealing resin 50. The thickness of the first input terminal 13 is thinner than the thickness of the first conductive layer 121.

[0159] As shown in FIGS. 45 and 50 , the output terminal 14 is located on the opposite side of the first conductive layer 121 in the first direction x, with the second conductive layer 122 sandwiched therebetween, and is connected to the second conductive layer 122. This allows the output terminal 14 to be electrically connected to the first electrodes 211 of the plurality of second elements 21B via the second conductive layer 122. AC power converted by the plurality of semiconductor elements 21 is output from the output terminal 14. In the semiconductor device B10, the output terminal 14 includes a pair of regions spaced apart from each other in the second direction y. Alternatively, the output terminal 14 may have a single configuration without a pair of regions. The output terminal 14 includes a covering portion 14A and an exposed portion 14B. As shown in FIG. 50 , the covering portion 14A is connected to the second conductive layer 122 and covered with a sealing resin 50. The covering portion 14A is flush with the second main surface 122A of the second conductive layer 122. The exposed portion 14B extends from the covered portion 14A in the first direction x and is exposed from the sealing resin 50. The thickness of the output terminal 14 is thinner than the thickness of the second conductive layer 122.

[0160] As shown in FIGS. 45 and 50 , the second input terminal 15 is located on the same side as the first input terminal 13 with respect to the first conductive layer 121 and the second conductive layer 122 in the first direction x, but is located away from the first conductive layer 121 and the second conductive layer 122. The second input terminal 15 is electrically connected to the second electrodes 212 of the plurality of second elements 21B. The second input terminal 15 is an N terminal (negative electrode) to which a DC power supply voltage to be converted is applied. The second input terminal 15 includes a pair of regions located away from each other in the second direction y. The first input terminal 13 is located between the pair of regions in the second direction y. The second input terminal 15 has a covering portion 15A and an exposed portion 15B. As shown in FIG. 50 , the covering portion 15A is located away from the first conductive layer 121 and is covered with a sealing resin 50. The exposed portion 15B extends from the covered portion 15A in the first direction x and is exposed from the sealing resin 50.

[0161] The pair of control wirings 60 constitute part of the conductive paths between the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the pair of fifth signal terminals 181, and the pair of sixth signal terminals 182, and the plurality of semiconductor elements 21. As shown in FIGS. 45 to 47 , the pair of control wirings 60 includes a first wiring 601 and a second wiring 602. In the first direction x, the first wiring 601 is located between the plurality of first elements 21A and the first input terminal 13 and the second input terminal 15. The first wiring 601 is bonded to the first main surface 121A of the first conductive layer 121. The first wiring 601 also constitutes part of the conductive path between the seventh signal terminal 19 and the first conductive layer 121. In the first direction x, the second wiring 602 is located between the plurality of second elements 21B and the output terminal 14. The second wiring 602 is joined to the second main surface 122A of the second conductive layer 122. As shown in Figures 52 and 53 , the pair of control wirings 60 has an insulating layer 61, multiple wiring layers 62, a metal layer 63, and multiple sleeves 64. The pair of control wirings 60 is covered with sealing resin 50 except for a portion of each of the multiple sleeves 64.

[0162] 52 and 53 , the insulating layer 61 includes a portion interposed between the plurality of wiring layers 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 is made of, for example, ceramics. The insulating layer 61 may be made of an insulating resin sheet instead of ceramics.

[0163] 52 and 53 , the multiple wiring layers 62 are located on one side of the insulating layer 61 in the thickness direction z. The multiple wiring layers 62 contain copper. As shown in Fig. 47 , the multiple wiring layers 62 include a first wiring layer 621, a second wiring layer 622, a pair of third wiring layers 623, a fourth wiring layer 624, and a fifth wiring layer 625. The pair of third wiring layers 623 are adjacent to each other in the second direction y.

[0164] 52 and 53 , the metal layer 63 is located on the opposite side of the multiple wiring layers 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The metal layer 63 contains copper. The metal layer 63 of the first wiring 601 is bonded to the first main surface 121A of the first conductive layer 121 by a second adhesive layer 68. The metal layer 63 of the second wiring 602 is bonded to the second main surface 122A of the second conductive layer 122 by a second adhesive layer 68. The second adhesive layer 68 is made of a material that may or may not be conductive. The second adhesive layer 68 is, for example, solder.

[0165] As shown in Figures 52 and 53, each of the multiple sleeves 64 is bonded to one of the multiple wiring layers 62 by a third adhesive layer 69. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of the multiple sleeves 64 is conductively bonded to one of the multiple wiring layers 62. As shown in Figures 44 and 51, an end surface 641 corresponding to the other end of the multiple sleeves 64 is exposed from the top surface 51 of the sealing resin 50, which will be described later. The third adhesive layer 69 is conductive. The third adhesive layer 69 is, for example, solder.

[0166] As shown in FIG. 46 , one of the pair of thermistors 22 is conductively joined to a pair of third wiring layers 623 of the first wiring 601. As shown in FIG. 46 , the other of the pair of thermistors 22 is conductively joined to a pair of third wiring layers 623 of the second wiring 602. The pair of thermistors 22 are, for example, NTC (Negative Temperature Coefficient) thermistors. NTC thermistors have the characteristic of gradually decreasing resistance as temperature increases. The pair of thermistors 22 are used as temperature detection sensors for the semiconductor device B10.

[0167] As shown in FIG. 43 , the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the pair of fifth signal terminals 181, the pair of sixth signal terminals 182, and the seventh signal terminal 19 are made of metal pins extending in the thickness direction z. These terminals protrude from the top surface 51 of the sealing resin 50, which will be described later. Furthermore, these terminals are individually press-fitted into the multiple sleeves 64 of the pair of control wires 60. As a result, each of these terminals is supported by one of the multiple sleeves 64 and is electrically connected to one of the multiple wiring layers 62.

[0168] 47 and 52 , the first signal terminal 161 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the first wiring layer 621 of the first wire 601. As a result, the first signal terminal 161 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the first wire 601. Furthermore, the first signal terminal 161 is electrically connected to the third electrodes 213 of the multiple first elements 21A. A gate voltage for driving the multiple first elements 21A is applied to the first signal terminal 161.

[0169] 47 and 53 , the second signal terminal 162 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the first wiring layer 621 of the second wire 602. As a result, the second signal terminal 162 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the second wire 602. Furthermore, the second signal terminal 162 is electrically connected to the third electrodes 213 of the multiple second elements 21B. A gate voltage for driving the multiple second elements 21B is applied to the second signal terminal 162.

[0170] As shown in Fig. 44 , the third signal terminal 171 is located adjacent to the first signal terminal 161 in the second direction y. As shown in Fig. 47 , the third signal terminal 171 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the second wiring layer 622 of the first wire 601. As a result, the third signal terminal 171 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the first wire 601. Furthermore, the third signal terminal 171 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple first elements 21A is applied to the third signal terminal 171.

[0171] As shown in Fig. 44 , the fourth signal terminal 172 is located next to the second signal terminal 162 in the second direction y. As shown in Fig. 47 , the fourth signal terminal 172 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the second wiring layer 622 of the second wire 602. As a result, the fourth signal terminal 172 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the second wire 602. Furthermore, the fourth signal terminal 172 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple second elements 21B is applied to the fourth signal terminal 172.

[0172] As shown in FIG. 44 , the pair of fifth signal terminals 181 are located on the opposite side of the third signal terminal 171 in the second direction y, with the first signal terminal 161 sandwiched therebetween. The pair of fifth signal terminals 181 are adjacent to each other in the second direction y. As shown in FIG. 47 , the pair of fifth signal terminals 181 are individually press-fitted into a pair of sleeves 64, among the multiple sleeves 64 of the pair of control wires 60, that are joined to the pair of third wiring layers 623 of the first wire 601. As a result, the pair of fifth signal terminals 181 are supported by the pair of sleeves 64 and are electrically connected to the pair of third wiring layers 623 of the first wire 601. Furthermore, the pair of fifth signal terminals 181 are electrically connected to the thermistor 22, among the pair of thermistors 22, that is electrically connected to the pair of third wiring layers 623 of the first wire 601.

[0173] As shown in FIG. 44 , the pair of sixth signal terminals 182 are located on the opposite side of the fourth signal terminal 172 in the second direction y, with the second signal terminal 162 sandwiched therebetween. The pair of sixth signal terminals 182 are adjacent to each other in the second direction y. As shown in FIG. 47 , the pair of sixth signal terminals 182 are individually press-fitted into a pair of sleeves 64, among the multiple sleeves 64 of the pair of control wires 60, that are joined to the pair of third wiring layers 623 of the second wire 602. As a result, the pair of sixth signal terminals 182 are supported by the pair of sleeves 64 and are electrically connected to the pair of third wiring layers 623 of the second wire 602. Furthermore, the pair of sixth signal terminals 182 are electrically connected to the thermistor 22, among the pair of thermistors 22, that is electrically connected to the pair of third wiring layers 623 of the second wire 602.

[0174] As shown in Fig. 44 , the seventh signal terminal 19 is located on the opposite side of the first signal terminal 161 in the second direction y, with the third signal terminal 171 sandwiched therebetween. As shown in Fig. 47 , the seventh signal terminal 19 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the fifth wiring layer 625 of the first wire 601. As a result, the seventh signal terminal 19 is supported by the sleeve 64 and is electrically connected to the fifth wiring layer 625 of the first wire 601. Furthermore, the seventh signal terminal 19 is electrically connected to the first conductive layer 121. A voltage equivalent to the DC power input to the first input terminal 13 and the second input terminal 15 is applied to the seventh signal terminal 19.

[0175] As shown in FIG. 47 , the multiple first wires 41 are conductively bonded to the third electrodes 213 of the multiple first elements 21A and the fourth wiring layer 624 of the first wiring 601. As shown in FIG. 47 , the multiple third wires 43 are conductively bonded to the fourth wiring layer 624 of the first wiring 601 and the first wiring layer 621 of the first wiring 601. This allows the first signal terminal 161 to be electrically connected to the third electrodes 213 of the multiple first elements 21A. The composition of the multiple first wires 41 and the multiple third wires 43 includes gold (Au). Alternatively, the composition of the multiple first wires 41 and the multiple third wires 43 may include copper or aluminum.

[0176] Furthermore, as shown in Fig. 47 , the plurality of first wires 41 are conductively joined to the third electrodes 213 of the plurality of second elements 21B and the fourth wiring layer 624 of the second wiring 602. Furthermore, as shown in Fig. 47 , the plurality of third wires 43 are conductively joined to the fourth wiring layer 624 of the second wiring 602 and the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 162 is electrically connected to the third electrodes 213 of the plurality of second elements 21B.

[0177] As shown in FIG. 47 , the multiple second wires 42 are conductively bonded to the fourth electrodes 214 of the multiple first elements 21A and the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 171 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. Furthermore, as shown in FIG. 47 , the multiple second wires 42 are conductively bonded to the fourth electrodes 214 of the multiple second elements 21B and the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 172 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. The composition of the multiple second wires 42 includes gold. Alternatively, the composition of the multiple second wires 42 may include copper or aluminum.

[0178] 47 , the fourth wire 44 is conductively bonded to the fifth wiring layer 625 of the first wiring 601 and the first main surface 121A of the first conductive layer 121. This allows the seventh signal terminal 19 to be electrically connected to the first conductive layer 121. The composition of the fourth wire 44 includes gold. Alternatively, the composition of the fourth wire 44 may include copper or aluminum.

[0179] As shown in Figures 47 and 52, the first conductive member 31 is conductively bonded to the second electrodes 212 of the multiple first elements 21A and the second main surface 122A of the second conductive layer 122. This allows the second electrodes 212 of the multiple first elements 21A to be electrically connected to the second conductive layer 122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in Figure 47, the first conductive member 31 has a main body 311, multiple first joint portions 312, multiple first connecting portions 313, second joint portions 314, and second connecting portions 315.

[0180] The main body portion 311 forms a main portion of the first conductive member 31. As shown in Fig. 47 , the main body portion 311 extends in the second direction y. As shown in Fig. 51 , the main body portion 311 straddles between the first conductive layer 121 and the second conductive layer 122.

[0181] 52, the multiple first bonding portions 312 are individually bonded to the second electrodes 212 of the multiple first elements 21A. Each of the multiple first bonding portions 312 faces the second electrode 212 of one of the multiple first elements 21A.

[0182] 47 , the first coupling portions 313 are connected to the main body portion 311 and the first bonding portions 312. The first coupling portions 313 are spaced apart from one another in the second direction y. As shown in FIG. 51 , when viewed in the second direction y, the first coupling portions 313 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they extend from the first bonding portions 312 toward the main body portion 311.

[0183] 47 and 51 , the second bonding portion 314 is bonded to the second main surface 122A of the second conductive layer 122. The second bonding portion 314 faces the second main surface 122A. The second bonding portion 314 extends in the second direction y.

[0184] 47 and 51 , the second connecting portion 315 is connected to the main body portion 311 and the second bonding portion 314. When viewed in the second direction y, the second connecting portion 315 is inclined in a direction away from the second main surface 122A of the second conductive layer 122 as it extends from the second bonding portion 314 toward the main body portion 311. The dimension of the second connecting portion 315 in the second direction y is equal to the dimension of the second bonding portion 314 in the second direction y.

[0185] 51, 52, and 55, the semiconductor device B10 further includes a first conductive bonding layer 33. The first conductive bonding layer 33 is interposed between the second electrodes 212 of the plurality of first elements 21A and the plurality of first joints 312. The first conductive bonding layer 33 conductively bonds the second electrodes 212 of the plurality of first elements 21A to the plurality of first joints 312. The first conductive bonding layer 33 is, for example, solder. Alternatively, the first conductive bonding layer 33 may include a sintered body of metal particles.

[0186] 51 , the semiconductor device B10 further includes a second conductive bonding layer 34. The second conductive bonding layer 34 is interposed between the second main surface 122A of the second conductive layer 122 and the second bonding portion 314. The second conductive bonding layer 34 conductively bonds the second main surface 122A and the second bonding portion 314. The second conductive bonding layer 34 is, for example, solder. Alternatively, the second conductive bonding layer 34 may include a sintered body of metal particles.

[0187] As shown in FIGS. 46 and 53 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second elements 21B and the covering portion 15A of the second input terminal 15. This electrically connects the second electrodes 212 of the plurality of second elements 21B to the second input terminal 15. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in FIG. 46 , the second conductive member 32 has a pair of main body portions 321, a plurality of third joint portions 322, a plurality of third connecting portions 323, a pair of fourth joint portions 324, a pair of fourth connecting portions 325, a plurality of intermediate portions 326, and a plurality of cross beam portions 327.

[0188] 46 , the pair of main body portions 321 are positioned apart from each other in the second direction y. The pair of main body portions 321 extend in the first direction x. As shown in FIG. 50 , the pair of main body portions 321 are arranged parallel to the first main surface 121A of the first conductive layer 121 and the second main surface 122A of the second conductive layer 122. The pair of main body portions 321 are positioned further away from the first main surface 121A and the second main surface 122A than the main body portion 311 of the first conductive member 31.

[0189] 46 , the intermediate portions 326 are spaced apart from one another in the second direction y and are located between the pair of main body portions 321 in the second direction y. The intermediate portions 326 extend in the first direction x. The dimension of each of the intermediate portions 326 in the first direction x is smaller than the dimension of each of the pair of main body portions 321 in the first direction x.

[0190] 53 , the multiple third joints 322 are individually joined to the second electrodes 212 of the multiple second elements 21B. Each of the multiple third joints 322 faces the second electrode 212 of one of the multiple second elements 21B.

[0191] 46 and 54 , the multiple third connecting portions 323 are connected to both sides of the multiple third joint portions 322 in the second direction y. Furthermore, the multiple third connecting portions 323 are connected to either of the pair of main body portions 321 or the multiple intermediate portions 326. When viewed along the first direction x, each of the multiple third connecting portions 323 is inclined in a direction away from the second main surface 122A of the second conductive layer 122 as it moves from either of the multiple third joint portions 322 to either of the pair of main body portions 321 or the multiple intermediate portions 326.

[0192] 46 and 50, the pair of fourth joint portions 324 are joined to the covering portion 15A of the second input terminal 15. The pair of fourth joint portions 324 face the covering portion 15A.

[0193] 46 and 50 , the pair of fourth connecting portions 325 are connected to the pair of main body portions 321 and the pair of fourth joint portions 324. When viewed in the second direction y, the pair of fourth connecting portions 325 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they move from the pair of fourth joint portions 324 toward the pair of main body portions 321.

[0194] As shown in FIGS. 46 and 55 , the multiple cross beam portions 327 are arranged along the second direction y. In a plan view, the multiple cross beam portions 327 include regions that individually overlap the multiple first joint portions 312 of the first conductive member 31. Of the multiple cross beam portions 327, the cross beam portion 327 located at the center in the second direction y is connected to the multiple intermediate portions 326 on both sides in the second direction y. Of the multiple cross beam portions 327, the remaining two cross beam portions 327 are connected to one of the pair of main body portions 321 and one of the multiple intermediate portions 326 on both sides in the second direction y. When viewed along the first direction x, the multiple cross beam portions 327 are convex in the thickness direction z toward the first main surface 121A of the first conductive layer 121.

[0195] 51 , 53 , and 54 , the semiconductor device B10 further includes a third conductive bonding layer 35. The third conductive bonding layer 35 is interposed between the second electrodes 212 of the plurality of second elements 21B and the plurality of third bonding portions 322. The third conductive bonding layer 35 conductively bonds the second electrodes 212 of the plurality of second elements 21B to the plurality of third bonding portions 322. The third conductive bonding layer 35 is, for example, solder. Alternatively, the third conductive bonding layer 35 may include a sintered body of metal particles.

[0196] 50 , the semiconductor device B10 further includes a fourth conductive bonding layer 36. The fourth conductive bonding layer 36 is interposed between the covering portion 15A of the second input terminal 15 and the pair of fourth joint portions 324. The fourth conductive bonding layer 36 conductively bonds the covering portion 15A and the pair of fourth joint portions 324. The fourth conductive bonding layer 36 is, for example, solder. Alternatively, the fourth conductive bonding layer 36 may include a sintered body of metal particles.

[0197] As shown in Figures 50, 51, 54, and 55, the sealing resin 50 covers the first conductive layer 121, the second conductive layer 122, the plurality of semiconductor elements 21, the first conductive members 31, and the second conductive members 32. The sealing resin 50 also covers a portion of each of the support substrate 11, the first input terminal 13, the output terminal 14, and the second input terminal 15. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. As shown in Figures 44, 48 to 51, the sealing resin 50 has a top surface 51, a bottom surface 52, a plurality of resin side surfaces 53, and a pair of recesses 55.

[0198] 50 and 51 , top surface 51 faces the same side in thickness direction z as first main surface 121A of first conductive layer 121. As shown in Fig. 50 and 51 , bottom surface 52 faces the opposite side in thickness direction z from top surface 51. As shown in Fig. 49 , heat dissipation layer 113 of support substrate 11 is exposed from bottom surface 52.

[0199] The plurality of resin side surfaces 53 are connected to the top surface 51. The plurality of resin side surfaces 53 include a pair of first side surfaces 531 and a pair of second side surfaces 532.

[0200] As shown in Figures 44 and 48, the pair of first side surfaces 531 are spaced apart from each other in the first direction x. The pair of first side surfaces 531 face the first direction x and extend in the second direction y. The pair of first side surfaces 531 are connected to the top surface 51. An exposed portion 13B of the first input terminal 13 and an exposed portion 15B of the second input terminal 15 are exposed from one of the pair of first side surfaces 531. An exposed portion 14B of the output terminal 14 is exposed from the other of the pair of first side surfaces 531.

[0201] 44 and 49 , the pair of second side surfaces 532 are spaced apart from each other in the second direction y. The pair of second side surfaces 532 face opposite each other in the second direction y and extend in the first direction x. The pair of second side surfaces 532 are connected to the top surface 51 and the bottom surface 52.

[0202] 44 and 49 , the pair of recesses 55 are recessed in the first direction x from the first side surfaces 531, on which the exposed portion 13B of the first input terminal 13 and the exposed portion 15B of the second input terminal 15 are exposed. The pair of recesses 55 extend from the top surface 51 to the bottom surface 52 in the thickness direction z. The pair of recesses 55 are located on both sides of the first input terminal 13 in the second direction y.

[0203] The plate 70 is not electrically connected to any of the semiconductor elements 21. In other words, the plate 70 is not electrically connected to any of the semiconductor elements 21. As shown in FIG. 44 , the plate 70 protrudes from one of the resin side surfaces 53. The composition of the plate 70 includes copper, similar to the compositions of the first input terminal 13, the output terminal 14, and the second input terminal 15. The composition of the plate 70 may be a metal or metal alloy other than copper. In other words, in this embodiment, the plate 70 includes a metal material.

[0204] The plate 70 includes a first plate 71 and two second plates 72. As shown in Figures 44 and 45, the first plate 71 protrudes from one of the pair of second side surfaces 532. Each of the two second plates 72 protrudes from the other of the pair of second side surfaces 532.

[0205] The first plate 71 is disposed on one side in the second direction y with respect to the first conductive layer 121 and the second conductive layer 122. The first plate 71 includes a first covered portion 711 and a first exposed portion 712.

[0206] 45 and 54 , the first covering portion 711 is covered with sealing resin 50. As a result, the first plate 71 is supported by the sealing resin 50. The upper surface of the first covering portion 711 (the surface facing upward in the thickness direction z) is located at the same position as the first main surface 121A in the thickness direction z.

[0207] As shown in FIGS. 45 and 54 , the first exposed portion 712 is exposed from the sealing resin 50. The first exposed portion 712 has a first root portion 712a, a first bent portion 712b, and a first mounting portion 712c. The first root portion 712a is connected to the first covering portion 711. The first root portion 712a is located on one side of the first covering portion 711 in the first direction x. The first root portion 712a is parallel to a plane (x-y plane) perpendicular to the thickness direction z. In the illustrated example, the first root portion 712a is positioned at the same height in the thickness direction z as the exposed portion 13B of the first input terminal 13, the exposed portions 14B of the output terminal 14, and the exposed portions 15B of the second input terminal 15. The first mounting portion 712c is located below the first root portion 712a in the thickness direction z. The first mounting portion 712c is parallel to the xy plane. The first mounting portion 712c is a portion used when fixing the semiconductor device B10 to a support member (a heat sink 80, described below). In the illustrated example, the lower surface of the first mounting portion 712c (the surface facing downward in the thickness direction z) is flush with the bottom surface 52. The first bent portion 712b is interposed between the first root portion 712a and the first mounting portion 712c. The first bent portion 712b bends downward in the thickness direction z (toward the bottom surface 52) from the first root portion 712a and connects to the first mounting portion 712c.

[0208] As shown in FIGS. 44 , 45 , and 54 , the first exposed portion 712 has a first through-hole 712d. The first through-hole 712d penetrates the first plate 71 in the thickness direction z. The first through-hole 712d is formed in the first mounting portion 712c of the first exposed portion 712. The first through-hole 712d is a perfect circle in a plan view (when viewed in the thickness direction z). In this disclosure, unless otherwise specified, the term "perfect circle" not only refers to a perfectly circular shape, but also includes cases where distortion occurs due to errors (manufacturing errors) during the manufacturing of the semiconductor device B10.

[0209] Each of the two second plates 72 is disposed on the other side in the second direction y with respect to the first conductive layer 121 and the second conductive layer 122. Each of the two second plates 72 includes a second covering portion 721 and a second exposed portion 722. The second covering portion 721 and the second exposed portion 722 described below are common to each second plate 72 unless otherwise specified.

[0210] 45 , 54 , and 55 , the second covering portion 721 is covered with the sealing resin 50. This causes the second plate 72 to be supported by the sealing resin 50. The upper surface (the surface facing upward in the thickness direction z) of the second covering portion 721 is located at the same position as the second main surface 122A in the thickness direction z.

[0211] As shown in FIGS. 44, 45, 54, and 55, the second exposed portion 722 is exposed from the sealing resin 50. The second exposed portion 722 has a second root portion 722a, a second bent portion 722b, and a second mounting portion 722c. The second root portion 722a is connected to the second covering portion 721. The second root portion 722a is located on the other side of the second covering portion 721 in the first direction x. The second root portion 722a is parallel to the xy plane. In the illustrated example, the second root portion 722a is disposed at the same height in the thickness direction z as the exposed portion 13B of the first input terminal 13, the exposed portions 14B of the output terminal 14, and the exposed portions 15B of the second input terminal 15. The second mounting portion 722c is located below the second root portion 722a in the thickness direction z. The second mounting portion 722c is parallel to the xy plane. The second mounting portion 722c is a portion used when fixing the semiconductor device B10 to a support member (a heat sink 80, described below). In the illustrated example, the lower surface of the second mounting portion 722c (the surface facing downward in the thickness direction z) is flush with the bottom surface 52. The second bent portion 722b is interposed between the second root portion 722a and the second mounting portion 722c. The second bent portion 722b bends downward in the thickness direction z (toward the bottom surface 52) from the second root portion 722a and connects to the second mounting portion 722c.

[0212] In each second plate 72, the second exposed portion 722 has a second through hole 722d, as shown in FIGS. 44, 45, and 54. The second through hole 722d described below is common to all second plates 72 unless otherwise specified. The second through hole 722d penetrates the second plate 72 in the thickness direction z. The second through hole 722d is formed in the second mounting portion 722c of the second exposed portion 722. The second through hole 722d is an elongated hole in plan view (as viewed in the thickness direction z). In this embodiment, the second through hole 722d has a longitudinal direction in the second direction y, but the longitudinal direction may also be the first direction x. Unlike this example, the second through hole 722d may be a perfect circle in plan view.

[0213] 44 and 45 , in the semiconductor device B10, each of the two second exposed portions 722 is offset in the first direction x with respect to the first exposed portion 712 when viewed along the second direction y. As shown in FIG. 44 , the two second exposed portions 722 are arranged with a gap in the first direction x. The first exposed portion 712 overlaps the gap between the two second exposed portions 722 when viewed along the second direction y. The dimension d1 of the gap along the first direction x (i.e., the separation distance between the two second exposed portions 722) is greater than the dimension of the first exposed portions 712 along the first direction x.

[0214] Next, a semiconductor module A10 of the present disclosure will be described with reference to Figures 56 to 58. The semiconductor module A10 includes a plurality of semiconductor devices B10, a heat sink 80, a plurality of wiring boards 81, a plurality of supports 85, and a plurality of fixtures 891, 892. The semiconductor module A10 is used, for example, in an inverter for driving a three-phase AC motor.

[0215] As shown in FIGS. 56 and 57 , the heat sink 80 supports the multiple semiconductor devices B10. The heat sink 80 is located on the opposite side of the multiple semiconductor devices B10 from the first signal terminals 161 and second signal terminals 162 with respect to the multiple semiconductor elements 21 of the multiple semiconductor devices B10. Therefore, the heat sink 80 faces the heat dissipation layers 113 of the multiple semiconductor devices B10. The heat sink 80 is made of a material containing aluminum, for example. As shown in FIG. 56 , the multiple semiconductor devices B10 are arranged on the heat sink 80 along the second direction y. In this case, between the sealing resins 50 of two semiconductor devices B10 adjacent in the second direction y, the first mounting portion 712c of the first plate 71 is interposed between the second mounting portions 722c of the two second plates 72.

[0216] As shown in FIGS. 56 and 57 , each of the multiple wiring substrates 81 is individually provided for each of the multiple semiconductor devices B10. As can be seen from FIGS. 56 and 57 , the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the pair of fifth signal terminals 181, the pair of sixth signal terminals 182, and the seventh signal terminal 19 of the corresponding semiconductor device B10 are inserted into each of the multiple wiring substrates 81, respectively, and are electrically connected to these terminals. Each of the multiple wiring substrates 81 is a gate driver that controls the driving of each semiconductor element 21 of the corresponding semiconductor device B10. Each of the multiple wiring substrates 81 faces the top surface 51 of the sealing resin 50 of the corresponding semiconductor device B10. The multiple wiring substrates 81 are located on the opposite side of the heat sink 80 from the multiple semiconductor elements 21 of the multiple semiconductor devices B10. In a plan view, the multiple wiring substrates 81 individually overlap the sealing resin 50 of the multiple semiconductor devices B10.

[0217] 58 , each of the multiple wiring boards 81 has a substrate 811, main wiring 812, back wiring 813, and internal wiring 814. The substrate 811 is provided with multiple through holes 811A that penetrate in the thickness direction z. The main wiring 812 is arranged on one side of the substrate 811 in the thickness direction z (the side opposite the semiconductor device B10 in the thickness direction z). The internal wiring 814 is arranged on the inner surface of the multiple through holes 811A. The internal wiring 814 is connected to the main wiring 812 and the back wiring 813. The main wiring 812 forms a path for mutual conduction between the internal wiring 814 and a circuit provided on any of the multiple wiring boards 81.

[0218] In each of the plurality of semiconductor devices B10, the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the fifth signal terminal 181, the sixth signal terminal 182, and the seventh signal terminal 19 are each inserted into a plurality of through holes 811A of a corresponding one of the plurality of wiring substrates 81. Figure 58 shows a state in which the first signal terminal 161 is inserted into the through hole 811A of the substrate 811 in a corresponding one of the plurality of semiconductor devices B10 and the plurality of wiring substrates 81. Below, with reference to Figure 58, the first signal terminal 161 and the through hole 811A will be described as an example, but the same applies to the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the fifth signal terminal 181, the sixth signal terminal 182, and the seventh signal terminal 19.

[0219] 58 , each of the first signal terminals 161 of the plurality of semiconductor devices B10 has a base 161A and a bulge 161B. One side of the base 161A in the thickness direction z is press-fitted into one of the plurality of sleeves 64 of the plurality of semiconductor devices B10. The bulge 161B is provided on the other side of the base 161A in the thickness direction z. The bulge 161B bulges in a direction perpendicular to the thickness direction z.

[0220] 58 , each of the first signal terminals 161 of the plurality of semiconductor devices B10 is press-fitted into one of the plurality of through holes 811A of the plurality of wiring boards 81. As a result, the internal wiring 814 arranged in one of the plurality of through holes 811A is pressure-welded to the bulging portion 161B of the first signal terminal 161. Therefore, by being press-fitted into one of the plurality of wiring boards 81 in the thickness direction z, each of the first signal terminals 161 of the plurality of semiconductor devices B10 is electrically connected to that wiring board 81.

[0221] As shown in FIG. 57 , the multiple support pillars 85 are located between the heat sink 80 and the multiple wiring substrates 81 in the thickness direction z. Unlike the illustrated example, the multiple support pillars 85 may be located between the sealing resin 50 and the wiring substrates 81. The multiple wiring substrates 81 are supported by the multiple support pillars 85. In the illustrated example, four support pillars 85 are arranged for each wiring substrate 81, and the four support pillars 85 support the four corners of the wiring substrate 81. As shown in FIG. 43 , in a plan view, the multiple support pillars 85 are located away from the top surface 51 of the sealing resin 50 of the multiple semiconductor devices B10.

[0222] The multiple fasteners 891, 892 are used to fasten the multiple semiconductor devices B10 to the heat sink 80. In this embodiment, the multiple fasteners 891, 892 are, for example, screws. Each of the multiple fasteners 891, 892 is fastened to a female-threaded hole formed in the heat sink 80. Each of the multiple fasteners 891 is inserted into a corresponding first through-hole 712d of the multiple first plates 71. Each of the multiple fasteners 892 is inserted into a corresponding second through-hole 722d of the multiple second plates 72.

[0223] The functions and effects of the semiconductor device B10 and the semiconductor module A10 are as follows.

[0224] The semiconductor device B10 includes a plate 70 that is not electrically connected to the semiconductor element 21. The plate 70 protrudes from one of the resin side surfaces 53 of the sealing resin 50. This configuration allows the plate 70 to be used to secure the semiconductor device B10 to a support member (e.g., a circuit board, a heat sink 80, a housing or frame of an electronic device, etc.) that supports the semiconductor device B10. In other words, the plate 70 is used for attachment when securing the semiconductor device B10 to the aforementioned support member. A configuration different from the semiconductor device B10 that does not include the plate 70 requires a separate attachment member (e.g., a leaf spring) to press the bottom surface 52 of the sealing resin 50 against the aforementioned support member. In this configuration, the semiconductor device without the plate 70 must be secured to the support member while aligning the relative positions of the semiconductor device, the support member, and the attachment member (leaf spring). Therefore, positioning the semiconductor device relative to the support member is difficult. In contrast, the semiconductor device B10 can be secured using the integrally formed plate 70, which facilitates positioning the semiconductor device B10 relative to the aforementioned support member. Therefore, the semiconductor device B10 can be easily fixed to the support member described above.

[0225] In the semiconductor device B10, the plate 70 includes a first plate 71 and a second plate 72. The first plate 71 protrudes from one of the pair of second side surfaces 532, and the second plate 72 protrudes from the other of the pair of second side surfaces 532. With this configuration, the semiconductor device B10 can be fixed to the aforementioned support member (e.g., the heat sink 80) on both sides of the sealing resin 50 in the second direction y. Therefore, the semiconductor device B10 can be more stably fixed to the aforementioned support member. In particular, in the semiconductor device B10, the plate 70 includes one first plate 71 and two second plates 72. With this configuration, the semiconductor device B10 is fixed to the aforementioned support member (e.g., the heat sink 80) at three points, thereby enabling more reliable fixation and suppressing rotation of the semiconductor device B10 about an axis in the thickness direction z.

[0226] In the semiconductor device B10, the first plate 71 and the second plate 72 are offset from each other in the first direction x. With this configuration, when a plurality of semiconductor devices B10 are arranged in the second direction y in the semiconductor module A10, as shown in FIG. 56 , at least a portion of the first plate 71 of one of two semiconductor devices B10 adjacent to each other in the first direction x (the first mounting portion 712c in the semiconductor device B10) and at least a portion of the second plate 72 of the other of the two semiconductor devices B10 (the second mounting portion 722c in the semiconductor device B10) can be arranged along the first direction x. Therefore, the semiconductor device B10 of the present disclosure can reduce the size (space) of the semiconductor module A10 in the second direction y.

[0227] In the semiconductor device B10, the first exposed portion 712 overlaps the gap between the two second exposed portions 722 when viewed along the second direction y, and the dimension of the gap along the first direction x is larger than the dimension of the first exposed portion 712 along the first direction x. With this configuration, as described above, the semiconductor device B10 can be fixed at three points, and at least a portion of the first plate 71 of one of two semiconductor devices B10 adjacent in the first direction x (the first mounting portion 712c in the semiconductor device B10) can be disposed between at least a portion of the two second plates 72 of the other of the two semiconductor devices B10 (the second mounting portions 722c in the semiconductor device B10). In other words, in the semiconductor module A10, the semiconductor device B10 is reliably fixed to the heat sink 80, and the semiconductor module A10 can be made smaller in size in the second direction y.

[0228] In the semiconductor device B10, the first exposed portion 712 of the first plate 71 has a first through-hole 712d, and the second exposed portion 722 of the second plate 72 has a second through-hole 722d. The first through-hole 712d is a perfect circle when viewed in the thickness direction z, and the second through-hole 722d is an elongated hole when viewed in the thickness direction z. This configuration suppresses rotation of the semiconductor device B10 about an axis in the thickness direction z while suppressing wobble of the semiconductor device B10 along the x-y plane when positioning the semiconductor device B10 relative to the support member (e.g., the heat sink 80) during fixation of the semiconductor device B10. Fixation of the semiconductor device B10 in the semiconductor module A10 is performed by inserting a fastener 891 into the first through-hole 712d to fix the first plate 71 to the heat sink 80, and inserting a fastener 892 into the second through-hole 722d to fix the second plate 72 to the heat sink 80. In the semiconductor device B10, if the first through-hole 712d and one of the two second through-holes 722d are perfectly round and the others are elongated holes, rotation and rattle of the semiconductor device B10 can be suppressed.

[0229] In the semiconductor device B10, a plurality of signal terminals (first signal terminal 161, second signal terminal 162, third signal terminal 171, fourth signal terminal 172, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182, and seventh signal terminal 19) extend upward in the thickness direction z from the top surface 51 of the sealing resin 50. In the semiconductor module A10, the plurality of signal terminals are inserted into the wiring board 81. In this configuration, if the semiconductor device B10 is not properly fixed in a predetermined position on the heat sink 80, the plurality of signal terminals cannot be inserted into the wiring board 81. On the other hand, in the semiconductor device B10 of the present disclosure, positioning on the heat sink 80 is easy, and therefore the semiconductor device B10 can be properly fixed in a predetermined position on the heat sink 80. In other words, the semiconductor module A10 can properly establish electrical continuity between the multiple signal terminals (first signal terminal 161, second signal terminal 162, third signal terminal 171, fourth signal terminal 172, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182, and the seventh signal terminal 19) of the semiconductor device B10 and the wiring board 81.

[0230] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0231] 59 shows a semiconductor device B11 according to a first modification of the fifth embodiment. The semiconductor device B11 has a smaller number of second plates 72 than the semiconductor device B10. Therefore, the plate 70 of the semiconductor device B11 includes one first plate 71 and one second plate 72.

[0232] 59 , the first plate 71 of the semiconductor device B11 is located on the side where the first input terminal 13 and the second input terminal 15 protrude from the center of the sealing resin 50 in the first direction x. Furthermore, the second plate 72 of the semiconductor device B11 is located on the side where the output terminal 14 protrudes from the center of the sealing resin 50 in the first direction x. In the illustrated example, the first exposed portion 712 and the second exposed portion 722 are offset in the first direction x when viewed in the second direction y. Unlike this example, the first exposed portion 712 and the second exposed portion 722 do not have to be offset in the first direction x when viewed in the second direction y. In this case, the first plate 71 and the second plate 72 may protrude from the center in the first direction x of the corresponding second side surface 532 of the pair of second side surfaces 532, or may be closer to either side in the first direction x than the center in the first direction x of the corresponding second side surface 532 of the pair of second side surfaces 532. However, as described above, in order to reduce the size of the semiconductor module A10 in the first direction x, it is preferable that the first exposed portion 712 and the second exposed portion 722 are offset in the first direction x when viewed in the second direction y.

[0233] According to the semiconductor device B11, like the semiconductor device B10, it is easy to fix the semiconductor device B11 to a support member (for example, the heat sink 80) on which the semiconductor device B11 is mounted.

[0234] 60 shows a semiconductor device B12 according to a second modification of the fifth embodiment. The semiconductor device B12 differs from the semiconductor device B10 in the following respect: the first covering portion 711 of the first plate 71 and the second covering portion 721 of each second plate 72 extend to a position where they overlap the support substrate 11 in a plan view.

[0235] 60 , the first covering portion 711 is located in the thickness direction z between the main body portion 321 of the second conductive member 32 and the first and second conductive layers 121 and 122. This allows the tip of the first covering portion 711 (the end opposite to the side connected to the first exposed portion 712) to extend upward in the thickness direction z above the first and second conductive layers 121 and 122 without interfering with the first and second conductive layers 121 and 122.

[0236] 60 , each of the two second covering portions 721 is located between the main body portion 321 of the second conductive member 32 and the first conductive layer 121 or the second conductive layer 122 in the thickness direction z. This allows the tip of each second covering portion 721 (the end opposite to the side connected to the second exposed portion 722) to extend upward in the thickness direction z above the first conductive layer 121 and the second conductive layer 122 without interfering with the first conductive layer 121 or the second conductive layer 122. Therefore, the second covering portion 721 of the semiconductor device B11 is covered with the sealing resin 50 over a wider area than the second covering portion 721 of the semiconductor device B10.

[0237] The semiconductor device B12, like the semiconductor device B10, can be easily fixed to a support member (e.g., a heat sink 80) to which the semiconductor device B12 is attached. Furthermore, the first covering portion 711 of the semiconductor device B12 is covered with the sealing resin 50 over a larger area than the first covering portion 711 of the semiconductor device B10. In the semiconductor device B12, the first covering portion 711 is covered with the sealing resin 50, and therefore the first plate 71 is supported by the sealing resin 50. In this configuration, when the semiconductor device B12 is fixed to the heat sink 80, stress is generated in the sealing resin 50 by the first covering portion 711. In the semiconductor device B12, the area covered by the sealing resin 50 of the first covering portion 711 is larger than in the semiconductor device B10, so stress concentration in the sealing resin 50 is alleviated, and damage to the sealing resin 50 can be suppressed. The same applies to each second plate 72. In other words, in semiconductor device B12, the area of ​​the second covering portion 721 covered by the sealing resin 50 is larger than in semiconductor device B10, so stress concentration on the sealing resin 50 is alleviated and damage to the sealing resin 50 can be suppressed.

[0238] 61 shows a semiconductor device B13 according to a third modified example of the fifth embodiment. The semiconductor device B13 differs from the semiconductor device B10 in the following respects. The first mounting portion 712c of the first plate 71 is located higher in the thickness direction z than the bottom surface 52 of the sealing resin 50. Furthermore, the second mounting portion 722c of each second plate 72 is located higher in the thickness direction z than the bottom surface 52 of the sealing resin 50.

[0239] Similar to the semiconductor device B10, the semiconductor device B13 can be easily fixed to a support member (e.g., a heat sink 80) to which the semiconductor device B13 is attached. Furthermore, in the semiconductor device B13, the first mounting portion 712c of the first plate 71 and the second mounting portions 722c of each second plate 72 are located above the bottom surface 52 in the thickness direction z. As a result, when the semiconductor device B13 is fixed to the heat sink 80, the elastic force of the first plate 71 and each second plate 72 increases the force pressing the semiconductor device B13 against the heat sink 80. This improves the adhesion between the semiconductor device B13 and the heat sink 80, thereby improving heat transfer from the semiconductor device B13 to the heat sink 80.

[0240] 62 shows a semiconductor device B14 according to a fourth modified example of the fifth embodiment. The semiconductor device B14 differs from the semiconductor device B10 in the following respects: the first covering portion 711 of the first plate 71 includes a pair of protrusions 711a, and the second covering portion 721 of each second plate 72 includes a pair of protrusions 721a.

[0241] The pair of protrusions 711a are formed on the tip of the first covering portion 711 (the end opposite to the side connected to the first exposed portion 712). In a plan view, the pair of protrusions 711a protrude from both sides of the first covering portion 711 in the first direction x. Unlike the example shown in the drawings, the first covering portion 711 may be configured to include only one of the pair of protrusions 711a.

[0242] The pair of protrusions 721a are formed on the tip (the end opposite to the side connected to the second exposed portion 722) of each second covering portion 721. In a plan view, the pair of protrusions 721a protrude from both sides of the second covering portion 721 in the first direction x. Note that, unlike the example shown in the figure, the second covering portion 721 may be configured to include only one of the pair of protrusions 721a.

[0243] Similar to the semiconductor device B10, the semiconductor device B14 can be easily fixed to a support member (e.g., a heat sink 80) to which the semiconductor device B14 is attached. Furthermore, in the semiconductor device B14, the pair of protrusions 711a can prevent the first plate 71 from coming off the sealing resin 50. Furthermore, in the semiconductor device B14, the pair of protrusions 721a can prevent each second plate 72 from coming off the sealing resin 50.

[0244] 63 shows a semiconductor device B15 according to a fifth modification of the fifth embodiment. The semiconductor device B15 differs from the semiconductor device B14 in the following respects: the positions of the pair of protrusions 711a on the first plate 71 are different; and the positions of the pair of protrusions 721a on each second plate 72 are different.

[0245] In the first plate 71 of the semiconductor device B15, the pair of protrusions 711a do not protrude from both sides of the first covering portion 711 in the first direction x, but protrude from both sides of the first covering portion 711 in the thickness direction z. Note that, in the semiconductor device B15 as well, as in the semiconductor device B14, the first covering portion 711 may be configured to include only one of the pair of protrusions 711a. Also, in each second plate 72, the pair of protrusions 721a do not protrude from both sides of the second covering portion 721 in the first direction x, but protrude from both sides of the second covering portion 721 in the thickness direction z. Note that, in the semiconductor device B15 as well, as in the semiconductor device B14, the second covering portion 721 may be configured to include only one of the pair of protrusions 721a.

[0246] The semiconductor device B15 can be easily fixed to a support member (e.g., a heat sink 80) to which the semiconductor device B15 is attached, similarly to the semiconductor device B10. Furthermore, the semiconductor device B15 can prevent the first plate 71 and each second plate 72 from coming out of the sealing resin 50, similarly to the semiconductor device B14.

[0247] 64 to 66 show a semiconductor device B20 according to the sixth embodiment. The semiconductor device B20 differs from the semiconductor device B10 in the following respect: a first plate 71 and two second plates 72 are connected to each other inside the sealing resin 50.

[0248] In this embodiment, the first plate 71 and the two second plates 72 are connected to each other, so the plate 70 is made of a single metal member. As shown in Figures 64 to 66, the plate 70 is disposed above the first conductive member 31 and the second conductive member 32 in the thickness direction z.

[0249] Similar to the semiconductor device B10, the semiconductor device B20 can be easily fixed to a support member (e.g., a heat sink 80) to which the semiconductor device B20 is attached. Therefore, in the semiconductor device of the present disclosure, there is no limitation as to whether the first plate 71 and each second plate 72 of the plate 70 are separate from each other or integral with each other.

[0250] In the semiconductor device B20, the first plate 71 and the two second plates 72 are connected to each other and formed integrally. This configuration can prevent the plates 70 from coming off the sealing resin 50.

[0251] 67 and 68 show a semiconductor device B30 according to the seventh embodiment. The semiconductor device B30 differs from the semiconductor device B10 in the following respect: the plates 70 (first plate 71 and each second plate 72) of the semiconductor device B30 are insulating.

[0252] In this embodiment, the first plate 71 and the two second plates 72 each contain an insulating material. The insulating material is, for example, polycarbonate or glass epoxy resin. The insulating material is not limited to these examples and may be any material that has adequate insulating properties and adequate strength for fixing the semiconductor device B30 to a support member (for example, the heat sink 80).

[0253] 67 and 68 , the second covering portion 721 of one of the two second plates 72 is adhered to the first main surface 121A of the first conductive layer 121 and the second main surface 122A of the second conductive layer 122. As can be seen from FIGS.

[0254] Similar to the semiconductor device B10, the semiconductor device B30 can be easily fixed to a support member (for example, a heat sink 80) to which the semiconductor device B30 is attached. Therefore, in the semiconductor device of the present disclosure, there is no limitation as to whether the plates 70 (the first plate 71 and each second plate 72) are conductive or insulating.

[0255] In the semiconductor device B30, the first covering portion 711 of the first plate 71 is bonded to the first main surface 121A of the first conductive layer 121 and the second main surface 122A of the second conductive layer 122. This configuration prevents the first plate 71 from coming off the sealing resin 50. Furthermore, when the semiconductor device B30 is fixed to the heat sink 80, stress from the first covering portion 711 to the sealing resin 50 is alleviated. Similarly, the second covering portion 721 of each second plate 72 is bonded to either the first main surface 121A of the first conductive layer 121 or the second main surface 122A of the second conductive layer 122. This configuration prevents the second plates 72 from coming off the sealing resin 50. Furthermore, when the semiconductor device B30 is fixed to the heat sink 80, stress from the second covering portion 721 to the sealing resin 50 is alleviated.

[0256] Although the semiconductor device B30 has been described as an example in which the first plate 71 and the two second plates 72 are separated from each other, this is not limiting, and the first plate 71 and the two second plates 72 may be integrally formed, as in the semiconductor device B20. That is, in the semiconductor device B20, the plate 70 may be configured to include an insulating material rather than a metal material. In this example, the plate 70 may be positioned so as to pass between the first conductive layer 121, the second conductive layer 122, the first conductive member 31, and the second conductive member 32, rather than being positioned above the first conductive member 31 and the second conductive member 32 in the thickness direction z. In this case, since the plate 70 is insulating, it may or may not contact the first conductive layer 121, the second conductive layer 122, the first conductive member 31, and the second conductive member 32.

[0257] The semiconductor device and semiconductor module according to the present disclosure are not limited to the above-described embodiments. The specific configurations of each part of the semiconductor device and semiconductor module according to the present disclosure can be freely designed in various ways. The present disclosure includes the embodiments described in Supplementary Notes 1B to 16B below. Supplementary Note 1B. A semiconductor device comprising: a semiconductor element; a sealing resin covering the semiconductor element; a terminal electrically connected to the semiconductor element; and a plate not electrically connected to the semiconductor element, wherein the sealing resin has a top surface and a bottom surface facing opposite each other in a thickness direction of the sealing resin, and a plurality of resin side surfaces each connected to the top surface, the terminals protruding from the sealing resin, and the plate protruding from any of the plurality of resin side surfaces. Supplementary Note 2B. The semiconductor device according to Appendix 1B, wherein the plurality of resin side surfaces include a pair of first side surfaces facing opposite each other in a first direction orthogonal to the thickness direction and a pair of second side surfaces facing opposite each other in a second direction orthogonal to the thickness direction and the first direction, the terminal includes a power terminal protruding from one of the pair of first side surfaces, and the plate protruding from at least one of the pair of second side surfaces. Appendix 3B. The semiconductor device according to Appendix 2B, wherein the plate includes a first plate protruding from one of the pair of second side surfaces and a second plate protruding from the other of the pair of second side surfaces, the first plate includes a first covering portion covered by the sealing resin and a first exposed portion exposed from the sealing resin, and the second plate includes a second covering portion covered by the sealing resin and at least one second exposed portion exposed from the sealing resin. Appendix 4B. The semiconductor device according to Appendix 3B, wherein the first exposed portion and each of the at least one second exposed portion are offset from each other in the first direction when viewed along the second direction. Appendix 5B. The semiconductor device according to Appendix 4B, wherein the at least one second exposed portion includes two second exposed portions, and the two second exposed portions extend in the second direction from the other of the pair of second side surfaces when viewed in the thickness direction and are arranged with a gap in between in the first direction.Appendix 6B. The semiconductor device according to Appendix 5B, wherein the first exposed portion overlaps the gap when viewed along the second direction, and a dimension of the gap along the first direction is larger than a dimension of the first exposed portion along the first direction. Appendix 7B. The semiconductor device according to any one of Appendixes 3B to 6B, wherein the first exposed portion has a first through hole penetrating in the thickness direction, and each of the at least one second exposed portion has a second through hole penetrating in the thickness direction. Appendix 8B. The semiconductor device according to Appendix 7B, wherein the first through hole is a perfect circle when viewed in the thickness direction, and the second through hole is an elongated hole when viewed in the thickness direction. Appendix 9B. The semiconductor device according to any one of Appendixes 3B to 8B, wherein the first plate and the second plate are disposed apart from each other. Appendix 10B. The semiconductor device according to any one of Appendixes 3B to 8B, wherein the first plate and the second plate are connected inside the sealing resin. Appendix 11B. The semiconductor device according to any one of Supplementary Notes 1B to 10B, wherein the plate includes a metal material.Supplementary Note 12B. The semiconductor device according to any one of Supplementary Notes 1B to 10B, wherein the plate includes an insulating material.Supplementary Note 13B. The semiconductor device according to any one of Supplementary Notes 1B to 12B, wherein the plate includes a bent portion and an attachment portion in a portion protruding from the sealing resin, the bent portion bent toward the bottom surface in the thickness direction, and the attachment portion is located closer to the top surface than the bottom surface in the thickness direction.Supplementary Note 14B. The semiconductor device according to any one of Supplementary Notes 1B to 13B, wherein the terminals include signal terminals protruding from the top surface in the thickness direction.Supplementary Note 15B. The semiconductor device according to any one of Supplementary Notes 1B to 14B, further comprising a support substrate supporting the semiconductor element, the support substrate being exposed from the bottom surface.Supplementary Note 16B. A semiconductor module comprising: the semiconductor device according to any one of Supplementary Note 1B to Supplementary Note 15B; and a heat sink in contact with the bottom surface, wherein the plate is fixed to the heat sink.

[0258] (Symbols used in FIGS. 1 to 42) A1, A11, A12, A2, A21, A3: Semiconductor module B1: Semiconductor device B11: First device B12: Second device B13: Third device B21: First outer device B22: Second outer device C1, C11: Mounting structure 11: Support substrate 111: Insulating layer 112: First wiring layer 1121: First mounting portion 1122: Second mounting portion 113: Second wiring layer 13: Power terminal 14: First power terminal 15: Second power terminal 16: Third power terminal 17: Signal terminal 170A: Base 170B: Bulging portion 171: First signal terminal 172: Second signal terminal 173: Third signal terminal 174: Fourth signal terminal 181: Fifth signal terminal 182: Sixth signal terminal 21: Semiconductor element 21A: First element 21B: Second element 211: First electrode 212: Second electrode 213: Third electrode 214: Fourth electrode 22: Thermistor 23: Conductive bonding layer 31: First conductive member 310: Through hole 311: Main body portion 312: First bonding portion 313: Second bonding portion 314: Second bonding portion 32: Second conductive member 321: Main body portion 322: Third bonding portion 324: Fourth bonding portion 326: Intermediate portion 327: Horizontal beam portion 328: Hanging portion 33: First conductive bonding layer 34: Second conductive bonding layer 35: Third conductive bonding layer 36: Fourth conductive bonding layer 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 50: Sealing portion 51: Top surface 52: Bottom surface 53: Resin side surface 531: First side surface 532: Second side surface 55: Recess 60: Control wiring 601: First wiring 602: Second wiring 61: Insulating layer 62: Wiring layer 621: First wiring layer 622: Second wiring layer 623: Third wiring layer 624: Fourth wiring layer 625: Fifth wiring layer 63: Metal layer 64: Sleeve 71: Linking portion 71A: First connecting portion 71B: Second connecting portion 710: Third through-hole 711: First strip-shaped portion 7111: Covered portion 7112: Covered portion 7113: Exposed portion 712: Second strip-shaped portion 7121: Covered portion 7122: Covered portion 7123: Exposed portion 72: Extension part721: First extending portion 7210: First through hole 7211: Covered portion 7212: Exposed portion 722: Second extending portion 7220: Second through hole 7221: Covered portion 7222: Exposed portion 791, 792: Insulating sheet 80: Heat sink 81: Wiring board 811: Board 811A: Through hole 812: Main wiring 813: Back wiring 814: Internal wiring 84: Mounting member 841: Through hole 86: Positioning pin 87: Fastening member 88: Support (Reference symbols used in Figures 43 to 68) A10: Semiconductor module B10 to B15, B20, B30: Semiconductor device 11: Support substrate 111: Insulating layer 112: Intermediate layer 113: Heat dissipation layer 121: First conductive layer 121A: First main surface 121B: First back surface 122: Second conductive layer 122A: Second main surface 122B: Second back surface 123: First adhesive layer 13: First input terminal 13A: Covered portion 13B: Exposed portion 14: Output terminal 14A: Covered portion 14B: Exposed portion 15: Second input terminal 15A: Covered portion 15B: Exposed portion 161: First signal terminal 161A: Base portion 161B: Bulging portion 162: Second signal terminal 171: Third signal terminal 172: Fourth signal terminal 181: Fifth signal terminal 182: Sixth signal terminal 19: Seventh signal terminal 21: Semiconductor element 21A: First element 21B: Second element 211: First electrode 212: Second electrode 213: Third electrode 214: Fourth electrode 22: Thermistor 23: Conductive bonding layer 31: First conductive member 311: Main body 312: First bonding portion 313: First connecting portion 314: Second bonding portion 315: Second connecting portion 32: Second conductive member 321: Main body 322: Third bonding portion 323: Third connecting portion 324: Fourth bonding portion 325: Fourth connecting portion 326: Middle portion 327: Cross beam portion 33: First conductive bonding layer 34: Second conductive bonding layer 35: Third conductive bonding layer 36: Fourth conductive bonding layer 41: First wire 42: Second wire 43: Third wire 44: Fourth wire 50: Sealing resin 51: Top surface 52: Bottom surface 53: Resin side surface 531: First side surface 532: Second side surface55: Recess 60: Control wiring 601: First wiring 602: Second wiring 61: Insulating layer 62: Wiring layer 621: First wiring layer 622: Second wiring layer 623: Third wiring layer 624: Fourth wiring layer 625: Fifth wiring layer 63: Metal layer 64: Sleeve 641: End face 68: Second adhesive layer 69: Third adhesive layer 70: Plate 71: First plate 711: First covering portion 711a: Protruding portion 712: First exposed portion 712a: First base portion 712b: First bent portion 712c: First mounting portion 712d: First through hole 72: Second plate 721: Second covering portion 721a: Protruding portion 722: Second exposed portion 722a: Second base portion 722b: Second bent portion 722c: Second mounting portion 722d: Second through hole 80: Heat sink 81: Wiring board 811: Board 811A: Through hole 812: Main wiring 813: Back wiring 814: Internal wiring 85: Support 891, 892: Fixture

Claims

1. a plurality of semiconductor devices each including a semiconductor element, a sealing portion covering the semiconductor element, and a signal terminal protruding from the sealing portion in a thickness direction of the sealing portion and electrically connected to the semiconductor element; A connection portion connecting the plurality of semiconductor devices; Equipped with the plurality of semiconductor devices include a first device and a second device adjacent to each other in a first direction perpendicular to the thickness direction; The coupling portion includes a first connection portion located between the first device and the second device in the first direction and connecting the first device and the second device.

2. an extension portion that is not conductive to the semiconductor element of each of the plurality of semiconductor devices; the plurality of semiconductor devices include a first outer device located at the outermost position on one side in the first direction and a second outer device located at the outermost position on the other side in the first direction, 2. The semiconductor module according to claim 1, wherein the extension portion includes a first extension portion protruding from the first outer device to the one side in the first direction, and a second extension portion protruding from the second outer device to the other side in the first direction.

3. The first extension portion has a first through hole penetrating in the thickness direction. The semiconductor module according to claim 2 , wherein the second extension portion has a second through hole penetrating therethrough in the thickness direction.

4. One of the first through hole and the second through hole opens in a perfect circle when viewed in the thickness direction, The semiconductor module according to claim 3 , wherein the other of the first through hole and the second through hole opens into an elongated hole when viewed in the thickness direction.

5. The semiconductor module according to claim 3 , wherein the connecting portion has a third through hole penetrating in the thickness direction.

6. Each of the plurality of semiconductor devices further includes a power terminal electrically connected to the semiconductor element, 6. The semiconductor module according to claim 1, wherein in each of said plurality of semiconductor devices, said power terminal protrudes from said sealing portion in a second direction perpendicular to said thickness direction and said first direction.

7. 7. The semiconductor module according to claim 6, wherein in each of the plurality of semiconductor devices, the semiconductor element includes a first element and a second element, and the power terminal includes a first power terminal conductive to the first element and a second power terminal conductive to the second element.

8. Each of the plurality of semiconductor devices includes a first mounting portion for mounting the first element and a second mounting portion for mounting the second element, 8. The semiconductor module of claim 7, wherein in each of the plurality of semiconductor devices, the first mounting portion is located on one side of the second direction relative to the second mounting portion, and the first power terminal and the second power terminal protrude from the sealing portion to the one side of the second direction.

9. a conductive member electrically connecting the second power terminal and the second element, 9 . The semiconductor module according to claim 8 , wherein a portion of the conductive member extends from an edge of the first mounting portion on the one side in the second direction to an edge of the first mounting portion on the other side in the second direction when viewed in the thickness direction.

10. The semiconductor module according to claim 9 , wherein the coupling portion is not electrically connected to the semiconductor element of each of the plurality of semiconductor devices.

11. The connecting portion is made of a conductive material, The semiconductor module according to claim 10 , wherein the first connection portion includes a first covering portion covered by the sealing portion of the first device and a second covering portion covered by the sealing portion of the second device.

12. the first connection portion includes an exposed portion exposed from each of the sealing portion of the first device and the sealing portion of the second device, The semiconductor module according to claim 11 , wherein the exposed portion is interposed between the first covered portion and the second covered portion in the first direction.

13. The semiconductor module according to claim 10 , wherein the connecting portion is made of an insulating material.

14. The semiconductor module according to claim 13 , wherein the connecting portion is formed integrally with the sealing portion of each of the plurality of semiconductor devices.

15. the coupling portion is electrically connected to the semiconductor element of each of the plurality of semiconductor devices; The semiconductor module according to claim 9 , wherein the first connection portion extends along the first direction and is connected to the second power terminal of the first device and the second power terminal of the second device.

16. the first connection portion includes a first band portion and a second band portion spaced apart in the second direction, The semiconductor module according to claim 9 , wherein the first strip portion is located on the one side in the second direction relative to the second strip portion.

17. the second strip portion is not conductive to the semiconductor element of each of the plurality of semiconductor devices; The semiconductor module according to claim 16 , wherein the second strip portion overlaps the second mounting portion when viewed in the thickness direction, but does not overlap the conductive member when viewed in the thickness direction.

18. the first strip portion is not conductive to the semiconductor element of each of the plurality of semiconductor devices; 18. The semiconductor module of claim 17, wherein the first band portion overlaps the first mounting portion and the conductive member when viewed in the thickness direction, and is positioned between the first mounting portion and the conductive member in the thickness direction and spaced apart from the first mounting portion and the conductive member.

19. the plurality of semiconductor devices includes a third device disposed on an opposite side of the first device with respect to the second device in the first direction, the second device and the third device are adjacent to each other in the first direction, 6. The semiconductor module according to claim 1, wherein the coupling portion includes a second connection portion located between the second device and the third device in the first direction and connecting the second device and the third device.

20. A semiconductor module according to any one of claims 1 to 5, a heat sink to which the semiconductor module is attached and which is in contact with each of the plurality of semiconductor devices.