Wafer structure and method for manufacturing semiconductor devices

Abstract

This wafer structure includes: a wafer having a first surface on one side and a second surface on the other side; a first electrode covering the first surface; a second electrode covering the inner part of the second surface such that a peripheral section of the second surface is exposed; and a protective tape that has higher adhesiveness to the peripheral section of the second surface than to the second electrode, and is adhered to the peripheral section of the second surface and the second electrode.

Description

Wafer structure and method of manufacturing semiconductor device

[0001] This application claims priority to Patent Application No. 2022-095664 filed with the Japan Patent Office on June 14, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a wafer structure and a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device, including the steps of forming a first electrode on a first main surface of a semiconductor wafer, forming a second electrode that covers the entire second main surface of the semiconductor wafer, adhering a first tape to the entire second main surface so as to cover the entire second electrode, adhering a second tape to the entire edge of the semiconductor wafer so as to overlap the first tape, and forming a plating layer on the first electrode with the first tape and second tape adhered.

[0003] US Patent Application Publication No. 2022-0020628

[0004] One embodiment provides a wafer structure and a method for manufacturing a semiconductor device that contributes to the manufacture of semiconductor devices with high reliability.

[0005] One embodiment provides a wafer structure including a wafer having a first surface on one side and a second surface on the other side, a first electrode covering the first surface, a second electrode covering an inner portion of the second surface so as to expose a peripheral portion of the second surface, and a protective tape having a property that the adhesion strength to the peripheral portion of the second surface is higher than the adhesion strength to the second electrode, and attached to the peripheral portion of the second surface and the second electrode.

[0006] One embodiment provides a method for manufacturing a semiconductor device, including the steps of preparing a wafer structure including a wafer having a first surface on one side and a second surface on the other side, and a first electrode covering the first surface; forming a second electrode covering an inner portion of the second surface so as to expose a peripheral portion of the second surface; and adhering a protective tape having a property that its adhesion strength to the peripheral portion of the second surface is higher than its adhesion strength to the second electrode to the peripheral portion of the second surface and the second electrode.

[0007] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0008] FIG. 1 is a plan view of a wafer structure according to a first embodiment, as viewed from the first main surface side. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a schematic cross-sectional view of the wafer structure shown in FIG. 1 . FIG. 4 is a plan view of the wafer structure shown in FIG. 1, as viewed from the second main surface side. FIG. 5 is a plan view showing an example layout of second electrodes shown in FIG. 3 . FIG. 6 is an enlarged cross-sectional view showing the peripheral portion of the wafer structure shown in FIG. 1 together with second electrodes according to a first embodiment. FIG. 7A is an enlarged cross-sectional view showing the peripheral portion of the wafer structure shown in FIG. 1 together with second electrodes according to a second embodiment. FIG. 7B is an enlarged cross-sectional view showing the peripheral portion of the wafer structure shown in FIG. 1 together with second electrodes according to a third embodiment. FIG. 8A is a cross-sectional view showing a method for manufacturing a semiconductor device according to the wafer structure shown in FIG. 1 . FIG. 8B is a cross-sectional view showing a process subsequent to FIG. 8A . FIG. 8C is a cross-sectional view showing a process subsequent to FIG. 8B . FIG. 8D is a cross-sectional view showing a process subsequent to FIG. 8C . FIG. 8E is a cross-sectional view showing a process subsequent to FIG. 8D . 8F is a cross-sectional view showing a step subsequent to FIG. 8E. FIG. 8G is a cross-sectional view showing a step subsequent to FIG. 8F. FIG. 9A is a cross-sectional view showing a step of forming a second electrode. FIG. 9B is a cross-sectional view showing a step subsequent to FIG. 9A. FIG. 9C is a cross-sectional view showing a step subsequent to FIG. 9B. FIG. 10 is a plan view of a wafer structure according to a second embodiment, as seen from the first main surface side. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 10. FIG. 12 is an enlarged cross-sectional view showing a main portion of the functional device shown in FIG. 11. FIG. 13 is a schematic cross-sectional view of the wafer structure shown in FIG. 10. FIG. 14A is a cross-sectional view showing a method for manufacturing a semiconductor device related to the wafer structure shown in FIG. 10. FIG. 14B is a cross-sectional view showing a step subsequent to FIG. 14A. FIG. 14C is a cross-sectional view showing a step subsequent to FIG. 14B. FIG. 14D is a cross-sectional view showing a step subsequent to FIG. 14C. FIG. 14E is a cross-sectional view showing a step subsequent to FIG. 14D. FIG. 14F is a cross-sectional view showing a step subsequent to FIG. 14E. Fig. 14G is a cross-sectional view showing a step subsequent to Fig. 14F. Fig. 15 is a plan view showing a wafer according to a modified example. Fig. 16 is a schematic cross-sectional view showing a step of forming a second electrode according to a first modified example. Fig. 17 is a schematic cross-sectional view showing a step of forming a second electrode according to a second modified example. Fig. 18 is a schematic cross-sectional view showing a step of forming a second electrode according to a third modified example.

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrative, and are not necessarily drawn to scale. Corresponding structures among the accompanying drawings are denoted by the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the previous descriptions apply. Terms such as "first," "second," and "third" are used in the embodiments, but these are symbols added to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] Fig. 1 is a plan view of a wafer structure 1A according to a first embodiment, as viewed from the first main surface 3 side. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a schematic cross-sectional view of the wafer structure 1A shown in Fig. 1. Fig. 4 is a plan view of the wafer structure 1A shown in Fig. 1, as viewed from the second main surface 4 side. Fig. 5 is a plan view showing an example layout of second electrodes 24 shown in Fig. 3.

[0011] Fig. 6 is an enlarged cross-sectional view showing the peripheral portion of the wafer structure 1A shown in Fig. 1 together with the second electrode 24 according to the first embodiment. Fig. 7A is an enlarged cross-sectional view showing the peripheral portion of the wafer structure 1A shown in Fig. 1 together with the second electrode 24 according to the second embodiment. Fig. 7B is an enlarged cross-sectional view showing the peripheral portion of the wafer structure 1A shown in Fig. 1 together with the second electrode 24 according to the third embodiment.

[0012] 1 to 6, the wafer structure 1A includes a wafer 2. In this embodiment, the wafer 2 is formed in a flat disk shape. Of course, the wafer 2 may also be formed in a flat rectangular parallelepiped shape. In this embodiment, the wafer 2 is made of a semiconductor single crystal having a plating reaction rate slower than that of a Si (silicon) single crystal. In other words, the wafer 2 is made of a semiconductor single crystal having a slower oxidation-reduction reaction rate than that of a Si single crystal. It is particularly preferable that the wafer 2 be made of a semiconductor single crystal having a Ni plating reaction rate slower than that of a Si single crystal.

[0013] The wafer 2 is most preferably made of a high-hardness semiconductor single crystal having a hardness higher than that of a Si single crystal. The wafer 2 is preferably made of a wide-bandgap semiconductor wafer including a wide-bandgap semiconductor single crystal. In other words, the wafer structure 1A is preferably a wide-bandgap semiconductor wafer structure. A wide-bandgap semiconductor is a semiconductor having a bandgap higher than that of Si.

[0014] In this embodiment, the wafer 2 is a SiC wafer containing hexagonal SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. In other words, the wafer structure 1A is a SiC wafer structure. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the wafer 2 contains 4H-SiC single crystal, but the wafer 2 may also contain SiC single crystal of another polytype.

[0015] The wafer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and a side surface 5 connecting the first main surface 3 and the second main surface 4. Hereinafter, one direction along the first main surface 3 will be referred to as the first direction X, a direction along the first main surface 3 that is perpendicular to the first direction X will be referred to as the second direction Y, and a direction that is perpendicular to the first main surface 3 will be referred to as the vertical direction Z. The first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0016] The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. Preferably, the first main surface 3 faces the silicon side of the SiC single crystal, and the second main surface 4 faces the carbon side of the SiC single crystal. The first main surface 3 is a device-forming surface, and the second main surface 4 is a non-device-forming surface. The second main surface 4 is a flat surface extending horizontally from the inner portion to the peripheral portion, and does not have any steps in the peripheral portion. In this embodiment, the second main surface 4 is a ground surface having multiple grinding marks recessed toward the first main surface 3. The depth of the grinding marks is preferably 0.5 μm or less. It is particularly preferable that the depth of the grinding marks be 0.1 μm or less.

[0017] The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. That is, the c-axis of the SiC single crystal may be inclined with respect to the vertical direction Z by the off angle. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0° and not more than 10°. The off angle is preferably not more than 5°. The off angle is particularly preferably not less than 2° and not more than 4.5°.

[0018] The wafer 2 has a mark 6 on the side surface 5 that indicates the crystal orientation of the SiC single crystal. In this embodiment, the mark 6 includes an orientation flat that is linearly cut out in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). In this embodiment, the orientation flat extends in the second direction Y.

[0019] The orientation flat does not necessarily have to extend in the second direction Y, but may extend in the first direction X. Of course, the mark 6 may include a first orientation flat extending in the first direction X and a first orientation flat extending in the second direction Y.

[0020] The wafer 2 may have a diameter of 50 mm to 300 mm (i.e., 2 inches to 12 inches) in a plan view. The diameter of the wafer 2 is defined by the length of a chord passing through the center of the wafer 2 outside the mark 6.

[0021] The wafer 2 is preferably a thin wafer having a thickness of 30 μm or more and less than 200 μm. The wafer 2 may have a thickness of 30 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, or 175 μm or more and 200 μm or less. The thickness of the wafer 2 is preferably 160 μm or less.

[0022] In this embodiment, the wafer structure 1A includes an n-type first region 7 (first semiconductor region) formed in a region (surface layer) on the first main surface 3 side of the wafer 2. The first region 7 is formed in a layer extending along the first main surface 3 and is exposed from the first main surface 3 and the side surface 5. In this embodiment, the first region 7 is made of an epitaxial layer (SiC epitaxial layer). The first region 7 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first region 7 is preferably 5 μm or more and 30 μm or less. It is particularly preferable that the thickness of the first region 7 be 25 μm or less.

[0023] In this embodiment, the wafer structure 1A includes an n-type second region 8 (second semiconductor region) formed in a region (surface layer) on the second main surface 4 side of the wafer 2. The second region 8 has a higher n-type impurity concentration than the first region 7 and is electrically connected to the first region 7 within the wafer 2. The second region 8 is formed in a layer extending along the second main surface 4 and is exposed from the second main surface 4 and the side surface 5. In this embodiment, the second region 8 is made of a semiconductor substrate (SiC substrate). In other words, the wafer 2 has a layered structure including a substrate and an epitaxial layer.

[0024] The second region 8 may have a thickness of 1 μm or more and less than 200 μm. The thickness of the second region 8 is preferably less than 160 μm. The thickness of the second region 8 is preferably 10 μm or more. The thickness of the second region 8 may be greater than the thickness of the first region 7. The thickness of the second region 8 may be less than the thickness of the first region 7.

[0025] The wafer structure 1A includes a plurality of device regions 10 provided on a first main surface 3. Each device region 10 corresponds to a semiconductor device (wide bandgap semiconductor device / SiC semiconductor device). Each of the device regions 10 is set to have a rectangular shape in a plan view. In this embodiment, the device regions 10 are arranged in a matrix along a first direction X and a second direction Y in a plan view.

[0026] The device regions 10 are arranged at intervals inward from the peripheral edge of the first main surface 3 in a plan view, and define a space 11 in the peripheral edge of the first main surface 3 where the device regions 10 are not present. In other words, the wafer 2 has an inner portion having the device regions 10 and a peripheral portion having no device regions 10. The space 11 is formed in a ring shape surrounding the device regions 10 in a plan view. The space 11 has a portion that extends in an arc shape in the area outside the mark 6 in a plan view, and a portion that extends linearly in the area along the mark 6.

[0027] The length of one side of each device region 10 may be 0.5 mm or more and 20 mm or less. The length of one side of each device region 10 is preferably 1 mm or more. The length of one side of each device region 10 is particularly preferably 2 mm or more. In this embodiment, the length of one side of each device region 10 is set in the range of 4 mm or more and 6 mm or less.

[0028] The wafer structure 1A includes a plurality of cutting lines 12 provided on the first main surface 3. The plurality of cutting lines 12 are set in a grid pattern extending along the first direction X and the second direction Y so as to partition a plurality of device regions 10.

[0029] The wafer structure 1A further includes functional devices 13 formed in each device region 10 on the first main surface 3. Each functional device 13 is formed spaced apart inward from the periphery of each device region 10. Each functional device 13 may include at least one of a switching device, a rectifying device, and a passive device.

[0030] The switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET). The rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode (SBD), and a fast recovery diode (FRD). The passive device may include at least one of a resistor, a capacitor, and a coil.

[0031] Each functional device 13 may include a circuit network (for example, an integrated circuit such as an LSI) that combines at least two of a switching device, a rectifying device, and a passive device. In this embodiment, each functional device 13 includes an SBD. Since the configurations of multiple device regions 10 (functional devices 13) are similar, the configuration of one device region 10 (functional device 13) will be described below.

[0032] 5, the wafer structure 1A includes an n-type diode region 14 formed in the surface layer portion of the first main surface 3 in the device region 10. In this embodiment, the diode region 14 is formed by utilizing the first region 7. The diode region 14 is formed at a distance inward from the periphery of the device region 10. The diode region 14 is formed in a polygonal shape (a quadrangular shape in this embodiment) in a plan view.

[0033] The wafer structure 1A includes a p-type (second conductivity type) guard region 15 formed in a surface layer portion of the first main surface 3 in the device region 10. The guard region 15 is formed in a surface layer portion of the first region 7 at a distance inward from the periphery of the device region 10. The guard region 15 is formed in a polygonal ring shape (a square ring in this embodiment) surrounding the diode region 14 in a plan view. The guard region 15 has an inner edge portion on the inner side of the device region 10 and an outer edge portion on the periphery side of the device region 10.

[0034] The wafer structure 1A includes a main surface insulating film 16 that selectively covers the first main surface 3 in the device region 10. The main surface insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 16 has a single-layer structure including a silicon oxide film. The main surface insulating film 16 has contact openings 17 that expose inner edges of the diode region 14 and the guard region 15.

[0035] The main surface insulating film 16 covers the inner part of the device region 10 at a distance inward from the periphery of the device region 10, and exposes the first main surface 3 (first region 7) from the periphery of the device region 10. In other words, the main surface insulating film 16 exposes the boundaries (plurality of lines 12 to cut) between the plurality of device regions 10. Of course, the main surface insulating film 16 may also cover the boundaries (plurality of lines 12 to cut) between the plurality of device regions 10.

[0036] The wafer structure 1A includes a first electrode 18 covering the first main surface 3 in the device region 10. In this embodiment, the first electrode 18 is formed as an anode electrode. The first electrode 18 is disposed inward from the periphery of the device region 10 with a space therebetween. The first electrode 18 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the device region 10 in a plan view. The first electrode 18 extends from above the main surface insulating film 16 into the contact opening 17 and is electrically connected to the inner edges of the diode region 14 and the guard region 15. Specifically, the first electrode 18 forms a Schottky junction with the diode region 14.

[0037] The first electrode 18 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the first main surface 3 side. The Ti-based metal film may include at least one of a Ti film and a Ti alloy film. The Al-based metal film is preferably thicker than the Ti-based metal film. The Al-based metal film includes at least one of an Al film and an Al alloy film. For example, the Al-based metal film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0038] The wafer structure 1A includes an insulating film 19 that covers the first electrode 18 in the device region 10. The insulating film 19 covers the peripheral portion of the first electrode 18 at a distance inward from the peripheral edge of the device region 10. The insulating film 19 defines a pad opening 20 in the inner portion of the device region 10 and defines a street opening 21 in the peripheral portion of the device region 10. The pad opening 20 exposes the inner portion of the first electrode 18. The pad opening 20 is formed in a polygonal shape (a quadrangle in this embodiment) that follows the peripheral edge of the first electrode 18 in a plan view.

[0039] The street openings 21 extend along the periphery of the device region 10 and expose the first main surface 3. Specifically, the street openings 21 are partitioned into a lattice shape extending in the first direction X and the second direction Y by a plurality of insulating films 19 adjacent to each other in the first direction X and the second direction Y, and expose the boundaries (a plurality of lines to cut 12) between the plurality of device regions 10. Of course, when a main surface insulating film 16 covering the first main surface 3 is formed at the boundaries between the plurality of device regions 10, the street openings 21 may expose the main surface insulating film 16 at the boundaries between the plurality of device regions 10.

[0040] The insulating film 19 is preferably thicker than the first electrode 18. The thickness of the insulating film 19 is preferably less than the thickness of the wafer 2. The thickness of the insulating film 19 may be 3 μm or more and 35 μm or less. The thickness of the insulating film 19 is preferably 25 μm or less.

[0041] In this embodiment, the insulating film 19 has a layered structure including an inorganic insulating film 22 (inorganic film) and an organic insulating film 23 (organic film), which are layered in this order from the first electrode 18 side. The inorganic insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 22 preferably includes an insulating material different from that of the main surface insulating film 16. In this embodiment, the inorganic insulating film 22 has a single-layer structure including a silicon nitride film. The thickness of the inorganic insulating film 22 may be 0.1 μm or more and 5 μm or less.

[0042] The organic insulating film 23 is thicker than the inorganic insulating film 22 and covers the inorganic insulating film 22. The organic insulating film 23 is preferably made of a photosensitive resin film. The organic insulating film 23 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. The thickness of the organic insulating film 23 may be 3 μm or more and 30 μm or less. The thickness of the organic insulating film 23 is preferably 20 μm or less.

[0043] The organic insulating film 23 may expose either or both of the inner edge portion and the outer edge portion of the inorganic insulating film 22. In this embodiment, the organic insulating film 23 exposes both the inner edge portion and the outer edge portion of the inorganic insulating film 22, and separates the inorganic insulating film 22 from the pad opening 20 and the street opening 21. Of course, the organic insulating film 23 may cover the entire area of ​​the inorganic insulating film 22.

[0044] The wafer structure 1A includes a second electrode 24 covering the second main surface 4. In this embodiment, the second electrode 24 is formed as a cathode electrode and is electrically connected to the second region 8 exposed from the second main surface 4. The second electrode 24 has a plating reaction rate faster than the plating reaction rate of the wafer 2. In other words, the second electrode 24 includes an electrode material whose oxidation-reduction reaction rate is faster than that of the wafer 2.

[0045] The second electrode 24 exposes at least a portion of the peripheral edge of the wafer 2 as a plating reaction inhibiting portion 25. In other words, the plating reaction inhibiting portion 25 is an exposed portion of the second main surface 4 that is exposed from the second electrode 24. In this embodiment, the second electrode 24 exposes the entire peripheral edge of the wafer 2 as the plating reaction inhibiting portion 25.

[0046] That is, the plating reaction inhibiting portion 25 exposes the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed from the peripheral portion of the second main surface 4. The plating reaction inhibiting portion 25 also exposes grinding marks formed on the peripheral portion of the second main surface 4. The portion of the second main surface 4 that forms the plating reaction inhibiting portion 25 is formed flush with the portion of the second main surface 4 that is hidden by the second electrode 24. That is, the plating reaction inhibiting portion 25 extends horizontally, and does not form a step on the second main surface 4 that is recessed toward the first main surface 3.

[0047] The plating reaction inhibiting portion 25 has a portion that extends in an arc shape in a region outside the mark 6 in a plan view, and a portion that extends linearly in a region along the mark 6. The plating reaction inhibiting portion 25 is formed in a region outside the plurality of device regions 10 in a plan view, and faces the space 11 in the thickness direction of the wafer 2. In other words, the plating reaction inhibiting portion 25 is formed in a ring shape that collectively surrounds the plurality of device regions 10 in a plan view.

[0048] The exposed width W of the plating reaction inhibiting portion 25 is preferably larger than the thickness of the second electrode 24. The exposed width W is preferably larger than the thickness of the first electrode 18. The exposed width W is preferably larger than the thickness of the insulating film 19. It is particularly preferable that the exposed width W is larger than the thickness of the wafer 2.

[0049] The exposed width W may be 0.5 mm or more and 5 mm or less. The exposed width W is preferably 1 mm or more and 2 mm or less. It is particularly preferable that the exposed width W is less than the length of one side of the device region 10. This configuration can prevent a decrease in the number of device regions 10 (i.e., the number of semiconductor devices) due to the introduction of the plating reaction inhibitor 25.

[0050] The second electrode 24 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film. The Al-based metal film may include at least one of an Al film and an Al alloy film. For example, the Al-based metal film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0051] The Ti-based metal film may include at least one of a Ti film and a Ti alloy film. The Ni-based metal film may include at least one of a Ni film and a Ni alloy film. The Pd-based metal film may include at least one of a Pd film and a Pd alloy film. The Au-based metal film may include at least one of an Au film and an Au alloy film. The Ag-based metal film may include at least one of an Ag film and an Ag alloy film.

[0052] 6 , in this embodiment, the second electrode 24 has a layered structure including a Ti film 31, a Ni film 32, and an Au film 33, which are layered in this order from the second main surface 4 side. The Ti film 31 directly covers the second main surface 4. In this embodiment, the Ti film 31 does not form a silicide (TiSi) layer in the surface layer portion of the second main surface 4. Of course, the Ti film 31 may form a silicide layer in the surface layer portion of the second main surface 4. The Ti film 31 may have a thickness of 500 Å or more and 1000 Å or less.

[0053] The Ni film 32 is thicker than the Ti film 31 and covers the Ti film 31. The thickness of the Ni film 32 may be 5,000 Å or more and 20,000 Å or more. The Au film 33 is thinner than the Ni film 32 and covers the Ni film 32. The thickness of the Au film 33 may be 500 Å or more and 1,000 Å or less.

[0054] 7A , the second electrode 24 may have a layered structure including an AlSi alloy film 34, a Ti film 35, a Ni film 36, and an Au film 37, which are layered in this order from the second main surface 4 side. The AlSi alloy film 34 directly covers the second main surface 4. In this embodiment, the AlSi alloy film 34 does not form a silicide (AlSi) layer in the surface layer portion of the second main surface 4. Of course, the AlSi alloy film 34 may form a silicide layer in the surface layer portion of the second main surface 4. The AlSi alloy film 34 may have a thickness of 500 Å or more and 2000 Å or less.

[0055] The Ti film 35 is thinner than the AlSi alloy film 34 and covers the AlSi alloy film 34. The thickness of the Ti film 35 may be 500 Å or more and 1000 Å or less. The Ni film 36 is thicker than the Ti film 35 and covers the Ti film 35. The Ni film 36 may have a thickness of 5000 Å or more and 20000 Å or more. The Au film 37 is thinner than the Ni film 36 and covers the Ni film 36. The Au film 37 may have a thickness of 500 Å or more and 1000 Å or less.

[0056] 7B , the second electrode 24 may have a layered structure including a Ti film 38, a Ni film 39, an Au film 40, and an Ag film 41, which are layered in this order from the second main surface 4 side. The Ti film 38 directly covers the second main surface 4. In this embodiment, the Ti film 38 does not form a silicide (TiSi) layer in the surface layer portion of the second main surface 4. Of course, the Ti film 38 may form a silicide layer in the surface layer portion of the second main surface 4. The Ti film 38 may have a thickness of 500 Å or more and 1000 Å or less.

[0057] The Ni film 39 is thicker than the Ti film 38 and covers the Ti film 38. The thickness of the Ni film 39 may be 5,000 Å or more and 20,000 Å or more. The Au film 40 is thinner than the Ni film 39 and covers the Ni film 39. The thickness of the Au film 33 may be 500 Å or more and 1,000 Å or less. The Ag film 41 is thicker than the Au film 40 and covers the Au film 40. The thickness of the Ag film 41 may be 1,000 Å or more and 3,000 Å or less.

[0058] The wafer structure 1A includes a protective tape 45 attached to the second electrode 24 of the wafer 2. The protective tape 45 may also be referred to as a "protective film," a "support tape," a "support film," or the like. The protective tape 45 is preferably thicker than the second electrode 24. The thickness of the protective tape 45 is preferably greater than the thickness of the first electrode 18. The thickness of the protective tape 45 is preferably greater than the thickness of the insulating film 19. The thickness of the protective tape 45 is preferably less than the thickness of the wafer 2. Of course, the thickness of the protective tape 45 may be greater than or equal to the thickness of the wafer 2.

[0059] The protective tape 45 includes a base film 46 and an adhesive layer 47. The base film 46 is made of an optically transparent organic film. The base film 46 preferably has a planar shape corresponding to the planar shape of the wafer 2. In this embodiment, the base film 46 is formed in a circular shape in a planar view. When a rectangular parallelepiped wafer 2 is used, the base film 46 is preferably formed in a quadrangular shape in a planar view.

[0060] The substrate film 46 is preferably thicker than the second electrode 24. The thickness of the substrate film 46 is preferably greater than the thickness of the first electrode 18. The thickness of the substrate film 46 is preferably greater than the thickness of the insulating film 19. The thickness of the substrate film 46 is preferably less than the thickness of the wafer 2. Of course, the thickness of the substrate film 46 may be greater than or equal to the wafer 2. The thickness of the substrate film 46 may be 10 μm or more and 100 μm or less. The thickness of the substrate film 46 is preferably 20 μm or more and 50 μm or less.

[0061] The adhesive layer 47 is provided on one side of the base film 46. The adhesive layer 47 is preferably provided over the entire area of ​​one side of the base film 46. The adhesive layer 47 is preferably thicker than the second electrode 24. The thickness of the adhesive layer 47 is preferably greater than the thickness of the first electrode 18.

[0062] The thickness of the adhesive layer 47 is preferably greater than the thickness of the insulating film 19. The thickness of the adhesive layer 47 is preferably less than the thickness of the wafer 2. Of course, the thickness of the adhesive layer 47 may be greater than or equal to the wafer 2. The thickness of the adhesive layer 47 may be 10 μm or more and 100 μm or less. The thickness of the adhesive layer 47 is preferably 20 μm or more and 50 μm or less.

[0063] The adhesive layer 47 may contain, for example, a photo-curable adhesive whose adhesive strength decreases when irradiated with ultraviolet light. The adhesive layer 47 has a property that its adhesion (adhesive strength) to the wafer 2 is stronger than its adhesion (adhesive strength) to the second electrode 24. In other words, the protective tape 45 has a property that its adhesion strength to the plating reaction inhibiting portion 25 (the peripheral portion of the second main surface 4) is stronger than its adhesion strength to the second electrode 24.

[0064] The adhesive strength of the protective tape 45 (adhesive layer 47) to the wafer 2 is preferably greater than 14.1 N / 25 mm. For example, the adhesive strength of the protective tape 45 to the SiC wafer is preferably greater than 14.4 N / 25 mm. The adhesive strength of the protective tape 45 to the second electrode 24 is equal to or greater than 8 N / 25 mm and less than 14 N / 25 mm. For example, the adhesive strength of the protective tape 45 to the Au film 33 is approximately 8.9 N / 25 mm. For example, the adhesive strength of the protective tape 45 to the Ag film 41 is approximately 10 N / 25 mm.

[0065] The protective tape 45 is attached to the second main surface 4 of the wafer 2 by adhering the adhesive layer 47 to the second electrode 24 and the plating reaction inhibiting portion 25 (the peripheral edge portion of the second main surface 4). The protective tape 45 covers the entire second electrode 24 and extends in the form of a film from above the second electrode 24 onto the plating reaction inhibiting portion 25. In this form, the protective tape 45 covers the plating reaction inhibiting portion 25 along the entire peripheral edge portion of the wafer 2.

[0066] That is, protective tape 45 covers the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed as plating reaction inhibiting portion 25. Protective tape 45 also covers grinding marks formed in plating reaction inhibiting portion 25. In this case, it is preferable that adhesive layer 47 fills in the grinding marks.

[0067] According to this configuration, the grinding marks increase the adhesion area of ​​the protective tape 45 (adhesive layer 47) to the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4). Therefore, the adhesion force of the protective tape 45 to the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4) increases. In other words, the grinding marks also function as anchor holes for the protective tape 45.

[0068] The adhesive portion of the protective tape 45 to the plating reaction inhibiting portion 25 has a portion that extends in an arc shape in a region outside the mark 6 in a plan view, and a portion that extends linearly in a region along the mark 6. Specifically, the adhesive portion of the protective tape 45 is formed in a region outside the plurality of device regions 10 in a plan view, and faces the space 11 across the wafer 2. In other words, the adhesive portion of the protective tape 45 is formed in a ring shape that collectively surrounds the plurality of device regions 10 in a plan view.

[0069] The protective tape 45 may form a gap 48 between the second main surface 4 and the edge of the second electrode 24. That is, the protective tape 45 may be attached to the second electrode 24 and the plating reaction inhibiting portion 25 so as to expose the edge of the second electrode 24. The gap 48 may be formed around a portion of or the entire periphery of the edge of the second electrode 24. Of course, the protective tape 45 may cover the edge of the second electrode 24 around a portion of or the entire periphery of the edge of the second electrode 24 so that the gap 48 is not formed.

[0070] The edge of the protective tape 45 has a portion that extends in an arc shape in the area outside the marks 6 in a plan view, and a portion that extends linearly in the area along the marks 6. It is preferable that the protective tape 45 extends horizontally from the area on the second main surface 4 to the area outside the second main surface 4. With this configuration, the entire second main surface 4 can be concealed by the protective tape 45. In this case, the portion of the pressure-sensitive adhesive layer 47 that covers the peripheral edge of the base film 46 may be exposed from the wafer 2.

[0071] It is preferable that the protective tape 45 exposes the side surface 5 of the wafer 2. It is particularly preferable that the protective tape 45 exposes the entire side surface 5. The protective tape 45 exposing the entire side surface 5 means that the base film 46 is not attached to the side surface 5 of the wafer 2 via the adhesive layer 47. Therefore, in a configuration in which a portion of the adhesive layer 47 overlaps the lower end of the side surface 5, if the base film 46 does not face the side surface 5 via the adhesive layer 47, the protective tape 45 exposes the entire side surface 5.

[0072] The protrusion width Wo of the protective tape 45 may be larger than the thickness of the wafer 2. The protrusion width Wo may be larger than the thickness of the second electrode 24. The protrusion width Wo may be larger than the thickness of the first electrode 18. The protrusion width Wo may be larger than the thickness of the insulating film 19. The protrusion width Wo is preferably smaller than the exposed width W of the plating reaction inhibition portion 25. The protrusion width Wo may be 0.1 mm or more and 2 mm or less. The protrusion width Wo is preferably 0.5 mm or more and 1 mm or less.

[0073] 8A to 8F are cross-sectional views showing the manufacturing method of the semiconductor device SD1. Figures 9A to 9C are cross-sectional views showing the process of forming the second electrode 24. Figures 8A to 8F (Figures 9F to 9C) also show part of the manufacturing process of the wafer structure 1A.

[0074] 8A , first, a wafer structure 1A is prepared before the step of forming the second electrode 24. The wafer structure 1A includes, in each device region 10, a diode region 14, a guard region 15, a main surface insulating film 16, a first electrode 18, and an insulating film 19. The wafer structure 1A before the step of forming the second electrode 24 includes a wafer 2 having a thickness of 200 μm or more. The wafer 2 may have a thickness of 200 μm or more and 1000 μm or less. The wafer 2 preferably has a thickness of 250 μm or more and 500 μm or less.

[0075] Next, referring to FIG. 8B , a thinning step of the wafer 2 is performed. The wafer 2 may be thinned from the second main surface 4 side by at least one of a grinding method and an etching method. In this embodiment, the wafer 2 is thinned by a grinding method on the second main surface 4. In this embodiment, the wafer 2 is ground until the thickness is less than 200 μm. As a result, the wafer 2 is thinned and grinding marks are formed on the second main surface 4 at the same time.

[0076] Next, referring to Fig. 8C, a step of forming the second electrode 24 is performed. Referring to Fig. 9A, in this step, a mask jig 50 is prepared as a mask for the peripheral portion of the second main surface 4. The mask jig 50 may be made of an inorganic material such as metal (e.g., stainless steel), glass, or ceramic, or may be made of an organic material such as resin. The mask jig 50 is configured to cover at least a portion of the peripheral portion of the second main surface 4 and expose an inner portion of the second main surface 4.

[0077] That is, the mask jig 50 is configured to cover the region of the peripheral edge of the second main surface 4 that is to be formed as the plating reaction inhibiting portion 25. In this form, the mask jig 50 is configured to be annular (specifically, circular) in plan view so as to cover the entire periphery of the peripheral edge of the second main surface 4 and expose the inner portion of the second main surface 4.

[0078] The mask jig 50 may have a portion that extends in an arc shape in a region outside the mark 6 in a plan view, and a portion that extends linearly in a region along the mark 6. The mask jig 50 is preferably thicker than the second electrode 24 to be formed.

[0079] 9B , the mask jig 50 is brought into contact with the peripheral portion of the second main surface 4. The mask jig 50 is brought into contact with the SiC single crystal (in this embodiment, the carbon surface of the SiC single crystal) exposed from the peripheral portion of the second main surface 4. The mask jig 50 is disposed in an area outside the plurality of device regions 10 in plan view, and faces the space 11 across the wafer 2. In other words, the plating reaction inhibiting portion 25 is disposed so as to collectively surround the plurality of device regions 10 in plan view. The coverage width (contact width) of the mask jig 50 with respect to the peripheral portion of the second main surface 4 corresponds to the exposed width W of the plating reaction inhibiting portion 25.

[0080] Next, with the mask jig 50 in contact with the second main surface 4, the second electrode 24 is deposited on the second main surface 4 and the mask jig 50 by sputtering. The thickness of the second electrode 24 is less than the thickness of the mask jig 50. The second electrode 24 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.

[0081] The Al-based metal film, Ti-based metal film, Ni-based metal film, Pd-based metal film, Au-based metal film, and Ag-based metal film can all be formed by sputtering. The second electrode 24 according to the first to third embodiments (see FIGS. 6, 7A, and 7B) is formed by appropriately adjusting the order in which these metal films are formed.

[0082] 9C , the mask jig 50 is removed from the second main surface 4. As a result, the portion of the second electrode 24 that covers the mask jig 50 is also removed at the same time, and a plating reaction inhibition portion 25 having a layout corresponding to the layout of the mask jig 50 is formed in the peripheral portion of the second main surface 4.

[0083] 8D, protective tape 45 is then attached to second electrode 24 and plating reaction inhibiting portion 25 (peripheral edge portion of second main surface 4). This completes the manufacture of wafer structure 1A shown in FIGS. 1 to 6. Wafer structure 1A is handled with protective tape 45 attached.

[0084] 8E, a plating film 51 is formed on the first electrode 18 by plating. The plating film 51 may be considered a component of the wafer structure 1A. In this process, the entire wafer structure 1A is immersed in a plating solution, and the plating film 51 is formed on the first electrode 18. This process may include a step of rocking the wafer structure 1A in the plating solution. The rocking step includes a stirring step of diffusing bubbles generated during the plating reaction into the solution. This process suppresses poor formation of the plating film 51 due to bubbles.

[0085] In the case of a wafer 2 having a thickness of less than 200 μm, the wafer 2 is deformed by stress from the plating solution during the rocking process. The protective tape 45 protects the second electrode 24 from the plating solution and also suppresses deformation of the wafer 2 in the plating solution. This suppresses abnormal deposition of the plating film 51 on the second electrode 24 and also suppresses cracks in the wafer 2.

[0086] Furthermore, the second electrode 24 exposes the peripheral edge of the second main surface 4, and the protective tape 45 covers the peripheral edge of the second main surface 4. In this configuration, the protective tape 45 has a property that its adhesion to the peripheral edge of the second main surface 4 is stronger than its adhesion to the second electrode 24. With this configuration, peeling of the protective tape 45 at the peripheral edge of the second main surface 4 is suppressed.

[0087] This suppresses abnormal plating film formation on the second electrode 24 due to peeling of the protective tape 45. Furthermore, the adhesion of the protective tape 45 to the peripheral edge of the second main surface 4 is improved, which suppresses intrusion of the plating solution into the region between the second main surface 4 and the protective tape 45. This suppresses abnormal plating film formation on the second electrode 24.

[0088] Furthermore, the peripheral edge of the second main surface 4 is exposed as a plating reaction inhibiting portion 25 that reacts slowly with the plating solution. The plating reaction inhibiting portion 25 inhibits the formation of the plating film 51. Therefore, even if the plating solution penetrates into the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 suppresses abnormal plating film formation.

[0089] In this embodiment, the step of forming the plating film 51 includes the steps of forming a Ni plating film 52, a Pd plating film 53, and an Au plating film 54 in this order from the first electrode 18 side. The step of forming the Ni plating film 52 includes the step of forming the Ni plating film 52 on the first electrode 18 by electroless plating. The step of forming the Ni plating film 52 includes the step of immersing the wafer structure 1A in a Ni plating solution. The step of forming the Ni plating film 52 also includes the step of swinging the wafer structure 1A in the Ni plating solution.

[0090] The peripheral portion of the second main surface 4 is preferably exposed as a plating reaction inhibition portion 25 that has a slow reaction rate with at least the Ni plating solution. By suppressing abnormal formation of the Ni plating film 52 on the second main surface 4 side, abnormal formation of the Pd plating film 53 and the Au plating film 54 on the second main surface 4 side can also be suppressed in the subsequent process.

[0091] The Ni plating film 52 is preferably thicker than the inorganic insulating film 22. In this case, the Ni plating film 52 is preferably formed on the first electrode 18 so as to run onto the edge of the inorganic insulating film 22 within the pad opening 20. The Ni plating film 52 is preferably formed at a distance from the opening edge of the pad opening 20 toward the first electrode 18 in the vertical direction Z.

[0092] In this embodiment, the Ni plating film 52 covers the first electrode 18 and the inorganic insulating film 22 in the pad opening 20, and is in contact with the organic insulating film 23. Of course, the Ni plating film 52 may be formed in the pad opening 20 at a distance from the organic insulating film 23, and may cover the edges of the first electrode 18 and the inorganic insulating film 22.

[0093] The Ni plating film 52 may have a thickness of 0.1 μm or more and 15 μm or less. The thickness of the Ni plating film 52 may be 0.1 μm or more and 1 μm or less, 1 μm or more and 3 μm or less, 3 μm or more and 6 μm or less, 6 μm or more and 9 μm or less, 9 μm or more and 12 μm or less, or 12 μm or more and 15 μm or less. The thickness of the Ni plating film 52 is preferably 2 μm or more and 8 μm or less.

[0094] The process of forming the Pd plating film 53 includes a step of forming the Pd plating film 53 on the Ni plating film 52 by electroless plating. The process of forming the Pd plating film 53 includes a step of immersing the wafer structure 1A in a Pd plating solution. The process of forming the Pd plating film 53 also includes a step of swinging the wafer structure 1A in the Pd plating solution.

[0095] The peripheral portion of the second main surface 4 is preferably exposed as a plating reaction inhibiting portion 25 that reacts slowly with the Pd plating solution. By suppressing abnormal formation of the Pd plating film 53 on the second main surface 4 side, abnormal formation of the Au plating film 54 on the second main surface 4 side can also be suppressed in a subsequent process.

[0096] The Pd plating film 53 is formed in the form of a film along the outer surface of the Ni plating film 52. The Pd plating film 53 is preferably formed at a distance from the opening edge of the pad opening 20 toward the Ni plating film 52. The Pd plating film 53 contacts the organic insulating film 23 within the pad opening 20 in the vertical direction Z. Of course, when the Ni plating film 52 is spaced apart from the organic insulating film 23, the Pd plating film 53 may cover the Ni plating film 52 at a distance from the organic insulating film 23. In this case, the Pd plating film 53 may cover the edge of the inorganic insulating film 22.

[0097] The Pd plating film 53 preferably has a thickness less than that of the Ni plating film 52. The thickness of the Pd plating film 53 may be 0.01 μm or more and 1 μm or less. The thickness of the Pd plating film 53 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0098] The step of forming the Au plating film 54 includes a step of forming the Au plating film 54 on the Pd plating film 53 by electroless plating. The step of forming the Au plating film 54 includes a step of immersing the wafer structure 1A in an Au plating solution. The step of forming the Au plating film 54 also includes a step of swinging the wafer structure 1A in the Au plating solution. The peripheral edge of the second main surface 4 is preferably exposed as a plating reaction inhibition portion 25 that reacts slowly with the Au plating solution.

[0099] The Au plating film 54 is formed in the form of a film along the outer surface of the Pd plating film 53. The Au plating film 54 is preferably formed at a distance from the opening edge of the pad opening 20 toward the Pd plating film 53 in the vertical direction Z. The Au plating film 54 is in contact with the organic insulating film 23 within the pad opening 20. Of course, if the Ni plating film 52 and the Pd plating film 53 are spaced apart from the organic insulating film 23, the Au plating film 54 may cover the Pd plating film 53 at a distance from the organic insulating film 23. In this case, the Au plating film 54 may cover the edge of the inorganic insulating film 22.

[0100] The Au plating film 54 preferably has a thickness less than that of the Ni plating film 52. The thickness of the Au plating film 54 may be 0.01 μm or more and 1 μm or less. The thickness of the Au plating film 54 may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0101] In this embodiment, an example has been shown in which the plating film 51 includes the Ni plating film 52, the Pd plating film 53, and the Au plating film 54. However, the plating film 51 may have a layered structure including only the Ni plating film 52 and the Au plating film 54 stacked in this order from the first electrode 18 side. Of course, the plating film 51 may have a single-layer structure consisting of the Ni plating film 52, the Pd plating film 53, or the Au plating film 54.

[0102] 8F , protective tape 45 is peeled off from second main surface 4 and second electrode 24. This step includes irradiating adhesive layer 47 of protective tape 45 with ultraviolet light to reduce the adhesive strength of adhesive layer 47. This step also includes peeling base film 46 together with adhesive layer 47 from second electrode 24.

[0103] 8G , the wafer 2 is cut along a plurality of lines 12 to cut. The wafer 2 may be cut (cut) in the vertical direction Z by a dicing blade, or may be cut (cleaved) in the vertical direction Z by a cleaving method utilizing a laser light irradiation process. In the cleaving method, a modified layer in which part of the crystal structure is modified is formed inside the wafer 2 by laser light irradiation, and the wafer 2 is cleaved in the vertical direction Z starting from the modified layer. Through the processes including those described above, the semiconductor device SD1 (a SiC semiconductor device in this embodiment) is manufactured.

[0104] As described above, the wafer structure 1A includes the wafer 2, the first electrode 18, the second electrode 24, and the protective tape 45. The wafer 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The first electrode 18 covers the first main surface 3. The second electrode 24 covers the inner portion of the second main surface 4 so as to expose the peripheral portion of the second main surface 4. The protective tape 45 is adhered to the peripheral portion of the second main surface 4 and the second electrode 24. The protective tape 45 has a property that its adhesion to the peripheral portion of the second main surface 4 is stronger than its adhesion to the second electrode 24.

[0105] This configuration can prevent the protective tape 45 from peeling off from the second main surface 4 and the second electrode 24. As a result, when the wafer structure 1A is subjected to a manufacturing method for the semiconductor device SD1, manufacturing defects due to peeling of the protective tape 45 can be prevented. Therefore, it is possible to provide a wafer structure 1A that contributes to the manufacturing of a highly reliable semiconductor device SD1. For example, when the wafer structure 1A is immersed in a plating solution, it is possible to prevent the plating solution from entering the region between the second main surface 4 and the protective tape 45. This prevents abnormal plating film formation on the second electrode 24.

[0106] When the second electrode 24 has a plating reaction rate higher than the plating reaction rate of the wafer 2, the second electrode 24 preferably exposes the peripheral edge of the wafer 2 as a plating reaction inhibiting portion 25. In other words, the peripheral edge of the wafer 2 is preferably made of a material that inhibits plating film formation.

[0107] In this case, it is preferable that the protective tape 45 be attached to the plating reaction inhibiting portion 25. This configuration can prevent the plating solution from entering the region between the plating reaction inhibiting portion 25 and the protective tape 45. Furthermore, even if the plating solution does enter the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 can prevent abnormal plating film formation.

[0108] The wafer 2 preferably includes a SiC single crystal. In this case, the second electrode 24 preferably exposes the SiC single crystal from the peripheral portion of the second main surface 4. The protective tape 45 is also preferably attached to the SiC single crystal at the peripheral portion of the second main surface 4. The SiC single crystal has physical properties that make it difficult for metal to deposit thereon by plating. Therefore, even if a plating solution penetrates into the region between the second main surface 4 and the protective tape 45, the SiC single crystal can suppress abnormal plating film formation.

[0109] The wafer 2 preferably has a thickness of less than 200 μm. This configuration can reduce the on-resistance caused by the thickness of the wafer 2. Furthermore, the protective tape 45 allows the wafer 2, which is relatively thin, to be handled while suppressing deformation of the wafer 2.

[0110] The second electrode 24 preferably exposes the entire periphery of the second main surface 4. In this case, the protective tape 45 is preferably attached to the entire periphery of the second main surface 4. This configuration can prevent the protective tape 45 from peeling off from the second main surface 4 along the entire periphery of the second main surface 4. Furthermore, it can prevent the plating solution from entering the region between the second main surface 4 and the protective tape 45 along the entire periphery of the second main surface 4.

[0111] The exposed width W of the plating reaction inhibition portion 25 (the peripheral portion of the second main surface 4) is preferably larger than the thickness of the second electrode 24. The exposed width W is preferably larger than the thickness of the wafer 2. These configurations can appropriately reduce the risk of the plating solution coming into contact with the second electrode 24.

[0112] The second main surface 4 preferably has grinding marks. In this case, the second electrode 24 preferably has the grinding marks exposed at the peripheral portion of the second main surface 4. The protective tape 45 is also preferably attached to the peripheral portion having the grinding marks. With this configuration, the adhesion of the protective tape 45 to the peripheral portion of the second main surface 4 can be increased by the grinding marks.

[0113] The second main surface 4 is preferably a flat surface. In other words, the second main surface 4 preferably does not have a step recessed toward the first main surface 3. This configuration can appropriately prevent the formation of a fragile portion of the wafer 2 on the second main surface 4. In particular, this configuration is preferably applied to a wafer 2 having a thickness of less than 200 μm.

[0114] The wafer structure 1A may include a plating film 51 covering the first electrode 18. In this case, the second electrode 24 preferably exposes the peripheral portion of the wafer 2 as a plating reaction inhibiting portion 25 that inhibits the formation of the plating film 51. The plating film 51 may include at least one of a Ni plating film 52, a Pd plating film 53, and an Au plating film 54.

[0115] The wafer structure 1A may include a plurality of device regions 10 set inward of the first main surface 3. In this case, it is preferable that the second electrode 24 exposes an area outside the plurality of device regions 10 in a plan view. According to this configuration, the semiconductor device SD1 having the second electrode 24 can be appropriately manufactured.

[0116] From another perspective, the manufacturing method of the semiconductor device SD1 includes a step of preparing a wafer structure 1A, a step of forming a second electrode 24, and a step of adhering a protective tape 45. In the step of preparing the wafer structure 1A, the wafer structure 1A is prepared, which includes a wafer 2 having a first surface on one side and a second main surface 4 on the other side, and a first electrode 18 covering the first surface.

[0117] In the step of forming the second electrode 24, the second electrode 24 is formed to cover the inner portion of the second main surface 4 so as to expose the peripheral portion of the second main surface 4. In the step of adhering the protective tape 45, the protective tape 45, which has a property that its adhesion to the peripheral portion of the second main surface 4 is stronger than its adhesion to the second electrode 24, is adhered to the peripheral portion of the second main surface 4 and the second electrode 24.

[0118] This manufacturing method can prevent the protective tape 45 from peeling off from the second main surface 4 and the second electrode 24. This can prevent manufacturing defects caused by peeling of the protective tape 45. Therefore, a manufacturing method can be provided that contributes to the manufacturing of a highly reliable semiconductor device SD1. For example, when the wafer 2 is immersed in a plating solution with the protective tape 45 attached, the plating solution can be prevented from penetrating into the region between the second main surface 4 and the protective tape 45. This prevents abnormal plating film formation on the second electrode 24.

[0119] When the second electrode 24 has a plating reaction rate higher than the plating reaction rate of the wafer 2, the second electrode 24 preferably exposes the peripheral edge of the wafer 2 as a plating reaction inhibiting portion 25. In other words, the peripheral edge of the wafer 2 is preferably made of a material that inhibits plating film formation.

[0120] In this case, it is preferable that the protective tape 45 be attached to the plating reaction inhibiting portion 25. This manufacturing method can prevent the plating solution from entering the region between the plating reaction inhibiting portion 25 and the protective tape 45. Furthermore, even if the plating solution does enter the region between the second main surface 4 and the protective tape 45, the plating reaction inhibiting portion 25 can prevent abnormal plating film formation.

[0121] The manufacturing method of the semiconductor device SD1 preferably further includes the step of immersing the wafer structure 1A with the protective tape 45 attached in a plating solution to form a plating film 51 on the first electrode 18. This manufacturing method can prevent the plating solution from penetrating into the region between the second main surface 4 and the protective tape 45. This can prevent abnormal plating film formation on the second electrode 24.

[0122] The step of forming the plating film 51 preferably includes a step of rocking the wafer structure 1A in the plating solution. This manufacturing method allows bubbles generated during the plating reaction to diffuse into the solution, thereby preventing defects in the formation of the plating film 51 caused by bubbles. This manufacturing method also allows the protective tape 45 to protect the second electrode 24 from the plating solution, while also preventing deformation of the wafer 2 in the plating solution.

[0123] This suppresses abnormal formation of plating film 51 on second electrode 24 and also suppresses cracks in wafer 2. In particular, a relatively thin wafer 2 of less than 200 μm is prone to deformation due to stress from the plating solution during the rocking process, but protective tape 45 can appropriately suppress deformation of the relatively thin wafer 2.

[0124] The step of forming the plating film 51 may include at least one of the steps of immersing the wafer structure 1A in a Ni plating solution to form a Ni plating film 52, immersing the wafer structure 1A in a Pd plating solution to form a Pd plating film 53, and immersing the wafer structure 1A in an Au plating solution to form an Au plating film 54. According to this manufacturing method, the protective tape 45 can suppress at least one of abnormal formation of the Ni plating film 52, the Pd plating film 53, and the Au plating film 54 on the second main surface 4 side.

[0125] The wafer 2 preferably includes a SiC single crystal. In this case, the second electrode 24 is preferably formed so as to expose the SiC single crystal from the peripheral portion of the second main surface 4. The protective tape 45 is preferably attached to the SiC single crystal at the peripheral portion of the second main surface 4. The SiC single crystal has physical properties that make it difficult for metal to be deposited by a plating method. Therefore, even if a plating solution penetrates into the region between the second main surface 4 and the protective tape 45, the SiC single crystal can suppress abnormal plating film formation.

[0126] In the step of preparing the wafer structure 1A, it is preferable to prepare the wafer structure 1A including the wafer 2 having a thickness of 200 μm or more. In this case, it is preferable that the method of manufacturing the semiconductor device SD1 includes a step of thinning the wafer 2 to a thickness of less than 200 μm prior to the step of forming the second electrode 24.

[0127] According to this manufacturing method, up until the thinning step of the wafer 2, the wafer 2 can be handled while suppressing deformation of the wafer 2 by using the relatively thick wafer 2. Then, in the thinning step of the wafer 2, it is possible to reduce the on-resistance caused by the thickness of the wafer 2. Then, after the step of attaching the protective tape 45, the wafer 2 can be handled while suppressing deformation of the relatively thin wafer 2 by using the protective tape 45.

[0128] The thinning step of the wafer 2 may include a step of grinding the entire surface of the second main surface 4 by a grinding method. In this case, the second electrode 24 is preferably formed so as to expose grinding marks at the peripheral portion of the second main surface 4. Furthermore, the protective tape 45 is preferably attached to the peripheral portion having the grinding marks. According to this manufacturing method, the adhesion of the protective tape 45 to the peripheral portion of the second main surface 4 can be increased by the grinding marks.

[0129] Fig. 10 is a plan view of the wafer structure 1B according to the second embodiment as seen from the first main surface 3 side. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 10. Fig. 12 is an enlarged cross-sectional view showing a main part of the functional device 13 shown in Fig. 11. Fig. 13 is a schematic cross-sectional view of the wafer structure 1B shown in Fig. 10.

[0130] 10 to 12, the wafer structure 1B has a configuration different from the wafer structure 1A described above in that the functional device 13 includes a MISFET instead of an SBD. In Fig. 11, the functional device 13 is shown in a simplified manner by dashed lines.

[0131] In this embodiment, the MISFET is a trench gate type. The other configurations of the wafer structure 1B are substantially the same as those of the wafer structure 1A. The following describes the differences between the wafer structure 1B and the wafer structure 1A. The following also describes the configuration of one device region 10.

[0132] The wafer structure 1B includes a p-type body region 60 formed in the device region 10 in a surface layer portion of the first main surface 3. The body region 60 is formed at an interval from the bottom of the first region 7 toward the first main surface 3, and extends in a layered manner in the surface layer portion of the first main surface 3. The body region 60 may be formed over the entire first main surface 3.

[0133] The wafer structure 1B includes an n-type source region 61 formed in a surface layer portion of the body region 60 in the device region 10. The source region 61 may be formed in an inner portion of the device region 10 with a gap therebetween from the periphery of the device region 10. The source region 61 has a higher n-type impurity concentration than the first region 7. The source region 61 is formed with a gap therebetween from the bottom of the body region 60 toward the first main surface 3, and extends in a layered manner in the surface layer portion of the first main surface 3. The source region 61 forms a channel together with the first region 7 in the body region 60.

[0134] The wafer structure 1B includes a plurality of first trench structures 62 formed on the first main surface 3 in the device region 10. The first trench structures 62 may be referred to as "trench gate structures." The plurality of first trench structures 62 control channel inversion and non-inversion. The plurality of first trench structures 62 extend through the body region 60 and the source region 61 to the first region 7. The plurality of first trench structures 62 may be arranged at intervals in the first direction X in a plan view and formed in strip shapes extending in the second direction Y. The plurality of first trench structures 62 are formed at intervals from the bottom of the first region 7 toward the first main surface 3.

[0135] Each first trench structure 62 includes a first trench 63, a first insulating film 64, and a first buried electrode 65. The first trench 63 is formed in the first main surface 3 and defines the wall surface of the first trench 63. The first insulating film 64 covers the wall surface of the first trench 63. The first buried electrode 65 is buried in the first trench 63 with the first insulating film 64 sandwiched between them. The first buried electrode 65 faces the channel with the first insulating film 64 sandwiched between them.

[0136] The wafer structure 1B includes a plurality of second trench structures 66 formed on the first main surface 3 in the device region 10. The second trench structures 66 may also be referred to as "trench source structures." Each of the plurality of second trench structures 66 is formed in a region between two adjacent first trench structures 62.

[0137] The second trench structures 66 may each be formed in a strip shape extending in the second direction Y in a plan view. The second trench structures 66 extend through the body region 60 and the source region 61 to the first region 7. The second trench structures 66 are formed at intervals from the bottom of the first region 7 toward the first main surface 3, and are deeper than the first trench structures 62.

[0138] Each second trench structure 66 includes a second trench 67, a second insulating film 68, and a second buried electrode 69. The second trench 67 is formed in the first main surface 3 and defines the wall surface of the second trench 67. The second insulating film 68 covers the wall surface of the second trench 67. The second buried electrode 69 is buried in the second trench 67 with the second insulating film 68 sandwiched therebetween.

[0139] The wafer structure 1B includes a plurality of p-type contact regions 70 formed in the device region 10 within the wafer 2 in regions along the plurality of second trench structures 66. The plurality of contact regions 70 have a higher p-type impurity concentration than the body region 60. Each contact region 70 covers the sidewall and bottom wall of each second trench structure 66 and is electrically connected to the body region 60.

[0140] The wafer structure 1B includes a plurality of p-type well regions 71 formed in the device region 10 within the wafer 2 in regions along the plurality of second trench structures 66. Each well region 71 has a p-type impurity concentration higher than that of the body region 60 and lower than that of the contact region 70. Each well region 71 covers the corresponding second trench structure 66 with the corresponding contact region 70 sandwiched therebetween. Each well region 71 covers the sidewalls and bottom wall of the corresponding second trench structure 66 and is electrically connected to the body region 60.

[0141] The wafer structure 1B includes a main surface insulating film 16 that covers the first main surface 3 in the device region 10. The main surface insulating film 16 is continuous with the first insulating film 64 and the second insulating film 68, and exposes the first buried electrode 65 and the second buried electrode 69. In this embodiment, the main surface insulating film 16 covers the peripheral portions of the device region 10 (boundaries between multiple device regions 10). In other words, the main surface insulating film 16 covers the entire first main surface 3. Of course, the main surface insulating film 16 may expose the peripheral portions of the device region 10 (boundaries between multiple device regions 10).

[0142] The wafer structure 1B includes an interlayer insulating film 72 that covers the main surface insulating film 16 in the device region 10. The interlayer insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 72 covers the plurality of first trench structures 62 and the plurality of second trench structures 66.

[0143] In this embodiment, the interlayer insulating film 72 covers the peripheral portion of the device region 10 (the boundary portion between multiple device regions 10) with the main surface insulating film 16 sandwiched therebetween. The interlayer insulating film 72 may cover the entire first main surface 3. Of course, when the main surface insulating film 16 exposes the first main surface 3 in the peripheral portion of the device region 10, the interlayer insulating film 72 may also expose the first main surface 3 in the peripheral portion of the device region 10.

[0144] As in the first embodiment, the wafer structure 1B includes a first buried electrode 65 disposed on an interlayer insulating film 72 in the device region 10. The first electrode 18 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the first main surface 3 side.

[0145] In this embodiment, the first electrode 18 includes a gate electrode 73 and a source electrode 74. In this embodiment, the gate electrode 73 is disposed in a region close to the center of one side of the device region 10 in a plan view. The gate electrode 73 may also be disposed in a corner of the device region 10 in a plan view. In this embodiment, the gate electrode 73 is formed in a quadrangular shape in a plan view.

[0146] The source electrode 74 is disposed on the interlayer insulating film 72 at a distance from the gate electrode 73. In this embodiment, the source electrode 74 is formed in a polygonal shape having a recess that is recessed along the gate electrode 73 in a plan view. Of course, the source electrode 74 may also be formed in a quadrangular shape in a plan view. The source electrode 74 penetrates the interlayer insulating film 72 and the main surface insulating film 16, and is electrically connected to the body region 60, the source region 61, and the plurality of second trench structures 66.

[0147] The wafer structure 1B includes a gate wiring electrode 75 extending from the gate electrode 73 onto the interlayer insulating film 72 in the device region 10. Like the gate electrode 73 (first electrode 18), the gate wiring electrode 75 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the first main surface 3 side. The gate wiring electrode 75 is formed in a strip shape extending along the periphery of the device region 10 so as to intersect (specifically, perpendicular to) the ends of the multiple first trench structures 62 in a plan view. The gate wiring electrode 75 penetrates the interlayer insulating film 72 and is electrically connected to the multiple first trench structures 62.

[0148] The wafer structure 1B includes an insulating film 19 that covers the first electrodes 18 in the device region 10. As in the first embodiment, the insulating film 19 has a laminated structure including an inorganic insulating film 22 and an organic insulating film 23 that are laminated in this order from the first electrode 18 side. In this embodiment, the insulating film 19 covers the peripheral edge of the gate electrode 73 and the peripheral edge of the source electrode 74 at intervals inward from the periphery of the device region 10. The insulating film 19 covers the entire area of ​​the gate wiring electrode 75.

[0149] The insulating film 19 defines a plurality of pad openings 20 that expose the inner portions of the gate electrode 73 and the source electrode 74, and defines street openings 21 that expose the interlayer insulating film 72 at the periphery of the device region 10. In this embodiment, the plurality of pad openings 20 include a gate pad opening 76 that exposes the inner portion of the gate electrode 73 and a source pad opening 77 that exposes the inner portion of the source electrode 74.

[0150] In this embodiment, the gate pad opening 76 is defined in a rectangular shape along the periphery of the gate electrode 73 in plan view. The source pad opening 77 is formed in a polygonal shape along the periphery of the source electrode 74 in plan view. The street opening 21 is formed in the same manner as in the first embodiment.

[0151] The organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the gate pad opening 76. The organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the source pad opening 77. The organic insulating film 23 may expose the edge of the inorganic insulating film 22 in the street opening 21. Of course, the organic insulating film 23 may cover the entire area of ​​the inorganic insulating film 22.

[0152] The wafer structure 1B includes a second electrode 24 covering the second main surface 4. In this embodiment, the second electrode 24 is formed as a drain electrode and is electrically connected to the second region 8 exposed from the second main surface 4. The second electrode 24 is formed in the same manner as in the first embodiment. Other details of the second electrode 24 are the same as those in the first embodiment.

[0153] Figures 14A to 14G are cross-sectional views showing a method for manufacturing the semiconductor device SD2 relating to the wafer structure 1B shown in Figure 10. Figures 14A to 14G also show part of the manufacturing process of the wafer structure 1B.

[0154] 14A , first, a wafer structure 1B is prepared before the step of forming the second electrode 24. The wafer structure 1B includes, in each device region 10, a body region 60, a source region 61, a first trench structure 62, a second trench structure 66, a contact region 70, a well region 71, a main surface insulating film 16, an interlayer insulating film 72, a gate electrode 73 (first electrode 18), a source electrode 74 (first electrode 18), a gate wiring electrode 75, and an insulating film 19. The wafer structure 1A before the step of forming the second electrode 24 includes a wafer 2 having a thickness of 200 μm or more. The wafer 2 may have a thickness of 200 μm or more and 1000 μm or less. The wafer 2 preferably has a thickness of 250 μm or more and 500 μm or less.

[0155] Next, referring to Fig. 14B, a thinning step of the wafer 2 is performed. The wafer 2 may be thinned from the second main surface 4 side by at least one of a grinding method and an etching method. In this embodiment, the wafer 2 is thinned by a grinding method on the second main surface 4. In this embodiment, the wafer 2 is ground until the thickness is less than 200 µm. As a result, grinding marks are formed on the second main surface 4.

[0156] 14C, the step of forming the second electrode 24 is carried out. The second electrode 24 is formed through steps similar to those shown in FIGS. 9A to 9C. As a result, a plating reaction inhibiting portion 25 having a layout corresponding to the layout of the mask jig 50 is formed in the peripheral portion of the second main surface 4.

[0157] 14D, protective tape 45 is then attached to second electrode 24 and plating reaction inhibiting portion 25 (peripheral edge portion of second main surface 4). This completes the manufacturing of wafer structure 1B shown in FIGS. 10 to 13. Wafer structure 1B is handled with protective tape 45 attached.

[0158] 14E, a plating film 51 is formed on the first electrode 18 by plating. In this embodiment, the step of forming the plating film 51 includes a step of forming a gate plating film 78 on the gate electrode 73 and a step of forming a source plating film 79. The plating film 51 (gate plating film 78 and source plating film 79) may be considered as one component of the wafer structure 1B.

[0159] As in the first embodiment, the process of forming the plating film 51 includes the steps of forming the Ni plating film 52, the Pd plating film 53, and the Au plating film 54 in this order from the first electrode 18 side. The Ni plating film 52, the Pd plating film 53, and the Au plating film 54 are formed in the pad openings 20 (the gate pad opening 76 and the source pad opening 77) in the same manner as in the first embodiment.

[0160] Of course, the plating film 51 may have a laminated structure including only the Ni plating film 52 and the Au plating film 54 laminated in this order from the first electrode 18 side. Alternatively, the plating film 51 may have a single-layer structure consisting of the Ni plating film 52, the Pd plating film 53, or the Au plating film 54.

[0161] 14F , protective tape 45 is peeled off from second main surface 4 and second electrode 24. This step includes irradiating adhesive layer 47 of protective tape 45 with ultraviolet light to reduce the adhesive strength of adhesive layer 47. This step also includes peeling base film 46 together with adhesive layer 47 from second electrode 24.

[0162] 14G, the wafer 2 is cut along the plurality of lines to cut 12. The wafer 2 may be cut (cut) by a dicing blade, or may be cut (cleaved) by a cleaving method utilizing a laser light irradiation process. Through the processes including those described above, the semiconductor device SD2 (a SiC semiconductor device in this embodiment) is manufactured.

[0163] As described above, the wafer structure 1B also provides the same effects as those described for the wafer structure 1A. Furthermore, the method for manufacturing the semiconductor device SD2 according to the wafer structure 1B also provides the same effects as those described for the method for manufacturing the semiconductor device SD2 according to the wafer structure 1A.

[0164] 15 is a plan view showing a wafer 2 according to a modified example that is applicable to each of the above-described embodiments. The mark 6 on the wafer 2 according to each of the above-described embodiments includes an orientation flat. In contrast, referring to FIG. 15, the mark 6 on the wafer 2 according to the modified example includes an orientation notch that is recessed in a tapered shape (tapered or triangular) on the side surface 5 toward the center of the first main surface 3.

[0165] The orientation notch may be recessed in the first direction X or the second direction Y (the a-axis direction or the m-axis direction) in a plan view. Of course, the mark 6 may include a first orientation notch recessed in the first direction X and a first orientation notch recessed in the second direction Y. Furthermore, the mark 6 may include at least one orientation flat and at least one orientation notch.

[0166] The second electrode 24 does not need to have a linearly extending portion along the orientation notch. The second electrode 24 covers the second main surface 4 at a distance inward from the orientation notch so as to expose the orientation notch. The second electrode 24 may expose the peripheral portion of the second main surface 4 in a circular shape. In other words, the plating reaction inhibition portion 25 may expose the peripheral portion of the second main surface 4 in a circular shape in the region along the mark 6 and the region outside the mark 6.

[0167] The edge of the protective tape 45 does not need to have a linear portion along the orientation notch, and may be formed in a circular shape around the entire periphery of the second main surface 4 in a plan view.

[0168] Fig. 16 is a schematic cross-sectional view showing the process of forming the second electrode 24 according to a first modified example applied to each of the above-described embodiments. Fig. 17 is a schematic cross-sectional view showing the process of forming the second electrode 24 according to a second modified example applied to each of the above-described embodiments. Fig. 18 is a schematic cross-sectional view showing the process of forming the second electrode 24 according to a third modified example applied to each of the above-described embodiments. In each of the above-described embodiments, the process of forming the second electrode 24 using a mask jig 50 has been described.

[0169] 16 , the second electrode 24 may be formed on the second main surface 4 by a lift-off method. In this case, a resist mask 81 may be formed on the second main surface 4 instead of the mask jig 50, and the resist mask 81 may be removed after the second electrode 24 is formed. In consideration of the number of steps and the load on the wafer 2, a process using the mask jig 50 is preferable.

[0170] 17 , the second electrode 24 may be shaped into a predetermined layout by etching. In this case, after the second electrode 24 is formed on the second main surface 4, a resist mask 82 having the predetermined layout is formed on the second electrode 24, and the second electrode 24 is shaped into the predetermined layout by etching via the resist mask 82. After unnecessary portions of the second electrode 24 are removed, the resist mask 82 is removed. Considering the number of steps and the load on the wafer 2, a process using a mask jig 50 is preferable.

[0171] 18 , the second electrode 24 may be formed into a predetermined layout by a grinding method. In this case, unnecessary portions of the second electrode 24 may be removed by bevel grinding the peripheral portion of the second electrode 24 (the peripheral portion of the second main surface 4). In this case, a portion of the wafer 2 may be removed along with a portion of the second electrode 24. That is, the plating reaction inhibition portion 25 may have a step 83 dug down toward the first main surface 3 at the peripheral portion of the second main surface 4. Considering the man-hours and the load on the wafer 2, a process using a mask jig 50 is preferable.

[0172] Although the embodiments have been described above, each embodiment may be implemented in other forms. For example, in the thinning process of the wafer 2 according to each of the above-described embodiments, the second region 8 may be removed to a thickness less than the thickness of the first region 7. Of course, in the thinning process of the wafer 2 according to each of the above-described embodiments, the entire second region 8 may be removed. In other words, a wafer 2 having a single-layer structure consisting of the first region 7 (SiC epitaxial layer) may be formed.

[0173] In these cases, in the step of adhering the protective tape 45, the protective tape 45 having a thickness greater than the thickness of the wafer 2 may be adhered to the second main surface 4. When a member that reinforces or supports the wafer 2 is provided on the first main surface 3, the protective tape 45 having a thickness smaller than the thickness of the wafer 2 may be adhered to the second main surface 4.

[0174] In each of the above-described embodiments, an example has been described in which the functional device 13 includes either an SBD or a MISFET. However, the functional device 13 may include both an SBD and a MISFET. That is, both the SBD and the MISFET may be formed in the same device region 10. Of course, in each of the above-described embodiments, the functional device 13 including an SBD and the functional device 13 including a MISFET may be formed in different device regions 10 on the same wafer 2.

[0175] In the second embodiment described above, an example has been described in which a trench gate type MISFET is formed as an example of the functional device 13. However, the functional device 13 may include a planar gate type MISFET instead of the trench gate type.

[0176] In the second embodiment described above, a p-type second region 8 may be employed instead of the n-type second region 8. In this case, the functional device 13 includes an IGBT (Insulated Gate Bipolar Transistor) instead of the MISFET. A specific configuration in this case can be obtained by replacing the "source" of the MISFET with the "emitter" of the IGBT and the "drain" of the MISFET with the "collector" of the IGBT in the above description.

[0177] In the above-described embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, in the above-described embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.

[0178] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "wafer structure" in the following clauses may be replaced with "wide bandgap semiconductor wafer structure," "SiC wafer structure," etc., as needed. Furthermore, the "semiconductor device" in the following clauses may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," etc., as needed.

[0179] [A1] A wafer structure (1A, 1B) including a wafer (2) having a first surface (3) on one side and a second surface (4) on the other side, a first electrode (18) covering the first surface (3), a second electrode (24) covering an inner portion of the second surface (4) so ​​as to expose a peripheral portion of the second surface (4), and a protective tape (45) having a property that its adhesion force to the peripheral portion of the second surface (4) is higher than its adhesion force to the second electrode (24), and attached to the peripheral portion of the second surface (4) and the second electrode (24).

[0180] [A2] A wafer structure (1A, 1B) described in A1, in which the second electrode (24) has a plating reaction rate higher than the plating reaction rate of the wafer (2), the peripheral portion of the wafer (2) is exposed as a plating reaction inhibiting portion (25), and the protective tape (45) is attached to the plating reaction inhibiting portion (25).

[0181] [A3] The wafer structure (1A, 1B) according to A1 or A2, wherein the wafer (2) includes a SiC single crystal, the second electrode (24) exposes the SiC single crystal from the peripheral portion of the second surface (4), and the protective tape (45) is attached to the SiC single crystal at the peripheral portion of the second surface (4).

[0182] [A4] A wafer structure (1A, 1B) according to any one of A1 to A3, wherein the wafer (2) has a thickness of less than 200 μm.

[0183] [A5] A wafer structure (1A, 1B) described in any one of A1 to A4, wherein the second electrode (24) has the entire periphery exposed, and the protective tape (45) is attached to the entire periphery.

[0184] [A6] A wafer structure (1A, 1B) according to any one of A1 to A5, wherein the exposed width (W) of the peripheral portion is greater than the thickness of the second electrode (24).

[0185] [A7] The wafer structure (1A, 1B) according to A6, wherein the exposed width (W) is greater than the thickness of the wafer (2).

[0186] [A8] A wafer structure (1A, 1B) described in any one of A1 to A7, wherein the wafer (2) has the second surface (4) having grinding marks, the second electrode (24) exposes the peripheral portion having the grinding marks, and the protective tape (45) is attached to the peripheral portion having the grinding marks.

[0187] [A9] A wafer structure (1A, 1B) according to any one of A1 to A8, wherein the second surface (4) is a flat surface.

[0188] [A10] The wafer structure (1A, 1B) according to any one of A1 to A9, further comprising a plating film (51) covering the first electrode (18).

[0189] [A11] The wafer structure (1A, 1B) according to A10, wherein the plating film (51) includes at least one of a Ni plating film (52), a Pd plating film (53), and an Au plating film (54).

[0190] [A12] A wafer structure (1A, 1B) according to any one of A1 to A11, further including a plurality of device regions (10) set in an inner portion of the first surface (3), and the second electrode (24) exposing an area outside the plurality of device regions (10) in a planar view.

[0191] [A13] A method for manufacturing a semiconductor device (SD1, SD2), comprising the steps of: preparing a wafer structure (1A, 1B) including a wafer (2) having a first surface (3) on one side and a second surface (4) on the other side, and a first electrode (18) covering the first surface (3); forming a second electrode (24) covering an inner portion of the second surface (4) so ​​as to expose the peripheral portion of the second surface (4); and adhering a protective tape (45) having a property that its adhesion strength to the peripheral portion of the second surface (4) is higher than its adhesion strength to the second electrode (24) to the peripheral portion of the second surface (4) and the second electrode (24).

[0192] [A14] A manufacturing method for a semiconductor device (SD1, SD2) described in A13, wherein the second electrode (24) has a plating reaction rate higher than the plating reaction rate of the wafer (2), and exposes the peripheral portion of the wafer (2) as a plating reaction inhibiting portion (25).

[0193] [A15] A method for manufacturing a semiconductor device (SD1, SD2) according to A13 or A14, further comprising the step of immersing the wafer structure (1A, 1B) in a plating solution with the protective tape (45) attached thereto to form a plating film (51) on the first electrode (18).

[0194] [A16] A method for manufacturing a semiconductor device (SD1, SD2) according to A15, wherein the step of forming the plating film (51) includes a step of oscillating the wafer structure (1A, 1B) in the plating solution.

[0195] [A17] The method for manufacturing a semiconductor device (SD1, SD2) according to A15 or A16, wherein the step of forming the plating film (51) includes at least one of the steps of immersing the wafer structure (1A, 1B) in a Ni plating solution to form a Ni plating film (52), immersing the wafer structure (1A, 1B) in a Pd plating solution to form a Pd plating film (53), and immersing the wafer structure (1A, 1B) in an Au plating solution to form an Au plating film (54).

[0196] [A18] A method for manufacturing a semiconductor device (SD1, SD2) according to any one of A13 to A17, wherein the wafer (2) includes a SiC single crystal, the second electrode (24) exposes the SiC single crystal from the peripheral portion of the second surface (4), and the protective tape (45) is attached to the SiC single crystal at the peripheral portion of the second surface (4).

[0197] [A19] A method for manufacturing a semiconductor device (SD1, SD2) according to any one of A13 to A18, further comprising the steps of: preparing the wafer structure (1A, 1B) including the wafer (2) having a thickness of 200 μm or more; and thinning the wafer (2) to a thickness of less than 200 μm prior to the step of forming the second electrode (24).

[0198] [A20] A method for manufacturing a semiconductor device (SD1, SD2) according to A19, wherein the thinning step of the wafer (2) includes a step of grinding the second surface (4) by a grinding method.

[0199] Although the embodiments have been described in detail above, these are merely specific examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiments.

[0200] 1A Wafer structure 1B Wafer structure 2 Wafer 3 First main surface 4 Second main surface 10 Device region 18 First electrode 24 Second electrode 25 Plating reaction inhibitor 45 Protective tape 51 Plating film 52 Ni plating film 53 Pd plating film 54 Au plating film W Exposed width SD1 Semiconductor device SD2 Semiconductor device

Claims

1. a wafer having a first surface on one side and a second surface on the other side; a first electrode covering the first surface; a second electrode covering an inner portion of the second surface so as to expose a peripheral portion of the second surface; a protective tape having a higher adhesion strength to the peripheral portion of the second surface than to the second electrode, the protective tape being attached to the peripheral portion of the second surface and the second electrode.

2. the second electrode has a plating reaction rate higher than a plating reaction rate of the wafer, and exposes the peripheral portion of the wafer as a plating reaction inhibiting portion; The wafer structure according to claim 1 , wherein the protective tape is attached to the plating reaction inhibiting portion.

3. the wafer comprises a SiC single crystal; the second electrode exposes the SiC single crystal from the peripheral portion of the second surface, The wafer structure according to claim 1 , wherein the protective tape is attached to the SiC single crystal at the peripheral portion of the second surface.

4. The wafer structure of claim 1 , wherein the wafer has a thickness of less than 200 μm.

5. the second electrode has an exposed entire periphery; The wafer structure according to claim 1 , wherein the protective tape is attached to the entire periphery of the peripheral portion.

6. The wafer structure of claim 1 , wherein an exposed width of the peripheral portion is greater than a thickness of the second electrode.

7. The wafer structure of claim 6 , wherein the exposed width is greater than a thickness of the wafer.

8. the wafer has the second surface having grinding marks; the second electrode exposes the peripheral portion having the grinding marks; The wafer structure according to claim 1 , wherein the protective tape is attached to the peripheral portion having the grinding marks.

9. The wafer structure of claim 1 , wherein the second surface comprises a flat surface.

10. The wafer structure according to claim 1 , further comprising a plating film covering the first electrode.

11. The wafer structure according to claim 10 , wherein the plating film includes at least one of a Ni plating film, a Pd plating film, and an Au plating film.

12. further comprising a plurality of device regions defined in an inner portion of the first surface; 10. The wafer structure according to claim 1, wherein the second electrode exposes a region outside a plurality of the device regions in a plan view.

13. providing a wafer structure including a wafer having a first surface on one side and a second surface on the other side, and a first electrode covering the first surface; forming a second electrode covering an inner portion of the second surface so as to expose a peripheral portion of the second surface; and adhering a protective tape to the peripheral portion of the second surface and the second electrode, the protective tape having a higher adhesion strength to the peripheral portion of the second surface than to the second electrode.

14. The method for manufacturing a semiconductor device according to claim 13 , wherein the second electrode has a plating reaction rate higher than a plating reaction rate of the wafer, and exposes the peripheral portion of the wafer as a plating reaction inhibiting portion.

15. The wafer comprising a SiC single crystal; the second electrode exposes the SiC single crystal from the peripheral portion of the second surface, The method for manufacturing a semiconductor device according to claim 13 , wherein the protective tape is attached to the SiC single crystal at the peripheral portion of the second surface.

16. 16. The method for manufacturing a semiconductor device according to claim 13, further comprising the step of immersing the wafer structure with the protective tape attached in a plating solution to form a plating film on the first electrode.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the step of forming the plating film includes a step of rocking the wafer structure in the plating solution.

18. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the plating film forming step includes at least one of a step of immersing the wafer structure in a Ni plating solution to form a Ni plating film, a step of immersing the wafer structure in a Pd plating solution to form a Pd plating film, and a step of immersing the wafer structure in a Au plating solution to form an Au plating film.

19. providing the wafer structure including the wafer having a thickness of 200 μm or greater; The method for manufacturing a semiconductor device according to any one of claims 13 to 15, further comprising the step of thinning the wafer to a thickness of less than 200 μm prior to the step of forming the second electrode.

20. 20. The method for manufacturing a semiconductor device according to claim 19, wherein said wafer thinning step includes the step of grinding said second surface by a grinding method.