Field effect transistor

Abstract

A field effect transistor (10) according to the present invention is provided with: an electron transit layer (26); an electron supply layer (28) which is arranged on the electron transit layer so as to generate a two-dimensional electron gas within the electron transit layer; and a source electrode (32), a drain electrode (34) and a gate structure (36), which are arranged on the electron supply layer (28). The electron transit layer (26) comprises an active region (26R1) in which the two-dimensional electron gas is generated, and an inactive region (26R2) which surrounds the active region when viewed in plan. The source electrode (32), the drain electrode (34) and the gate structure (36) are arranged on the electron supply layer (28) in a region that corresponds to the active region (26R1). The source electrode (32) comprises a source contact outer peripheral part (32CP) which surrounds the drain electrode (34) and the gate structure (36) when viewed in plan, while being in contact with the electron supply layer (28) along the outer periphery of the electron supply layer (28) corresponding to the boundary between the active region (26R1) and the inactive region (26R2).

Description

field-effect transistor

[0001] The present disclosure relates to field effect transistors.

[0002] Currently, high electron mobility transistors (HEMTs), which are a type of field-effect transistor (FET) using III-V semiconductors such as gallium nitride (GaN), are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel) (see, for example, Patent Document 1). Power transistors using HEMTs are recognized as devices that offer lower on-resistance and are capable of high-speed, high-frequency operation compared to typical silicon (Si) power transistors.

[0003] Japanese Patent Application Laid-Open No. 2017-73506

[0004] Because the gate capacitance of a HEMT is relatively small for a power transistor, surges due to static electricity or the like may not be sufficiently absorbed within the device. In particular, during the dicing process in which a semiconductor wafer is diced into chips, the semiconductor wafer is mechanically cut by rotating a blade at high speed, making it easy for surges to enter the transistor. If surge resistance is low, transistor characteristics may deteriorate due to surges, such as an increase in on-resistance and a decrease in breakdown voltage. The transistor is formed in an active region where 2DEG is generated. Therefore, there is still room for improvement in terms of resistance to surges that may enter the active region.

[0005] A field-effect transistor according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer disposed above the substrate, a second nitride semiconductor layer having a larger bandgap than the first nitride semiconductor layer and disposed on the first nitride semiconductor layer to generate two-dimensional electron gas in the first nitride semiconductor layer near an interface with the first nitride semiconductor layer, and a source electrode, a drain electrode, and a gate structure disposed on the second nitride semiconductor layer. The first nitride semiconductor layer includes an active region where the two-dimensional electron gas is generated and a non-active region surrounding the active region in a planar view. The source electrode, the drain electrode, and the gate structure are disposed on the second nitride semiconductor layer in a region corresponding to the active region. The source electrode includes a source contact periphery that surrounds the drain electrode and the gate structure in a planar view and is in contact with the second nitride semiconductor layer along the periphery of the second nitride semiconductor layer corresponding to the boundary between the active region and the non-active region.

[0006] A field effect transistor according to one aspect of the present disclosure can improve surge resistance.

[0007] FIG. 1 is a schematic plan view of an exemplary field effect transistor according to a first embodiment. FIG. 2 is a schematic cross-sectional view taken along line F2-F2 in FIG. 1. FIG. 3 is a schematic plan view showing an exemplary upper layer wiring structure of the field effect transistor of FIG. 1. FIG. 4 is a schematic plan view of an exemplary field effect transistor according to a second embodiment. FIG. 5 is a schematic plan view of an exemplary field effect transistor according to a third embodiment. FIG. 6 is a schematic plan view of an exemplary field effect transistor according to a fourth embodiment. FIG. 7 is a schematic plan view of an exemplary field effect transistor according to a fifth embodiment. FIG. 8 is a schematic plan view of an exemplary field effect transistor according to a sixth embodiment. FIG. 9 is a schematic cross-sectional view taken along line F9-F9 in FIG. 8. FIG. 10 is a schematic plan view of an exemplary field effect transistor according to a seventh embodiment. FIG. 11 is a schematic plan view of an exemplary field effect transistor according to an eighth embodiment. FIG. 12 is a schematic plan view of an exemplary field effect transistor according to a ninth embodiment. FIG. 13 is a schematic cross-sectional view taken along line F13-F13 in FIG. 12. FIG. 14 is a schematic plan view of an exemplary field effect transistor according to a tenth embodiment. FIG. 15 is a schematic plan view of an exemplary field-effect transistor according to the eleventh embodiment.

[0008] Hereinafter, several embodiments of field-effect transistors according to the present disclosure will be described with reference to the accompanying drawings. Note that components shown in the drawings may be partially enlarged for clarity and understanding, and are not necessarily drawn to scale. Also, to facilitate understanding, hatched lines may be omitted in cross-sectional views, and components may be shown with hatched lines in plan views. The accompanying drawings are merely illustrative of embodiments of the present disclosure, and should not be considered to limit the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] First Embodiment Fig. 1 is a schematic plan view of an exemplary field effect transistor (FET) 10 according to a first embodiment. Fig. 2 is a schematic cross-sectional view of the FET 10 taken along line F2-F2 in Fig. 1. The FET 10 can be configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. Representative examples of nitride semiconductors are gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN), and generally, Al ｘ In ｙ Ga １－ｘ－ｙ N (0≦x≦1, 0≦y≦1, 0≦x+y≦1).

[0011] Unless otherwise explicitly stated, the term "planar view" used in this disclosure refers to viewing an object (FET 10 or a component thereof) in the Z direction of the mutually orthogonal X, Y, and Z axes shown in each drawing. Hereinafter, the Y direction may be referred to as the first direction, and the X direction may be referred to as the second direction. For ease of understanding, the +Z direction may be referred to as up, the −Z direction as down, the +X direction as right, and the −X direction as left.

[0012] As shown in Fig. 1, the FET 10 includes a plurality of (four in the example of Fig. 1) FET cells 12A, 12B, 12C, and 12D. In the following description, when the FET cells 12A to 12D are not to be distinguished from one another, they are collectively referred to as FET cells 12. In the example of Fig. 1, for ease of understanding, the FET 10 is shown as including four FET cells 12, but the FET 10 can be configured as a power transistor (a power switching FET) by including, for example, tens to hundreds of FET cells 12.

[0013] In the example of Figure 1, FET cell 12A includes FET elements 14A1 and 14A2. Similarly, FET cell 12B includes FET elements 14B1 and 14B2, FET cell 12C includes FET elements 14C1 and 14C2, and FET cell 12D includes FET elements 14D1 and 14D2. In the following description, when these FET elements 14A1, 14A2, 14B1, 14B2, 14C1, 14C2, 14D1, and 14D2 are not distinguished from one another, they will be collectively referred to as FET elements 14. Each FET element 14 is a part of a transistor structure (a HEMT in the examples of Figures 1 and 2) that contributes to the operation of FET 10.

[0014] [1. Cross-sectional structure of FET (HEMT)] Figure 2 shows the structure of the FET cell 12A and its surrounding structure taken along line F2-F2 in Figure 1. First, an exemplary cross-sectional structure of the FET element 14 will be described below with reference to Figure 2. Note that the cross-sectional structure of the FET element 14 is the same for each FET cell 12.

[0015] The FET 10 includes a substrate 22, a buffer layer 24 formed on the substrate 22, an electron transit layer 26 formed on the buffer layer 24, and an electron supply layer 28 formed on the electron transit layer 26. The substrate 22 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate material. For example, the substrate 22 is a conductive Si substrate. The thickness of the substrate 22 may be, for example, 200 μm or more and 1500 μm or less. Note that the Z direction shown in each figure is a direction perpendicular to the main surface of the substrate 22.

[0016] The buffer layer 24 is located between the substrate 22 and the electron transit layer 26 and may be formed of any material capable of suppressing wafer warpage and cracking due to a mismatch in thermal expansion coefficients between the substrate 22 and the electron transit layer 26. The buffer layer 24 may include one or more nitride semiconductor layers. For example, the buffer layer 24 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 24 may be formed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0017] In one example, the buffer layer 24 includes a first buffer layer formed on the substrate 22 and a second buffer layer formed on the first buffer layer. The first buffer layer is, for example, an AlN layer and may have a thickness of, for example, about 200 nm. The second buffer layer includes, for example, a plurality of AlGaN layers, each of which may have a thickness of, for example, about 100 nm. Note that, in order to suppress leakage current in the buffer layer 24, impurities may be introduced into a portion of the buffer layer 24 to make it semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 １６ cm －３ It may be more than that.

[0018] The electron transit layer 26 may be formed of a nitride semiconductor. The electron transit layer 26 corresponds to a first nitride semiconductor layer. For example, the electron transit layer 26 may be a GaN layer. The thickness of the electron transit layer 26 may be, for example, 0.1 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 26, an impurity may be introduced into a part of the electron transit layer 26 to make the electron transit layer 26 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the impurity concentration may be, for example, 1×10 at a peak concentration. １９ cm －３ It may be more than that.

[0019] The electron supply layer 28 may be formed of a nitride semiconductor. The electron supply layer 28 corresponds to a second nitride semiconductor layer. For example, the electron supply layer 28 may be an AlGaN layer. In an AlGaN layer, the band gap increases as the Al composition increases. Therefore, the electron supply layer 28, which is an AlGaN layer, has a larger band gap than the electron transit layer 26, which is a GaN layer. For example, the electron supply layer 28 may be formed of Al ｘ Ga １－ｘ The electron supply layer 28 is composed of N, where x is in the range of 0.1<x<0.4, more preferably 0.2<x<0.3, but is not necessarily limited to this range. The thickness of the electron supply layer 28 may be, for example, 5 nm or more and 20 nm or less.

[0020] The electron transit layer 26 and the electron supply layer 28 are made of nitride semiconductors with different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 26 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 28 form a lattice-mismatched junction. Due to spontaneous polarization of the electron transit layer 26 and the electron supply layer 28 and piezoelectric polarization caused by stress on the heterojunction of the electron supply layer 28, the energy level of the conduction band of the electron transit layer 26 near the heterojunction interface between the electron transit layer 26 and the electron supply layer 28 is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 30 spreads within the electron transit layer 26 near the heterojunction interface between the electron transit layer 26 and the electron supply layer 28 (e.g., at a distance of about several nanometers from the interface).

[0021] The electron transit layer 26 includes an active region 26R1 where 2DEG 30 can be generated and a non-active region 26R2 that surrounds the active region 26R1 in a planar view. The non-active region 26R2 is formed, for example, by removing the upper periphery of the electron transit layer 26 together with the periphery of the electron supply layer 28 located directly above it. Therefore, the electron transit layer 26 includes a side surface 26S1 at the boundary between the active region 26R1 and the non-active region 26R2, and the electron supply layer 28 includes a side surface 28S1 that is formed continuously with the side surface 26S1 of the electron transit layer 26. In the example of FIG. 2 , the side surface 28S1 of the electron supply layer 28 coincides with the side surface 26S1 of the electron transit layer 26 in a planar view. The side surface 26S1 of the electron transit layer 26 serves as a step wall that forms a step between the active region 26R1 and the non-active region 26R2.

[0022] In the example of Figure 2, the side surface 28S1 of the electron supply layer 28 and the side surface 26S1 of the electron transit layer 26 are formed as vertical surfaces, but they may also be formed as inclined surfaces that slope outward from the upper end of the side surface 28S1 toward the lower end of the side surface 26S1.

[0023] The electron transit layer 26 includes an outer peripheral end surface 26S2 at the chip outer peripheral edge of the FET 10. Therefore, the inactive region 26R2 corresponds to the region of the electron transit layer 26 between the outer peripheral end surface 26S2 and the side surface 26S1. In the example of FIG. 2 , the inactive region 26R2 corresponds to the region of the electron transit layer 26 on which the electron supply layer 28 is not present. Therefore, no 2DEG 30 is generated in the inactive region 26R2. The inactive region 26R2 is formed along the outer peripheral end surface 26S2 of the electron transit layer 26 in a plan view (see FIG. 1 ).

[0024] The active region 26R1 corresponds to a region of the electron transit layer 26 that is located more inward than the inactive region 26R2 in plan view. In the example of FIG. 2 , the active region 26R1 corresponds to a region of the electron transit layer 26 on which the electron supply layer 28 exists (whereby the 2DEG 30 can be generated).

[0025] The inactive region 26R2 can be formed by, for example, using an etching method to remove the outer periphery of the electron supply layer 28 and the upper periphery of the electron transit layer 26 located immediately thereunder. However, the inactive region 26R2 is not limited to being formed by an etching method. For example, the inactive region 26R2 may be formed by using an ion implantation method to increase the resistance of the outer periphery of the electron supply layer 28 and the upper periphery of the electron transit layer 26 located immediately thereunder. However, since the etching method can be performed at lower cost than the ion implantation method, the use of the etching method is advantageous from the standpoint of cost.

[0026] The FET 10 further includes a source electrode 32, a drain electrode 34, and a gate structure 36 disposed on the electron supply layer 28. The FET 10 also includes a passivation layer 38 disposed on the electron supply layer 28 to cover the gate structure 36. The passivation layer 38 may be, for example, a silicon nitride (SiN) film, a silicon dioxide (SiO ２ ) film, silicon oxynitride (SiON) film, alumina (Al ２ O ３ The substrate is composed of a single film selected from the group consisting of an aluminum oxynitride (AlON) film, an AlN film, and an aluminum oxynitride (AlON) film, or a composite film containing any combination of two or more of these films.

[0027] The source electrode 32 and the drain electrode 34 are in ohmic contact with the 2DEG 30 generated in the electron transit layer 26 directly below the electron supply layer 28, i.e., are electrically connected to the 2DEG 30. The source electrode 32 and the drain electrode 34 may be formed of one or more metal layers using at least one of a titanium (Ti) layer, a titanium nitride (TiN) layer, an Al layer, an aluminum silicon copper (AlSiCu) layer, and an aluminum copper (AlCu) layer, for example. The source electrode 32 and the drain electrode 34 may be formed of the same metal material or different metal materials. Forming the source electrode 32 and the drain electrode 34 of the same metal material is advantageous in that both can be formed in the same process.

[0028] The cross-sectional shapes of the source electrode 32 and the drain electrode 34 are not particularly limited. For example, the source electrode 32 and the drain electrode 34 may be formed by forming one or more metal layers on the passivation layer 38 so as to fill the openings 38A, 38B of the passivation layer 38, and then etching the metal layers. In this case, as shown in the example of FIG. 2 , the source electrode 32 and the drain electrode 34 may each have a substantially T-shape or a substantially Y-shape in a cross section taken along the ZX plane in FIG. 2 .

[0029] In the example of FIG. 2 , the source electrode 32 may include a source electrode portion 32A and a source field plate portion 32B continuous with the source electrode portion 32A. The source electrode portion 32A includes a filling region that fills an opening 38A in the passivation layer 38 and an upper region that is formed integrally with this filling region. The source field plate portion 32B is formed integrally with the upper region of the source electrode portion 32A and is provided on the passivation layer 38 so as to cover the gate structure 36 in a plan view. The source field plate portion 32B serves to alleviate electric field concentration near the end of the gate structure 36 by extending a depletion layer toward the 2DEG 30 directly below the source field plate portion 32B when a high voltage is applied between the source and drain while the gate-source voltage is 0 V.

[0030] The gate structure 36 includes a gate layer 36A disposed on the electron supply layer 28 and a gate electrode 36B disposed on the gate layer 36A. The gate layer 36A may be formed of a nitride semiconductor having a band gap smaller than that of the electron supply layer 28. As an example, when the electron supply layer 28 is an AlGaN layer, the gate layer 36A may be a GaN layer doped with acceptor-type impurities, i.e., a p-type GaN layer. The acceptor-type impurities may be, for example, at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 36A may be, for example, 7×10 １８ cm －３ 1x10 or more ２０ cm －３ The following is the result.

[0031] When the gate layer 36A is formed of a nitride semiconductor containing acceptor-type impurities, the 2DEG 30 in the region directly below the gate layer 36A is depleted at zero bias when no voltage is applied to the gate electrode 36B, thereby blocking the conduction path (channel), thereby realizing a normally-off HEMT with a positive threshold voltage.

[0032] The thickness of the gate layer 36A is not particularly limited, but can be determined appropriately taking into consideration various parameters such as gate breakdown voltage. For example, the thickness of the gate layer 36A may be 80 nm or more and 150 nm or less. The cross-sectional shape of the gate layer 36A is also not particularly limited. The gate layer 36A may have, for example, a rectangular shape, a trapezoidal shape, a ridge shape, or any other shape in a cross section along the ZX plane in FIG. 2 .

[0033] The gate electrode 36B may be formed of one or more metal layers. The gate electrode 36B forms a Schottky junction or an ohmic junction with the gate layer 36A. For example, the gate electrode 36B may be a titanium nitride (TiN) layer. In this case, the gate electrode 36B forms a Schottky junction with the gate layer 36A. Alternatively, the gate electrode 36B may be formed of a first metal layer (e.g., a Ti layer) and a second metal layer (e.g., a TiN layer) provided on the first metal layer. The thickness of the gate electrode 36B may be, for example, 50 nm to 300 nm.

[0034] 2, the gate electrode 36B is disposed on a portion of the upper surface of the gate layer 36A and has a width in the X direction that is smaller than that of the gate layer 36A. This gate structure 36 is advantageous in reducing gate leakage current compared to a case in which the gate electrode 36B is formed with the same width in the X direction as the gate layer 36A. However, the gate electrode 36B may also be formed with the same width as the gate layer 36A.

[0035] The FET 10 further includes an interlayer insulating layer 42 that covers the passivation layer 38 as well as the source electrode 32 and the drain electrode 34, and a source wiring 44, a drain wiring 46, and a gate wiring 48 that are disposed on the interlayer insulating layer 42. Note that the passivation layer 38 and the interlayer insulating layer 42 are not shown in FIG. 1 to avoid cluttering the illustration. The interlayer insulating layer 42 is made of, for example, silicon dioxide (SiO ２ ) or other insulating materials. Although the interlayer insulating layer 42 in FIG. 2 is shown with a flat surface, it does not necessarily have to be flat. The interlayer insulating layer 42 may be formed with a uniform thickness within the FET 10 region so as to reflect the unevenness of the underlying interlayer insulating layer 42. The passivation layer 38 and the interlayer insulating layer 42 can be collectively referred to as insulating layers. The source wiring 44, the drain wiring 46, and the gate wiring 48 can be formed of a metal material such as gold (Au), Cu, or Al.

[0036] 2. Planar Layout of Source Electrode, Drain Electrode, and Gate Structure Next, an exemplary planar layout of the source electrode 32, drain electrode 34, and gate structure 36 of the FET 10 will be described with reference to FIG.

[0037] The drain electrode 34 includes multiple (four in the example of FIG. 1) drain contact portions 34C1, 34C2, 34C3, and 34C4 that contact the electron supply layer 28 (see FIG. 2). The drain contact portions 34C1 to 34C4 are spaced apart from one another in a first direction (Y direction) and a second direction (X direction) perpendicular to the first direction in a plan view. In the following description, when the drain contact portions 34C1 to 34C4 are not to be distinguished from one another, they will be collectively referred to as drain contact portion 34C.

[0038] The drain contact portion 34C is a portion of the drain electrode 34 that contacts the electron supply layer 28 in the active region 26R1. To avoid cluttering the illustration, portions of the drain electrode 34 other than the drain contact portion 34C are not shown in FIG. 1 . For ease of understanding, the drain contact portion 34C is indicated by hatched lines in FIG. 1 . Each drain contact portion 34C has a finger shape, i.e., an elongated shape, extending in the first direction.

[0039] The gate structure 36 includes a plurality of gate portions 36G1, 36G2, 36G3, and 36G4 (four in the example of FIG. 1). The gate portions 36G1, 36G2, 36G3, and 36G4 are each provided to annularly surround a corresponding one of the drain contact portions 34C1, 34C2, 34C3, and 34C4. In the following description, when the gate portions 36G1 to 36G4 are not to be distinguished from one another, they will be collectively referred to as gate portion 36G.

[0040] Each gate portion 36G includes a gate layer 36A and a gate electrode 36B, which have been described with reference to Fig. 2. To avoid complication of the illustration, the gate layer 36A is not shown in Fig. 1. For ease of understanding, the gate electrode 36B is indicated by hatched lines in Fig. 1. In each gate portion 36G, the gate layer 36A and the gate electrode 36B are formed in an annular shape.

[0041] It should be noted that the term "annular" as used in this disclosure refers not only to any structure that forms a continuous shape or loop without an end, but also to generally loop-shaped structures with gaps, such as, for example, a C-shape. Thus, an explicit reference to a "closed annular" refers to any structure that forms a continuous shape or loop without an end, while an explicit reference to an "open annular" refers to a generally loop-shaped structure with gaps. Such "annular" shapes can include not only ovals, but also any shapes that include multiple corners, such as square or rounded corners.

[0042] 1, each gate portion 36G is formed in a closed ring shape. However, each gate portion 36G is not necessarily limited to a closed ring shape and may be an open ring shape. For example, each annular gate portion 36G includes a pair of gate structure finger portions 36F1, 36F2 that are arranged in the formation region of the FET element 14 and extend parallel to the first direction (Y direction). For example, each gate portion 36G may be formed in an open ring shape with a gap at a position away from the pair of gate structure finger portions 36F1, 36F2.

[0043] Gate portions 36G adjacent to each other in the first direction (Y direction) are electrically connected to each other by a coupling portion 37. In the example of FIG. 1 , gate portions 36G1 and 36G3 are electrically connected to each other by the coupling portion 37, and gate portions 36G2 and 36G4 are electrically connected to each other by the coupling portion 37. The coupling portion 37 may have a width greater than the width of the gate electrode 36B in both the first direction (Y direction) and the second direction (X direction). Gate portions 36G adjacent to each other in the second direction (X direction) are spaced apart from each other.

[0044] The source electrode 32 includes a plurality of source contact portions 32C1 and 32C2 (two in the example of FIG. 1) that are arranged one by one between the gate portions 36G adjacent to each other in the second direction (X direction) and that contact the electron supply layer 28 (see FIG. 2). In the following description, when the source contact portions 32C1 and 32C2 are not to be distinguished from each other, they are collectively referred to as source contact portion 32C.

[0045] The source electrode 32 further includes a source contact periphery 32CP that contacts the electron supply layer 28 along the periphery of the electron supply layer 28 corresponding to the boundary between the active region 26R1 and the inactive region 26R2. The source contact periphery 32CP is disposed so as to surround the drain electrode 34 (all of the drain contact portions 34C) and the gate structure 36 (all of the gate portions 36G) in plan view.

[0046] The source contact portion 32C and the source contact peripheral portion 32CP are portions of the source electrode 32 that contact the electron supply layer 28 in the active region 26R1. To avoid complication of the illustration, portions of the source electrode 32 other than the source contact portion 32C and the source contact peripheral portion 32CP are not shown in Fig. 1. For ease of understanding, the source contact portion 32C and the source contact peripheral portion 32CP are indicated by hatched lines in Fig. 1.

[0047] In the example of FIG. 1 , the source contact portions 32C1 and 32C2 are spaced apart from each other in the first direction (Y direction). Furthermore, the source contact portions 32C1 and 32C2 are also spaced apart from the source contact periphery 32CP. Each source contact portion 32C has a finger shape, i.e., an elongated shape, extending in the first direction. For example, each source contact portion 32C may have the same length in the first direction as each drain contact portion 34C. The source contact portion 32C1 is disposed between the gate portion 36G1 and the gate portion 36G2, which are adjacent to each other in the second direction (X direction), and the source contact portion 32C2 is disposed between the gate portion 36G3 and the gate portion 36G4, which are adjacent to each other in the second direction.

[0048] The source contact outer periphery 32CP is formed in an annular shape along the outer periphery of the electron supply layer 28. In the example of FIG. 1 , the source contact outer periphery 32CP is formed in a closed annular shape. However, the source contact outer periphery 32CP is not necessarily limited to a closed annular shape. For example, the annular source contact outer periphery 32CP is disposed in the formation region of the FET element 14 and includes a pair of source outer periphery fingers 32F1, 32F2 extending parallel to the first direction (Y direction). For example, the source contact outer periphery 32CP may be formed in an open annular shape having a gap at a position away from the pair of source outer periphery fingers 32F1, 32F2.

[0049] In the example of FIG. 1, FET cell 12A (FET elements 14A1, 14A2) includes drain contact portion 34C1, a pair of gate structure finger portions 36F1, 36F2 of gate portion 36G1, source contact portion 32C1, and source outer periphery finger portion 32F1 of source contact outer periphery portion 32CP.

[0050] FET cell 12B (FET elements 14B1, 14B2) includes drain contact portion 34C2, a pair of gate structure finger portions 36F1, 36F2 of gate portion 36G2, source contact portion 32C1, and source outer periphery finger portion 32F2 of source contact outer periphery portion 32CP.

[0051] FET cell 12C (FET elements 14C1, 14C2) includes drain contact portion 34C3, a pair of gate structure finger portions 36F1, 36F2 of gate portion 36G3, source contact portion 32C2, and source outer periphery finger portion 32F1 of source contact outer periphery portion 32CP.

[0052] FET cell 12D (FET elements 14D1 and 14D2) includes drain contact portion 34C4, a pair of gate structure finger portions 36F1 and 36F2 of gate portion 36G4, source contact portion 32C2, and source outer periphery finger portion 32F2 of source contact outer periphery portion 32CP.

[0053] 3. Dummy Gate Structure Next, the dummy gate structure of the FET 10 will be described with continued reference to FIGS.

[0054] As shown in FIGS. 1 and 2, the FET 10 may include a dummy gate structure 50 disposed on the electron supply layer 28 in the active region 26R1 at a position outside the source contact periphery 32CP in a plan view.

[0055] The dummy gate structure 50 is formed in an annular shape along the outer periphery of the electron supply layer 28. Therefore, the dummy gate structure 50 annularly surrounds the source contact outer periphery 32CP on the electron supply layer 28. In the example of FIG. 1 , the dummy gate structure 50 is formed in a closed annular shape. However, the dummy gate structure 50 is not necessarily limited to a closed annular shape. For example, the annular dummy gate structure 50 includes a pair of dummy gate structure finger portions 50F1 and 50F2 extending parallel to the first direction (Y direction). For example, the dummy gate structure 50 may be formed in an open annular shape having a gap at a position away from the pair of dummy gate structure finger portions 50F1 and 50F2.

[0056] The dummy gate structure 50 may have a configuration similar to that of the gate structure 36. In the example of Fig. 2, the dummy gate structure 50 includes a dummy gate layer 50A disposed on the electron supply layer 28 and a dummy gate electrode 50B disposed on the dummy gate layer 50A.

[0057] For example, the dummy gate layer 50A is configured similarly to the gate layer 36A of the gate structure 36. Furthermore, the dummy gate electrode 50B is configured similarly to the gate electrode 36B of the gate structure 36. Therefore, the above-mentioned explanations regarding the gate layer 36A and the gate electrode 36B can be similarly applied to the dummy gate layer 50A and the dummy gate electrode 50B, respectively. Note that, to avoid complexity in the illustration, the dummy gate layer 50A is not shown in FIG. 1. Furthermore, to facilitate understanding, the dummy gate electrode 50B is indicated by hatched lines in FIG. 1.

[0058] The dummy gate structure 50 can be formed with the same dimensions in the second direction (X direction) as the gate structure 36. In the example of Fig. 2, the dummy gate layer 50A has the same length in the second direction as the gate layer 36A, and the dummy gate electrode 50B also has the same length in the second direction as the gate electrode 36B.

[0059] The dummy gate structure 50 (the dummy gate layer 50A and the dummy gate electrode 50B) includes a pair of dummy gate structure finger portions 50F1 and 50F2 extending in the first direction, similar to the pair of gate structure finger portions 36F1 and 36F2 of each gate portion 36G (the gate layer 36A and the gate electrode 36B). For example, the gate structure finger portions 36F1 and 36F2 and the dummy gate structure finger portions 50F1 and 50F2 are formed to have the same dimensions in the second direction in a plan view.

[0060] The dummy gate structures 50 serve to maintain the periodicity of the cross-sectional shape of the gate structures 36 in the second direction (X direction) when the gate structures 36 are formed, for example, through photolithography and etching processes. Note that in the example of FIG. 1 , the dummy gate structures 50 are not electrically controlled. Therefore, the dummy gate structures 50 do not control the current flowing between the drain electrode 34 and the source electrode 32 of the FET 10 (FET element 14).

[0061] The distance between the dummy gate structure 50 and the source contact outer periphery 32CP can be determined appropriately, for example, from the viewpoint of suppressing photolithography and etching abnormalities when forming the gate structure 36 and maintaining the periodicity of the gate structure 36. In the example of FIG. 1 , the dummy gate structure finger portion 50F1 and the source outer periphery finger portion 32F1 are adjacent to each other at a first distance in the second direction (X direction) in plan view, and the gate structure finger portion 36F1 and the source outer periphery finger portion 32F1 are adjacent to each other at a second distance in the second direction in plan view. In this case, the first distance may be equal to or greater than the second distance, for example, 1 to 5 times the second distance.

[0062] Similarly, the dummy gate structure finger portion 50F2 and the source outer periphery finger portion 32F2 are adjacent to each other at a first interval in the second direction in plan view, and the gate structure finger portion 36F2 and the source outer periphery finger portion 32F2 are adjacent to each other at a second interval in the second direction in plan view. In this case, the first interval may be equal to or greater than the second interval, for example, 1 to 5 times the second interval. By making the first interval equal to or greater than the second interval, it becomes easier to make the cross-sectional shape of the gate structure 36 uniform at the positions of all gate portions 36G (each of the gate structure finger portions 36F1, 36F2) including the gate structure finger portions 36F1, 36F2 adjacent to the source contact outer periphery portion 32CP.

[0063] 4. Planar Layout of Source Wiring, Drain Wiring, and Gate Wiring Next, still referring to FIG. 1, an exemplary planar layout of the source wiring 44, the drain wiring 46, and the gate wiring 48 arranged on the interlayer insulating layer 42 (see FIG. 2) will be described.

[0064] 1, the source wiring 44, the drain wiring 46, and the gate wiring 48 are disposed on the interlayer insulating layer 42 (see FIG. 2) in the region surrounded by the inactive region 26R2, i.e., the region corresponding to the active region 26R1. In this way, the configuration in which the source wiring 44, the drain wiring 46, and the gate wiring 48 are concentrated in the region above the active region 26R1 is advantageous in terms of reducing the chip area.

[0065] The number and shapes of the source wiring 44, drain wiring 46, and gate wiring 48 are not particularly limited and can be determined appropriately depending on, for example, the number and size of the FET cells 12. For the purpose of explanation, Fig. 1 shows a wiring structure including one source wiring 44, four drain wirings 46, and one gate wiring 48, but other numbers of wirings are also applicable.

[0066] The source wiring 44 is formed as a single continuous wiring as a whole, extending in both the first direction (Y direction) and the second direction (X direction). In the example of FIG. 1 , the source wiring 44 includes a first portion 44A extending in the first direction along the source periphery finger portion 32F1 (left side of FIG. 1 ), two second portions 44B extending in the first direction along the source periphery finger portion 32F2 (right side of FIG. 1 ), and six third portions 44C extending in the second direction. Each of the third portions 44C intersects with the source contact portion 32C between adjacent FET cells 12 in the second direction (between FET cells 12A and 12B or between FET cells 12C and 12D in the example of FIG. 1 ) and connects the first portion 44A to one of the second portions 44B.

[0067] The drain wirings 46 each extend in the second direction. In plan view, each drain wiring 46 is surrounded by the source wiring 44. In the example of FIG. 1 , each drain wiring 46 is surrounded by first to third portions 44A, 44B, and 44C of the source wiring 44, and intersects with the drain contact portion 34C of the FET cell 12 adjacent to it in the second direction.

[0068] The gate wiring 48 extends in the second direction. The gate wiring 48 extends in the second direction between two gate portions 36G adjacent to each other in the first direction (in the example of FIG. 1 , between gate portions 36G1 and 36G3 and between gate portions 36G2 and 36G4), and intersects with the coupling portion 37. The gate wiring 48 is adjacent to the source wiring 44 in a plan view. In the example of FIG. 1 , the gate wiring 48 is located between two third portions 44C of the source wirings 44 adjacent to each other in the first direction, and is adjacent to these two third portions 44C. Therefore, the gate wiring 48 is not adjacent to the drain wiring 46.

[0069] The source wiring 44 is electrically connected to the source electrode 32 by a connection conductor 49 that penetrates an insulating layer (interlayer insulating layer 42 in the example of FIG. 2) between the source wiring 44 and the source electrode 32. For example, the source wiring 44 and each source contact portion 32C are connected by the connection conductors 49 at a plurality of source connection points (three in the example of FIG. 1), and two or more connection conductors 49 are provided at each source connection point. Note that the connection conductors 49 that connect the source wiring 44 and each source contact portion 32C correspond to source connection conductors.

[0070] Similarly, the source wiring 44 and the source contact peripheral portion 32CP are connected at a plurality of (12 in the example of FIG. 1 ) source peripheral connection points by connecting conductors 49, and each source peripheral connection point is provided with two or more connecting conductors 49. The connecting conductors 49 connecting the source wiring 44 and the source contact peripheral portion 32CP correspond to the source peripheral connecting conductors.

[0071] Although a detailed cross section is not shown, the drain wiring 46 is also electrically connected to the drain electrode 34 by a connecting conductor 49. For example, the drain wiring 46 and each drain contact portion 34C are connected by the connecting conductors 49 at a plurality of drain connection points (two in the example of FIG. 1 ), and each drain connection point is provided with two or more connecting conductors 49. The connecting conductors 49 connecting the drain wiring 46 and each drain contact portion 34C correspond to the drain connecting conductors.

[0072] Similarly, although a detailed cross section is not shown, the gate wiring 48 is also electrically connected to the gate electrode 36B (gate structure 36) by a connecting conductor 49. For example, the gate wiring 48 and the coupling portion 37 are connected by the connecting conductor 49 at a gate connection point on the coupling portion 37, and two or more connecting conductors 49 are provided at the gate connection point. The gate wiring 48 is electrically connected to the gate electrode 36B via the connecting conductor 49 and the coupling portion 37. The connecting conductor 49 connecting the gate wiring 48 and the coupling portion 37 corresponds to the gate connecting conductor.

[0073] There is no particular limitation on the material of the connection conductor 49. For example, the connection conductor 49 may be formed of the same metal material as the source wiring 44, the drain wiring 46, and the gate wiring 48, or may be formed as a plug using a metal material different from those (for example, tungsten (W)).

[0074] 5. Planar Layout of Upper-Layer Wiring Next, an exemplary planar layout of upper-layer wiring arranged further above the source wiring 44, the drain wiring 46, and the gate wiring 48 will be described with reference to FIG.

[0075] 3, in the region corresponding to the active region 26R1, a source pad 62, a drain pad 64, and a gate pad 66 are disposed above the source wiring 44, the drain wiring 46, and the gate wiring 48. The source pad 62, the drain pad 64, and the gate pad 66 are formed on a layer of, for example, SiO ２ The active region 26R1 is disposed on an interlayer insulating layer (not shown) such as the active region 26R1. The configuration in which the source pad 62, the drain pad 64, and the gate pad 66 are concentrated in the region above the active region 26R1 is advantageous in terms of reducing the chip area.

[0076] The source pad 62, the drain pad 64, and the gate pad 66 may be formed of a metal material such as Au, Cu, or Al, and are used as connection members for connecting external connection terminals such as wires or solder balls.

[0077] The source wiring 44, the drain wiring 46, and the gate wiring 48 correspond to the first source wiring, the first drain wiring, and the first gate wiring, respectively. The source pad 62, the drain pad 64, and the gate pad 66 correspond to the second source wiring, the second drain wiring, and the second gate wiring, respectively. The insulating layer including the passivation layer 38 and the interlayer insulating layer 42 corresponds to the first insulating layer, and the interlayer insulating layer (not shown) covering the source wiring 44, the drain wiring 46, and the gate wiring 48 corresponds to the second insulating layer.

[0078] The source pad 62 and the drain pad 64 are each formed in a generally rectangular shape in a plan view and extend in the first direction (Y direction). The gate pad 66 is formed in a generally square shape in a plan view. The source pad 62 is electrically connected to the source wiring 44 by a connection conductor 68 that penetrates the second insulating layer at a location where the source pad 62 intersects with the source wiring 44 (third portion 44C). The drain pad 64 is electrically connected to the drain wiring 46 by a connection conductor 68 that penetrates the second insulating layer at a location where the source pad 62 intersects with the drain wiring 46. The gate pad 66 is provided, for example, near one end of the gate wiring 48 in a plan view, and is electrically connected to the gate wiring 48 by the connection conductor 68 that penetrates the second insulating layer at a location where the gate pad 66 intersects with the gate wiring 48.

[0079] Therefore, the source pad 62 is electrically connected to the source electrode 32 (source contact portions 32C1, 32C2 and source contact peripheral portion 32CP) via the connecting conductor 68, the source wiring 44, and the connecting conductor 49. The drain pad 64 is electrically connected to the drain electrode 34 (drain contact portions 34C1 to 34C4) via the connecting conductor 68, the drain wiring 46, and the connecting conductor 49. The gate pad 66 is electrically connected to the gate electrode 36B (gate portions 36G1 to 36G4) via the connecting conductor 68, the gate wiring 48, and the connecting conductor 49.

[0080] [FET Operation] Next, the operation of the FET 10 will be described. The FET 10 includes an electron transit layer 26 and an electron supply layer 28 disposed on the electron transit layer 26 to generate 2DEG 30 in the electron transit layer 26 near the interface with the electron transit layer 26. The electron transit layer 26 includes an active region 26R1 in which the 2DEG 30 can be generated and an inactive region 26R2 surrounding the active region 26R1 in a planar view. The source electrode 32, the drain electrode 34, and the gate structure 36 are disposed on the electron supply layer 28 in a region corresponding to the active region 26R1. The source electrode 32 includes a source contact periphery 32CP that surrounds the drain electrode 34 and the gate structure 36 in a planar view and is in contact with the electron supply layer 28 along the periphery of the electron supply layer 28 corresponding to the boundary between the active region 26R1 and the inactive region 26R2.

[0081] In this configuration, the source contact outer periphery 32CP is electrically connected to the 2DEG 30 at the outer periphery of the active region 26R1 (i.e., the 2DEG 30 located directly below the source contact outer periphery 32CP). This stabilizes the potential of the 2DEG 30 at the outer periphery of the active region 26R1 at the source potential. As a result, even if an external surge enters the chip (in the active region 26R1), the surge instantly spreads to the source electrode 32 via the source contact outer periphery 32CP located above the outer periphery of the active region 26R1. This suppresses the electrical impact on the gate structure 36 due to the surge entering the chip, thereby suppressing degradation of the characteristics of the FET 10. This improves the surge resistance of the FET 10.

[0082] The FET 10 of the first embodiment has the following advantages: (1-1) The source contact peripheral portion 32CP surrounds the drain electrode 34 and the gate structure 36 in a plan view and contacts the electron supply layer 28 along the periphery of the electron supply layer 28 corresponding to the boundary between the active region 26R1 and the inactive region 26R2. With this configuration, the source contact peripheral portion 32CP is electrically connected to the 2DEG 30 directly below it, thereby stabilizing the potential of the 2DEG 30 at the periphery of the active region 26R1 to the source potential. This improves surge resistance.

[0083] (1-2) The source contact peripheral portion 32CP is formed in a ring shape along the outer periphery of the electron supply layer 28. With this configuration, the ring-shaped source contact peripheral portion 32CP stabilizes the potential of the 2DEG 30 throughout the entire outer periphery of the active region 26R1 to the source potential, thereby further improving surge resistance.

[0084] (1-3) The drain electrode 34 includes drain contact portions 34C1-34C4 spaced apart from one another in the first direction (Y direction) and the second direction (X direction) in plan view, each having a finger shape extending in the first direction. The gate structure 36 includes gate portions 36G1-36G4 each annularly surrounding one of the drain contact portions 34C1-34C4. With this configuration, the region of the 2DEG 30 having the same potential as the drain contact portion 34C is limited to the range of the active region 26R1 surrounded by each gate portion 36G in plan view. Therefore, in a configuration in which the gate wiring 48 extends in the second direction between two gate portions 36G adjacent in the first direction, the gate wiring 48 does not pass above the region of the 2DEG 30 having the same potential as the drain contact portion 34C. This reduces the gate-drain capacitance, enabling high-speed switching operation of the FET 10.

[0085] (1-4) The source electrode 32 includes source contact portions 32C1 and 32C2 that are disposed between two gate portions 36G adjacent to each other in the second direction (X direction) and that contact the electron supply layer 28. With this configuration, the same source contact portion 32C is shared between two FET cells 12 adjacent to each other in the second direction (between FET cells 12A and 12B and between FET cells 12C and 12D in the example of FIG. 1), thereby reducing the chip area.

[0086] (1-5) The inactive region 26R2 is formed by removing the upper peripheral portion of the electron transit layer 26 together with the peripheral portion of the electron supply layer 28 located immediately above it. This removal can be performed using, for example, an etching method. Although the inactive region 26R2 can also be formed by increasing the resistance of the peripheral portion of the electron supply layer 28 and the upper peripheral portion of the electron transit layer 26 located immediately below it using an ion implantation method, using an etching method is advantageous from the standpoint of cost.

[0087] (1-6) The FET 10 includes a dummy gate structure 50 disposed on the electron supply layer 28 along the periphery of the electron supply layer 28 at a position outside the source contact periphery 32CP in a plan view. The dummy gate structure 50 may be formed with the same configuration and dimensions as the gate structure 36. For example, the pair of gate structure finger portions 36F1, 36F2 of the gate structure 36 may be formed with the same dimensions in the second direction (X direction) as the pair of dummy gate structure finger portions 50F1, 50F2 of the dummy gate structure 50. The dummy gate structure 50 maintains the periodicity of the cross-sectional shape of the gate structure 36 in the second direction, facilitating uniformity of the cross-sectional shape of the gate structure 36 regardless of the position of the FET cell 12. This allows uniform operation of the FET elements 14 (HEMTs in the example of FIG. 1 ) across the entire chip, improving the reliability of the FET 10.

[0088] (1-7) The first distance in the second direction between the dummy gate structure finger portion 50F1 (50F2) and the source outer periphery finger portion 32F1 (32F2) may be equal to or greater than the second distance in the second direction between the gate structure finger portion 36F1 (36F2) and the source outer periphery finger portion 32F1 (32F2). This configuration makes it easy to make the cross-sectional shape of the gate structure 36 uniform at the positions of all gate portions 36G (each of the gate structure finger portions 36F1, 36F2), including the gate portion 36G adjacent to the source contact outer periphery 32CP.

[0089] (1-8) The source wiring 44, the drain wiring 46, and the gate wiring 48 are disposed on an insulating layer (interlayer insulating layer 42 in the example of FIG. 2) in a region corresponding to the active region 26R1. By consolidating the source wiring 44, the drain wiring 46, and the gate wiring 48 in a region above the active region 26R1, it is possible to reduce the chip area.

[0090] (1-9) The drain wiring 46 is surrounded by the source wiring 44 in a plan view. With this configuration, the source wiring 44, which is at ground potential, surrounds the drain wiring 46 to which a high voltage is applied, thereby suppressing the movement of mobile ions or moisture in the insulating layer (the interlayer insulating layer 42 and the passivation layer 38 in the example of FIG. 2) due to an electric field. This improves surge resistance and moisture resistance, thereby improving the reliability of the FET 10.

[0091] (1-10) In plan view, the gate wiring 48 is adjacent to the source wiring 44 but not adjacent to the drain wiring 46. This configuration reduces the capacitance between the gate and the drain, enabling high-speed switching operation of the FET 10.

[0092] (1-11) Two or more connection conductors 49 are provided at each source connection point connecting the source wiring 44 and each source contact portion 32C. Similarly, two or more connection conductors 49 are provided at each source peripheral connection point connecting the source wiring 44 and each source contact peripheral portion 32CP. Similarly, two or more connection conductors 49 are provided at each drain connection point connecting the drain wiring 46 and each drain contact portion 34C. Similarly, two or more connection conductors 49 are provided at each gate connection point connecting the gate wiring 48 and the coupling portion 37. With this configuration, two or more connection conductors 49 are provided at each connection point, thereby reducing the contact resistance between the source wiring 44 and the source electrode 32, the contact resistance between the drain wiring 46 and the drain electrode 34, and the contact resistance between the gate wiring 48 and the coupling portion 37. This stabilizes the characteristics of the FET 10.

[0093] (1-12) The source pad 62, the drain pad 64, and the gate pad 66 are arranged in a region corresponding to the active region 26R1 above the source wiring 44, the drain wiring 46, and the gate wiring 48. Concentrating the source pad 62, the drain pad 64, and the gate pad 66 in a region above the active region 26R1 is advantageous in reducing the chip area.

[0094] Second Embodiment Next, a second embodiment will be described with reference to Fig. 4. Fig. 4 is a schematic plan view of an exemplary FET 10 according to the second embodiment. Note that in Fig. 4, components similar to those of the FET 10 of the first embodiment are denoted by the same reference numerals. Below, a description of components similar to those of the first embodiment will be omitted, and only components different from those of the first embodiment will be described.

[0095] 4, the FET 10 of the second embodiment differs from the FET 10 of the first embodiment in that the FET cells 12A, 12B, 12C, and 12D described with reference to FIG. 1 further include source contact portions 32C11, 32C12, 32C13, and 32C14, respectively. The other configurations are the same as those of the first embodiment. The source contact portions 32C11, 32C12, 32C13, and 32C14 each have a finger shape extending in the first direction (Y direction).

[0096] The source contact portion 32C11 is disposed between the drain contact portion 34C1 and the outer source finger portion 32F1 of the outer source contact portion 32CP, and the source contact portion 32C12 is disposed between the drain contact portion 34C2 and the outer source finger portion 32F2 of the outer source contact portion 32CP.

[0097] Similarly, source contact portion 32C13 is disposed between drain contact portion 34C3 and outer source finger portion 32F1 of outer source contact portion 32CP, and source contact portion 32C14 is disposed between drain contact portion 34C4 and outer source finger portion 32F2 of outer source contact portion 32CP.

[0098] Source contact outer periphery 32CP is arranged to surround, in plan view, FET cells 12A-12D, each including source contact portions 32C11-32C14. In this configuration, the symmetry of each of FET cells 12A-12D is improved compared to the configuration of the first embodiment (see FIG. 1) in which each of FET cells 12A-12D includes a portion of source contact outer periphery 32CP.

[0099] During operation of the FET 10, for example, in the FET cell 12A, the current flowing through the drain contact portion 34C1 generally flows into the source contact portions 32C1 and 32C11 adjacent to the drain contact portion 34C1 in a plan view. This is also true for the other FET cells 12B, 12C, and 12D. Therefore, unlike the first embodiment (see FIG. 1 ), almost no current from each drain contact portion 34C flows into the outer source contact portion 32CP. As a result, the current density of the two FET elements 14 in each FET cell 12 is made uniform, enabling uniform operation of all FET cells 12 (all FET elements 14), thereby improving the reliability of the FET 10.

[0100] In addition to the advantages (1-1) to (1-12) of the first embodiment, the FET 10 of the second embodiment has the following advantage: (2-1) The FET cells 12A, 12B, 12C, and 12D each further include source contact portions 32C11, 32C12, 32C13, and 32C14, respectively, which improves the symmetry of each of the FET cells 12A to 12D. As a result, the current density of the two FET elements 14 in each FET cell 12 is made uniform, enabling uniform operation of all of the FET cells 12 (all of the FET elements 14), thereby improving the reliability of the FET 10.

[0101] Third Embodiment Next, a third embodiment will be described with reference to Fig. 5. Fig. 5 is a schematic plan view of an exemplary FET 10 according to the third embodiment. Note that in Fig. 5, components similar to those of the FET 10 of the first embodiment are denoted by the same reference numerals. Below, a description of components similar to those of the first embodiment will be omitted, and only components different from those of the first embodiment will be described.

[0102] 5, FET 10 of the third embodiment differs from FET 10 of the first embodiment in that source contact portions 32C1 and 32C2 described with reference to FIG. 1 are replaced with source contact portion 32CX. The other configurations are the same as those of the first embodiment.

[0103] The source contact portion 32CX has a finger shape extending in the first direction (Y direction) and is located between two gate portions 36G adjacent to each other in the second direction (X direction). In the example of Fig. 5, the source contact portion 32CX is shared between the two gate portions 36G1 and 36G2 and between the two gate portions 36G3 and 36G4.

[0104] The source contact portion 32CX is directly connected to the source contact outer periphery 32CP. Therefore, while the source contact portions 32C1 and 32C2 in the first embodiment (see FIG. 1 ) have ends, the source contact portion 32CX does not have ends. That is, the source contact portion 32CX is continuous with the source contact outer periphery 32CP. In the example of FIG. 5 , the source contact outer periphery 32CP and the source contact portion 32CX form a first annular portion that annularly surrounds the gate portions 36G1 and 36G3 adjacent to each other in the first direction in a plan view, and a second annular portion that annularly surrounds the gate portions 36G2 and 36G4 adjacent to each other in the first direction in a plan view.

[0105] In the third embodiment, the source contact portion 32CX does not have an end portion, which prevents localized electric field concentration at the source contact portion 32CX. For example, in the first embodiment, electric field concentration may occur at the end portions of each of the source contact portions 32C1 and 32C2. Since such electric field concentration is prevented, the reliability of the FET 10 is improved.

[0106] In addition to the advantages (1-1) to (1-12) of the first embodiment, the FET 10 of the third embodiment has the following advantage: (3-1) The source contact portion 32CX is continuous with the source contact outer periphery 32CP and has no end portion. This prevents localized electric field concentration in the source contact portion 32CX, thereby improving the reliability of the FET 10.

[0107] Fourth Embodiment Next, a fourth embodiment will be described with reference to Fig. 6. Fig. 6 is a schematic plan view of an exemplary FET 10 according to the fourth embodiment. Note that in Fig. 6, components similar to those of the FET 10 of the third embodiment are denoted by the same reference numerals. Below, a description of the components similar to those of the third embodiment will be omitted, and only components different from those of the third embodiment will be described.

[0108] 6, the FET 10 of the fourth embodiment differs from the FET 10 of the third embodiment in that a dummy gate structure 50 is electrically connected to the gate structure 36. The other configurations are the same as those of the third embodiment. The connection structure between the dummy gate structure 50 and the gate structure 36 will now be described.

[0109] In the fourth embodiment, the dummy gate structure 50 includes a dummy gate coupling portion 52 A. The gate wiring 48 is configured in the same manner as the gate wiring 48 of the third embodiment, except that it extends in the second direction (X direction) to a position where it intersects with the dummy gate coupling portion 52 A in a plan view.

[0110] The gate wiring 48 is electrically connected to the dummy gate coupling portion 52A by a connecting conductor 49 that penetrates an insulating layer (not shown, for example, the interlayer insulating layer 42 and the passivation layer 38 in FIG. 2 ). For example, the gate wiring 48 and the dummy gate coupling portion 52A are connected by the connecting conductor 49 at a dummy gate connection point on the dummy gate coupling portion 52A. Two or more connecting conductors 49 are provided at the dummy gate connection point.

[0111] Therefore, dummy gate structure 50 is electrically connected to gate structure 36. In this configuration, the capacitance generated by dummy gate structure 50 is added to the capacitance generated by gate structure 36, increasing the gate capacitance of the entire FET 10. This improves the surge resistance of gate structure 36 and suppresses the occurrence of false firing during switching operations.

[0112] In addition to the advantages (1-1) to (1-12) of the first embodiment and the advantage (3-1) of the third embodiment, the FET 10 of the fourth embodiment has the following advantage: (4-1) Because the dummy gate structure 50 is electrically connected to the gate structure 36, the gate capacitance of the entire FET 10 is increased. This improves the surge resistance of the gate structure 36 and suppresses the occurrence of false firing during switching operations. This further improves the surge resistance.

[0113] Fifth Embodiment Next, a fifth embodiment will be described with reference to Fig. 7. Fig. 7 is a schematic plan view of an exemplary FET 10 according to the fifth embodiment. Note that in Fig. 7, components similar to those of the FET 10 of the third embodiment are denoted by the same reference numerals. Below, a description of components similar to those of the third embodiment will be omitted, and only components different from those of the third embodiment will be described.

[0114] 7 , the FET 10 of the fifth embodiment differs from the FET 10 of the third embodiment in that the dummy gate structure 50 is electrically connected to the source electrode 32. The other configurations are the same as those of the third embodiment. The connection structure between the dummy gate structure 50 and the source electrode 32 will now be described.

[0115] In the fifth embodiment, the dummy gate structure 50 includes one or more (two in the example of FIG. 7 ) dummy gate coupling portions 52B. The source wiring 44 includes one or more (two in the example of FIG. 7 ) extending portions 45A depending on the number of dummy gate coupling portions 52B. The extending portions 45A extend in the second direction (X direction) from the first portion 44A of the source wiring 44 to a position where they intersect with the dummy gate coupling portions 52B in a plan view.

[0116] The extending portion 45A of the source wiring 44 is electrically connected to the dummy gate coupling portion 52B by a connecting conductor 49 that penetrates an insulating layer (not shown, for example, the interlayer insulating layer 42 and the passivation layer 38 in FIG. 2). For example, the extending portion 45A of the source wiring 44 and the dummy gate coupling portion 52B are connected by the connecting conductor 49 at a dummy gate connection point on each dummy gate coupling portion 52B. Two or more connecting conductors 49 are provided at each dummy gate connection point.

[0117] Therefore, the dummy gate structure 50 is electrically connected to the source electrode 32. For example, if the FET 10 is configured as a normally-off type HEMT, the dummy gate structure 50 is electrically connected to the source electrode 32, thereby depleting the 2DEG 30 directly below the dummy gate structure 50 (e.g., the dummy gate layer 50A in FIG. 2 ). As a result, even if an external surge, such as a surge generated during a dicing process, enters the chip, the surge is prevented from entering the active region 26R1 surrounded by the dummy gate structure 50 (i.e., the formation region of the FET cells 12A-12D).

[0118] In addition to the advantages (1-1) to (1-12) of the first embodiment and the advantage (3-1) of the third embodiment, the FET 10 of the fifth embodiment has the following advantage: (5-1) Because the dummy gate structure 50 is electrically connected to the source electrode 32, the 2DEG 30 directly below the dummy gate structure 50 is depleted. This prevents external surges from penetrating into the active region 26R1 surrounded by the dummy gate structure 50. This improves surge resistance. In particular, when the dummy gate structure 50 is formed in a ring shape, the 2DEG 30 directly below the dummy gate structure 50 is depleted throughout the entire outer periphery of the active region 26R1. This further improves surge resistance.

[0119] Sixth Embodiment Next, a sixth embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a schematic plan view of an exemplary FET 10 according to the sixth embodiment, and FIG. 9 is a schematic cross-sectional view taken along line F9-F9 in FIG. 8. Note that in FIGS. 8 and 9, components similar to those of the FET 10 of the first embodiment are denoted by the same reference numerals. Below, a description of components similar to those of the first embodiment will be omitted, and only components different from those of the first embodiment will be described.

[0120] 8 and 9, the FET 10 of the sixth embodiment differs from the FET 10 of the first embodiment in that it includes a peripheral metal layer 70 at the boundary between the active region 26R1 and the inactive region 26R2. The other configurations are the same as those of the first embodiment.

[0121] 8 , the peripheral metal layer 70 covers both the side surface 26S1 of the electron transit layer 26 and the side surface 28S1 of the electron supply layer 28, which are located at the boundary between the active region 26R1 and the inactive region 26R2. For example, the peripheral metal layer 70 is formed in a ring shape around the entire periphery of the active region 26R1. Therefore, the peripheral metal layer 70 covers the 2DEG 30 exposed at the side surface 26S1 of the electron transit layer 26. In this way, the 2DEG 30 exposed at the side surface 26S1 of the electron transit layer 26 is covered with the peripheral metal layer 70, thereby stabilizing the potential of the 2DEG 30.

[0122] For example, if the 2DEG 30 exposed from the side surface 26S1 of the electron transit layer 26 is covered with an insulating layer such as SiN, the potential of the 2DEG 30 exposed on the side surface 26S1 may become unstable depending on the state of the insulating layer at the covering interface. Compared to this configuration, covering the 2DEG 30 exposed on the side surface 26S1 with the peripheral metal layer 70 stabilizes the potential of the 2DEG 30, thereby stabilizing the operation of the FET 10.

[0123] The material of the peripheral metal layer 70 is not particularly limited, and may be the same metal material as the source electrode 32 and the drain electrode 34, for example. In this case, the peripheral metal layer 70 makes ohmic contact with the 2DEG 30, so that the potential of the DEG 30 exposed on the side surface 26S1 of the electron transit layer 26 becomes constant over the entire periphery of the side surface 26S1. As a result, the operation of the FET 10 becomes more stable. Furthermore, since the peripheral metal layer 70 is formed during the process of forming the source electrode 32 and the drain electrode 34, this has the advantage of forming the peripheral metal layer 70 without adding any additional manufacturing steps.

[0124] 8, the side surface 28S1 of the electron supply layer 28 and the side surface 26S1 of the electron transit layer 26 are formed as vertical surfaces, but they may be formed as inclined surfaces that slope outward from the upper end of the side surface 28S1 toward the lower end of the side surface 26S1. In this case, the coverage of the peripheral metal layer 70 is improved, and the potential of the 2DEG 30 is further stabilized.

[0125] The FET 10 of the sixth embodiment has the following advantage in addition to the advantages (1-1) to (1-12) of the first embodiment: (6-1) The peripheral metal layer 70 covers the side surface 26S1 of the electron transit layer 26 and the side surface 28S1 of the electron supply layer 28, which are located at the boundary between the active region 26R1 and the inactive region 26R2, thereby covering the 2DEG 30 exposed at the side surface 26S1 of the electron transit layer 26. This stabilizes the potential of the 2DEG 30, thereby stabilizing the operation of the FET 10.

[0126] (6-2) The peripheral metal layer 70 can be formed of the same metal material as the source electrode 32 and the drain electrode 34. In this case, the peripheral metal layer 70 makes ohmic contact with the 2DEG 30, so that the potential of the DEG 30 exposed on the side surface 26S1 of the electron transit layer 26 becomes constant over the entire periphery of the side surface 26S1. As a result, the operation of the FET 10 becomes more stable. Furthermore, the peripheral metal layer 70 can be formed without adding any additional manufacturing steps.

[0127] Seventh Embodiment Next, a seventh embodiment will be described with reference to Fig. 10 . Fig. 10 is a schematic plan view of an exemplary FET 10 according to the seventh embodiment. Note that in Fig. 10 , components similar to those in the FET 10 of the sixth embodiment are denoted by the same reference numerals. Below, a description of the components similar to those in the FET 10 of the sixth embodiment will be omitted, and only components different from those in the sixth embodiment will be described.

[0128] 10 , the FET 10 of the seventh embodiment differs from the FET 10 of the sixth embodiment in that the peripheral metal layer 70 is electrically connected to the source electrode 32. The other configurations are the same as those of the sixth embodiment. The connection structure between the peripheral metal layer 70 and the source electrode 32 will be described below.

[0129] In the seventh embodiment, the peripheral metal layer 70 includes one or more (two in the example of FIG. 10 ) peripheral metal layer coupling portions 72. The source wiring 44 includes one or more (two in the example of FIG. 10 ) extending portions 45B depending on the number of peripheral metal layer coupling portions 72. The extending portions 45B extend in the second direction (X direction) from the first portion 44A of the source wiring 44 to a position where they intersect with the peripheral metal layer coupling portions 72 in a plan view.

[0130] The extending portion 45B of the source wiring 44 is electrically connected to the peripheral metal layer coupling portion 72 by the connecting conductor 49. For example, the extending portion 45B of the source wiring 44 and the peripheral metal layer coupling portion 72 are connected by the connecting conductor 49 at a peripheral metal layer connection point on the peripheral metal layer coupling portion 72. Two or more connecting conductors 49 are provided at the peripheral metal layer connection point.

[0131] Therefore, the peripheral metal layer 70 is electrically connected to the source electrode 32. As a result, the 2DEG 30 exposed on the side surface 26S1 of the electron transit layer 26 is connected to the peripheral metal layer 70 at the source potential. As a result, the potential of the 2DEG 30 located directly below the source contact peripheral portion 32CP is stabilized at the source potential, and the potential of the 2DEG 30 formed in the active region 26R1 outside the source contact peripheral portion 32CP in a plan view is stabilized at the source potential. This further stabilizes the operation of the FET 10.

[0132] The FET 10 of the seventh embodiment has the following advantage in addition to the advantages (1-1) to (1-12) of the first embodiment and the advantages (6-1) to (6-2) of the sixth embodiment. (7-1) Because the peripheral metal layer 70 is electrically connected to the source electrode 32, the 2DEG 30 exposed on the side surface 26S1 of the electron transit layer 26 is connected to the peripheral metal layer 70 at the source potential. As a result, the potential of the 2DEG 30 formed in the active region 26R1 outside the source contact peripheral portion 32CP in a plan view is stabilized to the source potential. This further stabilizes the operation of the FET 10.

[0133] Eighth Embodiment Next, an eighth embodiment will be described with reference to Fig. 11 . Fig. 11 is a schematic plan view of an exemplary FET 10 according to the eighth embodiment. In Fig. 11 , the same components as those in the FET 10 of the sixth embodiment are denoted by the same reference numerals. Below, a description of the same components as those in the sixth embodiment will be omitted, and only components different from those in the sixth embodiment will be described.

[0134] 11 , the FET 10 of the eighth embodiment differs from the FET 10 of the sixth embodiment in that the peripheral metal layer 70 is electrically connected to the dummy gate structure 50. The other configurations are the same as those of the sixth embodiment. The connection structure between the peripheral metal layer 70 and the dummy gate structure 50 will be described below.

[0135] In the eighth embodiment, the peripheral metal layer 70 includes one or more (two in the example of FIG. 11 ) peripheral metal layer coupling portions 72, as in the seventh embodiment (see FIG. 10 ). The dummy gate structure 50 includes one or more (two in the example of FIG. 11 ) dummy gate coupling portions 52C depending on the number of peripheral metal layer coupling portions 72. Each dummy gate coupling portion 52C is connected to a corresponding peripheral metal layer coupling portion 72 by a connection wiring 74. The connection wiring 74 is arranged in the same layer as the source wiring 44, the drain wiring 46, and the gate wiring 48.

[0136] Each connection wiring 74 is electrically connected to the peripheral metal layer connecting portion 72 by a connection conductor 49. For example, the connection wiring 74 and the peripheral metal layer connecting portion 72 are connected by the connection conductor 49 at a peripheral metal layer connection point on the peripheral metal layer connecting portion 72. Two or more connection conductors 49 are provided at the peripheral metal layer connection point.

[0137] Furthermore, each connection wiring 74 is electrically connected to the dummy gate coupling portion 52C by a connection conductor 49. For example, the connection wiring 74 and the dummy gate coupling portion 52C are connected at a dummy gate connection point on the dummy gate coupling portion 52C by the connection conductor 49. Two or more connection conductors 49 are provided at the dummy gate connection point.

[0138] Therefore, the peripheral metal layer 70 is electrically connected to the dummy gate structure 50. Here, the potential of the 2DEG 30 located directly below the source contact peripheral portion 32CP is maintained at the source potential, and therefore the potential of the 2DEG 30 exposed at the side surface 26S1 of the electron transit layer 26 is also the source potential. Therefore, the peripheral metal layer 70 connected to the 2DEG 30 exposed at the side surface 26S1 of the electron transit layer 26 and the dummy gate structure 50 connected to the peripheral metal layer 70 are at the source potential.

[0139] Therefore, the 2DEG 30 immediately below the dummy gate structure 50 is depleted. As a result, even if an external surge enters the chip, the surge is prevented from entering the active region 26R1 surrounded by the dummy gate structure 50 (i.e., the formation region of the FET cells 12A to 12D).

[0140] The connection wiring 74 may be connected to the source wiring 44. For example, the connection wiring 74 may be formed integrally with the source wiring 44. With this configuration, the peripheral metal layer 70 and the dummy gate structure 50 can be stabilized by the source potential.

[0141] The FET 10 of the eighth embodiment has the advantages (1-1) to (1-12) of the first embodiment and the advantages (6-1) to (6-2) of the sixth embodiment, as well as an advantage similar to (5-1) of the fifth embodiment and an advantage similar to (7-1) of the seventh embodiment.

[0142] Ninth Embodiment Next, a ninth embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 is a schematic plan view of an exemplary FET 10 according to the ninth embodiment, and FIG. 13 is a schematic cross-sectional view taken along line F13-F13 in FIG. 12. Note that in FIGS. 12 and 13, components similar to those in the FET 10 of the first embodiment are denoted by the same reference numerals. Below, a description of components similar to those in the first embodiment will be omitted, and only components different from those in the first embodiment will be described.

[0143] As shown in Fig. 12 , the FET 10 of the ninth embodiment includes a plurality of (eight in the example of Fig. 12 ) FET cells 12. Note that, for the purpose of explanation, the example of Fig. 12 shows eight FET cells 12, but a greater or lesser number of FET cells 12 may be formed. Each FET cell 12 (each source contact portion 32C, each drain contact portion 34C, each gate portion 36G, etc.) can be formed in the same manner as each FET cell 12 of the first embodiment, and therefore detailed description thereof will be omitted here.

[0144] In the ninth embodiment, an inactive region 26R3 is formed within the active region 26R1 in a plan view. For ease of understanding, in the following description, the inactive region 26R2 will be referred to as a first inactive region 26R2, and the inactive region 26R3 will be referred to as a second inactive region 26R3. As shown in FIG. 13 , the second inactive region 26R3 is formed by removing, by etching, a portion of the electron supply layer 28 and the electron transit layer 26 in a region corresponding to the second inactive region 26R3.

[0145] 12 , one or more (three in the example of FIG. 12 ) substrate exposure holes 80 that expose portions of the substrate 22 are formed in the second inactive region 26R3. The substrate exposure holes 80 are formed to a depth that penetrates through the electron transit layer 26 and the buffer layer 24 and reaches the interior of the substrate 22. Therefore, the substrate 22 includes grooves 22A1 formed as the bottoms of the substrate exposure holes 80 at positions corresponding to the substrate exposure holes 80. The substrate exposure holes 80 can be formed by, for example, etching.

[0146] 12 and 13 , a substrate connection conductor 82 is provided in the second inactive region 26R3, embedded in the substrate exposure hole 80 and in contact with the substrate 22. As shown in FIG. 13 , the substrate connection conductor 82 connects the substrate 22 and the source wiring 44, thereby electrically connecting the substrate 22 to the source electrode 32. The material of the substrate connection conductor 82 is not particularly limited, and may be formed of the same metal material as the source wiring 44, for example. Alternatively, the substrate connection conductor 82 may be formed of another metal material that can reduce contact resistance with the substrate 22.

[0147] In the ninth embodiment, the substrate 22 is electrically connected to the source electrode 32, and therefore a source potential is applied to the substrate 22. For example, when the FET 10 is configured as a nitride semiconductor HEMT, the switching speed may decrease due to the influence of electron traps, etc. In this regard, in the ninth embodiment, the potential of the substrate 22 is stabilized at the source potential, thereby suppressing the occurrence of such electron traps, and thereby suppressing a decrease in the switching speed.

[0148] 12 and 13, a step groove 22A2 is formed in the outer periphery of the substrate 22 in the first inactive region 26R2. The step groove 22A2 is formed as a scribe region for dividing the wafer into chips in a dicing process. As shown in FIG. 13, the step groove 22A2 and the recessed grooves 22A1 of each substrate exposure hole 80 are formed at the same depth from the main surface (top surface in FIG. 13) of the substrate 22.

[0149] The scribe region (step groove 22A) is formed by removing, for example, by etching, the outer periphery of the electron transit layer 26, the outer periphery of the buffer layer 24, and the outer periphery of the substrate 22 in the first inactive region 26R2. For example, the scribe region (step groove 22A) can be formed simultaneously with the formation of the substrate exposure holes 80. In this case, the step groove 22A2 and the recessed groove 22A1 of each substrate exposure hole 80 have the same depth. By removing the nitride semiconductor layer (electron transit layer 26 and buffer layer 24) located in the scribe region, it is not necessary to cut the nitride semiconductor in the dicing process. Therefore, problems such as chipping caused by cutting the nitride semiconductor in the dicing process do not occur.

[0150] 12 and 13 , the FET 10 of the ninth embodiment includes a dummy gate structure 90 that is disposed on the electron supply layer 28 along the periphery of the second inactive region 26R3 at a position outside the second inactive region 26R3 in a plan view. For ease of understanding, in the following description, the dummy gate structure 50 will be referred to as a first dummy gate structure 50, and the dummy gate structure 90 will be referred to as a second dummy gate structure 90.

[0151] The second dummy gate structure 90 serves to maintain the periodicity of the cross-sectional shape of the gate portions 36G around the second inactive region 26R3 when the gate structure 36 (each gate portion 36G) is formed through, for example, a photolithography process and an etching process. Note that in the examples of Figures 12 and 13, the dummy gate structure 50 does not control the current flowing between the drain electrode 34 and the source electrode 32 of the FET 10.

[0152] The second dummy gate structure 90 may be formed in the same manner as the first dummy gate structure 50 so as to have a cross-sectional structure similar to that of each gate portion 36G of the gate structure 36. Therefore, the description of the first dummy gate structure 50 in the first embodiment may also be applied to the second dummy gate structure 90.

[0153] For example, the second dummy gate structure 90 (the dummy gate layer 90A and the dummy gate electrode 90B) may be formed in a ring shape. The second dummy gate structure 90 includes a pair of dummy gate structure finger portions 90F1 and 90F2 extending in the first direction (Y direction) similar to the pair of gate structure finger portions 36F1 and 36F2 of each gate portion 36G (the gate layer 36A and the gate electrode 36B). For example, the gate structure finger portions 36F1 and 36F2 and the dummy gate structure finger portions 90F1 and 90F2 are formed to have the same dimensions in the second direction (X direction) in a plan view.

[0154] Furthermore, the distance in the second direction between the dummy gate structure finger portion 90F1 (90F2) and the adjacent source contact portion 32C may be equal to or greater than the distance in the second direction between the gate structure finger portion 36F1 (36F2) and the adjacent source contact portion 32C, for example, 1 to 5 times that distance. This configuration makes it easy to make the cross-sectional shape of the gate structure 36 uniform at the positions of all gate portions 36G (each of the gate structure finger portions 36F1, 36F2), including the gate portion 36G around the second inactive region 26R3. This makes it possible to uniformize the operation of the FET 10 (e.g., a HEMT in the ninth embodiment) across the entire chip, thereby improving the reliability of the FET 10.

[0155] Furthermore, the second dummy gate structure 90 is electrically connected to each of the gate portions 36G (i.e., gate structures 36) adjacent to each other in the first direction by connecting portions 37. The connecting portions 37 are connected to the gate wiring 48 by connecting conductors 49. In this configuration, the capacitance generated by the second dummy gate structure 90 is added to the capacitance generated by the gate structure 36, increasing the gate capacitance of the entire FET 10. This improves the surge resistance of the gate structure 36 and suppresses the occurrence of false firing during switching operations.

[0156] The second dummy gate structure 90 does not necessarily have to be connected to the gate wiring 48. For example, the second dummy gate structure 90 may be connected to the source wiring 44. Alternatively, the second dummy gate structure 90 may have a floating potential. Even in this case, the second dummy gate structure 90 plays a role in maintaining the periodicity of the cross-sectional shape of the gate portion 36G.

[0157] 12, the second dummy gate structure 90 is formed in an annular shape with the same size as each gate portion 36G in a planar view, but may be formed in an annular shape with a size larger than each gate portion 36G in a planar view. In this case, the area of ​​the second inactive region 26R3 and the area of ​​the substrate exposure hole 80 can be increased, making it easier to form the substrate exposure hole 80 by etching. Furthermore, the area of ​​the substrate connecting conductor 82 is also increased, making it possible to stably apply a source potential to the substrate 22.

[0158] In addition to the advantages (1-1) to (1-12) of the first embodiment, the FET 10 of the ninth embodiment has the following advantage: (9-1) The FET 10 includes a second inactive region 26R3, and a substrate connecting conductor 82 that connects the substrate 22 to the source electrode 32 is provided in the second inactive region 26R3. With this configuration, the potential of the substrate 22 is stabilized at the source potential, thereby suppressing the occurrence of electron traps and preventing a decrease in switching speed.

[0159] (9-2) The scribe region (step groove 22A) can be formed simultaneously with the formation of the substrate exposure hole 80. In this case, the nitride semiconductor layer (electron transit layer 26 and buffer layer 24) located in the scribe region is removed. With this configuration, it is not necessary to cut the nitride semiconductor in the dicing step, and therefore problems such as chipping caused by cutting the nitride semiconductor in the dicing step do not occur.

[0160] (9-3) The FET 10 includes a second dummy gate structure 90. The second dummy gate structure 90 serves to maintain the periodicity of the cross-sectional shape of the gate portion 36G around the second inactive region 26R3. The second dummy gate structure 90 can also provide advantages similar to those provided by the first dummy gate structure 50 described in the first embodiment.

[0161] Tenth Embodiment Next, a tenth embodiment will be described with reference to Fig. 14. Fig. 14 is a schematic plan view of an exemplary FET 10 according to the tenth embodiment. In Fig. 14, components similar to those of the FET 10 of the ninth embodiment are denoted by the same reference numerals. Below, a description of the components similar to those of the ninth embodiment will be omitted, and only components different from those of the ninth embodiment will be described.

[0162] 14 , the FET 10 of the tenth embodiment differs from the FET 10 of the ninth embodiment in that the substrate connecting conductor 82 is not connected to the source wiring 44. The other configurations are the same as those of the ninth embodiment. With this configuration, a desired potential may be applied to the substrate 22 via the substrate connecting conductor 82 by any means. This increases the versatility of the FET 10, allowing it to be used for various applications, for example, by applying the source potential of a low-side FET to the substrate 22 as a potential different from the source potential of the high-side FET of a half bridge.

[0163] The FET 10 of the tenth embodiment has advantages similar to those of the first embodiment (1-1) to (1-12) and the ninth embodiment (9-1) to (9-3). [Eleventh Embodiment] Next, the eleventh embodiment will be described with reference to FIG. 15 . FIG. 15 is a schematic plan view of an exemplary FET 10 according to the eleventh embodiment. Note that in FIG. 15 , components similar to those of the FET 10 of the tenth embodiment are denoted by the same reference numerals. Below, a description of the components similar to those of the tenth embodiment will be omitted, and only components different from those of the tenth embodiment will be described.

[0164] 15 , the FET 10 of the eleventh embodiment differs from the FET 10 of the tenth embodiment in that the second dummy gate structure 90 is electrically connected to the source electrode 32. The other configurations are the same as those of the tenth embodiment.

[0165] In the eleventh embodiment, the second dummy gate structure 90 includes one or more (two in the example of FIG. 15 ) dummy gate coupling portions 92. The source wiring 44 is electrically connected to the dummy gate coupling portions 92 by connecting conductors 49. For example, the source wiring 44 and the dummy gate coupling portions 92 are connected by the connecting conductors 49 at dummy gate connection points on each dummy gate coupling portion 92. Two or more connecting conductors 49 are provided at each dummy gate connection point.

[0166] Therefore, the second dummy gate structure 90 is electrically connected to the source electrode 32. In this configuration, the 2DEG 30 directly below the second dummy gate structure 90 is depleted. As a result, even if a surge enters the chip from the second inactive region 26R3, the surge is prevented from entering the active region 26R1 outside the second dummy gate structure 90 (i.e., into the formation region of each FET cell 12).

[0167] The FET 10 of the eleventh embodiment has the following advantage in addition to the advantages (1-1) to (1-12) of the first embodiment and the advantages (9-1) to (9-3) of the ninth embodiment: (11-1) Because the second dummy gate structure 90 is electrically connected to the source electrode 32, the 2DEG 30 directly below the second dummy gate structure 90 is depleted. As a result, even if a surge enters the chip from the second inactive region 26R3, the surge is prevented from entering the active region 26R1 outside the second dummy gate structure 90, thereby further improving surge resistance.

[0168] The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0169] The FET 10 in each of the above embodiments is not limited to using GaN. For example, nitride semiconductors such as AlN or InN may be used instead of GaN. The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Therefore, the expression "a first layer is formed on a second layer" means that in some embodiments, the first layer may be in contact with the second layer and disposed directly on the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers. For example, the above embodiments in which the electron supply layer 28 is formed on the electron transit layer 26 also include a structure in which an intermediate layer is disposed between the electron supply layer 28 and the electron transit layer 26 to stably form the 2DEG 30.

[0170] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0171] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "forward," "rearward," "sideways," "left," "right," "front," "rear," etc., used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations can be envisioned in this disclosure, and therefore these directional terms should not be interpreted narrowly.

[0172] [Notes] The technical ideas that can be understood from the above-described embodiments and modifications are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference numerals.

[0173] (Supplementary Note 1) A semiconductor device comprising: a substrate (22); a first nitride semiconductor layer (26) disposed above the substrate (22); a second nitride semiconductor layer (28) having a band gap larger than that of the first nitride semiconductor layer (26) and disposed on the first nitride semiconductor layer (26) to generate a two-dimensional electron gas (30) in the first nitride semiconductor layer (26) near an interface with the first nitride semiconductor layer (26); and a source electrode (32), a drain electrode (34), and a gate structure (36) disposed on the second nitride semiconductor layer (28), wherein the first nitride semiconductor layer (26) includes an active region (26R1) in which the two-dimensional electron gas (30) can be generated, and a non-active region (26R2) surrounding the active region (26R1) in a planar view, the source electrode (32), the drain electrode (34), and the gate structure (36) are disposed on the second nitride semiconductor layer (28) in a region corresponding to the active region (26R1), and the source electrode (32) includes a source contact peripheral portion (32CP) that surrounds the drain electrode (34) and the gate structure (36) in a planar view and is in contact with the second nitride semiconductor layer (28) along the periphery of the second nitride semiconductor layer (28) corresponding to the boundary between the active region (26R1) and the non-active region (26R2).

[0174] (Supplementary Note 2) The field effect transistor (10) according to Supplementary Note 1, wherein the source contact peripheral portion (32CP) is formed in a ring shape along the outer periphery of the second nitride semiconductor layer (28).

[0175] (Supplementary Note 3) The drain electrode (34) includes a plurality of drain contact portions (34C1, 34C2, 34C3, 34C4) in contact with the second nitride semiconductor layer (28), the plurality of drain contact portions being arranged spaced apart from one another in a first direction (Y) and a second direction (X) perpendicular to the first direction (Y) in a plan view, the plurality of drain contact portions (34C1, 34C2, 34C3, 34C4) each having a finger shape extending in the first direction (Y), the gate structure (36) includes a plurality of gate portions (36G1, 36G2, 36G3, 36G4) each annularly surrounding one of the plurality of drain contact portions (34C1, 34C2, 34C3, 34C4), The field-effect transistor (10) according to Appendix 1 or 2, wherein the source electrode (32) includes one or more source contact portions (32C1, 32C2; 32CX) arranged between two of the gate portions (36G1, 36G2; 36G3, 36G4) adjacent to each other in the second direction (X) and in contact with the second nitride semiconductor layer (28).

[0176] (Supplementary Note 4) The field effect transistor (10) according to Supplementary Note 3, wherein each of the one or more source contact portions (32CX) is directly coupled to the source contact periphery portion (32CP).

[0177] (Supplementary Note 5) The field-effect transistor (10) according to any one of Supplementary Notes 1 to 4, wherein the inactive region (26R2) is formed by removing a portion of the first nitride semiconductor layer (26) together with a portion of the second nitride semiconductor layer (28) located immediately above the portion.

[0178] (Supplementary Note 6) The field-effect transistor (10) according to any one of Supplementary Notes 1 to 5, further comprising: the first nitride semiconductor layer (26) includes a side surface (26S1) at a boundary position between the active region (26R1) and the non-active region (26R2); the second nitride semiconductor layer (28) includes a side surface (28S1) formed continuously with the side surface (26S1) of the first nitride semiconductor layer (26); and an outer metal layer (70) covering the side surface (26S1) of the first nitride semiconductor layer (26) and the side surface (28S1) of the second nitride semiconductor layer (28).

[0179] (Supplementary Note 7) The field effect transistor (10) according to Supplementary Note 6, wherein the outer peripheral metal layer (70) is formed in an annular shape.

[0180] (Supplementary Note 8) The field effect transistor (10) according to Supplementary Note 6 or 7, wherein the peripheral metal layer (70) is formed of the same material as the source electrode (32).

[0181] (Supplementary Note 9) The field effect transistor (10) according to any one of Supplementary Notes 1 to 8, further comprising a dummy gate structure (50) arranged on the second nitride semiconductor layer (28) along the periphery of the second nitride semiconductor layer (28) at a position outside the source contact periphery (32CP) in a plan view.

[0182] (Supplementary Note 10) A field effect transistor (10) according to Supplementary Note 9, wherein the drain electrode (34) extends in a first direction (Y) in a plan view, the gate structure (36) includes gate structure finger portions (36F1, 36F2) parallel to the first direction (Y), the dummy gate structure (50) includes dummy gate structure finger portions (50F1, 50F2) parallel to the first direction (Y), and the gate structure finger portions (36F1, 36F2) and the dummy gate structure finger portions (50F1, 50F2) are formed with the same dimensions in a second direction (X) perpendicular to the first direction (Y) in a plan view.

[0183] (Supplementary Note 11) The drain electrode (34) extends in a first direction (Y) in a plan view, The gate structure (36) includes gate structure finger portions (36F1, 36F2) parallel to the first direction (Y), The dummy gate structure (50) includes dummy gate structure finger portions (50F1, 50F2) parallel to the first direction (Y), The source contact outer periphery portion (32CP) includes source outer periphery finger portions (32F1, 32F2) parallel to the first direction (Y), The dummy gate structure finger portions (50F1, 50F2) and the source outer periphery finger portions (32F1, 32F2) are adjacent to each other at a first interval in a second direction (X) perpendicular to the first direction (Y) in a plan view, The field-effect transistor (10) according to Appendix 9, wherein the gate structure finger portions (36F1, 36F2) and the source peripheral finger portions (32F1, 32F2) are adjacent to each other at a second interval in the second direction (X) in a plan view, and the first interval is equal to or greater than the second interval.

[0184] (Supplementary Note 12) The field effect transistor (10) according to any one of Supplementary Notes 9 to 11, wherein the dummy gate structure (50) is formed in a ring shape along the outer periphery of the second nitride semiconductor layer (28).

[0185] (Supplementary Note 13) The field effect transistor (10) according to any one of Supplementary Notes 9 to 12, wherein the dummy gate structure (50) is electrically connected to the gate structure (36) or the source electrode (32).

[0186] (Supplementary Note 14) The field-effect transistor (10) according to any one of Supplementary Notes 6 to 8, further comprising a dummy gate structure (50) arranged on the second nitride semiconductor layer (28) along the periphery of the second nitride semiconductor layer (28) at a position outside the source contact periphery (32CP) in a planar view, and the peripheral metal layer (70) is electrically connected to the dummy gate structure (50) or the source electrode (32).

[0187] (Supplementary Note 15) A field-effect transistor (10) according to any one of Supplementary Notes 1 to 14, comprising: an insulating layer (38, 42) covering the source electrode (32), the drain electrode (34), and the gate structure (36); a source wiring (44), a drain wiring (46), and a gate wiring (48) arranged on the insulating layer (38, 42) in a region corresponding to the active region (26R1); and a plurality of connecting conductors (49) penetrating the insulating layer (38, 42), the plurality of connecting conductors (49) including a connecting conductor (49) electrically connecting the source wiring (44) and the source electrode (32), a connecting conductor (49) electrically connecting the drain wiring (46) and the drain electrode (34), and a connecting conductor (49) electrically connecting the gate wiring (48) and the gate structure (36).

[0188] (Supplementary Note 16) The field effect transistor (10) according to Supplementary Note 15, wherein the drain wiring (46) is surrounded by the source wiring (44) in a plan view.

[0189] (Supplementary Note 17) The field effect transistor (10) according to Supplementary Note 15 or 16, wherein the gate wiring (48) is adjacent to the source wiring (44) in a plan view.

[0190] (Supplementary Note 18) The semiconductor device includes an insulating layer (38, 42) covering the source electrode (32), the drain electrode (34), and the gate structure (36); a source wiring (44), a drain wiring (46), and a gate wiring (48) arranged on the insulating layer (38, 42) in a region corresponding to the active region (26R1); and a plurality of connection conductors (49) penetrating the insulating layer (38, 42), wherein the plurality of connection conductors (49) are: two or more connection conductors (49) provided at each of a plurality of source connection points connecting the source wiring (44) and each of the source contact portions; and two or more connection conductors (49) provided at each of a plurality of source peripheral connection points connecting the source wiring (44) and each of the source contact peripheral portions (32CP). two or more connection conductors (49) provided at each of a plurality of drain connection points that connect the drain wiring (46) and each of the drain contact portions (34C1, 34C2, 34C3, 34C4); and two or more connection conductors (49) provided at a gate connection point that connects the gate wiring (48) and a connection portion (37) that connects two of the gate portions (36G1, 36G3; 36G2, 36G4) adjacent to each other in the first direction (Y).

[0191] (Supplementary Note 19) A semiconductor device comprising: an insulating layer (38, 42) covering the source electrode (32), the drain electrode (34), and the gate structure (36); a source wiring (44), a drain wiring (46), and a gate wiring (48) arranged on the insulating layer (38, 42) in a region corresponding to the active region (26R1); and a plurality of connection conductors (49) penetrating the insulating layer (38, 42), the plurality of connection conductors (49) including a connection conductor (49) electrically connecting the source wiring (44) and the source electrode (32), a connection conductor (49) electrically connecting the drain wiring (46) and the drain electrode (34), and a connection conductor (49) electrically connecting the gate wiring (48) and the gate structure (36), 5. The field-effect transistor (10) according to claim 3 or 4, wherein the gate wiring (48) is arranged to extend in the second direction (X) between two of the gate portions (36G1, 36G3; 36G2, 36G4) adjacent to each other in the first direction (Y).

[0192] (Supplementary Note 20) The field-effect transistor (10) according to any one of Supplementary Notes 1 to 19, wherein the inactive region (26R2) is a first inactive region (26R2), the first nitride semiconductor layer (26) further includes a second inactive region (26R3) provided inside the active region (26R1) in a planar view, and the field-effect transistor (10) further includes a substrate exposure hole (80) exposing a portion of the substrate (22) in the second inactive region (26R3).

[0193] (Supplementary Note 21) The field effect transistor (10) according to Supplementary Note 20, further comprising a substrate connection conductor (82) provided in the substrate exposure hole (80) and electrically connecting the substrate (22) to the source electrode (32).

[0194] (Appendix 22) The field-effect transistor (10) according to appendix 20 or 21, wherein the substrate (22) includes a step groove (22A2) formed as a scribe region in the first inactive region (26R2), and a recessed groove (22A1) formed as a bottom of the substrate exposure hole (80) in the second inactive region (26R3), and the step groove (22A2) and the recessed groove (22A1) are formed at the same depth from a main surface of the substrate (22).

[0195] (Supplementary Note 23) The field-effect transistor (10) according to any one of Supplementary Notes 9 to 14, further comprising: the inactive region (26R2) is a first inactive region (26R2); the dummy gate structure (50) is a first dummy gate structure (50); the first nitride semiconductor layer (26) further includes a second inactive region (26R3) provided inside the active region (26R1) in a planar view; a substrate exposure hole (80) exposing a part of the substrate (22) in the second inactive region (26R3); and a second dummy gate structure (90) arranged on the second nitride semiconductor layer (28) along an outer periphery of the second inactive region (26R3) at a position outer than the second inactive region (26R3) in a planar view.

[0196] (Supplementary Note 24) The field effect transistor (10) according to Supplementary Note 23, wherein the second dummy gate structure (90) is electrically connected to the gate structure (36) or the source electrode (32).

[0197] (Supplementary Note 25) The insulating layer (38, 42) is a first insulating layer (38, 42), the source wiring (44) is a first source wiring (44), the drain wiring (46) is a first drain wiring (46), the gate wiring (48) is a first gate wiring (48), and the plurality of connecting conductors are a plurality of first connecting conductors; a second insulating layer covering the first source wiring (44), the first drain wiring (46), and the first gate wiring (48); a second source wiring (62), a second drain wiring (64), and a second gate wiring (66) arranged on the second insulating layer in a region corresponding to the active region (26R1); a plurality of second connection conductors (68) penetrating the second insulating layer, the plurality of second connection conductors (68) including a second connection conductor (68) electrically connecting the first source wiring (44) and the second source wiring (62), a second connection conductor (68) electrically connecting the first drain wiring (46) and the second drain wiring (64), and a second connection conductor (68) electrically connecting the first gate wiring (48) and the second gate wiring (66).

[0198] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0199] DESCRIPTION OF SYMBOLS 10... Field effect transistor 22... Substrate 22A1... Groove 22A2... Step groove 24... Buffer layer 26... Electron transit layer (first nitride semiconductor layer) 26R1... Active region 26R2... Inactive region (first inactive region) 26R3... Inactive region (second inactive region) 26S1... Side surface 28... Electron supply layer (second nitride semiconductor layer) 28S1... Side surface 30... Two-dimensional electron gas (2DEG) 32... Source electrode 32C1, 32C2, 32CX... Source contact portion 32CP... Source contact periphery portion 32F1, 32F2... Source periphery finger portion 34... Drain electrode 34C1, 34C2, 34C3, 34C4... Drain contact portion 36... Gate structure 36G1, 36G2, 36G3, 36G4... Gate portion 36F1, 36F2...Gate structure finger portion 37...Coupling portion 38...Passivation layer (insulating layer) 42...Interlayer insulating layer (insulating layer) 44...Source wiring 46...Drain wiring 48...Gate wiring 50...Dummy gate structure (first dummy gate structure) 50A...Dummy gate layer 50B...Dummy gate electrode 50F1, 50F2...Dummy gate structure finger portion 62...Source pad 64...Drain pad 66...Gate pad 68...Connecting conductor 70...Peripheral metal layer 80...Substrate exposure hole 82...Substrate connecting conductor 90...Dummy gate structure (second dummy gate structure)

Claims

1. A substrate; a first nitride semiconductor layer disposed above the substrate; a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer and disposed on the first nitride semiconductor layer so as to generate two-dimensional electron gas in the first nitride semiconductor layer near an interface with the first nitride semiconductor layer; a source electrode, a drain electrode, and a gate structure disposed on the second nitride semiconductor layer; the first nitride semiconductor layer includes an active region in which the two-dimensional electron gas can be generated, and a non-active region surrounding the active region in a plan view; the source electrode, the drain electrode, and the gate structure are disposed on the second nitride semiconductor layer in a region corresponding to the active region; the source electrode includes a source contact peripheral portion that surrounds the drain electrode and the gate structure in a planar view and is in contact with the second nitride semiconductor layer along a periphery of the second nitride semiconductor layer corresponding to a boundary between the active region and the non-active region.

2. The field effect transistor according to claim 1 , wherein the outer periphery of the source contact is formed in a ring shape along an outer periphery of the second nitride semiconductor layer.

3. the drain electrode includes a plurality of drain contact portions in contact with the second nitride semiconductor layer, the plurality of drain contact portions being arranged spaced apart from one another in a first direction and a second direction perpendicular to the first direction in a plan view; Each of the drain contact portions has a finger shape extending in the first direction, the gate structure includes a plurality of gate portions each annularly surrounding one of the plurality of drain contact portions; 3 . The field effect transistor according to claim 1 , wherein the source electrode includes one or more source contact portions disposed between two of the gate portions adjacent to each other in the second direction and in contact with the second nitride semiconductor layer.

4. The field effect transistor of claim 3 , wherein each of the one or more source contact portions is directly coupled to the source contact periphery.

5. the first nitride semiconductor layer includes a side surface at a boundary between the active region and the non-active region; the second nitride semiconductor layer includes a side surface formed continuously with a side surface of the first nitride semiconductor layer, The field effect transistor according to claim 1 , further comprising an outer periphery metal layer covering a side surface of the first nitride semiconductor layer and a side surface of the second nitride semiconductor layer.

6. The field effect transistor according to claim 5 , wherein the peripheral metal layer is formed in an annular shape.

7. The field effect transistor according to claim 1 , further comprising a dummy gate structure arranged on the second nitride semiconductor layer along a periphery of the second nitride semiconductor layer at a position outside a periphery of the source contact in a plan view.

8. The drain electrode extends in a first direction in a plan view, the gate structure includes gate structure fingers parallel to the first direction; the dummy gate structure includes a dummy gate structure finger portion parallel to the first direction; 8. The field effect transistor according to claim 7, wherein the gate structure finger portion and the dummy gate structure finger portion are formed to have the same dimensions in a second direction perpendicular to the first direction in a plan view.

9. The drain electrode extends in a first direction in a plan view, the gate structure includes gate structure fingers parallel to the first direction; the dummy gate structure includes a dummy gate structure finger portion parallel to the first direction; the source contact outer periphery includes a source outer periphery finger portion parallel to the first direction; the dummy gate structure finger portion and the source outer peripheral finger portion are adjacent to each other at a first interval in a second direction perpendicular to the first direction in a plan view, the gate structure finger portion and the source outer peripheral finger portion are adjacent to each other at a second interval in the second direction in a plan view, The field effect transistor of claim 7 , wherein the first spacing is greater than or equal to the second spacing.

10. The field effect transistor according to claim 7 , wherein the dummy gate structure is formed in a ring shape along an outer periphery of the second nitride semiconductor layer.

11. The field effect transistor of claim 7 , wherein the dummy gate structure is electrically connected to the gate structure or the source electrode.

12. a dummy gate structure disposed on the second nitride semiconductor layer along an outer periphery of the second nitride semiconductor layer at a position outside the outer periphery of the source contact in a plan view, The field effect transistor of claim 5 , wherein the peripheral metal layer is electrically connected to the dummy gate structure or the source electrode.

13. an insulating layer covering the source electrode, the drain electrode, and the gate structure; a source wiring, a drain wiring, and a gate wiring disposed on the insulating layer in a region corresponding to the active region; a plurality of connection conductors penetrating the insulating layer, the connection conductors including a connection conductor electrically connecting the source wiring and the source electrode, a connection conductor electrically connecting the drain wiring and the drain electrode, and a connection conductor electrically connecting the gate wiring and the gate structure; 3. The field effect transistor according to claim 1, comprising:

14. The field effect transistor according to claim 13 , wherein the drain wiring is surrounded by the source wiring in a plan view.

15. The field effect transistor according to claim 13 , wherein the gate wiring is adjacent to the source wiring in a plan view.

16. an insulating layer covering the source electrode, the drain electrode, and the gate structure; a source wiring, a drain wiring, and a gate wiring disposed on the insulating layer in a region corresponding to the active region; a plurality of connection conductors penetrating the insulating layer, the connection conductors including a connection conductor electrically connecting the source wiring and the source electrode, a connection conductor electrically connecting the drain wiring and the drain electrode, and a connection conductor electrically connecting the gate wiring and the gate structure; The field effect transistor according to claim 3 , wherein the gate wiring is disposed so as to extend in the second direction between two of the gate portions adjacent to each other in the first direction.

17. the non-active region is a first non-active region, the first nitride semiconductor layer further includes a second inactive region provided inside the active region in a plan view, The field effect transistor according to claim 1 , further comprising a substrate exposure hole exposing a portion of the substrate in the second non-active region.

18. The substrate is a step groove formed as a scribe region in the first non-active region; a groove formed as a bottom of the substrate exposure hole in the second non-active region, 18. The field effect transistor according to claim 17, wherein the step groove and the recessed groove are formed to the same depth from the main surface of the substrate.

19. the non-active region is a first non-active region, the dummy gate structure is a first dummy gate structure, the first nitride semiconductor layer further includes a second inactive region provided inside the active region in a plan view, a substrate exposure hole exposing a portion of the substrate in the second non-active region; a second dummy gate structure disposed on the second nitride semiconductor layer along an outer periphery of the second non-active region at a position outside the second non-active region in a plan view; The field effect transistor of claim 7 further comprising:

20. 20. The field effect transistor of claim 19, wherein the second dummy gate structure is electrically connected to the gate structure or the source electrode.