Output feedback circuit, linear electric power source

Abstract

In the present invention, for example, an output feedback circuit X comprises: an error amplifier 10 that is configured to generate an error signal S0 of the same phase as an output voltage Vout in accordance with the difference between an output voltage Vout or a feedback voltage Vfb corresponding to the output voltage Vout, and a prescribed reference voltage Vref; an amplifier 20 that is configured to generate a signal G0 for driving an output transistor M0 by amplifying the error signal S0; a signal wire L1 that is configured to transmit the error signal S0 to the amplifier 20; and a shield wire L2 that is laid so as to run in parallel adjacent to the signal wire L1 and is configured to have the output voltage Vout or a voltage of the same phase as the output voltage Vout be applied thereto.

Description

Output feedback circuit, linear power supply

[0001] The present disclosure relates to an output feedback circuit and a linear power supply using the same.

[0002] An output feedback circuit is incorporated into a linear power supply or the like that generates a desired output voltage from an input voltage (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2021-033472

[0004] However, in conventional output feedback circuits, there is room for improvement in both noise immunity and transient response characteristics.

[0005] For example, the output feedback circuit disclosed in this specification includes an error amplifier configured to generate an error signal in phase with the output voltage in accordance with the difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage; an amplifier configured to generate a drive signal for an output transistor by amplifying the error signal; a signal wiring configured to transmit the error signal from the output end of the error amplifier to the input end of the amplifier; and a shield wiring laid adjacent to and running parallel to the signal wiring, configured to apply the output voltage or a voltage in phase therewith.

[0006] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto.

[0007] According to the present disclosure, it is possible to provide an output feedback circuit that can improve both noise resistance and transient response characteristics, and a linear power supply that uses the same.

[0008] FIG. 1 is a diagram showing a comparative example of a linear power supply. FIG. 2 is a diagram showing a first embodiment of the linear power supply. FIG. 3 is a diagram showing an example configuration of an error amplifier and an amplifier. FIG. 4 is a diagram showing a planar layout of signal wiring and shield wiring. FIG. 5 is a diagram showing parasitic capacitance associated with wiring. FIG. 6 is a diagram showing parasitic capacitance in the linear power supply of the first embodiment. FIG. 7 is a diagram showing a second embodiment of the linear power supply. FIG. 8 is a diagram showing parasitic capacitance in the linear power supply of the second embodiment. FIG. 9 is a diagram showing behavior of the output voltage during a sudden change in output current. FIG. 10 is a diagram showing a third embodiment of the linear power supply. FIG. 11 is a diagram showing parasitic capacitance in the linear power supply of the third embodiment. FIG. 12 is a diagram showing a fourth embodiment of the linear power supply. FIG. 13 is a diagram showing a fifth embodiment of the linear power supply. FIG. 14 is a diagram showing a sixth embodiment of the linear power supply.

[0009] <Linear Power Supply (Comparative Example)> Figure 1 is a diagram showing a comparative example of a linear power supply (= an example of a general circuit configuration to be compared with the embodiments described below). A linear power supply 1 of this comparative example generates a desired output voltage Vout from an input voltage Vin and supplies it to a load 2 connected to an output terminal OUT. For example, linear power supply 1 may be an LDO (low drop out) regulator.

[0010] Referring to the figure, the linear power supply 1 includes an output transistor M0, an error amplifier 10, an amplifier 20, and a feedback voltage generating circuit 30. Note that some or all of these components may be integrated into a semiconductor device.

[0011] The output transistor M0 is connected between the application terminal of the input voltage Vin and the application terminal of the output voltage Vout. Referring to the figure, the output transistor M0 may be, for example, a PMOSFET (P-channel type metal oxide semiconductor field effect transistor). In this case, the source of the output transistor M0 is connected to the application terminal of the input voltage Vin, and the drain of the output transistor M0 is connected to the application terminal of the output voltage Vout.

[0012] The error amplifier 10 generates an error signal S0 according to the difference between a feedback voltage Vfb input to its non-inverting input terminal (+) and a reference voltage Vref input to its inverting input terminal (-). The reference voltage Vref may be a constant voltage that is not easily affected by the input voltage Vin and the ambient temperature.

[0013] The error signal S0 decreases when the feedback voltage Vfb is lower than the reference voltage Vref, and increases when the feedback voltage Vfb is higher than the reference voltage Vref. In other words, the error signal S0 decreases when the output voltage Vout is lower than the target value, and increases when the output voltage Vout is higher than the target value. In this way, the error amplifier 10 generates the error signal S0 in phase with the output voltage Vout according to the difference between the feedback voltage Vfb and the reference voltage Vref.

[0014] The error signal S0 is transmitted from the output terminal of the error amplifier 10 to the input terminal of the amplifier 20 via a signal line L1.

[0015] The amplifier 20 amplifies the error signal S0 to generate a drive signal G0 for the output transistor M0 and outputs it to the gate of the output transistor M0. If the output transistor M0 is a P-channel type (or a PNP type), the amplifier 20 may be a non-inverting output type (a so-called buffer) that generates a drive signal G0 of the same polarity (same logical level) as the error signal S0.

[0016] Generally, the gain of the error amplifier 10 is not very high. Therefore, an amplifier 20 for amplifying the error signal S0 is often provided after the error amplifier 10.

[0017] The higher the drive signal G0, the lower the gate-source voltage of the output transistor M0. Therefore, the on-resistance of the output transistor M0 increases, and the output current Iout flowing through the output transistor M0 decreases. As a result, the output voltage Vout decreases.

[0018] Conversely, the lower the drive signal G0, the higher the gate-source voltage of the output transistor M0. Therefore, the on-resistance of the output transistor M0 decreases, and the output current Iout flowing through the output transistor M0 increases. As a result, the output voltage Vout increases.

[0019] The feedback voltage generating circuit 30 includes resistors 31 and 32 connected in series between the output terminal OUT and the ground terminal, and divides the output voltage Vout to generate the feedback voltage Vfb. Note that the feedback voltage generating circuit 30 may be omitted and the output voltage Vout may be directly input to the error amplifier 10.

[0020] Among the above components, the error amplifier 10, the amplifier 20, and the feedback voltage generating circuit 30 form an output feedback circuit X for controlling the drive of the output transistor M0 so that the feedback voltage Vfb coincides with the reference voltage Vref.

[0021] The error amplifier 10 operates by receiving a bias current Ib1 generated by the current source 11. However, if it is necessary to reduce the current consumption of the linear power supply 1, the bias current Ib1 of the error amplifier 10 is also one of the currents to be reduced. If the bias current Ib1 of the error amplifier 10 is reduced, the output impedance of the error amplifier 10 increases, making the error signal S0 more susceptible to noise and other influences. As a result, the linear power supply 1 may malfunction or the stability of the output voltage Vout may be impaired.

[0022] Various embodiments that can solve the above problems will be proposed below.

[0023] <Linear Power Supply (First Embodiment)> Fig. 2 is a diagram showing a first embodiment of a linear power supply. The linear power supply 1 of the first embodiment is based on the comparative example (Fig. 1) described above, and further includes a shield wiring L2.

[0024] As indicated by the dashed dotted line in the figure, the shield wiring L2 is laid adjacent to and runs parallel to the signal wiring L1.

[0025] A plurality of shield wirings L2 may be laid in the same wiring layer as the shield wiring L2 so as to sandwich the signal wiring L1 in a planar manner. Alternatively, a plurality of shield wirings L2 may be laid in each of the wiring layers immediately above and below the wiring layer in which the signal wiring L1 is laid so as to sandwich the signal wiring L1 in a three-dimensional manner.

[0026] The shield wiring L2 is connected to a stable potential node (for example, a ground terminal) via a low-impedance conductive path.

[0027] 3 is a diagram showing an example of the configuration of the error amplifier 10 and the amplifier 20. The error amplifier 10 includes transistors 12 and 13 (e.g., PMOSFETs) and transistors 14 and 15 (e.g., NMOSFETs [N-channel type MOSFETs]) in addition to the aforementioned current source 11. The amplifier 20 of this example configuration includes a current source 21 and a transistor 22 (e.g., an NMOSFET).

[0028] The current source 11 is connected between the application terminal of the input voltage Vin and the sources of the transistors 12 and 13, and generates a bias current Ib1.

[0029] The gate of the transistor 12 is connected to the application terminal of the feedback voltage Vfb as the non-inverting input terminal (+) of the error amplifier 10. The gate of the transistor 13 is connected to the application terminal of the reference voltage Vref as the inverting input terminal (-) of the error amplifier 10.

[0030] The gates of the transistors 14 and 15 are both connected to the drain of the transistor 14. The drain of the transistor 14 is connected to the drain of the transistor 12. The drains of the transistors 13 and 15 are both connected to the first end of the signal line L1 as the output end of the error amplifier 10 (= the application end of the error signal S0). The sources of the transistors 14 and 15 are both connected to the ground end.

[0031] The current source 21 is connected between the application terminal of the input voltage Vin and the drain of the transistor 22, and generates a bias current Ib2.

[0032] The drain of the transistor 22 is connected to the application terminal of the drive signal G0 as the output terminal of the amplifier 20. The gate of the transistor 22 is connected to the second terminal of the signal line L1 as the input terminal of the amplifier 20. The source of the transistor 22 is connected to the ground terminal.

[0033] As described above, in addition to the signal wiring L1, a shield wiring L2 is laid between the output terminal of the error amplifier 10 and the input terminal of the amplifier 20 so as to run adjacent to and parallel to the signal wiring L1. The shield wiring L2 is connected to a stable potential node (for example, a ground terminal) via a low-impedance conductive path.

[0034] In the linear power supply 1 of the first embodiment, noise and the like superimposed from the outside can be guided to the shield wiring L2, and therefore the error signal S0 is less susceptible to the effects of noise and the like.

[0035] 4 is a diagram showing a planar layout of signal wiring L1 (solid lines) and shield wiring L2 (dashed lines) on a semiconductor substrate on which the error amplifier 10 and amplifier 20 are integrated. Note that the symbols D, S, and G in the diagram schematically indicate the drain, source, and gate of transistors 12 to 15 and transistor 22, respectively.

[0036] As shown in this figure, the signal wiring L1 and the shield wiring L2 run parallel to each other for a relatively long distance, connecting the output terminal of the error amplifier 10 (= the drains D of the transistors 13 and 15) and the input terminal of the amplifier 20 (= the gate of the transistor 22).

[0037] FIG. 5 is a diagram showing the parasitic capacitance occurring between the signal wiring L1 and the shield wiring L2 (corresponding to a partially enlarged view of the peripheral area of ​​the transistor 22 in FIG. 4).

[0038] As shown in the figure, a parasitic capacitance Cp exists between the signal wiring L1 and the shield wiring L2, with the signal wiring L1 and the shield wiring L2 acting as electrodes. The capacitance value of the parasitic capacitance Cp increases as the parallel running distance of the signal wiring L1 and the shield wiring L2 increases.

[0039] 6 is a diagram showing the parasitic capacitance Cp in the linear power supply 1 of the first embodiment. As shown in this diagram, when the output feedback circuit X is viewed as an equivalent circuit, the parasitic capacitance Cp described above is attached between the signal wiring L1 (= the application terminal of the error signal S0) and the ground terminal.

[0040] Therefore, a delay occurs in the error signal S0, dulling the waveform, deteriorating the transient response characteristics of the error amplifier 10 (and ultimately the linear power supply 1). In particular, when the bias current Ib1 is small, as mentioned above, the output impedance of the error amplifier 10 tends to increase, making it more susceptible to the effects of the parasitic capacitance Cp.

[0041] <Linear Power Supply (Second Embodiment)> Fig. 7 is a diagram showing a second embodiment of the linear power supply. The linear power supply 1 of the second embodiment is based on the first embodiment (Fig. 2) described above, but the shield wiring L2 is connected to the application of the output voltage Vout rather than to the ground terminal.

[0042] 8 is a diagram showing the parasitic capacitance Cp in the linear power supply 1 of the second embodiment. As shown in this diagram, when the output feedback circuit X is viewed as an equivalent circuit, the parasitic capacitance Cp described above is associated between the signal wiring L1 (= the application terminal of the error signal S0) and the application terminal of the output voltage Vout.

[0043] In this way, by capacitively connecting the signal wiring L1 (= the application terminal of the error signal S0) and the application terminal of the output voltage Vout, the AC component of the output voltage Vout is directly propagated to the error signal S0. As mentioned above, the error signal S0 is a voltage signal in phase with the output voltage Vout. This improves the transient response characteristics of the error amplifier 10 (and therefore the linear power supply 1) in the high frequency range. Furthermore, because the application terminal of the output voltage Vout has low impedance, the inherent shielding effect of the shield wiring L2 is not impaired.

[0044] 9 is a diagram showing the behavior of the output voltage Vout when the output current Iout suddenly changes. Regarding the output voltage Vout, the solid line indicates the behavior of the second embodiment (denoted as "Vout shield"), the large dashed line indicates the behavior of the first embodiment (denoted as "GND shield"), and the small dashed line indicates the behavior of the comparative example (denoted as "no shield").

[0045] From this figure, it can be seen that the linear power supply 1 of the second embodiment (FIG. 7) can suppress fluctuations in the output voltage Vout even when the output current Iout suddenly changes, compared to the comparative example (FIG. 1) and the first embodiment (FIG. 2) mentioned above.

[0046] <Linear Power Supply (Third Embodiment)> Figure 10 is a diagram showing a third embodiment of a linear power supply. The linear power supply 1 of the third embodiment is based on the second embodiment (Figure 7) described above, but the P-channel output transistor M0 is replaced with an N-channel output transistor M0'. In this case, the drain of the output transistor M0' is connected to the application terminal of the input voltage Vin, and the source of the output transistor M0' is connected to the application terminal of the output voltage Vout.

[0047] In addition, in the linear power supply 1 of the third embodiment, in accordance with the above changes, the non-inverting output amplifier 20 is replaced with an inverting output amplifier 20'. That is, the amplifier 20' generates a drive signal G0' of opposite polarity (inverted logic level) to the error signal S0. Therefore, the drive signal G0' becomes lower as the error signal S0 becomes higher, and becomes higher as the error signal S0 becomes lower.

[0048] 11 is a diagram showing the parasitic capacitance Cp in the linear power supply 1 of the third embodiment. As shown in this figure, when the output feedback circuit X is viewed as an equivalent circuit, the parasitic capacitance Cp described above is attached between the signal wiring L1 (= the application terminal of the error signal S0) and the application terminal of the output voltage Vout. In this respect, there is no difference from the second embodiment (FIG. 7) described above.

[0049] In this way, the configuration in which the output voltage Vout is applied to the shield wiring L2 can be applied regardless of the channel type of the output transistor.

[0050] <Linear Power Supply (Fourth Embodiment)> Fig. 12 is a diagram showing a fourth embodiment of a linear power supply. The linear power supply 1 of the fourth embodiment is based on the second embodiment (Fig. 7) and further includes a voltage clamp circuit 40.

[0051] The voltage clamp circuit 40 generates a clamp voltage Vout' that is in phase with the output voltage Vout and applies it to the shield wiring L2.

[0052] In this way, the connection destination of the shield wiring L2 is not necessarily limited to the application terminal of the output voltage Vout, but may be any potential node as long as it is in phase with the output voltage Vout and has low impedance.

[0053] In other words, it is sufficient that the AC behavior of the voltage applied to the shield wiring L2 is in phase with the output voltage Vout, and there is no problem even if the DC level is shifted.

[0054] <Linear Power Supply (Fifth Embodiment)> Fig. 13 is a diagram showing a fifth embodiment of a linear power supply. The linear power supply 1 of the fifth embodiment is based on the fourth embodiment (Fig. 12) described above, and includes a current source 41 and a transistor 42 (e.g., a PMOSFET) as components of a voltage clamp circuit 40.

[0055] The current source 41 is connected between the application terminal of the input voltage Vin and the source of the transistor 42, and generates a bias current Ib3.

[0056] The source of the transistor 42 is connected to the shield wiring L2 as the output terminal of the voltage clamp circuit 40 (=the application terminal of the clamp voltage Vout″). The drain of the transistor 42 is connected to the ground terminal. The gate of the transistor 42 is connected to the application terminal of the output voltage Vout.

[0057] In this case, the clamp voltage Vout" has a voltage value (=Vout+Vth

[42] ) that is higher than the output voltage Vout by the on-threshold voltage Vth

[42] of the transistor 42. In other words, the DC level of the clamp voltage Vout" deviates from the output voltage Vout. However, the AC behavior of the clamp voltage Vout" is in phase with the output voltage Vout. Therefore, the transient response characteristics can be improved while maintaining the shielding effect.

[0058] <Linear Power Supply (Sixth Embodiment)> Fig. 14 is a diagram showing a sixth embodiment of a linear power supply. The linear power supply 1 of the sixth embodiment is based on the fourth embodiment (Fig. 12) described above, and includes a current source 43 and a transistor 44 (e.g., an NMOSFET) as components of the voltage clamp circuit 40.

[0059] The current source 43 is connected between the source of the transistor 44 and the ground terminal, and generates a bias current Ib4.

[0060] The source of the transistor 44 is connected to the shield wiring L2 as the output terminal of the voltage clamp circuit 40 (=the application terminal of the clamp voltage Vout'''). The drain of the transistor 44 is connected to the application terminal of the input voltage Vin. The gate of the transistor 44 is connected to the application terminal of the output voltage Vout.

[0061] In this case, the clamp voltage Vout''' has a voltage value (=Vout-Vth

[44] ) that is lower than the output voltage Vout by the on-threshold voltage Vth

[44] of the transistor 44. That is, the DC level of the clamp voltage Vout''' deviates from the output voltage Vout. However, the AC behavior of the clamp voltage Vout''' is in phase with the output voltage Vout. Therefore, the transient response characteristics can be improved while maintaining the shielding effect.

[0062] Combination of Embodiments The second to sixth embodiments described above may be combined as appropriate as long as no contradictions are present. For example, although not shown, the third embodiment (FIG. 10) may be combined with any of the fourth to sixth embodiments (FIGS. 12 to 14) to introduce the voltage clamp circuit 40 while using the N-channel output transistor M0′.

[0063] <Summary> The various embodiments described above will be summarized below.

[0064] For example, the output feedback circuit disclosed in this specification is configured (first configuration) to include an error amplifier configured to generate an error signal in phase with the output voltage in accordance with the difference between the output voltage or a feedback voltage corresponding to the output voltage and a predetermined reference voltage; an amplifier configured to generate a drive signal for an output transistor by amplifying the error signal; a signal wiring configured to transmit the error signal from the output terminal of the error amplifier to the input terminal of the amplifier; and a shielding wiring laid adjacent to and running parallel to the signal wiring, configured to apply the output voltage or a voltage in phase therewith.

[0065] In the output feedback circuit according to the first configuration, the error amplifier may be configured (second configuration) to generate the error signal according to the difference between the output voltage or the feedback voltage input to the non-inverting input terminal and the reference voltage input to the inverting input terminal.

[0066] In the output feedback circuit according to the first or second configuration, the output transistor may be a P-channel type or a PNP type, and the amplifier may be a non-inverting output type (third configuration).

[0067] In the output feedback circuit according to the first or second configuration, the output transistor may be an N-channel type or an npn type, and the amplifier may be an inverting output type (fourth configuration).

[0068] Furthermore, the output feedback circuit according to any one of the first to fourth configurations may be configured (fifth configuration) to include a voltage clamp circuit configured to generate a clamp voltage in phase with the output voltage and apply it to the shield wiring.

[0069] Furthermore, in the output feedback circuit according to the fifth configuration, the voltage clamp circuit may be configured (sixth configuration) to include a transistor configured such that the gate is connected to the application terminal of the output voltage and the source is connected to the shield wiring.

[0070] Furthermore, in the output feedback circuit according to the sixth configuration, the transistor may be a P-channel type or a PNP type, and the clamp voltage may be higher than the output voltage by the on-threshold voltage of the transistor (seventh configuration).

[0071] Furthermore, in the output feedback circuit according to the sixth configuration, the transistor may be an N-channel type or an NPN type, and the clamp voltage may be lower than the output voltage by the on-threshold voltage of the transistor (eighth configuration).

[0072] Furthermore, the output feedback circuit according to any one of the first to eighth configurations may be configured (ninth configuration) to include a feedback voltage generation circuit configured to divide the output voltage to generate the feedback voltage.

[0073] Furthermore, for example, the linear power supply disclosed in this specification is configured (tenth configuration) to include the output transistor configured to be connected between the input voltage application terminal and the output voltage application terminal, and an output feedback circuit having any of the first to ninth configurations configured to drive the output transistor so that the output voltage or the feedback voltage coincides with the reference voltage.

[0074] <Other Modifications> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation.

[0075] For example, the PMOSFET and NMOSFET may be replaced with a pnp bipolar transistor and an npn bipolar transistor, respectively. In this case, the drain, source, and gate in the above description may be replaced with collector, emitter, and base.

[0076] That is, the above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is defined by the claims, and it can be understood that all modifications that fall within the meaning and scope of the claims are included.

[0077] REFERENCE SIGNS LIST 1 Linear power supply 2 Load 10 Error amplifier 11 Current source 12, 13 Transistor (PMOSFET) 14, 15 Transistor (NMOSFET) 20 Amplifier (non-inverting output type) 20' Amplifier (inverting output type) 21 Current source 22 Transistor (NMOSFET) 30 Feedback voltage generation circuit 31, 32 Resistor 40 Voltage clamp circuit 41 Current source 42 Transistor (PMOSFET) 43 Current source 44 Transistor (NMOSFET) Cp Parasitic capacitance L1 Signal wiring L2 Shield wiring M0 Output transistor (PMOSFET) M0' Output transistor (NMOSFET) OUT Output terminal X Output feedback circuit

Claims

1. an error amplifier configured to generate an error signal in phase with the output voltage in response to a difference between an output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage; an amplifier configured to amplify the error signal to generate a drive signal for an output transistor; a signal line configured to transmit the error signal from an output terminal of the error amplifier to an input terminal of the amplifier; a shield wiring that is laid adjacent to the signal wiring so as to run in parallel therewith and is configured so that the output voltage or a voltage having the same phase as the output voltage is applied thereto; An output feedback circuit comprising:

2. 2. The output feedback circuit according to claim 1, wherein the error amplifier generates the error signal according to a difference between the output voltage or the feedback voltage input to a non-inverting input terminal and the reference voltage input to an inverting input terminal.

3. 2. The output feedback circuit of claim 1, wherein the output transistor is a P-channel type or a pnp type, and the amplifier is a non-inverting output type.

4. 2. The output feedback circuit of claim 1, wherein the output transistor is an N-channel type or an npn type, and the amplifier is an inverting output type.

5. 2. The output feedback circuit of claim 1, further comprising a voltage clamp circuit configured to generate a clamp voltage in phase with the output voltage and apply the clamp voltage to the shield wiring.

6. 6. The output feedback circuit according to claim 5, wherein the voltage clamp circuit includes a transistor having a gate connected to an application terminal of the output voltage and a source connected to the shield wiring.

7. 7. The output feedback circuit according to claim 6, wherein the transistor is a P-channel type or a pnp type, and the clamp voltage is higher than the output voltage by an on-threshold voltage of the transistor.

8. 7. The output feedback circuit according to claim 6, wherein the transistor is an N-channel type or an npn type, and the clamp voltage is lower than the output voltage by an on-threshold voltage of the transistor.

9. The output feedback circuit of claim 1 , comprising a feedback voltage generating circuit configured to divide the output voltage to generate the feedback voltage.

10. The output transistor is configured to be connected between an application terminal of an input voltage and an application terminal of the output voltage; An output feedback circuit according to any one of claims 1 to 9, configured to drive the output transistor so that the output voltage or the feedback voltage coincides with the reference voltage; A linear power supply comprising: