Imaging element and imaging device

Abstract

An imaging element (1) comprises: a pixel array (40) in which a plurality of pixels (30) are arranged in rows and columns; a plurality of impedance conversion circuits (61) to which the pixel signals outputted from one or more pixels (30) are inputted for each column; and an A / D converter (64) that A / D converts a plurality of signals outputted from the plurality of impedance conversion circuits (61) for each column. The pixel array (40) includes, for each column, N pixel groups (100) each consisting of K or more pixels (30) that are consecutively arranged in the column direction. The N pixel groups (100) each have a vertical signal line (50) connected to L or more pixels (30) out of the K or more pixels (30). In each column, each of the N vertical signal lines (50) included in the N pixel groups (100) is connected to the input of any one of the plurality of impedance conversion circuits (61), while the output of each of the plurality of impedance conversion circuits (61) is connected to the A / D converter (64).

Description

Image sensor and image pickup device

[0001] The present disclosure relates to an imaging element and an imaging device that captures an image.

[0002] 2. Description of the Related Art Conventionally, an imaging element for capturing an image is known (see, for example, Japanese Patent Application Laid-Open No. 2003-144998).

[0003] JP 2015-53648 A

[0004] It is desirable to increase the readout speed of pixel signals from pixels in an image sensor. However, even if the readout speed is increased, it is undesirable for the quality of the captured image to be degraded.

[0005] Therefore, an object of the present disclosure is to provide an imaging element and the like that can increase the speed at which pixel signals are read out from pixels while suppressing degradation in the image quality of the captured image.

[0006] An imaging element according to one aspect of the present disclosure includes a pixel array in which a plurality of pixels are arranged in a matrix, the pixel array having a photoelectric conversion unit that converts received light into electric charges, a charge accumulation unit that accumulates the electric charges converted by the photoelectric conversion unit, and an amplification transistor that outputs a pixel signal corresponding to the amount of electric charge accumulated in the charge accumulation unit; a plurality of first impedance conversion circuits, each having an output impedance lower than an input impedance, for each column of the pixel array, to which a pixel signal output from at least one of the plurality of pixels is input; and a plurality of first impedance conversion circuits, each performing AD conversion on a plurality of first impedance conversion signals output from the plurality of first impedance conversion circuits, for each column of the pixel array. and a first AD converter comprising: a first vertical signal line connected to an input of the plurality of first impedance conversion circuits; and a second vertical signal line connected to an output of the plurality of first impedance conversion circuits, the pixel array including, for each column, N (N is an integer of 2 or more) pixel groups each including K or more pixels (K is an integer of 2 or more) of the plurality of pixels and arranged consecutively in the column direction, and each of the N pixel groups including L (L is an integer of 2 or more and K or less) first pixels of the K or more pixels, and each of the N first vertical signal lines connected to an input of the plurality of first impedance conversion circuits, the output of each of the plurality of first impedance conversion circuits being connected to the first AD converter.

[0007] An imaging device according to one aspect of the present disclosure includes the imaging element.

[0008] An imaging element according to one aspect of the present disclosure includes a pixel array in which pixels having a photoelectric conversion unit that converts received light into an electric charge are arranged in a matrix, a pixel group consisting of a plurality of the pixels in the pixel array, a vertical signal line connected to at least one of the plurality of pixels in the pixel group, an impedance conversion circuit connected to the vertical signal line and having an output impedance lower than an input impedance, and an AD converter connected to the impedance conversion circuit.

[0009] According to an image sensor or the like according to an aspect of the present disclosure, it is possible to increase the readout speed of pixel signals from pixels while suppressing degradation in the image quality of the captured image.

[0010] FIG. 1 is a perspective view showing the appearance of an image sensor according to the first embodiment. FIG. 2 is a plan view of a first semiconductor chip according to the first embodiment. FIG. 3 is a plan view of a pixel array according to the first embodiment. FIG. 4 is a circuit diagram showing a configuration of a pixel according to the first embodiment. FIG. 5 is a plan view of a second semiconductor chip according to the first embodiment. FIG. 6 is a plan view of a readout circuit according to the first embodiment. FIG. 7 is a circuit diagram showing an example of a configuration of a first impedance conversion circuit according to the first embodiment. FIG. 8 is a timing chart showing how a control unit according to the first embodiment operates current sources and the like to pass current to first vertical signal lines. FIG. 9 is a timing chart showing how a control unit according to the first embodiment operates current sources and the like to pass current to the first vertical signal lines. FIG. 10 is a timing chart showing how a control unit according to the first embodiment operates current sources and the like to pass current to the first vertical signal lines. FIG. 11 is a timing chart showing how a control unit according to the first embodiment operates current sources and the like to pass current to the first vertical signal lines. FIG. 12 is a plan view of a readout circuit according to Modification 1. FIG. 13 is a plan view of a readout circuit according to Modification 2. FIG. 14 is a plan view of a pixel array according to Modification 3. FIG. 15 is a circuit diagram showing a configuration of a pixel according to Modification 3. FIG. 16 is a plan view of a readout circuit according to Modification 3. FIG. 17 is a plan view of a readout circuit according to Modification 4. FIG. 18 is a plan view of a pixel array according to Embodiment 2. FIG. 19 is a plan view of a readout circuit according to Embodiment 2. FIG. 20 is a configuration diagram showing an example of the configuration of a readout circuit according to Embodiment 2. FIG. 21 is a plan view of a pixel array according to Modification 5. FIG. 22 is a plan view of a readout circuit according to Modification 5. FIG. 23 is a schematic diagram showing the configuration of an imaging device according to Embodiment 3. FIG. 24 is a plan view of a pixel array according to a supplementary modification. FIG. 25 is a plan view of a readout circuit according to a supplementary modification. FIG. 26 is a circuit diagram showing an example of the configuration of a first impedance conversion circuit according to a supplementary modification.

[0011] (Background to the Achievement of One Aspect of the Present Disclosure) Conventionally, as a technology for realizing an increase in the speed at which pixel signals are read out from pixels, a technology has been known in which a vertical signal line arranged for each column of a pixel array is divided into a plurality of vertical signal lines, and a plurality of AD (Analog to Digital) converters are connected to each of the divided vertical signal lines (hereinafter also referred to as "divided vertical signal lines"), and pixel signals are read out from pixels in each column using the divided vertical signal lines and the plurality of AD converters.

[0012] According to this technique, compared to a technique of reading out pixel signals from pixels in each column using one vertical signal line and one AD converter, the wiring capacitance of multiple divided vertical signal lines is reduced compared to the wiring capacitance of one vertical signal line, and the number of pixels connected as loads to multiple divided vertical signal lines is reduced compared to the number of pixels connected as loads to one vertical signal line, thereby making it possible to increase the speed at which pixel signals are read out from pixels.

[0013] In response to this, the inventors conducted experiments and studies using this technology and found that the use of this technology may result in a phenomenon in which the image captured by the imaging element is degraded.

[0014] That is, with this technology, pixels connected to different divided vertical signal lines are read by different AD converters, and the pixel signals read from each of the divided vertical lines reflect the characteristics of the AD converter connected to that divided vertical line. Therefore, if differences in characteristics occur among the AD converters due to manufacturing variations or the like, the differences in characteristics of the AD converters will be reflected in the pixel signals read from the pixels connected to the different divided vertical signal lines. This will degrade the image quality of the image captured by the image sensor.

[0015] Based on this finding, the inventors have further conducted repeated studies and experiments to suppress deterioration in the image quality of images captured by the imaging element, and have come up with the imaging element etc. according to the present disclosure described below.

[0016] An imaging element according to one aspect of the present disclosure includes a pixel array in which a plurality of pixels are arranged in a matrix, the pixel array having a photoelectric conversion unit that converts received light into electric charges, a charge accumulation unit that accumulates the electric charges converted by the photoelectric conversion unit, and an amplification transistor that outputs a pixel signal corresponding to the amount of electric charge accumulated in the charge accumulation unit; a plurality of first impedance conversion circuits, each having an output impedance lower than an input impedance, for each column of the pixel array, to which a pixel signal output from at least one of the plurality of pixels is input; and a plurality of first impedance conversion circuits, each performing AD conversion on a plurality of first impedance conversion signals output from the plurality of first impedance conversion circuits, for each column of the pixel array. and a first AD converter comprising: a first vertical signal line connected to an input of the plurality of first impedance conversion circuits; and a second vertical signal line connected to an output of the plurality of first impedance conversion circuits, the pixel array including, for each column, N (N is an integer of 2 or more) pixel groups each including K or more pixels (K is an integer of 2 or more) of the plurality of pixels and arranged consecutively in the column direction, and each of the N pixel groups including L (L is an integer of 2 or more and K or less) first pixels of the K or more pixels, and each of the N first vertical signal lines connected to an input of the plurality of first impedance conversion circuits, the output of each of the plurality of first impedance conversion circuits being connected to the first AD converter.

[0017] According to the image sensor having the above configuration, in each column, the plurality of first pixels are connected to any of the N first vertical signal lines divided into N. As a result, according to the image sensor having the above configuration, compared to a configuration in which the plurality of first pixels are connected to one vertical signal line in each column, the wiring capacitance of each first vertical signal line is reduced below the wiring capacitance of one vertical signal line, and the number of first pixels connected as loads to each first vertical signal line is reduced below the number of first pixels connected as loads to one vertical signal line, thereby making it possible to increase the speed at which pixel signals are read out from the first pixels.

[0018] Furthermore, in the image sensor having the above configuration, in each column, each of the N first vertical signal lines is connected to one AD converter via one of the plurality of first impedance conversion circuits. As a result, in the image sensor having the above configuration, compared to a configuration in which each of the N first vertical signal lines is connected to a respective one of the plurality of AD converters in each column, the pixel signals read from the first pixels connected to different first vertical signal lines are not affected by differences in characteristics that may occur in the plurality of AD converters. Therefore, in the image sensor having the above configuration, deterioration in the quality of images captured by the image sensor due to differences in characteristics that occur in the plurality of AD converters in each column is suppressed.

[0019] In this way, the imaging device having the above configuration can increase the speed at which pixel signals are read out from pixels while suppressing deterioration in the quality of the captured image.

[0020] Alternatively, L may be equal to K, and the K or more pixels may be the L or more first pixels.

[0021] This allows all of the pixels included in each of the N pixel groups to be the first pixels.

[0022] Further, K may be an integer equal to or greater than 4, and L may be an integer equal to or greater than 2 and equal to or less than K / 2; and the pixel array may further include, for each column, a plurality of second impedance conversion circuits having an output impedance lower than an input impedance, each of which receives a pixel signal output from at least one of the plurality of pixels as input, and a second AD converter for each column of the pixel array that performs AD conversion of the plurality of second impedance conversion signals output from the plurality of second impedance conversion circuits; each of the N pixel groups may further include second vertical signal lines connected to L or more second pixels among the K or more pixels, the L or more second pixels being different from the L or more first pixels; and for each column of the pixel array, each of the N second vertical signal lines included in the N pixel groups may be connected to an input of one of the plurality of second impedance conversion circuits, and an output of each of the plurality of second impedance conversion circuits may be connected to the second AD converter.

[0023] This allows pixel signals to be read out in parallel from first and second pixels that are included in the same pixel group, i.e., that are relatively close to each other, in each column. This makes it possible to relatively reduce a step in the subject in the captured image (rolling shutter distortion) that can occur when pixel signals are read out from pixels that are sequentially read out and scanned row by row when capturing an image of a moving subject, by reading pixel signals in parallel from two pixels that are relatively far apart in each column, and thus makes this step less noticeable.

[0024] Furthermore, for each column of the pixel array, at least one output of the plurality of first impedance conversion circuits may be connected to the first AD converter via a first common signal line, and at least one other output of the plurality of first impedance conversion circuits may be connected to the first AD converter via a second common signal line different from the first common signal line.

[0025] This makes it possible to reduce the load capacitance driven by the output of at least one of the plurality of first impedance conversion circuits and the load capacitance driven by the output of at least another of the plurality of first impedance conversion circuits, compared to a configuration in which all of the outputs of the plurality of first impedance conversion circuits are connected to the first AD converter via a single common signal line, thereby further increasing the speed at which pixel signals are read out from the pixels.

[0026] Furthermore, for each column of the pixel array, at least one input of the plurality of first impedance conversion circuits may be alternatively connected to two of the first vertical signal lines provided in two pixel groups adjacent to each other in the column direction among the N pixel groups.

[0027] This allows two first vertical signal lines provided in two pixel groups adjacent to each other in the column direction in each column to share one first impedance conversion circuit.

[0028] Furthermore, each of the plurality of first impedance conversion circuits may have an output transistor that outputs each of the plurality of first impedance conversion signals, and each of the output transistors may have a driving capability higher than that of the amplifier transistor.

[0029] This makes it possible to further increase the speed at which pixel signals are read out from the first pixels via the first impedance conversion circuit in each column.

[0030] Furthermore, the imaging device may further include a plurality of current sources for each column of the pixel array that pass current through each of the N first vertical signal lines, and a reference current source that uniformly defines the currents that flow through at least two current sources out of all of the plurality of current sources that the imaging device has.

[0031] This makes it possible to uniformly define the currents flowing through all current sources provided in the pixel array.

[0032] Further, N is an integer equal to or greater than 4, and the image sensor is configured by stacking a first semiconductor chip on which the pixel array is formed and a second semiconductor chip on which the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed, and in a plan view of the pixel array, the N first vertical signal lines provided in the N pixel groups for each column of the pixel array extend in the column direction of the pixel array and are lined up in the column direction of the pixel array, and one first impedance conversion circuit of the plurality of first impedance conversion circuits is The conversion circuit may be located between a third vertical signal line and a fourth vertical signal line that are adjacent to each other among the N first vertical signal lines in the column direction of the pixel array, and another first impedance conversion circuit of the plurality of first impedance conversion circuits may be located between a fifth vertical signal line and a sixth vertical signal line that are adjacent to each other among the N first vertical signal lines, the fifth vertical signal line and the sixth vertical signal line being different from both the third vertical signal line and the fourth vertical signal line, in the column direction of the pixel array.

[0033] This makes it possible to make relatively short the distance from the third and fourth vertical signal lines to one of the plurality of first impedance conversion circuits in each column, and the distance from the fifth and sixth vertical signal lines to another of the plurality of first impedance conversion circuits.

[0034] Furthermore, the imaging element may be configured by stacking a first semiconductor chip on which the pixel array is formed and a second semiconductor chip on which the plurality of first impedance conversion circuits and the first AD converter, which are provided for each column of the pixel array, are formed, and in a planar view of the pixel array, the N first vertical signal lines provided for the N pixel groups in each column of the pixel array extend in the column direction of the pixel array and are aligned in the column direction of the pixel array, and the range of existence of one or more wirings for connecting outputs of the plurality of first impedance conversion circuits and the first AD converter in the column direction of the pixel array may be within the range of existence of the N first vertical signal lines in the column direction of the pixel array.

[0035] This prevents one or more wires for connecting the outputs of the plurality of first impedance conversion circuits to the first AD converter in each column from becoming longer than necessary.

[0036] Furthermore, the imaging element may be configured by stacking a first semiconductor chip on which the pixel array is formed and a second semiconductor chip on which the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed, and in a planar view of the pixel array, the N first vertical signal lines provided for the N pixel groups in each column of the pixel array extend in the column direction of the pixel array and are aligned in the column direction of the pixel array, and the total wiring length of one or more wires for connecting the outputs of the plurality of first impedance conversion circuits and the first AD converter may be smaller than the total wiring length of the N first vertical signal lines.

[0037] This prevents one or more wires for connecting the outputs of the plurality of first impedance conversion circuits to the first AD converter in each column from becoming longer than necessary.

[0038] The pixel array may further include a plurality of current sources for each column that supply current to each of the N first vertical signal lines, and the imaging element may further include a control unit that controls all of the plurality of current sources of the pixel array, and the control unit may be configured to activate, for each column of the pixel array, a current source that supplies current to the first vertical signal line of a readout execution pixel group that is a pixel group consisting of the K or more pixels that output pixel signals, and to inactivate other current sources.

[0039] This allows current sources in each column other than the current source that supplies current to the first vertical signal line of the readout execution pixel group to be inactive, thereby reducing power consumption of the image sensor compared to when current is supplied to all of the first vertical signal lines.

[0040] The pixel array may further include a plurality of current sources for each column that pass current to each of the N first vertical signal lines, and the imaging element may further include a control unit that controls all of the plurality of current sources of the pixel array, and the control unit may set, for each column of the pixel array, a current source among the plurality of current sources that passes current to the first vertical signal line of a readout execution pixel group, which is a pixel group consisting of the K or more pixels that output pixel signals, to a first active state, and set the other current sources to a second active state in which the amount of current passed is smaller than that of the first active state.

[0041] This allows current sources in each column other than the current source that supplies current to the first vertical signal line of the readout execution pixel group to be set to the second active state, which supplies a smaller amount of current than in the first active state, thereby reducing power consumption of the image sensor compared to when a current of the amount corresponding to the first active state is supplied to all of the first vertical signal lines.

[0042] The pixel array further includes a plurality of current sources for each column that pass a current to each of the N first vertical signal lines, and the image sensor further includes a control unit that controls all of the plurality of current sources included in the pixel array, and the control unit activates, among the plurality of current sources, for each column of the pixel array, (1) a current source that passes a current to the first vertical signal line included in a readout execution pixel group that is a pixel group consisting of the K or more pixels that output pixel signals, and (2) a current source that passes a current to the first vertical signal line included in the K or more pixels of the readout execution pixel group. A current source that supplies a current to the first vertical signal line of a pre-readout pixel group, which is a pixel group consisting of the K or more pixels that will next output pixel signals, may be set to the active state before the K or more pixels of the pre-readout pixel group start outputting pixel signals, and (3) current sources other than the current source that supplies a current to the first vertical signal line of the readout pixel group and the current source that supplies a current to the first vertical signal line of the pre-readout pixel group may be set to the inactive state.

[0043] Generally, when a pixel signal is read from a pixel using a vertical signal line through which a current source passes immediately after the current source is changed from an inactive state to an active state, the pixel signal may not be read out accurately.

[0044] In contrast, in the image sensor having the above configuration, the current source that supplies current to the first vertical signal line of the pre-readout pixel group in each column is changed from an inactive state to an active state before the pixels in the pre-readout pixel group start outputting pixel signals. Therefore, with the image sensor having the above configuration, it is possible to prevent pixel signals from being read out with high accuracy when they are read out from the pixels.

[0045] Furthermore, the pixel array may further include, for each column, a plurality of current sources that pass current to power supply wiring connected to the K or more pixels included in each of the N pixel groups, and the imaging element may further include a control unit that controls all of the plurality of current sources of the pixel array, and the control unit may be configured to activate, among the plurality of current sources, a current source that passes current to the power supply wiring connected to the K or more pixels included in a pre-readout pixel group, which is a pixel group consisting of the K or more pixels that will output pixel signals after the K or more pixels included in a readout execution pixel group, which is a pixel group consisting of the K or more pixels that output pixel signals, before the K or more pixels included in the pre-readout pixel group start to output pixel signals, and to inactive current sources other than the current source that passes current to the power supply wiring connected to the K or more pixels included in the pre-readout pixel group.

[0046] Generally, there is a voltage difference between the power supply voltage supplied to a pixel when no current is flowing through the power supply wiring connected to that pixel and the power supply voltage supplied to that pixel when current is flowing through the power supply wiring connected to that pixel, the voltage difference being the voltage caused by IR drop that occurs depending on the amount of current flowing. Also, there is a difference in the pixel signal read out when no IR drop is occurring and when an IR drop is occurring.

[0047] In contrast, with an image sensor having the above configuration, in each column, current begins to flow through the power supply wiring connected to the pixels included in the pre-readout pixel group before the pixels included in the pre-readout pixel group start outputting pixel signals. Therefore, with an image sensor having the above configuration, IR drop has already occurred by the time the pixels included in the pre-readout pixel group start outputting pixel signals. Therefore, with an image sensor having the above configuration, when reading out pixel signals from pixels, it is possible to prevent the pixel signals from being unable to be read out accurately due to the presence or absence of the IR drop.

[0048] Furthermore, the pixel array may further include a plurality of current sources for each column that supply current to each of the N first vertical signal lines, and the image sensor may further include a control unit that controls all of the plurality of current sources of the pixel array, and the control unit may, for each column of the pixel array, (1) activate a current source that supplies current to the first vertical signal line of a readout pixel group that is a pixel group consisting of the K or more pixels that output pixel signals, (2) continue to maintain in the active state a current source that supplies current to the first vertical signal line of a post-readout pixel group that is a pixel group consisting of the K or more pixels that output pixel signals immediately before the K or more pixels of the readout pixel group, for a certain period of time even after the K or more pixels included in the post-readout pixel group have finished outputting pixel signals, and (3) inactivate current sources other than the current source that supplies current to the first vertical signal line of the readout pixel group and the current source that supplies current to the first vertical signal line of the post-readout pixel group.

[0049] Generally, when a current source that supplies current to a vertical signal line of a certain column is changed from an active state to an inactive state, this can have an adverse effect on the currents that are supplied to the vertical signal lines of other columns adjacent to the column, which can make it difficult to accurately read out pixel signals from pixels connected to the vertical signal lines of the other columns.

[0050] In contrast, with the image sensor having the above configuration, even if, for a certain period after completion of readout of pixel signals from pixels included in a readout execution pixel group in a certain column, there are pixels in another column adjacent to that column from which pixel signals are continuously read, the current source that supplies current to the first vertical signal line of that readout execution pixel group continues to maintain an active state during that certain period. Therefore, with the image sensor having the above configuration, even if, for a certain period after completion of readout of pixel signals from pixels included in a readout execution pixel group in a certain column, there are pixels in another column adjacent to that column from which pixel signals are continuously read, it is possible to prevent the image sensor from being unable to accurately read out pixel signals from those pixels.

[0051] Furthermore, the pixel array may further include, for each column, a plurality of current sources that pass current to power supply wiring connected to the K or more pixels included in each of the N pixel groups, and the image sensor may further include a control unit that controls all of the plurality of current sources of the pixel array, and the control unit may be configured to, for each column of the pixel array, continue to activate, for a certain period of time after the K or more pixels included in the post-readout pixel group have finished outputting their pixel signals, a current source that passes current to the power supply wiring connected to the K or more pixels included in the post-readout pixel group, the current source being a pixel group consisting of the K or more pixels that output pixel signals immediately before the K or more pixels included in the readout execution pixel group, the pixel group being consisting of the K or more pixels that output pixel signals, and to inactivate other current sources other than the current source that passes current to the power supply wiring connected to the K or more pixels included in the post-readout pixel group.

[0052] Generally, there is a voltage difference between the power supply voltage supplied to a pixel when no current is flowing through the power supply wiring connected to that pixel and the power supply voltage supplied to that pixel when current is flowing through the power supply wiring connected to that pixel, the voltage difference being the voltage caused by IR drop that occurs depending on the amount of current flowing. Also, there is a difference in the pixel signal read out when no IR drop is occurring and when an IR drop is occurring.

[0053] Furthermore, when a pixel in a certain column changes from a current-flowing state to a current-nonflowing state, the voltage of the power supply wiring connected to the pixels in other columns adjacent to that column may change, and this voltage change may prevent accurate reading of pixel signals from the pixels in those other columns.

[0054] In contrast, with the image sensor having the above configuration, even if, for a certain period after completion of readout of pixel signals from pixels included in a readout execution pixel group in a certain column, there are pixels in another column adjacent to that column from which pixel signals are continuously read, a state in which a current continues to flow is maintained in the power supply wiring connected to the pixels included in the readout execution pixel group in that certain column. Therefore, with the image sensor having the above configuration, even if, for a certain period after completion of readout of pixel signals from pixels included in a readout execution pixel group in a certain column, there are pixels in another column adjacent to that column from which pixel signals are continuously read, it is possible to prevent the image sensor from being unable to read pixel signals from those pixels with high accuracy.

[0055] Furthermore, N may be an even number greater than or equal to four, and for each column of the pixel array, the N pixel groups may include at least a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group, and for each column of the pixel array, a first switch may be provided that switches the first vertical signal line of the first pixel group and the first vertical signal line of the second pixel group between a conductive state and a non-conductive state, and a second switch may be provided that switches the first vertical signal line of the third pixel group and the first vertical signal line of the fourth pixel group between a conductive state and a non-conductive state.

[0056] This makes it possible to mix and read out pixel signals from the first pixel included in the first pixel group and the first pixel included in the second pixel group in each column, and to mix and read out pixel signals from the first pixel included in the third pixel group and the first pixel included in the fourth pixel group.

[0057] Furthermore, K is an integer of 8 or more, and L is an integer of 2 or more and K / 4 or less, and each of the N pixel groups further includes: a third vertical signal line connected to L or more third pixels among the K or more pixels, the L or more third pixels being different from the L or more first pixels and the L or more second pixels; and a fourth vertical signal line connected to L or more fourth pixels among the K or more pixels, the L or more fourth pixels being different from the L or more first pixels, the L or more second pixels, and the L or more third pixels; The image sensor further includes, for each column of the pixel array, a plurality of third impedance conversion circuits having an output impedance lower than an input impedance, each of which receives a pixel signal output from at least one of the plurality of pixels; a plurality of fourth impedance conversion circuits having an output impedance lower than an input impedance, each of which receives a pixel signal output from at least one of the plurality of pixels; a third AD converter that performs AD conversion on the plurality of third impedance conversion signals output from the plurality of third impedance conversion circuits; and a fourth AD converter that performs AD conversion on the plurality of fourth impedance conversion signals output from the plurality of fourth impedance conversion circuits; and a first switch that switches the first vertical signal line and the third vertical signal line between a conductive state and a non-conductive state, for each column of the pixel array and for each of the N pixel groups. and a switch, wherein, for each column of the pixel array, each of the N third vertical signal lines provided in the N pixel groups is connected to an input of one of the plurality of third impedance conversion circuits, and an output of each of the plurality of third impedance conversion circuits is connected to the third AD converter, each of the N fourth vertical signal lines provided in the N pixel groups is connected to an input of one of the plurality of fourth impedance conversion circuits, and an output of each of the plurality of fourth impedance conversion circuits is connected to the fourth AD converter;The photoelectric conversion units of the L or more first pixels and the photoelectric conversion units of the L or more third pixels may receive light of a first color that has passed through a first color filter, and the photoelectric conversion units of the L or more second pixels and the photoelectric conversion units of the L or more fourth pixels may receive light of a second color that has passed through a second color filter and is different from the first color.

[0058] This allows, in each column and each pixel group, pixel signals to be mixed and read out from the first pixel and the third pixel that receive light of the first color, and pixel signals to be mixed and read out from the second pixel and the fourth pixel that receive light of the second color.

[0059] An imaging device according to one aspect of the present disclosure includes the imaging element.

[0060] As described above, the imaging element included in the imaging device having the above configuration can increase the speed at which pixel signals are read out from pixels while suppressing deterioration in the quality of the captured image.

[0061] Therefore, with the imaging device having the above configuration, it is possible to increase the speed at which pixel signals are read out from pixels while suppressing deterioration in the quality of the captured image.

[0062] An imaging element according to one aspect of the present disclosure includes a pixel array in which pixels having a photoelectric conversion unit that converts received light into an electric charge are arranged in a matrix, a pixel group consisting of a plurality of the pixels in the pixel array, a vertical signal line connected to at least one of the plurality of pixels in the pixel group, an impedance conversion circuit connected to the vertical signal line and having an output impedance lower than an input impedance, and an AD converter connected to the impedance conversion circuit.

[0063] According to the imaging element having the above configuration, it is possible to increase the speed at which pixel signals are read out from pixels while suppressing deterioration in the quality of the captured image.

[0064] Specific examples of an imaging element and the like according to one aspect of the present disclosure will be described below with reference to the drawings. Each embodiment shown here illustrates one specific example of the present disclosure. Therefore, the numerical values, shapes, components, the arrangement and connection of the components, steps (processes), and the order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

[0065] First Embodiment An imaging element for capturing an image will be described below.

[0066] [Configuration] FIG. 1 is a perspective view showing the appearance of an imaging device 1 according to the first embodiment.

[0067] As shown in FIG. 1, the image sensor 1 is configured by stacking a first semiconductor chip 11 and a second semiconductor chip 12 on top of each other.

[0068] FIG. 2 is a plan view of the first semiconductor chip 11. As shown in FIG.

[0069] 2, components formed on the first semiconductor chip 11 are indicated by solid lines, and further, some of the components formed on the second semiconductor chip 12 are indicated by dashed lines. That is, only the components indicated by solid lines in FIG. 2 are formed on the first semiconductor chip 11.

[0070] Here, the positions of the components formed on the second semiconductor chip 12 shown by dashed lines in Figure 2 are the positions at which these components are projected onto the first semiconductor chip 11 in a direction perpendicular to the back surface of the imaging element 1 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other.

[0071] As shown in FIG. 2, the first semiconductor chip 11 has a pixel array 40 formed thereon, in which a plurality of pixels 30 are arranged in a matrix.

[0072] FIG. 3 is a plan view of the pixel array 40. As shown in FIG.

[0073] As shown in FIG. 3 , the pixel array 40 includes, for each column, N (N is an integer of 3 or greater) pixel groups 100 (corresponding to the first pixel group 100A, the second pixel group 100B, the third pixel group 100C, and the fourth pixel group 100D in FIG. 3 ), each of which is composed of K or more (K is an integer of 2 or greater) pixels 30 arranged consecutively in the column direction. Here, as an example, as shown in FIG. 3 , a case will be described in which N is 4, i.e., the N pixel groups 100 are the first pixel group 100A, the second pixel group 100B, the third pixel group 100C, and the fourth pixel group 100D. However, N does not necessarily have to be limited to 4 as long as it is an integer of 3 or greater. Here, the pixel groups 100 will be described as each consisting of K pixels 30. However, it is not necessarily required that all pixel groups 100 be composed of K pixels 30. For example, the first pixel group 100A may consist of K pixels 30, the second pixel group 100B may consist of K+1 pixels 30, the third pixel group 100C may consist of K pixels 30, and the fourth pixel group 100D may consist of K+2 pixels 30.

[0074] As shown in FIG. 3 , each of the N pixel groups 100 includes a first vertical signal line 50 (corresponding to the first vertical signal line 50A, the first vertical signal line 50B, the first vertical signal line 50C, and the first vertical signal line 50D in FIG. 3 ) connected to K pixels 30.

[0075] In each column of the pixel array 40, the N first vertical signal lines 50 extend in the column direction of the pixel array 40 in a plan view of the image sensor 1 and are aligned in the column direction of the pixel array 40.

[0076] In each column of the pixel array 40, the first vertical signal line 50A has a node 2AA connected to a node (here, a node 2AB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 50A has the node 2AA at an end on the first vertical signal line 50B side.

[0077] In each column of the pixel array 40, the first vertical signal line 50B has a node 2BA connected to a node (here, a node 2BB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 50B has the node 2BA at the end on the first vertical signal line 50A side.

[0078] In each column of the pixel array 40, the first vertical signal line 50C has a node 2CA connected to a node (here, a node 2CB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 50C has the node 2CA at the end on the first vertical signal line 50D side.

[0079] In each column of the pixel array 40, the first vertical signal line 50D has a node 2DA connected to a node (here, a node 2DB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 50D has the node 2DA at the end on the first vertical signal line 50C side.

[0080] FIG. 4 is a circuit diagram showing the configuration of the pixel 30.

[0081] As shown in FIG. 4 , the pixel 30 includes a photoelectric conversion unit 31 , a charge storage unit 32 , a transfer transistor 33 , a reset transistor 34 , an amplification transistor 35 , a selection transistor 36 , and a power supply line 37 .

[0082] The pixel 30 is, for example, a back-illuminated pixel.

[0083] The photoelectric conversion unit 31 converts received light into electric charges. The photoelectric conversion unit 31 is realized by, for example, a photodiode.

[0084] The charge storage section 32 stores the charges converted by the photoelectric conversion section 31 .

[0085] The transfer transistor 33 transfers the charges converted by the photoelectric conversion unit 31 to the charge accumulation unit 32. The transfer transistor 33 is realized by, for example, a MOS transistor.

[0086] The reset transistor 34 resets the charge stored in the charge storage unit 32. The reset transistor 34 is realized by, for example, a MOS transistor.

[0087] The amplifier transistor 35 outputs a pixel signal according to the amount of charge stored in the charge storage unit 32. The amplifier transistor 35 is realized by, for example, a MOS transistor.

[0088] The selection transistor 36 selects the pixel 30 that outputs a pixel signal to the first vertical signal line 50. The selection transistor 36 is realized by, for example, a MOS transistor.

[0089] The power supply wiring 37 is connected to the drain of the reset transistor 34 and the drain of the amplifier transistor 35 .

[0090] In addition, as long as the power supply wiring 37 is connected to the drain of the amplification transistor 35, it does not necessarily have to be connected to the drain of the reset transistor 34; in this case, the drain of the reset transistor 34 will be connected to another power supply wiring.

[0091] FIG. 5 is a plan view of the second semiconductor chip 12. As shown in FIG.

[0092] 5, the components formed on the second semiconductor chip 12 are indicated by solid lines, and further, the formation region of the pixel array 40 on the first semiconductor chip 11 is indicated by dashed lines. That is, only the components indicated by solid lines in FIG. 5 are formed on the second semiconductor chip 12.

[0093] Here, the position of the formation area of ​​the pixel array 40 indicated by the dashed line in Figure 5 is the position where the pixel array 40 is projected onto the second semiconductor chip 12 in a direction perpendicular to the surface of the imaging element 1 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other.

[0094] As shown in FIG. 5, the second semiconductor chip 12 is formed with a readout circuit 60, a control unit 70, a vertical scanning circuit 80, a reference current source 90, and a signal processing circuit 200.

[0095] As shown in FIG. 5, the pixel array 40 and the readout circuit 60 overlap each other in a plan view of the image sensor 1 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other.

[0096] Here, the pixel array 40 and the readout circuit 60 are described as overlapping each other when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other in a planar view of the image sensor 1, but they are not necessarily limited to an overlapping configuration.

[0097] FIG. 6 is a plan view of the readout circuit 60. As shown in FIG.

[0098] As shown in FIG. 6 , the readout circuit 60 includes, for each column of the pixel array 40, N first impedance conversion circuits 61 (corresponding to the first impedance conversion circuit 61A, the first impedance conversion circuit 61B, the first impedance conversion circuit 61C, and the first impedance conversion circuit 61D in FIG. 6 ), N current sources 62 (corresponding to the current source 62A, the current source 62B, the current source 62C, and the current source 62D in FIG. 6 ), a common signal line 63, and a first AD converter 64.

[0099] Furthermore, the readout circuit 60 has a node 2AB, a node 2BB, a node 2CB, and a node 2DB for each column of the pixel array 40.

[0100] The first impedance conversion circuit 61 is an impedance conversion circuit whose output impedance is lower than its input impedance, and receives as input a pixel signal output from at least one of the multiple pixels 30 included in the corresponding column of the pixel array 40.

[0101] Here, as a non-limiting example, the first impedance conversion circuit 61 will be described as a buffer.

[0102] FIG. 7 is a circuit diagram showing an example of the configuration of the first impedance conversion circuit 61. As shown in FIG.

[0103] As shown in FIG. 7, the first impedance conversion circuit 61 includes an output transistor 641 and a switch 642 .

[0104] The first impedance conversion circuit 61 may be configured as a circuit having an amplification function.

[0105] The output transistor 641 is a MOS transistor having a gate connected to the input and a drain connected to the output via a switch 642. The output transistor 641 has a higher driving capability than the amplifier transistor 35.

[0106] The first impedance conversion circuit 61 has a function of setting the output to a high impedance state. That is, the first impedance conversion circuit 61 can set the output to a high impedance state by setting the switch 642 to a non-conductive state.

[0107] Here, making the output high impedance means that when the output of one first impedance conversion circuit 61 and the output of the other first impedance conversion circuit 61 are short-circuited, the impedance of the output of one first impedance conversion circuit 61 is made higher than the output of the other first impedance conversion circuit 61 that is not performing the function of making the output high impedance.

[0108] When the first impedance conversion circuit 61 has the above configuration, a current source for driving the first impedance conversion circuit 61 is connected to the common signal line 63 .

[0109] Returning to FIG. 6, the description of the read circuit 60 will continue.

[0110] As shown in FIGS. 6 and 3 , the input of the first impedance conversion circuit 61A is connected to the first vertical signal line 50A in the corresponding column of the pixel array 40 via nodes 2AB and 2AA, the input of the first impedance conversion circuit 61B is connected to the first vertical signal line 50B in the corresponding column of the pixel array 40 via nodes 2BB and 2BA, the input of the first impedance conversion circuit 61C is connected to the first vertical signal line 50C in the corresponding column of the pixel array 40 via nodes 2CB and 2CA, and the input of the first impedance conversion circuit 61D is connected to the first vertical signal line 50D in the corresponding column of the pixel array 40 via nodes 2DB and 2DA.

[0111] The outputs of the N first impedance conversion circuits 61 are connected to a first AD converter 64 via a common signal line 63 .

[0112] Here, in each column of the pixel array 40, the first impedance conversion circuit 61A and the first impedance conversion circuit 61B are located between the first vertical signal line 50A and the first vertical signal line 50B in the column direction of the pixel array 40 in a planar view of the pixel array 40 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other in a planar view of the image sensor 1.

[0113] As a result, in each column of the pixel array 40, the distance from the first vertical signal line 50A to the first impedance conversion circuit 61A and the distance from the first vertical signal line 50B to the first impedance conversion circuit 61B are relatively short.

[0114] Note that, here, the first impedance conversion circuit 61A and the first impedance conversion circuit 61B are described as being located between the first vertical signal line 50A and the first vertical signal line 50B in the column direction of the pixel array 40 in a planar view of the pixel array 40 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other in a planar view of the image sensor 1; however, they are not necessarily limited to being located between the first vertical signal line 50A and the first vertical signal line 50B in the column direction of the pixel array 40.

[0115] In addition, in each column of the pixel array 40, the first impedance conversion circuit 61C and the first impedance conversion circuit 61D are located between the first vertical signal line 50C and the first vertical signal line 50D in the column direction of the pixel array 40 in a planar view of the pixel array 40 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other in a planar view of the image sensor 1.

[0116] As a result, in each column of the pixel array 40, the distance from the first vertical signal line 50C to the first impedance conversion circuit 61C and the distance from the first vertical signal line 50D to the first impedance conversion circuit 61D are relatively short.

[0117] Note that, here, the first impedance conversion circuit 61C and the first impedance conversion circuit 61D are described as being located between the first vertical signal line 50C and the first vertical signal line 50D in the column direction of the pixel array 40 in a planar view of the pixel array 40 when the first semiconductor chip 11 and the second semiconductor chip 12 are stacked on top of each other in a planar view of the image sensor 1; however, they are not necessarily limited to being located between the first vertical signal line 50C and the first vertical signal line 50D in the column direction of the pixel array 40.

[0118] Furthermore, in each column of the pixel array 40, the common signal line 63 extends in the column direction of the pixel array 40 in a plan view of the image sensor 1. In a plan view of the image sensor 1, the extent of the common signal line 63 in the column direction of the pixel array 40 falls within the extent of the N first vertical signal lines 50 in the column direction of the pixel array 40, and the wiring length of the common signal line 63 is shorter than the sum of the wiring lengths of the N first vertical signal lines 50.

[0119] This prevents the common signal line 63 from becoming longer than necessary in each column of the pixel array 40 .

[0120] The first AD converter 64 AD-converts each of the first impedance conversion signals output from the N first impedance conversion circuits 61 .

[0121] Here, in each column of the pixel array 40, the first AD converter 64 is located between the first impedance conversion circuit 61A and the first impedance conversion circuit 61B and the first impedance conversion circuit 61C and the first impedance conversion circuit 61D in a planar view of the pixel array 40.

[0122] As a result, in each column of the pixel array 40, the distance from the first impedance conversion circuit 61A and the first impedance conversion circuit 61B to the first AD converter 64, and the distance from the first impedance conversion circuit 61C and the first impedance conversion circuit 61D to the first AD converter 64 are relatively short.

[0123] Note that, here, the first AD converter 64 is described as being located between the first impedance conversion circuit 61A and the first impedance conversion circuit 61B and the first impedance conversion circuit 61C and the first impedance conversion circuit 61D in a planar view of the pixel array 40, but it is not necessarily limited to a configuration in which it is located between the first impedance conversion circuit 61A and the first impedance conversion circuit 61B and the first impedance conversion circuit 61C and the first impedance conversion circuit 61D.

[0124] The current source 62 forms a current mirror circuit together with a reference current source 90 (described later), and causes a current determined by the current flowing through the reference current source 90 to flow.

[0125] As shown in FIG. 6 , the current source 62A is connected to the first vertical signal line 50A (see FIG. 3 ) in the corresponding column of the pixel array 40 via nodes 2AA and 2AB, the current source 62B is connected to the first vertical signal line 50B (see FIG. 3 ) in the corresponding column of the pixel array 40 via nodes 2BA and 2BB, the current source 62C is connected to the first vertical signal line 50C (see FIG. 3 ) in the corresponding column of the pixel array 40 via nodes 2CA and 2CB, and the current source 62D is connected to the first vertical signal line 50D (see FIG. 3 ) in the corresponding column of the pixel array 40 via nodes 2DA and 2DB.

[0126] Returning to FIG. 5, the description of the second semiconductor chip 12 will continue.

[0127] The vertical scanning circuit 80 outputs, for each row of the pixel array 40, a vertical scanning signal that controls the pixels 30 located in that row.

[0128] The reference current source 90 is a current source that forms a current mirror circuit with each of the multiple current sources 62 included in the readout circuit 60 , and uniformly defines the currents that flow through all of the current sources 62 included in the readout circuit 60 .

[0129] Note that, here, the reference current source 90 is described as a current source that forms a current mirror circuit with each of the multiple current sources 62 included in the readout circuit 60, but the reference current source 90 is not necessarily limited to a configuration in which it is a current source that forms a current mirror circuit with each of the multiple current sources 62 included in the readout circuit 60, as long as it is a current source that forms a current mirror circuit with each of at least two of the multiple current sources 62 included in the readout circuit 60. In this case, the reference power supply 90 uniformly defines the currents that flow through these at least two current sources 62.

[0130] The signal processing circuit 200 generates an image based on a plurality of AD converted signals output from a plurality of first AD converters 64 included in the readout circuit 60 .

[0131] The control unit 70 controls the readout circuit 60 , the vertical scanning circuit 80 , the reference current source 90 , and the signal processing circuit 200 .

[0132] FIG. 8 is a timing chart showing how the control unit 70 controls the corresponding current source 62, etc. for each column of the pixel array 40 to pass a current through the first vertical signal line 50 in order to read out a pixel signal from each pixel 30 in the pixel array 40.

[0133] 8, the vertical axis of the top timing chart represents the current flowing through the first vertical signal line 50A, and the horizontal axis represents time. The vertical axis of the second timing chart represents the current flowing through the first vertical signal line 50B, and the horizontal axis represents time. The vertical axis of the third timing chart represents the current flowing through the first vertical signal line 50C, and the horizontal axis represents time. The vertical axis of the fourth timing chart represents the current flowing through the first vertical signal line 50D, and the horizontal axis represents time.

[0134] As shown in FIG. 8 , for each column of the pixel array 40, the control unit 70 activates the current source 62 that passes current to the first vertical signal line 50 of the readout execution pixel group, which is a pixel group 100 consisting of pixels 30 that output pixel signals, i.e., passes current, thereby passing a first amount of current to the first vertical signal line 50 of the readout execution pixel group, and deactivates the other current sources 62, i.e., does not pass current, thereby not passing current to the first vertical signal line 50 of the pixel groups 100 other than the readout execution pixel group.

[0135] By the control unit 70 controlling the current source 62 as described above, the power consumption of the image sensor 1 is reduced compared to when the first amount of current flows through all of the first vertical signal lines 50 .

[0136] <Discussion> With the image sensor 1 having the above configuration, in each column of the pixel array 40, the plurality of pixels 30 in that column are connected to any of the N divided first vertical signal lines 50. As a result, with the image sensor 1 having the above configuration, compared to a configuration in which the plurality of pixels 30 in each column of the pixel array 40 are connected to a single vertical signal line, the wiring capacitance of each first vertical signal line 50 is reduced below the wiring capacitance of a single vertical signal line, and the number of pixels 30 connected as loads to each first vertical signal line 50 is reduced below the number of pixels connected as loads to a single vertical signal line, thereby making it possible to increase the speed at which pixel signals are read out from the pixels 30.

[0137] Furthermore, with the image sensor 1 having the above configuration, in each column of the pixel array 40, each of the N first vertical signal lines 50 is connected to one first AD converter 64 via one of the plurality of first impedance conversion circuits 61. As a result, with the image sensor 1 having the above configuration, compared to a configuration in which each of the N first vertical signal lines 50 is connected to a respective one of a plurality of AD converters in each column of the pixel array 40, characteristic differences that may occur in the plurality of AD converters are not reflected in the pixel signals read from the pixels 30 connected to different first vertical signal lines 50. Therefore, with the image sensor 1 having the above configuration, deterioration in the quality of images captured by the image sensor due to characteristic differences occurring in the plurality of AD converters in each column of the pixel array 40 is suppressed.

[0138] In this way, the imaging device 1 having the above configuration can increase the speed at which pixel signals are read out from the pixels 30 while suppressing deterioration in the quality of the captured image.

[0139] In the first embodiment, the control unit 70 has been described as controlling the current source 62, etc., as shown in Fig. 8. However, the control unit 70 may control the current source 62, etc., as shown in Fig. 9, which will be described later, or may control the current source 62, etc., as shown in Fig. 10, which will be described later, or may control the current source 62, etc., as shown in Fig. 11, which will be described later.

[0140] FIG. 9 is a timing chart showing how the control unit 70 controls the corresponding current source 62, etc. for each column of the pixel array 40 to pass a current through the first vertical signal line 50 in order to read out a pixel signal from each pixel 30 in the pixel array 40.

[0141] 9, the vertical axis of the top timing chart represents the current flowing through the first vertical signal line 50A, and the horizontal axis represents time. The vertical axis of the second timing chart represents the current flowing through the first vertical signal line 50B, and the horizontal axis represents time. The vertical axis of the third timing chart represents the current flowing through the first vertical signal line 50C, and the horizontal axis represents time. The vertical axis of the fourth timing chart represents the current flowing through the first vertical signal line 50D, and the horizontal axis represents time.

[0142] As shown in FIG. 9 , for each column of the pixel array 40, the control unit 70 causes the current source 62 that passes a current to the first vertical signal line 50 of the readout execution pixel group, which is a pixel group 100 consisting of pixels 30 that output pixel signals, to be in a first active state, i.e., a state in which a first amount of current passes, thereby passing a first amount of current to the first vertical signal line 50 of the readout execution pixel group, and causes the other current sources 62 to be in a second active state, i.e., a state in which a second amount of current that is less than the first amount of current passes, thereby passing a second current to the first vertical signal line of the pixel group 100 other than the readout execution pixel group.

[0143] By the control unit 70 controlling the current source 62 as described above, the power consumption of the image sensor 1 is reduced compared to when the first amount of current flows through all of the first vertical signal lines 50 .

[0144] FIG. 10 is a timing chart showing how the control unit 70 controls the corresponding current source 62, etc. for each column of the pixel array 40 to pass a current through the first vertical signal line 50 in order to read out a pixel signal from each pixel 30 in the pixel array 40.

[0145] 10 , the vertical axis of the top timing chart represents the current flowing through the first vertical signal line 50A, and the horizontal axis represents time. The vertical axis of the second timing chart represents the current flowing through the first vertical signal line 50B, and the horizontal axis represents time. The vertical axis of the third timing chart represents the current flowing through the first vertical signal line 50C, and the horizontal axis represents time. The vertical axis of the fourth timing chart represents the current flowing through the first vertical signal line 50D, and the horizontal axis represents time.

[0146] As shown in FIG. 10 , for each column of the pixel array 40, the control unit 70 (1) activates the current source 62 that causes a current to flow to the first vertical signal line 50 of the readout pixel group, which is the pixel group 100 made up of the pixels 30 that output pixel signals, thereby causing a first amount of current to flow to the first vertical signal line 50 of the readout pixel group, and (2) activates the current source 62 that causes a current to flow to the first vertical signal line 50 of the pre-readout pixel group, which is the pixel group 100 made up of the pixels 30 that will output pixel signals after the pixels 30 included in the readout pixel group, thereby causing a pixel signal of the pixel 30 included in the pre-readout pixel group to be output. By making the current source 62 that supplies current to the first vertical signal line 50 of the readout execution pixel group active before starting output, a first amount of current flows through the first vertical signal line 50 of the readout execution pixel group before the pixels 30 included in the readout execution pixel group start outputting pixel signals, and (3) by making the current source 62 that supplies current to the first vertical signal line 50 of the readout execution pixel group and the current sources 62 other than the current source 62 that supplies current to the first vertical signal line 50 of the readout execution pixel group inactive, i.e., not passing current, no current flows through the first vertical signal line 50 of pixel groups 100 other than the readout execution pixel group and the readout execution pixel group.

[0147] By the control unit 70 controlling the current source 62 as described above, the power consumption of the image sensor 1 is reduced compared to when the first amount of current flows through all of the first vertical signal lines 50 .

[0148] In general, when a pixel signal is read from a pixel 30 using the first vertical signal line 50 through which the current source 62 passes current immediately after the current source 62 is changed from an inactive state to an active state, the pixel signal may not be read out accurately.

[0149] In contrast, by the control unit 70 controlling the current source 62 as described above, the current source 62 that supplies current to the first vertical signal line 50 of the pre-readout pixel group in each column of the pixel array 40 is changed from an inactive state to an active state before the pixel 30 included in the pre-readout pixel group starts outputting pixel signals.

[0150] Therefore, by the control unit 70 controlling the current source 62 as described above, when pixel signals are read out from the pixels 30, it is possible to prevent the pixel signals from being read out with high accuracy.

[0151] FIG. 11 is a timing chart showing how the control unit 70 controls the corresponding current source 62, etc. for each column of the pixel array 40 to pass a current through the first vertical signal line 50 in order to read out a pixel signal from each pixel 30 in the pixel array 40.

[0152] 11 , the vertical axis of the top timing chart represents the current flowing through the first vertical signal line 50A, and the horizontal axis represents time. The vertical axis of the second timing chart represents the current flowing through the first vertical signal line 50B, and the horizontal axis represents time. The vertical axis of the third timing chart represents the current flowing through the first vertical signal line 50C, and the horizontal axis represents time. The vertical axis of the fourth timing chart represents the current flowing through the first vertical signal line 50D, and the horizontal axis represents time.

[0153] As shown in FIG. 11 , for each column of the pixel array 40, the control unit 70 (1) activates the current source 62 that causes a current to flow to the first vertical signal line 50 of the readout execution pixel group, which is the pixel group 100 made up of the pixels 30 that output pixel signals, thereby causing a first amount of current to flow to the first vertical signal line 50 of the readout execution pixel group, and (2) activates the current source 62 that causes a current to flow to the first vertical signal line 50 of the post-readout pixel group, which is the pixel group 100 made up of the pixels 30 that output pixel signals immediately before the pixels 30 included in the post-readout pixel group, after the pixels 30 included in the post-readout pixel group have finished outputting pixel signals. (3) by keeping the current source 62 that supplies current to the first vertical signal line 50 of the readout execution pixel group and the current sources 62 other than the current source 62 that supplies current to the first vertical signal line 50 of the readout execution pixel group in an inactive state, i.e., a state in which no current is supplied, no current is supplied to the first vertical signal line 50 of pixel groups 100 other than the readout execution pixel group and the readout execution pixel group.

[0154] By the control unit 70 controlling the current source 62 as described above, the power consumption of the image sensor 1 is reduced compared to when the first amount of current flows through all of the first vertical signal lines 50 .

[0155] Furthermore, generally, when the current source 62 that supplies a current to the first vertical signal line 50 of a certain column of the pixel array 40 is changed from an active state to an inactive state, this may adversely affect the current that is supplied to the first vertical signal line 50 of another column adjacent to the column. This adverse effect may prevent accurate readout of pixel signals from the pixels 30 connected to the first vertical signal line 50 of the other column.

[0156] In contrast, by controlling the current source 62 as described above, the control unit 70 continues to maintain an active state of the current source 62 that supplies current to the first vertical signal line 50 of the readout pixel group in a certain column of the pixel array 40, even if, for a certain period of time after the readout of pixel signals from the pixels 30 included in the readout pixel group in that column has been completed, there exists a pixel 30 in another column adjacent to that column whose pixel signals are being continuously read out.

[0157] Therefore, by the control unit 70 controlling the current source 62 as described above, even if there are pixels 30 in other columns adjacent to a certain column of the pixel array 40 for which pixel signal reading continues for a certain period of time after reading of pixel signals from the pixels 30 included in the readout execution pixel group in that column has been completed, it is possible to prevent pixel signals from being unable to be read out accurately from those pixels 30.

[0158] (Modification 1) An image sensor according to Modification 1, which is configured by partially modifying the configuration of the image sensor 1 according to the first embodiment, will be described below.

[0159] In the following, for the imaging element of variant 1, components that are similar to those of the imaging element 1 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from the imaging element 1.

[0160] The image sensor according to the first modification is configured by changing the readout circuit 60 of the image sensor 1 according to the first embodiment to the readout circuit according to the first modification.

[0161] FIG. 12 is a plan view of a readout circuit 60A according to the first modification.

[0162] As shown in FIG. 12, the readout circuit 60A is configured by removing the first impedance conversion circuit 61B and the first impedance conversion circuit 61D from the readout circuit 60 according to embodiment 1 and adding a switch 65A and a switch 65B for each column of the pixel array 40.

[0163] The switch 65A selectively switches and connects the input of the first impedance conversion circuit 61A to either the node 2AB or the node 2BB.

[0164] The switch 65B selectively switches and connects the input of the first impedance conversion circuit 61C to either the node 2CB or the node 2DB.

[0165] <Discussion> In the image sensor according to the first variant of the above configuration, in each column of the pixel array 40, the first vertical signal line 50A and the first vertical signal line 50B provided in the first pixel group 100A and the second pixel group 100B adjacent to each other in the column direction can share one first impedance conversion circuit 61A.

[0166] Furthermore, in the imaging element according to the first configuration variant, in each column of the pixel array 40, the first vertical signal line 50C and the first vertical signal line 50D provided in the third pixel group 100C and the fourth pixel group 100D adjacent to each other in the column direction can share one first impedance conversion circuit 61B.

[0167] (Modification 2) An image sensor according to Modification 2, which is configured by partially changing the configuration of the image sensor according to Modification 1, will be described below.

[0168] In the following, for the imaging element of variant 2, components that are similar to those of the imaging element of variant 1 will be assigned the same symbols as those that have already been explained, and detailed explanations will be omitted. The explanation will focus on the differences from the imaging element of variant 1.

[0169] The image sensor according to the second modification is configured by changing the readout circuit 60A of the image sensor according to the first modification to the readout circuit according to the second modification.

[0170] FIG. 13 is a plan view of a readout circuit 60B according to the second modification.

[0171] As shown in FIG. 13, the readout circuit 60B is configured by removing the common signal line 63 from the readout circuit 60A according to variant example 1 and adding a first common signal line 631, a second common signal line 632, and a switch 66 for each column of the pixel array 40.

[0172] The output of the first impedance conversion circuit 61A is connected to one input of the switch 66 via a first common signal line 631, and the output of the first impedance conversion circuit 61C is connected to the other input of the switch 66 via a second common signal line 632.

[0173] The switch 66 selectively switches and connects the input of the first AD converter 64 to either the first common signal line 631 or the second common signal line 632 .

[0174] <Discussion> With the image sensor according to the modified example 2 having the above configuration, it is possible to reduce the load capacitance driven by the output of the first impedance conversion circuit 61A and the load capacitance driven by the output of the first impedance conversion circuit 61C in each column of the pixel array 40 compared to the image sensor according to the modified example 1. Therefore, with the image sensor according to the modified example 2, it is possible to further increase the readout speed of pixel signals from the pixels 30.

[0175] (Modification 3) An image sensor according to Modification 3, which is configured by partially modifying the configuration of the image sensor 1 according to the first embodiment, will be described below.

[0176] In the following, for the imaging element of variant example 3, components that are similar to those of the imaging element 1 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from the imaging element 1.

[0177] The imaging element according to Modification 3 is configured by changing the pixels 30 of the imaging element 1 according to Embodiment 1 to pixels according to Modification 3, changing the pixel array 40 to a pixel array according to Modification 3, changing the readout circuit 60 to a readout circuit according to Modification 3, and changing the control unit 70 to a control unit according to Modification 3.

[0178] FIG. 14 is a plan view of a pixel array 40C according to the third modification.

[0179] As shown in Figure 14, pixel array 40C is configured by changing each of N pixel groups 100 of pixel array 40 according to embodiment 1 to N pixel groups 101 (corresponding to first pixel group 101A, second pixel group 101B, third pixel group 101C, and fourth pixel group 101D in Figure 14).

[0180] Each of the N pixel groups 101 is configured by changing pixel 30 to pixel 30C from each of the N pixel groups 100 and adding power supply wiring 51 (corresponding to power supply wiring 51A, power supply wiring 51B, power supply wiring 51C, and power supply wiring 51D in Figure 14).

[0181] FIG. 15 is a circuit diagram showing the configuration of a pixel 30C according to the third modification.

[0182] As shown in FIG. 15, a pixel 30C is configured by changing the power supply wiring 37 according to the first embodiment to a power supply wiring 37D.

[0183] The power supply wiring 37D is connected to the power supply wiring 51 included in the pixel group 100 including the pixel 30C.

[0184] Returning to FIG. 14, the description of the pixel array 40C continues.

[0185] In each column of the pixel array 40C, the power supply wiring 51A is connected to the power supply wiring 37D of the pixel 30C included in the first pixel group 100A, and has a node 2AC connected to a node on the second semiconductor chip 12 side (here, node 2AD described later).

[0186] In each column of the pixel array 40C, the power supply wiring 51B is connected to the power supply wiring 37D of the pixel 30C included in the second pixel group 100B, and has a node 2BC connected to a node on the second semiconductor chip 12 side (here, node 2BD described later).

[0187] In each column of the pixel array 40C, the power supply wiring 51C is connected to the power supply wiring 37D of the pixel 30C included in the third pixel group 100C, and has a node 2CC connected to a node on the second semiconductor chip 12 side (here, node 2CD described later).

[0188] In each column of the pixel array 40C, the power supply wiring 51D is connected to the power supply wiring 37D of the pixel 30C included in the fourth pixel group 100D, and has a node 2DC connected to a node on the second semiconductor chip 12 side (here, node 2DD described later).

[0189] FIG. 16 is a plan view of a readout circuit 60C according to the third modification.

[0190] As shown in FIG. 16, the readout circuit 60C is configured by adding a switch 67A, a switch 67B, a switch 67C, a switch 67D, a node 2AD, a node 2BD, a node 2CD, and a node 2DD to the readout circuit 60 according to embodiment 1, for each column of the pixel array 40.

[0191] The switch 67A selectively switches and connects the input of the first impedance conversion circuit 61A and the current source 62A to either the node 2AB or the node 2AD.

[0192] The switch 67B selectively connects the input of the first impedance conversion circuit 61B and the current source 62B to either the node 2BB or the node 2BD.

[0193] The switch 67C selectively switches and connects the input of the first impedance conversion circuit 61C and the current source 62C to either the node 2CB or the node 2CD.

[0194] The switch 67D selectively switches and connects the input of the first impedance conversion circuit 61D and the current source 62D to either the node 2DB or the node 2DD.

[0195] The control unit of variant example 3 activates, for each column of the pixel array 40, a current source 62 that flows a current to a power supply wiring 51 connected to a pixel 30C included in a pre-readout pixel group, which is a pixel group 100 made up of pixels 30C that will output a pixel signal after the pixel 30C included in a readout execution pixel group, which is a pixel group 100 made up of pixels 30C that will output a pixel signal, before the pixel 30C included in the pre-readout pixel group starts to output a pixel signal, thereby flowing a current to the power supply wiring 37 of the pixel 30C included in the pre-readout pixel group before the pixel 30C included in the pre-readout pixel group starts to output a pixel signal, and by deactivating the other current sources 62, no current other than the current that flows when the pixel 30C is operating flows to the power supply wiring 37 of the pixel 30C included in a pixel group 100 other than the pre-readout pixel group.

[0196] Here, making the current source 62 that passes current through the power supply wiring 51 active means controlling the switch 67 connected to the corresponding current source 62 to make the corresponding power supply wiring 51 and the corresponding current source 62 connected.

[0197] Also, here, making the current source 62 that flows current through the power supply wiring 51 inactive means controlling the switch 67 connected to the corresponding current source 62 to make the corresponding power supply wiring 51 and the corresponding current source 62 not connected to each other.

[0198] <Discussion> Generally, a voltage difference occurs between the power supply voltage supplied to pixel 30C when no current is flowing through power supply wiring 51 connected to pixel 30C and the power supply voltage supplied to pixel 30C when current is flowing through power supply wiring 51 connected to pixel 30C, the voltage difference being due to IR drop that occurs depending on the amount of current flowing. Furthermore, a difference occurs in the pixel signal read out when no IR drop is occurring and when an IR drop is occurring.

[0199] In contrast, in the image sensor according to the third modified example of the configuration, in each column, a current begins to flow through the power supply wiring 51 connected to the pixels 30C included in the pre-readout pixel group before the pixels 30C included in the pre-readout pixel group start to output pixel signals. Therefore, in the image sensor according to the third modified example of the configuration, an IR drop has already occurred at the time when the pixels 30C included in the pre-readout pixel group start to output pixel signals. Therefore, in the image sensor according to the third modified example of the configuration, when reading out pixel signals from the pixels 30C, it is possible to prevent the pixel signals from being unable to be read out accurately due to the presence or absence of the IR drop.

[0200] In addition, in Modification 3, the control unit according to Modification 3 may perform the following operations instead of the operations described above.

[0201] That is, for each column of the pixel array 40, the control unit in accordance with the third modification keeps the current source 62 that flows current to the power supply wiring 51 connected to the pixels 30C included in the post-read execution pixel group, which is the pixel group 100 made up of the pixels 30C that output a pixel signal immediately before the pixels 30C included in the readout execution pixel group, which is the pixel group 100 made up of the pixels 30C that output a pixel signal, in an active state for a certain period of time even after the pixels 30C of the post-readout execution pixel group have finished outputting their pixel signals, thereby allowing current to continue to flow to the power supply wiring 37 of the pixels 30C included in the post-readout execution pixel group for a certain period of time even after the pixels 30C included in the post-readout execution pixel group have finished outputting their pixel signals, and by keeping the other current sources 62 in an inactive state, no current other than the current that flows when the pixels 30C are operating flows to the power supply wiring 37 of the pixels 30C included in the pixel groups 100 other than the post-readout execution pixel group.

[0202] Generally, when a state in which a current flows through a pixel 30C in a certain column changes to a state in which a current does not flow, the voltage of the power supply wiring 51 connected to the pixel 30C in another column adjacent to the column may change. This voltage change may prevent accurate reading of pixel signals from the pixel 30C in the other column.

[0203] In contrast, with the image sensor according to the third modified example of the above configuration, even if, for a certain period after completion of readout of pixel signals from pixels 30C included in a readout execution pixel group in a certain column, there exists a pixel 30C in another column adjacent to the column from which pixel signals are continuously read, a state in which a current continues to flow is maintained through the power supply wiring connected to the pixel 30C included in the readout execution pixel group in the certain column during that certain period. Therefore, with the image sensor according to the third modified example of the above configuration, even if, for a certain period after completion of readout of pixel signals from pixels 30C included in a readout execution pixel group in a certain column, there exists a pixel 30C in another column adjacent to the column from which pixel signals are continuously read, it is possible to prevent pixel signals from being unable to be read out with high accuracy from those pixels 30C.

[0204] (Modification 4) Hereinafter, an image sensor according to Modification 4, which is configured by partially changing the configuration of the image sensor according to Modification 2, will be described.

[0205] In the following, for the imaging element of variant 4, components that are similar to those of the imaging element of variant 2 will be assigned the same symbols as those that have already been explained, and detailed explanations will be omitted. The explanation will focus on the differences from the imaging element of variant 2.

[0206] The image sensor according to the fourth modification is configured by changing the readout circuit 60B of the image sensor according to the second modification to the readout circuit according to the fourth modification.

[0207] FIG. 17 is a plan view of a readout circuit 60D according to the fourth modification.

[0208] As shown in FIG. 17, the readout circuit 60D is configured by adding a switch 68A and a switch 68B for each column of the pixel array 40 to the readout circuit 60B according to the second modification.

[0209] The switch 68A switches the node 2AB and the node 2BB between a conductive state and a non-conductive state, i.e., the switch 68A switches the first vertical signal line 50A included in the first pixel group 100A and the first vertical signal line 50B included in the second pixel group 100B between a conductive state and a non-conductive state.

[0210] The switch 68B switches the node 2CB and the node 2DB between a conductive state and a non-conductive state, i.e., the switch 68B switches the first vertical signal line 50C included in the third pixel group 100C and the first vertical signal line 50D included in the fourth pixel group 100D between a conductive state and a non-conductive state.

[0211] <Discussion> With the image sensor according to the fourth variation of the above configuration, in each column of the pixel array 40, it is possible to mix and read out pixel signals from the pixels 30 included in the first pixel group 100A and the pixels 30 included in the second pixel group 100B, and it is also possible to mix and read out pixel signals from the pixels 30 included in the third pixel group 100C and the pixels 30 included in the fourth pixel group 100D.

[0212] Second Embodiment An image pickup device according to a second embodiment, which is configured by partially modifying the configuration of the image pickup device 1 according to the first embodiment, will be described below.

[0213] In the following, for the imaging element of embodiment 2, components that are similar to those of the imaging element 1 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from the imaging element 1.

[0214] The imaging element of embodiment 2 is configured by changing the pixel array 40 of the imaging element 1 of embodiment 1 to the pixel array of embodiment 2, and changing the readout circuit 60 to the readout circuit of embodiment 2.

[0215] FIG. 18 is a plan view of a pixel array 40E according to the second embodiment.

[0216] As shown in FIG. 18, a pixel array 40E is formed by arranging a plurality of pixels 30 in a matrix.

[0217] As shown in FIG. 18 , the pixel array 40E includes, for each column, N (N is an integer of 3 or greater) pixel groups 110 (corresponding to the first pixel group 110A, the second pixel group 110B, the third pixel group 110C, and the fourth pixel group 110D in FIG. 18 ), each of which is composed of K or more (K is an integer of 4 or greater) pixels 30 arranged consecutively in the column direction. Here, as an example, as shown in FIG. 18 , a case will be described in which N is 4, i.e., the N pixel groups 110 are the first pixel group 110A, the second pixel group 110B, the third pixel group 110C, and the fourth pixel group 110D. However, N does not necessarily have to be limited to 4 as long as it is an integer of 3 or greater. Here, the pixel groups 110 will be described as each consisting of K pixels 30. However, it is not necessarily required that all pixel groups 110 be composed of K pixels 30. For example, the first pixel group 110A may consist of K pixels 30, the second pixel group 110B may consist of K+1 pixels 30, the third pixel group 110C may consist of K pixels 30, and the fourth pixel group 110D may consist of K+2 pixels 30.

[0218] As shown in FIG. 18 , each of the N pixel groups 110 includes M (M is an integer equal to or greater than 2 and equal to or less than K / 2) vertical signal lines, including a first vertical signal line 55A (corresponding to the first vertical signal line 55AA, the first vertical signal line 55AB, the first vertical signal line 55AC, and the first vertical signal line 55AD in FIG. 18 ) connected to L or more (L is an integer equal to or greater than 2 and equal to or less than K / 2) pixels 30 out of the K pixels 30, and a second vertical signal line 55B (corresponding to the second vertical signal line 55BA, the second vertical signal line 55BB, the second vertical signal line 55BC, and the second vertical signal line 55BD in FIG. 18 ) connected to another L or more pixels 30 out of the K pixels 30.

[0219] Here, it is described that each of the N pixel groups 110 has M vertical signal lines including a first vertical signal line 55A, a second vertical signal line 55B, a third vertical signal line 55C, and an Mth vertical signal line 55M. However, the M vertical signal lines that each of the N pixel groups 110 has only to have at least two vertical signal lines, the first vertical signal line 55A and the second vertical signal line 55B.

[0220] In addition, the following description will be given assuming that the first vertical signal line 55A, the second vertical signal line 55B, the third vertical signal line 55C, and the Mth vertical signal line 55M are each connected to L pixels 30. However, as long as the first vertical signal line 55A, the second vertical signal line 55B, the third vertical signal line 55C, and the Mth vertical signal line 55M are each connected to L or more pixels 30, the configuration is not necessarily limited to one in which all of the first vertical signal line 55A, the second vertical signal line 55B, the third vertical signal line 55C, and the Mth vertical signal line 55M are connected to L pixels 30. For example, the configuration may be such that the first vertical signal line 55A is connected to L pixels 30, the second vertical signal line 55B is connected to L+1 pixels 30, the third vertical signal line 55C is connected to L pixels 30, and the Mth vertical signal line 55M is connected to L+2 pixels 30.

[0221] In each column of the pixel array 40E, the first vertical signal line 55AA has a node 2AAA connected to a node (here, a node 2AAB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 55AA has the node 2AAA at the end on the first vertical signal line 55AB side.

[0222] In each column of the pixel array 40E, the first vertical signal line 55AB has a node 2ABA connected to a node (here, a node 2ABB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 55AB has a node 2ABA at an end on the first vertical signal line 55AA side.

[0223] In each column of the pixel array 40E, the first vertical signal line 55AC has a node 2ACA that is connected to a node (here, a node 2ACB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 55AC has a node 2ACA at an end on the first vertical signal line 55AD side.

[0224] In each column of the pixel array 40E, the first vertical signal line 55AD has a node 2ADA connected to a node (here, a node 2ADB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the first vertical signal line 55AD has the node 2ADA at the end on the first vertical signal line 55AC side.

[0225] In each column of the pixel array 40E, the second vertical signal line 55BA has a node 2BAA that is connected to a node (here, a node 2BAB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the second vertical signal line 55BA has a node 2BAA at an end on the second vertical signal line 55BB side.

[0226] In each column of the pixel array 40E, the second vertical signal line 55BB has a node 2BBA connected to a node (here, a node 2BBB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the second vertical signal line 55BB has a node 2BBA at an end on the second vertical signal line 55BA side.

[0227] In each column of the pixel array 40E, the second vertical signal line 55BC has a node 2BCA connected to a node (here, a node 2BCB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the second vertical signal line 55BC has the node 2BCA at the end on the second vertical signal line 55BD side.

[0228] In each column of the pixel array 40E, the second vertical signal line 55BD has a node 2BDA connected to a node (here, a node 2BDB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the second vertical signal line 55BD has a node 2BDA at an end on the side of the second vertical signal line 55BC.

[0229] In each column of the pixel array 40E, the third vertical signal line 55CA has a node 2CAA that is connected to a node (here, a node 2CAB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the third vertical signal line 55CA has the node 2CAA at the end on the third vertical signal line 55CB side.

[0230] In each column of the pixel array 40E, the third vertical signal line 55CB has a node 2CBA connected to a node (here, a node 2CBB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the third vertical signal line 55CB has a node 2CBA at an end on the third vertical signal line 55CA side.

[0231] In each column of the pixel array 40E, the third vertical signal line 55CC has a node 2CCA connected to a node (here, a node 2CCB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the third vertical signal line 55CC has a node 2CCA at an end on the third vertical signal line 55CD side.

[0232] In each column of the pixel array 40E, the third vertical signal line 55CD has a node 2CDA connected to a node (here, a node 2CDB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the third vertical signal line 55CD has a node 2CDA at the end on the third vertical signal line 55CC side.

[0233] In each column of the pixel array 40E, the Mth vertical signal line 55MA has a node 2MAA connected to a node (here, a node 2MAB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the Mth vertical signal line 55MA has a node 2MAA at an end on the Mth vertical signal line 55MB side.

[0234] In each column of the pixel array 40E, the Mth vertical signal line 55MB has a node 2MBA connected to a node (here, a node 2MBB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the Mth vertical signal line 55MB has a node 2MBA at an end on the Mth vertical signal line 55MA side.

[0235] In each column of the pixel array 40E, the Mth vertical signal line 55MC has a node 2MCA connected to a node (here, a node 2MCB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the Mth vertical signal line 55MC has a node 2MCA at an end on the Mth vertical signal line 55MD side.

[0236] In each column of the pixel array 40E, the Mth vertical signal line 55MD has a node 2MDA connected to a node (here, a node 2MDB described later) on the side of the second semiconductor chip 12. Here, as a non-limiting example, the Mth vertical signal line 55MD has a node 2MDA at an end on the Mth vertical signal line 55MC side.

[0237] FIG. 19 is a plan view of a readout circuit 60E according to the second embodiment.

[0238] 19 , the readout circuit 60E includes, for each column of the pixel array 40E, N / 2 (here, 2) first impedance conversion circuits 611 (corresponding to the first impedance conversion circuit 611A and the first impedance conversion circuit 611C in FIG. 19 ), N / 2 second impedance conversion circuits 612 (corresponding to the second impedance conversion circuit 612A and the second impedance conversion circuit 612C in FIG. 19 ), N / 2 third impedance conversion circuits 613 (corresponding to the third impedance conversion circuit 613A and the third impedance conversion circuit 613C in FIG. 19 ), N / 2 Mth impedance conversion circuits 61M (corresponding to the Mth impedance conversion circuit 61MA and the Mth impedance conversion circuit 61MC in FIG. 19 ), and M×N current sources 62 (the current sources 61A and 61B in FIG. 19 ). 2AA, current source 62AB, current source 62AC, current source 62AD, current source 62BA, current source 62BB, current source 62BC, current source 62BD, current source 62CA, current source 62CB, current source 62CC, current source 62CD, current source 62MA, current source 62MB, current source 62MC, and current source 62MD), and M×N / 2 switches 65 (switches 65AA, 65AB, 65BA, 19) common signal lines 63 (corresponding to common signal lines 63A, 63B, 63C, and 63M in FIG. 19), a first AD converter 64A, a second AD converter 64B, a third AD converter 64C, and an Mth AD converter 64M.

[0239] Here, the readout circuit 60E is described as having a plurality (two in this case) of first impedance conversion circuits 611, a plurality (two in this case) of second impedance conversion circuits 612, a plurality (two in this case) of third impedance conversion circuits 613, and a plurality (two in this case) of Mth impedance conversion circuits 61M for each column of the pixel array 40E, but it is sufficient that the readout circuit 60E has at least a plurality of first impedance conversion circuits 611 and a plurality of second impedance conversion circuits 612 for each column of the pixel array 40E.

[0240] Furthermore, here, the readout circuit 60E is described as having M AD converters including a first AD converter 64A, a second AD converter 64B, a third AD converter 64C, and an Mth AD converter 64M for each column of the pixel array 40E, but it is sufficient that the readout circuit 60E has at least the first AD converter 64A and the second AD converter 64B for each column of the pixel array 40E.

[0241] In addition, the readout circuit 60E has, for each column of the pixel array 40E, node 2AAB, node 2ABB, node 2ACB, node 2ADB, node 2BAB, node 2BBB, node 2BCB, node 2BDB, node 2CAB, node 2CBB, node 2CCB, node 2CDB, node 2MAB, node 2MBB, node 2MCB, and node 2MDB.

[0242] The switch 65AA selectively switches and connects the input of the first impedance conversion circuit 611A to either the node 2AAB or the node 2ABB.

[0243] The switch 65AB selectively switches and connects the input of the first impedance conversion circuit 611C to either the node 2ACB or the node 2ADB.

[0244] The switch 65BA selectively switches and connects the input of the second impedance conversion circuit 612A to either the node 2BAB or the node 2BBB.

[0245] The switch 65BB selectively switches and connects the input of the second impedance conversion circuit 612C to either the node 2BCB or the node 2BDB.

[0246] The switch 65CA selectively switches and connects the input of the third impedance conversion circuit 613A to either the node 2CAB or the node 2CBB.

[0247] The switch 65CB selectively switches and connects the input of the third impedance conversion circuit 613C to either the node 2CCB or the node 2CDB.

[0248] The switch 65MA selectively switches and connects the input of the Mth impedance conversion circuit 61MA to either the node 2MAB or the node 2MBB.

[0249] The switch 65MB selectively switches and connects the input of the Mth impedance conversion circuit 61MC to either the node 2MCB or the node 2MDB.

[0250] The first impedance conversion circuit 611, the second impedance conversion circuit 612, the third impedance conversion circuit 613, and the Mth impedance conversion circuit 61M are circuits similar to the first impedance conversion circuit 61 according to the first embodiment.

[0251] As shown in FIGS. 19 and 18 , the input of the first impedance conversion circuit 611A is connected to the first vertical signal line 55AA or the first vertical signal line 55AB in the corresponding column of the pixel array 40E via a switch 65AA and nodes 2AAB and 2AAA, or nodes 2ABB and 2ABA, and the input of the first impedance conversion circuit 611C is connected to the first vertical signal line 55AA or the first vertical signal line 55AB in the corresponding column of the pixel array 40E via a switch 65AB and nodes 2ACB and 2ACA, or nodes 2ADB and 2ADA. The input of the second impedance conversion circuit 612A is connected to the second vertical signal line 55AC or the first vertical signal line 55AD of the corresponding column of the pixel array 40E via a switch 65BA and nodes 2BAB and 2BAA, or nodes 2BBB and 2BBA. The input of the second impedance conversion circuit 612C is connected to the second vertical signal line 55BA or the second vertical signal line 55BB of the corresponding column of the pixel array 40E via a switch 65BB and nodes 2BCB and 2BCA, or nodes 2BDB and 2BDA. The input of the third impedance conversion circuit 613A is connected to the second vertical signal line 55BC or the second vertical signal line 55BD in the corresponding column of the pixel array 40E via a switch 65CA and nodes 2CAB and 2CAA, or nodes 2CBB and 2CBA, respectively, and the input of the third impedance conversion circuit 613C is connected to the third vertical signal line 55CA or the third vertical signal line 55CB in the corresponding column of the pixel array 40E via a switch 65CB and nodes 2CCB and 2CCA, or nodes 2CDB and 2CBA. The input of the Mth impedance conversion circuit 61MA is connected to the Mth vertical signal line 55MA or the Mth vertical signal line 55MB in the corresponding column of the pixel array 40E via a switch 65MA and nodes 2MAB and 2MAA, or nodes 2MBB and 2MBA, and the input of the Mth impedance conversion circuit 61MC is connected to the Mth vertical signal line 55CC or the Mth vertical signal line 55CD in the corresponding column of the pixel array 40E via a switch 65MB and nodes 2MCB and 2MCA, or nodes 2MBB and 2MBA.The node 2MDB and the node 2MDA are connected to the Mth vertical signal line 55MC or the Mth vertical signal line 55MD in the corresponding column of the pixel array 40E.

[0252] The outputs of the N / 2 first impedance conversion circuits 611 are connected to a first AD converter 64A via a common signal line 63A, the outputs of the N / 2 second impedance conversion circuits 612 are connected to a second AD converter 64B via a common signal line 63B, the outputs of the N / 2 third impedance conversion circuits 613 are connected to a third AD converter 64C via a common signal line 63C, and the outputs of the N / 2 Mth impedance conversion circuits 61M are connected to an Mth AD converter 64M via a common signal line 63M.

[0253] The first AD converter 64A AD converts each of the first impedance conversion signals output from the N / 2 first impedance conversion circuits 611.

[0254] The second AD converter 64B AD converts each of the second impedance conversion signals output from the N / 2 second impedance conversion circuits 612 .

[0255] The third AD converter 64C AD converts each of the third impedance conversion signals output from the N / 2 third impedance conversion circuits 613.

[0256] The Mth AD converter 64M AD converts each of the Mth impedance conversion signals output from the N / 2 Mth impedance conversion circuits 61M.

[0257] The current source 62AA is connected to the first vertical signal line 55AA in the corresponding column of the pixel array 40E via nodes 2AAB and 2AAA, the current source 62AB is connected to the first vertical signal line 55AB in the corresponding column of the pixel array 40E via nodes 2ABB and 2ABA, the current source 62AC is connected to the first vertical signal line 55AC in the corresponding column of the pixel array 40E via nodes 2ACB and 2ACA, and the current source 62AD is connected to the first vertical signal line 55AA in the corresponding column of the pixel array 40E via nodes 2ADB and 2ADA. The current source 62BA is connected to the first vertical signal line 55AD in the corresponding column of the pixel array 40E via nodes 2BAB and 2BAA, the current source 62BB is connected to the second vertical signal line 55BB in the corresponding column of the pixel array 40E via nodes 2BBB and 2BBA, the current source 62BC is connected to the second vertical signal line 55BC in the corresponding column of the pixel array 40E via nodes 2BCB and 2BCA, and the current source 62BD is connected to the second vertical signal line 55BC in the corresponding column of the pixel array 40E via nodes 2BD The current source 62CA is connected to the second vertical signal line 55BD in the corresponding column of the pixel array 40E via nodes 2CAB and 2CAA, the current source 62CB is connected to the third vertical signal line 55CB in the corresponding column of the pixel array 40E via nodes 2CBB and 2CBA, and the current source 62CC is connected to the third vertical signal line 55BD in the corresponding column of the pixel array 40E via nodes 2CCB and 2CCA. The current source 62CD is connected to the third vertical signal line 55CD in the corresponding column of the pixel array 40E via nodes 2CDB and 2CDA, the current source 62MA is connected to the Mth vertical signal line 55MA in the corresponding column of the pixel array 40E via nodes 2MAB and 2MAA, the current source 62MB is connected to the Mth vertical signal line 55MB in the corresponding column of the pixel array 40E via nodes 2MBB and 2MBA, and the current source 62MC is connected to the Mth vertical signal line 55MB in the corresponding column of the pixel array 40E via nodes 2MCB and 2MCA.The current source 62MD is connected to the Mth vertical signal line 55MC in the corresponding column of the pixel array 40E via the node 2MDB and the node 2MDA, and the current source 62MD is connected to the Mth vertical signal line 55MD in the corresponding column of the pixel array 40E via the node 2MDB and the node 2MDA.

[0258] <Discussion> In the imaging device according to the second embodiment having the above configuration, in each column of the pixel array 40E, pixel signals can be read out in parallel from the pixels 30 connected to the first vertical signal line 55A and the pixels 30 connected to the second vertical signal line 55B that are included in the same pixel group, i.e., that are relatively close to each other. As a result, when pixel signals are read out from the pixels 30 by sequentially performing readout scanning for each row of the pixel array 40E, when imaging a moving subject, a step (rolling shutter distortion) of the subject in the captured image that can occur when pixel signals are read out in parallel from two pixels that are relatively far apart in each column of the pixel array 40E can be made relatively small, and therefore the step can be made less noticeable.

[0259] In addition, in embodiment 2, in one pixel group 110 (for example, the first pixel group 110A) among the N pixel groups 110, at least one of the pixels 30 connected to each of the M vertical signal lines may be an OB (Optical Black) pixel 30E.

[0260] Here, the OB pixel 30E refers to a pixel 30 whose photoelectric conversion unit 31 does not receive light.

[0261] FIG. 20 is a schematic diagram showing an example of the configuration of the read circuit 60E when N is 4, M is 4, K is 8, and L is 2.

[0262] 20 , in this configuration example, of the pixels 30 included in the first pixel group 110A, four pixels 30 are OB pixels 30E. In the first pixel group 110A, each of the four OB pixels 30E is connected to one of four vertical signal lines.

[0263] In this configuration example, each of the four AD converters (corresponding to ADC1, ADC2, ADC3, and ADC4 in FIG. 20, and corresponding to the first AD converter 64A, the second AD converter 64B, the third AD converter 64C, and the Mth AD converter 64M in FIG. 19) performs AD conversion on the pixel signal of the OB pixel 30E.

[0264] Therefore, according to this configuration example, the offset errors of these four AD converters can be corrected using the pixel signals of these four OB pixels 30E.

[0265] (Modification 5) An image sensor according to Modification 5, which is configured by partially modifying the configuration of the image sensor according to Embodiment 2, will be described below.

[0266] In the following, for the imaging element of variant 5, components that are similar to those of the imaging element of embodiment 2 will be assigned the same symbols as those that have already been explained, and detailed explanations will be omitted. The explanation will focus on the differences from the imaging element of embodiment 2.

[0267] The imaging element according to the fifth modification is configured by changing the pixel array 40E of the imaging element according to the second embodiment to the pixel array according to the fifth modification, and changing the readout circuit 60E to the readout circuit according to the fifth modification.

[0268] FIG. 21 is a plan view of a pixel array 40F according to the fifth modification.

[0269] As shown in FIG. 21, the pixel array 40F is configured by changing the N pixel groups 110 in each column of the pixel array 40E according to embodiment 2 to N pixel groups 111 (corresponding to the first pixel group 111A, the second pixel group 111B, the third pixel group 111C, and the fourth pixel group 111D in FIG. 18).

[0270] Each of the N pixel groups 111 is configured by changing, from each of the N pixel groups 110, the pixel 30 connected to the first vertical signal line 55A and the pixel 30 connected to the third vertical signal line 55C to pixel 30A, and changing the pixel 30 connected to the second vertical signal line 55B and the pixel 30 connected to the Mth vertical signal line 55M to pixel 30B.

[0271] Here, in Modification 5, L is an integer of 2 or more, M is an integer of 4 or more, and K is an integer of 8 or more.

[0272] Although not shown in FIG. 21 , L or more pixels 30A are connected to the first vertical signal line 55A, L or more pixels 30B are connected to the second vertical signal line 55B, L or more pixels 30A are connected to the third vertical signal line 55C, and L or more pixels 30B are connected to the Mth vertical signal line 55M.

[0273] Pixel 30A is configured from pixel 30 according to embodiment 1, with the photoelectric conversion unit 31 modified to receive light of a first color that has passed through a first color filter, and pixel 30B is configured from pixel 30 according to embodiment 1, with the photoelectric conversion unit 31 modified to receive light of a second color that is different from the light of the first color that has passed through a second color filter.

[0274] FIG. 22 is a plan view of a readout circuit 60F according to the fifth modification.

[0275] As shown in FIG. 22, the read circuit 60F is configured by adding M×N / 2 switches 69 (corresponding to switches 69AA, 69AB, 69AC, 69AD, 69BA, 69BB, 69BC, and 69BD in FIG. 22) to the read circuit 60E according to the second embodiment.

[0276] The switch 69AA switches the node 2AAB and the node 2CAB between a conductive state and a non-conductive state. That is, the switch 69AA switches the first vertical signal line 55AA included in the first pixel group 111A and connected to the pixel 30A, and the third vertical signal line 55CA included in the first pixel group 111A and connected to the pixel 30A, between a conductive state and a non-conductive state.

[0277] The switch 69AB switches the node 2ABB and the node 2CBB between a conductive state and a non-conductive state. That is, the switch 69AB switches the first vertical signal line 55AB included in the second pixel group 111B and connected to the pixel 30A, and the third vertical signal line 55CB included in the second pixel group 111B and connected to the pixel 30A, between a conductive state and a non-conductive state.

[0278] The switch 69AC switches the node 2ACB and the node 2CCB between either a conductive state or a non-conductive state. That is, the switch 69AC switches the first vertical signal line 55AC included in the third pixel group 111C and connected to the pixel 30A, and the third vertical signal line 55CC included in the third pixel group 111C and connected to the pixel 30A, between either a conductive state or a non-conductive state.

[0279] The switch 69AD switches the node 2ADB and the node 2CDB between a conductive state and a non-conductive state. That is, the switch 69AD switches the first vertical signal line 55AD included in the fourth pixel group 111D and connected to the pixel 30A, and the third vertical signal line 55CD included in the fourth pixel group 111D and connected to the pixel 30A, between a conductive state and a non-conductive state.

[0280] The switch 69BA switches the node 2BAB and the node 2MAB between a conductive state and a non-conductive state. That is, the switch 69BA switches the second vertical signal line 55BA included in the first pixel group 111A and connected to the pixel 30B, and the Mth vertical signal line 55MA included in the first pixel group 111A and connected to the pixel 30B, between a conductive state and a non-conductive state.

[0281] The switch 69BB switches the node 2BBB and the node 2MBB between a conductive state and a non-conductive state. That is, the switch 69BB switches the second vertical signal line 55BB included in the second pixel group 111B and connected to the pixel 30B, and the Mth vertical signal line 55MB included in the second pixel group 111B and connected to the pixel 30B, between a conductive state and a non-conductive state.

[0282] The switch 69BC switches the node 2BCB and the node 2MCB between a conductive state and a non-conductive state. That is, the switch 69BC switches the second vertical signal line 55BC included in the third pixel group 111C and connected to the pixel 30B, and the Mth vertical signal line 55MC included in the third pixel group 111C and connected to the pixel 30B, between a conductive state and a non-conductive state.

[0283] The switch 69BD switches the node 2BDB and the node 2MDB between a conductive state and a non-conductive state. That is, the switch 69BD switches the third vertical signal line 55CD included in the fourth pixel group 111D and connected to the pixel 30B, and the Mth vertical signal line 55MD included in the fourth pixel group 111D and connected to the pixel 30B, between a conductive state and a non-conductive state.

[0284] <Discussion> According to the imaging device of Variation 5 having the above configuration, in each column and each pixel group 111 of the pixel array 40F, it is possible to mix and read out pixel signals from the pixel 30A that is connected to the first vertical signal line 55A and receives light of a first color and the pixel 30A that is connected to the third vertical signal line 55C and receives light of the first color, and to mix and read out pixel signals from the pixel 30B that is connected to the second vertical signal line 55B and receives light of a second color and the pixel 30B that is connected to the Mth vertical signal line 55M and receives light of the second color.

[0285] Third Embodiment An imaging device according to a third embodiment, which includes an imaging element according to any one of the first to second embodiments and the first to fifth modifications, will be described below.

[0286] In the following, the imaging device according to embodiment 3 will be described as being equipped with the imaging element 1 according to embodiment 1, but the imaging device according to embodiment 3 does not necessarily have to be limited to a configuration that includes the imaging element 1 according to embodiment 1, as long as it includes the imaging element according to any of embodiments 1 to 2 or variants 1 to 5.

[0287] FIG. 23 is a schematic diagram showing the configuration of an imaging device 300 according to the third embodiment.

[0288] The imaging device 300 is, for example, a digital still camera, a handy video recorder, or the like.

[0289] As shown in FIG. 23, the imaging device 300 includes the imaging element 1, a signal processing device 310, and a lens 320.

[0290] The lens 320 focuses light from the subject that is the object to be imaged by the imaging device 300 onto the area in the imaging element 1 where the pixel array 40 is formed, and forms an image of the subject onto the area in the imaging element 1 where the pixel array 40 is formed.

[0291] The signal processing device 310 performs various signal processing on the signal (for example, an image) output from the image sensor 1 .

[0292] <Considerations> As described above in the first embodiment, the image sensor 1 can increase the speed at which pixel signals are read out from the pixels 30 while suppressing degradation in the quality of the captured image.

[0293] Therefore, the imaging device 300 having the above configuration can increase the speed at which pixel signals are read out from the pixels 30 while suppressing deterioration in the quality of the captured image.

[0294] (Supplementary Note) The imaging element and imaging device according to one aspect of the present disclosure have been described above based on Embodiments 1 to 3 and Modifications 1 to 5, but the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the spirit of the present disclosure, various modifications that would occur to a person skilled in the art may be made to these embodiments and modifications, or configurations constructed by combining components of different embodiments and modifications may also be included within the scope of one or more aspects of the present disclosure.

[0295] (1) In the first to third embodiments and the first to fifth modifications, N has been described as an integer equal to or greater than 3. However, N may be 2. In other words, N may be an integer equal to or greater than 2.

[0296] FIG. 24 shows an example of a plan view of the pixel array 40 when N is 2, and FIG. 25 shows an example of a plan view of the readout circuit 60A when N is 2.

[0297] (2) In the first embodiment, the circuit configuration shown in FIG. 7 is given as an example of the circuit configuration of the first impedance conversion circuit 61 having the function of making the output high impedance.

[0298] However, the first impedance conversion circuit 61 does not need to be limited to the circuit configuration shown in FIG.

[0299] As another circuit configuration of the first impedance conversion circuit 61 having the function of making the output high impedance, for example, the circuit configuration shown in FIG. 26 can be considered.

[0300] The present disclosure is widely applicable to imaging elements, imaging devices, and the like.

[0301] REFERENCE SIGNS LIST 1 imaging element 2AA, 2BA, 2CA, 2DA, 2AC, 2BC, 2CC, 2DC, 2AB, 2BB, 2CB, 2DB, 2AD, 2BD, 2CD, 2DD, 2AAA, 2ABA, 2ACA, 2ADA, 2BAA, 2BBA, 2BCA, 2BDA, 2CAA, 2CBA, 2CCA, 2CDA, 2MAA, 2MBA, 2MCA, 2MDA, 2AAB, 2ABB, 2ACB, 2ADB, 2BAB, 2BBB, 2BCB, 2BDB, 2CAB, 2CBB, 2CCB, 2CDB, 2MAB, 2MBB, 2MCB, 2MDB node 11 first semiconductor chip 12 second semiconductor chip 30, 30A, 30B, 30C Pixel 30E OB pixel 31 Photoelectric conversion unit 32 Charge storage unit 33 Transfer transistor 34 Reset transistor 35 Amplification transistor 36 Selection transistor 37, 37D, 51, 51A, 51B, 51C, 51D Power supply wiring 40, 40C, 40E, 40F Pixel array 50, 50A, 50B, 50C, 50D, 55A, 55AA, 55AB, 55AC, 55AD First vertical signal line 55B, 55BA, 55BB, 55BC, 55BD Second vertical signal line 55C, 55CA, 55CB, 55CC, 55CD Third vertical signal line 55M, 55MA, 55MB, 55MC, 55MD Mth vertical signal line 60, 60A, 60B, 60C, 60D, 60E, 60F Readout circuits 61, 61A, 61B, 61C, 61D, 611, 611A, 611C First impedance conversion circuit 62, 62A, 62B, 62C, 62D, 62AA, 62AB, 62AC, 62AD, 62BA, 62BB, 62BC, 62BD, 62CA, 62CB, 62CC, 62CD, 62MA, 62MB, 62MC, 62MD Current sources 63, 63A, 63B, 63C, 63M Common signal lines 64, 64A First AD converter 64B Second AD converter 64C Third AD converter 64M Mth AD converter 65, 65A, 65B, 65AA, 65AB, 65BA, 65BB, 65CA, 65CB, 65MA, 65MB, 66, 67, 67A, 67B, 67C, 67D, 68A, 68B, 69, 69AA, 69AB, 69AC, 69AD, 69BA, 69BB, 69BC, 69BD, 642 Switch 70 Control unit80 Vertical scanning circuit 90 Reference current source 100, 101, 110, 111 Pixel group 100A, 101A, 110A, 111A First pixel group 100B, 101B, 110B, 111B Second pixel group 100C, 101C, 110C, 111C Third pixel group 100D, 101D, 110D, 111D Fourth pixel group 200 Signal processing circuit 300 Imaging device 310 Signal processing device 320 Lens 612, 612A, 612C Second impedance conversion circuit 613, 613A, 613C Third impedance conversion circuit 61M, 61MA, 61MC Mth impedance conversion circuit 631 First common signal line 632 Second common signal line 641 Output transistor

Claims

1. A pixel array including a plurality of pixels arranged in a matrix, each pixel having a photoelectric conversion unit that converts received light into an electric charge, a charge accumulation unit that accumulates the electric charge converted by the photoelectric conversion unit, and an amplification transistor that outputs a pixel signal corresponding to the amount of electric charge accumulated in the charge accumulation unit; a plurality of first impedance conversion circuits for each column of the pixel array, each having an output impedance lower than an input impedance, wherein a pixel signal output from at least one of the plurality of pixels is input to each of the plurality of first impedance conversion circuits; and a first AD converter for each column of the pixel array that AD converts each of the plurality of first impedance conversion signals output from the plurality of first impedance conversion circuits, wherein the pixel array includes N (N is an integer of 2 or more) pixel groups for each column, each consisting of K or more pixels (K is an integer of 2 or more) of the plurality of pixels, the K or more pixels being arranged consecutively in the column direction, and each of the N pixel groups includes a first vertical signal line connected to L or more (L is an integer of 2 or more and equal to or less than K) first pixels out of the K or more pixels, In the image sensor, for each column of the pixel array, each of the N first vertical signal lines included in the N pixel groups is connected to an input of one of the plurality of first impedance conversion circuits, and an output of each of the plurality of first impedance conversion circuits is connected to the first AD converter.

2. The imaging device according to claim 1, wherein L is equal to K, and the K or more pixels are the L or more first pixels.

3. The image sensor according to claim 1, wherein K is an integer equal to or greater than 4, and L is an integer equal to or greater than 2 and equal to or less than K / 2, further comprising: for each column of the pixel array, a plurality of second impedance conversion circuits having an output impedance lower than an input impedance, each of which receives a pixel signal output from at least one of the plurality of pixels; and a second AD converter for each column of the pixel array that performs AD conversion on the plurality of second impedance conversion signals output from the plurality of second impedance conversion circuits, wherein each of the N pixel groups further comprises second vertical signal lines connected to L or more second pixels among the K or more pixels, the L or more second pixels being different from the L or more first pixels, and wherein for each column of the pixel array, each of the N second vertical signal lines included in the N pixel groups is connected to an input of one of the plurality of second impedance conversion circuits, and an output of each of the plurality of second impedance conversion circuits is connected to the second AD converter.

4. An imaging element according to any one of claims 1 to 3, wherein, for each column of the pixel array, the output of at least one of the plurality of first impedance conversion circuits is connected to the first AD converter via a first common signal line, and the output of at least another of the plurality of first impedance conversion circuits is connected to the first AD converter via a second common signal line different from the first common signal line.

5. The image sensor according to any one of claims 1 to 3, wherein, for each column of the pixel array, at least one input of the plurality of first impedance conversion circuits is alternatively connected to two of the first vertical signal lines provided in two pixel groups that are adjacent to each other in the column direction among the N pixel groups.

6. The image sensor according to any one of claims 1 to 3, wherein each of the plurality of first impedance conversion circuits has an output transistor that outputs each of the plurality of first impedance conversion signals, and each of the output transistors has a higher driving capability than the amplifying transistor.

7. An image sensor according to any one of claims 1 to 3, further comprising a plurality of current sources for supplying current to each of the N first vertical signal lines for each column of the pixel array, and further comprising a reference current source for uniformly defining the currents flowing in at least two current sources out of all of the plurality of current sources included in the image sensor.

8. N is an integer equal to or greater than 4, and the imaging element is configured by stacking a first semiconductor chip on which the pixel array is formed and a second semiconductor chip on which the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed, and in a plan view of the pixel array, for each column of the pixel array, the N first vertical signal lines provided in the N pixel groups extend in the column direction of the pixel array and are lined up in the column direction of the pixel array, and one first impedance conversion circuit of the plurality of first impedance conversion circuits is located between a third vertical signal line and a fourth vertical signal line that are adjacent to each other among the N first vertical signal lines in the column direction of the pixel array, 4. The image sensor according to claim 1, wherein another one of the plurality of first impedance conversion circuits is located between a fifth vertical signal line and a sixth vertical signal line that are adjacent to each other among the N first vertical signal lines and that are different from both the third vertical signal line and the fourth vertical signal line in the column direction of the pixel array.

9. The image sensor according to any one of claims 1 to 3, wherein the image sensor is configured by stacking a first semiconductor chip on which the pixel array is formed and a second semiconductor chip on which the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed, and in a plan view of the pixel array, for each column of the pixel array, the N first vertical signal lines provided for the N pixel groups extend in the column direction of the pixel array and are aligned in the column direction of the pixel array, and the range of existence of one or more wires for connecting outputs of the plurality of first impedance conversion circuits and the first AD converter in the column direction of the pixel array falls within the range of existence of the N first vertical signal lines in the column direction of the pixel array.

10. The image sensor according to any one of claims 1 to 3, wherein the image sensor is configured by stacking a first semiconductor chip on which the pixel array is formed and a second semiconductor chip on which the plurality of first impedance conversion circuits and the first AD converter provided for each column of the pixel array are formed, and wherein, in a plan view of the pixel array, for each column of the pixel array, the N first vertical signal lines provided for the N pixel groups extend in the column direction of the pixel array and are aligned in the column direction of the pixel array, and the total wiring length of one or more lines connecting the outputs of the plurality of first impedance conversion circuits and the first AD converter is smaller than the total wiring length of the N first vertical signal lines.

11. The image sensor according to any one of claims 1 to 3, wherein the pixel array further includes a plurality of current sources for each column that cause a current to flow to each of the N first vertical signal lines, and the image sensor further includes a control unit that controls all of the plurality of current sources of the pixel array, and the control unit activates, for each column of the pixel array, a current source that causes a current to flow to the first vertical signal line of a readout execution pixel group that is a pixel group consisting of the K or more pixels that output pixel signals, and deactivates other current sources.

12. The image sensor according to any one of claims 1 to 3, wherein the pixel array further includes a plurality of current sources for each column that cause a current to flow to each of the N first vertical signal lines, and the image sensor further includes a control unit that controls all of the plurality of current sources of the pixel array, and the control unit sets, for each column of the pixel array, a current source among the plurality of current sources that causes a current to flow to the first vertical signal line of a readout execution pixel group that is a pixel group consisting of the K or more pixels that output pixel signals, to a first active state, and sets the other current sources to a second active state in which the amount of current that flows is smaller than that in the first active state.

13. The pixel array further includes a plurality of current sources for each column that supply current to each of the N first vertical signal lines, and the imaging device further includes a control unit that controls all of the plurality of current sources included in the pixel array.

4. The image sensor according to claim 1, wherein the control unit, for each column of the pixel array, of the plurality of current sources, (1) activates a current source that causes a current to flow to the first vertical signal line of a readout pixel group that is a pixel group consisting of the K or more pixels that output pixel signals, (2) activates a current source that causes a current to flow to the first vertical signal line of a pre-readout pixel group that is a pixel group consisting of the K or more pixels that will output pixel signals after the K or more pixels of the readout execution pixel group, before the K or more pixels of the pre-readout pixel group start outputting pixel signals, and (3) inactivates current sources other than the current source that causes a current to flow to the first vertical signal line of the readout execution pixel group and the current source that causes a current to flow to the first vertical signal line of the pre-readout pixel group.

14. The image sensor according to any one of claims 1 to 3, wherein the pixel array further comprises, for each column, a plurality of current sources that pass current to power supply wiring connected to the K or more pixels included in each of the N pixel groups, and the image sensor further comprises a control unit that controls all of the plurality of current sources of the pixel array, and the control unit, for each column of the pixel array, activates, before the K or more pixels of the pre-readout pixel group start to output pixel signals, the current sources that pass current to the power supply wiring connected to the K or more pixels included in the pre-readout pixel group, which is a pixel group consisting of the K or more pixels that will output pixel signals next after the K or more pixels included in the readout execution pixel group, which is a pixel group consisting of the K or more pixels that output pixel signals, and inactivates other current sources other than the current sources that pass current to the power supply wiring connected to the K or more pixels included in the pre-readout pixel group.

15. The pixel array further includes a plurality of current sources for each column that pass a current to each of the N first vertical signal lines, and the image sensor further includes a control unit that controls all of the plurality of current sources of the pixel array, and the control unit, for each column of the pixel array, among the plurality of current sources, (1) activates a current source that passes a current to the first vertical signal line of a readout pixel group that is a pixel group consisting of the K or more pixels that output pixel signals, (2) continues to maintain in the active state a current source that passes a current to the first vertical signal line of a post-readout pixel group that is a pixel group consisting of the K or more pixels that output pixel signals immediately before the K or more pixels of the readout pixel group, for a certain period of time even after the K or more pixels included in the post-readout pixel group have finished outputting pixel signals, and (3) inactivates current sources other than the current source that passes a current to the first vertical signal line of the readout pixel group and the current source that passes a current to the first vertical signal line of the post-readout pixel group. The imaging device according to claim 1 .

16. The image sensor according to any one of claims 1 to 3, wherein the pixel array further comprises, for each column, a plurality of current sources that cause current to flow to power supply wiring connected to the K or more pixels included in each of the N pixel groups, and the image sensor further comprises a control unit that controls all of the plurality of current sources of the pixel array, and the control unit is configured to, for each column of the pixel array, continue to activate, for a certain period of time after the K or more pixels included in the post-read execution pixel group have finished outputting pixel signals, a current source that causes current to flow to the power supply wiring connected to the K or more pixels included in the post-read execution pixel group, the pixel group being made up of the K or more pixels that output pixel signals, and to inactivate, current sources other than the current source that causes current to flow to the power supply wiring connected to the K or more pixels included in the post-read execution pixel group.

17. The image sensor according to any one of claims 1 to 3, wherein N is an even number equal to or greater than 4, and the N pixel groups in each column of the pixel array include at least a first pixel group, a second pixel group, a third pixel group, and a fourth pixel group, and further comprising, for each column of the pixel array, a first switch that switches the first vertical signal line of the first pixel group and the first vertical signal line of the second pixel group between a conductive state and a non-conductive state, and a second switch that switches the first vertical signal line of the third pixel group and the first vertical signal line of the fourth pixel group between a conductive state and a non-conductive state.

18. K is an integer equal to or greater than 8, and L is an integer equal to or greater than 2 and equal to or less than K / 4, and each of the N pixel groups further includes: a third vertical signal line connected to L or more third pixels among the K or more pixels, the L or more third pixels being different from the L or more first pixels and the L or more second pixels; and a fourth vertical signal line connected to L or more fourth pixels among the K or more pixels, the L or more first pixels, the L or more second pixels, and the L or more fourth pixels being different from the L or more third pixels, and the image sensor further includes: a plurality of third impedance conversion circuits, for each column of the pixel array, having an output impedance lower than an input impedance, each of which receives as input a pixel signal output from at least one of the plurality of pixels; a plurality of fourth impedance conversion circuits having an output impedance lower than an input impedance, each of which receives as input a pixel signal output from at least one of the plurality of pixels; a third AD converter that performs AD conversion on the plurality of third impedance conversion signals output from the plurality of third impedance conversion circuits; and a fourth AD converter that performs AD conversion on the plurality of fourth impedance conversion signals output from the plurality of fourth impedance conversion circuits; and for each column of the pixel array and for each of the N pixel groups, a first switch that switches the first vertical signal line and the third vertical signal line between a conductive state and a non-conductive state, and a second switch that switches the second vertical signal line and the fourth vertical signal line between a conductive state and a non-conductive state, and for each column of the pixel array,4. The image sensor according to claim 3, wherein each of the N third vertical signal lines included in the N pixel groups is connected to an input of one of the plurality of third impedance conversion circuits, and an output of each of the plurality of third impedance conversion circuits is connected to the third AD converter; each of the N fourth vertical signal lines included in the N pixel groups is connected to an input of one of the plurality of fourth impedance conversion circuits, and an output of each of the plurality of fourth impedance conversion circuits is connected to the fourth AD converter; the photoelectric conversion units of the L or more first pixels and the photoelectric conversion units of the L or more third pixels receive light of a first color that has passed through a first color filter, and the photoelectric conversion units of the L or more second pixels and the photoelectric conversion units of the L or more fourth pixels receive light of a second color that is different from the first color and that has passed through a second color filter.

19. An imaging device comprising the imaging element according to any one of claims 1 to 3.

20. An imaging device comprising: a pixel array in which pixels having photoelectric conversion units that convert received light into electric charges are arranged in a matrix; a pixel group consisting of a plurality of the pixels in the pixel array; a vertical signal line connected to at least one of the plurality of pixels in the pixel group; an impedance conversion circuit connected to the vertical signal line and having an output impedance lower than its input impedance; and an AD converter connected to the impedance conversion circuit.

21. The image sensor according to claim 20, wherein there are a plurality of the impedance conversion circuits, the pixel array comprises, for each column, N (N is an integer of 2 or more) pixel groups each made up of a plurality of pixels connected to any one of M (M is an integer of 1 or more) vertical signal lines, and each of the N x M vertical signal lines of the N pixel groups is connected to an input of any one of the plurality of impedance conversion circuits.

22. The image sensor according to claim 21, further comprising a plurality of switches capable of alternatively selecting one of the M vertical signal lines provided in each of two or more mutually different pixel groups out of the N pixel groups, and each of the inputs of the plurality of impedance conversion circuits is connected to one of the plurality of switches.

23. An image sensor according to claim 21 or claim 22, wherein there are a plurality of AD converters, and each of the M vertical signal lines provided in each of P (P is an integer between 2 and N) pixel groups out of the N pixel groups is connected to one of the plurality of AD converters via one of the plurality of impedance conversion circuits.

24. An image sensor according to claim 21 or 22, wherein one vertical signal line of the M vertical signal lines provided in each of P pixel groups (P is an integer between 2 and N) out of the N pixel groups is connected to the common AD converter via one impedance conversion circuit out of the plurality of impedance conversion circuits, and the plurality of impedance conversion circuits have a function of setting the output to high impedance.

25. The image sensor according to claim 22, wherein there are a plurality of AD converters, and at least one of the output lines connecting any one of the plurality of impedance conversion circuits to any one of the plurality of AD converters overlaps, in a plan view, with at least one of the plurality of AD converters that is not connected to any one of the impedance conversion circuits.

26. The image sensor according to claim 22, wherein the AD converter is connected to one or more of the M vertical signal lines that overlap the AD converter in a planar view and one or more vertical signal lines that do not overlap the AD converter in a planar view.