Structure, quantum bit, quantum computing device and method for producing structure

Abstract

A method for producing a structure according to the present invention comprises: a step for forming an s-wave superconductor layer on a base material; a step for forming a first transition metal dichalcogenide layer, which contains a van der Waals layered substance, on the s-wave superconductor layer; and a step for forming a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer.

Description

Structure, quantum bit, quantum computing device, and method for manufacturing the structure

[0001] The present disclosure relates to structures, quantum bits, quantum processing devices, and methods for manufacturing structures.

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure that generates Majorana particles. WTe, a layered material of transition metal dichalcogenide, is one of the two-dimensional topological insulators. ２ A single layer film of WTe is used. ２ Research is also being conducted on higher-order topological insulator layers consisting of multilayers of

[0003] Japanese Patent Application Publication No. 2014 / 0174343 U.S. Patent No. 10,403,809 U.S. Patent Application Publication No. 2019 / 0131129 Japanese Patent Application Publication No. 2018-9201

[0004] N. Read and D. Green, Phys. Rev. B 61, 10267 (2000)V. Mourik et al., Science 336, 25 (2012)J. Alicea, Rep. Prog. Phys. 75, 076501 (2012)S. Wu et al., Science 359, 76 (2018)Y.-B. Choi et al. al., Nat. Mater 19, 974 (2020)LA Walsh et al., 2D Mater. 4, 025044 (2017)

[0005] Although theoretical proposals have been made so far, the crystallinity of WTe ２ It is not easy to stably obtain a transition metal dichalcogenide layer such as the above.

[0006] An object of the present disclosure is to provide a structure, a quantum bit, a quantum processing device, and a method for manufacturing the structure that enable good crystallinity to be obtained in a transition metal dichalcogenide layer.

[0007] According to one aspect of the present disclosure, there is provided a method for manufacturing a structure, the method including the steps of forming an s-wave superconductor layer on a substrate, forming a first transition metal dichalcogenide layer including a van der Waals layer material on the s-wave superconductor layer, and forming a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer.

[0008] According to the present disclosure, good crystallinity can be obtained in the transition metal dichalcogenide layer.

[0009] FIG. 1 is a cross-sectional view showing a structure according to the first embodiment. FIG. 2 is a cross-sectional view (part 1) showing a method for manufacturing a structure according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) showing a method for manufacturing a structure according to the first embodiment. FIG. 4 is a cross-sectional view (part 3) showing a method for manufacturing a structure according to the first embodiment. FIG. 5 is a cross-sectional view (part 4) showing a method for manufacturing a structure according to the first embodiment. FIG. 6 is a cross-sectional view (part 5) showing a method for manufacturing a structure according to the first embodiment. FIG. 7 is a diagram showing the results of STEM observation (part 1). FIG. 8 is a diagram showing the results of STEM observation (part 2). FIG. 9 is a diagram showing the results of Raman spectroscopy for the first embodiment. FIG. 10 is a top view showing a quantum bit according to the second embodiment. FIG. 11 is a cross-sectional view (part 1) showing a quantum bit according to the second embodiment. FIG. 12 is a cross-sectional view (part 2) showing a quantum bit according to the second embodiment. FIG. 13 is a perspective view showing a high-order topological insulator layer. FIG. 14 is a top view (part 1) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 15 is a top view (part 2) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 16 is a top view (part 3) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 17 is a top view (part 4) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 18 is a top view (part 5) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 19 is a top view (part 6) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 20 is a cross-sectional view (part 1) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 21 is a cross-sectional view (part 2) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 22 is a cross-sectional view (part 3) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 23 is a cross-sectional view (part 4) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 24 is a cross-sectional view (part 5) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 25 is a cross-sectional view (part 6) showing a method for manufacturing a quantum bit according to the second embodiment. FIG. 26 is a diagram showing a quantum processing device according to a third embodiment.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side referred to as the upper side and the Z2 side referred to as the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side.

[0011] First Embodiment First, a first embodiment will be described. The first embodiment relates to a structure. Fig. 1 is a cross-sectional view showing a structure according to the first embodiment.

[0012] The structure 100 according to the first embodiment includes a substrate 110, an s-wave superconductor layer 120, a first transition metal dichalcogenide layer 130, and a second transition metal dichalcogenide layer 140. The s-wave superconductor layer 120 is formed on the substrate 110. The first transition metal dichalcogenide layer 130 is formed on the s-wave superconductor layer 120. The second transition metal dichalcogenide layer 140 is formed on the first transition metal dichalcogenide layer 130.

[0013] The substrate 110 is, for example, a single crystal substrate with a surface Miller index of (100). The material of the substrate 110 is, for example, MgO. In the first embodiment, the substrate 110 is an example of a base material.

[0014] The s-wave superconductor layer 120 is, for example, an Nb layer whose surface has a Miller index of (100). The thickness of the s-wave superconductor layer 120 is, for example, about 40 nm.

[0015] The first transition metal dichalcogenide layer 130 includes a van der Waals layered material, which is a two-dimensional material. The van der Waals layered material is, for example, NbTe ２ The first transition metal dichalcogenide layer 130 is NbTe２ The first transition metal dichalcogenide layer 130 has a thickness of, for example, 1 nm to 5 nm.

[0016] The second transition metal dichalcogenide layer 140 is, for example, WTe ２ For example, the second transition metal dichalcogenide layer 140 is a two-dimensional material, WTe ２ The second transition metal dichalcogenide layer 140 has a thickness of, for example, 1 nm to 5 nm.

[0017] Next, a method for manufacturing the structure 100 according to the first embodiment will be described. Figures 2 to 6 are cross-sectional views showing the method for manufacturing the structure 100 according to the first embodiment. Here, a MgO single crystal substrate with Miller indices (100) is used as the substrate 110, a Nb layer is formed as the s-wave superconductor layer 120, and a NbTe layer is formed as the first transition metal dichalcogenide layer 130. ２ and forming a layer of WTe as the second transition metal dichalcogenide layer 140. ２ A multilayer film of the above will be formed.

[0018] First, as shown in FIG. 2, a substrate 110 (MgO single crystal substrate) is prepared, and the substrate 110 is annealed at approximately 1200°C for 3 to 4 hours in an oxygen atmosphere at atmospheric pressure. Next, the substrate 110 is immersed in methanol for 20 to 30 minutes, and then rinsed with ultrapure water. These treatments can improve the flatness of the surface of the substrate 110. For example, the surface of the substrate 110 will have atomic-level flatness.

[0019] 3, an s-wave superconductor layer 120 (Nb layer) is formed on the substrate 110. The s-wave superconductor layer 120 can be epitaxially grown by, for example, pulsed laser deposition (PLD). For example, the thickness of the s-wave superconductor layer 120 is set to about 40 nm.

[0020] When forming the s-wave superconductor layer 120 by the PLD method, the basic vacuum level is set to, for example, 5×10 －６The pressure is set to 100 Pa or less, and a KrF excimer laser (λ=248 nm) light source can be used as the laser light source. When forming the s-wave superconductor layer 120, for example, a Nb pure metal target can be used as the target. When forming the s-wave superconductor layer 120, for example, the temperature of the substrate 110 is maintained at about 950°C, and the laser energy density is set to 2.0 J / cm. ２ The irradiation frequency is 10 Hz, the distance between the substrate 110 and the target is about 5 cm, and the deposition rate is 1.0 nm / min. The Nb layer grows epitaxially on the substrate 110 maintained at about 950°C, while being oriented in the

[100] direction. After the epitaxial growth, post-annealing is preferably performed at 1100°C to 1200°C for 10 minutes. Post-annealing can improve the flatness of the surface of the s-wave superconductor layer 120. For example, the surface of the s-wave superconductor layer 120 will have atomic-level flatness.

[0021] 4, a chalcogen layer 131 is formed on the s-wave superconductor layer 120, and a metal layer 132 containing a transition metal is formed on the chalcogen layer 131. Here, a Te layer is formed as the chalcogen layer 131, and an Nb layer is formed as the metal layer 132. For example, the thickness of the chalcogen layer 131 is set to 20 nm, and the thickness of the metal layer 132 is set to 2 nm.

[0022] When forming the chalcogen layer 131 by the PLD method, the basic vacuum level is set to, for example, 5×10 －６ The pressure is set to 1 Pa or less, and a KrF excimer laser (λ=248 nm) light source can be used as the laser light source. When forming the chalcogen layer 131, for example, a Te pure metal target can be used as the target. When forming the chalcogen layer 131, for example, the temperature of the substrate 110 is kept at room temperature, and the laser energy density is set to 1.0 J / cm. ２ The irradiation frequency is 1 Hz, the distance between the substrate 110 and the target is about 5 cm, and the film formation rate is 10.0 nm / min.

[0023] When forming the metal layer 132 by the PLD method, the base vacuum level is set to, for example, 5×10 －６The pressure is set to 100 Pa or less, and a KrF excimer laser (λ=248 nm) light source can be used as the laser light source. When forming the metal layer 132, for example, a Nb pure metal target can be used as the target. When forming the metal layer 132, for example, the temperature of the substrate 110 is kept at room temperature, and the laser energy density is set to 2.0 J / cm. ２ The irradiation frequency is 10 Hz, the distance between the substrate 110 and the target is about 5 cm, and the film formation rate is 1.0 nm / min.

[0024] After the metal layer 132 is formed, post-annealing is performed at 250° C. to 350° C. for 1 hour. That is, the chalcogen layer 131 and the metal layer 132 are heated. As a result, as shown in FIG. 5, the Te contained in the chalcogen layer 131 and the Nb contained in the metal layer 132 are converted into NbTe, which is a van der Waals layered material. ２ is produced, and NbTe ２ A first transition metal dichalcogenide layer 130 (NbTe ２ A first transition metal dichalcogenide layer 130 is formed on the s-wave superconductor layer 120. The Nb contained in the s-wave superconductor layer 120 may also be used to form the first transition metal dichalcogenide layer 130. Furthermore, a portion of the chalcogen layer 131 may remain after the formation of the first transition metal dichalcogenide layer 130. Although the vapor pressure of Te is relatively low, the metal layer 132 formed on the chalcogen layer 131 functions as a cap layer, suppressing rapid evaporation of Te in the chalcogen layer 131 due to heating. The first transition metal dichalcogenide layer 130 is formed in a layered form on the s-wave superconductor layer 120, and the crystal structure of the first transition metal dichalcogenide layer 130 exhibits a 1T structure. The thickness of the first transition metal dichalcogenide layer 130 is, for example, 1 nm to 5 nm.

[0025] Next, as shown in FIG. 6, a second transition metal dichalcogenide layer 140 (WTe ２ The second transition metal dichalcogenide layer 140 can be epitaxially grown by, for example, the PLD method. For example, the thickness of the second transition metal dichalcogenide layer 140 is set to about 1 nm to 5 nm.

[0026] When forming the second transition metal dichalcogenide layer 140 by the PLD method, the base vacuum level is set to, for example, 5×10 －６ The pressure is set to 1 Pa or less, and a KrF excimer laser (λ=248 nm) light source can be used as the laser light source. ２ When forming the second transition metal dichalcogenide layer 140, for example, the temperature of the substrate 110 is maintained at about 325° C., and the laser energy density is set to 1.0 J / cm 2 . ２ The irradiation frequency is 10 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film formation rate is 1.0 nm / min. The second transition metal dichalcogenide layer 140 grows epitaxially on the first transition metal dichalcogenide layer 130. The crystal structure of the second transition metal dichalcogenide layer 140 exhibits a Td structure.

[0027] The s-wave superconductor layer 120 and the second transition metal dichalcogenide layer 140 can be epitaxially grown in situ in the same vacuum chamber, for example. The s-wave superconductor layer 120, the chalcogen layer 131, the metal layer 132, and the second transition metal dichalcogenide layer 140 can be formed by physical vapor deposition in a vacuum integrated process. The method for forming the s-wave superconductor layer 120, the chalcogen layer 131, the metal layer 132, and the second transition metal dichalcogenide layer 140 is not limited to PLD. For example, they may be formed by molecular beam epitaxy (MBE), sputtering, or evaporation.

[0028] In this manner, the structure 100 according to the first embodiment can be manufactured.

[0029] In the structure 100, the first transition metal dichalcogenide layer 130 functions as a seed layer when forming the second transition metal dichalcogenide layer 140. This allows the second transition metal dichalcogenide layer 140 to have good crystallinity. That is, in this embodiment, the first transition metal dichalcogenide layer 130 includes a van der Waals layered material, and the top surface of the first transition metal dichalcogenide layer 130 is an inactive surface with suppressed dangling bonds. This allows the second transition metal dichalcogenide layer 140 with good crystallinity to be grown heteroepitaxially.

[0030] After the second transition metal dichalcogenide layer 140 is formed, it is preferable to perform post-annealing at approximately 300° C. for 30 minutes to 1 hour. This is because the crystallinity of the second transition metal dichalcogenide layer 140 is improved.

[0031] Next, the results of scanning transmission electron microscope (STEM) observations of the first embodiment conducted by the inventors will be described. In this observation, a sample was prepared in accordance with the first embodiment, and STEM observations were performed on this sample. The first transition metal dichalcogenide layer 130 was made of three layers of NbTe ２ The second transition metal dichalcogenide layer 140 is a three-layer WTe ２ A laminated film of the above was formed. Figures 7 and 8 are diagrams showing the results of STEM observation. Figure 7 shows a wide-area image obtained by the high-angle annular dark field (HAADF) method, and Figure 8 shows a narrow-area image obtained by the high-resolution HAADF method. "Nb(100)" in Figures 7 and 8 indicates that the s-wave superconductor layer 120 is an Nb layer whose surface (upper surface) has Miller indices of (100).

[0032] As shown in Fig. 7, a second transition metal dichalcogenide layer 140 was observed, which was grown uniformly over at least several tens of nanometers in a plane parallel to the surface of the s-wave superconductor layer 120. Furthermore, as shown in Fig. 8, a first transition metal dichalcogenide layer 130 (NbTe) was observed, which was epitaxially grown in three layers on the s-wave superconductor layer 120.２ layer) and second transition metal dichalcogenide layer 140 (WTe ２ The contrast is different between the first transition metal dichalcogenide layer 130 and the second transition metal dichalcogenide layer 140. ２ thickness of 1 layer and 1 layer of WTe ２ The thickness of each is about 0.7 nm.

[0033] Next, the results of Raman spectroscopy measurements performed by the inventors on the first embodiment will be described. In this measurement, a sample (first sample) similar to the sample used in the STEM observation was prepared, and Raman spectroscopy measurements were performed on the first sample. In addition, second and third samples were also prepared, and Raman spectroscopy measurements were also performed on the second and third samples. The second sample was prepared using WTe contained in the second transition metal dichalcogenide layer 140. ２ The third sample has 12 layers of second transition metal dichalcogenide layers 140 (12 layers of WTe) on the s-wave superconductor layer 120 without forming the first transition metal dichalcogenide layers 130. ２ ) are formed. The other configurations of the second and third samples are the same as those of the first sample. FIG. 9 shows the results of Raman spectroscopy measurement for the first embodiment.

[0034] As shown in FIG. 9, in the first sample, WTe ２ A derived from １ ２ (213 cm －１ ) and A １ ５ (164cm －１ ) phonon modes, as well as NbTe ２ A derived from １ｇ (159cm －１ ) and E ｇ (103cm －１ ) phonon modes were also observed. In the second sample, the WTe ２ By increasing the number of layers, A １ ２ and A １ ５ On the other hand, in the third sample, the peak intensity of WTe ２Although there are many layers of A １ ２ and A １ ５ The peak intensity of was low. This result indicates that the crystallinity of the second transition metal dichalcogenide layer 140 in the third sample was lower than that in the second sample. From the above results, it can be said that the first transition metal dichalcogenide layer 130 contributes to improving the crystallinity of the second transition metal dichalcogenide layer 140.

[0035] Second Embodiment Next, a second embodiment will be described. The second embodiment relates to a quantum bit. The quantum bit according to the second embodiment is used in a quantum operation device such as a quantum computer. FIG. 10 is a top view showing a quantum bit according to the second embodiment. FIGS. 11 and 12 are cross-sectional views showing a quantum bit according to the second embodiment. FIG. 11 corresponds to a cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 corresponds to a cross-sectional view taken along line XII-XII in FIG. 10.

[0036] The quantum bit 1 according to the second embodiment includes a substrate 90, an s-wave superconductor layer 10, a transition metal dichalcogenide layer 70, a higher-order topological insulator layer 20, a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, and a third ferromagnetic insulator layer 33. The quantum bit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, and a third SQUID 63.

[0037] The substrate 90 is, for example, a single crystal substrate with a surface Miller index of (100). Materials for the substrate 90 include MgO, mica, sapphire, and SiC. The substrate 90 may also be a Si substrate with a thermal oxide film.

[0038] The s-wave superconductor layer 10 is provided on a portion of the surface of the substrate 90. The s-wave superconductor layer 10 is, for example, an Nb layer with a surface Miller index of (100). The thickness of the s-wave superconductor layer 10 is, for example, about 40 nm. The planar shape of the s-wave superconductor layer 10 is a rectangle with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction.

[0039] The transition metal dichalcogenide layer 70 is provided on the s-wave superconductor layer 10. The transition metal dichalcogenide layer 70 includes a van der Waals layered material, which is a two-dimensional material. The van der Waals layered material is, for example, NbTe ２ The transition metal dichalcogenide layer 70 is NbTe ２ The thickness of the transition metal dichalcogenide layer 70 is, for example, 2 nm. The transition metal dichalcogenide layer 70 is also an example of a first transition metal dichalcogenide layer.

[0040] The high-order topological insulator layer 20 is provided on the transition metal dichalcogenide layer 70. The high-order topological insulator layer 20 is, for example, WTe ２ For example, the high-order topological insulator layer 20 may be a two-dimensional material such as WTe ２ The thickness of the high-order topological insulator layer 20 is, for example, 10 nm. The high-order topological insulator layer 20 is also an example of a second transition metal dichalcogenide layer.

[0041] 13 is a perspective view showing a high-order topological insulator layer 20. The shape of the high-order topological insulator layer 20 is approximately a rectangular parallelepiped. The a-axis direction of the high-order topological insulator layer 20 is parallel to the Y1-Y2 direction, the b-axis direction is parallel to the X1-X2 direction, and the c-axis direction is parallel to the Z1-Z2 direction. The Miller indices of the top surface of the high-order topological insulator layer 20 are (001), the Miller indices of the side surface on the Y2 side are (100), and the Miller indices of the side surface on the X1 side are (010).

[0042] A groove 50 that is T-shaped in plan view is formed on the surface of the high-order topological insulator layer 20. The groove 50 includes a first groove 51, a second groove 52, and a third groove 53. For example, the widths of the first groove 51, the second groove 52, and the third groove 53 are 20 nm and 5 nm, respectively. The first groove 51 and the third groove 53 extend parallel to the X1-X2 direction, and the second groove 52 extends parallel to the Y1-Y2 direction. The first groove 51 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the X2-side end of the high-order topological insulator layer 20 to the center in the X1-X2 direction. The third groove 53 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the X1-side end of the high-order topological insulator layer 20 to the center in the X1-X2 direction. Therefore, the first groove 51 and the third groove 53 are formed in a straight line. The second groove 52 is provided near the center of the high-order topological insulator layer 20 in the X1-X2 direction, and extends from the Y1-side end to the center of the high-order topological insulator layer 20 in the Y1-Y2 direction. Therefore, the second groove 52 is perpendicular to the first groove 51 and the third groove 53.

[0043] The higher-order topological insulator layer 20 has a first region 21 on the Y2 side of the first groove 51 and the third groove 53. The higher-order topological insulator layer 20 has a second region 22 on the Y1 side of the first groove 51 and the X2 side of the second groove 52. The higher-order topological insulator layer 20 has a third region 23 on the Y1 side of the third groove 53 and the X1 side of the second groove 52.

[0044] The first region 21, the second region 22, and the third region 23 each have a hinge helical channel on one of two intersecting lines between a plane perpendicular to the a-axis direction and a plane perpendicular to the c-axis direction. The hinge helical channel is parallel to the b-axis direction. Specifically, the first region 21 has a first hinge helical channel 11 on the intersecting line (ridge line) between the top surface and the side surface on the Y1 side. The second region 22 has a second hinge helical channel 12 on the intersecting line between the side surface on the Y2 side and the bottom surface of the first groove 51. The third region 23 has a third hinge helical channel 13 on the intersecting line between the side surface on the Y2 side and the bottom surface of the third groove 53. The first hinge helical channel 11 may be located at the intersection of the Y1 side surface of the first region 21 and the bottom surface of the groove 50, the second hinge helical channel 12 may be located at the intersection of the top surface of the second region 22 and the Y2 side surface, and the third hinge helical channel 13 may be located at the intersection of the top surface of the third region 23 and the Y2 side surface.

[0045] The first ferromagnetic insulator layer 31 is provided on a portion of the first region 21, the second region 22, and the groove 50, and covers a portion of the first hinge helical channel 11 and the second hinge helical channel 12. The second ferromagnetic insulator layer 32 is provided on a portion of the second region 22, the third region 23, and the groove 50, and covers a portion of the second hinge helical channel 12 and the third hinge helical channel 13. The third ferromagnetic insulator layer 33 is provided on a portion of the third region 23, the first region 21, and the groove 50, and covers a portion of the third hinge helical channel 13 and the first hinge helical channel 11. The first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 may be made of Cr. ２ Ga ２ Te ６ The materials of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 may be other diluted magnetic semiconductors. The thicknesses of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 are, for example, about 30 nm.

[0046] The second ferromagnetic insulator layer 32 is spaced from the first ferromagnetic insulator layer 31 on the X1 side in the X1-X2 direction on the second hinge helical channel 12. The third ferromagnetic insulator layer 33 is spaced from the second ferromagnetic insulator layer 32 on the X1 side in the X1-X2 direction on the third hinge helical channel 13. The third ferromagnetic insulator layer 33 is spaced from the first ferromagnetic insulator layer 31 on the X1 side in the X1-X2 direction on the first hinge helical channel 11.

[0047] The first gate electrode 41 is provided on the first ferromagnetic insulator layer 31. The second gate electrode 42 is provided on the second ferromagnetic insulator layer 32. The third gate electrode 43 is provided on the third ferromagnetic insulator layer 33. The first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 may be made of Au. The thickness of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 is, for example, about 50 nm.

[0048] The first SQUID 61 has a lower superconductor layer 61A, a lower superconductor layer 61B, a tunnel barrier layer 61C, and an upper superconductor layer 61D.

[0049] The lower superconductor layer 61A and the lower superconductor layer 61B protrude toward the X2 side from the X2-side side surface of the s-wave superconductor layer 10. The lower superconductor layer 61A is located on the Y2 side of the lower superconductor layer 61B. In a plan view, the lower superconductor layer 61A protrudes toward the X2 side from the first region 21, and the lower superconductor layer 61B protrudes toward the X2 side from the second region 22. The lower superconductor layer 61A and the lower superconductor layer 61B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 61A and the lower superconductor layer 61B are connected to the s-wave superconductor layer 10. The lower superconductor layer 61A and the lower superconductor layer 61B are, for example, Nb layers with a thickness of about 40 nm.

[0050] The tunnel barrier layer 61C and the upper superconductor layer 61D have a U-shaped planar shape. The material of the tunnel barrier layer 61C is NbO ｘThe upper superconductor layer 61D may be made of Nb. The tunnel barrier layer 61C has a thickness of, for example, about 1 nm to 5 nm, and the upper superconductor layer 61D has a thickness of, for example, about 40 nm. One end of the tunnel barrier layer 61C contacts the lower superconductor layer 61A, and the other end of the tunnel barrier layer 61C contacts the lower superconductor layer 61B. The upper superconductor layer 61D is provided on the tunnel barrier layer 61C.

[0051] A tunnel barrier layer 61C is sandwiched between lower superconductor layer 61A and upper superconductor layer 61D, and between lower superconductor layer 61B and upper superconductor layer 61D. First SQUID 61 is configured with such Josephson junctions. First SQUID 61 detects changes in magnetic flux between first hinge helical channel 11 and second hinge helical channel 12.

[0052] The second SQUID 62 has a lower superconductor layer 62A, a lower superconductor layer 62B, a tunnel barrier layer 62C, and an upper superconductor layer 62D.

[0053] The lower superconductor layer 62A and the lower superconductor layer 62B protrude toward the Y1 side from the Y1-side side surface of the s-wave superconductor layer 10. The lower superconductor layer 62A is located on the X2 side of the lower superconductor layer 62B. In a plan view, the lower superconductor layer 62A protrudes toward the Y1 side from the second region 22, and the lower superconductor layer 62B protrudes toward the Y1 side from the third region 23. The lower superconductor layer 62A and the lower superconductor layer 62B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 62A and the lower superconductor layer 62B are connected to the s-wave superconductor layer 10. The lower superconductor layer 62A and the lower superconductor layer 62B are, for example, Nb layers with a thickness of about 40 nm.

[0054] The tunnel barrier layer 62C and the upper superconductor layer 62D have a U-shaped planar shape. The material of the tunnel barrier layer 62C is NbO ｘThe upper superconductor layer 62D may be made of Nb. The tunnel barrier layer 62C has a thickness of, for example, about 1 nm to 5 nm, and the upper superconductor layer 62D has a thickness of, for example, about 40 nm. One end of the tunnel barrier layer 62C contacts the lower superconductor layer 62A, and the other end of the tunnel barrier layer 62C contacts the lower superconductor layer 62B. The upper superconductor layer 62D is provided on the tunnel barrier layer 62C.

[0055] A tunnel barrier layer 62C is sandwiched between lower superconductor layer 62A and upper superconductor layer 62D, and between lower superconductor layer 62B and upper superconductor layer 62D. Second SQUID 62 is configured with such Josephson junctions. Second SQUID 62 detects changes in magnetic flux between second hinge helical channel 12 and third hinge helical channel 13.

[0056] The third SQUID 63 has a lower superconductor layer 63A, a lower superconductor layer 63B, a tunnel barrier layer 63C, and an upper superconductor layer 63D.

[0057] The lower superconductor layer 63A and the lower superconductor layer 63B protrude toward the X1 side from the X1-side side surface of the s-wave superconductor layer 10. The lower superconductor layer 63A is located closer to the Y1 side than the lower superconductor layer 63B. In a plan view, the lower superconductor layer 63A protrudes toward the X1 side from the third region 23, and the lower superconductor layer 63B protrudes toward the X1 side from the first region 21. The lower superconductor layer 63A and the lower superconductor layer 63B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layer 63A and the lower superconductor layer 63B are connected to the s-wave superconductor layer 10. The lower superconductor layer 63A and the lower superconductor layer 63B are, for example, Nb layers with a thickness of about 40 nm.

[0058] The tunnel barrier layer 63C and the upper superconductor layer 63D have a U-shaped planar shape. The material of the tunnel barrier layer 63C is NbO ｘThe upper superconductor layer 63D may be made of Nb. The tunnel barrier layer 63C has a thickness of, for example, about 1 nm to 5 nm, and the upper superconductor layer 63D has a thickness of, for example, about 40 nm. One end of the tunnel barrier layer 63C contacts the lower superconductor layer 63A, and the other end of the tunnel barrier layer 63C contacts the lower superconductor layer 63B. The upper superconductor layer 63D is provided on the tunnel barrier layer 63C.

[0059] Tunnel barrier layer 63C is sandwiched between lower superconductor layer 63A and upper superconductor layer 63D, and between lower superconductor layer 63B and upper superconductor layer 63D. Third SQUID 63 is configured with such Josephson junctions. Third SQUID 63 detects changes in magnetic flux between third hinge helical channel 13 and first hinge helical channel 11.

[0060] In the quantum bit 1 configured in this manner, four Majorana particles γ1, γ2, γ3, and γ4 are generated. For example, Majorana particle γ1 is stably generated near the first gate electrode 41 of the first hinge helical channel 11, and Majorana particle γ4 is stably generated near the third gate electrode 43 of the first hinge helical channel 11. Furthermore, for example, Majorana particle γ2 is stably generated between the first gate electrode 41 and the second gate electrode 42 of the second hinge helical channel 12, and Majorana particle γ3 is stably generated between the second gate electrode 42 and the third gate electrode 43 of the third hinge helical channel 13. The Majorana particles γ1 to γ4 are exchanged by a change in electrostatic potential accompanying the application of gate voltages to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.

[0061] For example, in the exchange between Majorana fermions γ1 and γ2, an electric field is applied from the first gate electrode 41, and a minute change in magnetic flux during the exchange between Majorana fermions γ1 and γ2 is detected as a minute change in a voltage signal by the first SQUID 61. In the exchange between Majorana fermions γ2 and γ3, an electric field is applied from the second gate electrode 42, and a minute change in magnetic flux during the exchange between Majorana fermions γ2 and γ3 is detected as a minute change in a voltage signal by the second SQUID 62. In addition, in the exchange between Majorana fermions γ3 and γ4, an electric field is applied from the third gate electrode 43, and a minute change in magnetic flux during the exchange between Majorana fermions γ3 and γ4 is detected as a minute change in a voltage signal by the third SQUID 63.

[0062] WTe, a layered transition metal dichalcogenide material ２ The monolayer film of WTe is easily oxidized and its properties change when exposed to the atmosphere. ２ It is possible to suppress oxidation by sandwiching the monolayer film between chemically stable materials such as hexagonal boron nitride (h-BN) or graphene, but this makes the manufacturing process of the quantum bit more complicated. ２ In contrast, in this embodiment, it is difficult to adjust the size of the monolayer film of WTe ２ Since the high-order topological insulator layer 20 including a multilayer film such as WTe is used, a structure for suppressing oxidation is not required. ２ This is easier than adjusting the size of the monolayer membrane.

[0063] It is also possible to provide multiple quantum bits 1 on the substrate 90 to achieve a multi-qubit configuration, or to mount a semiconductor integrated circuit on the substrate 90. Therefore, according to this embodiment, it is possible to accelerate research and development toward realizing a practical error-tolerant quantum computer.

[0064] Next, a method for manufacturing the quantum bit 1 according to the second embodiment will be described. Figures 14 to 19 are top views showing the method for manufacturing the quantum bit 1 according to the second embodiment. Figures 20 to 25 are cross-sectional views showing the method for manufacturing the quantum bit 1 according to the second embodiment.

[0065] First, as shown in Figures 14 and 20, a substrate 90 is prepared and annealed at approximately 1200°C for 3 to 4 hours in an oxygen atmosphere at atmospheric pressure. Next, the substrate 90 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These treatments can improve the flatness of the surface of the substrate 90. Figure 20 corresponds to a cross-sectional view taken along line XX-XX in Figure 14.

[0066] Thereafter, an s-wave superconductor layer 19 is formed on the substrate 90, a first transition metal dichalcogenide layer 79 is formed on the s-wave superconductor layer 19, and a higher-order topological insulator layer 29 is formed on the first transition metal dichalcogenide layer 79. For example, a Nb layer is formed as the s-wave superconductor layer 19, and a NbTe layer is formed as the first transition metal dichalcogenide layer 79. ２ A layer is formed, and a WTe ２ The s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 can be formed by the same methods as those for the s-wave superconductor layer 120, the first transition metal dichalcogenide layer 130, and the second transition metal dichalcogenide layer 140 in the first embodiment, respectively.

[0067] After the formation of the higher-order topological insulator layer 29, the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 are processed to form the s-wave superconductor layer 19 into the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B, as shown in Figures 15 and 21. Figure 21 corresponds to a cross-sectional view taken along line XXI-XXI in Figure 15.

[0068] When processing the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29, a first electron beam resist is first spin-coated onto the higher-order topological insulator layer 29. Next, a first mask pattern is formed from the first electron beam resist by electron beam lithography. The first mask pattern covers the portions of the s-wave superconductor layer 19 where the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B are to be formed, from above the higher-order topological insulator layer 29, and leaves the other portions exposed. As the first electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used. After the first mask pattern is formed, Ar ion milling is performed to process the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29. In the Ar ion milling, for example, the beam acceleration voltage is set to 280 V and the beam current is set to 150 mA.

[0069] After processing the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29, the first mask pattern is removed. As shown in Figures 16 and 22, the higher-order topological insulator layer 29 and the first transition metal dichalcogenide layer 79 are processed to form a higher-order topological insulator layer 29A having a rectangular planar shape and a flat upper surface from the higher-order topological insulator layer 29, and a transition metal dichalcogenide layer 70 having a rectangular planar shape from the first transition metal dichalcogenide layer 79. Figure 22 corresponds to a cross-sectional view taken along line XXII-XXII in Figure 16.

[0070] When processing the higher-order topological insulator layer 29 and the first transition metal dichalcogenide layer 79, a second electron beam resist is first spin-coated onto the higher-order topological insulator layer 29 and the substrate 90. Next, a second mask pattern is formed from the second electron beam resist by electron beam lithography. The second mask pattern covers the portion of the higher-order topological insulator layer 29 above the s-wave superconductor layer 10 and exposes the portions above the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. For example, a resist prepared by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used as the second electron beam resist. After forming the second mask pattern, the higher-order topological insulator layer 29 and the first transition metal dichalcogenide layer 79 are processed by Ar ion milling. As a result, the higher-order topological insulator layer 29A and the transition metal dichalcogenide layer 70 are formed, and the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B are exposed from the higher-order topological insulator layer 29A and the transition metal dichalcogenide layer 70. In the Ar ion milling, for example, the beam acceleration voltage is 280 V and the beam current is 150 mA.

[0071] After the formation of the higher-order topological insulator layer 29A and the transition metal dichalcogenide layer 70, the second mask pattern is removed, and the higher-order topological insulator layer 29A is processed to form a higher-order topological insulator layer 20 including a first region 21, a second region 22, and a third region 23 from the higher-order topological insulator layer 29A, as shown in Figures 17 and 23. Figure 23 corresponds to a cross-sectional view taken along line XXIII-XXIII in Figure 17.

[0072] When processing the higher-order topological insulator layer 29A, a third electron beam resist is first spin-coated onto the higher-order topological insulator layer 29A, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a third mask pattern is formed from the third electron beam resist by electron beam lithography. The third mask pattern exposes the portions of the higher-order topological insulator layer 29A where the grooves 50 are to be formed and covers the other portions. For example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used as the third electron beam resist. After forming the third mask pattern, the higher-order topological insulator layer 29A is processed by Ar ion milling. As a result, a groove 50 including a first groove 51, a second groove 52, and a third groove 53 is formed, and a high-order topological insulator layer 20 including a first region 21, a second region 22, and a third region 23 is obtained. The first region 21 includes a first hinge helical channel 11, the second region 22 includes a second hinge helical channel 12, and the third region 23 includes a third hinge helical channel 13 (see FIG. 13 ). In Ar ion milling, for example, the beam acceleration voltage is 280 V and the beam current is 150 mA.

[0073] After the formation of the higher-order topological insulator layer 20, the third mask pattern is removed, and the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are formed as shown in Figures 18 and 24. Figure 24 corresponds to a cross-sectional view taken along line XXIV-XXIV in Figure 18.

[0074] When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43, a fourth electron beam resist is first spin-coated on the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a fourth mask pattern is formed from the fourth electron beam resist by electron beam lithography. The fourth mask pattern exposes portions where the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are to be formed, and covers other portions. As the fourth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used. After forming the fourth mask pattern, Cr ２ Ga ２ Te ６ A layer and an Au layer are formed.

[0075] Cr ２ Ga ２ Te ６ When forming the layer by the PLD method, for example, the temperature of the substrate 90 is maintained at 200° C., and the laser energy density is 1.0 J / cm ２ ~2.0 J / cm ２ The irradiation frequency is 1 Hz, the distance between the substrate 90 and the target is about 5 cm, and the film formation rate is 1.0 nm / min to 2.0 nm / min.

[0076] When the Au layer is formed by the PLD method, for example, the temperature of the substrate 90 is kept at room temperature, and the laser energy density is set to 1.0 J / cm ２ ~2.0 J / cm ２ The irradiation frequency is set to 5 Hz, the distance between the substrate 90 and the target is set to about 5 cm, and the film formation rate is set to 5.0 nm / min to 10.0 nm / min.

[0077] Cr ２ Ga ２ Te ６ After the formation of the Au layer and the Cr layer, a fourth mask pattern is formed on the Cr layer.２ Ga ２ Te ６ The first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are obtained. Furthermore, four Majorana particles γ1, γ2, γ3, and γ4 are generated.

[0078] Next, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are formed as shown in Figures 19 and 25. Figure 25 corresponds to a cross-sectional view taken along line XXV-XXV in Figure 19.

[0079] When forming the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D, a fifth electron beam resist is first spin-coated onto the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, the lower superconductor layer 63B, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. Next, a fifth mask pattern is formed from the fifth electron beam resist by electron beam lithography. The fifth mask pattern exposes the portions where the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D will be formed and covers the other portions. For example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used as the fifth electron beam resist. After forming the fifth mask pattern, NbO ｘ A layer and an Nb layer are formed.

[0080] NbO ｘ When forming the layer by the PLD method, for example, a Nb metal target is used, the temperature of the substrate 90 is maintained at room temperature, and the oxygen partial pressure in the vacuum chamber is adjusted to about 50 Pa to 55 Pa. The Nb layer can be formed under the same conditions as those for the s-wave superconductor layer 19.

[0081] NbO ｘ After the formation of the Nb layer and the Nb layer, a fifth mask pattern is formed on the NbO ｘThe Nb layer and the Nb layer are removed together, that is, lift-off is performed. As a result, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are obtained, and the first SQUID 61, the second SQUID 62, and the third SQUID 63 are formed.

[0082] In this manner, the quantum bit 1 according to the second embodiment can be manufactured.

[0083] In the present disclosure, the material of the s-wave superconductor layer is not limited to Nb. The material of the s-wave superconductor layer may be Pb. The material of the chalcogen layer is not limited to Te. The material of the chalcogen layer may be S or Se. The material of the chalcogen layer may be the same as the chalcogen element contained in the second transition metal dichalcogenide layer. The material of the metal layer is not limited to Nb. The material of the metal layer may be Pb. The transition metal contained in the s-wave superconductor layer and the transition metal contained in the metal layer are preferably the same, but may be different. If the transition metal contained in the s-wave superconductor layer and the transition metal contained in the metal layer are the same, the first transition metal dichalcogenide layer is likely to contain one type of transition metal dichalcogenide. On the other hand, if the transition metal contained in the s-wave superconductor layer and the transition metal contained in the metal layer are different, the first transition metal dichalcogenide layer may contain two or more types of transition metal dichalcogenides. Even if the first transition metal dichalcogenide layer contains two or more types of transition metal dichalcogenides, the second transition metal dichalcogenide layer can have good crystallinity. The chalcogen elements contained in the first transition metal dichalcogenide layer and the chalcogen elements contained in the second transition metal dichalcogenide layer may be the same type.

[0084] In this disclosure, the material of the second transition metal dichalcogenide layer (including the higher-order topological insulator layer) is WTe ２ The second transition metal dichalcogenide layer may contain, as a transition metal, Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt, or any combination thereof. The layered material contained in the second transition metal dichalcogenide layer may be a single layer.

[0085] Third Embodiment Next, a third embodiment will be described. The third embodiment relates to a quantum processing device including the quantum bit 1 according to the second embodiment. Fig. 26 is a diagram showing a quantum processing device according to the third embodiment.

[0086] As shown in FIG. 26 , the quantum processing device 2 according to the third embodiment has a quantum bit chip 81, a signal generator 82, a signal demodulator 83, and a cryogenic dilution refrigerator 84. The quantum bit chip 81 includes a plurality of quantum bits 1 according to the second embodiment. The quantum bit chip 81 is housed in a cryogenic dilution refrigerator 84 and cooled to a temperature of 10 mK or less. The signal generator 82 generates a microwave pulse signal, and the microwave pulse signal is input to the quantum bit chip 81. The quantum bit chip 81 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 83 demodulates the signal output from the quantum bit chip 81. The signal generator 82 and the signal demodulator 83 are used at a temperature of, for example, about room temperature.

[0087] Since the quantum processing device 2 according to the third embodiment includes the quantum bit 1 according to the second embodiment, it is possible to stably generate Majorana particles and perform stable operations.

[0088] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0089] 1: Quantum bit 2: Quantum processing device 10: s-wave superconductor layer 11: First hinged helical channel 12: Second hinged helical channel 13: Third hinged helical channel 20: Higher-order topological insulator layer 21: First region 22: Second region 23: Third region 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate electrode 42: Second gate electrode 43: Third gate electrode 50: Groove 51: First groove 52: Second groove 53: Third groove 61: First SQUID 62: Second SQUID 63: Third SQUID 70: Transition metal dichalcogenide layer 100: Structure 110: Substrate 120: s-wave superconductor layer 130: First transition metal dichalcogenide layer 131: Chalcogen layer 132: Metal layer 140: Second transition metal dichalcogenide layer

Claims

1. forming an s-wave superconductor layer on a substrate; forming a first transition metal dichalcogenide layer including a van der Waals layer material on the s-wave superconductor layer; forming a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer; A method for producing a structure comprising the steps of:

2. 2. The method for producing a structure according to claim 1, wherein the second transition metal dichalcogenide layer is a high-order topological insulator layer including a plurality of transition metal dichalcogenides stacked on the first transition metal dichalcogenide layer.

3. The step of forming the first transition metal dichalcogenide layer includes: forming a chalcogen layer on the s-wave superconductor layer; forming a metal layer containing a transition metal on the chalcogen layer; heating the chalcogen layer and the metal layer; 3. The method for producing a structure according to claim 1, further comprising the steps of:

4. 4. The method for producing a structure according to claim 3, wherein the chalcogen layer contains S, Se, or Te, or any combination thereof.

5. 4. The method for manufacturing a structure according to claim 3, wherein the s-wave superconductor layer is made of the same transition metal as that contained in the metal layer.

6. A substrate; an s-wave superconductor layer provided on the substrate; a first transition metal dichalcogenide layer comprising a van der Waals layered material disposed on the s-wave superconductor layer; a second transition metal dichalcogenide layer provided on the first transition metal dichalcogenide layer; A structure comprising:

7. 7. The structure of claim 6, wherein the second transition metal dichalcogenide layer is a higher-order topological insulator layer including a plurality of transition metal dichalcogenides stacked on the first transition metal dichalcogenide layer.

8. 8. The structure of claim 6 or 7, wherein the first transition metal dichalcogenide layer comprises S, Se, or Te, or any combination thereof.

9. 8. The method for manufacturing a structure according to claim 6, wherein the s-wave superconductor layer is made of the same transition metal as that contained in the first transition metal dichalcogenide layer.

10. an s-wave superconductor layer; a transition metal dichalcogenide layer including a van der Waals layered material disposed on the s-wave superconductor layer; a high-order topological insulator layer disposed on the transition metal dichalcogenide layer; a first ferromagnetic insulator layer disposed on the highly ordered topological insulator layer; a first gate electrode provided on the first ferromagnetic insulator layer; having The high-order topological insulator layer is a first region having a first hinge helical channel; a second region having a second hinged helical channel spaced from the first hinged helical channel; having The first ferromagnetic insulator layer covers the first hinged helical channel and the second hinged helical channel.

11. 11. The quantum bit of claim 10, further comprising a first superconducting quantum interferometer that detects changes in magnetic flux between the first hinged helical channel and the second hinged helical channel.

12. the higher-order topological insulator layer has a third region with a third hinged helical channel spaced from the first hinged helical channel and the second hinged helical channel; a second ferromagnetic insulator layer covering the second hinge helical channel and the third hinge helical channel; a second gate electrode provided on the second ferromagnetic insulator layer; a third ferromagnetic insulator layer covering the third hinge helical channel and the first hinge helical channel; a third gate electrode provided on the third ferromagnetic insulator layer; 12. The quantum bit of claim 10 or 11, comprising:

13. A second superconducting quantum interference detector; a third superconducting quantum interference detector; having a second superconducting quantum interferometer for detecting a change in magnetic flux between the second hinged helical channel and the third hinged helical channel; 13. The qubit of claim 12, wherein a third superconducting quantum interferometer detects changes in magnetic flux between the third hinged helical channel and the first hinged helical channel.

14. The high-order topological insulator layer is a first groove defining the first region and the second region; a second groove defining the second region and the third region; a third groove defining the third region and the first region; 13. The quantum bit of claim 12, wherein

15. The first groove and the third groove extend in a common first direction, The second groove extends in a second direction perpendicular to the first direction, 15. The quantum bit of claim 14, wherein the first groove, the second groove, and the third groove are connected.

16. A quantum computing device comprising the quantum bit according to claim 10 or 11.