Semiconductor device and electronic apparatus

Abstract

Provided is a semiconductor device that demonstrates fast access speed. This semiconductor device has a first storage layer, a second storage layer, and a circuit layer. The first storage layer has a plurality of first storage circuits, the second storage layer has a second storage circuit, and the circuit layer has a selector. The selector has a plurality of input terminals and an output terminal. The first storage layer is positioned below the circuit layer, and the second storage layer is positioned above the circuit layer. The plurality of first storage circuits are electrically connected to the plurality of input terminals, and the second storage circuit is electrically connected to the output terminal. The selector has a function of enabling conduction between one selected from the plurality of input terminals, and the output terminal of the selector. The semiconductor device has a function for writing data read out from the second storage circuit to the first storage circuit via the selector.

Description

Semiconductor devices and electronic devices

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and testing methods thereof.

[0003] In recent years, with the increase in the amount of data handled, there has been a demand for memory devices with larger storage capacities. In order to increase the storage capacity per unit area, it is effective to form memory cells by stacking them, as in 3D NAND type memory devices (see Patent Documents 1 to 3). By stacking memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells.

[0004] US Patent Application Publication No. 2011 / 0065270 US Patent Application Publication No. 2016 / 0149004 US Patent Application Publication No. 2013 / 0069052

[0005] Storage devices used as cache memories, main memories, etc. of computers are required to have a short access time, in other words, fast write and read speeds, etc. For example, the access times (sometimes called delay times or latencies) of SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are approximately several nanoseconds to several tens of nanoseconds, and therefore are used as cache memories, main memories, etc. of computers.

[0006] Incidentally, storage devices located higher in the memory hierarchy, such as registers and cache memories provided in processors such as CPUs (Central Processing Units), have smaller storage capacities than storage devices located lower in the memory hierarchy, so there are times when necessary data is not stored in the registers or cache memories (this is sometimes called a cache miss). When a cache miss occurs, the processor accesses storage devices located lower in the memory hierarchy to obtain the necessary data (this is sometimes called a cache miss penalty). Data is exchanged between the processor and storage devices located lower in the memory hierarchy via bus wiring. Note that the access speed from the CPU to storage devices located lower in the memory hierarchy via the bus wiring is slow, which is likely to affect the processor's operating speed.

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with high access speed.An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with a small circuit area.An object of one embodiment of the present invention is to provide an electronic device including the above-described semiconductor device.An object of one embodiment of the present invention is to provide a novel semiconductor device or a novel electronic device.

[0008] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems.

[0009] (1) One embodiment of the present invention is a semiconductor device including a first memory layer, a second memory layer, and a circuit layer. The first memory layer includes a plurality of first memory circuits, the second memory layer includes a second memory circuit, and the circuit layer includes a selector. The selector includes a plurality of input terminals and an output terminal. The first memory layer is located below the circuit layer, and the second memory layer is located above the circuit layer. Each of the plurality of first memory circuits is electrically connected to a plurality of input terminals, and the second memory circuit is electrically connected to an output terminal. The selector has a function of establishing electrical continuity between one selected from the plurality of input terminals and the output terminal. The semiconductor device also has a function of writing data read from the second memory circuit to the first memory circuit via the selector.

[0010] (2) Alternatively, in one embodiment of the present invention, the semiconductor device according to (1) may have a structure including a semiconductor substrate containing silicon. In particular, the first memory layer is preferably located on the semiconductor substrate, and the first memory circuit preferably includes a first transistor. Note that the first transistor has silicon in a channel formation region.

[0011] (3) In another embodiment of the present invention, in the above-described (2), the second memory circuit may include a second transistor. In particular, the second transistor preferably includes a metal oxide in a channel formation region.

[0012] The metal oxide contains one or more elements selected from indium, zinc, and an element M. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

[0013] (4) Alternatively, in one aspect of the present invention, in the above (3), the data may be any one of 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, and 256 bits.

[0014] (5) Alternatively, in one embodiment of the present invention, in the above-described (4), the first memory circuit and the second memory circuit may not be connected to each other through a system bus.

[0015] (6) One embodiment of the present invention is a semiconductor device including a first memory layer, a second memory layer, and a circuit layer. The first memory layer includes a plurality of first memory circuits, the second memory layer includes a second memory circuit, and the circuit layer includes a selector. The second memory circuit includes a capacitor and a second transistor. The capacitor includes a first conductor, a second conductor, a first insulator, and a second insulator, and the second transistor includes a second conductor, a third conductor, a fourth conductor, a third insulator, a fourth insulator, and a metal oxide. The selector includes a plurality of input terminals and an output terminal. The first memory layer is located below the circuit layer, and the second memory layer is located above the circuit layer.

[0016] The first insulator has a first opening. The first conductor is located on the side and bottom surfaces of the first opening and on the top surface of the first insulator. The second insulator is located on the top surface of the first insulator and on the top surface of the first conductor. The second conductor is located on a region of the top surface of the second insulator that overlaps with the first conductor. The third insulator is located on the top surface of the second conductor, and the third conductor is located on the top surface of the third insulator. The third insulator and the third conductor have a second opening. The metal oxide is located on the side surface of the second opening and on the top surface of the second conductor and the top surface of the third conductor. The fourth insulator is located on the top surface of the metal oxide and on the top surface of the third conductor. The fourth conductor is located on the top surface of the metal oxide and on the top surface of the third conductor. The fourth conductor is located on a region of the top surface of the fourth insulator that overlaps with the metal oxide.

[0017] The plurality of first memory circuits are electrically connected to a plurality of input terminals, and the third conductor is electrically connected to an output terminal. The selector has a function of establishing electrical continuity between a selected one of the plurality of input terminals and the output terminal. The semiconductor device also has a function of writing data read from the second memory circuit to the first memory circuit via the selector.

[0018] (7) Alternatively, in one embodiment of the present invention, in the above-described (6), the metal oxide may contain one or more elements selected from indium, zinc, and an element M.

[0019] The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

[0020] (8) Alternatively, in one embodiment of the present invention, the semiconductor device according to (7) may have a structure including a semiconductor substrate containing silicon. In particular, the first memory layer is preferably located on the semiconductor substrate, and the first memory circuit preferably includes a first transistor. Note that the first transistor has silicon in a channel formation region.

[0021] (9) Alternatively, in one aspect of the present invention, in the above (8), the second insulator may have an oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium.

[0022] (10) Alternatively, in one aspect of the present invention, in the above (9), the data may be any one of 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, and 256 bits.

[0023] (11) Alternatively, according to one embodiment of the present invention, in the above-described (10), the first memory circuit and the second memory circuit may not be connected to each other through a system bus.

[0024] (12) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (1) to (11) above and a housing.

[0025] According to one embodiment of the present invention, a semiconductor device with high access speed can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with a small circuit area can be provided. According to one embodiment of the present invention, an electronic device including the semiconductor device described above can be provided. According to one embodiment of the present invention, a novel semiconductor device or a novel electronic device can be provided.

[0026] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0027] FIG. 1A is a schematic perspective view showing an example of the configuration of a semiconductor device, and FIG. 1B is a block diagram showing an example of the configuration of the semiconductor device. FIG. 2 is a conceptual diagram explaining a memory hierarchy in which multiple memory devices provided in a computer are associated. FIG. 3 is a schematic perspective view showing an example of the configuration of a semiconductor device. FIG. 4 is a schematic perspective view showing an example of the configuration of a semiconductor device. FIG. 5 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 6 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 7 is a circuit diagram showing an example of the configuration of a semiconductor device. FIGS. 8A and 8B are circuit diagrams showing an example of the configuration of a semiconductor device. FIG. 9 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 11 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 12 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 13 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 14 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 15 is a schematic perspective view explaining an example of the configuration of a memory device. FIG. 16 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 17 is a block diagram showing an example of the configuration of a memory circuit provided in a semiconductor device. FIGS. 18A to 18E are circuit diagrams showing example configurations of memory cells provided in a semiconductor device. 19A to 19C are circuit diagrams showing an example of the configuration of a memory cell included in a semiconductor device. FIGS. 20A and 20B are circuit diagrams showing an example of the configuration of a memory cell included in a semiconductor device. FIG. 21 is a schematic cross-sectional view illustrating an example of the configuration of a semiconductor device. FIG. 22 is a schematic cross-sectional view illustrating an example of the configuration of a semiconductor device. FIGS. 23A and 23B are schematic cross-sectional views illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 24 is a schematic cross-sectional view illustrating an example of the configuration of a transistor included in a semiconductor device. FIG. 25 is a schematic cross-sectional view illustrating an example of the configuration of a capacitive element included in a semiconductor device. FIG. 26 is a schematic cross-sectional view illustrating an example of the configuration of a semiconductor device. FIGS. 27A to 27C are plan views showing an example of the configuration of a transistor included in a semiconductor device, and FIG. 27D is a cross-sectional view showing an example of the configuration of a transistor included in a semiconductor device. FIG. 28A is a plan view showing an example of the configuration of a transistor included in a semiconductor device, and FIG. 28B is a cross-sectional view showing an example of the configuration of a transistor included in a semiconductor device.29A and 29B are diagrams showing an example of an electronic component. FIGS. 30A and 30B are diagrams showing an example of an electronic device, and FIGS. 30C to 30E are diagrams showing an example of a mainframe computer. FIG. 31 is a diagram showing an example of space equipment. FIG. 32 is a diagram showing an example of a storage system applicable to a data center. FIG. 33A is a schematic perspective view showing an example of the configuration of a display device, and FIG. 33B is a block diagram showing an example of the configuration of the display device. FIG. 34 is a circuit diagram showing an example of the configuration of a pixel circuit included in the display device. FIG. 35 is a schematic perspective view showing an example of the configuration of a stacked structure included in the display device. FIGS. 36A to 36I are perspective views showing an example of an electronic device.

[0028] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are all examples of a semiconductor device. Furthermore, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0029] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film or a layer).

[0030] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0031] Note that when both an element and a power supply line (for example, VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or a wiring that provides a desired potential) are arranged between X and Y, it is not specified that X and Y are electrically connected. Note that when only a power supply line is arranged between X and Y, there is no other element between X and Y, so X and Y are directly connected. Therefore, when only a power supply line is arranged between X and Y, it can also be said that "X and Y are electrically connected." However, when both an element and a power supply line are arranged between X and Y, it can be said that X and the power supply line are electrically connected (via the element) and Y and the power supply line are electrically connected, but it is not specified that X and Y are electrically connected. Note that when the gate and source of a transistor are connected between X and Y, it is not specified that X and Y are electrically connected. Note that when the gate and drain of a transistor are connected between X and Y, it is not specified that X and Y are electrically connected. That is, in the case of a transistor, if there is a connection between X and Y via the drain and source of the transistor, it is defined that X and Y are electrically connected. Note that if a capacitive element is disposed between X and Y, it may or may not be defined that X and Y are electrically connected. For example, in the configuration of a digital circuit or logic circuit, if a capacitive element is disposed between X and Y, it may not be defined that X and Y are electrically connected. On the other hand, for example, in the configuration of an analog circuit, if a capacitive element is disposed between X and Y, it may be defined that X and Y are electrically connected.

[0032] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (for example, inverters, NAND circuits, and NOR circuits), signal conversion circuits (for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (for example, power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (for example, circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0033] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0034] For example, the term "X, Y, the source (sometimes referred to as either the first terminal or the second terminal) and the drain (sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Alternatively, the term "the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Alternatively, the term "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are connected in this order." Using a similar expression to these examples, the order of connections in the circuit configuration can be specified to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expression methods are merely examples and are not limiting. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0035] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has both the function of a wiring and the function of an electrode. Therefore, in this specification, the term "electrically connected" also includes such a case where one conductive film has the functions of multiple components.

[0036] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0037] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," and "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0038] Furthermore, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification.

[0039] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0040] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0041] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. Also, a terminal, a wiring, etc. can be referred to as a node.

[0042] Furthermore, in this specification and the like, a selector may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, a selector may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, a selector may refer to a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, a selector may refer to a multiplexer or a demultiplexer.

[0043] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0044] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0045] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0046] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0047] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0048] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not necessarily mean that electrode B is formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not necessarily mean that electrode B is formed in direct contact with below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0049] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0050] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation, the terms "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be interchanged with the term "insulator."

[0051] Furthermore, the terms "electrode," "wiring," and "terminal" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0052] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." The term "potential" applied to wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0053] In addition, timing charts may be used in this specification and the like to explain an operation method of a semiconductor device. The timing charts used in this specification and the like illustrate ideal operation examples, and the periods, magnitudes of signals (e.g., potentials or currents), and timings described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification and the like can be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as being long and the other period is shown as being short, the lengths of the two periods may be equal, or one period may be short and the other period may be long.

[0054] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0055] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0056] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0057] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0058] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0059] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls conduction and non-conduction.

[0060] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0061] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0062] In addition, the content (or even a part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even a part of the content) described in that embodiment and one or more other content (or even a part of the content) described in another embodiment.

[0063] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0064] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0065] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0066] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0067] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0068] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0069] First, the concept of a memory hierarchy that associates various storage devices provided in a computer will be explained. Figure 2 shows an example of such a memory hierarchy. The memory hierarchy 100 shown in Figure 2 includes a register 101, a first cache memory 102, a second cache memory 103, a main memory 104, and an auxiliary storage device 105.

[0070] The register 101 is a storage device included in a processor such as a CPU or a GPU (Graphics Processing Unit). The register 101 has a function of temporarily storing input data to an arithmetic circuit included in the processor and output data calculated by the arithmetic circuit. The register 101 may also have a function of temporarily storing not only data related to the arithmetic circuit but also data related to a control device included in the processor.

[0071] The register 101 includes, for example, a flip-flop circuit.

[0072] The first cache memory 102 is, for example, a storage device located between the register 101 and the main memory 104 in the memory hierarchy 100, and has the function of storing data that is frequently accessed by the CPU. The first cache memory 102 is generally sometimes called a primary cache memory.

[0073] The second cache memory 103 is, for example, a storage device located between the register 101 and the main memory 104 in the memory hierarchy 100, and has the function of storing data that is accessed most frequently by the CPU, next to the first cache memory 102. The second cache memory 103 is generally sometimes called a secondary cache memory.

[0074] The first cache memory 102 and the second cache memory 103 include, for example, an SRAM.

[0075] Depending on the computer, the second cache memory 103 may not be provided in the storage hierarchy 100. Alternatively, a cache memory (sometimes called a third cache memory or tertiary cache memory) with a slower access speed and a larger storage capacity than the second cache memory 103 may be provided in the storage hierarchy 100. In other words, the storage hierarchy 100 may include one or more cache memories.

[0076] The memory hierarchy 100 may also be configured such that the first cache memory 102 and the second cache memory 103 are included in a processor. The memory hierarchy 100 may also be configured such that the first cache memory 102 is included in a processor and the second cache memory 103 is included in a main memory 104, which will be described later.

[0077] The main memory 104 is, for example, a storage device located between the first cache memory 102 and the second cache memory 103 and the auxiliary storage device 105 in the memory hierarchy 100, and has the function of directly writing or reading data by receiving a command signal from a processor equipped with a register 101.

[0078] The main memory 104 includes, for example, a DRAM.

[0079] The auxiliary storage device 105 is a storage device with a large storage capacity, and for example, a non-volatile storage device is mainly used for the auxiliary storage device 105. Examples of non-volatile storage devices include magnetic storage media (for example, a hard disk drive (HDD) or a magnetic tape) and flash memory (for example, a solid state drive (SSD) or a USB memory).

[0080] The storage hierarchy 100 may be configured such that a storage device called a disk cache is provided between the main memory 104 and the auxiliary storage device 105. By providing a disk cache between the main memory 104 and the auxiliary storage device 105, the speed of data transfer between the main memory 104 and the auxiliary storage device 105 can be increased.

[0081] A difference is likely to occur between the operating speed of the processor and the operating speed (sometimes referred to as the access speed) of each storage device included in the storage hierarchy 100 (particularly storage devices located in a lower hierarchy than the first cache memory 102). For this reason, in the storage hierarchy 100, the higher the storage device is located, the faster the access speed is generally required. Furthermore, the higher the storage device is located, the closer it is required to be to the arithmetic circuit or control circuit included in the processor.

[0082] Furthermore, in the memory hierarchy 100, it is preferable that frequently accessed storage devices have small storage capacities. This is because a small storage capacity shortens the time required to search for data stored in the storage device, thereby increasing the operating speed of the storage device. On the other hand, if a processor is to process a large amount of data, it is preferable that the storage capacity of the entire memory hierarchy 100 be large. Therefore, the lower the storage device, the larger the storage capacity is required. For example, it is preferable that the first cache memory 102 has a larger storage capacity than the register 101, it is preferable that the second cache memory 103 has a larger storage capacity than the first cache memory 102, it is preferable that the main memory 104 has a larger storage capacity than the second cache memory 103, and it is preferable that the auxiliary storage device 105 has a larger storage capacity than the main memory 104.

[0083] In the memory hierarchy from the register 101 to the main memory 104, when a processor reads necessary data, it attempts to access the storage devices in order, starting from the highest one in the memory hierarchy 100. Furthermore, if the necessary data is not stored in a storage device in a higher hierarchy (a cache miss occurs), the processor accesses a storage device in a lower hierarchy than the storage device in the higher hierarchy. In particular, the lower the hierarchy of the storage device, the longer the distance to the processor (register 101) and the longer the time required for access (a cache miss penalty occurs). Furthermore, bus wiring (e.g., an internal bus or an external bus) may be used to transfer data between storage devices in two different hierarchies, and the greater the amount of data flowing through the bus wiring, the greater the impact on the processor's performance (operating speed).

[0084] 1A and 1B show a semiconductor device according to one embodiment of the present invention that solves the above-described problems. Fig. 1A is a schematic perspective view illustrating a configuration example of a semiconductor device DEV according to one embodiment of the present invention, and Fig. 1B is a block diagram of the semiconductor device DEV.

[0085] The semiconductor device DEV has a memory layer MEML_L which is a lower memory device in the memory hierarchy 100, a memory layer MEML_H which is an upper memory device in the memory hierarchy 100, and a circuit layer SWCL. The memory layer MEML_H is located below the circuit layer SWCL, and the memory layer MEML_L is located above the circuit layer SWCL. That is, in the semiconductor device DEV, the memory layer MEML_H, the circuit layer SWCL, and the memory layer MEML_L are stacked from the bottom up.

[0086] The memory layer MEML_L is, for example, a memory layer in the memory hierarchy 100 that includes the register 101, the first cache memory 102, the second cache memory 103, or the main memory 104.

[0087] The memory layer MEML_H is, for example, a memory layer included in a higher hierarchy than the memory layer MEML_L in the memory hierarchy 100. For example, if the memory layer MEML_L includes a first cache memory 102, the memory layer MEML_H preferably includes a register 101. Also, for example, if the memory layer MEML_L includes a second cache memory 103, the memory layer MEML_H preferably includes the first cache memory 102. Also, for example, if the memory layer MEML_L includes a main memory 104, the memory layer MEML_H preferably includes the second cache memory 103.

[0088] 1A and 1B, it is assumed that the memory layer MEML_L includes a plurality of memory circuits ME_L, and that the memory layer MEML_H includes a plurality of memory circuits ME_H.

[0089] As an example, as shown in FIG. 3 , the memory circuit ME_L has a memory cell array in which multiple memory cells MC_L are arranged in a matrix of one or more rows. Furthermore, when wiring WL_L extends in the row direction as a read word line in the memory cell array, wiring BL_L preferably extends in the column direction as a bit line for transmitting data read from the memory cells MC_L. Furthermore, it is preferable that one row of memory cells MC_L in the memory cell array (illustrated as region MA_L in FIG. 3 ) holds one data item. For example, if one memory cell MC_L has a storage capacity of one bit and the memory cell array has eight columns, one row of memory cells MC_L in the memory cell array (memory cells MC_L in region MA_L) holds one data item with a storage capacity of eight bits. In other words, 8 bits (one byte) of data can be read with one read operation. Furthermore, for example, if one memory cell MC_L has a storage capacity of one bit and the memory cell array has 64 columns, the memory cells MC_L in region MA_L hold one data item with a storage capacity of 64 bits. That is, 64 bits (8 bytes) of data can be read in one read operation. The number of columns of the memory cell array is not limited to a multiple of 8, and may be an integer of 1 or greater.

[0090] In other words, when the number of rows in the memory cell array of memory circuit ME_L is m (here, m is an integer greater than or equal to 1) and the number of columns is n (here, n is an integer greater than or equal to 1), it can be said that memory circuit ME_L can hold m pieces of n-bit data.

[0091] As an example, the memory circuit ME_H has a memory cell array in which multiple memory cells MC_H are arranged in a matrix of one or more rows, similar to the memory circuit ME_L. The memory cells included in the memory circuit ME_H may have the same or different configuration as the memory cells included in the memory circuit ME_L. Furthermore, when wirings WL_H extend in the row direction as write word lines in the memory cell array, wirings BL_H preferably extend in the column direction as bit lines transmitting data to be written to the memory cells MC_H. Furthermore, it is preferable that one row of memory cells MC_H in the memory cell array (illustrated as region MA_H in FIG. 3 ) hold one piece of data. For example, if one memory cell MC_H has a storage capacity of one bit and the memory cell array has eight columns, one piece of data with a storage capacity of 8 bits (1 byte) can be written to the memory cells MC_H in region MA_H. Furthermore, for example, if one memory cell MC_H has a storage capacity of 1 bit and the number of columns of the memory cell array is 64, one data item with a storage capacity of 64 bits (8 bytes) can be written to the memory cells MC_H in the area MA_H. Note that the number of columns of the memory cell array is not limited to a multiple of 8, and may be an integer of 1 or greater.

[0092] Similar to memory circuit ME_L, when the number of rows in the memory cell array of memory circuit ME_H is m (where m is an integer greater than or equal to 1) and the number of columns is n (where n is an integer greater than or equal to 1), memory circuit ME_H can hold m n-bit data.

[0093] In particular, it is preferable that the storage capacity of data held in the region MA_H is the same as the storage capacity of data held in the region MA_L. That is, it is preferable that the number of rows and columns of the memory cell array of the memory circuit ME_H is equal to the number of rows and columns of the memory cell array of the memory circuit ME_L.

[0094] 1B and 3, the semiconductor device DEV is configured such that one memory circuit ME_L transmits one piece of 1-bit or multi-bit data to the circuit layer SWCL. The semiconductor device DEV is also configured such that one memory circuit ME_H receives one piece of 1-bit or multi-bit data from the circuit layer SWCL. Therefore, each of the memory circuits ME_L and ME_H is, for example, a memory circuit that stores digital data.

[0095] For example, the memory circuit ME_L has a function of reading 8-bit (1 byte) data and transmitting the data to the circuit layer SWCL. The memory circuit ME_H has a function of writing 8-bit data transmitted from the memory circuit ME_L via the circuit layer SWCL. The memory circuits ME_L and ME_H may handle data of less than 8 bits, such as 1 bit, 2 bits, or 4 bits. They may also handle data of more than 8 bits, such as 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits.

[0096] Therefore, when the read word lines extend in the row direction in the memory cell array included in the memory circuit ME_H, the number of columns of the memory cell array is preferably equal to the number of columns of the memory cell array included in the memory circuit ME_L. For example, if the memory cells in each of the memory circuits ME_L and ME_H can hold 1-bit data, the number of columns of the memory cell arrays in each of the memory circuits ME_L and ME_H can be eight, thereby making each of the memory circuits ME_L and ME_H a memory circuit that handles 8-bit data. In this case, the number of wirings BL_L used to transmit data from the memory circuit ME_L to the circuit layer SWCL can be eight, and the number of wirings BL_H used to transmit data from the circuit layer SWCL to the memory circuit ME_H can also be eight. Furthermore, for example, the number of columns of the memory cell arrays in each of the memory circuits ME_L and ME_H can be 64, thereby making each of the memory circuits ME_L and ME_H a memory circuit that handles 64-bit data. In addition, at this time, the number of wirings BL_L used to transmit data from the memory circuit ME_L to the circuit layer SWCL can be 64, and the number of wirings BL_H used to transmit data from the circuit layer SWCL to the memory circuit ME_H can also be 64.

[0097] Furthermore, when the wiring WL_H functioning as a read word line in the memory cell array included in the memory circuit ME_H extends in the row direction, it is preferable that the number of rows of the memory cell array included in the memory circuit ME_H is equal to the number of rows of the memory cell array included in the memory circuit ME_L.

[0098] Note that specific circuit configurations of the memory circuits ME_L and ME_H will be described later.

[0099] Incidentally, since the memory layer MEML_L overlaps the memory layer MEML_H via the circuit layer SWCL, for example, by forming wiring that functions as a plug in each of the memory layer MEML_L, the circuit layer SWCL, and the memory layer MEML_H, the memory layer MEML_L and the circuit layer SWCL can be electrically connected, and the circuit layer SWCL and the memory layer MEML_H can also be electrically connected. That is, the electrical connection between the memory layer MEML_L and the circuit layer SWCL, and the electrical connection between the circuit layer SWCL and the memory layer MEML_H can be achieved by wiring in the stacking direction. In this case, compared to forming wiring on a flat surface, the length of the wiring can be shortened and the number of wiring can be increased. Therefore, by stacking the memory layer MEML_L, the circuit layer SWCL, and the memory layer MEML_H and forming wiring in the stacking direction, the amount of data exchanged between the memory layer MEML_L and the memory layer MEML_H can be increased. Moreover, the data transfer speed between the memory layer MEML_L and the memory layer MEML_H can be increased.

[0100] Furthermore, because the memory layer MEML_L and the memory layer MEML_H are electrically connected via the circuit layer SWCL, for example, a system bus need not be provided between the memory layer MEML_L and the memory layer MEML_H. A system bus is a data transmission path (wiring) that connects each device constituting a computer to the processor, and is divided into an external bus that connects the processor to each external device (e.g., main memory, auxiliary storage device, or optical drive) and an internal bus that connects circuits within the processor (e.g., cache memory, control device, or arithmetic circuit). In particular, when the processor is a CPU, the system bus is sometimes called a CPU bus. Because the system bus is connected to each device, the transmission path (wiring) tends to be long, which can increase the time required for data transmission and the power consumption required for data transmission.

[0101] As in the semiconductor device DEV, by exchanging data directly between the memory layer MEML_L and the memory layer MEML_H without going through a system bus, the access speed of the processor equipped with the semiconductor device DEV can be improved and power consumption can be reduced.

[0102] The circuit layer SWCL has a function of selecting one of the plurality of memory circuits ME_L included in the memory layer MEML_L and one of the plurality of memory circuits ME_H included in the memory layer MEML_H, and bringing the selected memory circuit ME_L and the memory circuit ME_H into a conductive state. Also, each of the plurality of memory circuits ME_L that are not selected becomes non-conductive with the plurality of memory circuits ME_H included in the memory layer MEML_H.

[0103] In other words, by using the circuit layer SWCL to select one of the multiple memory circuits ME_L included in the memory layer MEML_L and one of the multiple memory circuits ME_H included in the memory layer MEML_H, data held in the area MA_L of the memory cell array of the selected memory circuit ME_L in the memory layer MEML_L can be read and written to the area MA_H of the memory cell array of the selected memory circuit ME_H in the memory layer MEML_H.

[0104] Although the above example shows a configuration in which one piece of data is read from the region MA_L of the memory cell array in the memory circuit ME_L and written to the region MA_H of the memory cell array in the memory circuit ME_H, one embodiment of the present invention is not limited to this. The configuration of the semiconductor device DEV in FIG. 3 may be changed so that multiple pieces of data, rather than one piece of data, are read from the memory circuit ME_L and written to the memory circuit ME_H.

[0105] 4 is configured such that a plurality of wirings BLUT_L are electrically connected to each of a plurality of memory cells MC_L arranged in a memory cell array of a memory circuit ME_L, and the plurality of wirings BLUT_L are electrically connected to a circuit layer SWCL. Also, the semiconductor device DEV shown in FIG. 4 is configured such that a plurality of wirings BLUT_H are electrically connected to each of a plurality of memory cells MC_H arranged in a memory cell array of a memory circuit ME_H, and the plurality of wirings BLUT_H are electrically connected to a circuit layer SWCL.

[0106] That is, the number of wirings of the wiring BLUT_L is equal to the number of memory cells MC_L arranged in the memory cell array of the memory circuit ME_L. The number of wirings of the wiring BLUT_H is equal to the number of memory cells MC_H arranged in the memory cell array of the memory circuit ME_H. Preferably, the number of rows of the memory cell array of the memory circuit ME_L is equal to the number of rows of the memory cell array of the memory circuit ME_H, and the number of columns of the memory cell array of the memory circuit ME_L is equal to the number of columns of the memory cell array of the memory circuit ME_H.

[0107] The wiring BLUT_L is a wiring corresponding to the wiring BL_L in Fig. 3 and differs from the wiring BL_L in Fig. 3 in that it is electrically connected to one of the memory cells MC_L included in the memory circuit ME_L. Similarly, the wiring BLUT_H is a wiring corresponding to the wiring BL_H in Fig. 3 and differs from the wiring BL_H in Fig. 3 in that it is electrically connected to one of the memory cells MC_H included in the memory circuit ME_H.

[0108] 4 , by electrically connecting one wiring BLUT_L to each of a plurality of memory cells MC_L in the memory circuit ME_L, it is possible to simultaneously transmit a plurality of data held in memory cells MC_L arranged in not one row but multiple rows (all rows) in the memory cell array of the memory circuit ME_L to the circuit layer SWCL. Also, by electrically connecting one wiring BLUT_H to each of a plurality of memory cells MC_H in the memory circuit ME_H, it is possible to simultaneously write data transmitted from the circuit layer SWCL to memory cells MC_H arranged in not one row but multiple rows (all rows) in the memory cell array of the memory circuit ME_H.

[0109] Note that the above-described memory circuits ME_L and ME_H may be memory circuits that store analog data instead of digital data. In this case, data exchanged between the memory circuits ME_L and ME_H via the circuit layer SWCL can be analog data instead of digital data. In the case of analog data, the number of wirings connected between the memory circuits ME_L and ME_H can be smaller than in the case of handling digital data, thereby further reducing the circuit area of ​​the semiconductor device DEV.

[0110] <Configuration Example of Circuit Layer SWCL> Next, a configuration example of the circuit layer SWCL will be described.

[0111] <<Direct Map Method>> First, a case where the direct map method is applied as the storage structure of the storage layer MEML_L and the storage layer MEML_H will be described.

[0112] The direct mapping method is a method in which, when data stored in a memory circuit ME_L included in a memory layer MEML_L is written to a memory circuit ME_H in a memory layer MEML_H, the address of the memory circuit ME_H to which the data is written is determined based on the address of the memory circuit ME_L in which the data is stored.

[0113] An example of the direct mapping method applied to the memory layers MEML_L and MEML_H is shown in FIG. 5. In the semiconductor device DEV of FIG. 5, the memory layer MEML_L is, for example, ５ = 32 blocks, and the memory layer MEML_H has a storage capacity of, for example, 2 ３ = 8 blocks of storage capacity. Note that in the memory layer MEML_L, one block corresponds to one memory circuit ME_L, and in the memory layer MEML_H, one block corresponds to one memory circuit ME_H. That is, the memory layer MEML_L has 32 memory circuits ME_L, and the memory layer MEML_H has 8 memory circuits ME_H.

[0114] Furthermore, memory addresses ranging from "00000" to "11111" are assigned to each of the 32 memory circuits ME_L in the memory layer MEML_L. Similarly, memory addresses ranging from "000" to "111" are assigned to each of the eight memory circuits ME_H in the memory layer MEML_H.

[0115] For simplicity, each of the memory circuits ME_L and ME_H has a matrix-shaped memory cell array of one row. That is, when data is read from the memory circuit ME_L, data from that row is uniquely read from the memory circuit ME_L. Also, when data is written to the memory circuit ME_H, data is uniquely written to that row in the memory circuit ME_H.

[0116] Here, attention is focused on the memory circuit ME_L of a block in which the lowest three bits of the memory address are "000" among the 32 memory circuits ME_L in the memory layer MEML_L (although not all blocks are shown in FIG. 5, there are four blocks in the memory layer MEML_L in FIG. 5). The semiconductor device DEV in FIG. 5 is configured so that data of any one of the memory circuits ME_L of a block in which the lowest three bits of the memory address are "000" is transmitted to the memory circuit ME_H in the memory layer MEML_H whose memory address is "000".

[0117] Similarly, attention is focused on the memory circuit ME_L of the block in which the lowest three bits of the memory address are "100" among the three memory circuits ME_L in the memory layer MEML_L. The semiconductor device DEV in Fig. 5 is configured so that data of any one of the memory circuits ME_L of the block in which the lowest three bits of the memory address are "100" is transmitted to the memory circuit ME_H in the memory layer MEML_H in which the memory address is "100".

[0118] Similarly, of the 32 memory circuits ME_L in the memory layer MEML_L, attention is focused on the memory circuits ME_L in the block in which the lowest three bits of the memory address are "111." The semiconductor device DEV in Fig. 5 is configured so that data of any one of the memory circuits ME_L in the block in which the lowest three bits of the memory address are "111" is transmitted to the memory circuit ME_H in the memory layer MEML_H in which the memory address is "111."

[0119] To summarize the above, when data read from memory layer MEML_L is written to memory layer MEML_H, the address of memory circuit ME_H to which the data of memory layer MEML_H is written is limited to the same value as the lowest three bits of the memory address of memory layer MEML_L from which the data is read.

[0120] As described above, in the direct mapping method, when data read from the memory layer MEML_L is written to the memory layer MEML_H, the memory address of the memory circuit ME_H to which the data in the memory layer MEML_H is written is determined based on the memory address of the memory circuit ME_L in the memory layer MEML_L from which the data is read. In other words, in this way, in the direct mapping method, the data written to the memory circuit ME_H is limited to the data read from the memory circuit ME_L at a specific memory address. Therefore, for example, when searching for data in a certain memory circuit ME_L in the memory layer MEML_L from among multiple memory circuits ME_H in the memory layer MEML_H, the specified memory circuit ME_H can be found from the memory layer MEML_H using the memory address of the memory circuit ME_L in which the desired data is stored. Therefore, by using the direct mapping method, the data read speed can be increased.

[0121] An example of the configuration of a circuit layer SWCL when the direct mapping method is applied to the semiconductor device DEV will be described. Fig. 6 is a circuit diagram in which an example of the circuit configuration of the circuit layer SWCL is added to the semiconductor device DEV shown in Fig. 5. Note that in Fig. 6, the circuit layer SWCL shown in Figs. 1A and 1B is illustrated as a circuit layer SWCLA.

[0122] The circuit layer SWCLA has switches SW

[00000] to SW

[11111] . Note that Fig. 6 illustrates only switches SW

[00000] , SW

[00100] , SW

[00111] , SW

[01000] , SW

[01100] , SW

[01111] , SW

[10000] , SW

[10100] , SW

[10111] , and SW

[11111] .

[0123] A first terminal of the switch SW

[00000] is electrically connected to the memory circuit ME_L at memory address "00000" in the memory layer MEML_L. A first terminal of the switch SW

[01000] is electrically connected to the memory circuit ME_L at memory address "01000" in the memory layer MEML_L. A first terminal of the switch SW

[10000] is electrically connected to the memory circuit ME_L at memory address "10000" in the memory layer MEML_L. Although not shown, a first terminal of the switch SW

[11000] is electrically connected to the memory circuit ME_L at memory address "11000" in the memory layer MEML_L. Further, second terminals of the switches SW

[00000] , SW

[01000] , SW

[10000] , and SW

[11000] are electrically connected to the memory circuit ME_H at the memory address "000" in the memory layer MEML_H.

[0124] By turning on one of the switches SW

[00000] , SW

[01000] , SW

[10000] , and SW

[11000] and turning off the rest, one of the memory addresses "00000", "01000", "10000", and "11000" of the memory layer MEML_L is selected. After that, the data held in the memory circuit ME_L at the selected memory address is read out, and the data is transmitted to the memory circuit ME_H at the memory address "000" of the memory layer MEML_H, and the data is stored in the memory circuit ME_H at the memory address "000".

[0125] Similarly, a first terminal of the switch SW

[00100] is electrically connected to the memory circuit ME_L at memory address "00100" in the memory layer MEML_L. A first terminal of the switch SW

[01100] is electrically connected to the memory circuit ME_L at memory address "01100" in the memory layer MEML_L. A first terminal of the switch SW

[10100] is electrically connected to the memory circuit ME_L at memory address "10100" in the memory layer MEML_L. Although not shown, a first terminal of the switch SW

[11100] is electrically connected to the memory circuit ME_L at memory address "11100" in the memory layer MEML_L. Further, second terminals of the switches SW

[00100] , SW

[01100] , SW

[10100] , and SW

[11100] are electrically connected to the memory circuit ME_H at memory address "100" in the memory layer MEML_H.

[0126] By turning on one of the switches SW

[00100] , SW

[01100] , SW

[10100] , and SW

[11100] and turning off the rest, one of the memory addresses "00100", "01100", "10100", and "11100" of the memory layer MEML_L is selected. After that, the data held in the memory circuit ME_L at the selected memory address is read out, and the data is transmitted to the memory circuit ME_H at the memory address "100" of the memory layer MEML_H, and the data is stored in the memory circuit ME_H at the memory address "100".

[0127] Similarly, a first terminal of the switch SW

[00111] is electrically connected to the memory circuit ME_L at memory address "00111" in the memory layer MEML_L. Also, a first terminal of the switch SW

[01111] is electrically connected to the memory circuit ME_L at memory address "01111" in the memory layer MEML_L. Also, a first terminal of the switch SW

[10111] is electrically connected to the memory circuit ME_L at memory address "10111" in the memory layer MEML_L. Also, a first terminal of the switch SW

[11111] is electrically connected to the memory circuit ME_L at memory address "11111" in the memory layer MEML_L. Further, second terminals of the switches SW

[00111] , SW

[01111] , SW

[10111] , and SW

[11111] are electrically connected to the memory circuit ME_H at the memory address "111" in the memory layer MEML_H.

[0128] By turning on one of the switches SW

[00111] , SW

[01111] , SW

[10111] , and SW

[11111] and turning off the rest, one of the memory addresses "00111", "01111", "10111", and "11111" of the memory layer MEML_L is selected. After that, the data held in the memory circuit ME_L at the selected memory address is read out, and the data is transmitted to the memory circuit ME_H at the memory address "111" of the memory layer MEML_H, and the data is stored in the memory circuit ME_H at the memory address "111".

[0129] In order to simply explain the circuit layer SWCLA in Fig. 6, a configuration example of a portion of the semiconductor device DEV in Fig. 6 is shown in Fig. 7. Note that the circuit layer SWCLA shown in Fig. 7 differs from the circuit layer SWCLA shown in Fig. 6 in that a selector MPX is illustrated. Also, Fig. 7 excerpts memory circuits ME_L in the memory layer MEML_L having memory addresses of "00000", "01000", "10000", and "11000", and memory circuit ME_H in the memory layer MEML_H having a memory address of "000".

[0130] The selector MPX has, for example, a plurality of input terminals IT and one output terminal OT.

[0131] Each of the multiple input terminals IT of the selector MPX is electrically connected to a multiple memory circuit ME_L of the memory layer MEML_L. Note that the lower-order predetermined few bits of the memory addresses of the multiple memory circuits ME_L electrically connected to each of the multiple input terminals IT of the selector MPX are assumed to be equal to each other (in FIG. 7, the lower three bits of the memory address of the memory circuit ME_L are "000"). Furthermore, the output terminal OT of the selector MPX is electrically connected to the memory circuit ME_H having a memory address equal to the lower-order predetermined few bits of the memory address of the memory circuit ME_L (in FIG. 7, the memory address of the memory circuit ME_H is "000").

[0132] The selector MPX has a function of bringing one of the multiple input terminals IT of the selector MPX into a conductive state and the output terminal OT of the selector MPX in response to, for example, a signal SSIG input to the selector MPX. The selector MPX also has a function of selecting one of the input signals input to the multiple input terminals IT of the selector MPX in response to the signal SSIG input to the selector MPX, and outputting the selected input signal to the output terminal OT of the selector MPX. The selector MPX also has a function of bringing each of the remaining multiple input terminals IT of the selector MPX into a non-conductive state and the output terminal OT of the selector MPX in response to, for example, the signal SSIG input to the selector MPX.

[0133] For this reason, the selector MPX is sometimes called a multiplexer.

[0134] Furthermore, a sample-and-hold circuit may be provided between the output terminal OT of the selector MPX and the memory circuit ME_H. By providing a sample-and-hold circuit between the output terminal OT of the selector MPX and the memory circuit ME_H in the semiconductor device DEV, it is possible to temporarily hold the data at the output terminal OT of the selector MPX. In other words, it is possible to prepare data to be written to the memory circuit ME_H in advance, thereby increasing the operating speed of the semiconductor device DEV.

[0135] 8A and 8B are circuit diagrams each showing a specific example of the configuration of the selector MPX.

[0136] 6, the selector MPX shown in Fig. 8A has a configuration in which a first terminal of each of the switches SW1 to SW4 is electrically connected to a corresponding memory circuit ME_L, and a second terminal of each of the switches SW1 to SW4 is electrically connected to a memory circuit ME_H. In addition, a control terminal of the switch SW1 is electrically connected to a wiring SL1, a control terminal of the switch SW2 is electrically connected to a wiring SL2, a control terminal of the switch SW3 is electrically connected to a wiring SL3, and a control terminal of the switch SW4 is electrically connected to a wiring SL4.

[0137] Note that the switches SW1 to SW4 can be, for example, electrical switches (for example, analog switches or transistors). When transistors are used as the switches SW1 to SW4, the transistors can be transistors (OS transistors) containing an oxide semiconductor (metal oxide) in a channel formation region. Metal oxide will be described in detail in Embodiments 2 and 3. The transistors can also be transistors containing silicon in a channel formation region (Si transistors). Note that silicon can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like. Other than electrical switches, mechanical switches can also be used.

[0138] In this specification, each of the switches SW1 to SW4 is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input to the control terminal.

[0139] Each of the wirings SL1 to SL4 functions as a wiring that transmits a signal (variable potential) for switching the switches SW1 to SW4 between a conductive state and a non-conductive state. Note that the signal transmitted to each of the wirings SL1 to SL4 corresponds to the signal SSIG in FIG. 7. Note that each of the wirings SL1 to SL4 may function as a wiring that supplies a constant potential (for example, a high-level potential, a low-level potential, a ground potential, or a negative potential) instead of a signal (variable potential).

[0140] 8A, for example, a high-level potential is applied to one selected from the wirings SL1 to SL4, and a low-level potential is applied to the remaining wirings, thereby enabling conduction between one of the multiple input terminals IT of the selector MPX and the output terminal OT of the selector MPX. Note that, when it is desired to achieve a non-conduction state between all of the multiple input terminals IT of the selector MPX and the output terminal OT of the selector MPX, for example, a low-level potential may be applied to each of the wirings SL1 to SL4.

[0141] The selector MPX shown in Fig. 8B is configured in a tournament format using a plurality of switches. Note that the selector MPX in Fig. 8B includes switches SWa1, SWa2, SWb1, SWb2, SWb3, and SWb4, and the description of each switch can be found in the description of switches SW1 to SW4 shown in Fig. 8A.

[0142] A first terminal of each of the switches SWb1 to SWb4 is electrically connected to a corresponding memory circuit ME_L. The first terminal of the switch SWa1 is electrically connected to a second terminal of the switch SWb1 and a second terminal of the switch SWb2. The first terminal of the switch SWa2 is electrically connected to a second terminal of the switch SWb3 and a second terminal of the switch SWb4. The second terminal of the switch SWa1 and the second terminal of the switch SWa2 are electrically connected to the memory circuit ME_H. The control terminals of the switches SWb1 and SWb3 are electrically connected to a wiring SLb1, the control terminals of the switches SWb2 and SWb4 are electrically connected to a wiring SLb2, the control terminal of the switch SWa1 is electrically connected to a wiring SLa1, and the control terminal of the switch SWa2 is electrically connected to a wiring SLa2.

[0143] For the wirings SLa1, SLa2, SLb1, and SLb2, the description of the wirings SL1 to SL4 in FIG. 8A can be referred to.

[0144] In particular, the signal supplied to the wiring SLa1 is preferably a signal obtained by inverting the logic of the signal supplied to the wiring SLa2. Furthermore, the signal supplied to the wiring SLb1 is preferably a signal obtained by inverting the logic of the signal supplied to the wiring SLb2. This allows one of the switches SWa1 and SWa2 to be turned on and the other to be turned off. Furthermore, one of the switches SWb1 and SWb2 can be turned on and the other to be turned off. Furthermore, one of the switches SWb3 and SWb4 can be turned on and the other to be turned off.

[0145] As described above, by applying a predetermined signal to each of the wirings SLa1, SLa2, SLb1, and SLb2, it is possible to bring one of the input terminals IT of the selector MPX and the output terminal OT of the selector MPX into a conductive state. Note that, when it is desired to bring all of the input terminals IT of the selector MPX into a non-conductive state from the output terminal OT of the selector MPX, for example, a low-level potential may be applied to each of the wirings SLa1 and SLa2.

[0146] Note that one embodiment of the present invention is not limited to the above-described configuration of the semiconductor device DEV, and may be configured in a manner in which the above-described semiconductor device is modified.

[0147] For example, in the above-mentioned semiconductor device DEV, the memory layer MEML_L has 32 memory circuits ME_L and the memory layer MEML_H has 8 memory circuits ME_H, but the number of memory circuits ME_L that the memory layer MEML_L has and the number of memory circuits ME_H that the memory layer MEML_H has are not particularly limited.

[0148] Furthermore, for example, in the semiconductor device DEV described above, the block of the memory circuit ME_H to be the storage destination is determined by referencing the lowest three bits of the memory address of the memory layer MEML_L, but the memory address referenced by the memory layer MEML_L may be the lowest one bit, the lowest two bits, or the lowest four bits or more. Furthermore, the number of memory circuits ME_L provided in the memory layer MEML_L and the number of memory circuits ME_H provided in the memory layer MEML_H may be determined according to the range of the memory address to be referenced.

[0149] <<Set Associative Method>> Next, a case where the set associative method is applied as the storage structure of the storage layer MEML_L and the storage layer MEML_H, which is different from the direct map method, will be described.

[0150] The set associative method is a method in which, when data held in a memory circuit ME_L included in a memory layer MEML_L is written to a memory circuit ME_H in a memory layer MEML_H, the data held in a memory circuit ME_L included in a memory layer MEML_L is held in one of multiple memory circuits ME_H specified based on the address of that memory circuit ME_L.

[0151] An example of the set associative method applied to the memory layers MEML_L and MEML_H is shown in Fig. 9. The semiconductor device DEV in Fig. 9 is configured such that the memory layer MEML_L includes 32 memory circuits ME_L and the memory layer MEML_H includes 8 memory circuits ME_H, similar to the semiconductor device DEV in Fig. 5. Furthermore, the semiconductor device DEV in Fig. 9 also illustrates memory addresses, similar to the semiconductor device DEV in Fig. 5.

[0152] 9, a block (memory circuit ME_H) having a memory address of "000" or "001" is set ST_1. A block (memory circuit ME_H) having a memory address of "010" or "011" is set ST_2. A block (memory circuit ME_H) having a memory address of "100" or "101" is set ST_3. A block (memory circuit ME_H) having a memory address of "110" or "111" is set ST_4.

[0153] 9, similarly to the semiconductor device DEV of FIG. 5, each of the memory circuits ME_L and ME_H has a matrix-shaped memory cell array of one row. That is, when data is read from the memory circuit ME_L, data from that one row is uniquely read from the memory circuit ME_L. Also, when data is written to the memory circuit ME_H, data is uniquely written to that one row in the memory circuit ME_H.

[0154] Here, attention is focused on the memory circuits ME_L of the blocks in which the lowest three bits of the memory address are "000" among the 32 memory circuits ME_L of the memory layer MEML_L (although not all blocks are shown in FIG. 9, there are four blocks in the memory layer MEML_L of FIG. 9). The semiconductor device DEV of FIG. 9 is configured so that data of any one of the memory circuits ME_L of the blocks in which the lowest three bits of the memory address are "000" is transmitted to any one of the memory circuits ME_H included in the set ST_1 in the memory layer MEML_H.

[0155] Similarly, attention is focused on the memory circuits ME_L of the blocks in which the lowest three bits of the memory address are "100" among the 32 memory circuits ME_L of the memory layer MEML_L (although not all blocks are shown in FIG. 9, there are four blocks in the memory layer MEML_L of FIG. 9). The semiconductor device DEV of FIG. 9 is configured so that data of any one of the memory circuits ME_L of the blocks in which the lowest three bits of the memory address are "100" is transmitted to any one of the memory circuits ME_H included in the set ST_3 in the memory layer MEML_H.

[0156] In other words, like the direct map method, in the set associative method, when data read from the memory layer MEML_L is written to the memory layer MEML_H, the memory address of the memory circuit ME_H to which the data in the memory layer MEML_H is written is determined based on the memory address of the memory circuit ME_L in the memory layer MEML_L from which the data is read, but the memory circuit ME_H to which the data is written can be selected from multiple blocks included in a specified set.

[0157] 9, a method of selecting one of two memory circuits ME_H as a write destination for data read from the memory layer MEML_L is sometimes called a 2-way set associative method. Also, a method of selecting one of N (N is an integer equal to or greater than 2) memory circuits ME_H as a write destination for data read from the memory layer MEML_L is sometimes called an N-way set associative method.

[0158] In the set associative method, as in the direct mapped method, the memory address of the memory circuit ME_H to which data in the memory layer MEML_H is written is determined based on the memory address of the memory circuit ME_L in the memory layer MEML_L from which the data is read. In other words, in this way, in the set associative method, the data written to the memory circuit ME_H is limited to the data read from the memory circuit ME_L at a specific memory address. Therefore, for example, when searching for data in a certain memory circuit ME_L in the memory layer MEML_L from among the multiple memory circuits ME_H in the memory layer MEML_H, the specified memory circuit ME_H can be found from the memory layer MEML_H using the memory address of the memory circuit ME_L in which the desired data is stored. Therefore, by using the set associative method, the data read speed can be increased. Unlike the direct map method, there are multiple candidates (the number of blocks included in the set) for the memory circuit ME_H to which the data read from the memory layer MEML_L is written, so the time required to search for the desired data (the time required for reading) may be longer than with the direct map method.

[0159] FIG. 10 shows an example of the configuration of the circuit layer SWCL in the semiconductor device DEV of FIG. 10. Note that FIG. 10 illustrates a circuit layer SWCLB as the circuit layer SWCL. Also, FIG. 10 illustrates, as an example, memory layers MEML_L and MEML_H. Also, FIG. 10 excerpts memory circuits ME_L in the memory layer MEML_L having memory addresses of "00000," "01000," "10000," and "11000," and memory circuits ME_H (set ST_1) in the memory layer MEML_H having memory addresses of "000" and "001."

[0160] The circuit layer SWCLB has a selector MPX and a selector DMPX. The selector MPX has, as an example, a plurality of input terminals IT1 and one output terminal OT1. The selector DMPX has, as an example, one input terminal IT2 and a plurality of output terminals OT2. For the selector MPX, the description of the selector MPX in FIG. 7 can be referred to.

[0161] Each of the multiple input terminals IT1 of the selector MPX is electrically connected to a multiple memory circuit ME_L of the memory layer MEML_L. Note that the lower-order predetermined few bits of the memory addresses of the multiple memory circuits ME_L electrically connected to each of the multiple input terminals IT1 of the selector MPX are assumed to be equal to each other. Furthermore, the output terminal OT1 of the selector MPX is electrically connected to the input terminal IT2 of the selector DMPX. Furthermore, each of the multiple output terminals OT2 of the selector DMPX is electrically connected to the memory circuit ME_H of a predetermined memory address.

[0162] The selector DMPX has a function of bringing the input terminal IT2 of the selector DMPX into a conductive state and one of the plurality of output terminals OT2 of the selector DMPX in response to a signal DSIG input to the selector DMPX, and also has a function of bringing the input terminal IT2 of the selector DMPX into a non-conductive state and each of the remaining plurality of output terminals OT2 of the selector DMPX.

[0163] For this reason, the selector DMPX is sometimes called a demultiplexer.

[0164] FIG. 11 is a circuit diagram showing a specific example of the configuration of the selector MPX and the selector DMPX in FIG.

[0165] 8, the selector DMPX shown in FIG. 11 is configured such that first terminals of the switches SW1 to SW4 are electrically connected to corresponding memory circuits ME_L, second terminals of the switches SW1 to SW4 are electrically connected to first terminals of the switches SW5 and SW6, and second terminals of the switches SW5 and SW6 are electrically connected to corresponding memory circuits ME_H. The control terminal of the switch SW1 is electrically connected to wiring SL1, the control terminal of the switch SW2 is electrically connected to wiring SL2, the control terminal of the switch SW3 is electrically connected to wiring SL3, and the control terminal of the switch SW4 is electrically connected to wiring SL4. The control terminal of the switch SW5 is electrically connected to wiring SL5.

[0166] For the wirings SL1 to SL4, the description of the wirings SL1 to SL4 shown in FIG. 8A can be referred to.

[0167] The wirings SL5 and SL6 each function as a wiring that transmits a signal (variable potential) for switching the switches SW5 and SW6 between a conductive state and a non-conductive state, for example. Note that the signal transmitted to the wirings SL5 and SL6 corresponds to the signal DSIG in FIG. 10. Note that the wirings SL5 and SL6 may each function as a wiring that supplies a constant potential (for example, a high-level potential, a low-level potential, a ground potential, or a negative potential) instead of a signal (variable potential).

[0168] The selector MPX shown in FIG. 11 can establish electrical continuity between one of the multiple input terminals IT1 of the selector MPX and the output terminal OT1 of the selector MPX by, for example, applying a high-level potential to one selected from the wirings SL1 to SL4 and a low-level potential to the remaining wirings. That is, as described above, the memory circuit ME_L included in the memory layer MEML_L can be selected. Furthermore, the selector DMPX shown in FIG. 11 can establish electrical continuity between the input terminal IT2 of the selector DMPX and one of the multiple output terminals OT2 of the selector MPX by, for example, applying a high-level potential to one of the wirings SL5 and SL6 and a low-level potential to the other. That is, as described above, the memory circuit ME_H included in the memory layer MEML_H can be selected. This establishes electrical continuity between the memory circuit ME_L from which data is read and the memory circuit ME_H to which the data is written.

[0169] One or both of the selector MPX and the selector DMPX in FIG. 11 may have a tournament-type circuit configuration like the selector MPX in FIG. 8B (not shown).

[0170] A sample-and-hold circuit may be provided between one of the plurality of output terminals OT2 of the selector DMPX and one of the plurality of storage circuits ME_H. In the semiconductor device DEV, by providing a sample-and-hold circuit between the output terminal OT2 of the selector DMPX and the storage circuit ME_H, data at the output terminal OT2 of the selector DMPX can be temporarily held. For example, in the semiconductor device DEV of FIG. 11 , by providing a sample-and-hold circuit between the output terminal OT2 of the selector DMPX and the storage circuit ME_H, data to be written to the storage circuits ME_H at memory addresses "000" and "001" can be temporarily held in advance. Furthermore, by simultaneously outputting the sample-and-hold circuit, write data can be simultaneously transmitted to the storage circuits ME_H at memory addresses "000" and "001." In other words, the write operations in the storage circuits ME_H at memory addresses "000" and "001" can be synchronized. This eliminates the need to operate the multiple memory circuits ME_H individually, and thus the operating speed of the semiconductor device DEV can be increased.

[0171] Note that one aspect of the present invention is not limited to the configuration of the semiconductor device DEV described above, and may be a configuration in which the semiconductor device DEV described above is modified.

[0172] For example, in the above-mentioned semiconductor device DEV, the memory layer MEML_L has 32 memory circuits ME_L and the memory layer MEML_H has 8 memory circuits ME_H, but the number of memory circuits ME_L that the memory layer MEML_L has and the number of memory circuits ME_H that the memory layer MEML_H has are not particularly limited.

[0173] Furthermore, for example, in the above-described semiconductor device DEV, the set in the memory layer MEML_H to be the storage destination is determined by referencing the lowest three bits of the memory address of the memory layer MEML_L, but the memory address referenced by the memory layer MEML_L may be the lowest one bit, the lowest two bits, or the lowest four bits or more. Alternatively, in the above description, the number of blocks in a set is two as a two-way set associative method, but the number of blocks in a set may be three or more. Furthermore, the number of memory circuits ME_L provided in the memory layer MEML_L and the number of memory circuits ME_H provided in the memory layer MEML_H may be determined according to the range of memory addresses to be referenced and the number of blocks in a set.

[0174] <<Full Associative Method>> Next, a case will be described in which the full associative method is applied as the storage structure of the storage layer MEML_L and the storage layer MEML_H, which is different from the direct map method and the set associative method.

[0175] The fully associative method is a method in which data read from one selected from a plurality of memory circuits ME_L included in the memory layer MEML_L is held in one selected from a plurality of memory circuits ME_H in the memory layer MEML_H, regardless of the memory address of the selected memory circuit ME_L. In other words, in the fully associative method, there are no particular restrictions on the data written to the memory circuit ME_H of the memory layer MEML_H.

[0176] An example of the full associative method applied to the memory layers MEML_L and MEML_H is shown in Fig. 12. The semiconductor device DEV in Fig. 12 is configured such that the memory layer MEML_L includes 32 memory circuits ME_L and the memory layer MEML_H includes 8 memory circuits ME_H, similar to the semiconductor device DEV in Fig. 5. Furthermore, the semiconductor device DEV in Fig. 12 also illustrates memory addresses, similar to the semiconductor device DEV in Fig. 5.

[0177] As explained in the direct map method and the set associative method, in the semiconductor device DEV, the number of memory circuits ME_L included in the memory layer MEML_L may be a number other than 32. Similarly, the number of memory circuits ME_H included in the memory layer MEML_H may be a number other than 8.

[0178] 12, similarly to the semiconductor device DEV of FIG. 5, each of the memory circuits ME_L and ME_H has a matrix-shaped memory cell array of one row. That is, when data is read from the memory circuit ME_L, data from that one row is uniquely read from the memory circuit ME_L. Also, when data is written to the memory circuit ME_H, data is uniquely written to that one row in the memory circuit ME_H.

[0179] Data written to one selected from the plurality of memory circuits ME_H of the memory layer MEML_H is data read from one selected from the plurality of memory circuits ME_L of the memory layer MEML_L. For example, in the semiconductor device DEV of Figure 12, an example is shown in which data read from one selected from the memory circuits ME_L of the memory layer MEML_L having memory addresses from "00000" to "11111" is written to the memory circuit ME_H of the memory layer MEML_H having a memory address of "001".

[0180] 12, each of the memory circuits ME_H of the memory layer MEML_H of the semiconductor device DEV may store one of the data held in the memory circuits ME_L of the memory layer MEML_L having memory addresses from "00000" to "11111". A specific example will be described with reference to FIG. 13. Data held in the memory circuit ME_L of the memory layer MEML_L having a memory address of "00000" is written to the memory circuit ME_H of the memory layer MEML_H having a memory address of "00000". Furthermore, data held in the memory circuit ME_L of the memory layer MEML_L having a memory address of "00100" is written to the memory circuit ME_H of the memory layer MEML_H having a memory address of "001". Furthermore, data held in a memory circuit ME_L having a memory address of "01000" in the memory layer MEML_L is written to a memory circuit ME_H having a memory address of "010" in the memory layer MEML_H. Furthermore, data held in a memory circuit ME_L having a memory address of "10100" in the memory layer MEML_L is written to a memory circuit ME_H having a memory address of "011" in the memory layer MEML_H. Furthermore, data held in a memory circuit ME_L having a memory address of "10010" in the memory layer MEML_L is written to a memory circuit ME_H having a memory address of "100" in the memory layer MEML_H. Furthermore, data held in a memory circuit ME_L having a memory address of "10100" in the memory layer MEML_L is written to a memory circuit ME_H having a memory address of "101" in the memory layer MEML_H. Furthermore, data held in the memory circuit ME_L of the memory layer MEML_L having a memory address of "00111" is written to the memory circuit ME_H of the memory layer MEML_H having a memory address of "110". Furthermore, data held in the memory circuit ME_L of the memory layer MEML_L having a memory address of "01101" is written to the memory circuit ME_H of the memory layer MEML_H having a memory address of "111".

[0181] In the full associative method, for example, if an empty block (a memory circuit ME_H in which no data is held) exists in the memory layer MEML_H, data held in one of the memory circuits ME_L at memory addresses "00000" to "11111" in the memory layer MEML_L can be stored in the empty block. Therefore, by using the full associative method, data can be written preferentially to a memory circuit ME_H that becomes an empty block, and the number of memory circuits ME_H that become empty blocks (memory circuits ME_H in an idle state) can be reduced.

[0182] Fig. 14 shows a configuration example of the circuit layer SWCL in the semiconductor device DEV of Fig. 13. Note that Fig. 14 illustrates the circuit layer SWCLC as the circuit layer SWCL. Fig. 14 also illustrates the memory layers MEML_L and MEML_H.

[0183] The circuit layer SWCLC has a selector MPX and a selector DMPX. As an example, the selector MPX has a plurality of input terminals IT1 and one output terminal OT1. Furthermore, as an example, the selector DMPX has one input terminal IT2 and a plurality of output terminals OT2. For the selector MPX, the description of the selector MPX in FIG. 7 can be referred to. For the selector DMPX, the description of the selector DMPX in FIG. 10 can be referred to.

[0184] Each of the multiple input terminals IT1 of the selector MPX is electrically connected to all of the memory circuits ME_L in the memory layer MEML_L. Also, the output terminal OT2 of the selector MPX is electrically connected to the input terminal IT2 of the selector DMPX. Also, each of the multiple output terminals OT2 of the selector DMPX is electrically connected to all of the memory circuits ME_H in the memory layer MEML_H.

[0185] For the configuration of the selector MPX, the description of the selector MPX shown in Figures 8A and 8B can be referred to. For the configuration of the selector DMPX, the description of the selector DMPX shown in Figure 11 can be referred to.

[0186] Furthermore, similar to the semiconductor device DEV of FIG. 11 used in the explanation of the set associative method, in the semiconductor device DEV shown in FIG. 14, a sample and hold circuit may be provided between one of the plurality of output terminals OT2 of the selector DMPX and one of the plurality of memory circuits ME_H.

[0187] Note that in this embodiment, one embodiment of the present invention is not limited to the above-described structure of the semiconductor device, and may be a modified structure of the above-described semiconductor device.

[0188] For example, in the above explanations of the direct map method, the set associative method, and the full associative method, the memory circuits ME_L and ME_H each have a matrix-shaped memory cell array of one row, but the memory circuits ME_L and ME_H each may have a matrix-shaped memory cell array of multiple rows. In this case, it is preferable that data read from the i-th row (where i is an integer of 1 or greater) of the memory cell array of the memory circuit ME_L be written to the i-th row of the memory cell array of the memory circuit ME_H.

[0189] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0190] Embodiment 2 In this embodiment, a configuration example of the semiconductor device DEV described in the above embodiment and the memory circuits included in the memory layers MEML_L and MEML_H will be described.

[0191] Fig. 15 shows a schematic perspective view of an example of the configuration of the semiconductor device DEV. Fig. 16 shows a block diagram of an example of the configuration of the semiconductor device DEV. The semiconductor device DEV has a drive circuit region 50, a control processing region 80, a circuit layer 90, and N cell array layers 60 (N is an integer equal to or greater than 1). Each cell array layer 60 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns.

[0192] Note that Figure 16 shows an example in which memory cell 10[1,1], memory cell 10[m,1] (where m is an integer greater than or equal to 1), memory cell 10[1,n] (where n is an integer greater than or equal to 1), memory cell 10[m,n], and memory cell 10[i,j] (where i is an integer greater than or equal to 1 and m, and j is an integer greater than or equal to 1 and n) are arranged in cell array layer 60_k.

[0193] FIG. 16 also shows an example in which a cell array 70, a drive circuit 71, a drive circuit 72, an ALU (Arithmetic logic unit) 81, an ALU controller 82, an instruction decoder 83, an interrupt controller 84, and a timing controller 85 are arranged in a control processing area 80.

[0194] The cell array layers 60_1 to 60_N correspond to the memory layer MEML_L described in embodiment 1. The circuit layer 90 corresponds to the circuit layer SWCL described in embodiment 1. The cell array 70 corresponds to the memory layer MEML_H described in embodiment 1.

[0195] The driving circuit region 50 has a function of driving the memory cells 10 included in the cell array layers 60_1 to 60_N. For example, the driving circuit region 50 can write data to the memory cells 10 or read data from the memory cells 10.

[0196] The control processing area 80 corresponds to, for example, a processor applicable to a computer. The cell array 70, the drive circuit 71, and the drive circuit 72 function as cache memory or registers provided in the processor. Specifically, for example, the drive circuit 71 functions as a column driver for the cell array 70, and the drive circuit 72 functions as a row driver for the cell array 70. In addition, in FIG. 16, the cell array 70 has a plurality of memory cells 75 arranged in an array.

[0197] The N cell array layers 60 are provided, for example, on the circuit layer 90. The circuit layer 90 is also provided, for example, on the drive circuit region 50 and the control processing region 80. In particular, by providing the N cell array layers 60 on the drive circuit region 50 and the control processing region 80, the area occupied by the semiconductor device DEV can be reduced. Furthermore, the memory capacity per unit area of ​​the cell array layer 60 can be increased.

[0198] The drive circuit region 50 and the control processing region 80 may be arranged on the same substrate. For example, the drive circuit region 50 and the control processing region 80 may be created on a semiconductor substrate (for example, a single crystal substrate containing silicon). The configuration of the semiconductor device DEV is not limited to that shown in FIG. 15 . For example, the drive circuit region 50 may be provided on the control processing region 80. In this case, the drive circuit region 50 and the control processing region 80 may be arranged on separate substrates, and the drive circuit region 50 may be provided on the control processing region 80 using a Cu-Cu (copper-copper) direct bonding technique or the like.

[0199] In the present embodiment and the like, the first cell array layer 60 is referred to as cell array layer 60_1, the second cell array layer 60 is referred to as cell array layer 60_2, and the third cell array layer 60 is referred to as cell array layer 60_3. Furthermore, the kth cell array layer 60 (k is an integer of 1 to N) is referred to as cell array layer 60_k, and the Nth cell array layer 60 is referred to as cell array layer 60_N. Note that in the present embodiment and the like, when describing matters relating to all N cell array layers 60 or when indicating matters common to each of the N cell array layers 60, the term "cell array layer 60" may be used.

[0200] <Configuration Example of Control Processing Area 80> In Figure 16, the control processing area 80 includes, for example, an ALU 81, an ALU controller 82, an instruction decoder 83, an interrupt controller 84, and a timing controller 85. Note that the control processing area 80 shown in Figure 16 is merely an example showing a simplified configuration, and the control processing area 80 provided in an actual processor has a wide variety of configurations depending on its application. For example, the configuration including the CPU or arithmetic circuit shown in Figure 16 may be considered as one core, and a configuration may include multiple such cores, each operating in parallel, i.e., a GPU-like configuration. Furthermore, the number of bits that the CPU can handle in its internal arithmetic circuit, system bus, etc. may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits or more.

[0201] An instruction input to the control processing area 80 is input to an instruction decoder 83 and decoded. After being decoded, the instruction is input to an ALU controller 82, an interrupt controller 84, and a timing controller 85. The instruction may also be input to drive circuits 71 and 72 of the memory circuits provided in the control processing area 80.

[0202] The ALU controller 82, interrupt controller 84, and timing controller 85 perform various controls based on the decoded instructions. Specifically, the ALU controller 82 generates signals to control the operation of the ALU 81. Furthermore, the interrupt controller 84 processes interrupt requests from external input / output devices or peripheral circuits based on their priority or mask status while a program is being executed in the drive circuit area 50. Furthermore, the memory circuit in the control processing area 80 generates addresses of memory cells included in the cell array 70 based on the decoded instructions, and can read or write data from or to the cell array 70 depending on the status of the drive circuit area 50.

[0203] The timing controller 85 also generates signals that control the timing of the operations of the ALU 81, the ALU controller 82, the instruction decoder 83, the interrupt controller 84, and the memory circuits provided in the control processing area 80. For example, the timing controller 85 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above. The clock signal generated by the timing controller 85 may be the signal CLK described above.

[0204] The memory circuit in the control processing area 80 selects the data retention operation in the memory cells 75 in the cell array 70 in accordance with instructions from the ALU 81. That is, it selects whether the memory cells in the cell array 70 retain data using flip-flops or using capacitive elements. If data retention using flip-flops is selected, power supply voltage is supplied to the memory cells 75 in the cell array 70. If data retention using capacitive elements is selected, data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells 75 in the cell array 70 can be stopped.

[0205] 16, the drive circuit region 50 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generating circuit 33.

[0206] In the drive circuit region 50, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal. Note that FIG. 16 illustrates an example in which signals BW, CE, GW, CLK, WAKE, PON1, and PON2 are generated in the control processing region 80 and transmitted from the control processing region 80 to the drive circuit region 50.

[0207] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32 instead of the control processing area 80.

[0208] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the drive circuit region 50 and the cell array layer 60. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the drive circuit region 50 and the cell array layer 60. The control circuit 32 also generates control signals for the peripheral circuit 41 so that this operation mode is executed.

[0209] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0210] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0211] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed.

[0212] The row driver 43 has a function of selecting a write and read word line specified by the row decoder 42 (for example, any one of the wirings WL[1] to WL[m] shown in FIG. 17, which will be described later).

[0213] The column driver 45 has a function of writing data to the memory cells 10, a function of reading data from the memory cells 10, and a function of holding the read data. The column driver 45 has a function of selecting write and read bit lines (for example, wirings BL[1] to BL[n] shown in FIG. 17 , which will be described later) designated by the column decoder 44.

[0214] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 (referred to as first data in the above embodiment) is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. Note that in the above embodiment, the read data (Dout) is treated as data resulting from calculation. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the drive circuit region 50. The data output from the output circuit 48 is a signal RDA.

[0215] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the drive circuit region 50 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The signal PON1 switches the PSW22 between the ON state and the OFF state, and the signal PON2 switches the PSW23 between the ON state and the OFF state. In FIG. 16, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple power domains may also be used. In this case, a power switch may be provided for each power domain.

[0216] Next, the electrical connection between the peripheral circuit 41 and the cell array layer 60 will be described.

[0217] 17 is a block diagram showing an example of the configuration of the peripheral circuit 41 and the cell array layer 60_k. In FIG. 17, a row decoder 42 and a row driver 43 are electrically connected to the wirings WL[1] to WL[m], respectively, and a column decoder 44, a column driver 45, and a sense amplifier 46 are electrically connected to the wirings BL[1] to BL[n], respectively.

[0218] The wirings WL[1] to WL[m] function as word lines. Each of the wirings WL[1] to WL[m] may be a plurality of wirings instead of a single wiring. For example, the wirings WL may include a write word line and a read word line.

[0219] The wirings BL[1] to BL[n] function as bit lines. Each of the wirings BL[1] to BL[n] may be a plurality of wirings instead of a single wiring. For example, the wiring BL may include a write bit line and a read bit line.

[0220] The memory cell 10[i,j] arranged in the i-th row and j-th column is electrically connected to a wiring WL[i] and a wiring BL[j].

[0221] As shown in FIG. 17, by electrically connecting the cell array layer 60_k and the peripheral circuit 41, it is possible to write data to the cell array layer 60_k and read data from the cell array layer 60_k.

[0222] <Configuration Example of Cell Array Layer 60 and Cell Array 70> Next, a circuit configuration that can be applied to the cell array layer 60 or the cell array 70 will be described.

[0223] 18A shows a configuration example in which a DRAM is applied as the cell array layer 60 or the cell array 70 (hereinafter collectively referred to as the memory cell array MCA). The DRAM can be applied to one or more selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104 in the memory hierarchy 100 of FIG. 2, for example. In particular, it is preferable to apply the DRAM to the main memory 104, for example.

[0224] 18A shows only the memory cells MC located in the first row, first column, the first row, nth column, the mth row, first column, and the mth row, nth column of the memory cell array MCA having m rows and n columns. Therefore, in FIG. 18A, the wiring WL in the first row is shown as wiring WL[1], the wiring WL in the mth row is shown as wiring WL[m], the wiring BL in the first column is shown as wiring BL[1], and the wiring BL in the nth row is shown as wiring BL[n].

[0225] The memory cell MC corresponds to the memory cell 10 when the memory cell array MCA is the cell array layer 60, or corresponds to the memory cell 75 when the memory cell array MCA is the cell array 70.

[0226] In the memory cell array MCA of FIG. 18A, the memory cell MC has a transistor M1 and a capacitance element C1.

[0227] In the memory cell MC in the i-th row and j-th column (i is an integer from 1 to m, and j is an integer from 1 to n), a first terminal of the transistor M1 is electrically connected to a wiring BL[j], a second terminal of the transistor M1 is electrically connected to a first terminal of a capacitor C1, and a gate of the transistor M1 is electrically connected to a wiring WL[i]. The second terminal of the capacitor C1 is electrically connected to a wiring CL.

[0228] The wiring CL functions as, for example, a wiring that applies a constant potential. The constant potential can be a high-level potential, a low-level potential, a ground potential, or a negative potential. The wiring CL may also function as a wiring that applies a variable potential (for example, a pulse potential).

[0229] 18A, the transistor M1 is illustrated as an n-channel transistor, but the transistor M1 may be a p-channel transistor. Furthermore, not only in the memory cell array MCA of FIG. 18A, but also in other embodiments, the n-channel transistors illustrated in this specification may be replaced with p-channel transistors. Conversely, the p-channel transistors illustrated in this specification may be replaced with n-channel transistors.

[0230] The transistors described in this specification, including the transistor M1 included in the memory cell array MCA in FIG. 18A , can be Si transistors containing silicon in a channel formation region. Examples of silicon include hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single-crystal silicon. The transistors described in this specification can be OS transistors. OS transistors will be described later in this embodiment and Embodiment 3. Examples of transistors other than OS transistors and Si transistors include transistors containing germanium (Ge) or the like in a channel formation region, transistors containing a compound semiconductor such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or silicon germanium (SiGe) in a channel formation region, transistors containing carbon nanotubes in a channel formation region, and transistors containing an organic semiconductor in a channel formation region.

[0231] In particular, in an OS transistor, the metal oxide contained in the channel formation region is preferably an oxide containing one or more selected from the group consisting of indium, an element M (examples of the element M include aluminum, gallium, yttrium, tin, copper, vanadium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony), and zinc. Furthermore, the off-state current of an OS transistor containing the metal oxide in the channel formation region is preferably 10 aA (1×10) per 1 μm of channel width. −１７ A) or less, preferably 1 aA (1×10 −１８ A) or less, and more preferably 10 zA (1×10 −２０ A) or less, more preferably 1zA (1×10 −２１ A) or less, more preferably 100 yA (1×10 −２２ A) or less. Furthermore, since the carrier concentration of the metal oxide in the OS transistor is low, the off-state current of the OS transistor remains low even when the temperature of the OS transistor changes. For example, even when the temperature of the OS transistor is 150° C., the off-state current of the OS transistor can be 100 zA per 1 μm of channel width.

[0232] In particular, a DRAM using an OS transistor as the transistor M1 may be referred to as a dynamic oxide semiconductor random access memory (DOSRAM).

[0233] The capacitive element C1 may be a ferroelectric capacitor having a pair of electrodes and a ferroelectric material sandwiched between the pair of electrodes. In this case, the memory cell array MCA may be called a Ferroelectric Random Access Memory (FeRAM).

[0234] In this case, the wiring CL does not function as a wiring for supplying a constant potential, but functions as a plate line for polarizing the ferroelectric film of the ferroelectric capacitor or for reversing the polarization of the ferroelectric film.

[0235] For example, data is written to the capacitance element C1, which is a ferroelectric capacitor, by turning on the transistor M1, applying a voltage corresponding to the data to the line BL, and applying a predetermined potential to the line CL, thereby polarizing the ferroelectric film included in the capacitance element C1. Data written from the capacitance element C1 is read by turning on the transistor M1 and then applying a pulse potential to the line CL. The magnitude of the pulse potential applied to the line CL may be the same as the potential applied to the line CL during writing. When reading data stored in the capacitance element C1, the stored data is determined to be "0" or "1" depending on whether polarization reversal occurs due to the pulse potential from the line CL. When polarization reversal occurs in the ferroelectric film of the capacitance element C1, a current flows through the line BL via the transistor M1. In other words, the data stored in the capacitance element C1 can be read by obtaining the amount of current flowing through the line BL using a readout circuit, such as an integrator circuit (or a current-charge (IQ) conversion circuit) or a current-voltage conversion circuit.

[0236] <<Configuration Example 2>> The memory cell array MCA is not limited to the circuit diagram shown in Fig. 18A and may have a configuration obtained by appropriately modifying the circuit diagram of Fig. 18A. For example, as shown in Fig. 18B, in the memory cell array MCA of Fig. 18A, a back gate may be provided in the transistor M1.

[0237] Although the electrical connection of the back gate of transistor M1 is not illustrated in FIG. 18B , the connection destination of the back gate of transistor M1 can be determined depending on the desired operation or characteristics of transistor M1. For example, the back gate of transistor M1 can be electrically connected to the gate of transistor M1. By electrically connecting the gate and back gate of transistor M1, the current flowing when transistor M1 is in an on state can be increased. Furthermore, for example, a wiring for electrically connecting the back gate of transistor M1 to an external circuit can be provided to the back gate of transistor M1, and a potential can be applied to the back gate of transistor M1 from the external circuit to increase the threshold voltage. With this configuration, the off-state current of transistor M1 can be reduced by the external circuit.

[0238] In the memory cell array MCA in FIG. 18B, the transistor M1 having a back gate can be, for example, the above-described OS transistor.

[0239] 18A has been described, a back gate may be provided in a transistor included in another configuration. In other words, the transistors described in this specification and the like may be transistors having a back gate.

[0240] 18C shows a configuration example in which a ReRAM (Resistive Random Access Memory) is applied as the memory cell array MCA. Note that the ReRAM can be applied to one or more selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104 in the memory hierarchy 100 of FIG. 2, for example. In particular, it is preferable to apply the ReRAM to the main memory 104, for example.

[0241] In the memory cell array MCA of Fig. 18C, the memory cell MC has a transistor M1 and a resistance change element VR. The memory cell MC shown in Fig. 18C uses the resistance change element VR instead of the capacitance element C1 in the memory cell MC of Fig. 18A.

[0242] <<Configuration Example 4>> Fig. 18D shows a configuration example in which an MRAM (Magnetic Random Access Memory) is applied as the memory cell array MCA. Note that the MRAM can be applied to one or more selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104 in the memory hierarchy 100 of Fig. 2, for example. In particular, it is preferable to apply the MRAM to the main memory 104, for example.

[0243] 18D, the memory cell MC includes a transistor M1 and an MTJ (Magnetic Tunnel Junction) element MR. The memory cell MC shown in FIG. 18D uses the MTJ element MR instead of the capacitive element C1 in the memory cell MC of FIG. 18A.

[0244] 18E shows a configuration example in which a PRAM (Phase Change Random Access Memory) is applied as the memory cell array MCA. The PRAM can be applied to one or more selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104 in the memory hierarchy 100 of FIG. 2 . In particular, it is preferable to apply the PRAM to the main memory 104, for example.

[0245] In the memory cell array MCA of Fig. 18E, the memory cell MC has a transistor M1 and a phase change memory PCM. The memory cell MC shown in Fig. 18E uses the phase change memory PCM instead of the capacitive element C1 in the memory cell MC of Fig. 18A.

[0246] In the manufacturing process, the phase change memory PCM included in the PRAM can be manufactured by replacing the dielectric material of the capacitance element C1 used in the DRAM with a phase change material. In other words, the PRAM can be manufactured by using DRAM manufacturing equipment.

[0247] 19A shows an example of a memory cell array MCA including memory cells each having a two-transistor, one-capacitor configuration. Note that the memory cell array MCA shown in Fig. 19A can be applied to, for example, one or more of the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104 in the memory hierarchy 100 of Fig. 2.

[0248] 19A shows only the memory cells MC located in the first row, first column, the first row, nth column, the mth row, first column, and the mth row, nth column of the memory cell array MCA having m rows and n columns. Therefore, in FIG. 19A, the wires located in the first column are shown as wire RBL[1], wire WBL[1], and wire SL[1], the wires located in the mth column are shown as wire RBL[n], wire WBL[n], and wire SL[n], the wires located in the first row are shown as wire WL[1] and wire RWL[1], and the wires located in the mth row are shown as wire WL[m] and wire RWL[m].

[0249] The memory cell MC includes a transistor M2, a transistor M3, and a capacitance element C2.

[0250] The transistors M2 and M3 can be, for example, transistors that can be used for the transistor M1.

[0251] In particular, when an OS transistor is used as the transistor M2, a semiconductor device including the memory cell MC illustrated in FIG. 19A can be called a nonvolatile oxide semiconductor random access memory (NOSRAM).

[0252] In the memory cell MC in the i-th row and j-th column, the first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor C2, the second terminal of the transistor M2 is electrically connected to the wiring WBL[j], and the gate of the transistor M2 is electrically connected to the wiring WWL[i]. The second terminal of the capacitor C2 is electrically connected to the wiring RWL[i]. The first terminal of the transistor M3 is electrically connected to the wiring RBL[j], the second terminal of the transistor M3 is electrically connected to the wiring SL[j], and the gate of the transistor M3 is electrically connected to the first terminal of the capacitor C2. Note that the wiring WWL[i], wiring RWL[i], wiring RBL[j], wiring WBL[j], and wiring SL[j] are not shown in FIG. 19A .

[0253] The wiring WBL[j] functions as a write bit line, the wiring RBL[j] functions as a read bit line, and each of the wiring WBL[j] and the wiring RBL[j] corresponds to the wiring BL shown in Fig. 17. The wiring WWL[i] functions as a write word line, the wiring RWL[i] functions as a read word line, and each of the wiring WWL[i] and the wiring RWL[i] corresponds to the wiring WL shown in Fig. 17.

[0254] When writing and reading data, a constant potential such as a high-level potential is preferably applied to the wiring RWL[i]. When storing data, a constant potential such as a low-level potential is preferably applied to the wiring RWL[i].

[0255] The wiring SL[j] functions as a wiring that applies a predetermined potential when data is read from the memory cell MC.

[0256] When writing data to the memory cell MC in the i-th row and j-th column, a high-level potential is applied to the wiring WWL[i] to turn on the transistor M2, i.e., to establish electrical continuity between the wiring WBL[j] and the first terminal of the capacitor C2 of each memory cell MC. At this time, a high-level potential is preferably applied to the wiring RWL[i]. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL[j], and the potential is written to the first terminal of the capacitor C2 and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WL[i] to turn off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor C2 and the gate of the transistor M3. The potential of the wiring RWL[i] is then changed from high to low, lowering the gate potential of the transistor M3 through capacitive coupling of the capacitor C2 and turning off the transistor M3.

[0257] Data is read from the memory cell MC in the i-th row and j-th column by applying a high-level potential to the wiring RWL[i] and a predetermined potential to the wiring SL[j]. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, by reading the potential of the wiring RBL[j] connected to the first terminal of the transistor M3, the potential held in the first terminal of the capacitor C2 (or the gate of the transistor M3) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor C2 (or the gate of the transistor M3).

[0258] 17 is not limited to the memory cell MC shown in FIG. 19A. The memory cell MC shown in FIG. 19A can have circuits removed or the circuit connections changed depending on the situation. For example, transistors provided with back gates may be applied to the transistors M2 and M3.

[0259] 19A, the wiring WBL[j] and the wiring RBL[j] may be combined into a single wiring. The memory cell array MCA shown in FIG. 19B has a configuration in which the wiring WBL[j] and the wiring RBL[j] in the memory cell array MCA of FIG. 19A are combined into a single wiring BL[j]. By combining multiple wirings into a single wiring, the circuit area of ​​the memory cell array MCA can be reduced.

[0260] Furthermore, the circuit configuration of the memory cell MC shown in Fig. 19A may be changed to the memory cell MC shown in Fig. 19C. The memory cell MC shown in Fig. 19C differs from the memory cell MC in Fig. 19A in that it includes a transistor M6.

[0261] In the memory cell MC in the i-th row and j-th column, the first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor C2, the second terminal of the transistor M2 is electrically connected to the wiring WBL[j], and the gate of the transistor M2 is electrically connected to the wiring WWL[i]. The second terminal of the capacitor C2 is electrically connected to the wiring CL[i]. The first terminal of the transistor M3 is electrically connected to the first terminal of the transistor M6, the second terminal of the transistor M3 is electrically connected to the wiring SL[j], and the gate of the transistor M3 is electrically connected to the first terminal of the capacitor C2. The second terminal of the transistor M6 is electrically connected to the wiring RBL[j], and the gate of the transistor M6 is electrically connected to the wiring RWL[j]. Note that the wiring WWL[i], wiring RWL[i], wiring CL[i], wiring RBL[j], wiring WBL[j], and wiring SL[j] are not shown in FIG. 19C .

[0262] The wiring CL[i] functions as, for example, a wiring that applies a constant potential. The constant potential can be a high-level potential, a low-level potential, a ground potential, or a negative potential. Note that the wiring CL[i] may also function as a wiring that applies a variable potential (for example, a pulse potential).

[0263] 19C, the transistor M6 functions as a read transistor. Note that the transistor M6 can be a transistor that can be used as the transistor M2 or the transistor M3.

[0264] In addition, in the memory cell MC of Figure 19A, the wiring RWL[i] that functions as a read word line is electrically connected to the second terminal of the capacitance element C2, while in the memory cell MC of Figure 19C, the wiring CL[i] that serves as a wiring that applies a constant potential is electrically connected to the second terminal of the capacitance element C2.

[0265] 19A, the read operation is performed by changing the gate potential of transistor M3 through capacitive coupling by capacitive element C2, so a read failure may occur if the gate potential of transistor M3 does not change correctly due to parasitic capacitance, etc. On the other hand, in the memory cell MC of FIG. 19C, the gate potential of transistor M3 is not changed through capacitive coupling by capacitive element C2, so the above-mentioned read failure does not occur.

[0266] 20A shows an example of an SRAM that can be applied to the memory cells MC of the memory cell array MCA. The SRAM can be applied to one or more selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104 in the memory hierarchy 100 of FIG. 2 . In particular, it is preferable to apply the SRAM to the register 101, the first cache memory 102, and the second cache memory 103, for example.

[0267] The memory cell MC includes a transistor M4, a transistor M4r, a logic circuit INV1, and a logic circuit INV2.

[0268] The transistor M4 and the transistor M4r can be, for example, a transistor that can be used as the transistor M1.

[0269] The logic circuits INV1 and INV2 have a function of generating and outputting an inverted signal of a signal input to the circuit. For example, inverter circuits can be used as the logic circuits INV1 and INV2. Other than inverter circuits, logic circuits such as NAND circuits, NOR circuits, XOR circuits, or combinations of these can also be used.

[0270] A first terminal of the transistor M4 is electrically connected to the wiring BL, a second terminal of the transistor M4 is electrically connected to the input terminal of the logic circuit INV1 and the output terminal of the logic circuit INV2, and a gate of the transistor M4 is electrically connected to the wiring WL. A first terminal of the transistor M4r is electrically connected to the wiring BLB, a second terminal of the transistor M4r is electrically connected to the output terminal of the logic circuit INV1 and the input terminal of the logic circuit INV2, and a gate of the transistor M4r is electrically connected to the wiring WL.

[0271] The high-power input terminals of the logic circuits INV1 and INV2 are electrically connected to a wiring C1L, and the low-power input terminals of the logic circuits INV1 and INV2 are electrically connected to a wiring C2L. The wiring C1L functions as a wiring that applies a high-level potential, and the wiring C2L functions as a wiring that applies a low-level potential. Note that the wirings C1L and C2L may be wirings that apply a variable potential instead of a constant potential.

[0272] Data is written by applying a high-level potential to the wiring WL, turning on the transistor M4 and establishing electrical continuity between the wiring BL and the input terminal of the logic circuit INV1 and the output terminal of the logic circuit INV2. At this time, the transistor M4r is also turned on, establishing electrical continuity between the wiring BLB and the output terminal of the logic circuit INV1 and the input terminal of the logic circuit INV2. Therefore, when writing data to the memory cell MC, write data signals can be transmitted from the wiring BL and the wiring BLB. The write data signal input to the wiring BL is preferably an inverted signal of the signal input to the wiring BLB. The wirings BL and BLB correspond to the wiring BL shown in FIG. 17, and the wiring WL corresponds to the wiring WL shown in FIG. 17.

[0273] Furthermore, the memory cell MC shown in Figure 17 is not limited to the memory cell MC shown in Figure 20A. The memory cell MC shown in Figure 20A can have circuits added or removed, and the circuit connections can be changed depending on the situation. For example, as shown in Figure 20B, the memory cell MC of Figure 20A may be configured to include a transistor M5, a transistor M5r, a capacitive element C3, and a capacitive element C3r.

[0274] The transistor M5 and the transistor M5r can be, for example, a transistor that can be used as the transistor M1.

[0275] The first terminal of the transistor M5 is electrically connected to the second terminal of the transistor M4, the input terminal of the logic circuit INV1, and the output terminal of the logic circuit INV2. The second terminal of the transistor M5 is electrically connected to the first terminal of the capacitor C3, and the gate of the transistor M5 is electrically connected to the wiring W2L. The first terminal of the transistor M5r is electrically connected to the second terminal of the transistor M4, the input terminal of the logic circuit INV1, and the output terminal of the logic circuit INV2. The second terminal of the transistor M5r is electrically connected to the first terminal of the capacitor C3r, and the gate of the transistor M5r is electrically connected to the wiring W2L. The second terminals of the capacitors C3 and C3r are electrically connected to the wiring CL.

[0276] 20B corresponds to the wiring WL in FIG. 20A. The wiring W2L functions as a second word line and switches the transistors M5 and M5r between the on state and the off state. The wiring W1L and the wiring W2L correspond to the wiring WL shown in FIG. 17.

[0277] The wiring CL functions as a wiring for applying a constant potential to the second terminals of the capacitors C3 and C3r. The constant potential can be a high-level potential, a low-level potential, a ground potential, or a negative potential. The wiring CL may also function as a wiring for applying a variable potential (e.g., a pulse potential).

[0278] By turning on the transistors M5 and M5r via the wiring W2L, electrical continuity is established between the second terminal of the transistor M4 and the first terminal of the capacitor C3, and electrical continuity is established between the second terminal of the transistor M4r and the first terminal of the capacitor C3r. As a result, the potentials of the input terminal of the logic circuit INV1 and the output terminal of the logic circuit INV2 are written to the first terminal of the capacitor C3, and the potentials of the output terminal of the logic circuit INV1 and the input terminal of the logic circuit INV2 are written to the first terminal of the capacitor C3r. Thereafter, by turning off the transistors M5 and M5r via the wiring W2L, the first terminals of the capacitors C3 and C3r can be brought into a floating state, and the potentials written to the first terminals of the capacitors C3 and C3r can be maintained. At this time, even if the supply of voltage from the wirings C1L and C2L is temporarily stopped and the driving of the logic circuits INV1 and INV2 is stopped, data can be retained by the transistors M5, M5r, the capacitors C3, and C3r.

[0279] 21 shows a cross-sectional configuration example of a semiconductor device DEV according to one embodiment of the present invention. The semiconductor device DEV shown in FIG. 21 includes a circuit layer 90 and a plurality of cell array layers 60 (corresponding to the memory layer MEML_L in FIG. 1 described in Embodiment 1) above a driver circuit region 50 and a control processing region 80. The plurality of cell array layers 60 are located above the circuit layer 90.

[0280] 21 illustrates a transistor 400 included in the driver circuit region 50. The transistor 400 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 400 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a semiconductor substrate (particularly, a single-crystal substrate made of silicon).

[0281] The substrate 311 may be a single-crystal substrate made of germanium. In addition to semiconductor substrates, other materials that can be used include, for example, an SOI (silicon-on-insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, and a paper or base film containing a fibrous material. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. When a heat treatment is included in the manufacturing process of the semiconductor device DEV, it is preferable to select a material with high heat resistance for the substrate.

[0282] Here, in the transistor 400 shown in FIG. 21 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI (Silicon On Insulator) substrate.

[0283] Note that the transistor 400 illustrated in FIG. 21 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0284] A wiring layer having an interlayer film, wiring, and plugs may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug may be integral. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0285] For example, an insulator 320, an insulator 301, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 400. A conductor 328 or the like is embedded in the insulator 320 and the insulator 301. A conductor 330 or the like is embedded in the insulator 324 and the insulator 326. The conductors 328 and 330 function as contact plugs or wirings.

[0286] The materials for each plug and wiring (conductor 328 and conductor 330) can be one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Furthermore, it is preferable to use a low-resistance conductive material such as aluminum or copper as the material. The use of a low-resistance conductive material can reduce the wiring resistance.

[0287] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 301 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0288] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 22 , an insulator 350, an insulator 357, and an insulator 352 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 functions as a contact plug or a wiring. Furthermore, a material that can be used for the conductor 328 or the conductor 330 can be used for the conductor 356.

[0289] The circuit layer 90 includes, as an example, a transistor MN. As an example, the transistor MN may be a transistor included in the circuit layer SWCL described in embodiment 1. For example, the transistor included in the circuit layer SWCL may be a transistor included in a switch included in the circuit layer SWCL.

[0290] As the transistor MN, for example, a transistor applicable to the transistor M1 can be used.

[0291] 21 , a conductor 361 and the like are provided on the conductor 356. A conductor 362 is embedded in the circuit layer 90, and a conductor 540a and a conductor 540b are provided on each of a pair of low-resistance regions of the transistor MN in the circuit layer 90. A conductor 363a and a conductor 363b are provided above the transistor MN. The conductors 361, 362, 363a, and 363b function as contact plugs or wiring.

[0292] Each of the multiple cell array layers 60 has multiple memory cells MC. Note that the memory cells MC shown in Fig. 21 are the memory cells MC shown in Fig. 18B as an example. Therefore, each of the memory cells MC shown in Fig. 21 includes a transistor M1 and a capacitance element C1.

[0293] Furthermore, a conductor 502 is embedded in the interlayer film between the circuit layer 90 and the cell array layer 60_1. Furthermore, in each of the multiple cell array layers 60, a conductor 503 is embedded in insulators 514, 516, and 520, which will be described later. Note that the conductor 503 may be embedded in a portion of the conductor 502. The conductors 502 and 503 function as contact plugs or wiring. Furthermore, a conductor functioning as a contact plug or wiring for electrically connecting to the memory cells MC of the upper cell array layer 60 is embedded in each of the multiple cell array layers 60. Furthermore, in each of the multiple cell array layers 60, a conductor 504 is embedded in insulators 520, 522, conductor 542b, insulator 554, insulator 580, and insulator 574, which will be described later. Note that the insulator 574 may be an insulating film made of the same material as the insulator 514. The conductors 502, 503, and 504 function as contact plugs or wirings.

[0294] 21 , as an example, a transistor MN in the circuit layer 90 is electrically connected to a transistor M1 included in a memory cell MC in the cell array layer 60_1 via a conductor 540a, a conductor 363b, a conductor 502, and a conductor 503. In particular, the transistor MN and the transistor M1 are electrically connected to each other by contact between the conductor 503 and a conductor 542a or a conductor 542b, which will be described later.

[0295] In FIG. 21, one transistor MN is provided on the electrical path between the transistor 400 included in the drive circuit region 50 and the control processing region 80 and the transistor M1 included in the memory cell MC of the cell array layer 60_1, but multiple transistors MN may be provided on the electrical path depending on the situation.

[0296] Furthermore, the semiconductor device DEV in Figure 21 has a configuration in which multiple cell array layers 60 are stacked in order from the bottom up, but the cell array included in the semiconductor device DEV may also be formed in the stacking direction as shown in Figure 22.

[0297] In the semiconductor device DEV of FIG. 22 , a conductor 502 is embedded in the interlayer film between the circuit layer 90 and the cell array layer 60_1. Furthermore, in each of the multiple cell array layers 60, a conductor 503 is embedded in an insulator 514 and an insulator 516, which will be described later. Note that the conductor 503 may be embedded in a portion of the conductor 502. Furthermore, in each of the multiple cell array layers 60, a conductor 504 is embedded in an insulator 520, an insulator 522, a conductor 542b, an insulator 554, an insulator 580, and an insulator 574, which will be described later. Note that the insulator 574 may be an insulating film made of the same material as the insulator 514. The conductors 502, 503, and 504 function as contact plugs or wiring.

[0298] 22 , as an example, the transistor MN of the circuit layer 90 is electrically connected to the transistor M1 included in each memory cell MC of the plurality of cell array layers 60 via the conductor 540a, the conductor 363b, the conductor 502, the conductor 503, and the conductor 504. In particular, the transistor MN and the transistor M1 are electrically connected to each other by the conductor 504 coming into contact with the conductor 542b described later.

[0299] <<Configuration Example of Transistor>> Next, configuration examples of the transistor M1 and the transistor MN shown in FIGS. 21 and 22 will be described.

[0300] 23A and 23B are applicable to the transistors M1 and MN of the semiconductor device DEV, and Fig. 23A in particular shows a schematic cross-sectional view of the transistor 500 in the channel length direction, and Fig. 23B shows a schematic cross-sectional view of the transistor 500 in the channel width direction. Note that Fig. 23A and 23B show a configuration in which the transistor 500 is provided over an insulator 512.

[0301] 23A and 23B can be used for the transistor MN of the semiconductor device DEV. Also, for example, the configuration of the transistor 500 shown in FIG. 25, which is a modification of FIG. 23A, can be used for the transistor M1 of the semiconductor device DEV. In particular, it is preferable that the transistor M1 provided in the cell array layer 60 use the configuration of the transistor 500 shown in FIG. 25 in order to be electrically connected to the conductor 504.

[0302] 23A and 23B , for example, the transistor 500 includes a metal oxide 531a, a metal oxide 531b, a conductor 505, a conductor 542a, a conductor 542b, an insulator 580, a conductor 560, an insulator 514, an insulator 516, an insulator 520, an insulator 522, an insulator 524, an insulator 550, an insulator 554, an insulator 574, an insulator 580, and an insulator 581. Note that the transistor 500 does not necessarily include all of the above-described components. For example, the transistor 500 may not include the insulator 520.

[0303] The conductor 505 (conductor 505a and conductor 505b) and the insulator 516 are disposed above a substrate (not shown). In particular, the conductor 505 is preferably embedded in the insulator 516. Specifically, the conductor 505a is preferably provided in contact with the bottom surface and sidewall of an opening provided in the insulator 516. The conductor 505b is preferably provided so as to be embedded in a recess formed in the conductor 505a. Note that in the transistor 500 shown in FIGS. 23A and 23B , the height of the top surface of the conductor 505b is approximately the same as the height of the top surface of the conductor 505a and the height of the top surface of the insulator 516.

[0304] The metal oxide 531 and the conductor 560 are arranged in a region overlapping the conductor 505. The metal oxide 531b is arranged on the metal oxide 531a. The conductors 542a and 542b are arranged on the metal oxide 531b, spaced apart from each other. The insulator 580 is arranged on the conductors 542a and 542b. In particular, an opening is formed in the insulator 580 in a region between the conductors 542a and 542b. The conductor 560 is arranged in this opening. The insulator 550 is arranged between the metal oxide 531b, the conductors 542a and 542b, and the insulator 580 and the conductor 560. Here, as shown in FIGS. 23A and 23B , it is preferable that the top surface of the conductor 560 approximately coincides with the top surfaces of the insulators 550 and 580. Note that below, the conductors 505a and 505b may be collectively referred to as the conductors 505. The metal oxides 531a and 531b may be collectively referred to as the metal oxides 531. The conductors 542a and 542b may be collectively referred to as the conductors 542.

[0305] 23A , a region 543a may be formed as a low-resistance region at the interface between the metal oxide 531b and the conductor 542a and in its vicinity. Similarly, a region 543b may be formed as a low-resistance region at the interface between the metal oxide 531b and the conductor 542b and in its vicinity. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0306] By providing the conductor 542a (conductor 542b) so as to be in contact with the metal oxide 531, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the metal oxide 531 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0307] 23A and 23B , the side surfaces of the conductors 542a and 542b facing the conductor 560 have a substantially vertical shape. Note that the transistor 500 shown in FIGS. 23A and 23B is not limited to this, and the angle between the side surface and the bottom surface of the conductors 542a and 542b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductors 542a and 542b may have multiple surfaces.

[0308] Note that the transistor 500 has a structure in which two layers of the metal oxide 531a and the metal oxide 531b are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof; however, the present invention is not limited to this. For example, the metal oxide 531b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 531a and the metal oxide 531b may have a stacked structure of two or more layers.

[0309] Here, the conductor 560 functions as a first gate electrode (sometimes referred to as a gate electrode, a top gate electrode, or a front gate electrode) of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. Here, the arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the first gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 500. This enables a high-resolution display device. Furthermore, the display device can have a narrow frame.

[0310] The conductor 505 may function as a second gate electrode (which may also be referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductor 505 may be changed independently of the potential applied to the conductor 560, thereby reducing the threshold voltage V ｔｈ In particular, applying a negative potential to the conductor 505 can control the V ｔｈ Therefore, when a negative potential is applied to the conductor 505, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when no negative potential is applied.

[0311] The conductor 505 is preferably larger than the channel formation region of the metal oxide 531. In particular, as shown in Fig. 23B, the conductor 505 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the metal oxide 531. In other words, outside the side surface of the metal oxide 531 in the channel width direction, the conductor 505 and the conductor 560 preferably overlap with each other with an insulator interposed therebetween.

[0312] 23A, the conductor 560 preferably includes a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Although the conductor 560 is shown as having a two-layer laminated structure in FIGS. 23A and 23B, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.

[0313] 23A and 23B , the transistor 500 preferably includes an insulator 512 disposed on a substrate (not shown), an insulator 514 disposed on the insulator 512, an insulator 516 disposed on the insulator 514, a conductor 505 disposed so as to be embedded in the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 505, an insulator 522 disposed on the insulator 520, and an insulator 524 disposed on the insulator 522. A metal oxide 531 a is preferably disposed on the insulator 524.

[0314] 23A and 23B, it is preferable that an insulator 554 be disposed among the insulator 522, the insulator 524, the metal oxide 531a, the metal oxide 531b, the conductor 542a, the conductor 542b, and the insulator 580. Here, it is preferable that the insulator 554 be in contact with the side surface of the insulator 550, the top and side surfaces of the conductor 542a, the top and side surfaces of the conductor 542b, the metal oxide 531a, the metal oxide 531b, the side surface and top surface of the insulator 524, and the top surface of the insulator 522, as shown in FIG.

[0315] An insulator 574 and an insulator 581 functioning as interlayer films are preferably provided over the transistor 500. Here, the insulator 574 is preferably provided in contact with the top surfaces of the conductor 560, the insulator 550, and the insulator 580. In this case, the top surface of the insulator 580 is preferably planarized.

[0316] It is preferable to provide a conductor 540 (conductor 540a and conductor 540b) that is electrically connected to the transistor 500 and functions as a plug. For this reason, the conductor 540 is provided in contact with the inner walls of the openings of the insulators 554, 580, 574, and 581. In particular, a first conductor of the conductor 540 may be provided in contact with the inner walls, and a second conductor of the conductor 540 may be provided on a side surface of the first conductor. Here, the height of the top surface of the conductor 540 and the height of the top surface of the insulator 581 can be made approximately the same.

[0317] Specifically, for example, a first conductor of conductor 540a is provided in contact with the inner wall of one of the two openings of insulators 581, 574, 580, and 554, and a second conductor of conductor 540a is formed in contact with the side surface thereof. Note that conductor 542a is located in part of the bottom of the opening, and conductor 540a is in contact with conductor 542a. Similarly, for example, a first conductor of conductor 540b is provided in contact with the inner wall of the other of the two openings of insulators 581, 574, 580, and 554, and a second conductor of conductor 540b is formed in contact with the side surface thereof. Note that conductor 542b is located in part of the bottom of the opening, and conductor 540b is in contact with conductor 542b.

[0318] Note that, although the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, the present invention is not limited to this. For example, the conductor 540 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0319] 23B , in a region of the metal oxide 531b that does not overlap with the conductor 542, in other words, in the channel formation region of the metal oxide 531, the side surfaces of the metal oxide 531 are arranged to be covered with the conductor 560. This makes it easier for the electric field of the conductor 560, which functions as a first gate electrode, to act on the side surfaces of the metal oxide 531, and as a result, the channel formation region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560. This increases the on-state current of the transistor 500 and improves its frequency characteristics.

[0320] Note that the structure of a transistor in a semiconductor device of one embodiment of the present invention is not limited to the transistor 500 illustrated in Fig. 23A . For example, the transistor included in the semiconductor device DEV may have a structure in Fig. 23A in which the conductor 542a and the conductor 542b are formed not only over the metal oxide 531b but also on the side surface of the metal oxide 531a, the side surface of the insulator 524, and the top surface of the insulator 522 (see Fig. 25 ).

[0321] <<Constituent Materials of Transistor>> Next, constituent materials that can be used for the transistor 500 will be described.

[0322] [Metal Oxide (Oxide Semiconductor)] The transistor 500 preferably uses a metal oxide that functions as an oxide semiconductor for the metal oxide 531 (the metal oxide 531a and the metal oxide 531b) including the channel formation region. For example, the metal oxide that serves as the channel formation region of the metal oxide 531 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more.

[0323] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition to these, it is preferable that it contains element M. As element M, one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used. In particular, element M is preferably one or more of aluminum, gallium, yttrium, and tin. Furthermore, it is more preferable that element M contains one or both of gallium and tin.

[0324] As described above, the metal oxide 531 includes the metal oxide 531a and the metal oxide 531b on the metal oxide 531a. By providing the metal oxide 531a below the metal oxide 531b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 531a to the metal oxide 531b.

[0325] Furthermore, the metal oxide 531 preferably has a stacked structure of multiple oxide layers with different atomic ratios of the respective metal atoms. For example, when the metal oxide 531 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 531a to the number of atoms of all elements constituting the metal oxide 531a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 531b to the number of atoms of all elements constituting the metal oxide 531b. Furthermore, the atomic ratio of the element M contained in the metal oxide 531a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 531b to In.

[0326] The energy of the conduction band minimum of the metal oxide 531a is preferably higher than the energy of the conduction band minimum of the metal oxide 531b. In other words, the electron affinity of the metal oxide 531a is preferably smaller than the electron affinity of the metal oxide 531b.

[0327] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxide 531a and the metal oxide 531b. In other words, the energy level of the conduction band minimum at the junction between the metal oxide 531a and the metal oxide 531b changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 531a and the metal oxide 531b.

[0328] Specifically, when the metal oxide 531a and the metal oxide 531b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the metal oxide 531b is an In—Ga—Zn oxide (indium-gallium-zinc oxide), the metal oxide 531a can be an In—Ga—Zn oxide, a Ga—Zn oxide, or a gallium oxide.

[0329] Specifically, the metal oxide 531a may have an atomic ratio of In:Ga:Zn=1:3:4, 1:3:2, or 1:1:0.5, and the metal oxide 531b may have an atomic ratio of In:Ga:Zn=1:1:1, 4:2:3, or 3:1:2.

[0330] In this case, the main carrier path is the metal oxide 531b. By configuring the metal oxide 531a as described above, the defect state density at the interface between the metal oxide 531a and the metal oxide 531b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve high on-state current and high frequency characteristics.

[0331] Furthermore, by providing the conductor 542 so as to be in contact with the metal oxide 531, the oxygen concentration may be reduced in the vicinity of the conductor 542 of the metal oxide 531. Furthermore, a metal compound layer containing a metal contained in the conductor 542 and components of the metal oxide 531 may be formed in the vicinity of the conductor 542 of the metal oxide 531. In such a case, the carrier density increases in the region of the metal oxide 531 in the vicinity of the conductor 542, and the region becomes a low-resistance region.

[0332] Incidentally, the thickness of the metal oxide 531b in a region that does not overlap with the conductor 542 may be thinner than the thickness of the region that overlaps with the conductor 542. This is formed by removing part of the top surface of the metal oxide 531b when forming the conductors 542a and 542b. When a conductive film that will become the conductor 542 is formed on the top surface of the metal oxide 531b, a low-resistance region may be formed near the interface with the conductive film. In this way, removing the low-resistance region located between the conductors 542a and 542b on the top surface of the metal oxide 531b can prevent a channel from being formed in that region.

[0333] [Conductor] For the conductor, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing two or more of the above metal elements, is preferably used. For the conductor, for example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. The conductor may be a semiconductor with high electrical conductivity, such as polycrystalline silicon containing an impurity element (such as phosphorus), or a silicide (such as nickel silicide).

[0334] A plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0335] The conductor 505a, which functions as the second gate electrode, is a material containing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (e.g., N ２ O, NO or NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms, or a conductive material that has a function of suppressing the diffusion of oxygen (for example, oxygen atoms and / or oxygen molecules).

[0336] By using a conductive material that can reduce hydrogen diffusion for the conductor 505a, it is possible to prevent impurities such as hydrogen contained in the conductor 505b from diffusing to the metal oxide 531 via the insulator 524. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 505a, it is possible to prevent the conductor 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 505a may be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride may be used for the conductor 505a.

[0337] The conductor 505b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0338] The conductor 542 (conductor 542a and conductor 542b) functioning as a source electrode or a drain electrode is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing two or more selected from the above metal elements. For example, the conductor 542 is preferably made of tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0339] The conductor 560a, which functions as the first gate electrode, is made of the above-mentioned hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO or NO ２ It is preferable to use a conductor that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms, or a conductive material that has a function of suppressing the diffusion of oxygen (for example, oxygen atoms and / or oxygen molecules).

[0340] The conductor 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductor 560b caused by oxygen contained in the insulator 550. Examples of conductive materials that have a function of suppressing oxygen diffusion include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Furthermore, by providing a conductive material containing oxygen as the conductor 560a, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0341] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0342] The conductor 560 may be made of, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon. For example, the conductor may be made of indium gallium zinc oxide containing nitrogen. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0343] Although the conductor 560 is shown as having a two-layer structure in FIGS. 23A and 23B, it may have a single-layer structure or a laminated structure of three or more layers.

[0344] The conductors 540a and 540b, which function as plugs, are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0345] When the conductor 540 has a layered structure, the conductors in contact with the conductor 542, the insulator 554, the insulator 580, the insulator 574, and the insulator 581 preferably have the above-described function of suppressing the diffusion of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used for the conductor. Furthermore, a conductive material that suppresses the diffusion of impurities such as water and hydrogen may be used in a single-layer structure or a layered structure. The use of such a conductive material can suppress the absorption of oxygen added to the insulator 580 by the conductors 540a and 540b. Furthermore, impurities such as water and hydrogen from layers above the insulator 581 can be suppressed from entering the metal oxide 531 through the conductors 540a and 540b.

[0346] Similarly, the materials that can be applied to conductor 540a or conductor 540b can be used for each of conductor 361, conductor 362, conductor 363a, conductor 363b, conductor 502, conductor 503, and conductor 504, which function as contact plugs or wirings.

[0347] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0348] The insulator 514 preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the transistor 500 from the substrate side. Therefore, the insulator 514 does not contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, or nitrogen oxide molecules (for example, N ２ O, NO or NO２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., impermeability of the impurities is low). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., impermeability of the oxygen is low).

[0349] Examples of insulators that suppress the permeation of impurities such as water and hydrogen and oxygen include, for example, insulators containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and may be used in a single layer or a multilayer configuration. Specifically, examples of insulators that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulators that suppress the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, examples of insulators that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0350] In particular, it is preferable to use aluminum oxide or silicon nitride for the insulator 514. This can prevent impurities such as water and hydrogen from diffusing from the substrate side of the insulator 514 to the transistor 500 side. Alternatively, it can prevent oxygen contained in the insulator 524 or the like from diffusing to the substrate side of the insulator 514.

[0351] The insulators 520, 522, and 524 function as a second gate insulator.

[0352] Here, oxygen is preferably released from the second gate insulator in contact with the metal oxide 531 by heating. In this specification and the like, oxygen released by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride may be used as appropriate for the insulator 524 that functions as the second gate insulator. By providing an insulator containing oxygen in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be reduced and the reliability of the transistor 500 can be improved.

[0353] Specifically, an oxide material from which some oxygen is released by heating is preferably used as the insulator 524. The oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen converted into oxygen atoms by thermal desorption spectrometry (TDS) is 1.0×10 １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0×10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0354] Like the insulator 514, the insulator 522 preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the transistor 500 from the substrate side. For example, the insulator 522 preferably has lower hydrogen permeability than the insulator 524.

[0355] Furthermore, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., the oxygen is less likely to permeate). For example, the insulator 522 preferably has lower oxygen permeability than the insulator 524. The insulator 522 preferably has a function of suppressing the diffusion of oxygen, which can reduce the diffusion of oxygen contained in the metal oxide 531 toward the substrate. Furthermore, the conductor 505 can be prevented from reacting with oxygen contained in the insulator 524 and the metal oxide 531.

[0356] The insulator 522 may be an insulator containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Examples of insulators containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the metal oxide 531 and the intrusion of impurities, such as hydrogen, into the metal oxide 531 from the periphery of the transistor 500.

[0357] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0358] The insulator 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３A single layer or a stack of insulators containing so-called high-k materials such as BST (Bistella tetragonal silicon dioxide) may be used. Alternatively, the insulator 522 may be an insulator with a high dielectric constant, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. As transistors become more miniaturized or highly integrated, problems such as leakage current due to thinning of the gate insulator may occur. Using a high-k material as the insulator functioning as the gate insulator allows the gate potential during transistor operation to be reduced while maintaining the physical film thickness.

[0359] The insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant. Furthermore, the insulator 520 may be made of a material that can be used for the insulator 524.

[0360] Note that one or more selected from the insulator 520, the insulator 522, and the insulator 524 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being made of the same material, and may be made of different materials.

[0361] The insulators 512, 516, 580, and 581, which function as interlayer films, preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. Furthermore, the insulators 516, 580, and 581 preferably have reduced concentrations of impurities such as water and hydrogen.

[0362] The insulators 512, 516, 580, and 581 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. The insulators 512, 516, 580, and 581 can be formed using, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. The insulators 512, 516, 580, and 581 can be formed using resin. The materials that can be used for the insulators 512, 516, 580, and 581 may be an appropriate combination of the above-mentioned materials.

[0363] Like the insulators 514 and 522, the insulators 554 and 574 preferably have a function of suppressing diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and / or hydrogen molecules). That is, the insulators 554 and 574 preferably function as barrier insulating films that suppress entry of the impurities into the transistor 500. The insulators 554 and 574 preferably have a function of suppressing diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). For example, the insulators 554 and 574 preferably have lower oxygen permeability than the insulators 524, 550, and 580. That is, the insulators 554 and 574 preferably have a function of suppressing oxygen from being released from the metal oxide 531 and diffusing outside the insulator 554 or above the insulator 580. Therefore, the insulators 554 and 574 can be formed using a material that can be used for the insulator 514 or the insulator 524.

[0364] In this manner, the insulator 524, the metal oxide 531, and the insulator 550 are surrounded by the insulators 522, 554, and 574, which can prevent impurities such as water and hydrogen from entering the transistor 500 from the outside. Furthermore, the diffusion of oxygen from the inside to the outside of the transistor 500 can be prevented.

[0365] The insulator 550 functions as a first gate insulator. The insulator 550 is preferably disposed in contact with the top surface of the metal oxide 531b. The insulator 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

[0366] The insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen, similar to the insulator 524. The thickness of the insulator 550 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

[0367] Note that an insulator may be provided between the insulator 580, the insulator 554, the conductor 542, and the metal oxide 531b and the insulator 550. For example, aluminum oxide or hafnium oxide is preferably used as the insulator. Providing the insulator can suppress release of oxygen from the metal oxide 531b, excessive supply of oxygen to the metal oxide 531b, and oxidation of the conductor 542.

[0368] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. This can suppress oxidation of the conductor 560 due to oxygen in the insulator 550.

[0369] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 550, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 550 and the metal oxide, a stacked structure that is stable against heat and has a high dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0370] Specifically, the metal oxide may be, for example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium. In particular, it is preferable to use, as the metal oxide, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing oxides of either or both of aluminum and hafnium.

[0371] Note that a barrier insulating film against impurities such as water, hydrogen, and oxygen may be provided between the conductor 540 and the insulator 580, the insulator 574, and the insulator 581. This can prevent water and impurities from being mixed into the metal oxide 531 from the insulator 580 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0372] Although not shown, a conductor functioning as wiring may be disposed so as to contact the upper surface of the conductor 540a and the upper surface of the conductor 540b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0373] <<Configuration Example of Capacitor Element>> Next, a configuration example of the capacitative element C1 shown in FIGS. 21 and 22 will be described.

[0374] 25 shows a configuration example of a capacitor 600 as the capacitor C1. In addition to the capacitor 600, a configuration example of a transistor 500 is also shown in FIG.

[0375] 25 , an opening in the insulator 580 is provided in a region over the insulator 554 that overlaps with the conductor 542a functioning as a source electrode or drain electrode of the transistor 500. Note that the region may be partially overlapped with the insulator 524 and the metal oxide 531.

[0376] An insulator 552 is formed on the insulator 580 on the side surface of the opening and on the insulator 554 on the bottom surface of the opening. Furthermore, a conductor 561a and a conductor 561b are formed in this order on the insulator 552. Note that in this specification and the like, the conductor 561a and the conductor 561b may be collectively referred to as the conductor 561.

[0377] The conductor 542a functions as one of a pair of electrodes of the capacitor 600. The conductor 561 functions as the other of the pair of electrodes of the capacitor 600. The insulator 552 functions as a dielectric of the capacitor 600.

[0378] The conductor 561 preferably extends as a wiring in the channel width direction, for example. That is, the conductor 561 may have a region in the channel width direction where it does not overlap with the conductor 542a but overlaps with the insulator 554 and the insulator 522.

[0379] The conductor 561a can be formed using, for example, a material that can be used for the conductor 560a. The conductor 561b can be formed using, for example, a material that can be used for the conductor 560b.

[0380] A material with a high dielectric constant is preferably used for the insulator 552. For example, the insulator 552 may be a single layer or a stack of insulators including a high-k material that can be used for the insulator 522. The insulator 552 may also include silicon oxide or silicon oxynitride, which are thermally stable.

[0381] 23A and 23B . For example, the transistor 500 illustrated in FIG. 24 may be used as the transistor related to the semiconductor device of one embodiment of the present invention. The transistor 500 illustrated in FIG. 24 is a modification of the transistor 500 illustrated in FIG. 23A and 23B and differs from the transistor 500 illustrated in FIG. 23A and 23B in that an insulator 551 is included and the conductor 542a (the conductor 542a1 and the conductor 542a2) and the conductor 542b (the conductor 542b1 and the conductor 542b2) have a stacked-layer structure.

[0382] The conductor 542a has a layered structure of a conductor 542a1 and a conductor 542a2 on the conductor 542a1, and the conductor 542b has a layered structure of a conductor 542b1 and a conductor 542b2 on the conductor 542b1. The conductors 542a1 and 542b1 in contact with the metal oxide 531b are preferably conductors that are resistant to oxidation, such as metal nitrides. This prevents the conductors 542a and 542b from being excessively oxidized by oxygen contained in the metal oxide 531b. Furthermore, the conductors 542a2 and 542b2 are preferably conductors such as metal layers that have higher conductivity than the conductors 542a1 and 542b1. This allows the conductors 542a and 542b to function as highly conductive wirings or electrodes. In this manner, a semiconductor device can be provided in which the conductors 542a and 542b functioning as wirings or electrodes are provided in contact with the top surface of the metal oxide 531 functioning as an active layer.

[0383] For the conductor 542a1 and the conductor 542b1, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0384] Furthermore, the conductors 542a2 and 542b2 preferably have higher conductivity than the conductors 542a1 and 542b1. For example, the film thickness of the conductors 542a2 and 542b2 is preferably greater than the film thickness of the conductors 542a1 and 542b1. The conductors 542a2 and 542b2 may be made of a conductor that can be used for the conductor 560b. The above structure can reduce the resistance of the conductors 542a2 and 542b2.

[0385] From the above, for example, tantalum nitride or titanium nitride can be used for the conductors 542a1 and 542b1, and tungsten can be used for the conductors 542a2 and 542b2.

[0386] 24 , in a cross-sectional view of the transistor 500 in the channel length direction, the distance between the conductor 542a1 and the conductor 542b1 is smaller than the distance between the conductor 542a2 and the conductor 542b2. This configuration makes it possible to further shorten the distance between the source and the drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 500. By miniaturizing the semiconductor device in this way, it is possible to provide a semiconductor device with improved operating speed.

[0387] The insulator 551 is preferably an insulator that is resistant to oxidation, such as nitride. The insulator 551 is formed in contact with the side surfaces of the conductor 542a2 and the conductor 542b2 and functions to protect the conductors 542a2 and 542b2. Since the insulator 551 is exposed to an oxidizing atmosphere, an inorganic insulator that is resistant to oxidation is preferable. Furthermore, since the insulator 551 is in contact with the conductors 542a2 and 542b2, an inorganic insulator that is resistant to oxidation of the conductors 542a2 and 542b2 is preferable. Therefore, the insulator 551 is preferably an insulating material that has barrier properties against oxygen. For example, silicon nitride can be used as the insulator 551.

[0388] In the transistor 500 shown in FIG. 24 , openings are formed in the insulators 554, 580, 574, and 581 using a first mask to form the conductors 542a2 and 542b2. The insulator 551 is formed in contact with the sidewalls of the openings. Then, the conductors 542a1 and 542b1 are formed using a second mask to complete the transistor 500. The openings overlap with the regions between the conductors 542a2 and 542b2. Parts of the conductors 542a1 and 542b1 protrude into the openings. Therefore, the insulator 551 is in contact with the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surfaces of the conductors 542a2, and the side surfaces of the conductors 542b2 within the openings. In addition, the insulator 550 contacts the top surface of the metal oxide 531 in the region between the conductor 542a1 and the conductor 542b1.

[0389] After the conductors 542a1 and 542b1 are formed, heat treatment is preferably performed in an oxygen-containing atmosphere before the insulator 550 is formed. This allows oxygen to be supplied to the metal oxide 531a and the metal oxide 531b, thereby reducing oxygen vacancies. Furthermore, the insulator 551 is formed in contact with the side surfaces of the conductors 542a2 and 542b2, which prevents the conductors 542a2 and 542b2 from being excessively oxidized. As a result, the electrical characteristics and reliability of the transistor can be improved. Furthermore, variation in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed.

[0390] 24, the insulator 524 may be formed in an island shape in the transistor 500. Here, the side edge of the insulator 524 may be formed so as to roughly coincide with the side edge of the metal oxide 531.

[0391] 24, the transistor 500 may have a structure in which the insulator 522 is in contact with the insulator 516 and the conductor 505. In other words, the transistor 500 may have a structure in which the insulator 520 shown in FIGS.

[0392] <Configuration Example 2 of Semiconductor Device DEV> Next, Fig. 26 shows a cross-sectional configuration example of the semiconductor device DEV according to one embodiment of the present invention, which is different from Fig. 21 and Fig. 22. The semiconductor device DEV shown in Fig. 26 is a modified example of the semiconductor device DEV of Fig. 22, and differs from the semiconductor device DEV of Fig. 22 in that, in memory cells MC provided in a plurality of cell array layers 60, a capacitive element C1 is provided below a transistor M1.

[0393] In order to reduce repetition of explanation, in this configuration example, explanations regarding the substrate 311, the drive circuit region 50, the control processing region 80, and the circuit layer 90 will be omitted.

[0394] 26, each of the multiple cell array layers 60 has multiple memory cells MC different from the memory cells MC shown in Fig. 22. Note that the memory cells MC shown in Fig. 26 are the memory cells MC shown in Fig. 18A as an example. Therefore, each of the memory cells MC shown in Fig. 26 is illustrated as including a transistor M1 and a capacitance element C1.

[0395] Furthermore, a conductor 364 is embedded in the interlayer film between the circuit layer 90 and the cell array layer 60_1. Furthermore, in each of the plurality of cell array layers 60, a conductor 365 is embedded in an insulator 592, which will be described later. Furthermore, in each of the plurality of cell array layers 60, a conductor 366 is embedded in an insulator 593, an insulator 594, an insulator 553, and an insulator 595, which will be described later. Furthermore, in each of the plurality of cell array layers 60, a conductor 367 is embedded in an insulator 596, an insulator 583, a conductor 545, an insulator 555, and an insulator 597, which will be described later. The conductors 364, 365, 366, and 367 function as contact plugs or wiring.

[0396] The conductor 364, the conductor 365, the conductor 366, and the conductor 367 can be made of, for example, the material that can be used for the conductor 502, the conductor 503, or the conductor 504 described above.

[0397] 26 , as an example, transistor MN in circuit layer 90 is electrically connected to transistor M1 included in each memory cell MC in a plurality of cell array layers 60 via conductor 540a, conductor 363b, conductor 364, conductor 365, conductor 366, and conductor 367. In particular, transistor MN and transistor M1 are electrically connected to each other by contact between conductor 504 and conductor 542b, which will be described later.

[0398] In FIG. 26, one transistor MN is provided on the electrical path between the transistor 400 included in the drive circuit region 50 and the control processing region 80 and the transistor M1 included in the memory cell MC of the cell array layer 60_1, but multiple transistors MN may be provided on the electrical path depending on the situation.

[0399] <<Configuration Example of Memory Cell MC>> Next, a configuration example of the memory cells MC included in the plurality of cell array layers 60 of the semiconductor device DEV of FIG. 26 will be described.

[0400] 27A is a plan view showing an example of the configuration of memory cells MC and their periphery included in each of the plurality of cell array layers 60 of the semiconductor device DEV described above. In FIGS. 27A to 27D, the transistor 500A corresponds to the transistor M1 in FIG. 26, and the capacitive element 600A corresponds to the capacitive element 600A in FIG. 26. FIG. 27D is a cross-sectional view taken along dashed dotted line A1-A2 shown in FIG. 27A. Note that some of the components of the transistor M1, such as insulators, are omitted in FIG. 27A. Also, some of the components, such as insulators, are omitted in the subsequent plan views of transistors.

[0401] For example, the capacitor 600A includes an insulator 592, an insulator 593, an insulator 594, an insulator 553, an insulator 595, a conductor 563, a conductor 564, and a conductor 544.

[0402] A conductor 563 is embedded in the insulator 592. The conductor 563 can be, for example, a wiring CL extending in the Y direction.

[0403] The insulator 592 can be, for example, a material that can be used for the above-described insulator 512, insulator 516, insulator 580, or insulator 581. In particular, the insulator 592 is preferably a material with a low dielectric constant, and more preferably, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride.

[0404] The conductor 563 can be made using, for example, a material that can be used for the conductor 505 or the conductor 365 described above.

[0405] As an example, insulators 593 and 594 are formed in this order on the insulator 592 and the conductor 563. Furthermore, openings are provided in the regions of the insulators 593 and 594 that overlap with the conductor 563. The conductor 564 is formed on the bottom surface (on the conductor 563) and side surfaces of the opening. In FIG. 27 , the conductor 564 is also formed on the top surface of the insulator 594. Furthermore, insulators 553 are formed on the insulators 594 and 564. Furthermore, a conductor 544 is formed so as to cover the region of the insulator 553 that overlaps with the conductor 564. Furthermore, insulators 595 are formed on the conductor 544 and the insulator 553. It is preferable that the height of the top surface of the insulator 595 and the height of the top surface of the conductor 544 are approximately the same. For this reason, the insulator 595 and the conductor 544 are preferably planarized by a planarization treatment using, for example, a chemical mechanical polishing (CMP) method.

[0406] The conductor 564 corresponds to, for example, one of a pair of terminals in the capacitor 600A, and the conductor 544 corresponds to, for example, the other of the pair of terminals in the capacitor 600A.

[0407] 23A to 25 or the capacitor 600 shown in Fig. 25. For example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used for the conductor 564 and the conductor 544. The materials listed above are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0408] The insulator 553 functions as, for example, a dielectric sandwiched between a pair of terminals in the capacitor 600 A. For this reason, the insulator 553 is preferably formed using any of the above-described materials that can be used for the insulator 552.

[0409] The insulators 594 and 595 can be, for example, any of the materials that can be used for the above-described insulators 512, 516, 580, and 581. In particular, the insulators 594 and 595 are preferably made of a material with a low dielectric constant, and more preferably made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride.

[0410] The transistor 500A is provided above the conductor 544 and the insulator 595 of the capacitor 600A.

[0411] The transistor 500A has a configuration in which the direction of the channel length is not substantially parallel to the substrate 311 but is along the side surface of an opening provided in an insulator 583 described later.

[0412] 27A illustrates an example in which the conductor 545 extends in a direction perpendicular to the conductors 544 and 565. Note that as described above, the conductor 544 also functions as the other of the pair of electrodes of the capacitor 600A.

[0413] The conductor 544 and the conductor 545 can be formed using, for example, a material that can be used for the conductor 542 included in the transistor 500. The conductor 565 can be formed using, for example, a material that can be used for the conductor 560 included in the transistor 500.

[0414] For the metal oxide 533, for example, a material that can be used for the metal oxide 531 included in the transistor 500 can be used.

[0415] 27A and 27D , the direction in which the conductor 545 extends is the X direction. Furthermore, the direction perpendicular to the X direction and parallel to, for example, the top surface of the conductor 563 is the Y direction, and the direction perpendicular to the top surface of the conductor 563 is the Z direction. The definitions of the X direction, Y direction, and Z direction may be the same or different in the subsequent drawings. The X direction, Y direction, and Z direction may be perpendicular to each other. Furthermore, in the description of plan views in this specification, etc., the X direction may be referred to as the right side or left side, and the Y direction may be referred to as the top side or bottom side. Furthermore, the right side may be referred to as the X direction, the left side as the −X direction, the top side as the Y direction, and the bottom side as the −Y direction.

[0416] The conductor 544 serves as one of a source electrode and a drain electrode of the transistor 500A. The conductor 545 serves as the other of the source electrode and the drain electrode of the transistor 500A. The insulator 555 serves as a gate insulating layer of the transistor 500A. The conductor 565 serves as a gate electrode of the transistor 500A.

[0417] The entire region of the metal oxide 533 that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. The region of the metal oxide 533 that is in contact with the source electrode functions as a source region, and the region that is in contact with the drain electrode functions as a drain region.

[0418] An insulator 596 is provided over the insulator 595 and the conductor 544. The insulator 596 can function as an interlayer insulating layer. The interlayer insulating layer here can be a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and / or hydrogen molecules). For this reason, the insulator 596 can be made of a material that can be used for the insulator 514 or the insulator 522.

[0419] An insulator 583 (insulators 583a and 583b) is provided over the insulator 596, and a conductor 545 is provided over the insulator 583. The insulator 583 can function as an interlayer insulating layer. The interlayer insulating layer here can be an interlayer film for separating the source electrode and gate electrode of the transistor 500A. The insulator 597 functions as an interlayer film for providing a circuit element or a wiring above the transistor 500A.

[0420] The insulator 583 can be made of, for example, a material that can be used for the insulators 514, 516, 522, 524, 550, 554, 574, 580, and 581 included in the transistor 500.

[0421] Specifically, the insulator 583a is preferably made of, for example, an oxide or an oxynitride. Furthermore, the insulator 583a is preferably made of a film that releases oxygen when heated. Furthermore, the insulator 583a can preferably be made of, for example, silicon oxide or silicon oxynitride. When the insulator 583a releases oxygen, oxygen can be supplied from the insulator 583a to the metal oxide 533. Supplying oxygen from the insulator 583a to the metal oxide 533, particularly to the channel formation region of the metal oxide 533, can reduce oxygen vacancies in the metal oxide 533 and hydrogen trapped in the oxygen vacancies. Therefore, the transistor 500A can have favorable electrical characteristics and high reliability.

[0422] Specifically, the insulator 583b can preferably be made of, for example, silicon nitride, silicon nitride oxide, or aluminum oxide. The insulator 583b preferably has a region containing more nitrogen than the insulator 583a. The insulator 583b can be made of, for example, a material containing more nitrogen than the insulator 583a. The insulator 583b can preferably be made of a nitride or nitride oxide. The insulator 583b can preferably be made of, for example, silicon nitride or silicon nitride oxide. By using silicon nitride or silicon nitride oxide for the insulator 583b, the insulator 583b can function as a blocking layer that suppresses oxygen from being released from the insulator 583a. By using silicon nitride or silicon nitride oxide for the insulator 583b, the insulator 583b can be made of, for example, a blocking layer that suppresses hydrogen from diffusing into the metal oxide 533 through the insulator 583.

[0423] The insulator 596 and the insulator 583 have an opening 601 that reaches the conductor 544. The conductor 545 has an opening 603 that reaches the opening 601. In other words, the opening 603 has a region that overlaps with the opening 601.

[0424] 27A shows the components of the transistor 500A, including the conductor 544, the conductor 545, the metal oxide 533, the conductor 565, and the openings 601 and 603. FIG. 23B shows a configuration example in which the conductor 565 is omitted from the components shown in FIG. 27A . That is, FIG. 27B shows the conductor 544, the conductor 545, the metal oxide 533, the openings 601 and 603. FIG. 27C shows a configuration example in which the metal oxide 533 is further omitted from the components shown in FIG. 27B . That is, FIG. 27C shows the conductor 544, the conductor 545, the openings 601 and 603.

[0425] 27C and 27D, the conductor 545 has an opening 603 in a region overlapping with the conductor 544. As shown in Fig. 27C, the conductor 545 can be configured to cover the entire outer periphery of the opening 601 in a plan view. Here, it is preferable that the conductor 545 is not provided inside the opening 601. In other words, it is preferable that the conductor 545 does not contact the side surface of the insulator 583 on the opening 601 side.

[0426] 27A to 27C show an example in which the shapes of the openings 601 and 603 are each circular in a plan view. By making the planar shapes of the openings 601 and 603 circular, the processing accuracy when forming the openings 601 and 603 can be improved, and the openings 601 and 603 can be formed in fine sizes. Note that in this specification, a circle is not limited to a perfect circle. For example, the planar shapes of the openings 601 and 603 may be elliptical, or may be shapes including curves. Or, they may be polygonal.

[0427] 27D shows an example in which the end of the conductor 545 on the opening 603 side coincides with or roughly coincides with the end of the insulator 583 on the opening 601 side. It can also be said that the planar shape of the opening 603 coincides with or roughly coincides with the planar shape of the opening 601. Note that in this specification and the like, the end of the conductor 545 on the opening 603 side refers to the lower surface end of the conductor 545 on the opening 603 side. The lower surface of the conductor 545 refers to the surface on the insulator 583 side. The end of the insulator 583 on the opening 601 side refers to the upper surface end of the insulator 583 on the opening 601 side. The upper surface of the insulator 583 refers to the surface on the conductor 545 side. Furthermore, the planar shape of the opening 603 refers to the planar shape of the lower surface end of the conductor 545 on the opening 603 side. The planar shape of the opening 601 refers to the planar shape of the upper surface end of the insulator 583 on the opening 601 side.

[0428] Incidentally, "the edges are aligned" or "approximately aligned" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, or when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the edges are also said to be approximately aligned, or the planar shapes are said to be approximately aligned.

[0429] The opening 601 can be formed, for example, using the resist mask used to form the opening 603. Specifically, first, an insulator 596 over the conductor 544 and the insulator 595, an insulator 583 over the insulator 596, a conductive film to be the conductor 545 over the insulator 583, and a resist mask over the conductive film are formed. Then, after forming the opening 603 in the conductive film using the resist mask, an opening 601 is formed in the insulator 596 and the insulator 583 using the resist mask. This allows the edge of the opening 601 to coincide or approximately coincide with the edge of the opening 603. Such a structure can simplify the process.

[0430] The metal oxide 533 is provided to cover the openings 601 and 603 and to have regions located inside the openings 601 and 603. The metal oxide 533 has a shape that follows the shapes of the top surface and side surface of the conductor 545, the side surface of the insulator 583, the side surface of the insulator 596, and the top surface of the conductor 544. The metal oxide 533 has regions that are in contact with, for example, the top surface and side surface of the conductor 545, the side surface of the insulator 583, and the top surface of the conductor 544.

[0431] It is preferable that the metal oxide 533 covers the end of the conductor 545 on the opening 603 side. For example, Fig. 27D shows a configuration in which the end of the metal oxide 533 is located on the conductor 545. It can also be said that the end of the metal oxide 533 is in contact with the upper surface of the conductor 545.

[0432] 27D shows the metal oxide 533 having a single-layer structure, one embodiment of the present invention is not limited to this. The metal oxide 533 may have a stacked structure of two or more layers.

[0433] The insulator 555, which functions as a gate insulating layer of the transistor 500A, is provided to cover the openings 601 and 603 and to have regions located inside the openings 601 and 603. The insulator 555 is provided over the metal oxide 533, the conductor 545, and the insulator 583. The insulator 555 can have a region in contact with the top surface and side surfaces of the metal oxide 533, the top surface and side surfaces of the conductor 545, the top surface of the insulator 583, and the top surface of the insulator 596. The insulator 555 has a shape that follows the shapes of the top surface of the insulator 596, the top surface of the insulator 583, the top surface and side surfaces of the conductor 545, and the top surface and side surfaces of the metal oxide 533.

[0434] The conductor 565 functioning as the gate electrode of the transistor 500A is provided over the insulator 555 and can have a region in contact with the top surface of the insulator 555. The conductor 565 has a region overlapping with the metal oxide 533 with the insulator 555 interposed therebetween. The conductor 565 has a shape that follows the shape of the top surface of the insulator 555.

[0435] 27D , in the openings 601 and 603, the conductor 565 has a region that overlaps with the metal oxide 533 with the insulator 555 interposed therebetween. In the example shown in FIG. 27D , the conductor 565 has a region that overlaps with the conductors 544 and 545 with the insulator 555 and the metal oxide 533 interposed therebetween. The conductor 565 also covers the entire metal oxide 533. With this structure, a gate electric field can be applied to the entire metal oxide 533, thereby improving the electrical characteristics of the transistor 500A, for example, increasing the on-state current of the transistor.

[0436] The transistor 500A is a so-called top-gate transistor having a gate electrode above the metal oxide 533. Furthermore, since the bottom surface of the metal oxide 533 has a region in contact with a source electrode and a drain electrode, the transistor 500A can be called a TGBC (Top Gate Bottom Contact) transistor.

[0437] The transistor 500A can be applied to, for example, one or more transistors selected from the transistors included in the memory cell MC, the transistors included in the circuit layer 90, the transistors included in the drive circuit region 50, and the transistors included in the control processing region 80.

[0438] The channel length and channel width of the transistor 500A will now be described with reference to Figures 28A and 28B. Figure 28A is an enlarged plan view illustrating an example of the configuration of the transistor 500A and its periphery shown in Figure 27A. Figure 28B is an enlarged cross-sectional view illustrating an example of the configuration of the transistor 500A and its periphery shown in Figure 27D.

[0439] In the metal oxide 533, the region in contact with the conductor 544 functions as one of the source and drain regions, the region in contact with the conductor 545 functions as the other of the source and drain regions, and the region between the source and drain regions functions as a channel formation region.

[0440] The channel length of the transistor 500A is the distance between the source region and the drain region. In Figure 28B, the channel length L500 of the transistor 500A is indicated by a dashed double-headed arrow. The channel length L500 is the distance between the end of the region where the metal oxide 533 and the conductor 544 contact each other and the end of the region where the metal oxide 533 and the conductor 545 contact each other in a cross-sectional view.

[0441] Here, the channel length L500 of the transistor 500A corresponds to the length of the side surface of the insulator 583 on the opening 601 side when viewed from the XZ plane. In other words, the channel length L500 is determined by the film thickness T583 of the insulator 583 and the angle θ583 between the side surface of the insulator 583 on the opening 601 side and the surface on which the insulator 583 is to be formed (here, the top surface of the conductor 544), and is not affected by the performance of the exposure apparatus used to fabricate the transistor. Therefore, the channel length L500 can be made smaller than the resolution limit of the exposure apparatus, allowing for the realization of a fine-sized transistor. For example, the channel length L500 is preferably 0.010 μm or more and less than 3.0 μm, more preferably 0.050 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less. In FIG. 28B, the thickness T583 of the insulator 583 is indicated by a dashed line with a double-headed arrow.

[0442] By applying the transistor 500A to the transistor included in the memory cell MC of the semiconductor device DEV, the transistor included in the memory cell MC can be miniaturized, thereby enabling the miniaturization of the memory cell MC. This allows the semiconductor device DEV to be miniaturized. Furthermore, by reducing the channel length L500, the on-current of the transistor 500A can be increased. Therefore, by applying the transistor 500A to the transistor included in the semiconductor device DEV, for example, the transistor included in the memory cell MC, the semiconductor device DEV can be driven at high speed.

[0443] The channel length L500 can be controlled by adjusting the film thickness T583 and angle θ583 of the insulator 596 and the insulator 583.

[0444] The thickness T583 of the insulator 596 and the insulator 583 is preferably 0.010 μm or more and less than 3.0 μm, more preferably 0.050 μm or more and less than 3.0 μm, even more preferably 0.10 μm or more and less than 3.0 μm, even more preferably 0.15 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, and even more preferably is preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and 1.0 μm or less, and even more preferably 0.50 μm or more and 1.0 μm or less.

[0445] The side surfaces of the insulators 596 and 583 on the opening 601 side are preferably tapered. The angle θ583 formed by the side surfaces of the insulators 596 and 583 on the opening 601 side and the surface on which the insulator 596 is to be formed (here, the top surface of the conductor 544) is preferably less than 90 degrees. By reducing the angle θ583, the coverage of a layer (e.g., the metal oxide 533) provided on the insulator 583 can be improved. However, reducing the angle θ583 reduces the contact area between the metal oxide 533 and the conductor 544, which may increase the contact resistance between the metal oxide 533 and the conductor 544. The angle θ583 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, even more preferably 55 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 90 degrees, even more preferably 60 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 85 degrees, even more preferably 65 degrees or more and less than 80 degrees, and even more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ583 within the above-mentioned range, the coverage of the layer (e.g., the metal oxide 533) formed on the conductor 544 and the insulator 583 can be improved, and defects such as discontinuities or voids in the layer can be suppressed. Furthermore, the contact resistance between the metal oxide 533 and the conductor 544 can be reduced.

[0446] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0447] 28B shows a cross-sectional view in which the side surfaces of the insulator 596 and the insulator 583 facing the opening 601 are linear; however, one embodiment of the present invention is not limited to this. In a cross-sectional view, the side surfaces of the insulator 596 and the insulator 583 facing the opening 601 may be curved, or the side surfaces may have both linear and curved regions.

[0448] The channel width of the transistor 500A is the width of the source region or the width of the drain region in a direction perpendicular to the channel length direction. That is, the channel width is the width of the region where the metal oxide 533 and the conductor 544 contact or the width of the region where the metal oxide 533 and the conductor 545 contact in a direction perpendicular to the channel length direction. Here, the channel width of the transistor 500A is described as the width of the region where the metal oxide 533 and the conductor 545 contact in a direction perpendicular to the channel length direction. In Figures 28A and 28B, the channel width W500 of the transistor 500A is indicated by a solid double-headed arrow. The channel width W500 is the length of the bottom end of the conductor 545 on the opening 603 side in a plan view.

[0449] The channel width W500 is determined by the planar shape of the opening 603. In Figures 28A and 28B, the width D500 of the opening 603 is indicated by a two-dot chain line with a double arrow. The width D500 indicates the short side of the smallest rectangle circumscribing the opening 603 in a planar view. When the opening 603 is formed using photolithography, the width D500 of the opening 603 is equal to or greater than the limit resolution of the exposure device. The width D500 is, for example, preferably 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, even more preferably 0.20 μm or more and less than 4.0 μm, even more preferably 0.20 μm or more and less than 3.5 μm, even more preferably 0.20 μm or more and less than 3.0 μm, even more preferably 0.20 μm or more and less than 2.5 μm, even more preferably 0.20 μm or more and less than 2.0 μm, even more preferably 0.20 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.5 μm, even more preferably 0.30 μm or more and less than 1.2 μm, even more preferably 0.40 μm or more and 1.2 μm or less, even more preferably 0.40 μm or more and less than 1.0 μm, and even more preferably 0.50 μm or more and less than 1.0 μm. When the opening 603 has a circular planar shape, the width D500 corresponds to the diameter of the opening 603, and the channel width W500 can be made equal to the periphery of the opening 603 in a planar view, and can be calculated as "D500 x π".

[0450] Because the size of the transistor 500A is small, by applying the transistor 500A to the cell array layer 60, a semiconductor device with high storage density can be provided. Furthermore, because the transistor 500A operates quickly, by applying the transistor 500A to a semiconductor device, a semiconductor device with high driving speed can be provided. Furthermore, because the transistor 500A has stable electrical characteristics, by applying the transistor 500A to a semiconductor device, a highly reliable semiconductor device can be provided. Furthermore, because the amount of off-state current of the transistor 500A is small, by applying the transistor 500A to a semiconductor device, a semiconductor device with low power consumption can be provided.

[0451] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0452] In this embodiment, a transistor having an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that in the description of the OS transistor, a comparison with a transistor having silicon in a channel formation region (also referred to as a Si transistor) will also be briefly described.

[0453] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0454] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0455] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0456] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on (a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0457] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as off-leak current or Ioff) of the transistor can be reduced.

[0458] Furthermore, in Si transistors, a short channel effect (also referred to as SCE) occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0459] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0460] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0461] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0462] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0463] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when the semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty in achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0464] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0465] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0466] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0467] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0468] [Electronic Component] FIG. 29A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 29A has semiconductor device 710 inside mold 711. FIG. 29A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0469] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0470] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0471] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to achieve a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0472] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0473] 29B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on interposer 731.

[0474] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0475] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0476] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0477] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0478] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0479] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space such as the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0480] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0481] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 29B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0482] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0483] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 30A . The electronic device 6500 shown in FIG. 30A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more of a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0484] 30B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0485] [Mainframe] Next, Fig. 30C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 30C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0486] The computer 5620 can have the configuration shown in the perspective view in Fig. 30D, for example. In Fig. 30D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0487] A PC card 5621 shown in Figure 30E is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although Figure 30E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to for the semiconductor devices.

[0488] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0489] Each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for supplying power to the PC card 5621, inputting signals, etc. Furthermore, each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of standards for the respective connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0490] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0491] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0492] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0493] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0494] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0495] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0496] Fig. 31 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 31, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0497] 31 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0498] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0499] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0500] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0501] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The change in electrical characteristics of an OS transistor due to radiation exposure is smaller than that of a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0502] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0503] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0504] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0505] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0506] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0507] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0508] Fig. 32 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 32 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0509] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0510] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0511] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0512] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0513] Note that by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0514] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0515] Embodiment Mode 5 In this embodiment mode, a structural example in which the stacked structure described in the above embodiment mode is applied to a display device and an electronic device to which the display device is applied will be described.

[0516] <Configuration Example of Display Device> FIG. 33A is a schematic perspective view showing a configuration example of a display device DSP to which the stacked structure is applied, and FIG. 33B is a block diagram of the display device DSP.

[0517] The display device DSP has a memory circuit region MEMA, a drive circuit region DRVA, a circuit layer SWCL, and a display region EMA. The memory circuit region MEMA and the drive circuit region DRVA are located below the circuit layer SWCL, and the display region EMA is located above the circuit layer SWCL. In other words, in the display device DSP, the memory circuit region MEMA and the drive circuit region DRVA, the circuit layer SWCL, and the display region EMA are stacked in this order from the bottom.

[0518] The memory circuit area MEMA has, for example, a plurality of memory circuits ME. The memory circuits ME in embodiment 1 can be referred to for the memory circuits ME. Therefore, the memory circuit area MEMA may include memory circuits ME having, for example, DRAM, DOSRAM (registered trademark), NOSRAM (registered trademark), SRAM, FeRAM, ReRAM, MRAM, or PRAM. Also, in FIG. 33B , the memory circuits ME are, as an example, memory circuits that store digital data, each configured to transmit one-bit or multi-bit data to the circuit layer SWCL. The memory circuits ME also store image data to be transmitted to the pixel circuits PX, which will be described later.

[0519] For example, the memory circuit ME has a function of reading 8-bit (1 byte) image data and transmitting the image data to the drive circuit area DRVA (described later). Note that the data that the memory circuit ME can handle is not limited to 8 bits, and it may handle data of less than 8 bits, such as 1 bit, 2 bits, or 4 bits. It may also handle data of more than 8 bits, such as 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits.

[0520] The drive circuit area DRVA includes, for example, a plurality of digital-to-analog conversion circuits DAC. The digital-to-analog conversion circuits DAC convert digital image data read from the memory circuit ME into analog data. The drive circuit area DRVA also has a function of transmitting the converted analog data to the circuit layer SWCL.

[0521] The circuit layer SWCL includes, for example, a selector MPX. Note that for the selector MPX, the description of the selector MPX described in the first embodiment can be referred to.

[0522] The display area EMA has, for example, a plurality of pixel circuits PX. In particular, it is preferable that the pixel circuits PX are arranged in an array in the display area EMA.

[0523] The selector MPX has a plurality of input terminals IT electrically connected to a plurality of digital-to-analog conversion circuits DAC in the drive circuit area DRVA, and an output terminal OT electrically connected to one of a plurality of pixel circuits PX included in the display area EMA.

[0524] The selector MPX has a function of bringing one of the plurality of input terminals IT of the selector MPX into a conductive state and the output terminal OT of the selector MPX in response to a signal PSIG input to the selector MPX, and also has a function of bringing each of the remaining plurality of input terminals IT of the selector MPX into a non-conductive state and the output terminal OT of the selector MPX.

[0525] By configuring the display device DSP as described above, the display device DSP can select image data from the image data stored in each of the multiple memory circuits ME in the memory circuit area MEMA, and display the selected image data on one of the multiple pixel circuits PX in the display area EMA.

[0526] Next, a configuration example of the pixel circuit PX will be described.

[0527] Fig. 34 shows a circuit layer OSL that can be provided in the pixel circuit PX and an emitting layer LE connected to the circuit layer OSL. In Fig. 34, the emitting layer LE includes a light-emitting device 130. Fig. 34 also shows the connections of the circuit elements included in the circuit layer OSL provided in the pixel circuit PX.

[0528] The circuit layer OSL includes a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. The transistors 500A, 500B, and 500C can each be, for example, a transistor applicable to the transistor M1 described in Embodiment 1. In particular, the transistors 500A, 500B, and 500C are preferably OS transistors. Note that FIG. 34 illustrates the transistors 500A, 500B, and 500C as OS transistors each having a backgate electrode. In this case, the backgate electrode may be configured to receive the same signal as the gate electrode, or a different signal from the gate electrode. Note that although FIG. 34 illustrates the transistors 500A, 500B, and 500C each having a backgate electrode, the transistors 500A, 500B, and 500C may not have a backgate electrode.

[0529] The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light-emitting device 130, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting device 130.

[0530] The transistor 500A has a first terminal electrically connected to the gate electrode of the transistor 500B, a second terminal electrically connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling switching between an on state and an off state based on the potential of the wiring G1 that functions as a gate line.

[0531] The line SL functions as a source line in the pixel circuit PX, and therefore, image data transmitted to the line SL becomes image data output from the selector MPX of the circuit layer SWCL described above.

[0532] The transistor 500C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light-emitting device 130, and a gate electrode having a function of controlling switching between an on state and an off state based on the potential of the wiring G2 functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the circuit layer OSL to the drive circuit area DRVA.

[0533] The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

[0534] The light-emitting device 130 includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting device 130.

[0535] This allows the intensity of light emitted by light-emitting device 130 to be controlled in accordance with an image signal applied to the gate electrode of transistor 500B. Furthermore, the reference potential of wiring V0 applied via transistor 500C can suppress variations in the gate-source voltage of transistor 500B.

[0536] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 500B or the current flowing through the light-emitting device 130 to the outside. The current output to the wiring V0 is converted into a voltage by, for example, a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by, for example, an analog-to-digital conversion circuit and output to a circuit that performs dimming and toning processes. Note that the above-mentioned source follower circuit, analog-to-digital conversion circuit, and circuit that performs dimming and toning processes may each be included in, for example, the drive circuit area DRVA.

[0537] 35 is a diagram schematically showing the hierarchical relationship between a drive circuit area DRVA, a memory circuit area MEMA, a circuit layer SWCL, a circuit layer OSL including a plurality of transistors included in the pixel circuits PX, and an emission layer LE including the light-emitting devices 130. Note that the display area EMA of the display device DSP shown in FIG. 35 includes, as an example, the circuit layer OSL and the emission layer LE.

[0538] In the configuration shown in FIG. 35 as an example, the wiring electrically connecting the circuit layer OSL and the drive circuit region DRVA can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, thereby enabling the display device DSP to be driven at high speed. This allows a sufficient frame period to be ensured even if the display device DSP has a large number of pixel circuits PX, thereby increasing the pixel density of the display device DSP. Furthermore, increasing the pixel density of the display device DSP can increase the resolution of the image displayed by the display device DSP. For example, the pixel density of the display device DSP can be set to 500 ppi or more, preferably 1000 ppi or more, more preferably 3000 ppi or more, even more preferably 5000 ppi or more, and even more preferably 6000 ppi or more. Therefore, the display device DSP can be a display device for XR (Extended Reality or Cross Reality) such as AR (Augmented Reality) and VR (Virtual Reality), and is suitable for use in electronic devices such as HMDs (Head Mounted Displays) where the display unit is close to the user.

[0539] <Configuration Example of Electronic Device> Next, an example of an electronic device to which the above-described display device DSP can be applied will be described.

[0540] The electronic device includes, for example, a display device and one or more selected from an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0541] The electronic device may also have a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0542] Examples of secondary batteries include lithium ion secondary batteries (e.g., lithium polymer batteries (lithium ion polymer batteries) using a gel electrolyte), nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0543] The electronic device may also have an antenna. By receiving a signal through the antenna, images, information, etc. can be displayed on the display unit. When the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0544] The display area of ​​the electronic device can display images with resolutions such as full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0545] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0546] The electronic device can be incorporated along a flat or curved surface of an interior or exterior wall of a building such as a house or a building, or along a flat or curved surface of an interior or exterior of an automobile or the like.

[0547] 36A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0548] 36B is a diagram showing the appearance of an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, a crown 5904, and a band 5905.

[0549] 36C also illustrates a notebook information terminal 5300. The notebook information terminal 5300 illustrated in FIG. 36C includes, for example, a display unit 5331 in a housing 5330a and a keyboard unit 5350 in a housing 5330b.

[0550] 36A to 36C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and notebook information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0551] 36D is a diagram showing the appearance of a camera 8000 with a viewfinder 8100 attached. The camera 8000 has a housing 8001, a display unit 8002, operation buttons 8003, and a shutter button 8004. A detachable lens 8006 is attached to the camera 8000. The viewfinder 8100 has a housing 8101, a display unit 8102, and a button 8103.

[0552] Note that the camera 8000 may have the lens 8006 and the housing integrated together.

[0553] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display portion 8002 that functions as a touch panel.

[0554] The housing 8001 has a mount with electrodes, and in addition to the finder 8100, for example, a strobe device can be connected.

[0555] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display portion 8102.

[0556] The button 8103 functions as a power button.

[0557] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0558] 36E is a diagram showing the appearance of a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, and buttons 5203.

[0559] Furthermore, the images of the portable game console 5200 can be output by a display device provided in a television device, a display for a personal computer, a game display, or a head-mounted display.

[0560] A low-power consumption portable game console 5200 can be realized by applying the display device described in the above embodiment to the portable game console 5200. In addition, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0561] 36E illustrates a portable game machine as an example of a game machine, but the electronic device of one aspect of the present invention is not limited to this. Examples of the electronic device of one aspect of the present invention include a stationary game machine, an arcade game machine installed in an entertainment facility (e.g., a game center or an amusement park), and a pitching machine for batting practice installed in a sports facility.

[0562] 36F is a perspective view of a television set. The television set 9000 includes a housing 9002, a display 9001, speakers 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, and a sensor 9007 (for example, a sensor having a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light (including infrared rays), liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, or odor; or a sensor having a function of sensing or detecting odor or light (including infrared rays)). The storage device of one embodiment of the present invention can be included in the television set. The television set can include a display 9001 that is, for example, 50 inches or larger, or 100 inches or larger.

[0563] A low-power television set 9000 can be realized by applying the display device described in the above embodiment to the television set 9000. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0564] [Mobile Body] The display device according to one embodiment of the present invention can also be applied to the vicinity of the driver's seat of an automobile, which is a mobile body.

[0565] Fig. 36G is a diagram showing the area around the windshield in the interior of a car, illustrating display panels 5701, 5702, and 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0566] The display panels 5701 to 5703 can display various information such as navigation information, a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, and air conditioning settings. The display items and layouts displayed on the display panels can be changed as needed to suit the user's preferences, improving the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0567] The display panel 5704 can complement the view blocked by the pillar (blind spot) by displaying an image from an imaging means provided on the vehicle body. That is, by displaying an image from an imaging means provided on the outside of the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0568] The display device of one embodiment of the present invention can be applied to the display panels 5701 to 5704, for example.

[0569] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, examples of the moving object include a train, a monorail, a ship, and an aircraft (e.g., a helicopter, an unmanned aerial vehicle (drone), an airplane, and a rocket), and the display device of one embodiment of the present invention can be applied to these moving objects.

[0570] [Digital Signage] Fig. 36H illustrates an example of a digital signage that can be attached to a wall. Fig. 36H illustrates a state in which a digital signage 6200 is attached to a wall 6201. The display device of one embodiment of the present invention can be applied to, for example, a display portion of the digital signage 6200. The digital signage 6200 may be provided with an interface such as a touch panel.

[0571] Although the above description shows an example of an electronic device that can be mounted on a wall as an example of an electronic signboard, the type of electronic signboard is not limited to this. For example, electronic signboards can be mounted on a pole, placed on a stand on the ground, or installed on the roof or side wall of a building.

[0572] 36I is a diagram showing the appearance of an electronic device 8300 which is a head-mounted display. The electronic device 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, a fixture 8304 a to be attached to the head, and a pair of lenses 8305.

[0573] Although not shown in FIG. 36I, the electronic device 8300 may also be provided with an interface such as an operation button or a power button.

[0574] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to curve the display portion 8302 because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, three-dimensional display using parallax can be performed. Note that the configuration is not limited to one display portion 8302, and two display portions 8302 may be provided, with one display portion being arranged for each eye of the user.

[0575] Note that, for example, a display device with extremely high definition is preferably used for the display portion 8302. By using a display device with high definition for the display portion 8302, even if an image is enlarged using the lens 8305, pixels are not visible to a user, and more realistic images can be displayed.

[0576] Furthermore, the head-mounted display, which is an electronic device, may be configured as an electronic device that is a glasses-type head-mounted display, rather than the electronic device 8300 that is a goggle-type head-mounted display as shown in Figure 36I.

[0577] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0578] DEV: semiconductor device, MEML_L: memory layer, MEML_H: memory layer, SWCL: circuit layer, SWCLA: circuit layer, SWCLB: circuit layer, SWCLC: circuit layer, ME_L: memory circuit, ME_H: memory circuit, MC_L: memory cell, MC_H: ​​memory cell, WL_L: wiring, WL_H: wiring, BL_L: wiring, BL_H: wiring, BLUT_L: wiring, BLUT_H: wiring, MA_L: area, MA_H: area, MPX: selector, DMPX: selector, SW

[00000] : switch, SW

[00100] : switch, SW

[00111] : switch, SW[0 1000]: Switch, SW

[01100] : Switch, SW

[01111] : Switch, SW

[10000] : Switch, SW

[10100] : Switch, SW

[10111] : Switch, SW

[11111] : Switch, SW1: Switch, SW2: Switch, SW3: Switch, SW4: Switch, SW5: Switch, SW6: Switch, SWa1: Switch, SWa2: Switch, SWb1: Switch, SWb2: Switch, SWb3: Switch, SWb4: Switch, IT: Terminal, IT1: Terminal, IT2: Terminal, OT: Terminal, OT1: Terminal, O T2: terminal, SL1: wiring, SL2: wiring, SL3: wiring, SL4: wiring, SL5: wiring, SL6: wiring, SLa1: wiring, SLa2: wiring, SLb1: wiring, SLb2: wiring, PON1: signal, PON2: signal, ADDR: signal, BW: signal, CE: signal, GW: signal, CLK: signal, WAKE: signal, WDA: signal, RDA: signal, SSIG: signal, DSIG: signal, MC: memory cell, M1: transistor, M2: transistor, M4: transistor, M4r: transistor, M5: transistor, M5r: transistor, M6: transistor, M N: transistor, C1: capacitance element, C2: capacitance element, C3: capacitance element, C3r: capacitance element, VR: resistance change element, MR: MTJ element, PCM: phase change memory, INV1: logic circuit, INV2: logic circuit, BL: wiring, BL[1]: wiring, BL[n]: wiring, BLB: wiring, WBL[1]: wiring, WBL[n]: wiring, RBL[1]: wiring, RBL[n]: wiring, WL: wiring, WL[1]: wiring, WL[m]: wiring, W1L: wiring, W2L: wiring, SL[1]: wiring, SL[n]: wiring, CL: wiring, CL[1]: wiring, CL[m]: wiring, C1L: wiring,C2L: wiring, OSL: circuit layer, ME: memory circuit, DRV: drive circuit area, DRVA: drive circuit area, VCOM: wiring, ANO: wiring, PSIG: signal, 10: memory cell, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: drive circuit area, 60: cell array layer, 60_1: cell array layer, 60_2: cell array layer, 60_3: ​​cell array layer, 60_k: cell array layer, 60_N: cell array layer, 70: cell array, 71: drive circuit, 72: drive circuit, 75: memory cell, 80: control processing area, 81: ALU, 82: ALU controller, 83: instruction decoder, 84: interrupt controller, 85: timing controller, 90: circuit layer, 100: memory hierarchy, 101: register, 102: first cache memory, 103: second cache memory, 104: main memory, 105: auxiliary storage device, 301: insulator, 311: substrate, 313: semiconductor region, 314a: low resistance region region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 356: conductor, 357: insulator, 361: conductor, 362: conductor, 363a: conductor, 363b: conductor, 364: conductor, 365: conductor, 366: conductor, 367: conductor, 400: transistor, 500: transistor, 500A: transistor, 500B: transistor, 500C: transistor, 502: conductor, 503: conductor, 504: conductor , 505: conductor, 505a: conductor, 505b: conductor, 512: insulator, 514: insulator, 516: insulator, 520: insulator, 522: insulator, 524: insulator, 531: metal oxide, 531a: metal oxide, 531b: metal oxide, 533: metal oxide, 540a: conductor, 540b: conductor, 542a: conductor, 542a1: conductor, 542a2: conductor, 542b: conductor, 542b1: conductor, 542b2: conductor, 543a: region, 543b: region, 544: conductor, 545: conductor, 550: insulator, 551: insulator, 552: insulator,553: insulator, 554: insulator, 555: insulator, 560: conductor, 560a: conductor, 560b: conductor, 561: conductor, 561a: conductor, 561b: conductor, 563: conductor, 564: conductor, 565: conductor, 574: insulator, 580: insulator, 581: insulator, 583: insulator, 583a: insulator, 583b: insulator, 592: insulator, 593: insulator, 594: insulator, 595: insulator, 596: insulator, 597: insulator, 600: capacitive element, 600A: capacitive element, 700: electronic component, 704: mounting substrate, 710: semiconductor device, 7 11: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: notebook information terminal, 5330a: housing, 5330b: housing, 5331: display unit, 5350: keyboard unit, 5500: information terminal, 5510: housing, 5511: display unit, 5600: mainframe computer, 5610: rack, 5620: calculation machine, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 5900: information terminal, 5901: housing, 5902: display unit, 5903: operation button, 5904: crown, 5905: band, 6200: electronic signboard, 6201: wall, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6 506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device,7004: Storage area network, 8000: Camera, 8001: Housing, 8002: Display unit, 8003: Operation buttons, 8004: Shutter button, 8006: Lens, 8100: Viewfinder, 8101: Housing, 8102: Display unit, 8103: Button, 8300: Electronic device, 8301: Housing, 8302: Display unit, 8304: Fixing device, 8304a: Fixing device, 8305: Lens, 9000: Television device, 9001: Display unit, 9002: Housing, 9003: Speaker, 9006: Connection terminal, 9007: Sensor,

Claims

1. Having a first memory layer, a second memory layer, and a circuit layer, The first memory layer has a plurality of first memory circuits, The second memory layer has a second memory circuit, The second memory circuit comprises a capacitive element and a second transistor, The circuit layer has a selector, The selector has a plurality of input terminals and an output terminal, The first memory layer is located below the circuit layer, The second memory layer is located above the circuit layer, Each of the plurality of first memory circuits is electrically connected to the plurality of input terminals, The selector has the function of creating a conductive state between one input terminal selected from the plurality of input terminals and the output terminal. A semiconductor device having the function of writing data read from the second memory circuit to the first memory circuit via the selector, A first conductor that functions as wiring to which a constant potential is applied, A first insulator having a region positioned above the first conductor and having a first opening, A second conductor having a region that contacts the first conductor in a region overlapping with the first opening, a region that contacts the side surface of the first insulator in the first opening, and a region that contacts the upper surface of the first insulator, A third conductor having a region that overlaps with the first opening, a region that overlaps with the second conductor and the first conductor via the second insulator, a region that overlaps with the second conductor and the side surface of the first insulator in the first opening via the second insulator, and a region that overlaps with the upper surface of the second conductor and the first insulator via the second insulator, A third insulator having a region positioned above the third conductor and having a second opening, A fourth conductor having a region positioned above the third insulator and having a third opening, A metal oxide having a region that contacts the third conductor in the region overlapping with the second opening, a region that contacts the side surface of the third insulator in the second opening, a region that contacts the side surface of the fourth conductor in the third opening, and a region that contacts the upper surface of the fourth conductor, A fifth conductor having a region that overlaps with the metal oxide and the third conductor via the fourth insulator in a region that overlaps with the second opening, a region that overlaps with the metal oxide and the side surface of the third insulator in the second opening via the fourth insulator, a region that overlaps with the metal oxide and the side surface of the fourth conductor in the third opening via the fourth insulator, and a region that overlaps with the metal oxide and the upper surface of the fourth conductor via the fourth insulator, The second conductor functions as one electrode of the capacitive element, The third conductor has the function of being the other electrode of the capacitive element and the function of being either the source electrode or the drain electrode of the second transistor. The fourth conductor functions as the gate electrode of the second transistor. The fifth conductor functions as the other of the source electrode or drain electrode of the second transistor. The fourth conductor is electrically connected to the output terminal. Semiconductor equipment.

2. In claim 1, The metal oxide comprises one or more elements selected from indium, zinc, and element M. The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. Semiconductor equipment.

3. In claim 2, Having a semiconductor substrate containing silicon, The first memory layer is located on the semiconductor substrate, The first memory circuit has a first transistor, The first transistor has silicon in the channel formation region. Semiconductor equipment.

4. In claim 3, The second insulator has an oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium. Semiconductor equipment.

5. In claim 4, The aforementioned data is one of the following: 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits. Semiconductor equipment.

6. In claim 5, The first memory circuit and the second memory circuit are not connected by a system bus. Semiconductor equipment.

7. A semiconductor device according to any one of claims 1 to 6, and a housing, electronic equipment.