Semiconductor device and method for producing semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a well region which is formed in a surface part of a first main surface of a semiconductor layer; a source region which is formed in a surface part of the well region; a drain region which is formed in the surface part of the well region at a distance from the source region so as to define a channel region between itself and the source region; a planar gate structure which is formed on the first main surface of the semiconductor layer so as to face the channel region; and a memory structure which is arranged so as to be laterally adjacent to the planar gate structure. The memory structure comprises an insulating film which is formed on the channel region and a charge storage film which faces the channel region with the insulating film being interposed therebetween. This semiconductor device additionally comprises a p-type impurity region that has a higher impurity concentration than the well region.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] For example, Patent Document 1 below is a document disclosing a semiconductor device equipped with a nonvolatile memory. In a memory cell equipped in the semiconductor device disclosed in Patent Document 1, a gate electrode is formed on a p-well region via a gate insulating film. On the sides of the gate electrode, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially stacked on a resistance change portion formed on the surface portion of the p-well region. In this memory cell, writing is performed by injecting hot electrons generated near the drain region into the silicon nitride film. Because this memory cell is used as an OTPROM (One Time Programmable Read Only Memory), no erasure operation is performed except for a quality confirmation test.

[0003] Japanese Patent Application Laid-Open No. 2005-064295

[0004] One object of the present invention is to provide a semiconductor device and a manufacturing method thereof in which, in a configuration in which a memory structure is arranged adjacent to a side of a planar gate structure, data can be repeatedly written to and erased from the memory structure at a low voltage.

[0005] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer having a main surface, a well region formed in a surface portion of the main surface of the semiconductor layer, first and second regions formed in the surface portion of the well region at a distance from each other in a first direction, a third region formed in the surface portion of the main surface of the semiconductor layer in a channel region between the first and second regions, a planar gate structure including a gate insulating film and a gate electrode stacked in the second direction on the main surface of the semiconductor layer so as to face the third region, and sidewall structures arranged adjacent to and laterally in the first direction of the planar gate structure on the first region side, wherein the first and second regions have a first conductivity type, and the well region and the third region have a second conductivity type, and the sidewall structures include first and second insulating films and a charge storage film arranged between the first and second insulating films, and the first insulating film is adjacent to the planar gate structure in the first direction.

[0006] According to this configuration, the third region is formed in the channel region between the first region and the second region. This makes it easier to generate hot carriers (hot electrons and hot holes). This allows the applied voltage for injecting hot electrons into the charge storage film during a write operation and the applied voltage for drawing hot holes into the charge storage film during an erase operation to be reduced.

[0007] 7A is a plan view of a main part of a semiconductor device according to an embodiment of the present invention; FIG. 7B is a cross-sectional view taken along line II-II in FIG. 1; FIG. 7C is a cross-sectional view taken along line III-III in FIG. 1; and FIG. 7D is an enlarged view of region IV in FIG. 2. FIG. 7E is a cross-sectional view taken along line III-III in FIG. 1; and FIG. 7F is an enlarged view of region IV in FIG. 2. FIG. 7F is a cross-sectional view taken along line II-II in FIG. 1; and FIG. 7G is a cross-sectional view taken along line III-III in FIG. 1; and FIG. 7H is a cross-sectional view taken along line III-III in FIG. 1; and FIG. 7J is a cross-sectional view taken along line III-III in FIG. 7K. A cross-sectional view showing a process after FIG. 7L. A cross-sectional view showing a process after FIG. 7M. A cross-sectional view showing a process after FIG. 7N. A cross-sectional view showing a process after FIG. 7O. A cross-sectional view showing a process after FIG. 7P. A cross-sectional view showing a process after FIG. 7Q. A cross-sectional view showing a process after FIG. 7R. A cross-sectional view showing a process after FIG. 7S. A cross-sectional view showing a process after FIG. 7T. A cross-sectional view showing a process after FIG. 7U. A cross-sectional view showing a process after FIG. 7V. A cross-sectional view showing a process after FIG. 7W. A cross-sectional view showing a process after FIG. 7X. A cross-sectional view showing a process after FIG. 7Y.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0009] FIG. 1 is a plan view of a main part of a semiconductor device 1 according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 1. FIG. 4 is an enlarged view of region IV shown in FIG. 2. In FIG. 1, an insulating spacer 43, a coated insulating film 51, and an interlayer insulating film 65, which will be described later, have been removed. The configuration of the semiconductor device 1 will be described below with reference to FIGS. 1 to 4.

[0010] The semiconductor device 1 is a nonvolatile memory using a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor device 1 includes a semiconductor layer 2 made of single crystal silicon.

[0011] 2 , in this embodiment, the semiconductor layer 2 is formed in a rectangular parallelepiped shape. The semiconductor layer 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The semiconductor device 1 includes a p-type (second conductivity type) back gate region 20 formed in the semiconductor layer 2. The back gate region 20 is formed throughout the entire semiconductor layer 2.

[0012] The semiconductor device 1 includes a trench insulation structure 10 that defines a device region 6 in which a MOSFET is formed. The trench insulation structure 10 includes a trench 11 and an insulating filling 12. The trench 11 is formed by digging down the first main surface 3 toward the second main surface 4. The trench 11 is formed in a quadrangular ring shape in a plan view seen from the normal direction Z of the first main surface 3 and the second main surface 4 (hereinafter simply referred to as "plan view"), and defines the quadrangular device region 6 (see also FIG. 1 ).

[0013] 1 , the trench 11 is formed in a quadrangular ring shape in a plan view seen from the normal direction Z of the first main surface 3 and the second main surface 4 (hereinafter simply referred to as "plan view"), and defines a quadrangular device region 6. The direction in which one side of the device region 6 extends in the plan view is defined as a first direction X. The direction perpendicular to both the first direction X and the normal direction Z is defined as a second direction Y.

[0014] 2 , the trench 11 specifically includes an inner wall 13 on one side, an outer wall 14 on the other side, and a bottom wall 15 connecting the inner wall 13 and the outer wall 14. The inner wall 13 is formed in a rectangular ring shape in a plan view. The outer wall 14 is formed in a rectangular ring shape extending parallel to the inner wall 13 in a plan view. The outer wall 14 does not necessarily have to extend parallel to the inner wall 13, and may be formed in a shape different from that of the inner wall 13. The bottom wall 15 extends parallel to the first main surface 3. The bottom wall 15 may be formed in a curved shape toward the second main surface 4.

[0015] In this embodiment, the trench 11 is formed in a tapered shape with the opening width narrowing toward the bottom wall 15. The taper angle of the trench 11 may be greater than 90° and not greater than 125°. The taper angle is preferably greater than 90° and not greater than 100°. The taper angle of the trench 11 is the angle between the inner wall 13 (outer wall 14) of the trench 11 and the first main surface 3 within the semiconductor layer 2. Of course, the trench 11 may be formed perpendicular to the first main surface 3.

[0016] The depth of trench 11 may be 0.1 μm or more and 1 μm or less. The width of trench 11 is arbitrary. The width of trench 11 may be 0.1 μm or more and 10 μm or less. The width of trench 11 is defined by the width in a direction perpendicular to the direction in which trench 11 extends in a plan view.

[0017] The insulating filling material 12 is buried in the trench 11. The insulating filling material 12 may be made of any insulator. The insulating filling material 12 may be made of silicon oxide (SiO ２ The insulating fill 12 may include at least one of silicon dioxide (SiO 2 ) and silicon nitride (SiN). In this embodiment, the insulating fill 12 is made of silicon oxide.

[0018] The insulating filling 12 includes a buried portion 17 and a protruding portion 18. The buried portion 17 is located on the bottom wall 15 side of the trench 11 relative to an opening end 16 of the trench 11. The protruding portion 18 protrudes from the buried portion 17 toward the opposite side from the bottom wall 15 side.

[0019] The semiconductor device 1 includes a p-type (second conductivity type) well region 21 formed in the device region 6 on the surface portion of the first main surface 3. The well region 21 extends in a first direction X along the first main surface 3. The p-type impurity concentration of the well region 21 exceeds the p-type impurity concentration of the back gate region 20. The p-type impurity concentration of the well region 21 is, for example, 10×10 １２ cm －３ Higher 10x10 １６ cm －３ The following is the result.

[0020] The bottom of the well region 21 is electrically connected to the back gate region 20. In this embodiment, the well region 21 is formed deeper than the trench 11 and partially covers the bottom wall 15 of the trench 11. Unlike this embodiment, the well region 21 may be formed in a region on the first main surface 3 side of the bottom wall 15 of the trench 11, and the boundary between the well region 21 and the back gate region 20 may be located between the bottom wall 15 of the trench 11 and the first main surface 3.

[0021] The semiconductor device 1 includes an n-type (first conductivity type) source region 22 formed in the surface portion of a well region 21, and an n-type (first conductivity type) drain region 23 formed in the surface portion of the well region 21 at a distance from the source region 22. The n-type impurity concentrations of the source region 22 and the drain region 23 are, for example, 10×10 １６ cm －３ 10 x 10 or more ２０ cm －３ The following is the result.

[0022] A channel region 24 of the MOSFET is formed between the drain region 23 and the source region 22 in the surface portion of the device region 6. The channel region 24 forms a current path along the second direction Y between the source region 22 and the drain region 23.

[0023] A p-type impurity region 21A is formed in the channel region 24. The impurity concentration of the p-type impurity region 21A is higher than the impurity concentration of the well region 21, and the depth of the p-type impurity region 21A is shallower than the depth of the well region 21. The impurity concentration of the p-type impurity region 21A is 10×10 １６ cm －３Higher, 10x10 １７ cm －３ For example, if the semiconductor layer is silicon (Si) and the impurity element introduced into the well region 21 is boron (B+), the impurity element introduced into the p-type impurity region 21A is boron. By forming the p-type impurity region 21A, it is possible to reduce the write voltage when used as a memory transistor.

[0024] The source region 22 has a bottom located closer to the first main surface 3 than the bottom of the well region 21. The drain region 23 has a bottom located closer to the first main surface 3 than the bottom of the well region 21.

[0025] The bottom of the source region 22 is flat and has no steps. The source region 22 is in contact with the channel region 24, and no LDD (Lightly Doped Drain) region having a lower n-type impurity concentration than the source region 22 is provided between the source region 22 and the channel region 24. The bottom of the drain region 23 is flat and has no steps. The drain region 23 is in contact with the channel region 24, and no LDD (Lightly Doped Drain) region having a lower n-type impurity concentration than the drain region 23 is provided between the drain region 23 and the channel region 24.

[0026] The semiconductor device 1 includes a planar gate structure 30 formed on the first main surface 3 in the device region 6 so as to face the channel region 24. The planar gate structure 30 extends in a first direction X along the first main surface 3. An end of the planar gate structure 30 in the first direction X reaches onto the trench isolation structure 10. Unlike this embodiment, the end of the planar gate structure 30 in the first direction X may extend to the outside of the trench isolation structure 10. The planar gate structure 30 is located between the source region 22 and the drain region 23 in a plan view.

[0027] The planar gate structure 30 includes a gate insulating film 31 formed on the semiconductor layer 2 in the device region 6 , and a gate electrode 32 formed on the gate insulating film 31 .

[0028] The gate insulating film 31 is made of an oxide of the semiconductor layer 2. Specifically, the gate insulating film 31 is made of an oxide formed in a film shape by oxidizing the surface portion of the first main surface 3. That is, the gate insulating film 31 is made of a silicon oxide film (SiO ２ The gate insulating film 31 is made of a thermal oxide of the semiconductor layer 2 formed in a film shape by thermally oxidizing the surface portion of the first main surface 3 of the semiconductor layer 2. That is, the gate insulating film 31 is made of a silicon thermal oxide film (thermal oxide film) formed along the first main surface 3. The gate insulating film 31 may have a thickness T1 of 7 nm or more and 13 nm or less (see FIG. 4). The thickness T1 of the gate insulating film 31 may be, for example, 10 nm.

[0029] The gate insulating film 31 extends in the first direction X along the first major surface 3. The gate insulating film 31 has a first surface 31a in contact with the first major surface 3 and a second surface 31b on the opposite side of the first surface 31a from the semiconductor layer 2. The first surface 31a and the second surface 31b may extend parallel to each other, and the gate insulating film 31 may have a substantially constant thickness. Both ends of the gate insulating film 31 in the first direction X are connected to the insulating filling 12.

[0030] In the first main surface 3, recesses 33 are formed on both sides of the gate insulating film 31 to recess the first main surface 3 toward the second main surface 4. The recesses 33 may be formed in the entire area between the gate insulating film 31 and the protruding portion 18 of the insulating filling 12 in the device region 6.

[0031] The gate electrode 32 is made of conductive polysilicon and is formed on the gate insulating film 31. The width (gate length) of the gate electrode 32 in the second direction Y may be 0.13 μm or more and 0.3 μm or less.

[0032] 2 and 3 , the gate electrode 32 crosses the opening end 16 of the trench 11 and reaches above the filling insulating material 12. Specifically, the gate electrode 32 includes a main body portion 35 that faces the first main surface 3 across the gate insulating film 31 in the device region 6, and a lead portion 36 that faces the filling insulating material 12 outside the device region 6.

[0033] The main body 35 is formed as a film extending along the gate insulating film 31 on the gate insulating film 31. The lead-out portion 36 is led out from the main body 35 onto the protruding portion 18 of the insulating embedment 12.

[0034] 1, the semiconductor device 1 includes a memory structure 40 capable of writing, erasing, and reading data. The memory structure 40 is disposed adjacent to the side of the planar gate structure 30 so as to cover the sidewalls of the gate electrode 32. Therefore, the memory structure 40 is also called a sidewall structure.

[0035] Specifically, the memory structure 40 covers the sidewall of the main body 35 of the gate electrode 32 in the device region 6 , and covers the sidewall of the lead-out portion 36 outside the device region 6 .

[0036] The memory structure 40 has a rectangular ring shape surrounding the planar gate structure 30 in a planar view. The memory structure 40 includes a first portion 40A and a second portion 40B facing the device region 6, and a pair of connecting portions 40C connecting the first portion 40A and the second portion 40B. The first portion 40A is a portion located between the source region 22 and the planar gate structure 30. The second portion 40B is a portion located between the drain region 23 and the planar gate structure 30. Each connecting portion 40C is a portion of the memory structure 40 located on an insulating filling 12.

[0037] 2, the memory structure 40 has an inner surface 40a along the sidewall of the planar gate structure 30 and an outer surface 40b curved to protrude toward the opposite side from the planar gate structure 30. The memory structure 40 includes an insulating film 41 formed on the channel region 24, a charge storage film 42 facing the channel region 24 with the insulating film 41 in between, and an insulating spacer 43 formed on the charge storage film 42. The insulating film 41 corresponds to a "first insulating film," and the insulating spacer 43 corresponds to a "second insulating film."

[0038] The insulating film 41 is made of oxides of the semiconductor layer 2 and the gate electrode 32. Specifically, the insulating film 41 is made of oxides formed in a film shape by oxidizing the surface portion of the semiconductor layer 2 and the sidewalls of the gate electrode 32. The insulating film 41 is made of a silicon oxide film (SiO ２ More specifically, insulating film 41 is made of a thermal oxide film formed by thermally oxidizing the surface portion of semiconductor layer 2 and the sidewalls of gate electrode 32. In other words, insulating film 41 is made of a silicon thermal oxide film formed along first main surface 3 and the side surfaces of gate electrode 32.

[0039] The insulating film 41 is made of oxides of the semiconductor layer 2 and the gate electrode 32, and is therefore not formed on the insulating filling 12 (see FIG. 3).

[0040] 4, insulating film 41 may have a thickness T2 of 5 nm to 10 nm, for example, 8 nm. Insulating film 41 is preferably thinner than gate insulating film 31 (T2<T1).

[0041] The insulating film 41 has a first surface 41a in contact with the first main surface 3 of the semiconductor layer 2, a second surface 41b on the opposite side of the semiconductor layer 2 from the first surface 41a, a third surface 41c in contact with the sidewall of the planar gate structure 30 (the sidewall of the gate electrode 32), and a fourth surface 41d on the opposite side of the planar gate structure 30 from the third surface 41c.

[0042] The insulating film 41 includes a first insulating portion 46 that extends along the first main surface 3 of the semiconductor layer 2 in the device region 6, and a second insulating portion 47 that is connected to the first insulating portion 46 and extends along the sidewall of the planar gate structure 30. The insulating film 41 may be formed in an L-shape in cross section by connecting the first insulating portion 46 and the second insulating portion 47 orthogonally.

[0043] Since the insulating film 41 is not formed on the insulating filling 12, the first insulating portion 46 is not provided in the connecting portion 40C of the memory structure 40 (see FIG. 3).

[0044] The insulating film 41 is formed on the first main surface 3 in the recess 33 and adjacent to the gate insulating film 31. The first insulating portion 46 is located closer to the second main surface 4 than the gate insulating film 31. The first surface 41a of the insulating film 41 may be located closer to the second main surface 4 (see FIG. 2 ) than the first surface 31a of the gate insulating film 31. The second surface 41b of the insulating film 41 may be formed flush with the first surface 31a of the gate insulating film 31.

[0045] The charge storage film 42 is made of an insulator different from the insulating film 41, for example, a silicon nitride film (SiN film). The charge storage film 42 is formed along the insulating film 41. The charge storage film 42 may have a thickness T3 of 10 nm or more and 50 nm or less. The thickness T3 of the charge storage film 42 may be, for example, 30 nm.

[0046] The charge storage film 42 has a rectangular ring shape surrounding the planar gate structure 30 in a plan view (see FIG. 1). That is, the charge storage film 42 extends in the first direction X, and both ends of the charge storage film 42 in the first direction X are located outside the device region 6 (see FIG. 3). In this embodiment, both ends of the charge storage film 42 in the first direction X are located on the insulating filling 12.

[0047] The charge storage film 42 includes a first storage portion 48 formed on the first insulating portion 46 of the insulating film 41, and a second storage portion 49 connected to the first storage portion 48 and formed on the side of the second insulating portion 47. The charge storage film 42 may be formed in an L-shape in cross section by connecting the first storage portion 48 and the second storage portion 49 orthogonally.

[0048] The first accumulation portion 48 faces the insulating filling 12 outside the device region 6. In the device region 6, the first accumulation portion 48 faces the semiconductor layer 2 with the first insulating portion 46 of the insulating film 41 interposed therebetween. The second accumulation portion 49 faces the planar gate structure 30 with the second insulating portion 47 of the insulating film 41 interposed therebetween.

[0049] The source region 22 and the drain region 23 are formed in a self-aligned manner with respect to the memory structure 40. Therefore, the boundary between the source region 22 and the channel region 24, in a plan view, substantially coincides with the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3. Similarly, the boundary between the drain region 23 and the channel region 24, in a plan view, substantially coincides with the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3.

[0050] Strictly speaking, the boundary between the source region 22 and the channel region 24 is located slightly closer to the planar gate structure 30 than the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3. Similarly, the boundary between the drain region 23 and the channel region 24 is also located slightly closer to the planar gate structure 30 than the boundary between the outer side surface 40b of the memory structure 40 and the first main surface 3.

[0051] Therefore, the first accumulation portion 48 of the charge accumulation film 42 includes a first opposing portion 48A facing the channel region 24 across the insulating film 41, and a second opposing portion 48B facing the source region 22 and the drain region 23. The first opposing portion 48A is larger than the second opposing portion 48B in a plan view (see FIG. 1).

[0052] The charge storage film 42 has a recess 50 formed by the first storage portion 48 and the second storage portion 49. The recess 50 is provided on the opposite side of the first storage portion 48 from the first insulating portion 46 and on the opposite side of the second storage portion 49 from the second insulating portion 47.

[0053] The insulating spacer 43 is disposed adjacent to the charge storage film 42 in the recess 50. The insulating spacer 43 is made of, for example, silicon oxide. The insulating spacer 43 faces the insulating film 41 with the charge storage film 42 interposed therebetween.

[0054] The semiconductor device 1 further includes a coated insulating film 51 that coats the planar gate structure 30 and the memory structure 40. Both ends of the coated insulating film 51 in the second direction Y are located on the opposite side of the memory structure 40 from the planar gate structure 30. The coated insulating film 51 extends in the first direction X, and both ends of the coated insulating film 51 in the first direction X reach onto the buried insulating material 12 (see FIG. 3 ). Therefore, the coated insulating film 51 coats the source region 22 and the drain region 23 in the device region 6, and coats the buried insulating material 12 outside the device region 6.

[0055] In detail, the covering insulating film 51 integrally has a first covering portion 52 covering the gate electrode 32, a second covering portion 53 covering the outer surface 40b of the memory structure 40, a third covering portion 54 covering the source region 22 and the drain region 23 in the device region 6, and a fourth covering portion 55 (see Figure 3) covering the protrusion 18 of the insulating buried object 12 outside the device region 6.

[0056] The third covering portion 54 covers the source region 22 on the side of the first portion 40A of the memory structure 40, and covers the drain region 23 on the side of the second portion 40B. The fourth covering portion 55 covers the insulating filling 12 on the side of the connecting portion 40C of the memory structure 40 (see FIG. 3). A through-hole 52A is formed in the first covering portion 52 in a region facing the trench insulating structure 10 across the gate electrode 32 (see FIG. 3).

[0057] 2 and 3, semiconductor device 1 includes a gate silicide film 60, a source silicide film 61, and a drain silicide film 62.

[0058] 3, the gate silicide film 60 is formed on the surface of the gate electrode 32 in a portion that forms the bottom of the through hole 52A. The gate silicide film 60 is made of a polycide film that is formed integrally with the gate electrode 32.

[0059] 2, the source silicide film 61 and the drain silicide film 62 are made of silicide films formed integrally with the semiconductor layer 2. The source silicide film 61 is formed in the surface portion of the source region 22 on the side opposite to the memory structure 40 with respect to the coated insulating film 51. The drain silicide film 62 is formed in the surface portion of the drain region 23 on the side opposite to the memory structure 40 with respect to the coated insulating film 51.

[0060] The gate silicide film 60, the source silicide film 61 and the drain silicide film 62 are made of TiSi, TiSi ２ , NiSi, CoSi, CoSi ２ , MoSi ２ and WSi ２ Each of the above may include at least one of the following:

[0061] The semiconductor device 1 includes an interlayer insulating film 65 that covers the first main surface 3. The interlayer insulating film 65 is an oxide film (SiO ２ The interlayer insulating film 65 includes at least one of an oxide film (a silicon nitride film) and a nitride film (a silicon nitride film). The interlayer insulating film 65 may have a single-layer structure made of an oxide film or a nitride film. The interlayer insulating film 65 may have a layered structure in which one or more oxide films and one or more nitride films are layered in any order. The interlayer insulating film 65 covers the trench insulating structure 10 and the device region 6 on the first main surface 3.

[0062] Semiconductor device 1 includes a gate contact electrode 66 , a source contact electrode 67 , and a drain contact electrode 68 that penetrate interlayer insulating film 65 .

[0063] The gate contact electrode 66 is electrically connected to the gate electrode 32 via the gate silicide film 60. Specifically, the gate contact electrode 66 is electrically connected to the gate electrode 32 and faces the insulating filling 12 with the gate electrode 32 interposed therebetween.

[0064] Unlike this embodiment, if the gate electrode 32 extends beyond the insulating filling 12 , the gate contact electrode 66 may face the semiconductor layer 2 outside the insulating filling 12 .

[0065] The source contact electrode 67 is electrically connected to the source region 22 via the source silicide film 61. The drain contact electrode 68 is electrically connected to the drain region 23 via the drain silicide film 62.

[0066] The gate contact electrode 66, the source contact electrode 67, and the drain contact electrode 68 are buried in contact holes 69 formed in the interlayer insulating film 65. Each of the contact electrodes (gate contact electrode 66, source contact electrode 67, and drain contact electrode 68) is made of at least one of copper and tungsten.

[0067] A barrier electrode film may be provided between each contact electrode and the inner wall of the contact hole 69. The barrier electrode film may have a single-layer structure made of a Ti film or a TiN film, or may have a layered structure including a Ti film and a TiN film stacked in any order.

[0068] Semiconductor device 1 includes gate wiring 70, source wiring 71, and drain wiring 72 formed on interlayer insulating film 65. Gate wiring 70 is electrically connected to gate contact electrode 66. Drain wiring 72 is electrically connected to drain contact electrode 68. Source wiring 71 is electrically connected to source contact electrode 67.

[0069] Each of the wirings (gate wiring 70, source wiring 71, and drain wiring 72) may include at least one of an Al film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film.

[0070] A barrier wiring film may be provided between each wiring and the interlayer insulating film 65. The barrier wiring film may have a single layer structure made of a Ti film or a TiN film. The barrier wiring film may have a multilayer structure including a Ti film and a TiN film stacked in any order. The barrier wiring film may also be provided on each wiring.

[0071] 5A to 5E and 6, the operations (write operation, erase operation, and read operation) of the memory structure 40 will be specifically described. In each operation, a reference potential is applied to the back gate region 20 connected to the well region 21.

[0072] 5A is a schematic diagram for explaining the initial state before a write operation of the memory structure 40. FIG. 5B is a schematic diagram for explaining the write operation of the memory structure 40.

[0073] 5A, the gate threshold voltage Vth before potentials are applied to the gate electrode 32, the source region 22, and the drain region 23 is defined as a first threshold voltage Vth1 (initial threshold voltage). The state before potentials are applied to the gate electrode 32, the source region 22, and the drain region 23 refers to a state in which the gate potential Vg, the source potential Vs, and the drain potential Vd are all 0 V (Vg = Vs = Vd = 0 V). The gate potential Vg is the potential applied to the gate electrode 32. The source potential Vs is the potential applied to the source region 22. The drain potential Vd is the potential applied to the drain region 23.

[0074] As shown in FIG. 5B, the write operation is achieved by injecting electrons (hot electrons HE) generated by impact ionization near the source region 22 into the charge storage film 42 .

[0075] Specifically, during a write operation, a positive potential (e.g., 4 V) is applied to the gate electrode 32 and the source region 22 (Vg = Vs = 4 V), and a reference potential (Vd = 0 V) ​​is applied to the drain region 23. This causes a drain-source current Ids to flow from the source region 22 to the drain region 23, concentrating an electric field near the source region 22. As a result, hot electrons HE are generated by impact ionization near the source region 22. The hot electrons HE are injected into the charge storage film 42 (see FIG. 4) of the memory structure 40.

[0076] The gate potential Vg and source potential Vs in the write operation are not limited to 4V, but may be any potential selected from the range of 3V or more and 5V or less, for example.

[0077] The potential difference between the source region 22 and the gate electrode 32 is called the gate-source voltage Vgs. For example, when the gate potential Vg is 4 V and the source potential Vs is 4 V, the gate-source voltage Vgs is 0 V (Vgs=0 V).

[0078] The gate threshold voltage Vth increases due to the negative charge of the electrons injected into the charge storage film 42 by the write operation. Specifically, the gate threshold voltage Vth becomes a second threshold voltage Vth2 (see FIG. 5D) that is higher than the first threshold voltage Vth1 (Vth=Vth2, Vth2>Vth1).

[0079] 5C is a schematic diagram for explaining the erase operation of the memory structure 40. As shown in FIG. 5C, the erase operation is achieved by injecting holes (hot holes HH) generated by the band-to-band tunneling phenomenon into the charge storage film 42.

[0080] More specifically, during an erase operation, a negative potential (for example, −4 V) is applied to the gate electrode 32 (Vg=−4 V), a positive potential (for example, 4 V) is applied to the source region 22 (Vs=4 V), and the drain region 23 is opened. In other words, a high voltage is applied between the source region 22 and the gate electrode 32. As a result, a source-to-backgate current Isb flows from the source region 22 to the backgate region 20 via the well region 21.

[0081] Therefore, hot holes HH are generated by the band-to-band tunneling phenomenon near the boundary between the well region 21 and the source region 22. The hot holes HH are injected into the charge storage film 42 of the memory structure 40 (see FIG. 4).

[0082] The gate potential Vg in the erase operation is not limited to −4 V, and may be a potential arbitrarily selected from the range of −5 V to −3 V. The source potential Vs in the erase operation is not limited to 4 V, and may be a potential arbitrarily selected from the range of 3 V to 5 V.

[0083] In an erase operation, when the gate potential Vg is −4 V and the source potential Vs is 4 V, the gate-source voltage Vgs is 8 V (Vgs=8 V). For example, when the thickness T2 of the insulating film 41 is 8 nm and the thickness T1 of the gate insulating film is 10 nm, the insulating film 41 is thinner than the gate insulating film 31. Therefore, compared to a configuration in which the thicknesses of the insulating film 41 and the gate insulating film 31 are the same, the gate-source voltage Vgs is more efficiently divided by the charge storage film 42. Therefore, an electric field is more likely to concentrate near the source region 22, making it easier to generate hot holes HH.

[0084] The gate threshold voltage Vth decreases due to the positive charges of the holes injected into the charge storage film 42 by the erase operation. Specifically, the gate threshold voltage Vth returns from the second threshold voltage Vth2 to the first threshold voltage Vth1 (see FIG. 5E) (Vth=Vth1).

[0085] Next, the read operation of the memory structure 40 will be described. Fig. 5D is a schematic diagram for explaining the read operation after the write operation. Fig. 5E is a schematic diagram for explaining the read operation after the erase operation (i.e., the initial state). Fig. 6 is a graph showing the relationship between the gate potential Vg and the drain-source current Ids after the write operation and the erase operation.

[0086] During a read operation, a drain-source current Ids flows in the opposite direction to that during a write operation. The magnitude of the drain-source current Ids determines whether data has been written to the memory structure 40. Specifically, during a read operation after either a write operation or an erase operation, a positive potential (e.g., 1.5 V) is applied to the gate electrode 32, a positive potential (e.g., 0.5 V) is applied to the drain region 23, and a reference potential (Vs=0 V) is applied to the source region 22.

[0087] When the gate potential Vg is 1.5 V and the drain potential Vd is 0.5 V, the potential difference between the drain region 23 and the gate electrode 32 (drain-gate voltage Vdg) is 1.0 V (Vg=1.5 V, Vd=0.5 V, Vdg=1.0 V).

[0088] The gate threshold voltage Vth (second threshold voltage Vth2) after the write operation is greater than the gate threshold voltage (first threshold voltage Vth1) after the erase operation. Therefore, as shown in FIG. 6 , when the gate potential Vg is a predetermined read potential Vr (Vg=Vr) during a read operation, the drain-source current Ids2 during the read operation after the write operation is smaller than the drain-source current Ids1 during the read operation after the erase operation. This current difference ΔI (ΔI=Ids1−Ids2) can be used to determine whether data has been written to the memory structure 40.

[0089] The first threshold voltage Vth1 is, for example, 0.7 V or more and 2.0 V or less, and the second threshold voltage Vth2 is a voltage obtained by adding a potential to the first threshold voltage Vth1. For example, when the first threshold voltage Vth1 is 1.0, the second threshold voltage Vth2 is a higher voltage (1.2 V or more and 5.0 V or less). The read potential Vr is, for example, 1.5 V or more and 5.0 V or less.

[0090] In this embodiment, the bottoms of the source region 22 and the drain region 23 are flat without any steps, and no LDD regions are provided in the source region 22 and the drain region 23. Therefore, the charge storage film 42 faces the channel region 24. In addition, in this embodiment, boron is additionally implanted into the channel region 24 to form a p-type impurity region 21A. This makes it easy to generate hot carriers. Therefore, hot electrons HE can be injected into the charge storage film 42 at a low voltage during a write operation, and hot holes HH can be drawn into the charge storage film 42 at a low voltage during an erase operation. This allows data to be written to and erased from the memory structure 40 repeatedly and efficiently, while also reducing the voltage required for writing and erasing.

[0091] Furthermore, by making the insulating film 41 thinner than the gate insulating film 31, the gate-source voltage Vgs can be efficiently divided by the charge storage film 42. Therefore, the hot holes HH can be easily drawn into the charge storage film 42.

[0092] In this embodiment, the memory structure 40 is covered with the insulating cover film 51. Therefore, the memory structure 40 can be prevented from being silicided.

[0093] In this embodiment, the coated insulating film 51 partially covers the source region 22 and the drain region 23 on the sides of the memory structure 40. The source silicide film 61 and the drain silicide film 62 are formed on the surfaces of the source region 22 and the drain region 23, respectively, on the side opposite to the memory structure 40 with respect to the coated insulating film 51. Therefore, compared to a configuration in which the coated insulating film 51 does not cover the source region 22 and the drain region 23, the source silicide film 61 and the drain silicide film 62 can be located farther away from the charge storage film 42. This makes it possible to suppress the outflow of electrons from the charge storage film 42.

[0094] In this embodiment, the charge storage film 42 has a recess 50 on the opposite side of the first storage portion 48 from the planar gate structure 30 and on the opposite side of the second storage portion 49 from the semiconductor layer 2, and the insulating spacer 43 is disposed in the recess 50. Therefore, the charge storage film 42 is surrounded by the insulating film 41 and the insulating spacer 43, i.e., the insulator. Therefore, the gate-source voltage Vgs can be efficiently divided by the charge storage film 42.

[0095] Figures 7A to 7Z are cross-sectional views for explaining an example of a method for manufacturing the semiconductor device 1 shown in Figure 1. Figures 7A to 7Z are cross-sectional views of a region corresponding to Figure 2. Figures 7A to 7Z only show a method for manufacturing the device region 6 where a MOSFET is formed.

[0096] 7A, a semiconductor wafer 75 is prepared. The semiconductor wafer 75 serves as the base of the semiconductor layer 2. The semiconductor wafer 75 has a first wafer main surface 76 on one side and a second wafer main surface 77 on the other side. The first wafer main surface 76 and the second wafer main surface 77 correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively (see FIG. 2).

[0097] Next, a resist mask 80 having a predetermined pattern is formed on the semiconductor wafer 75. The resist mask 80 exposes the region of the semiconductor wafer 75 where the trench 11 is to be formed, and covers the other regions.

[0098] 7B, unnecessary portions of the first wafer main surface 76 are removed by etching through the resist mask 80. The etching may be dry etching (e.g., RIE) and / or wet etching. The etching is preferably dry etching (e.g., RIE).

[0099] As a result, trenches 11 that define the device regions 6 are formed in the first wafer main surface 76. The resist mask 80 is then removed. A detailed description of the trenches 11 has been given above and will be omitted here.

[0100] 7C , a base insulating film 81, which serves as a base for the insulating filling 12, is formed on the first wafer main surface 76. In this embodiment, the base insulating film 81 is made of silicon oxide. The base insulating film 81 may be formed by a CVD method. The base insulating film 81 fills the trench 11.

[0101] 7D , unnecessary portions of the base insulating film 81 are removed by etching. The base insulating film 81 is removed until the first wafer main surface 76 is exposed. The etching may be a dry etching method (e.g., RIE) and / or a wet etching method. As a result, the insulating filling 12 located in the trench 11 is formed.

[0102] 7E, a first base film 82 that serves as a base for the gate insulating film 31 (see FIG. 2) is formed on the surface portion of the first wafer main surface 76 in the device region 6. The first base film 82 is made of an oxide of the semiconductor wafer 75. The first base film 82 is formed by oxidizing the surface portion of the first wafer main surface 76 into a film using an oxidation process. Specifically, the first base film 82 is formed by a thermal oxidation process.

[0103] According to the oxidation process (thermal oxidation process), a silicon oxide film (silicon thermal oxide film) is formed along the first wafer main surface 76. The thickness of the first base film 82 may be the same as the thickness T1 of the gate insulating film 31 (see FIG. 4), i.e., 7 nm to 13 nm. The first base film 82 is integral with the insulating filling 12.

[0104] 7F , a p-type well region 21 is formed in the surface portion of the first wafer main surface 76 in the device region 6. The well region 21 is formed by introducing p-type impurities into the surface portion of the first wafer main surface 76 by ion implantation via the gate insulating film 31. By forming the well region 21, a region in the semiconductor wafer 75 having a lower p-type impurity concentration than the well region 21 becomes the back gate region 20.

[0105] 7G, a p-type impurity region 21A for adjusting the write voltage is formed in the surface portion of the p-type well region 21. The p-type impurity region 21A has a concentration different from that of the p-type well region 21. The conditions for forming the p-type impurity region 21A are, for example, when the p-type impurity element is boron (B+), an acceleration energy of 25 keV, and a dose of 3.6×10 １３ cm －2 In this case, when the normal transistor and the memory transistor are provided separately, a resist mask 21B having a predetermined pattern is formed on the surface and then the p-type impurity is introduced so that the impurity is selectively additionally injected into the p-well region where the memory transistor is formed.

[0106] 7F and 7G may be performed at any timing. For example, the introduction of the p-type impurity into the first wafer main surface 76 may be performed before the gate insulating film 31 is formed on the first wafer main surface 76. In this case, a sacrificial oxide film may be formed on the first wafer main surface 76, and the p-type impurity may be introduced into the first wafer main surface 76 through the sacrificial oxide film. Then, after the sacrificial oxide film is removed, the gate insulating film 31 is formed.

[0107] 7H, the gate electrode 32 is formed on the first wafer main surface 76 so as to cover the first base film 82 and the insulating filling 12. In this embodiment, the gate electrode 32 is made of conductive polysilicon. The gate electrode 32 may be formed by a CVD method.

[0108] Next, referring to FIG. 7I, a resist mask 87 having a predetermined pattern is formed on the gate electrode 32. The resist mask 87 exposes unnecessary portions of the gate electrode 32 and covers the remaining regions. Next, the unnecessary portions of the gate electrode 32 are removed by etching through the resist mask 87. The etching method may be dry etching (e.g., RIE) and / or wet etching. The wet etching may be performed by supplying HF (hydrofluoric acid), for example. This forms the gate electrode 32. Thereafter, as shown in FIG. 7J, the resist mask 87 is removed.

[0109] 7K , the first base film 82 is partially removed by etching to form the gate insulating film 31. Due to the partial removal of the first base film 82, the first wafer main surface 76 is recessed toward the second wafer main surface 77 on the side of the gate insulating film 31. Due to the recession of the first wafer main surface 76, a first recess 78 is formed on the side of the planar gate structure 30, recessing the first wafer main surface 76 toward the second wafer main surface 77. In this manner, due to the partial removal of the first base film 82, the gate insulating film 31 is formed and the first recess 78 is also formed. Due to the recession of the first wafer main surface 76, a portion of the insulating filling 12 protrudes from the trench 11.

[0110] The etching method may be a dry etching method (for example, an RIE method) and / or a wet etching method. By partially removing the first base film 82, a planar gate structure 30 including a gate insulating film 31 and a gate electrode 32 is formed.

[0111] 7L, a second base film 83, which serves as a base for the insulating film 41 (see FIG. 2), is formed on the surface portion of the first wafer main surface 76 in the first recess 78 and on the surface portion of the gate electrode 32. The second base film 83 is made of oxides of the semiconductor wafer 75 and the gate electrode 32. The second base film 83 is formed by oxidizing the surface portion of the semiconductor wafer 75 in the device region 6 and the surface portion of the gate electrode 32 into a film using an oxidation process. Specifically, the second base film 83 is formed by a thermal oxidation process.

[0112] According to the oxidation treatment method (thermal oxidation treatment method), a silicon oxide film (silicon thermal oxide film) is formed along the first wafer main surface 76 and the gate electrode 32. The thickness of the second base film 83 may be the same as the thickness T2 of the insulating film 41 (see FIG. 4), that is, 5 nm or more and 10 nm or less.

[0113] Next, referring to FIG. 7M , a third base film 84, which serves as the base of the charge storage film 42, is formed on the first wafer main surface 76 so as to cover the second base film 83 and the insulating embedding 12. In this embodiment, the third base film 84 is made of silicon nitride. The third base film 84 may be formed by a CVD method. The thickness of the third base film 84 may be the same as the thickness T3 of the charge storage film 42 (see FIG. 4 ), i.e., between 10 nm and 50 nm.

[0114] 7N, a fourth base film 85, which will serve as the base of the insulating spacer 43 (see FIG. 2), is formed on the first wafer main surface 76 so as to cover the third base film 84. In this embodiment, the fourth base film 85 is made of silicon oxide. The fourth base film 85 may be formed by a CVD method.

[0115] 7O , the second base film 83, the third base film 84, and the fourth base film 85 are partially removed by etching so as to leave portions covering the sidewalls of the planar gate structure 30. This forms the memory structure 40 made up of the insulating film 41, the charge storage film 42, and the insulating spacer 43. That is, the memory structure 40 is formed in a self-aligned manner with the planar gate structure 30. The etching method may be a dry etching method (e.g., an RIE method).

[0116] The partial removal of the second base film 83 causes the first wafer main surface 76 to further recede toward the second wafer main surface 77 on the sides of the memory structure 40. As the first wafer main surface 76 recede toward the second wafer main surface 77, the first recess 78 on the sides of the planar gate structure 30 deepens, forming a second recess 79. The insulating film 41 is disposed on the first wafer main surface 76 within the second recess 79. The second recess 79 corresponds to the recess 33 (see FIG. 4 ). The recede of the first wafer main surface 76 increases the amount of protrusion of the insulating filling 12 from the trench 11.

[0117] 7P, an n-type drain region 23 and an n-type source region 22 are formed in the surface portion of the well region 21. Specifically, the source region 22 is formed in the surface portion of the well region 21 on one side of the memory structure 40 by introducing n-type impurities into the surface portion of the well region 21 by ion implantation using the memory structure 40 as a mask. The drain region 23 is formed in the surface portion of the well region 21 on the other side of the memory structure 40 by introducing n-type impurities into the surface portion of the well region 21 by ion implantation using the memory structure 40 as a mask. In other words, the drain region 23 and the source region 22 are each formed in a self-aligned manner with respect to the memory structure 40.

[0118] 7Q, a coated insulating film 51 is formed on the device region 6 and the insulating filling 12. In this embodiment, the coated insulating film 51 is made of silicon oxide. The coated insulating film 51 may be formed by a CVD method.

[0119] 7R, a resist mask 89 having a predetermined pattern is formed on the coated insulating film 51. The resist mask 89 exposes unnecessary portions of the coated insulating film 51 and covers the remaining regions. Next, the unnecessary portions of the coated insulating film 51 are removed by etching using the resist mask 89.

[0120] 7S, portions of the insulating coating film 51 that cover the planar gate structure 30 and the memory structure 40 and portions that cover the device region 6 on the sides of the memory structure 40 remain. The portions of the insulating coating film 51 that cover the gate electrode 32 outside the device region 6 are removed to form through-holes 52A. The etching method may be dry etching (e.g., RIE) and / or wet etching. Thereafter, the resist mask 89 is removed.

[0121] 7T, a gate silicide film 60, a source silicide film 61, and a drain silicide film 62 are formed. In this step, a metal film 88 is first formed to cover the first wafer main surface 76 and the gate electrode 32 in the device region 6. The metal film 88 contains at least one of Ti, Ni, Co, Mo, and W. The metal film 88 may be formed by sputtering or vapor deposition.

[0122] Next, the gate electrode 32 and the portion of the first wafer main surface 76 that is in contact with the metal film 88 are silicided. The silicidation may be performed by an annealing method (for example, an RTA (rapid thermal anneal) method). As a result, TiSi, TiSi ２ , NiSi, CoSi, CoSi ２ , MoSi ２ and WSi ２ The gate silicide film 60, the drain silicide film 62, and the source silicide film 61 are formed, each including at least one of the following: The metal film 88 is then removed.

[0123] 7U, an interlayer insulating film 65 is formed on the first wafer main surface 76. The interlayer insulating film 65 includes at least one of an oxide film and a nitride film. The interlayer insulating film 65 may be formed by a CVD method. The interlayer insulating film 65 covers the trench isolation structure 10 and the planar gate structure 30 on the first wafer main surface 76.

[0124] 7V , a resist mask 93 having a predetermined pattern is formed on the interlayer insulating film 65. The resist mask 93 exposes regions of the interlayer insulating film 65 where a plurality of contact holes 69 are to be formed, and covers other regions. Next, unnecessary portions of the interlayer insulating film 65 are removed by etching via the resist mask 93. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, a plurality of contact holes 69 are formed in the interlayer insulating film 65 at positions corresponding to the gate electrode 32, the source region 22, and the drain region 23, respectively. The contact hole 69 corresponding to the gate electrode 32 communicates with the through hole 52A that penetrates the coating insulating film 51. The resist mask 93 is then removed.

[0125] 7W , a base contact electrode film 90 serving as a base for gate contact electrode 66, drain contact electrode 68, and source contact electrode 67 is formed on interlayer insulating film 65, filling a plurality of contact holes 69. Base contact electrode film 90 may be formed by sputtering or vapor deposition.

[0126] 7X, unnecessary portions of base contact electrode film 90 are removed by etching. Base contact electrode film 90 is removed until interlayer insulating film 65 is exposed. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, gate contact electrode 66, drain contact electrode 68, and source contact electrode 67 are formed.

[0127] 7Y, a base wiring film 91 serving as a base for the gate wiring 70, the drain wiring 72, and the source wiring 71 is formed on the interlayer insulating film 65. The base wiring film 91 may be formed by sputtering or vapor deposition.

[0128] 7Z, a resist mask 92 having a predetermined pattern is formed on the base wiring film 91. The resist mask 92 covers regions of the interlayer insulating film 65 where the gate wiring 70, the drain wiring 72, and the source wiring 71 are to be formed, and leaves the other regions exposed.

[0129] Next, unnecessary portions of the base wiring film 91 are removed by etching via the resist mask 92. The etching may be dry etching (e.g., RIE) and / or wet etching. As a result, the gate wiring 70, source wiring 71, and drain wiring 72 are formed on the interlayer insulating film 65. The resist mask 92 is then removed. The semiconductor wafer 75 is then cut into a plurality of semiconductor devices 1. The semiconductor device 1 is manufactured through the processes including those described above.

[0130] According to this manufacturing method, the memory structure 40 is formed in a self-aligned manner without using a resist mask, which makes it possible to form the memory structure 40 more efficiently than in a method of forming a memory structure using a resist mask.

[0131] The present invention is not limited to the above-described embodiment, and can be embodied in other forms.

[0132] For example, in the above-described embodiment, an n-type (first polarity type) MOSFET is formed, which includes a p-type well region 21, an n-type source region 22, and an n-type drain region 23. However, unlike the above-described embodiment, a p-type (second polarity type) MOSFET may be formed, which includes an n-type well region 21, a p-type source region 22, and a p-type drain region 23.

[0133] Various aspects of the present disclosure are summarized below as appendices. a first region and a second region formed in a surface portion of the main surface of the semiconductor layer and spaced apart from each other in a first direction; a third region formed in a channel region between the first region and the second region and in the surface portion of the main surface of the semiconductor layer; a planar gate structure including a gate insulating film and a gate electrode stacked in a second direction on the main surface of the semiconductor layer so as to face the third region; and sidewall structures arranged adjacent to a lateral side of the planar gate structure on the first region side in the first direction, wherein a conductivity type of the first region and the second region is a first conductivity type, and a conductivity type of the well region and the third region is a second conductivity type, the sidewall structure including a first insulating film and a second insulating film, and a charge storage film arranged between the first insulating film and the second insulating film, the first insulating film being adjacent to the planar gate structure in the first direction,

[0134] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein an impurity concentration of the third region is higher than an impurity concentration of the well region, and a depth of the third region is shallower than a depth of the well region.

[0135] (Note 3) The impurity concentration of the well region is 10×10 １２ cm －３ Higher, 10x10 １６ cm －３ the impurity concentration of the third region is 10×10 or less １６ cm －３ Higher, 10x10 １７ cm －３ 3. The semiconductor device according to claim 1, wherein:

[0136] (Supplementary Note 4) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, wherein the semiconductor layer is silicon, and the impurity in the third region is boron.

[0137] (Supplementary Note 5) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the memory structure is configured to inject hot electrons into the charge storage film during a write operation and to draw hot holes into the charge storage film during an erase operation.

[0138] (Supplementary Note 6) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 5, wherein the thickness of the first insulating film is smaller than the thickness of the gate insulating film.

[0139] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, wherein a recess that recesses the main surface of the semiconductor layer is provided on a side of the gate insulating film, and the first insulating film is formed on the main surface of the semiconductor layer within the recess so as to be adjacent to the gate insulating film.

[0140] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, wherein the charge storage film is an insulator different from the first insulating film.

[0141] (Note 9) The charge storage film is made of SiN, and the first insulating film is made of SiO ２ 9. The semiconductor device according to claim 1, wherein:

[0142] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, wherein the charge storage film includes a first storage portion facing the main surface of the semiconductor layer across the first insulating film, and a second storage portion facing the planar gate structure across the first insulating film.

[0143] (Appendix 11) The semiconductor device described in Appendix 10, wherein the charge storage film has a recess on the opposite side of the first insulating film with respect to the first storage portion and on the opposite side of the first insulating film with respect to the second storage portion, and the second insulating film is arranged adjacent to the charge storage film within the recess.

[0144] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 11, further comprising a covering insulating film that covers the planar gate structure and the memory structure.

[0145] (Appendix 13) The semiconductor device according to appendix 12, wherein the covering insulating film covers the first region and the second region on the sides of the memory structure, and further includes a silicide film formed on the surface portions of the first region and the second region on the opposite side of the covering insulating film from the memory structure side.

[0146] (Appendix 14) A method for manufacturing a semiconductor device, comprising the steps of: forming a well region of a second conductivity type in a surface portion of a main surface of a semiconductor wafer; forming an impurity region of the second conductivity type, the impurity region having a higher concentration than the well region, in at least a part of the surface portion of the well region; forming a planar gate structure on the main surface; forming a memory structure, on a side of the planar gate structure, the memory structure having an insulating film disposed on the main surface and a charge storage film disposed on the insulating film; forming a source region of a first conductivity type in a surface portion of the well region on one side of the memory structure, and forming a drain region of the first conductivity type in the surface portion of the well region on the other side of the memory structure, with the impurity region of the second conductivity type facing the planar gate structure and the charge storage film sandwiched between the source region and the source region.

[0147] (Supplementary Note 15) The method for manufacturing a semiconductor device according to Supplementary Note 14, wherein the step of forming the planar gate structure includes the steps of forming a gate insulating film on the main surface of the semiconductor wafer and forming a gate electrode on the gate insulating film.

[0148] (Appendix 16) A method for manufacturing a semiconductor device according to Appendix 15, wherein the step of forming the gate insulating film includes the steps of forming a first base film on a surface portion of the main surface of the semiconductor wafer, and partially removing the first base film to form the gate insulating film and to form a recess that recesses the main surface to the side of the gate insulating film, and the step of forming the memory structure includes the step of forming a second base film that serves as a base for the insulating film on the surface portion of the main surface of the semiconductor wafer within the recess.

[0149] (Supplementary Note 17) The method for manufacturing a semiconductor device according to Supplementary Note 16, wherein the first base film and the second base film are formed by a thermal oxidation process.

[0150] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0151] 1 semiconductor device, 2 semiconductor layer, 3 first main surface, 4 second main surface, 6 device region, 10 trench insulation structure, 11 trench, 12 insulating buried material, 13 inner wall, 14 outer wall, 15 bottom wall, 16 opening edge, 17 buried portion, 18 protrusion, 20 back gate region, 21 well region, 21A p-type impurity region, 21B, 80, 87, 89, 92, 93 resist mask, 22 source region, 23 drain region, 24 channel region, 30 planar gate structure, 31 gate insulating film, 32 gate electrode, 35 main body portion, 36 lead-out portion, 40 memory structure, 41 insulating film, 42 charge storage film, 43 insulating spacer, 50 recess, 51 covering insulating film, 60 gate silicide film, 61 source silicide film, 62 drain silicide film, 65 interlayer insulating film, 66 Gate contact electrode, 67 source contact electrode, 68 drain contact electrode, 69 contact hole, 70 gate wiring, 71 source wiring, 72 drain wiring, 75 semiconductor wafer, 76 first wafer main surface, 77 second wafer main surface, 81 base insulating film, 82 first base film, 83 second base film, 84 third base film, 85 fourth base film, 88 metal film, 90 base contact electrode film, 91 base wiring film.

Claims

1. A semiconductor device comprising: a semiconductor layer having a primary surface; a well region formed in a surface portion of the main surface of the semiconductor layer; a first region and a second region formed on a surface portion of the well region and spaced apart from each other in a first direction; a third region formed in a channel region between the first region and the second region on a surface portion of the main surface of the semiconductor layer; a planar gate structure including a gate insulating film and a gate electrode stacked in a second direction on the main surface of the semiconductor layer so as to face the third region; a sidewall structure disposed adjacent to a side of the planar gate structure on a side of the first region in the first direction, the first region and the second region have a first conductivity type; the well region and the third region have a second conductivity type; The sidewall structure is A first insulating film and a second insulating film; a charge storage film disposed between the first insulating film and the second insulating film; the first insulating film is adjacent to the planar gate structure in the first direction; The first insulating film, the second insulating film and the charge storage film form a memory structure.

2. an impurity concentration of the third region is higher than an impurity concentration of the well region; The semiconductor device according to claim 1 , wherein a depth of said third region is shallower than a depth of said well region.

3. The impurity concentration of the well region is 10×10 １２ cm －３ Higher, 10x10 １６ cm －３ is as follows: The impurity concentration of the third region is 10×10 １６ cm －３ Higher, 10x10 １７ cm －３ 2. The semiconductor device according to claim 1, wherein:

4. the semiconductor layer is silicon; 2. The semiconductor device according to claim 1, wherein the impurity in said third region is boron.

5. 5. The semiconductor device according to claim 1, wherein the memory structure is configured to inject hot electrons into the charge storage film during a write operation and to draw hot holes into the charge storage film during an erase operation.

6. The semiconductor device according to claim 1 , wherein the first insulating film has a thickness smaller than a thickness of the gate insulating film.

7. a recess for recessing the main surface of the semiconductor layer is provided on a side of the gate insulating film; 5 . The semiconductor device according to claim 1 , wherein the first insulating film is formed on the main surface of the semiconductor layer in the recess so as to be adjacent to the gate insulating film.

8. The semiconductor device according to claim 1 , wherein the charge storage film is an insulator different from the first insulating film.

9. The charge storage film is made of SiN, and the first insulating film is made of SiO ２ The semiconductor device according to claim 1 , comprising:

10. 5. The semiconductor device according to claim 1, wherein the charge storage film includes a first storage portion facing the main surface of the semiconductor layer across the first insulating film, and a second storage portion facing the planar gate structure across the first insulating film.

11. the charge storage film has a recess on a side opposite to the first insulating film with respect to the first storage portion and on a side opposite to the first insulating film with respect to the second storage portion, The semiconductor device according to claim 10 , wherein the second insulating film is disposed adjacent to the charge storage film in the recess.

12. 5. The semiconductor device according to claim 1, further comprising an insulating film covering said planar gate structure and said memory structure.

13. the insulating coating layer covers the first region and the second region on sides of the memory structure; 13. The semiconductor device according to claim 12, further comprising a silicide film formed on a surface portion of said first region and said second region on a side opposite to said memory structure with respect to said insulating cover film.

14. forming a well region of a second conductivity type in a surface portion of a main surface of the semiconductor wafer; forming an impurity region of a second conductivity type having a higher concentration than the well region in at least a part of a surface of the well region; forming a planar gate structure on the major surface; forming a memory structure on a side of the planar gate structure, the memory structure having an insulating film disposed on the main surface and a charge storage film disposed on the insulating film; forming a source region of a first conductivity type in a surface portion of the well region on one side of the memory structure, and forming a drain region of the first conductivity type in the surface portion of the well region on the other side of the memory structure, sandwiching the impurity region of a second conductivity type facing the planar gate structure and the charge storage film between the source region and the impurity region.

15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the step of forming a planar gate structure includes the steps of: forming a gate insulating film on the main surface of the semiconductor wafer; and forming a gate electrode on the gate insulating film.

16. The step of forming the gate insulating film includes a step of forming a first base film on a surface portion of the main surface of the semiconductor wafer, and a step of forming the gate insulating film and forming a recess that recesses the main surface on a side of the gate insulating film by partially removing the first base film, 16. The method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the memory structure includes the step of forming a second base film serving as a base for the insulating film on a surface portion of the main surface of the semiconductor wafer within the recess.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the first base film and the second base film are formed by a thermal oxidation process.