Semiconductor device

Abstract

A semiconductor device (10) comprises: a semiconductor layer (14) including a peripheral region (40) and an inner region (42); a gate wire (44); and a source wire (34). A plurality of peripheral gate fingers (46) of the gate wire (44) are spaced apart from each other by a plurality of gaps (48) disposed along the outer edge of the inner region (42). The inner region (42) includes a plurality of sub-regions (52) divided by at least two mutually intersecting inner gate fingers (50) of the gate wire (44). A peripheral segment (58) of the source wire (34) is continuous with at least two of a plurality of inner segments (56) that are respectively disposed in the plurality of sub-regions (52). Each of the at least two inner segments (56) is connected to the peripheral segment (58) via a gap (48), among the plurality of gaps (48), that is adjacent to the sub-region (52) in which the inner segment (56) is disposed.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Japanese Patent Application Laid-Open No. 2006-129999 discloses a semiconductor device having a trench gate structure in which a gate electrode is embedded in a gate trench. The semiconductor device described in Japanese Patent Application Laid-Open No. 2006-129999 includes a gate main surface electrode that integrally includes a gate pad electrode and a gate finger electrode. The gate finger electrode is electrically connected to multiple gate electrodes of the trench gate structure via multiple gate plug electrodes.

[0003] Japanese Patent Application Laid-Open No. 2021-125649

[0004] In a semiconductor device having a trench gate structure, the shorter the length of the gate trench, the lower the resistance of the electrode (e.g., gate electrode) embedded in the gate trench. However, the resistance and parasitic capacitance caused by the wiring layout (e.g., gate fingers) for reducing the length of the gate trench may adversely affect the switching characteristics of the semiconductor device.

[0005] a plurality of gate trenches formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a plurality of gate electrodes, each of which is embedded in a corresponding one of the gate trenches via the insulating layer; a plurality of field plate electrodes, each of which is embedded in a corresponding one of the gate trenches via the insulating layer while being spaced from the gate electrode; a gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes; and a source wiring formed on the insulating layer, spaced from the gate wiring and electrically connected to the plurality of field plate electrodes. The gate wiring includes: a plurality of peripheral gate fingers arranged in the peripheral region, the plurality of peripheral gate fingers being separated from one another by a plurality of gaps arranged along the outer edge of the inner region; and a plurality of inner gate fingers arranged in the inner region, each of the plurality of inner gate fingers being connected to at least one of the plurality of peripheral gate fingers. The inner region includes a plurality of subregions separated by at least two of the plurality of inner gate fingers that intersect with one another. The source wiring includes a plurality of inner segments arranged in the plurality of subregions, respectively, and a peripheral segment arranged in the peripheral region. The peripheral segment is continuous with at least two of the plurality of inner segments, and each of the at least two inner segments is connected to the peripheral segment via a gap of the plurality of gaps adjacent to the subregion in which the inner segment is arranged.

[0006] According to the semiconductor device of the present disclosure, the resistance and parasitic capacitance caused by the wiring layout can be reduced, thereby improving the switching characteristics.

[0007] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 1. FIG. 4 is a schematic plan view of an exemplary semiconductor device according to a comparative example. FIG. 5 is a graph showing the feedback capacitance of the semiconductor device. FIG. 6 is a schematic plan view of an exemplary semiconductor device according to a second embodiment. FIG. 7 is a schematic plan view of an exemplary semiconductor device according to a third embodiment. FIG. 8 is a schematic cross-sectional view of an exemplary semiconductor device for explaining a modification of the trench gate structure.

[0008] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] First Embodiment FIG. 1 is a schematic plan view of an exemplary semiconductor device 10 according to a first embodiment. The semiconductor device 10 may be, for example, a MISFET having a trench gate structure. The semiconductor device 10 includes a semiconductor substrate 12, a semiconductor layer 14 formed on the semiconductor substrate 12, a plurality of gate trenches 16 formed in the semiconductor layer 14, and an insulating layer 18 formed on the semiconductor layer 14. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 is a direction perpendicular to the surface of the semiconductor substrate 12. Note that the term "plan view" used in this specification refers to viewing the semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

[0011] In this embodiment, the semiconductor substrate 12 may be a Si substrate, and the semiconductor layer 14 may be a Si epitaxial layer. In FIG. 1, reference numerals 12 and 14 indicate the rectangular outer edges of the semiconductor substrate 12 and the semiconductor layer 14. The area defined by the outer edge of the semiconductor substrate 12 shown in FIG. 1 may correspond to one chip (die). The insulating layer 18 may be made of silicon oxide (SiO ２ ) layer and / or silicon nitride (SiN) layer.

[0012] (Example of Trench Gate Structure) FIG. 2 is a schematic cross-sectional view of the semiconductor device 10 taken along line F2-F2 in FIG. 1. While FIG. 2 shows a cross-section in the YZ plane of the gate trenches 16 of the first set S1, the cross-sections of the gate trenches 16 of the third set S3 and the gate trenches 16 of the fifth set S5 may also be similar to FIG. 2. Furthermore, the cross-sections in the XZ plane of the gate trenches 16 of the second set S2 and the gate trenches 16 of the fourth set S4 may also be similar to FIG. 2. While the following mainly describes one gate trench 16 and related configuration, it should be noted that such description may be similarly applied to other gate trenches and related configurations.

[0013] The semiconductor substrate 12 may include a top surface 12A and a bottom surface 12B opposite the top surface 12A. The semiconductor substrate 12 may correspond to a drain region of a MISFET. The Z-axis direction is a direction perpendicular to the top surface 12A and the bottom surface 12B of the semiconductor substrate 12.

[0014] The semiconductor layer 14 includes a drift region 20 formed on the semiconductor substrate (drain region) 12 , a body region 22 formed on the drift region 20 , and a source region 24 formed on the body region 22 .

[0015] The drain region formed by the semiconductor substrate 12 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 12 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The semiconductor substrate 12 may have a thickness of 50 μm or more and 450 μm or less.

[0016] The drift region 20 may be an n-type region containing n-type impurities at a concentration lower than that of the semiconductor substrate (drain region) 12. The n-type impurity concentration of the drift region 20 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The drift region 20 may have a thickness of 1 μm or more and 25 μm or less.

[0017] The body region 22 may be a p-type region containing p-type impurities. The p-type impurity concentration of the body region 22 may be 1×10 １６ cm －３ 1x10 or more １８ cm －３ The body region 22 may have a thickness of not less than 0.2 μm and not more than 1.0 μm.

[0018] The source region 24 may be an n-type region containing n-type impurities at a higher concentration than the drift region 20. The n-type impurity concentration of the source region 24 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The source region 24 may have a thickness of 0.1 μm or more and 1 μm or less.

[0019] In this disclosure, n-type is also referred to as a first conductivity type, and p-type is also referred to as a second conductivity type. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc. The p-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0020] The semiconductor device 10 may further include a drain electrode 26 formed on the bottom surface 12B of the semiconductor substrate 12. The drain electrode 26 is electrically connected to the semiconductor substrate (drain region) 12. The drain electrode 26 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0021] The gate trench 16 has an opening in the upper surface 14A of the semiconductor layer 14 and has a depth in the Z-axis direction. The gate trench 16 has sidewalls 16A and a bottom wall 16B. The gate trench 16 penetrates the source region 24 and the body region 22 of the semiconductor layer 14 to reach the drift region 20. Therefore, the bottom wall 16B of the gate trench 16 is adjacent to the drift region 20. The gate trench 16 may have a depth of 1 μm or more and 10 μm or less. The depth of the gate trench 16 may correspond to the distance in the Z-axis direction from the upper surface 14A of the semiconductor layer 14 to the bottom wall 16B of the gate trench 16.

[0022] The sidewall 16A of the gate trench 16 may extend in the Z-axis direction (a direction perpendicular to the top surface 14A of the semiconductor layer 14) or may be inclined with respect to the Z-axis direction. In one example, the sidewall 16A may be inclined with respect to the Z-axis direction so that the width of the gate trench 16 decreases toward the bottom wall 16B. In addition, the bottom wall 16B of the gate trench 16 does not necessarily have to be flat, and may be curved in part or entirely, for example.

[0023] The semiconductor device 10 includes a plurality of gate electrodes 28 and a plurality of field plate electrodes 30. Each of the plurality of gate electrodes 28 is embedded in a corresponding one of the plurality of gate trenches 16 via an insulating layer 18. Each of the plurality of field plate electrodes 30 is embedded in a corresponding one of the plurality of gate trenches 16 via the insulating layer 18 and spaced apart from the gate electrode 28. The gate electrode 28 may be configured to receive a gate voltage, and the field plate electrode 30 may be configured to receive a reference voltage (or source voltage). In one example, the gate electrode 28 and the field plate electrode 30 may be formed from conductive polysilicon.

[0024] The gate electrode 28 may include an upper surface 28A covered by the insulating layer 18 and a bottom surface 28B opposite the upper surface 28A. The field plate electrode 30 is disposed below the gate electrode 28 within the gate trench 16. More specifically, the field plate electrode 30 may be disposed between the bottom surface 28B of the gate electrode 28 and the bottom wall 16B of the gate trench 16. At least a portion of the bottom surface 28B of the gate electrode 28 faces the field plate electrode 30 with the insulating layer 18 interposed therebetween. The gate electrode 28 further includes a side surface 28C facing the sidewall 16A of the gate trench 16.

[0025] An upper surface 28A of the gate electrode 28 may be located lower than an upper surface 14A of the semiconductor layer 14. A bottom surface 28B of the gate electrode 28 may be located near the interface between the drift region 20 and the body region 22 in the Z-axis direction, and may preferably be located lower than the interface. The upper surface 28A and the bottom surface 28B of the gate electrode 28 may be flat or curved.

[0026] The gate electrode 28 and the field plate electrode 30 are surrounded by an insulating layer 18. The field plate electrode 30 may have a width smaller than that of the gate electrode 28. Because the field plate electrode 30 has a relatively small width, the thickness of the insulating layer 18 surrounding the field plate electrode 30 is relatively large.

[0027] The semiconductor device 10 may further include a source contact plug 32 that penetrates the insulating layer 18. The source contact plug 32 may extend parallel to the gate trenches 16 in a plan view and may be disposed between two gate trenches 16 (see FIG. 1 ). The semiconductor device 10 further includes a source wiring 34 formed on the insulating layer 18. The source wiring 34 may be configured to receive a reference voltage (or a source voltage). The source wiring 34 is connected to the source contact plug 32.

[0028] The semiconductor layer 14 may further include a contact region 36. The contact region 36 may be a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 36 is higher than that of the body region 22, and is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The source contact plug 32 extends through the insulating layer 18 and the source region 24 to contact the contact region 36. The contact region 36 is electrically connected to the source wiring 34 via the source contact plug 32.

[0029] The insulating layer 18 includes a gate insulating portion 38 interposed between the gate electrode 28 and the semiconductor layer 14 and covering the sidewall 16A of the gate trench 16. The gate insulating portion 38 is a portion of the insulating layer 18 located between the side surface 28C of the gate electrode 28 and the sidewall 16A of the gate trench 16. The gate electrode 28 faces the semiconductor layer 14 via the gate insulating portion 38. When a predetermined voltage is applied to the gate electrode 28, a channel is formed in the p-type body region 22 adjacent to the gate insulating portion 38. The semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 24 and the n-type drift region 20 via this channel. Furthermore, since the source wiring 34 is electrically connected to the field plate electrode 30, electric field concentration in the gate trench 16 can be alleviated, thereby improving the breakdown voltage of the semiconductor device 10.

[0030] (Planar Layout of Semiconductor Device) Next, referring again to FIG. 1 , the planar layout of the semiconductor device 10 will be described. The semiconductor layer 14 includes a peripheral region 40 and an inner region 42 having a rectangular outer edge surrounded by the peripheral region 40 in a planar view. The boundary between the peripheral region 40 and the inner region 42 is indicated by a two-dot chain line in FIG. 1 . The outer edge of the peripheral region 40 may coincide with the outer edge of the semiconductor layer 14 in a planar view, or may be located inside the outer edge of the semiconductor layer 14. In one example, the peripheral region 40 may be located between the outer edge of the semiconductor layer 14 and the inner region 42. The rectangular outer edge of the inner region 42 has two sides extending in the Y-axis direction and two sides extending in the X-axis direction in a planar view. Note that in this specification, the Y-axis direction may be referred to as the first direction, and the X-axis direction may be referred to as the second direction. The second direction is a direction perpendicular to the first direction in a planar view.

[0031] The semiconductor device 10 further includes a gate wiring 44 formed on the insulating layer 18 and electrically connected to the plurality of gate electrodes 28 (see FIG. 2). The source wiring 34 is formed on the insulating layer 18 and is spaced apart from the gate wiring 44. The source wiring 34 may be spaced apart from the gate wiring 44 by a predetermined distance (determined, for example, in consideration of the breakdown voltage, etc.). As described above, the source wiring 34 is electrically connected to the plurality of field plate electrodes 30 (see FIG. 2).

[0032] The gate wiring 44 includes a plurality of peripheral gate fingers 46 arranged in the peripheral region 40. The plurality of peripheral gate fingers 46 are separated from one another by a plurality of gaps 48 arranged along the outer edge of the inner region 42. In the example of FIG. 1 , the plurality of peripheral gate fingers 46 may include four peripheral gate fingers 46A, 46B, 46C, and 46D. More specifically, the plurality of peripheral gate fingers 46 may include a first peripheral gate finger 46A and a second peripheral gate finger 46B extending in the Y-axis direction, and a third peripheral gate finger 46C and a fourth peripheral gate finger 46D extending in the X-axis direction.

[0033] The gate wiring 44 further includes a plurality of inner gate fingers 50 arranged in the inner region 42. Each of the plurality of inner gate fingers 50 is connected to at least one of the plurality of peripheral gate fingers 46. The plurality of inner gate fingers 50 may include a first inner gate finger 50A extending in the Y-axis direction and a second inner gate finger 50B extending in the X-axis direction.

[0034] The inner region 42 includes a plurality of subregions 52 separated by at least two of the plurality of inner gate fingers 50 that intersect with each other. Each of the plurality of subregions 52 is adjacent to at least one of the plurality of peripheral gate fingers 46. In the example of FIG. 1 , a first inner gate finger 50A and a second inner gate finger 50B intersect with each other. The plurality of subregions 52 includes four subregions 52A, 52B, 52C, and 52D. The four subregions 52A, 52B, 52C, and 52D are separated by the first inner gate finger 50A and the second inner gate finger 50B that intersect with each other. Each of the four subregions 52A, 52B, 52C, and 52D is adjacent to the first inner gate finger 50A and the second inner gate finger 50B in a plan view. In the example of FIG. 1, the four gaps 48A, 48B, 48C, and 48D are adjacent to the four sub-regions 52A, 52B, 52C, and 52D, respectively.

[0035] The first inner gate finger 50A is connected to the third perimeter gate finger 46C and the fourth perimeter gate finger 46D. The second inner gate finger 50B is connected to the first perimeter gate finger 46A and the second perimeter gate finger 46B.

[0036] The gate wiring 44 may further include a gate pad 54. In the example of Fig. 1, the gate pad 54 is connected to the first inner gate finger 50A and the fourth outer peripheral gate finger 46D.

[0037] In plan view, sub-region 52A is surrounded by first inner gate finger 50A, second inner gate finger 50B, and first outer perimeter gate finger 46A. Gap 48A adjacent to sub-region 52A is formed between first outer perimeter gate finger 46A and third outer perimeter gate finger 46C.

[0038] In plan view, subregion 52B is surrounded by first inner gate finger 50A, second inner gate finger 50B, and third outer perimeter gate finger 46C. Gap 48B adjacent to subregion 52B is formed between third outer perimeter gate finger 46C and second outer perimeter gate finger 46B.

[0039] In plan view, subregion 52C is surrounded by first inner gate finger 50A, second inner gate finger 50B, and fourth outer perimeter gate finger 46D. Gap 48C adjacent to subregion 52C is formed between fourth outer perimeter gate finger 46D and first outer perimeter gate finger 46A.

[0040] In plan view, subregion 52D is surrounded by first inner gate finger 50A, second inner gate finger 50B, second outer periphery gate finger 46B, fourth outer periphery gate finger 46D, and gate pad 54. Gap 48D adjacent to subregion 52D is formed between second outer periphery gate finger 46B and fourth outer periphery gate finger 46D.

[0041] In this manner, the outer edge of each subregion 52 is surrounded by the gate wiring 44, except for the portion adjacent to the gap 48. Each subregion 52 is rectangular in plan view and has four sides. At least two of the gaps 48 may be formed over a length at least equal to that of one side of the subregion 52 to which the gap 48 is adjacent. In the example of FIG. 1 , three of the gaps 48 are formed over a length equal to that of one side of the subregion 52 (52A, 52B, 52C) to which the gap 48 is adjacent. In other words, each of the subregions 52A, 52B, 52C is surrounded on three sides by the gate wiring 44.

[0042] The source wiring 34 includes a plurality of inner segments 56 arranged in the plurality of sub-regions 52, respectively, and an outer periphery segment 58 arranged in the outer periphery region 40. The outer periphery segment 58 is continuous with at least two of the plurality of inner segments 56. Each of the at least two inner segments 56 is connected to the outer periphery segment 58 via one of the plurality of gaps 48 that is adjacent to the sub-region 52 in which the inner segment 56 is arranged.

[0043] In the example of FIG. 1 , the multiple inner segments 56 include four inner segments 56A, 56B, 56C, and 56D arranged in four sub-regions 52A, 52B, 52C, and 52D, respectively. The outer periphery segment 58 is continuous with the four inner segments 56A, 56B, 56C, and 56D. Each of the four inner segments 56A, 56B, 56C, and 56D is connected to the outer periphery segment 58 through one of the four gaps 48A, 48B, 48C, and 48D that is adjacent to the sub-region 52 in which the inner segment 56 is arranged. That is, the inner segment 56A is connected to the outer periphery segment 58 through the gap 48A that is adjacent to the sub-region 52A in which the inner segment 56A is arranged. The inner segment 56B is connected to the outer periphery segment 58 through the gap 48B that is adjacent to the sub-region 52B in which the inner segment 56B is arranged. Inner segment 56C is connected to outer periphery segment 58 through gap 48C adjacent to sub-region 52C in which inner segment 56C is located. Inner segment 56D is connected to outer periphery segment 58 through gap 48D adjacent to sub-region 52D in which inner segment 56D is located.

[0044] In this manner, the outer periphery segment 58 may be continuous with (all of) the multiple inner segments 56. In this case, each of the multiple inner segments 56 may be connected to the outer periphery segment 58 through one of the multiple gaps 48 that is adjacent to the subregion 52 in which the inner segment 56 is located.

[0045] The peripheral segment 58 may extend along the outer edge of the semiconductor layer 14 in a plan view, except for the region where the gate pad 54 is located. (Gate Trench Arrangement) Each of the multiple gate trenches 16 may be arranged to intersect with one of one or more inner gate fingers 50 of the multiple peripheral gate fingers 46 in a plan view. The semiconductor device 10 may further include multiple gate contact plugs 60. The gate electrode 28 (see FIG. 2 ) embedded in each gate trench 16 may be connected to one of one or more inner gate fingers 50 of the multiple peripheral gate fingers 46 via at least one of the multiple gate contact plugs 60. The gate contact plug 60 may be arranged in a region where each of the multiple gate trenches 16 intersects with one or more inner gate fingers 50 of the multiple peripheral gate fingers 46 in a plan view.

[0046] The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each of the gate trenches 16 in the first set S1 extends in the Y-axis direction in a plan view. Each of the gate trenches 16 in the second set S2 extends in the X-axis direction in a plan view. Each of the gate trenches 16 in the first set S1 and the second set S2 intersects with one of the plurality of peripheral gate fingers 46 in a plan view. The gate trenches 16 in the first set S1 and the second set S2 are arranged across the inner region 42 and the peripheral region 40.

[0047] The plurality of gate trenches 16 may include a third set S3 of gate trenches 16 and a fourth set S4 of gate trenches 16. Each of the gate trenches 16 in the third set S3 extends in the Y-axis direction in a plan view. Each of the gate trenches 16 in the fourth set S4 extends in the X-axis direction in a plan view. Each of the gate trenches 16 in the third set S3 and the fourth set S4 intersects with one of the plurality of inner gate fingers 50 in a plan view. The gate trenches 16 in the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

[0048] 1 , the main portions of each gate trench 16 in the first set S1, excluding the ends, are arranged in sub-region 52B or sub-region 52C. The main portions of each gate trench 16 in the second set S2, excluding the ends, are arranged in sub-region 52A or sub-region 52D. The main portions of each gate trench 16 in the third set S3, excluding the ends, are arranged in sub-region 52B or sub-region 52C. The main portions of each gate trench 16 in the fourth set S4, excluding the ends, are arranged in sub-region 52A or sub-region 52D.

[0049] Optionally, the plurality of gate trenches 16 may include a fifth set S5 of gate trenches 16 (although only one gate trench 16 is shown in FIG. 1 , the fifth set may include a plurality of gate trenches 16). Each gate trench 16 in the fifth set S5 extends in the Y-axis direction in plan view and intersects with the fourth outer periphery gate finger 46D in plan view. A major portion, excluding the ends, of each gate trench 16 in the fifth set S5 is disposed next to the gate pad 54 in the subregion 52D.

[0050] Each of the sets S1, S2, S3, S4, and S5 may include one or more gate trenches 16. Some of the gate trenches 16 included in each of the sets S1, S2, S3, S4, and S5 may be aligned parallel to one another at equal intervals. The number of gate trenches included in each of the sets S1, S2, S3, S4, and S5 can be determined appropriately depending on the layout.

[0051] The semiconductor device 10 may further include a field plate trench 62. An electrode having the same potential as the field plate electrode 30 (see FIG. 2) may be disposed within the field plate trench 62. The field plate trench 62 may be configured to connect aligned gate trenches 16 whose main portions are disposed in the same subregion 52. The field plate trench 62 may include a portion 62A that connects the gate trenches 16 and two portions 62B that extend parallel to the gate trenches 16. The portion 62A may extend perpendicular to the gate trenches 16. The two portions 62B may be provided on both sides of the connected gate trench 16. The electrode disposed within the field plate trench 62 may be integrally connected to the field plate electrode 30 (see FIG. 2) that is disposed in the gate trench 16 that communicates with the field plate trench 62.

[0052] Fig. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in Fig. 1. Fig. 3 shows a cross section in the YZ plane of two gate trenches 16 (one of the first set S1 and one of the third set S3) located below inner segment 56C.

[0053] A gate electrode 28 and a field plate electrode 30 are disposed in each gate trench 16. The gate electrode 28 is disposed above the field plate electrode 30 and is connected to the gate wiring 44 via a gate contact plug 60.

[0054] The semiconductor device 10 may further include a plurality of field plate contact plugs 64. The field plate electrode 30 embedded in each of the gate trenches 16 of the first set S1 may include a first end 66 connected to the outer periphery segment 58 via at least one of the plurality of field plate contact plugs 64 and a second end 68 connected to one of the plurality of inner segments 56 (inner segment 56C in the example of FIG. 3 ) via at least one of the plurality of field plate contact plugs 64. The field plate electrode 30 embedded in each of the gate trenches 16 of the third set S3 may include a first end 70 connected to one of the plurality of inner segments 56 (inner segment 56C in the example of FIG. 3 ) via at least one of the plurality of field plate contact plugs 64 and a second end 72 connected to another of the plurality of inner segments 56 (inner segment 56A in the example of FIG. 3 ) via at least one of the plurality of field plate contact plugs 64.

[0055] The gate electrode 28 does not exist above the ends 66, 68, 70, and 72. The ends 66, 68, 70, and 72 extend in the Z-axis direction from the bottom of the gate trench 16 to near the opening, and therefore can be connected to the source wiring 34 located above them via the field plate contact plug 64.

[0056] (Operation of Semiconductor Device) The operation of the semiconductor device 10 of this embodiment will be described below. The gate wiring 44 includes a plurality of peripheral gate fingers 46 arranged in the peripheral region 40. The plurality of peripheral gate fingers 46 are separated from one another by a plurality of gaps 48 arranged along the outer edge of the inner region 42. If each of the plurality of peripheral gate fingers 46 were extended to eliminate the gaps 48 and connected to one another, the extended portions would cause an excess gate-drain capacitance C ｇｄ Gate-drain capacitance C ｇｄ is the feedback capacitance C of the semiconductor device 10 ｒｓｓ This corresponds to the feedback capacitance C ｒｓｓA large capacitance C can reduce the switching speed of the semiconductor device 10. Therefore, by arranging a plurality of gaps 48 along the outer edge of the inner region 42, the excess gate-drain capacitance C ｇｄ can be suppressed.

[0057] In this embodiment, each of the multiple gate trenches 16 is arranged so as to intersect with one of the multiple outer gate fingers 46 and one of the multiple inner gate fingers 50 in plan view. Therefore, even if the gate finger does not extend into the region where the gap 48 is located, the gate electrode 28 embedded in each gate trench 16 can be connected to the gate wiring 44.

[0058] The source wiring 34 also includes a plurality of inner segments 56 arranged in the plurality of sub-regions 52, respectively, and an outer periphery segment 58 arranged in the outer periphery region 40. The outer periphery segment 58 is continuous with at least two of the plurality of inner segments 56, and each of the at least two inner segments 56 is connected to the outer periphery segment 58 via one of the plurality of gaps 48 that is adjacent to the sub-region 52 in which the inner segment 56 is arranged. Therefore, the resistance generated by the source wiring 34 can be reduced.

[0059] Furthermore, the gate wiring 44 includes a plurality of inner gate fingers 50 arranged in the inner region 42. Each of the inner gate fingers 50 is connected to at least one of the outer gate fingers 46. Therefore, the area in which the gate trench 16 can be arranged is expanded, and the on-resistance R of the semiconductor device 10 is reduced. ｏｎ can be reduced.

[0060] (Semiconductor Device of Comparative Example) The reduction of resistance and parasitic capacitance by the semiconductor device 10 will be described in more detail below with reference to FIG. 4. FIG. 4 is a schematic plan view of an exemplary semiconductor device 100 according to a comparative example. In FIG. 4, components similar to those in the semiconductor device 10 shown in FIG. 1 are denoted by the same reference numerals. Further, detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0061] The semiconductor device 100 includes a gate wiring 102 and a source wiring 104 that are different from the gate wiring 44 and source wiring 34 of the semiconductor device 10 of this embodiment. The gate wiring 102 is formed on an insulating layer 18 and is electrically connected to a plurality of gate electrodes 28 (see FIG. 2). The source wiring 104 is formed on the insulating layer 18 and is spaced apart from the gate wiring 102. The source wiring 104 is electrically connected to a plurality of field plate electrodes 30 (see FIG. 2).

[0062] The gate wiring 102 includes a peripheral gate finger 106 disposed in the peripheral region 40 and a gate pad 108 connected to the peripheral gate finger 106. The peripheral gate finger 106 extends along the outer edge of the inner region 42 but does not completely surround the inner region 42 in a plan view. The peripheral gate finger 106 is interrupted by a gap 110 disposed in the peripheral region 40. The peripheral gate finger 106 includes a first portion 106A and a second portion 106B extending in the Y-axis direction, and a third portion 106C and a fourth portion 106D extending in the X-axis direction. The first portion 106A is connected between the third portion 106C and the fourth portion 106D. The second portion 106B is connected to the fourth portion 106D. The second portion 106B is not connected to the third portion 106C. A gap 110 is formed between the second portion 106B and the third portion 106C.

[0063] The gate wiring 102 further includes a first inner gate finger 112A and a second inner gate finger 112B arranged in the inner region 42. The first inner gate finger 112A extends in the Y-axis direction, and the second inner gate finger 112B extends in the X-axis direction. The first inner gate finger 112A and the second inner gate finger 112B cross each other. The first inner gate finger 112A is connected to the outer periphery gate finger 106 and the gate pad 108. Meanwhile, the second inner gate finger 112B is not connected to the outer periphery gate finger 106, but is connected only to the first inner gate finger 112A. One end of the first inner gate finger 112A and both ends of the second inner gate finger 112B are spaced apart from the outer periphery gate finger 106. More specifically, one end of the first inner gate finger 112A is separated from the third portion 106C of the peripheral gate finger 106 by a gap 114. Furthermore, one end of the second inner gate finger 112B is separated from the first portion 106A of the peripheral gate finger 106 by a gap 116. The other end of the second inner gate finger 112B is separated from the second portion 106B of the peripheral gate finger 106 by a gap 118. Thus, in the semiconductor device 10 of the comparative example, three gaps 114, 116, and 118 exist in the inner region 42.

[0064] The inner region 42 includes four subregions 120A, 120B, 120C, and 120D separated by a first inner gate finger 112A and a second inner gate finger 112B that intersect with each other. Each of the four subregions 120A, 120B, 120C, and 120D is adjacent to the first inner gate finger 112A and the second inner gate finger 112B in a plan view. The gap 110 arranged in the outer periphery region 40 is adjacent only to the subregion 120A. No gaps are present in the outer periphery region 40 that are adjacent to other subregions 120B, 120C, or 120D.

[0065] The source wiring 104 includes four inner segments 122A, 122B, 122C, and 122D arranged in the four sub-regions 120A, 120B, 120C, and 120D, respectively, and an outer periphery segment 124 arranged in the outer periphery region 40. The outer periphery segment 124 is continuous only with the inner segment 122A. The inner segment 122A is connected to the outer periphery segment 124 through a gap 110 adjacent to the sub-region 120A in which the inner segment 122A is arranged. The other inner segments 122B, 122C, and 122D are not directly connected to the outer periphery segment 124, and the inner segment 122B is connected to the inner segment 122A through a gap 114 arranged in the inner region 42. The inner segment 122C is connected to the inner segment 122A through a gap 118 arranged in the inner region 42. The inner segment 122D is connected to the inner segment 122B through a gap 116 arranged in the inner region 42.

[0066] The peripheral segment 124 extends along the outer edge of the semiconductor layer 14 in a plan view, excluding the region where the gate pad 108 is disposed. The peripheral segment 124 is directly connected only to the inner segment 122A, and therefore there is a relatively long distance between the portion of the peripheral segment 124 that is located near the gate pad 108, for example, and the inner segment 122A.

[0067] Each of the multiple gate trenches 16 can be arranged so as to intersect with the outer periphery gate finger 106, the first inner gate finger 112A, or the second inner gate finger 112B in plan view.

[0068] The multiple gate trenches 16 include gate trenches 16 of a first set S1 and gate trenches 16 of a second set S2. Each gate trench 16 of the first set S1 extends in the Y-axis direction in a plan view. Each gate trench 16 of the second set S2 extends in the X-axis direction in a plan view. Each gate trench 16 of the first set S1 and the second set S2 intersects with the peripheral gate fingers 106 in a plan view. The gate trenches 16 of the first set S1 and the second set S2 are arranged across the inner region 42 and the peripheral region 40.

[0069] The plurality of gate trenches 16 includes gate trenches 16 of a third set S3 and gate trenches 16 of a fourth set S4. Each gate trench 16 of the third set S3 extends in the Y-axis direction in a plan view. Each gate trench 16 of the fourth set S4 extends in the X-axis direction in a plan view. Each gate trench 16 of the third set S3 intersects with the second inner gate finger 112B in a plan view. Each gate trench 16 of the fourth set S4 intersects with the first inner gate finger 112A in a plan view. The gate trenches 16 of the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

[0070] The plurality of gate trenches 16 includes a fifth set S5 of gate trenches 16 (although only one gate trench 16 is shown in FIG. 4 , the plurality of gate trenches 16 may include multiple gate trenches 16). Each gate trench 16 of the fifth set S5 extends in the Y-axis direction in plan view and intersects with the peripheral gate fingers 106 in plan view. A major portion, excluding the ends, of each gate trench 16 of the fifth set S5 is disposed next to the gate pad 108 in the subregion 120D.

[0071] As described above, in the semiconductor device 100 of the comparative example, the peripheral gate finger 106 also extends to a region that does not intersect with the gate trench 16. Specifically, the first portion 106A of the peripheral gate finger 106 adjacent to the sub-region 120B does not intersect with the gate trench 16. Furthermore, the second portion 106B of the peripheral gate finger 106 adjacent to the sub-region 120C does not intersect with the gate trench 16. Due to the presence of the gate wiring 102 in a region that does not intersect with the gate trench 16, the semiconductor device 100 generates an extra gate-drain capacitance C ｇｄ may occur.

[0072] In this regard, in the semiconductor device 10 of this embodiment, the multiple peripheral gate fingers 46 are separated from one another by multiple gaps 48 arranged along the outer edge of the inner region 42. By arranging the multiple gaps 48 along the outer edge of the inner region 42, the excess gate-drain capacitance C ｇｄ can be suppressed.

[0073] FIG. 5 shows the feedback capacitance C ｒｓｓ 4. The vertical axis represents the feedback capacitance, and the horizontal axis represents the drain-source voltage. The vertical and horizontal axes are logarithmic. The example corresponds to the semiconductor device 10 of the first embodiment, and the comparative example corresponds to the semiconductor device 100 shown in FIG. 4. The drain-source voltage V ｄｓ When is relatively large, the feedback capacitance C ｒｓｓ (=C ｇｄ ) is reduced by about 20% compared to the comparative example.

[0074] Furthermore, in the semiconductor device 100 of the comparative example, the peripheral segment 124 of the source wiring 104 is directly connected only to the inner segment 122A. For example, there is a relatively long distance from the portion of the peripheral segment 124 located near the gate pad 108 to the inner segment 122A. In particular, the distance from the field plate contact plug 64, which is disposed in the region where the gate trench 16 included in the fifth set S5 shown in FIG. 4 intersects with the peripheral segment 124, to the inner segment 122A is relatively long, at approximately 40% of the perimeter of the outer edge of the inner region 42. Therefore, in the semiconductor device 100, the layout of the source wiring 104 can cause an increase in resistance.

[0075] In this regard, in the semiconductor device 10 of this embodiment, the outer periphery segment 58 is continuous with at least two of the multiple inner segments 56, and each of the at least two inner segments 56 is connected to the outer periphery segment 58 through one of the multiple gaps 48 that is adjacent to the subregion 52 in which the inner segment 56 is located. Therefore, the resistance generated by the source wiring 34 can be reduced.

[0076] Furthermore, in the semiconductor device 100 of the comparative example, one end of the first inner gate finger 112A and both ends of the second inner gate finger 112B are spaced apart from the peripheral gate finger 106. The lengths of the first inner gate finger 112A and the second inner gate finger 112B are reduced by the three gaps 114, 116, and 118 arranged in the inner region 42. This reduces the number of gate trenches 16 that can be arranged to intersect with the first inner gate finger 112A or the second inner gate finger 112B. In the semiconductor device 100, the four inner segments 122A, 122B, 122C, and 122D are connected via the three gaps 114, 116, and 118 arranged in the inner region 42, thereby reducing the area of ​​the active region in which gate trenches 16 can be arranged. This reduces the on-resistance R of the semiconductor device 100. ｏｎ can increase.

[0077] In this regard, in the semiconductor device 10 of this embodiment, each of the inner gate fingers 50 is connected to at least one of the outer gate fingers 46. Therefore, the area in which the gate trenches 16 can be arranged is expanded, and the on-resistance R ｏｎ can be reduced.

[0078] As described above, the semiconductor device 10 of this embodiment can reduce the resistance and parasitic capacitance caused by the wiring layout, thereby improving the switching characteristics. The semiconductor device 10 of this embodiment has the following advantages.

[0079] (1-1) The multiple peripheral gate fingers 46 are spaced apart from one another by multiple gaps 48 arranged along the outer edge of the inner region 42. Each of the multiple inner gate fingers 50 is connected to at least one of the multiple peripheral gate fingers 46. The peripheral segment 58 is continuous with at least two of the multiple inner segments 56, and each of the at least two inner segments 56 is connected to the peripheral segment 58 via a gap 48 of the multiple gaps 48 that is adjacent to the sub-region 52 in which the inner segment 56 is arranged.

[0080] This reduces the resistance and parasitic capacitance caused by the wiring layout, improving the switching characteristics of the semiconductor device 10. (1-2) At least two of the gaps 48 may be formed over a length at least equal to the length of one side of the subregion 52 to which the gap 48 is adjacent. By making the length of the gap 48 relatively large, the resistance and parasitic capacitance caused by the wiring layout can be further reduced.

[0081] (1-3) Each of the multiple sub-regions 52 may be adjacent to at least one of the multiple peripheral gate fingers 46. This makes it possible to arrange gate trenches 16 in each sub-region 52 that intersect with the peripheral gate fingers 46 in plan view.

[0082] (1-4) The outer periphery segment 58 is continuous with the inner segments 56, and each of the inner segments 56 may be connected to the outer periphery segment 58 via one of the gaps 48 that is adjacent to the subregion 52 in which the inner segment 56 is located. By connecting all of the inner segments 56 located in the subregions 52 to the outer periphery segment 58, the resistance and parasitic capacitance resulting from the wiring layout can be further reduced.

[0083] (1-5) Each of the multiple gate trenches 16 may be arranged so as to intersect with one of the multiple outer gate fingers 46 and one of the multiple inner gate fingers 50 in plan view. This makes it possible to connect the gate electrode 28 in each gate trench 16 to the gate wiring 44.

[0084] (1-6) The multiple gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 in the first set S1 extends in the Y-axis direction (first direction) in a plan view, and each gate trench 16 in the second set S2 extends in the X-axis direction (second direction) in a plan view. Each gate trench 16 in the first set S1 and the second set S2 may intersect with one of the multiple peripheral gate fingers 46 in a plan view. This can reduce warping of the semiconductor substrate 12 during wafer processing compared to a case where only gate trenches 16 extending in the same direction are arranged to intersect with the peripheral gate fingers 46.

[0085] (1-7) The plurality of gate trenches 16 may further include a third set S3 of gate trenches 16 and a fourth set S4 of gate trenches 16. Each of the gate trenches 16 in the third set S3 extends in the Y-axis direction (first direction) in a plan view, and each of the gate trenches 16 in the fourth set S4 extends in the X-axis direction (second direction) in a plan view. Each of the gate trenches 16 in the third set S3 and the fourth set S4 may intersect with one of the plurality of inner gate fingers 50 in a plan view. This can reduce warping of the semiconductor substrate 12 during wafer processing compared to a case where only gate trenches 16 extending in the same direction are arranged to intersect with the inner gate fingers 50.

[0086] (1-8) The field plate electrode 30 embedded in each gate trench 16 of the first set S1 may include a first end 66 connected to the outer periphery segment 58 via at least one of the plurality of field plate contact plugs 64 and a second end 68 connected to one of the plurality of inner segments 56 via at least one of the plurality of field plate contact plugs 64. The field plate electrode 30 embedded in each gate trench 16 of the third set S3 may include a first end 70 connected to one of the plurality of inner segments 56 via at least one of the plurality of field plate contact plugs 64 and a second end 72 connected to another one of the plurality of inner segments 56 via at least one of the plurality of field plate contact plugs 64.

[0087] Since two ends of the field plate electrode 30 are connected to the source wiring 34, the resistance due to the length of the field plate electrode 30 can be reduced compared to when only one end is connected.

[0088] Second Embodiment Fig. 6 is a schematic cross-sectional view of an exemplary semiconductor device 200 according to a second embodiment. In Fig. 6, the same components as those in the semiconductor device 10 shown in Figs. 1 to 3 are denoted by the same reference numerals. Detailed description of the same components as those in the semiconductor device 10 will be omitted.

[0089] The semiconductor device 200 may be, for example, a MISFET having a trench gate structure as shown in Fig. 2. The semiconductor device 200 includes a gate wiring 202 and a source wiring 204 that are different from the gate wiring 44 and the source wiring 34 of the semiconductor device 10 of the first embodiment.

[0090] The gate wiring 202 is formed on the insulating layer 18 and is electrically connected to a plurality of gate electrodes 28 (see FIG. 2). The source wiring 204 is formed on the insulating layer 18 and is spaced apart from the gate wiring 202. The source wiring 204 is electrically connected to a plurality of field plate electrodes 30 (see FIG. 2).

[0091] The gate wiring 202 includes a plurality of perimeter gate fingers 206 arranged in the perimeter region 40. The plurality of perimeter gate fingers 206 are separated from one another by a plurality of gaps 208 arranged along the outer edge of the inner region 42. In the example of FIG. 6 , the plurality of perimeter gate fingers 206 may include six perimeter gate fingers 206A, 206B, 206C, 206D, 206E, and 206F. More specifically, the plurality of perimeter gate fingers 206 may include a first perimeter gate finger 206A, a second perimeter gate finger 206B, and a third perimeter gate finger 206C extending in the Y-axis direction, and a fourth perimeter gate finger 206D and a fifth perimeter gate finger 206E extending in the X-axis direction. The plurality of perimeter gate fingers 206 may further include a sixth perimeter gate finger 206F that is continuous with a second inner gate finger 210B, which will be described later.

[0092] The gate wiring 202 further includes a plurality of inner gate fingers 210 arranged in the inner region 42. Each of the plurality of inner gate fingers 210 is connected to at least one of the plurality of peripheral gate fingers 206. The plurality of inner gate fingers 210 may include a first inner gate finger 210A extending in the Y-axis direction, and a second inner gate finger 210B and a third inner gate finger 210C extending in the X-axis direction.

[0093] The inner region 42 includes a plurality of subregions 212 separated by at least two of the plurality of inner gate fingers 210 that intersect with one another. In the example of FIG. 6 , the first inner gate finger 210A intersects with the second inner gate finger 210B and the third inner gate finger 210C. The plurality of subregions 212 includes six subregions 212A, 212B, 212C, 212D, 212E, and 212F. Each of the six subregions 212A, 212B, 212C, 212D, 212E, and 212F is adjacent to the first inner gate finger 210A and adjacent to either the second inner gate finger 210B or the third inner gate finger 210C in a plan view. In the example of FIG. 6, six gaps 208 are adjacent to six sub-regions 212A, 212B, 212C, 212D, 212E, and 212F, respectively.

[0094] The first inner gate finger 210A is connected to the fourth perimeter gate finger 206D and the fifth perimeter gate finger 206E. The second inner gate finger 210B is connected to the first perimeter gate finger 206A and the sixth perimeter gate finger 206F. The third inner gate finger 210C is connected to the second perimeter gate finger 206B and the third perimeter gate finger 206C.

[0095] The gate wiring 202 may further include a gate pad 214. In the example of Figure 6, the gate pad 214 is connected to the first inner gate finger 210A and the fifth outer periphery gate finger 206E.

[0096] In plan view, subregion 212A is surrounded by first inner gate finger 210A, second inner gate finger 210B, and first outer perimeter gate finger 206A. Gap 208A adjacent to subregion 212A is formed between first outer perimeter gate finger 206A and fourth outer perimeter gate finger 206D.

[0097] Subregion 212B is surrounded by first inner gate finger 210A, second inner gate finger 210B, and fourth perimeter gate finger 206D in plan view. Gap 208B adjacent to subregion 212B is formed between fourth perimeter gate finger 206D and sixth perimeter gate finger 206F.

[0098] In a plan view, subregion 212C is surrounded by first inner gate finger 210A, second inner gate finger 210B, and third inner gate finger 210C. Gap 208C adjacent to subregion 212C is formed between first outer perimeter gate finger 206A and third outer perimeter gate finger 206C.

[0099] Subregion 212D is surrounded in plan view by first inner gate finger 210A, second inner gate finger 210B, third inner gate finger 210C, and second outer periphery gate finger 206B. Gap 208D adjacent to subregion 212D is formed between second inner gate finger 210B and second outer periphery gate finger 206B.

[0100] In plan view, subregion 212E is surrounded by first inner gate finger 210A, third inner gate finger 210C, third outer perimeter gate finger 206C, fifth outer perimeter gate finger 206E, and gate pad 214. Gap 208E adjacent to subregion 212E is formed between third outer perimeter gate finger 206C and fifth outer perimeter gate finger 206E.

[0101] Subregion 212F is surrounded by first inner gate finger 210A, third inner gate finger 210C, and fifth outer perimeter gate finger 206E in plan view. Gap 208F adjacent to subregion 212F is formed between second outer perimeter gate finger 206B and fifth outer perimeter gate finger 206E.

[0102] One of the six sub-regions 212 (212C) is not adjacent to any of the perimeter gate fingers 206, but is adjacent to the first inner gate finger 210A, the second inner gate finger 210B, and the third inner gate finger 210C. The other five of the six sub-regions 212 (212A, 212B, 212D, 212E, 212F) are adjacent to at least one of the perimeter gate fingers 206.

[0103] In this manner, the outer edge of each subregion 212 is surrounded by the gate wiring 202, except for the portion adjacent to the gap 208. Each subregion 212 is rectangular in plan view and has four sides. At least two of the gaps 208 may be formed over a length at least equal to that of one side of the subregion 212 to which the gap 208 is adjacent. In the example of FIG. 6 , four of the gaps 208 are formed over a length equal to that of one side of the subregion 212 (212A, 212B, 212C, 212F) to which the gap 208 is adjacent. In other words, each of the subregions 212A, 212B, 212C, 212F is surrounded by the gate wiring 202 on three sides.

[0104] The source wiring 204 includes a plurality of inner segments 216 arranged in the plurality of sub-regions 212, respectively, and a peripheral segment 218 arranged in the peripheral region 40. The peripheral segment 218 is continuous with at least two of the plurality of inner segments 216. Each of the at least two inner segments 216 is connected to the peripheral segment 58 via one of the plurality of gaps 208 that is adjacent to the sub-region 212 in which the inner segment 216 is arranged.

[0105] 6 , the multiple inner segments 216 include six inner segments 216A, 216B, 216C, 216D, 216E, and 216F arranged in six sub-regions 212A, 212B, 212C, 212D, 212E, and 212F, respectively. The outer periphery segment 218 is continuous with the six inner segments 216A, 216B, 216C, 216D, 216E, and 216F. Each of the six inner segments 216A, 216B, 216C, 216D, 216E, and 216F is connected to the outer periphery segment 218 through one of the six gaps 208A, 208B, 208C, 208D, 208E, and 208F that is adjacent to the sub-region 212 in which the inner segment 216 is arranged. That is, inner segment 216A is connected to outer periphery segment 218 through gap 208A adjacent to sub-region 212A in which inner segment 216A is located. Inner segment 216B is connected to outer periphery segment 218 through gap 208B adjacent to sub-region 212B in which inner segment 216B is located. Inner segment 216C is connected to outer periphery segment 218 through gap 208C adjacent to sub-region 212C in which inner segment 216C is located. Inner segment 216D is connected to outer periphery segment 218 through gap 208D adjacent to sub-region 212D in which inner segment 216D is located. Inner segment 216E is connected to outer periphery segment 218 through gap 208E adjacent to sub-region 212E in which inner segment 216E is located. Inner segment 216F is connected to outer periphery segment 218 through gap 208F adjacent to sub-region 212F in which inner segment 216F is located.

[0106] In this manner, the outer periphery segment 218 may be continuous with (all of) the multiple inner segments 216. In this case, each of the multiple inner segments 216 may be connected to the outer periphery segment 218 through one of the multiple gaps 208 that is adjacent to the subregion 212 in which the inner segment 216 is located.

[0107] The peripheral segment 218 may extend along the outer edge of the semiconductor layer 14 in a plan view, except for the region where the gate pad 214 is located. (Gate Trench Arrangement) Each of the multiple gate trenches 16 may be arranged to intersect with one of one or more inner gate fingers 210 of the multiple peripheral gate fingers 206 in a plan view. The semiconductor device 200 may further include multiple gate contact plugs 60. The gate electrode 28 (see FIG. 2 ) embedded in each gate trench 16 may be connected to one of one or more inner gate fingers 210 of the multiple peripheral gate fingers 206 via at least one of the multiple gate contact plugs 60. The gate contact plug 60 may be arranged in a region where each of the multiple gate trenches 16 intersects with one of one or more inner gate fingers 210 of the multiple peripheral gate fingers 206 in a plan view.

[0108] The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each of the gate trenches 16 in the first set S1 extends in the Y-axis direction in a plan view. Each of the gate trenches 16 in the second set S2 extends in the X-axis direction in a plan view. Each of the gate trenches 16 in the first set S1 and the second set S2 intersects with one of the plurality of peripheral gate fingers 206 in a plan view. The gate trenches 16 in the first set S1 and the second set S2 are arranged across the inner region 42 and the peripheral region 40.

[0109] The plurality of gate trenches 16 may include a third set S3 of gate trenches 16 and a fourth set S4 of gate trenches 16. Each of the gate trenches 16 in the third set S3 extends in the Y-axis direction in a plan view. Each of the gate trenches 16 in the fourth set S4 extends in the X-axis direction in a plan view. Each of the gate trenches 16 in the third set S3 and the fourth set S4 intersects with one of the plurality of inner gate fingers 210 in a plan view. The gate trenches 16 in the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

[0110] 6 , the main portions of each gate trench 16 in the first set S1, excluding the ends, are arranged in subregion 212B or subregion 212F. The main portions of each gate trench 16 in the second set S2, excluding the ends, are arranged in subregion 212A, subregion 212D, or subregion 212E. The main portions of each gate trench 16 in the third set S3, excluding the ends, are arranged in subregion 212B, subregion 212C, or subregion 212F. The main portions of each gate trench 16 in the fourth set S4, excluding the ends, are arranged in subregion 212A, subregion 212D, or subregion 212E.

[0111] Optionally, the plurality of gate trenches 16 may include a fifth set S5 of gate trenches 16 (although only one gate trench 16 is shown in FIG. 6 , the fifth set S5 may include a plurality of gate trenches 16). Each gate trench 16 in the fifth set S5 extends in the Y-axis direction in plan view and intersects with the fifth outer periphery gate finger 206E in plan view. A major portion, excluding the ends, of each gate trench 16 in the fifth set S5 is disposed next to the gate pad 214 in the subregion 212E.

[0112] Each of the sets S1, S2, S3, S4, and S5 may include one or more gate trenches 16. Some of the gate trenches 16 included in each of the sets S1, S2, S3, S4, and S5 may be aligned parallel to one another at equal intervals. The number of gate trenches included in each of the sets S1, S2, S3, S4, and S5 can be determined appropriately depending on the layout.

[0113] The semiconductor device 200 may further include a field plate trench 62. An electrode having the same potential as the field plate electrode 30 (see FIG. 2) may be disposed within the field plate trench 62. The field plate trench 62 may be configured to connect aligned gate trenches 16 whose main portions are disposed in the same subregion 212. The field plate trench 62 may include a portion 62A that connects the gate trenches 16 and two portions 62B that extend parallel to the gate trenches 16. The portion 62A may extend perpendicular to the gate trenches 16. The two portions 62B may be provided on both sides of the connected gate trench 16. The electrode disposed within the field plate trench 62 may be integrally connected to the field plate electrode 30 (see FIG. 2) that is disposed in the gate trench 16 that communicates with the field plate trench 62.

[0114] The semiconductor device 200 may further include a plurality of field plate contact plugs 64. The field plate electrode 30 (see FIG. 2 ) embedded in each gate trench 16 may include two ends connected to the outer periphery segment 218 or one of the inner segments 216 via at least one of the plurality of field plate contact plugs 64.

[0115] (Operation of Semiconductor Device) The operation of the semiconductor device 200 of this embodiment will be described below. The gate wiring 202 includes a plurality of peripheral gate fingers 206 arranged in the peripheral region 40. The plurality of peripheral gate fingers 206 are separated from one another by a plurality of gaps 208 arranged along the outer edge of the inner region 42. If each of the plurality of peripheral gate fingers 206 were extended to eliminate the gaps 208 and connected to one another, the extended portions would generate an excess gate-drain capacitance C ｇｄ Gate-drain capacitance C ｇｄ is the feedback capacitance C of the semiconductor device 200 ｒｓｓ This corresponds to the feedback capacitance C ｒｓｓA large capacitance C can reduce the switching speed of the semiconductor device 200. Therefore, by arranging the gaps 208 along the outer edge of the inner region 42, the excess gate-drain capacitance C ｇｄ can be suppressed.

[0116] In this embodiment, each of the multiple gate trenches 16 is arranged so as to intersect with one of the multiple outer gate fingers 206 and one of the multiple inner gate fingers 210 in plan view. Therefore, even if the gate finger does not extend into the region where the gap 208 is arranged, the gate electrode 28 embedded in each gate trench 16 can be connected to the gate wiring 202.

[0117] Furthermore, the source wiring 204 includes a plurality of inner segments 216 arranged in the plurality of sub-regions 212, respectively, and a peripheral segment 218 arranged in the peripheral region 40. The peripheral segment 218 is continuous with at least two of the plurality of inner segments 216, and each of the at least two inner segments 216 is connected to the peripheral segment 218 via one of the plurality of gaps 208 that is adjacent to the sub-region 212 in which the inner segment 216 is arranged. Therefore, the resistance generated by the source wiring 204 can be reduced.

[0118] Furthermore, the gate wiring 202 includes a plurality of inner gate fingers 210 arranged in the inner region 42. Each of the inner gate fingers 210 is connected to at least one of the outer gate fingers 206. Therefore, the area in which the gate trench 16 can be arranged is expanded, and the on-resistance R of the semiconductor device 200 is reduced. ｏｎ can be reduced.

[0119] As described above, the semiconductor device 200 of this embodiment can reduce the resistance and parasitic capacitance caused by the wiring layout and improve the switching characteristics. The semiconductor device 200 of this embodiment has the following advantages.

[0120] (2-1) The multiple peripheral gate fingers 206 are separated from one another by multiple gaps 208 arranged along the outer edge of the inner region 42. Each of the multiple inner gate fingers 210 is connected to at least one of the multiple peripheral gate fingers 206. The peripheral segment 218 is continuous with at least two of the multiple inner segments 216, and each of the at least two inner segments 216 is connected to the peripheral segment 218 via a gap 208 among the multiple gaps 208 that is adjacent to the sub-region 212 in which the inner segment 216 is arranged.

[0121] This reduces the resistance and parasitic capacitance caused by the wiring layout, improving the switching characteristics of the semiconductor device 200. (2-2) At least two of the gaps 208 may be formed over a length at least equal to the length of one side of the subregion 212 to which the gap 208 is adjacent. By making the length of the gap 208 relatively large, the resistance and parasitic capacitance caused by the wiring layout can be further reduced.

[0122] (2-3) The outer periphery segment 218 is continuous with the inner segments 216, and each of the inner segments 216 may be connected to the outer periphery segment 218 via one of the gaps 208 that is adjacent to the subregion 212 in which the inner segment 216 is located. By connecting all of the inner segments 216 located in the subregions 212 to the outer periphery segment 218, the resistance and parasitic capacitance resulting from the wiring layout can be further reduced.

[0123] (2-4) Each of the multiple gate trenches 16 may be arranged so as to intersect with one of the multiple outer gate fingers 206 and one of the multiple inner gate fingers 210 in plan view. This allows the gate electrode 28 in each gate trench 16 to be connected to the gate wiring 202.

[0124] (2-5) The multiple gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 in the first set S1 extends in the Y-axis direction (first direction) in a plan view, and each gate trench 16 in the second set S2 extends in the X-axis direction (second direction) in a plan view. Each gate trench 16 in the first set S1 and the second set S2 may intersect with one of the multiple peripheral gate fingers 206 in a plan view. This can reduce warping of the semiconductor substrate 12 during wafer processing compared to a case where only gate trenches 16 extending in the same direction are arranged to intersect with the peripheral gate fingers 206.

[0125] (2-6) The plurality of gate trenches 16 may further include a third set S3 of gate trenches 16 and a fourth set S4 of gate trenches 16. Each of the gate trenches 16 in the third set S3 extends in the Y-axis direction (first direction) in a plan view, and each of the gate trenches 16 in the fourth set S4 extends in the X-axis direction (second direction) in a plan view. Each of the gate trenches 16 in the third set S3 and the fourth set S4 may intersect with one of the plurality of inner gate fingers 210 in a plan view. This can reduce warpage of the semiconductor substrate 12 during wafer processing compared to a case where only gate trenches 16 extending in the same direction are arranged to intersect with the inner gate fingers 210.

[0126] (2-7) The field plate electrode 30 embedded in each gate trench 16 may include two ends connected to the outer circumferential segment 218 or one of the inner segments 216 via at least one of the field plate contact plugs 64. Because the two ends of the field plate electrode 30 are connected to the source wiring 204, the resistance due to the length of the field plate electrode 30 can be reduced compared to when only one end is connected.

[0127] 7 is a schematic cross-sectional view of an exemplary semiconductor device 300 according to a third embodiment. In FIG. 7, the same components as those in the semiconductor device 10 shown in FIGS. 1 to 3 are denoted by the same reference numerals. Detailed description of the same components as those in the semiconductor device 10 will be omitted.

[0128] The semiconductor device 300 may be, for example, a MISFET having a trench gate structure as shown in Fig. 2. The semiconductor device 300 includes a gate wiring 302 and a source wiring 304 that are different from the gate wiring 44 and the source wiring 34 of the semiconductor device 10 of the first embodiment.

[0129] The gate wiring 302 is formed on the insulating layer 18 and is electrically connected to a plurality of gate electrodes 28 (see FIG. 2). The source wiring 304 is formed on the insulating layer 18 and is spaced apart from the gate wiring 302. The source wiring 304 is electrically connected to a plurality of field plate electrodes 30 (see FIG. 2).

[0130] The gate wiring 302 includes a plurality of peripheral gate fingers 306 arranged in the peripheral region 40. The plurality of peripheral gate fingers 306 are separated from one another by a plurality of gaps 308 arranged along the outer edge of the inner region 42. In the example of FIG. 7 , the plurality of peripheral gate fingers 306 may include three peripheral gate fingers 306A, 306B, and 306C. More specifically, the plurality of peripheral gate fingers 306 may include a first peripheral gate finger 306A extending in the Y-axis direction, a second peripheral gate finger 306B extending in the X-axis direction, and a third peripheral gate finger 306C including a portion extending in the Y-axis direction and a portion extending in the X-axis direction. The third peripheral gate finger 306C may be L-shaped in plan view. A gate pad 314 (described later) may be arranged to overlap the corner of the third peripheral gate finger 306C.

[0131] The gate wiring 302 further includes a plurality of inner gate fingers 310 arranged in the inner region 42. Each of the plurality of inner gate fingers 310 is connected to at least one of the plurality of peripheral gate fingers 306. The plurality of inner gate fingers 310 may include a first inner gate finger 310A extending in the Y-axis direction and a second inner gate finger 310B extending in the X-axis direction.

[0132] The inner region 42 includes a plurality of subregions 312 separated by at least two of the plurality of inner gate fingers 310 that intersect with each other. Each of the plurality of subregions 312 is adjacent to at least one of the plurality of peripheral gate fingers 306. In the example of FIG. 7 , the first inner gate finger 310A and the second inner gate finger 310B intersect with each other. The plurality of subregions 312 includes four subregions 312A, 312B, 312C, and 312D. The four subregions 312A, 312B, 312C, and 312D are separated by the first inner gate finger 310A and the second inner gate finger 310B that intersect with each other. Each of the four subregions 312A, 312B, 312C, and 312D is adjacent to the first inner gate finger 310A and the second inner gate finger 310B in a plan view. 7, three gaps 308 are adjacent to three sub-regions 312A, 312B, and 312C, respectively. Sub-region 312D is not adjacent to any gaps disposed in the outer peripheral region 40.

[0133] The first inner gate finger 310A is connected to the second perimeter gate finger 306B, which is connected to the first perimeter gate finger 306A and the third perimeter gate finger 306C.

[0134] The gate wiring 302 may further include a gate pad 314. In the example of FIG. 7 , the gate pad 314 is connected to the third outer peripheral gate finger 306C. The gate pad 314 is arranged so as to overlap with a corner of the L-shaped third outer peripheral gate finger 306C. This allows the gate pad 314 to be arranged near a corner of the inner region 42 in the semiconductor device 300 in plan view.

[0135] In a plan view, subregion 312A is surrounded by first inner gate finger 310A, second inner gate finger 310B, and first outer perimeter gate finger 306A. Gap 308A adjacent to subregion 312A is formed between first outer perimeter gate finger 306A and second outer perimeter gate finger 306B.

[0136] Subregion 312B is surrounded in plan view by first inner gate finger 310A, second inner gate finger 310B, and second perimeter gate finger 206B. Gap 308B adjacent to subregion 312B is formed between second perimeter gate finger 306B and third perimeter gate finger 306C.

[0137] In a plan view, subregion 312C is surrounded by first inner gate finger 310A, second inner gate finger 310B, and third outer perimeter gate finger 306C. Gap 308C adjacent to subregion 312C is formed between first outer perimeter gate finger 306A and third outer perimeter gate finger 306C. Subregion 312C is also adjacent to gap 316, which is disposed in inner region 42. Gap 316 is formed between first inner gate finger 310A and third outer perimeter gate finger 306C.

[0138] In a plan view, subregion 312D is surrounded by first inner gate finger 310A, second inner gate finger 310B, third outer perimeter gate finger 306C, and gate pad 314. As described above, subregion 312D is not adjacent to a gap disposed in outer perimeter region 40. Instead, subregion 312D is adjacent to gap 316 disposed in inner region 42.

[0139] In this way, the outer edge of each subregion 312 is surrounded by the gate wiring 302, except for the portions adjacent to the gaps 308 and 316. Each subregion 312 is rectangular in plan view and has four sides. At least two of the gaps 308 may be formed over a length at least equal to that of one side of the subregion 312 to which the gap 308 is adjacent. In the example of FIG. 7 , three gaps 308A, 308B, and 308C are formed over a length equal to that of one side of the subregion 312 (312A, 312B, and 312C) to which the gap 308 is adjacent.

[0140] The source wiring 304 includes a plurality of inner segments 318 arranged in the plurality of sub-regions 312, respectively, and a peripheral segment 320 arranged in the peripheral region 40. The peripheral segment 320 is continuous with at least two of the plurality of inner segments 318. Each of the at least two inner segments 318 is connected to the peripheral segment 320 via one of the plurality of gaps 308 that is adjacent to the sub-region 312 in which the inner segment 318 is arranged.

[0141] 7 , the multiple inner segments 318 include a first inner segment 318A, a second inner segment 318B, a third inner segment 318C, and a fourth inner segment 318D, which are arranged in four sub-regions 312A, 312B, 312C, and 312D, respectively. The outer periphery segment 320 is continuous with the first inner segment 318A, the second inner segment 318B, and the third inner segment 318C. Each of the first inner segment 318A, the second inner segment 318B, and the third inner segment 318C is connected to the outer periphery segment 320 through a gap 308, among the multiple gaps 308A, 308B, and 308C, that is adjacent to the sub-region 312 in which the inner segment 318 is arranged. That is, the first inner segment 318A is connected to the outer periphery segment 320 through the gap 308A that is adjacent to the sub-region 312A in which the first inner segment 318A is arranged. The second inner segment 318B is connected to the outer periphery segment 320 through a gap 308B adjacent to the sub-region 312B in which the second inner segment 318B is located. The third inner segment 318C is connected to the outer periphery segment 320 through a gap 308C adjacent to the sub-region 312C in which the third inner segment 318C is located.

[0142] Meanwhile, the fourth inner segment 318D is connected to one of the first inner segment 318A, the second inner segment 318B, and the third inner segment 318C in the inner region 42. In the example of Figure 7, the fourth inner segment 318D is connected to the third inner segment 318C through a gap 316 disposed in the inner region 42.

[0143] The peripheral segment 320 may extend along the outer edge of the semiconductor layer 14 in a plan view, except for the region where the gate pad 314 is located. (Gate Trench Arrangement) Each of the multiple gate trenches 16 may be arranged to intersect with one of one or more inner gate fingers 310 of the multiple peripheral gate fingers 306 in a plan view. The semiconductor device 300 may further include multiple gate contact plugs 60. The gate electrode 28 (see FIG. 2 ) embedded in each gate trench 16 may be connected to one of one or more inner gate fingers 310 of the multiple peripheral gate fingers 306 via at least one of the multiple gate contact plugs 60. The gate contact plug 60 may be arranged in a region where each of the multiple gate trenches 16 intersects with one of one or more inner gate fingers 310 of the multiple peripheral gate fingers 306 in a plan view.

[0144] The plurality of gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each of the gate trenches 16 in the first set S1 extends in the Y-axis direction in a plan view. Each of the gate trenches 16 in the second set S2 extends in the X-axis direction in a plan view. Each of the gate trenches 16 in the first set S1 and the second set S2 intersects with one of the plurality of peripheral gate fingers 306 in a plan view. The gate trenches 16 in the first set S1 and the second set S2 are arranged across the inner region 42 and the peripheral region 40.

[0145] The plurality of gate trenches 16 may include a third set S3 of gate trenches 16 and a fourth set S4 of gate trenches 16. Each of the gate trenches 16 in the third set S3 extends in the Y-axis direction in a plan view. Each of the gate trenches 16 in the fourth set S4 extends in the X-axis direction in a plan view. Each of the gate trenches 16 in the third set S3 and the fourth set S4 intersects with one of the plurality of inner gate fingers 310 in a plan view. The gate trenches 16 in the third set S3 and the fourth set S4 are entirely disposed within the inner region 42.

[0146] 7 , the main portions of each gate trench 16 in the first set S1, excluding the ends, are arranged in sub-region 312B or sub-region 312C. The main portions of each gate trench 16 in the second set S2, excluding the ends, are arranged in sub-region 312A or sub-region 312D. The main portions of each gate trench 16 in the third set S3, excluding the ends, are arranged in sub-region 312B or sub-region 312C. The main portions of each gate trench 16 in the fourth set S4, excluding the ends, are arranged in sub-region 312A or sub-region 312D.

[0147] Optionally, the plurality of gate trenches 16 may include a fifth set S5 of gate trenches 16. Each of the gate trenches 16 in the fifth set S5 extends in the Y-axis direction in plan view and intersects with the third peripheral gate finger 306C in plan view. A major portion, excluding the ends, of each of the gate trenches 16 in the fifth set S5 is disposed next to the gate pad 314 in the subregion 312D.

[0148] Each of the sets S1, S2, S3, S4, and S5 may include one or more gate trenches 16. Some of the gate trenches 16 included in each of the sets S1, S2, S3, S4, and S5 may be aligned parallel to one another at equal intervals. The number of gate trenches included in each of the sets S1, S2, S3, S4, and S5 can be determined appropriately depending on the layout.

[0149] The semiconductor device 300 may further include a field plate trench 62. An electrode having the same potential as the field plate electrode 30 (see FIG. 2) may be disposed within the field plate trench 62. The field plate trench 62 may be configured to connect aligned gate trenches 16 whose main portions are disposed in the same subregion 312. The field plate trench 62 may include a portion 62A that connects the gate trenches 16 and two portions 62B that extend parallel to the gate trenches 16. The portion 62A may extend perpendicular to the gate trenches 16. The two portions 62B may be provided on both sides of the connected gate trench 16. The electrode disposed within the field plate trench 62 may be integrally connected to the field plate electrode 30 (see FIG. 2) that is disposed in the gate trench 16 that communicates with the field plate trench 62.

[0150] The semiconductor device 300 may further include a plurality of field plate contact plugs 64. The field plate electrode 30 (see FIG. 2 ) embedded in each gate trench 16 may include two ends connected to the outer periphery segment 320 or one of the inner segments 318 via at least one of the plurality of field plate contact plugs 64.

[0151] (Operation of Semiconductor Device) The operation of the semiconductor device 300 of this embodiment will be described below. The gate wiring 302 includes a plurality of peripheral gate fingers 306 arranged in the peripheral region 40. The plurality of peripheral gate fingers 306 are separated from one another by a plurality of gaps 308 arranged along the outer edge of the inner region 42. If each of the plurality of peripheral gate fingers 306 were extended to eliminate the gaps 308 and connected to one another, the extended portions would generate an excess gate-drain capacitance C ｇｄ Gate-drain capacitance C ｇｄ is the feedback capacitance C of the semiconductor device 300 ｒｓｓ This corresponds to the feedback capacitance C ｒｓｓA large capacitance C can reduce the switching speed of the semiconductor device 300. Therefore, by arranging multiple gaps 308 along the outer edge of the inner region 42, the excess gate-drain capacitance C ｇｄ can be suppressed.

[0152] In this embodiment, each of the multiple gate trenches 16 is arranged so as to intersect with one of the multiple outer gate fingers 306 and one of the multiple inner gate fingers 310 in plan view. Therefore, even if the gate finger does not extend into the region where the gap 308 is located, the gate electrode 28 embedded in each gate trench 16 can be connected to the gate wiring 302.

[0153] The source wiring 304 also includes a plurality of inner segments 318 arranged in the plurality of sub-regions 312, respectively, and a peripheral segment 320 arranged in the peripheral region 40. The peripheral segment 320 is continuous with at least two of the plurality of inner segments 318, and each of the at least two inner segments 318 is connected to the peripheral segment 320 via one of the plurality of gaps 308 that is adjacent to the sub-region 312 in which the inner segment 318 is arranged. Therefore, the resistance generated by the source wiring 304 can be reduced.

[0154] Furthermore, the gate wiring 302 includes a plurality of inner gate fingers 310 arranged in the inner region 42. Each of the inner gate fingers 310 is connected to at least one of the outer gate fingers 306. Therefore, the area in which the gate trench 16 can be arranged is expanded, and the on-resistance R of the semiconductor device 300 is reduced. ｏｎ can be reduced.

[0155] As described above, the semiconductor device 300 of this embodiment can reduce the resistance and parasitic capacitance caused by the wiring layout and improve the switching characteristics. The semiconductor device 300 of this embodiment has the following advantages.

[0156] (3-1) The multiple perimeter gate fingers 306 are separated from one another by multiple gaps 308 arranged along the outer edge of the inner region 42. Each of the multiple inner gate fingers 310 is connected to at least one of the multiple perimeter gate fingers 306. The peripheral segment 320 is continuous with at least two of the multiple inner segments 318, and each of the at least two inner segments 318 is connected to the peripheral segment 320 via a gap 308 among the multiple gaps 308 that is adjacent to the subregion 312 in which the inner segment 318 is arranged.

[0157] This reduces the resistance and parasitic capacitance caused by the wiring layout, improving the switching characteristics of the semiconductor device 300. (3-2) At least two of the gaps 308 may be formed over a length at least equal to the length of one side of the subregion 312 to which the gap 308 is adjacent. By making the length of the gap 308 relatively large, the resistance and parasitic capacitance caused by the wiring layout can be further reduced.

[0158] (3-3) Each of the multiple sub-regions 312 may be adjacent to at least one of the multiple peripheral gate fingers 306. This makes it possible to arrange gate trenches 16 in each sub-region 52 that intersect with the peripheral gate fingers 306 in plan view.

[0159] (3-4) Each of the multiple gate trenches 16 may be arranged so as to intersect with one of the multiple outer gate fingers 306 and one of the multiple inner gate fingers 310 in plan view. This allows the gate electrode 28 in each gate trench 16 to be connected to the gate wiring 302.

[0160] (3-5) The multiple gate trenches 16 may include a first set S1 of gate trenches 16 and a second set S2 of gate trenches 16. Each gate trench 16 in the first set S1 extends in the Y-axis direction (first direction) in a plan view, and each gate trench 16 in the second set S2 extends in the X-axis direction (second direction) in a plan view. Each gate trench 16 in the first set S1 and the second set S2 may intersect with one of the multiple peripheral gate fingers 306 in a plan view. This can reduce warping of the semiconductor substrate 12 during wafer processing compared to a case where only gate trenches 16 extending in the same direction are arranged to intersect with the peripheral gate fingers 306.

[0161] (3-6) The plurality of gate trenches 16 may further include gate trenches 16 of a third set S3 and gate trenches 16 of a fourth set S4. Each gate trench 16 of the third set S3 extends in the Y-axis direction (first direction) in a plan view, and each gate trench 16 of the fourth set S4 extends in the X-axis direction (second direction) in a plan view. Each gate trench 16 of the third set S3 and the fourth set S4 may intersect with one of the plurality of inner gate fingers 310 in a plan view. This can reduce warping of the semiconductor substrate 12 during wafer processing compared to a case where only gate trenches 16 extending in the same direction are arranged to intersect with the inner gate fingers 310.

[0162] (3-7) The field plate electrode 30 embedded in each gate trench 16 may include two ends connected to the outer circumferential segment 320 or one of the inner segments 318 via at least one of the field plate contact plugs 64. Because the two ends of the field plate electrode 30 are connected to the source wiring 304, the resistance due to the length of the field plate electrode 30 can be reduced compared to when only one end is connected.

[0163] [Modification of Trench Gate Structure] FIG. 8 is a schematic cross-sectional view of an exemplary semiconductor device 400 for explaining a modification of the trench gate structure.

[0164] The semiconductor device 400 may be a MISFET using a SiC substrate. The semiconductor device 400 includes a semiconductor substrate 402, a semiconductor layer 404 formed on the semiconductor substrate 402, a plurality of gate trenches 406 formed in the semiconductor layer 404, and a plurality of source trenches 408 formed in the semiconductor layer 404. The gate trenches 406 and the source trenches 408 may be arranged alternately.

[0165] The semiconductor substrate 402 may be a SiC substrate. The semiconductor layer 404 may be a SiC epitaxial layer. The semiconductor substrate 402 may include a top surface 402A and a bottom surface 402B opposite the top surface 402A. The semiconductor substrate 402 may correspond to a drain region of a MISFET. The Z-axis direction is a direction perpendicular to the top surface 402A and the bottom surface 402B of the semiconductor substrate 402.

[0166] The semiconductor layer 404 includes a drift region 410 formed on the semiconductor substrate (drain region) 402 , a body region 412 formed on the drift region 410 , and a source region 414 formed on the body region 412 .

[0167] The drain region formed by the semiconductor substrate 402 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 402 may be 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The semiconductor substrate 402 may have a thickness of 5 μm or more and 300 μm or less.

[0168] The drift region 410 may be an n-type region containing n-type impurities at a lower concentration than the semiconductor substrate (drain region) 402. The n-type impurity concentration of the drift region 410 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The drift region 410 may have a thickness of 5 μm or more and 20 μm or less.

[0169] The drift region 410 may include a first concentration region 416 (low concentration region) having a relatively low concentration formed on the semiconductor substrate 402, and a second concentration region 418 (high concentration region) formed on the first concentration region 416 and having a higher concentration than the first concentration region 416. The n-type impurity concentration of the first concentration region 416 is 1×10 １５ cm －３ 1x10 or more １７ cm －３ The n-type impurity concentration of the second concentration region 418 may be 1×10 １６ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0170] Although not shown, a buffer region may be formed between the semiconductor substrate 402 and the drift region 410. The buffer region may have a concentration gradient such that the n-type impurity concentration gradually decreases from the n-type impurity concentration of the semiconductor substrate 402 to the n-type impurity concentration of the drift region 410.

[0171] The body region 412 may be a p-type region containing p-type impurities. The p-type impurity concentration of the body region 412 may be 1×10 １６ cm －３ 1x10 or more １８ cm －３ The source region 414 may be an n-type region containing n-type impurities at a higher concentration than the second concentration region 418. The n-type impurity concentration of the source region 414 may be 1×10 １８ cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0172] In this disclosure, n-type is also referred to as a first conductivity type, and p-type is also referred to as a second conductivity type. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc. The p-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0173] The semiconductor device 400 may further include a drain electrode 420 formed on the bottom surface 402B of the semiconductor substrate 402. The drain electrode 420 is electrically connected to the semiconductor substrate (drain region) 402. The drain electrode 420 may be made of at least one of titanium (Ti), nickel (Ni), palladium (Pd), gold (Au), and silver (Ag).

[0174] The gate trench 406 has an opening in the upper surface 404A of the semiconductor layer 404 and has a depth in the Z-axis direction. The gate trench 406 may have a depth of 0.1 μm or more and 3 μm or less. The gate trench 406 has sidewalls 406A and a bottom wall 406B. The gate trench 406 penetrates the source region 414 and the body region 412 of the semiconductor layer 404. The semiconductor layer 404 may further include a first well region 422 formed between the second concentration region 418 and the sidewalls 406A and bottom wall 406B of the gate trench 406. The first well region 422 may be a p-type region containing a higher concentration of p-type impurities than the body region 412. The p-type impurity concentration of the first well region 422 is 1×10 １６ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0175] The source trench 408 has an opening in the upper surface 404A of the semiconductor layer 404 and has a depth in the Z-axis direction. The source trench 408 may have a depth of 0.5 μm or more and 10 μm or less. The source trench 408 has sidewalls 408A and a bottom wall 408B. The source trench 408 penetrates the source region 414 and the body region 412 of the semiconductor layer 404. The semiconductor layer 404 may further include a second well region 424 formed between the second concentration region 418 and the sidewalls 408A and bottom wall 408B of the source trench 408. The second well region 424 may be a p-type region containing a higher concentration of p-type impurities than the body region 412. The p-type impurity concentration of the second well region 424 is 1×10 １６ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0176] The semiconductor device 400 further includes an insulating layer 426 formed on the semiconductor layer 404, and a plurality of gate electrodes 428. Each of the plurality of gate electrodes 428 is embedded in a corresponding one of the plurality of gate trenches 406 via the insulating layer 426.

[0177] The semiconductor device 400 further includes a plurality of source electrodes 430. Each of the plurality of source electrodes 430 is embedded in a corresponding one of the plurality of source trenches 408 via an insulating layer 426.

[0178] The gate electrode 428 may be configured to receive a gate voltage, and the source electrode 430 may be configured to receive a reference voltage (or source voltage). The gate electrode 428 and the source electrode 430 may be formed from conductive polysilicon, in one example.

[0179] The semiconductor device 400 may further include a plurality of gate contact electrodes 432. The plurality of gate contact electrodes 432 cover a portion of the upper surface 404A of the semiconductor layer 404 and are connected to the plurality of gate electrodes 428, respectively.

[0180] The semiconductor device 400 may further include an insulating layer 434 formed on the upper surface 404A of the semiconductor layer 404. The insulating layer 434 is formed to be thicker than the gate contact electrodes 432. The insulating layer 434 has a plurality of gate openings 434A that expose the plurality of gate contact electrodes 432, respectively.

[0181] The semiconductor device 400 may further include a gate wiring 436 formed on the insulating layer 434. The gate wiring 436 includes a barrier layer 438 formed on the insulating layer 434 and a wiring layer 440 formed on the barrier layer 438. The barrier layer 438 may include at least one of a Ti layer and a TiN layer. The barrier layer 438 may have a thickness of 10 nm to 500 nm. The wiring layer 440 may include at least one of a Cu layer, an Al layer, an AlCu alloy layer, an AlSi alloy layer, and an AlSiCu alloy layer. The wiring layer 440 may have a thickness of 0.5 μm to 10 μm.

[0182] The gate trench 406 of the semiconductor device 400 using SiC as described above can be arranged in the planar layout of the semiconductor device 10 of the first embodiment shown in FIG. 1 . Specifically, the gate trench 406 shown in FIG. 8 can be arranged at the position of the gate trench 16 shown in FIG. 1 . In this case, the gate wiring 436 corresponds to the gate wiring 44 shown in FIG. 1 . Therefore, FIG. 8 shows a cross section of a region where the gate wiring 436 formed as a gate finger is arranged. The source electrode 430 can be electrically connected to a source wiring (not shown) corresponding to the source wiring 34 shown in FIG. 1 . Furthermore, the gate trench 406 of the semiconductor device 400 can also be arranged in the planar layout of the semiconductor device 200 of the second embodiment shown in FIG. 6 or the planar layout of the semiconductor device 300 of the third embodiment shown in FIG. 7 . As a result, the resistance and parasitic capacitance caused by the wiring layout can be reduced and the switching characteristics can be improved even in the semiconductor device 400 using SiC.

[0183] [Other Modifications] Each of the above-described embodiments and modifications can be modified as follows: The length of each gate trench 16 in the first set S1 may be the same as or different from the length of each gate trench 16 in the third set S3. Similarly, the length of each gate trench 16 in the second set S2 may be the same as or different from the length of each gate trench 16 in the fourth set S4.

[0184] The number of inner gate fingers 50 may be four or more. Some of the gaps 48 may be formed over a length that is shorter than one side of the sub-region 52 to which the gap 48 is adjacent.

[0185] A structure in which the conductivity types of the regions in the semiconductor layer 14 are reversed may be adopted. That is, a p-type region may be made into an n-type region, and an n-type region may be made into a p-type region. An additional wiring structure may be formed on the layer including the source wiring 34 and the gate wiring 44.

[0186] 6, the plurality of peripheral gate fingers 206 do not have to include the sixth peripheral gate finger 206F. In this case, one gap may be formed between the second peripheral gate finger 206B and the fourth peripheral gate finger 206D.

[0187] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "only A, or only B, or both A and B."

[0188] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0189] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0190] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, and does not necessarily have to completely coincide with the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0191] [Supplementary Note] The technical ideas that can be understood from the above-described embodiment and each modified example are described below. Note that, for the purpose of aiding understanding and not intending to limit the scope of the invention, the corresponding reference numerals in the embodiment are shown in parentheses for the configurations described in the Supplementary Note. The reference numerals are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference numerals.

[0192] (Appendix A1) A semiconductor substrate (12); A semiconductor layer (14) formed on the semiconductor substrate (12) and including an outer periphery region (40) and an inner region (42) having a rectangular outer edge surrounded by the outer periphery region (40) in a plan view; A plurality of gate trenches (16) formed in the semiconductor layer (14); An insulating layer (18) formed on the semiconductor layer (14); A plurality of gate electrodes (28), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18); A plurality of field plate electrodes (30), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18) while being spaced apart from the gate electrode (28); A gate wiring (44) formed on the insulating layer (18) and electrically connected to the plurality of gate electrodes (28); and a source wiring (34) formed on the insulating layer (18), spaced apart from the gate wiring (44), and electrically connected to the plurality of field plate electrodes (30), wherein the gate wiring (44) comprises: a plurality of peripheral gate fingers (46) arranged in the outer periphery region (40), the plurality of peripheral gate fingers (46) being spaced apart from one another by a plurality of gaps (48) arranged along an outer edge of the inner region (42); and a plurality of inner gate fingers (50) arranged in the inner region (42), each of the plurality of peripheral gate fingers (46) being connected to at least one of the plurality of inner gate fingers (46), wherein the inner region (42) comprises a plurality of subregions (52) separated by at least two of the plurality of inner gate fingers (50) that intersect with one another, and the source wiring (34) comprises: a plurality of inner segments (56) arranged in each of the plurality of subregions (52), and a peripheral segment (58) disposed in said peripheral region (40),The semiconductor device, wherein the outer periphery segment (58) is continuous with at least two of the plurality of inner segments (56), and each of the at least two inner segments (56) is connected to the outer periphery segment (58) through a gap (48) among the plurality of gaps (48) that is adjacent to the sub-region (52) in which the inner segment (56) is located.

[0193] (Appendix A2) A semiconductor device according to Appendix A1, wherein each sub-region (52) is rectangular in plan view and has four sides, and at least two of the plurality of gaps (48) are formed over a length at least equal to that of one side of the sub-region (52) to which the gap (48) is adjacent.

[0194] (Supplementary Note 3) The semiconductor device according to Supplementary Note A1 or A2, wherein each of the plurality of sub-regions (52) is adjacent to at least one of the plurality of peripheral gate fingers (46).

[0195] (Appendix A4) A semiconductor device described in any one of Appendices A1 to A3, wherein the outer circumferential segment (58) is continuous with the plurality of inner segments (56), and each of the plurality of inner segments (56) is connected to the outer circumferential segment (58) via a gap (48) among the plurality of gaps (48) that is adjacent to the sub-region (52) in which the inner segment (56) is arranged.

[0196] (Appendix A5) A semiconductor device described in any one of Appendices A1 to A4, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, and the plurality of inner gate fingers (50) include a first inner gate finger (50A) extending in the first direction and a second inner gate finger (50B) extending in the second direction.

[0197] (Appendix A6) The semiconductor device described in Appendix 5, wherein the plurality of subregions (52) include four subregions (52A, 52B, 52C, 52D), and each of the four subregions (52A, 52B, 52C, 52D) is adjacent to the first inner gate finger (50A) and the second inner gate finger (50B) in a planar view.

[0198] (Appendix A7) The plurality of inner segments (56) include four inner segments (56A, 56B, 56C, 56D) respectively arranged in the four sub-regions (52A, 52B, 52C, 52D), and the plurality of gaps (48) include four gaps (48A, 48B, 48C, 48C) respectively adjacent to the four sub-regions (52A, 52B, 52C, 52D), The semiconductor device described in Appendix A6, wherein the outer circumferential segment (58) is continuous with the four inner segments (56A, 56B, 56C, 56D), and each of the four inner segments (56A, 56B, 56C, 56D) is connected to the outer circumferential segment (58) through a gap (48) among the four gaps (48A, 48B, 48C, 48C) adjacent to the sub-region (52) in which the inner segment (56) is arranged.

[0199] (Appendix A8) The semiconductor device according to any one of Appendices A5 to A7, wherein the plurality of outer peripheral gate fingers (46) include a first outer peripheral gate finger (46A) and a second outer peripheral gate finger (46B) extending in the first direction, and a third outer peripheral gate finger (46C) and a fourth outer peripheral gate finger (46D) extending in the second direction, the first inner gate finger (50A) is connected to the third outer peripheral gate finger (46C) and the fourth outer peripheral gate finger (46D), and the second inner gate finger (50B) is connected to the first outer peripheral gate finger (46A) and the second outer peripheral gate finger (46B).

[0200] (Appendix A9) The plurality of inner segments (318) include first, second, third, and fourth inner segments (318A, 318B, 318C, 318D) respectively arranged in the four sub-regions (312), the outer circumferential segment (320) is continuous with the first, second, and third inner segments (318A, 318B, 318C), and each of the first, second, and third inner segments (318A, 318B, 318C) is connected to the outer circumferential segment (320) via a gap (308) among the plurality of gaps (308) that is adjacent to the sub-region (312) in which the inner segment (318) is arranged, The semiconductor device of appendix A6 or A7, wherein the fourth inner segment (318D) is connected to one of the first, second, and third inner segments (318A, 318B, 318C) in the inner region (42).

[0201] (Appendix A10) The semiconductor device according to Appendix A9, wherein the gate wiring (302) includes a gate pad (314), the plurality of outer gate fingers (306) include a first outer gate finger (306A) extending in the first direction, a second outer gate finger (306B) extending in the second direction, and a third outer gate finger (306C) including a portion extending in the first direction and a portion extending in the second direction, the first inner gate finger (310A) is connected to the second outer gate finger (306B), the second inner gate finger (310B) is connected to the first outer gate finger (306A) and the third outer gate finger (306C), and the gate pad (314) is connected to the third outer gate finger (306C).

[0202] (Appendix A11) A semiconductor device according to Appendix A1 or A2, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, the plurality of inner gate fingers (210) include a first inner gate finger (210A) extending in the first direction, a second inner gate finger (210B) extending in the second direction, and a third inner gate finger (210C) extending in the second direction, and the first inner gate finger (210A) intersects with the second inner gate finger (210B) and the third inner gate finger (210C).

[0203] (Appendix A12) The semiconductor device according to Appendix A11, wherein the plurality of subregions (212) include six subregions (212A, 212B, 212C, 212D, 212E, 212F), and each of the six subregions (212A, 212B, 212C, 212D, 212E, 212F) is adjacent to the first inner gate finger (210A) in a planar view and adjacent to the second inner gate finger (210B) or the third inner gate finger (210C) in a planar view.

[0204] (Appendix A13) The plurality of inner segments (216) include six inner segments (216A, 216B, 216C, 216D, 216E, 216F) respectively arranged in the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), and the plurality of gaps (208) include six gaps (208A, 208B, 208C, 208D, 208E, 208F) respectively adjacent to the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), A semiconductor device as described in Appendix A12, wherein the outer circumferential segment (218) is continuous with the six inner segments (216A, 216B, 216C, 216D, 216E, 216F), and each of the six inner segments (216A, 216B, 216C, 216D, 216E, 216F) is connected to the outer circumferential segment (218) through a gap (208) among the six gaps (208A, 208B, 208C, 208D, 208E, 208F) adjacent to the sub-region (212) in which the inner segment (216) is arranged.

[0205] (Appendix A14) A semiconductor device described in Appendix A12 or A13, wherein one of the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F) is not adjacent to any of the plurality of outer gate fingers (206) and is adjacent to the first, second, and third inner gate fingers (210A, 210B, 210C).

[0206] (Appendix A15) The semiconductor device according to any one of Appendices A1 to A14, wherein each of the plurality of gate trenches (16) is arranged to intersect with one of the plurality of outer gate fingers (46) or one of the plurality of inner gate fingers (50) in a planar view.

[0207] (Appendix A16) The semiconductor device according to any one of Appendices A1 to A14, further comprising a plurality of gate contact plugs (60), wherein a gate electrode (28) embedded in each gate trench (16) is connected to one of the plurality of outer gate fingers (46) or one of the plurality of inner gate fingers (50) via at least one of the plurality of gate contact plugs (60).

[0208] (Appendix A17) The semiconductor device according to any one of Appendices A1 to A14, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, the plurality of gate trenches (16) include a first set (S1) of gate trenches and a second set (S2) of gate trenches, each gate trench of the first set (S1) extending in the first direction in a planar view and each gate trench of the second set (S2) extending in the second direction in a planar view, and each gate trench of the first set (S1) and the second set (S2) intersecting with one of the plurality of peripheral gate fingers (46) in a planar view.

[0209] (Appendix A18) The semiconductor device described in Appendix A17, wherein the plurality of gate trenches (16) further include a third set (S3) of gate trenches and a fourth set (S4) of gate trenches, each of the gate trenches of the third set (S3) extending in the first direction in a planar view, each of the gate trenches of the fourth set (S4) extending in the second direction in a planar view, and each of the gate trenches of the third set (S3) and the fourth set (S4) intersecting with one of the plurality of inner gate fingers (50) in a planar view.

[0210] (Appendix A19) A semiconductor device according to Appendix A18, wherein the first set (S1) and the second set (S2) of gate trenches are arranged across the inner region (42) and the outer periphery region (40), and the third set (S3) and the fourth set (S4) of gate trenches are arranged entirely within the inner region (42).

[0211] (Appendix A20) The semiconductor device according to appendix A18 or A19, further comprising a plurality of field plate contact plugs (64), wherein the field plate electrode (30) embedded in each of the first set (S1) of gate trenches includes a first end (66) connected to the outer circumferential segment (58) via at least one of the plurality of field plate contact plugs (64) and a second end (68) connected to one of the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64), and wherein the field plate electrode (30) embedded in each of the third set (S3) of gate trenches includes a first end (70) connected to one of the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64) and a second end (72) connected to another of the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64).

[0212] (Appendix A21) The semiconductor device according to any one of Appendices A1 to A20, wherein the semiconductor layer (14) includes a drift region (20) of a first conductivity type, a body region (22) of a second conductivity type formed on the drift region (20), and a source region (24) of the first conductivity type formed on the body region (22), and the gate trench (16) penetrates the source region (24) and the body region (22) and reaches the drift region (20).

[0213] (Appendix B1) A semiconductor substrate (12); A semiconductor layer (14) formed on the semiconductor substrate (12) and including an outer periphery region (40) and an inner region (42) having a rectangular outer edge surrounded by the outer periphery region (40) in a plan view; A plurality of gate trenches (16) formed in the semiconductor layer (14); An insulating layer (18) formed on the semiconductor layer (14); A plurality of gate electrodes (28), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18); A plurality of field plate electrodes (30), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18) while being spaced apart from the gate electrode (28); A gate wiring (44) formed on the insulating layer (18) and electrically connected to the plurality of gate electrodes (28); and a source wiring (34) formed on the insulating layer (18), spaced apart from the gate wiring (44), and electrically connected to the plurality of field plate electrodes (30), wherein the gate wiring (44) comprises: a plurality of peripheral gate fingers (46) arranged in the outer periphery region (40), the plurality of peripheral gate fingers (46) being spaced apart from one another by a plurality of gaps (48) arranged along an outer edge of the inner region (42); and a plurality of inner gate fingers (50) arranged in the inner region (42), each of the plurality of peripheral gate fingers (46) being connected to at least one of the plurality of inner gate fingers (46), wherein the inner region (42) comprises a plurality of subregions (52) separated by at least two of the plurality of inner gate fingers (50) that intersect with one another, and the source wiring (34) comprises: a plurality of inner segments (56) arranged in each of the plurality of subregions (52), and a peripheral segment (58) disposed in said peripheral region (40),The outer circumferential segment (58) is continuous with the plurality of inner segments (56), and each of the plurality of inner segments (56) is connected to the outer circumferential segment (58) through a gap (48) among the plurality of gaps (48) that is adjacent to the sub-region (52) in which the inner segment (56) is located.

[0214] (Appendix B2) A semiconductor device according to Appendix B1, wherein each sub-region (52) is rectangular in plan view and has four sides, and at least two of the gaps (48) are formed over a length at least equal to that of one side of the sub-region (52) to which the gap (48) is adjacent.

[0215] (Appendix B3) The semiconductor device according to appendix B1 or B2, wherein each of the plurality of sub-regions (52) is adjacent to at least one of the plurality of peripheral gate fingers (46).

[0216] (Appendix B4) A semiconductor device described in any one of Appendices B1 to B3, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, and the plurality of inner gate fingers (50) include a first inner gate finger (50A) extending in the first direction and a second inner gate finger (50B) extending in the second direction.

[0217] (Appendix B5) The semiconductor device described in Appendix B4, wherein the plurality of subregions (52) include four subregions (52A, 52B, 52C, 52D), and each of the four subregions (52A, 52B, 52C, 52D) is adjacent to the first inner gate finger (50A) and the second inner gate finger (50B) in a planar view.

[0218] (Appendix B6) The plurality of inner segments (56) include four inner segments (56A, 56B, 56C, 56D) respectively arranged in the four sub-regions (52A, 52B, 52C, 52D), and the plurality of gaps (48) include four gaps (48A, 48B, 48C, 48C) respectively adjacent to the four sub-regions (52A, 52B, 52C, 52D), The semiconductor device described in Appendix B5, wherein the outer peripheral segment (58) is continuous with the four inner segments (56A, 56B, 56C, 56D), and each of the four inner segments (56A, 56B, 56C, 56D) is connected to the outer peripheral segment (58) through a gap (48) among the four gaps (48A, 48B, 48C, 48C) that is adjacent to the sub-region (52) in which the inner segment (56) is arranged.

[0219] (Appendix B7) A semiconductor device according to any one of Appendices B4 to B6, wherein the plurality of outer peripheral gate fingers (46) include a first outer peripheral gate finger (46A) and a second outer peripheral gate finger (46B) extending in the first direction, and a third outer peripheral gate finger (46C) and a fourth outer peripheral gate finger (46D) extending in the second direction, the first inner gate finger (50A) is connected to the third outer peripheral gate finger (46C) and the fourth outer peripheral gate finger (46D), and the second inner gate finger (50B) is connected to the first outer peripheral gate finger (46A) and the second outer peripheral gate finger (46B).

[0220] (Appendix B8) A semiconductor device according to Appendix B1 or B2, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, the plurality of inner gate fingers (210) include a first inner gate finger (210A) extending in the first direction, a second inner gate finger (210B) extending in the second direction, and a third inner gate finger (210C) extending in the second direction, and the first inner gate finger (210A) intersects with the second inner gate finger (210B) and the third inner gate finger (210C).

[0221] (Appendix B9) The semiconductor device according to Appendix B8, wherein the plurality of subregions (212) include six subregions (212A, 212B, 212C, 212D, 212E, 212F), and each of the six subregions (212A, 212B, 212C, 212D, 212E, 212F) is adjacent to the first inner gate finger (210A) in a planar view and adjacent to the second inner gate finger (210B) or the third inner gate finger (210C) in a planar view.

[0222] (Appendix B10) The plurality of inner segments (216) include six inner segments (216A, 216B, 216C, 216D, 216E, 216F) respectively arranged in the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), and the plurality of gaps (208) include six gaps (208A, 208B, 208C, 208D, 208E, 208F) respectively adjacent to the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F), A semiconductor device as described in Appendix B9, wherein the outer circumferential segment (218) is continuous with the six inner segments (216A, 216B, 216C, 216D, 216E, 216F), and each of the six inner segments (216A, 216B, 216C, 216D, 216E, 216F) is connected to the outer circumferential segment (218) through a gap (208) among the six gaps (208A, 208B, 208C, 208D, 208E, 208F) adjacent to the sub-region in which the inner segment (216) is arranged.

[0223] (Appendix B11) A semiconductor device described in Appendix B9 or B10, wherein one of the six sub-regions (212A, 212B, 212C, 212D, 212E, 212F) is not adjacent to any of the plurality of outer gate fingers (206) and is adjacent to the first, second, and third inner gate fingers (210A, 210B, 210C).

[0224] (Appendix B12) A semiconductor device described in any one of Appendices B1 to B11, wherein each of the plurality of gate trenches (16) is arranged so as to intersect with one of the plurality of peripheral gate fingers (46) or one of the plurality of inner gate fingers (50) in a planar view.

[0225] (Appendix B13) A semiconductor device according to any one of Appendices B1 to B12, further comprising a plurality of gate contact plugs (60), wherein a gate electrode (28) embedded in each gate trench (16) is connected to one of the plurality of outer gate fingers (46) or one of the plurality of inner gate fingers (50) via at least one of the plurality of gate contact plugs (60).

[0226] (Appendix B14) The semiconductor device according to any one of Appendices B1 to B13, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, the plurality of gate trenches (16) include a first set (S1) of gate trenches and a second set (S2) of gate trenches, each gate trench of the first set (S1) extending in the first direction in a planar view and each gate trench of the second set (S2) extending in the second direction in a planar view, and each gate trench of the first set (S1) and the second set (S2) intersecting with one of the plurality of peripheral gate fingers (46) in a planar view.

[0227] (Appendix B15) The semiconductor device described in Appendix B14, wherein the plurality of gate trenches (16) further include a third set (S3) of gate trenches and a fourth set (S4) of gate trenches, each of the gate trenches of the third set (S3) extending in the first direction in a planar view, each of the gate trenches of the fourth set (S4) extending in the second direction in a planar view, and each of the gate trenches of the third set (S3) and the fourth set (S4) intersecting with one of the plurality of inner gate fingers (50) in a planar view.

[0228] (Appendix B16) A semiconductor device according to Appendix B15, wherein the first set (S1) and the second set (S2) of gate trenches are arranged across the inner region (42) and the outer periphery region (40), and the third set (S3) and the fourth set (S4) of gate trenches are arranged entirely within the inner region (42).

[0229] (Appendix B17) The semiconductor device according to appendix B15 or B16, further comprising a plurality of field plate contact plugs (64), wherein the field plate electrode (30) embedded in each of the first set (S1) of gate trenches includes a first end (66) connected to the outer circumferential segment (58) via at least one of the plurality of field plate contact plugs (64) and a second end (68) connected to one of the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64), and wherein the field plate electrode (30) embedded in each of the third set (S3) of gate trenches includes a first end (70) connected to one of the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64) and a second end (72) connected to another of the plurality of inner segments (56) via at least one of the plurality of field plate contact plugs (64).

[0230] (Appendix B18) The semiconductor device according to any one of Appendices B1 to B17, wherein the semiconductor layer (14) includes a drift region (20) of a first conductivity type, a body region (22) of a second conductivity type formed on the drift region (20), and a source region (24) of the first conductivity type formed on the body region (22), and the gate trench (16) penetrates the source region (24) and the body region (22) and reaches the drift region (20).

[0231] (Appendix C1) A semiconductor substrate (12); A semiconductor layer (14) formed on the semiconductor substrate (12) and including an outer periphery region (40) and an inner region (42) having a rectangular outer edge surrounded by the outer periphery region (40) in a plan view; A plurality of gate trenches (16) formed in the semiconductor layer (14); An insulating layer (18) formed on the semiconductor layer (14); A plurality of gate electrodes (28), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18); A plurality of field plate electrodes (30), each of which is embedded in a corresponding one of the plurality of gate trenches (16) via the insulating layer (18) while being spaced apart from the gate electrode (28); A gate wiring (302) formed on the insulating layer (18) and electrically connected to the plurality of gate electrodes (28); and a source wiring (304) formed on the insulating layer (18), spaced apart from the gate wiring (302), and electrically connected to the plurality of field plate electrodes (30), wherein the gate wiring (302) includes: three peripheral gate fingers (306A, 306B, 306C) arranged in the peripheral region (40), the three peripheral gate fingers (306A, 306B, 306C) being spaced apart from one another by three gaps (308A, 308B, 308C) arranged along an outer edge of the inner region (42); and two inner gate fingers (310A, 310B) arranged in the inner region (42), each connected to at least one of the three peripheral gate fingers (306A, 306B, 306C), The inner region (42) includes four sub-regions (312A, 312B, 312C, 312D) separated by the two inner gate fingers (310A, 310B) that cross each other, and the source wiring (304) includes first, second, third, and fourth inner segments (318A, 318B, 318C, 318D) that are respectively arranged in the four sub-regions (312A, 312B, 312C, 312D).318D), and an outer circumferential segment (320) arranged in the outer circumferential region (40), wherein the outer circumferential segment (320) is continuous with the first, second, and third inner segments (318A, 318B, 318C), and each of the first, second, and third inner segments (318A, 318B, 318C) is connected to the outer circumferential segment (320) through a gap (308) of the three gaps (308A, 308B, 308C) adjacent to the sub-region (312) in which the inner segment (318) is arranged.

[0232] (Appendix C2) A semiconductor device according to Appendix C1, wherein each sub-region (312) is rectangular in plan view and has four sides, and at least two of the three gaps (308A, 308B, 308C) are formed over a length at least equal to that of one side of the sub-region (312) to which the gap (308) is adjacent.

[0233] (Supplementary Note C3) The semiconductor device according to Supplementary Note C1 or C2, wherein each of the four sub-regions (312A, 312B, 312C, 312D) is adjacent to at least one of the three outer periphery gate fingers (306A, 306B, 306C).

[0234] (Appendix C4) The semiconductor device according to any one of appendices C1 to C3, wherein the fourth inner segment (318D) is connected to one of the first, second, and third inner segments (318A, 318B, 318C) in the inner region (42).

[0235] (Appendix C5) A semiconductor device according to any one of Appendices C1 to C4, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, and the two inner gate fingers (310A, 310B) include a first inner gate finger (310A) extending in the first direction and a second inner gate finger (310B) extending in the second direction.

[0236] (Appendix C6) The semiconductor device according to Appendix C5, wherein the gate wiring (302) includes a gate pad, the three outer periphery gate fingers (306A, 306B, 306C) include a first outer periphery gate finger (306A) extending in the first direction, a second outer periphery gate finger (306B) extending in the second direction, and a third outer periphery gate finger (306C) including a portion extending in the first direction and a portion extending in the second direction, the first inner gate finger (310A) is connected to the second outer periphery gate finger (306B), the second inner gate finger (310B) is connected to the first outer periphery gate finger (306A) and the third outer periphery gate finger (306C), and the gate pad is connected to the third outer periphery gate finger (306C).

[0237] (Appendix C7) A semiconductor device according to any one of Appendices C1 to C6, wherein each of the plurality of gate trenches (16) is arranged so as to intersect with one of the three outer gate fingers (306A, 306B, 306C) or one of the two inner gate fingers (310A, 310B) in a planar view.

[0238] (Appendix C8) A semiconductor device according to any one of Appendices C1 to C7, further comprising a plurality of gate contact plugs (60), wherein a gate electrode (28) embedded in each gate trench (16) is connected to one of the three outer gate fingers (306A, 306B, 306C) or one of the two inner gate fingers (310A, 310B) via at least one of the plurality of gate contact plugs (60).

[0239] (Appendix C9) The semiconductor device according to any one of Appendices C1 to C8, wherein the rectangular outer edge of the inner region (42) has two sides extending in a first direction in a planar view and two sides extending in a second direction perpendicular to the first direction in a planar view, the plurality of gate trenches (16) include a first set (S1) of gate trenches and a second set (S2) of gate trenches, each gate trench of the first set (S1) extending in the first direction in a planar view and each gate trench of the second set (S2) extending in the second direction in a planar view, and each gate trench of the first set (S1) and the second set (S2) intersecting with one of the three peripheral gate fingers (306A, 306B, 306C) in a planar view.

[0240] (Appendix C10) The semiconductor device described in Appendix C9, wherein the plurality of gate trenches (16) further include a third set (S3) of gate trenches and a fourth set (S4) of gate trenches, each of the gate trenches of the third set (S3) extending in the first direction in a planar view, each of the gate trenches of the fourth set (S4) extending in the second direction in a planar view, and each of the gate trenches of the third set (S3) and the fourth set (S4) intersecting with one of the two inner gate fingers (310A, 310B) in a planar view.

[0241] (Appendix C11) A semiconductor device according to Appendix C10, wherein the first set (S1) and the second set (S2) of gate trenches are arranged across the inner region (42) and the outer periphery region (40), and the third set (S3) and the fourth set (S4) of gate trenches are arranged entirely within the inner region (42).

[0242] (Appendix C12) The semiconductor device further comprises a plurality of field plate contact plugs (64), wherein the field plate electrode (30) embedded in each of the first set (S1) of gate trenches includes a first end connected to the outer circumferential segment (320) via at least one of the plurality of field plate contact plugs (64), and a second end connected to one of the first, second, third, and fourth inner segments (318A, 318B, 318C, 318D) via at least one of the plurality of field plate contact plugs (64), The semiconductor device of claim 10 or 11, wherein the field plate electrode (30) embedded in each of the third set (S3) of gate trenches includes a first end connected to one of the first, second, third, and fourth inner segments (318A, 318B, 318C, 318D) via at least one of the plurality of field plate contact plugs (64), and a second end connected to another one of the first, second, third, and fourth inner segments (318A, 318B, 318C, 318D) via at least one of the plurality of field plate contact plugs (64).

[0243] (Appendix C13) The semiconductor device according to any one of Appendices C1 to C12, wherein the semiconductor layer (14) includes a drift region (20) of a first conductivity type, a body region (22) of a second conductivity type formed on the drift region (20), and a source region (24) of the first conductivity type formed on the body region (22), and the gate trench (16) penetrates the source region (24) and the body region (22) and reaches the drift region (20).

[0244] 10, 100, 200, 300, 400... Semiconductor device 12, 402... Semiconductor substrate 12A, 402A... Top surface 12B, 402B... Bottom surface 14, 404... Semiconductor layer 16, 406... Gate trench 18, 426, 434... Insulating layer 20, 410... Drift region 22, 412... Body region 24, 414... Source region 26, 420... Drain electrode 28, 428... Gate electrode 28A... Top surface 28B... Bottom surface 28C... Side surface 30... Field plate electrode 32... Source contact plug 34, 104, 204... Source wiring 36... Contact region 38... Gate insulating portion 40... Peripheral region 42... Inner region 44, 102, 202, 302, 436... Gate wiring 46, 106, 206, 306... Peripheral gate fingers 46A, 206A, 306A... First peripheral gate finger 46B, 206B, 306B... Second peripheral gate finger 46C, 206C, 306C... Third peripheral gate finger 46D, 206D... Fourth peripheral gate finger 206E... Fifth peripheral gate finger 206F... Sixth peripheral gate finger 48, 48A, 48B, 48C, 48D, 110, 114, 116, 118, 208, 208A, 208B, 208C, 208D, 208E, 208F, 308, 308A, 208B, 308C, 316... Gap 50, 112, 210, 310... Inner gate finger 50A, 112A, 210A, 310A... First inner gate finger 50B, 112B, 210B, 310B... Second inner gate finger 210C... Third inner gate finger 52, 52A, 52B, 52C, 52D, 120A, 120B, 120C, 120D, 212, 212A, 212B, 212C, 212D, 212E, 212F, 312, 312A, 312B, 312C, 312D... Sub-regions 54, 108, 214, 314... Gate pad 56, 56A, 56B, 56C, 56D, 122A, 122B, 122C, 122D, 216, 216A, 216B, 216C, 216D, 216E, 216F, 318, 318A, 318B, 318C, 318D... inner segments 58, 124, 218,320...periphery segment 60...gate contact plug 62...field plate trench 64...field plate contact plug 66, 68, 70, 72...end portion 408...source trench 422...first well region 424...second well region 430...source electrode 432...gate contact electrode 438...barrier layer 440...wiring layer S1...first set S2...second set S3...third set S4...fourth set

Claims

1. A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate, the semiconductor layer including an outer periphery region and an inner region having a rectangular outer edge surrounded by the outer periphery region in a plan view; A plurality of gate trenches formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a plurality of gate electrodes, each of which is embedded in a corresponding one of the plurality of gate trenches via the insulating layer; a plurality of field plate electrodes, each of which is embedded in a corresponding one of the plurality of gate trenches via the insulating layer while being spaced apart from the gate electrode; a gate wiring formed on the insulating layer and electrically connected to the plurality of gate electrodes; a source wiring formed on the insulating layer, spaced apart from the gate wiring, and electrically connected to the plurality of field plate electrodes; Equipped with The gate wiring is a plurality of perimeter gate fingers disposed in the perimeter region, the plurality of perimeter gate fingers being spaced apart by a plurality of gaps disposed along an outer edge of the inner region; a plurality of inner gate fingers disposed in the inner region, each inner gate finger connected to at least one of the plurality of perimeter gate fingers; Including, the inner region includes a plurality of sub-regions separated by at least two mutually intersecting inner gate fingers among the plurality of inner gate fingers; The source wiring is A plurality of inner segments disposed in the plurality of sub-regions, respectively; a peripheral segment disposed in the peripheral region; Including, The semiconductor device, wherein the outer perimeter segment is continuous with at least two of the plurality of inner segments, and each of the at least two inner segments is connected to the outer perimeter segment through a gap among the plurality of gaps that is adjacent to a subregion in which the inner segment is located.

2. Each sub-region is rectangular in plan view and has four sides; The semiconductor device according to claim 1 , wherein at least two of the plurality of gaps are formed over a length at least equal to one side of the sub-regions adjacent to the gap.

3. The semiconductor device of claim 1 , wherein each of said plurality of sub-regions is adjacent to at least one of said plurality of perimeter gate fingers.

4. 2. The semiconductor device of claim 1 , wherein the outer periphery segment is continuous with the inner segments, and each of the inner segments is connected to the outer periphery segment through a gap among the gaps that is adjacent to a sub-region in which the inner segment is located.

5. a rectangular outer edge of the inner region has two sides extending in a first direction in a plan view and two sides extending in a second direction perpendicular to the first direction in a plan view; The semiconductor device according to claim 1 , wherein the inner gate fingers include a first inner gate finger extending in the first direction and a second inner gate finger extending in the second direction.

6. The semiconductor device according to claim 5 , wherein the plurality of sub-regions include four sub-regions, each of the four sub-regions being adjacent to the first inner gate finger and the second inner gate finger in a plan view.

7. the plurality of inner segments includes four inner segments disposed in the four sub-regions, respectively; the plurality of gaps includes four gaps adjacent to the four sub-regions, respectively; 7. The semiconductor device of claim 6, wherein the outer periphery segment is continuous with the four inner segments, and each of the four inner segments is connected to the outer periphery segment through one of the four gaps that is adjacent to a sub-region in which the inner segment is disposed.

8. the plurality of perimeter gate fingers include a first perimeter gate finger and a second perimeter gate finger extending in the first direction, and a third perimeter gate finger and a fourth perimeter gate finger extending in the second direction; the first inner gate finger is connected to the third perimeter gate finger and the fourth perimeter gate finger; The semiconductor device of claim 5 , wherein the second inner gate finger is connected to the first outer perimeter gate finger and the second outer perimeter gate finger.

9. the plurality of inner segments includes first, second, third, and fourth inner segments disposed in the four sub-regions, respectively; the outer circumferential segment is contiguous with the first, second, and third inner segments; each of the first, second, and third inner segments is connected to the outer periphery segment through a gap of the plurality of gaps adjacent to a sub-region in which the inner segment is disposed; The semiconductor device of claim 6 , wherein the fourth inner segment is connected to one of the first, second and third inner segments in the inner region.

10. the gate wiring includes a gate pad, the plurality of perimeter gate fingers include a first perimeter gate finger extending in the first direction, a second perimeter gate finger extending in the second direction, and a third perimeter gate finger including a portion extending in the first direction and a portion extending in the second direction; the first inner gate finger is connected to the second perimeter gate finger; the second inner gate finger is connected to the first perimeter gate finger and to the third perimeter gate finger; The semiconductor device of claim 9 , wherein the gate pad is connected to the third outer perimeter gate finger.

11. a rectangular outer edge of the inner region has two sides extending in a first direction in a plan view and two sides extending in a second direction perpendicular to the first direction in a plan view; the plurality of inner gate fingers include a first inner gate finger extending in the first direction, a second inner gate finger extending in the second direction, and a third inner gate finger extending in the second direction; The semiconductor device of claim 1 , wherein the first inner gate finger intersects with the second inner gate finger and the third inner gate finger.

12. 12. The semiconductor device according to claim 11, wherein the plurality of subregions include six subregions, each of the six subregions being adjacent to the first inner gate finger in a planar view and adjacent to the second inner gate finger or the third inner gate finger in a planar view.

13. the plurality of inner segments includes six inner segments disposed in the six sub-regions, respectively; the plurality of gaps includes six gaps adjacent to the six sub-regions, respectively; 13. The semiconductor device of claim 12, wherein the outer periphery segment is continuous with the six inner segments, and each of the six inner segments is connected to the outer periphery segment through one of the six gaps that is adjacent to a sub-region in which the inner segment is located.

14. 13. The semiconductor device of claim 12, wherein one of the six sub-regions is not adjacent to any of the plurality of outer perimeter gate fingers and is adjacent to the first, second, and third inner gate fingers.

15. The semiconductor device according to any one of claims 1 to 14, wherein each of the plurality of gate trenches is arranged so as to intersect with one of the plurality of peripheral gate fingers or one of the plurality of inner gate fingers in a planar view.

16. Further comprising a plurality of gate contact plugs; The semiconductor device according to any one of claims 1 to 14, wherein a gate electrode embedded in each gate trench is connected to one of the plurality of outer gate fingers or one of the plurality of inner gate fingers via at least one of the plurality of gate contact plugs.

17. a rectangular outer edge of the inner region has two sides extending in a first direction in a plan view and two sides extending in a second direction perpendicular to the first direction in a plan view; The semiconductor device of any one of claims 1 to 14, wherein the plurality of gate trenches include a first set of gate trenches and a second set of gate trenches, each of the gate trenches of the first set extending in the first direction in a planar view, each of the gate trenches of the second set extending in the second direction in a planar view, and each of the gate trenches of the first set and the second set intersecting with one of the plurality of peripheral gate fingers in a planar view.

18. 18. The semiconductor device of claim 17, wherein the plurality of gate trenches further include a third set of gate trenches and a fourth set of gate trenches, each of the gate trenches of the third set extending in the first direction in a plan view, each of the gate trenches of the fourth set extending in the second direction in a plan view, and each of the gate trenches of the third set and the fourth set intersecting with one of the inner gate fingers in a plan view.

19. the first and second sets of gate trenches are disposed across the inner region and the outer periphery region, 20. The semiconductor device of claim 18, wherein the third and fourth sets of gate trenches are disposed entirely within the inner region.

20. A plurality of field plate contact plugs are further included, a field plate electrode embedded in each of the first set of gate trenches includes a first end connected to the outer periphery segment via at least one of the plurality of field plate contact plugs and a second end connected to one of the plurality of inner segments via at least one of the plurality of field plate contact plugs; 20. The semiconductor device of claim 18, wherein a field plate electrode embedded in each of the third set of gate trenches includes a first end connected to one of the plurality of inner segments via at least one of the plurality of field plate contact plugs, and a second end connected to another one of the plurality of inner segments via at least one of the plurality of field plate contact plugs.