Oxide semiconductor film, thin-film transistor, and electronic device

Abstract

This oxide semiconductor film is provided on a substrate and includes a plurality of crystal grains. The oxide semiconductor film includes indium (In), and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanide elements. The plurality of crystal grains include a crystal grain boundary that is defined when the crystal orientation difference of two adjacent measurement points, as obtained by an electron backscatter diffraction (EBSD) method, exceeds 5°, and the average KAM value as calculated by the EBSD method is 1.0° or greater. The average value of change in the crystal grain boundary orientation as calculated by the EBSD method may be 40° or less.

Description

Oxide semiconductor film, thin film transistor, and electronic device

[0001] One embodiment of the present invention relates to an oxide semiconductor (Poly-OS) film having a polycrystalline structure, a thin film transistor including the Poly-OS film, and an electronic device including the thin film transistor.

[0002] In recent years, development of thin film transistors using oxide semiconductor films as channels has been progressing, instead of silicon semiconductor films using amorphous silicon, low-temperature polysilicon, single-crystal silicon, etc. (see, for example, Patent Documents 1 to 6). Thin film transistors including such oxide semiconductor films can be formed using a simple structure and a low-temperature process, similar to thin film transistors including amorphous silicon films. Furthermore, thin film transistors including oxide semiconductor films are known to have higher field-effect mobility than thin film transistors including amorphous silicon films.

[0003] JP 2021-141338 A JP 2014-099601 A JP 2021-153196 A JP 2018-006730 A JP 2016-184771 A JP 2021-108405 A

[0004] However, the field-effect mobility of a thin film transistor including a conventional oxide semiconductor film is not so high even when a crystalline oxide semiconductor film is used. Therefore, it has been desired to improve the crystalline structure of the oxide semiconductor film used in the thin film transistor and thereby increase the field-effect mobility of the thin film transistor.

[0005] In view of the above problems, an object of one embodiment of the present invention is to provide an oxide semiconductor film having a novel crystal structure. Another object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having the novel crystal structure. Another embodiment of the present invention relates to an electronic device including a thin film transistor.

[0006] An oxide semiconductor film according to one embodiment of the present invention is an oxide semiconductor film provided on a substrate and including a plurality of crystal grains, the oxide semiconductor film including indium (In) and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and a lanthanoid element, the plurality of crystal grains including a grain boundary defined when a difference in crystal orientation between two adjacent measurement points obtained by an electron backscatter diffraction (EBSD) method exceeds 5°, and an average KAM value calculated by the EBSD method is 1.0° or more.

[0007] A thin film transistor according to one embodiment of the present invention includes the oxide semiconductor film as a channel.

[0008] An electronic device according to one embodiment of the present invention includes the thin film transistor.

[0009] 1 is an IPF map in the normal direction (ND direction) to the film surface of an oxide semiconductor film according to one embodiment of the present invention, obtained by crystal orientation analysis using EBSD. FIG. 2 is a schematic cross-sectional view showing the configuration of a thin film transistor according to one embodiment of the present invention. FIG. 3 is a schematic plan view showing the configuration of a thin film transistor according to one embodiment of the present invention. FIG. 4 is a flowchart showing a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention. 1 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 2-2 obtained by crystal orientation analysis using the EBSD method. FIG. 2 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 3-1 obtained by crystal orientation analysis using the EBSD method. FIG. 3 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 3-2 obtained by crystal orientation analysis using the EBSD method. FIG. 4 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 3-3 obtained by crystal orientation analysis using the EBSD method. FIG. 5 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 4-1 obtained by crystal orientation analysis using the EBSD method. FIG. 6 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 4-2 obtained by crystal orientation analysis using the EBSD method.1 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 5-1 obtained by crystal orientation analysis using the EBSD method. 2 is an IPF map in the normal direction (ND direction) to the film surface of the oxide semiconductor film of Example 5-2 obtained by crystal orientation analysis using the EBSD method. 3 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in the oxide semiconductor film of Example 1. 4 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in the oxide semiconductor film of Example 2-1. 5 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in the oxide semiconductor film of Example 2-2. 6 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in the oxide semiconductor film of Example 3-1. 1 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in an oxide semiconductor film of Example 3-2. 2 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in an oxide semiconductor film of Example 3-3. 3 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in an oxide semiconductor film of Example 4-1. 4 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in an oxide semiconductor film of Example 4-2. 5 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in an oxide semiconductor film of Example 5-1. 5 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in an oxide semiconductor film of Example 5-2. 1 is a graph showing a distribution map of all adjacent point orientation changes, a distribution map of KAM values, and a distribution map of grain boundary orientation changes in the oxide semiconductor film of the comparative example, in which an IPF map is obtained in the normal direction (ND direction) to the film surface of the oxide semiconductor film of the comparative example, obtained by crystal orientation analysis using an EBSD method.

[0010] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." For convenience of explanation, the terms "up" and "downward" are used in the description. However, for example, the hierarchical relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the hierarchical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When referring to a pixel electrode above a thin film transistor, the thin film transistor and the pixel electrode may not overlap in a planar view. On the other hand, when referring to a pixel electrode vertically above a thin film transistor, the thin film transistor and the pixel electrode may overlap in a planar view.

[0012] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0013] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0014] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0015] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0016] First Embodiment An oxide semiconductor film according to one embodiment of the present invention will be described with reference to FIG.

[0017] [1. Composition of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment contains indium (In) and at least one or more metal elements (M) other than indium. The composition ratio of the oxide semiconductor film preferably satisfies formula (1) in terms of the atomic ratio of indium and at least one or more metal elements. In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, an oxide semiconductor film having crystallinity can be formed. Furthermore, the crystal structure of the oxide semiconductor film preferably has a bixbyite structure. By increasing the ratio of indium, an oxide semiconductor film having a bixbyite structure can be formed.

[0018]

[0019] The at least one metal element is preferably one or more elements selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid elements.

[0020] The first metal element included in the at least one metal element is preferably gallium. Gallium belongs to the same group 13 as indium, and therefore does not impair the crystallinity of the oxide semiconductor film. That is, even if the oxide semiconductor film contains gallium as the first metal element, it is possible to form an oxide semiconductor film having a bixbyite structure.

[0021] When the first metal element is gallium, the oxide semiconductor film may contain a second metal element (M2) selected from the group consisting of aluminum, yttrium, scandium, and lanthanoid elements. In this case, in the composition ratio of the oxide semiconductor film, the atomic ratio of indium, gallium, and the second metal element preferably satisfies formulas (2), (3), and (4). Because the ratio of the second metal element is lower than the ratio of indium or gallium, the second metal element does not impair the crystallinity of the oxide semiconductor film.

[0022]

[0023]

[0024]

[0025] Although the detailed manufacturing method of the oxide semiconductor film will be described later together with the manufacturing method of a thin film transistor, the oxide semiconductor film can be formed by a sputtering method. The composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target. With a sputtering target having the above-described composition, an oxide semiconductor film without compositional deviation of metal elements can be formed by sputtering. Therefore, the composition of the metal elements (e.g., indium or gallium) of the oxide semiconductor film may be the same as the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor film can be specified based on the composition of the metal elements of the sputtering target. Note that this is not limited to the above because the oxygen contained in the oxide semiconductor film varies depending on the sputtering process conditions, etc.

[0026] The composition of metal elements in the oxide semiconductor film can also be determined by X-ray fluorescence analysis, electron probe microanalyzer (EPMA) analysis, or the like. Furthermore, since the oxide semiconductor film has a polycrystalline structure, the composition of the oxide semiconductor film may be determined by X-ray diffraction (XRD). Specifically, the composition of metal elements in the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained by XRD.

[0027] [2. Crystal Structure of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment has a polycrystalline structure including a plurality of crystal grains. Although the details will be described later, by using a Poly-crystalline Oxide Semiconductor (Poly-OS) technique, an oxide semiconductor film having a novel polycrystalline structure different from conventional oxide semiconductor films can be formed. Therefore, hereinafter, the oxide semiconductor film having a polycrystalline structure according to this embodiment may be referred to as a Poly-OS film to distinguish it from conventional oxide semiconductor films having a polycrystalline structure.

[0028] Each crystal grain in the Poly-OS film may be composed of a plurality of crystallites. The crystallite diameter is not particularly limited, but is preferably 1 nm or more, more preferably 10 nm or more, and further preferably 10 nm or more. The crystallite diameter can be measured by electron beam diffraction, XRD, or the like.

[0029] The crystal structure of the Poly-OS film is not particularly limited, but is preferably a bixbite structure. The crystal structure of the Poly-OS film can be identified by XRD or electron beam diffraction. As shown in formula (1), a Poly-OS film having a bixbite structure can be formed by increasing the proportion of indium in the oxide semiconductor film. Furthermore, gallium belongs to the same group 13 element as indium, and therefore does not prevent the Poly-OS film from having a bixbite structure.

[0030] In the Poly-OS film, the crystal grains may have one type of crystal structure or may have multiple types of crystal structures. When the Poly-OS film has multiple types of crystal structures, one of the multiple types of crystal structures is preferably a bixbyite structure.

[0031] The crystal structure of a Poly-OS film is different from that of a conventional oxide semiconductor film having a polycrystalline structure. Specifically, the inventors have found that crystal grains contained in a Poly-OS film have characteristics different from those contained in conventional oxide semiconductor films. Such characteristics of a Poly-OS film can be measured by electron backscatter diffraction (EBSD). Hereinafter, measurement of an oxide semiconductor film by EBSD will be described.

[0032] [2-1. EBSD Method] The EBSD method is an analytical method in which an object to be measured is irradiated with an electron beam, and electron backscatter diffraction generated on each crystal plane of the crystal structure of the object to be measured is analyzed to measure the crystal structure of a measurement region of the object to be measured. The EBSD method can obtain information such as the crystal grains or crystal orientation of an oxide semiconductor film in the measurement region by analyzing data obtained from an EBSD detector attached to a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0033] [2-2. IPF Map] An IPF (Inverse Pole Figure) map is an image in which the crystal orientation relative to the normal direction of the surface of a substrate (or the surface of an oxide semiconductor film formed on a substrate) is classified according to a predetermined index. Generally, the crystal orientation relative to the normal direction of the substrate surface is color-coded according to a color key. Measurement using the EBSD method can acquire information on the crystal orientation, and therefore an IPF map can be created based on the acquired information on the crystal orientation.

[0034] [2-3. Crystal Grains] A crystal grain is a crystalline region surrounded by a crystal grain boundary. Since EBSD provides information about the crystal orientation, a crystal grain boundary can be defined based on the crystal orientation. Generally, when the difference in crystal orientation between two adjacent measurement points exceeds 5°, it is defined that a crystal grain boundary exists between the two measurement points. Therefore, the above definition also applies to Poly-OS films.

[0035] [2-4. Grain size] The grain size is a value indicating the size of a grain. Since the EBSD method can calculate the area S of a grain, the diameter of a circle corresponding to the area S is defined as the grain size d.

[0036] [2-5. Average Crystal Grain Size] The average crystal grain size is the average value of the crystal grain sizes of a plurality of crystal grains. Since a Poly-OS film contains a plurality of crystal grains, the Poly-OS film can be evaluated using the average crystal grain size. Average crystal grain size d ＡＶＥ is calculated by the formula (2).ｊ is the area ratio of the jth grain (the ratio of the area of ​​the grain to the area of ​​the entire EBSD measurement area (measurement area)), and d ｊ is the grain size of the jth grain, and N is the number of grains. As shown in equation (2), the average grain size d ＡＶＥ is the area average within the measurement area weighted by the area of ​​the grains. ＡＶＥ When the crystal grain size is large, it can be said that many crystal grains with large grain sizes are present in the oxide semiconductor film.

[0037]

[0038] The average crystal grain size of the plurality of crystal grains included in the Poly-OS film is, for example, 0.1 μm or more, preferably 0.3 μm or more, and further preferably 0.5 μm or more.

[0039] [2-6. KAM Value] The KAM (Kernel Average Misorientation) value is the average value of the crystal orientation misorientation between one measurement point within a crystal grain and all measurement points adjacent to that measurement point. The KAM value is calculated based on two adjacent measurement points within a crystal grain. Therefore, the crystal orientation misorientation between two adjacent measurement points across a grain boundary is excluded from the calculation of the KAM value.

[0040] The KAM value is a value that represents the change in crystal orientation within a crystal grain. As mentioned above, if the crystal orientation difference exceeds 5°, it is considered to be a crystal grain boundary, so the KAM value ranges from 0° to 5°. A large KAM value means that the local change in crystal orientation within the crystal grain is large, and the crystal grain is highly distorted.

[0041] The average KAM value can be calculated based on the distribution chart of the KAM values. The average KAM value represents one of the properties of crystal grains contained in the Poly-OS film. A large average KAM value means that the Poly-OS film has a large change in crystal orientation and contains many crystals with large strain. The average KAM value of the Poly-OS film is 0.8° or more, preferably 1.0° or more, and more preferably 1.2° or more.

[0042] [2-7. Grain Boundary Orientation Change] The grain boundary orientation change is the difference in crystal orientation between two adjacent measurement points across a grain boundary. In other words, the grain boundary orientation change corresponds to the crystal orientation difference excluded from the calculation of the KAM value.

[0043] The grain boundary orientation change is a value that represents the change in crystal orientation at the grain boundary. As mentioned above, at the grain boundary, the crystal orientation difference exceeds 5°, so the grain boundary orientation change is in the range of more than 5°. A large grain boundary orientation change means that the change in crystal orientation between two adjacent crystal grains at the grain boundary is large, and the degree of coincidence of the crystal orientations of the two adjacent crystal grains at the grain boundary is low. In other words, a large grain boundary orientation change means that the lattice coherence is low and there is a grain boundary with many defects. Conversely, a small grain boundary orientation change means that the lattice coherence at the grain boundary is high and there is a grain boundary with few defects. Here, lattice coherence is defined as the degree of coincidence of the lattice constant and crystal orientation between two crystal grains.

[0044] The average value of the grain boundary orientation change can be calculated based on the distribution map of the grain boundary orientation change. The average value of the grain boundary orientation change represents one of the properties of the crystal grains contained in the Poly-OS film. A small average value of the grain boundary orientation change means that the Poly-OS film has high lattice matching and contains many grain boundaries with few defects. In the Poly-OS film, the average value of the grain boundary orientation change is 40° or less, preferably 39° or less, and more preferably 38° or less.

[0045] [2-8. Crystal Orientation Analysis of Oxide Semiconductor Film by EBSD Method] As described above, by using the EBSD method, it is possible to obtain information about the crystal structure of the oxide semiconductor film, in particular, about the crystal orientation of crystal grains included in the oxide semiconductor film. Therefore, the crystal orientation analysis of the oxide semiconductor film according to this embodiment, that is, the Poly-OS film, by the EBSD method will be described with reference to FIG.

[0046] 1 shows an IPF map representing the crystal orientation in the normal direction (ND direction) to the film surface of an oxide semiconductor film according to one embodiment of the present invention, obtained by crystal orientation analysis using the EBSD method. Note that the IPF map of the Poly-OS film shown in FIG. 1 is one example, and further examples of Poly-OS films will be described later. Details of the conditions for the EBSD method will be described in the examples below, and therefore will not be described here.

[0047] In the IPF map shown in Fig. 1, the crystal orientation of each measurement point in the normal direction (ND direction) to the film surface of the Poly-OS film is classified according to the index shown in Fig. 1, and the grain boundaries are indicated by black lines. That is, the crystal orientation of each measurement point in the ND direction is classified based on the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111>. In Fig. 1, when the difference in crystal orientation between two adjacent measurement points exceeds 5°, it is determined that a crystal grain boundary exists between the two adjacent measurement points, and a black line is drawn between the two adjacent measurement points.

[0048] Here, the crystal orientation <001> represents

[001] and its equivalents

[100] and

[010] . The crystal orientation <101> represents

[101] and its equivalents

[110] and

[011] . The crystal orientation <111> represents

[111] . Furthermore, in each orientation, "1" may be "-1" and is considered to be an axis equivalent to each orientation.

[0049] In addition to <001>, <101>, and <111>, other crystal orientations include <hk0> (h≠k, h and k are natural numbers), <hhl> (h≠l, h and l are natural numbers), and <hkl> (h≠k≠l, h, k, and l are natural numbers).

[0050] As shown in FIG. 1 , the Poly-OS film includes multiple crystal grains surrounded by black lines. Multiple crystal orientations can be observed within a single crystal grain. That is, the crystal orientation of the crystal grains in the Poly-OS film changes within the crystal grain. For example, the crystal orientations <001> and <111> are measured near the center of the crystal grain, and change to the crystal orientation <101> from near the center toward the grain boundary. Furthermore, the same crystal orientation can be observed near the grain boundary, and the deviation of the crystal orientation in the direction perpendicular to the film surface at the grain boundary is extremely small. This means that the lattice coherence is high and there are few defects at the grain boundary of the Poly-OS film. When the lattice coherence is high across the grain boundary, the crystal orientation normal to the film surface is, for example, the crystal orientation <101> or the crystal orientation <111>. That is, the crystal orientation normal to each film surface at two adjacent measurement points sandwiching a grain boundary is 15° or less from the crystal orientation <101>, preferably 10° or less from the crystal orientation <101>. Alternatively, the crystal orientation normal to each film surface at two adjacent measurement points sandwiching a grain boundary is 15° or less from the crystal orientation <111>, preferably 10° or less from the crystal orientation <111>.

[0051] Furthermore, when the crystal orientation difference between two adjacent measurement points across a grain boundary is 15° or less, the lattice matching across the grain boundary can be said to be high. In a Poly-OS film, when the crystal orientation difference between two adjacent measurement points exceeds 5°, the area between the two measurement points is defined as a crystal grain boundary. However, many regions are included in which the crystal orientation difference between the two adjacent measurement points is 15° or less. Therefore, in a distribution diagram of the crystal orientation change of the Poly-OS film, the peak of the crystal orientation difference may appear at 15° or less.

[0052] The crystal orientation of crystal grains in a Poly-OS film changes significantly within the crystal grain. Furthermore, in a Poly-OS film, the crystal orientation changes within adjacent crystal grains so that lattice matching at the grain boundaries is improved. These characteristics are quantified: the average KAM value of the Poly-OS film is 0.8° or more, and the average change in grain boundary orientation is 40° or less. These characteristics of the Poly-OS film are completely different from those of conventional oxide semiconductor films. Thus, the inventors have discovered a Poly-OS film with a novel crystal structure through trial and error.

[0053] As described above, the oxide semiconductor film according to one embodiment of the present invention, i.e., the Poly-OS film, has a novel crystal structure. The Poly-OS film has high lattice matching and few defects at the grain boundaries, which suppresses grain boundary scattering and improves bulk mobility. Therefore, in a thin film transistor including the Poly-OS film as a channel, grain boundary scattering is suppressed and field-effect mobility is improved.

[0054] 2 to 11, a thin film transistor 10 according to one embodiment of the present invention will be described. The thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a memory circuit.

[0055] [1. Configuration of Thin Film Transistor 10] The configuration of a thin film transistor 10 according to one embodiment of the present invention will be described with reference to Figures 2 and 3. Figure 2 is a schematic cross-sectional view showing the configuration of a thin film transistor 10 according to one embodiment of the present invention. Figure 3 is a schematic plan view showing the configuration of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 2 is a cross-sectional view taken along line AA' in Figure 3.

[0056] As shown in FIG. 2 , the thin film transistor 10 includes a substrate 100, a light-shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203. The light-shielding layer 105 is provided on the substrate 100. The first insulating layer 110 covers the upper surface and end surfaces of the light-shielding layer 105 and is provided on the substrate 100. The second insulating layer 120 is provided on the first insulating layer 110. The oxide semiconductor layer 140 is provided on the second insulating layer 120. The gate insulating layer 150 covers the upper surface and end surfaces of the oxide semiconductor layer 140 and is provided on the second insulating layer 120. The gate electrode 160 overlaps the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surfaces of the gate electrode 160 and is provided on the gate insulating layer 150. The fourth insulating layer 180 is provided on the third insulating layer 170. The gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 have openings 171 and 173 through which part of the upper surface of the oxide semiconductor layer 140 is exposed. The source electrode 201 is provided on the fourth insulating layer 180 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. Note that hereinafter, when the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrodes 200.

[0057] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with respect to the gate electrode 160. That is, the oxide semiconductor layer 140 includes the channel region CH overlapping with the gate electrode 160, as well as the source region S and the drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has semiconductor properties. The source region S and the drain region D each have conductor properties. Therefore, the electrical conductivities of the source region S and the drain region D are greater than that of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a stacked-layer structure.

[0058] 3 , each of the light-shielding layer 105 and the gate electrode 160 has a constant width in the D1 direction and extends in the D2 direction perpendicular to the D1 direction. In the D1 direction, the width of the light-shielding layer 105 is larger than the width of the gate electrode 160. The channel region CH completely overlaps with the light-shielding layer 105. In the thin-film transistor 10, the D1 direction corresponds to the direction in which a current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0059] The substrate 100 can support each layer constituting the thin film transistor 10. The substrate 100 can be, for example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate. Alternatively, a rigid substrate having no light-transmitting properties, such as a silicon substrate, can also be used. Alternatively, a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used. Impurities may be introduced into the resin substrate in order to improve the heat resistance of the substrate 100. A substrate in which a silicon oxide film or a silicon nitride film is formed on the rigid or flexible substrate described above can also be used as the substrate 100.

[0060] The light-shielding layer 105 can reflect or absorb external light. As described above, the light-shielding layer 105 is provided with an area larger than the channel region CH of the oxide semiconductor layer 140, and therefore can block external light incident on the channel region CH. The light-shielding layer 105 can be made of, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or alloys or compounds thereof. Furthermore, if electrical conductivity is not required, the light-shielding layer 105 does not necessarily need to contain a metal. For example, a black matrix made of a black resin can also be used as the light-shielding layer 105. The light-shielding layer 105 may have a single-layer structure or a multilayer structure. For example, the light-shielding layer 105 may have a multilayer structure of red, green, and blue color filters.

[0061] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (e.g., water) entering from the outside. Each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can be made of, for example, silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon oxynitride (SiN ｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ), aluminum oxide nitride (AlN ｘ O ｙ ), aluminum nitride (AlN ｘ ) is used. Here, silicon oxynitride (SiO ｘ N ｙ ) and aluminum oxynitride (AlO ｘ N ｙ ) are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than oxygen (O) (x>y), respectively. Silicon oxynitride (SiN ｘ O ｙ ) and aluminum oxide nitride (AlN ｘ O ｙ ) is a silicon compound and an aluminum compound containing a smaller ratio of oxygen than nitrogen (x>y). Furthermore, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single-layer structure or a multilayer structure.

[0062] Furthermore, each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarizing function or a function of releasing oxygen by heat treatment. For example, if the second insulating layer 120 has a function of releasing oxygen by heat treatment, oxygen is released from the second insulating layer 120 by the heat treatment performed in the manufacturing process of the thin film transistor 10, and the released oxygen can be supplied to the oxide semiconductor layer 140.

[0063] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof, may be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a multilayer structure.

[0064] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, the gate insulating layer 150 includes silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), aluminum oxide (AlO ｘ ), or aluminum oxynitride (AlO ｘ N ｙ ) is used. The gate insulating layer 150 preferably has a composition close to the stoichiometric ratio. The gate insulating layer 150 also preferably has few defects. For example, the gate insulating layer 150 may be made of an oxide in which no defects are observed when evaluated by electron spin resonance (ESR).

[0065] The oxide semiconductor layer 140 can be the Poly-OS film described in the first embodiment.

[0066] The configuration of the thin-film transistor 10 has been described above. The thin-film transistor 10 described above is a so-called top-gate transistor. Various modifications of the thin-film transistor 10 are possible. For example, if the light-shielding layer 105 is conductive, the thin-film transistor 10 may be configured such that the light-shielding layer 105 functions as a gate electrode, and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin-film transistor 10 is a so-called dual-gate transistor. Furthermore, if the light-shielding layer 105 is conductive, the light-shielding layer 105 may be a floating electrode or may be connected to the source electrode 201. Furthermore, the thin-film transistor 10 may be a so-called bottom-gate transistor in which the light-shielding layer 105 functions as a main gate electrode.

[0067] 4 to 11, a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention will be described. Fig. 4 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention. Figs. 5 to 11 are schematic cross-sectional views showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0068] 4, the method for manufacturing the thin-film transistor 10 includes steps S1010 to S1110. Steps S1010 to S1110 will be described in order below, but the order of the steps may be reversed in the method for manufacturing the thin-film transistor 10. Furthermore, the method for manufacturing the thin-film transistor 10 may include additional steps.

[0069] In step S1010, a light-shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light-shielding layer 105 is patterned using photolithography. A first insulating layer 110 and a second insulating layer 120 are formed on the light-shielding layer 105 (see FIG. 5 ). The first insulating layer 110 and the second insulating layer 120 are formed using CVD. For example, silicon nitride and silicon oxide are formed as the first insulating layer 110 and the second insulating layer 120, respectively. When silicon nitride is used as the first insulating layer 110, the first insulating layer 110 can block impurities diffusing from the substrate 100 side into the oxide semiconductor layer 140. When silicon oxide is used as the second insulating layer 120, the second insulating layer 120 can release oxygen by heat treatment.

[0070] In step S1020, an oxide semiconductor film 145 is formed over the second insulating layer 120 (see FIG. 6 ). The oxide semiconductor film 145 is formed by a sputtering method. The thickness of the oxide semiconductor film 145 is, for example, 10 nm to 100 nm, preferably 15 nm to 70 nm, and more preferably 15 nm to 40 nm.

[0071] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order for the oxide semiconductor layer 140 to have a uniform polycrystalline structure in the substrate plane, the oxide semiconductor film 145 is preferably amorphous after deposition and before heat treatment. Therefore, the deposition conditions for the oxide semiconductor film 145 are preferably such that the oxide semiconductor layer 140 immediately after deposition is as little crystallized as possible. When the oxide semiconductor film 145 is deposited by a sputtering method, the oxide semiconductor film 145 is deposited while controlling the temperature of the deposition target (the substrate 100 and the layer formed on the substrate 100) to 100° C. or lower, preferably 80° C. or lower, and more preferably 50° C. or lower. The oxide semiconductor film 145 is deposited under a low oxygen partial pressure condition. The oxygen partial pressure is 2% to 20%, preferably 3% to 15%, and more preferably 3% to less than 10%.

[0072] In step S1030, the oxide semiconductor film 145 is patterned (see FIG. 7 ). The oxide semiconductor film 145 is patterned by photolithography. The oxide semiconductor film 145 may be etched by wet etching or dry etching. In the wet etching, an acidic etchant may be used. Examples of the etchant that may be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide, and hydrofluoric acid.

[0073] In step S1040, heat treatment is performed on the oxide semiconductor film 145. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing." In OS annealing, the oxide semiconductor film 145 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or higher and 500° C. or lower, preferably 350° C. or higher and 450° C. or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, preferably 30 minutes or higher and 60 minutes or lower. By the OS annealing, the oxide semiconductor film 145 is crystallized, and the oxide semiconductor layer 140 having a polycrystalline structure (i.e., the oxide semiconductor layer 140 including a Poly-OS film) is formed.

[0074] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see FIG. 8 ). The gate insulating layer 150 is formed using a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm. After the gate insulating layer 150 is formed, a process of introducing oxygen into a part of the gate insulating layer 150 may be performed.

[0075] In step S1060, a heat treatment is performed on the oxide semiconductor layer 140. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing." When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are generated on the top surface and side surfaces of the oxide semiconductor layer 140. When the oxidation annealing is performed, oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, and the oxygen defects are repaired.

[0076] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see FIG. 9). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned using photolithography.

[0077] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see FIG. 9 ). The source region S and the drain region D are formed by ion implantation. Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask. Examples of the implanted impurities include argon (Ar), phosphorus (P), and boron (B). In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen vacancies are generated by the ion implantation, and hydrogen is trapped in the generated oxygen vacancies. This reduces the resistance of the source region S and the drain region D. On the other hand, in the channel region that overlaps with the gate electrode 160, impurities are not implanted, so no oxygen vacancies are generated and the resistance of the channel region CH does not decrease.

[0078] In the thin-film transistor 10, impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150, and therefore the gate insulating layer 150 may also contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0079] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see FIG. 10 ). The third insulating layer 170 and the fourth insulating layer 180 are formed using a CVD method. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the fourth insulating layer 180 is also 50 nm or more and 500 nm or less.

[0080] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 (see FIG. 11 ). By forming the openings 171 and 173, the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0081] In step S1110, a source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171, and a drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a single conductive film that has been deposited. Through the above steps, the thin film transistor 10 shown in FIG. 2 is manufactured.

[0082] Although the method for manufacturing the thin film transistor 10 has been described above, the method for manufacturing the thin film transistor 10 is not limited to this.

[0083] In the thin film transistor 10 according to this embodiment, the oxide semiconductor layer 140 includes a Poly-OS film having a novel crystal structure. The Poly-OS film has high lattice matching and contains many crystal grain boundaries with few defects, which suppresses grain boundary scattering. As a result, the field-effect mobility of the thin film transistor 10 is improved.

[0084] Third Embodiment An electronic device according to a third embodiment of the present invention will be described with reference to FIG.

[0085] FIG. 12 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Specifically, FIG. 12 shows a smartphone, which is an example of the electronic device 1000. The electronic device 1000 includes a display device 1100 with curved sides. The display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit, a drive circuit, and the like. The pixel circuit and the drive circuit include the thin-film transistor 10 described in the second embodiment. The thin-film transistor 10 has high field-effect mobility, which improves the responsiveness of the pixel circuit and the drive circuit, and as a result, can improve the performance of the electronic device 1000.

[0086] The electronic device 1000 according to this embodiment is not limited to a smartphone. The electronic device 1000 also includes electronic devices having a display device, such as a watch, a tablet, a laptop computer, a car navigation system, or a television. The thin-film transistor 10 described in the first embodiment can be applied to any electronic device, regardless of whether or not it has a display device.

[0087] The Poly-OS film will be described in more detail based on the fabricated samples.

[0088] [1. Sample Fabrication] For the samples described below, oxide semiconductor films were fabricated on substrates using a sputtering process and an OS annealing process. In the sputtering process, a sputtering target containing indium (In) and gallium (Ga) as the first metal element (M1) in the sintered body was used in both the examples and the comparative examples. The atomic ratio of indium to all metal elements contained in the sintered body was 70%. In both samples, the chemical composition of the oxide semiconductor film after the OS annealing process was similar to that of the sputtering target. The first metal element (M1) contained in the sintered body of the examples is not limited to gallium (Ga). Aluminum (Al), yttrium (Y), scandium (Sc), and lanthanoid elements also exhibit similar effects.

[0089] [Example 1] SiO as an undercoat film ｘAn oxide semiconductor film having a thickness of 30 nm was formed by a sputtering process on the glass substrate on which the oxide semiconductor film had been formed. The oxygen partial pressure during film formation was 5%, and the substrate temperature during film formation was controlled to be 100°C or lower. The formed oxide semiconductor film was then subjected to an OS annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled between 350°C and 450°C, and the ultimate temperature was maintained for 60 minutes.

[0090] Example 2 A laminated film (AlO ｘ / SiO ｘ ) was formed. An oxide semiconductor film was formed to a thickness of 30 nm on a glass substrate on which an underlayer film had been formed by a sputtering process. The oxygen partial pressure during film formation was 5%, and the substrate temperature during film formation was controlled to be 100°C or lower. The formed oxide semiconductor film was then subjected to an OS annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled between 350°C and 450°C, and the ultimate temperature was maintained for 60 minutes ("Example 2-1" and "Example 2-2").

[0091] Example 3 A laminated film (AlO ｘ / SiO ｘ ) was formed. An oxide semiconductor film was formed by a sputtering process on a glass substrate on which an underlayer film had been formed, to a thickness of 30 nm ("Example 3-1"), 25 nm ("Example 3-2"), or 20 nm ("Example 3-3"). The oxygen partial pressure during film formation was 3%, and the substrate temperature during film formation was controlled to be 100°C or lower. The formed oxide semiconductor film was then subjected to an OS annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled between 350°C and 450°C, and the ultimate temperature was maintained for 60 minutes.

[0092] Example 4 A laminated film (AlO ｘ / SiO ｘ) was formed. An oxide semiconductor film was formed to a thickness of 15 nm on a glass substrate on which an underlayer film had been formed by a sputtering process. The oxygen partial pressure during film formation was 3%, and the substrate temperature during film formation was controlled so that the substrate temperature was 100°C or lower. The formed oxide semiconductor film was then subjected to an OS annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled between 350°C and 450°C, and the ultimate temperature was maintained for 60 minutes ("Example 4-1" and "Example 4-2").

[0093] Example 5 A laminated film (AlO ｘ / SiO ｘ ) was formed. Note that before the aluminum oxide film was formed, the silicon oxide film was subjected to a surface treatment by a wet process. After the aluminum oxide film was formed, the aluminum oxide film was either subjected to a surface treatment using plasma ("Example 5-1") or not ("Example 5-2"). An oxide semiconductor film was formed to a thickness of 15 nm by a sputtering process on a glass substrate on which an undercoat film had been formed. The oxygen partial pressure during film formation was 3%, and the substrate temperature during film formation was controlled so that it was 100°C or lower. The formed oxide semiconductor film was then subjected to an OS annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled between 350°C and 450°C, and the ultimate temperature was maintained for 60 minutes.

[0094] Comparative Example: An oxide semiconductor film was formed on a quartz substrate by a sputtering process to a thickness of 50 nm. The oxygen partial pressure during film formation was 10%, and the substrate temperature was not controlled during film formation. The formed oxide semiconductor film was then subjected to an OS annealing process in an air atmosphere. In the annealing process, the ultimate temperature was controlled between 350°C and 450°C, and the ultimate temperature was maintained for 60 minutes.

[0095] The differences in process conditions for each sample are summarized in Table 1.

[0096]

[0097] [2. Crystal Structure Analysis by XRD Method] The crystal structure of the oxide semiconductor film of each sample was analyzed by XRD method. All the oxide semiconductor films were crystalline and had a bixbyite-type crystal structure.

[0098] [3. Crystal Orientation Analysis by EBSD Method] The crystal orientation of the oxide semiconductor film of each sample was analyzed by EBSD method. The measurement conditions for EBSD method are shown in Table 2. The crystal orientation analysis was performed using OIM-Analysis (ver. 7.1) manufactured by TSL Solutions, Inc. The crystal structure file of bixbyite-type structure 14388 from the Inorganic Crystal Structure Database (ICSD: Chemical Information Association) was used to orient the crystal structure. As a result of the measurement and analysis, when the CI value was 0.6 or more, the obtained pattern was sufficiently clear, and it was determined that the crystal orientation was identified as a bixbyite-type structure.

[0099]

[0100] IPF maps in the normal direction (ND direction) to the film surface of the oxide semiconductor films of Example 1, Example 2-1, Example 2-2, Example 3-1, Example 3-2, Example 3-3, Example 4-1, Example 4-2, Example 5-1, Example 5-2, and the comparative example are shown in FIGS. 13 to 22 and 33, respectively. In each IPF map, a grain boundary is indicated by a black line, as it is assumed that a grain boundary exists when the difference in crystal orientation between two adjacent measurement points exceeds 5°. In addition, in FIGS. 13 to 22 and 33, the crystal orientation at each measurement point in the normal direction to the substrate surface (or the surface of the oxide semiconductor film) is classified according to an index. Specifically, the crystal orientation at each measurement point in the normal direction to the substrate surface is classified based on the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111>.

[0101] As shown in FIGS. 13 to 22 and 33 , each oxide semiconductor film includes multiple crystal grains separated by crystal grain boundaries according to the above definition. Multiple crystal orientations can be seen within the crystal grains in FIGS. 13 to 22 . Therefore, the oxide semiconductor films of the examples are Poly-OS films in which the crystal orientation changes within the crystal grains. In particular, in the oxide semiconductor films of the examples shown in FIGS. 16 to 22 , it can be seen that the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111> are included within one crystal grain. That is, it can be seen that at least one crystal grain in the oxide semiconductor films of the examples shown in FIGS. 16 to 22 includes the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111>, and the crystal orientation changes significantly within the crystal grain. On the other hand, in the oxide semiconductor film of the comparative example shown in FIG. 33 , multiple crystal orientations cannot be seen within the crystal grains. Therefore, the oxide semiconductor film of the comparative example is a conventional oxide semiconductor film in which the crystal orientation does not change within the crystal grains. As described above, the oxide semiconductor film of the example and the oxide semiconductor film of the comparative example have the same bixbyite-type crystal structure, but the characteristics of the crystal orientation of the crystal grains contained therein are significantly different between the oxide semiconductor film of the example and the oxide semiconductor film of the comparative example.

[0102] Next, an analysis based on the crystal orientation difference between two adjacent measurement points will be described.

[0103] Graphs showing the distribution of crystal orientation misorientation of the oxide semiconductor films of Example 1, Example 2-1, Example 2-2, Example 3-1, Example 3-2, Example 3-3, Example 4-1, Example 4-2, Example 5-1, Example 5-2, and Comparative Example are shown in FIGS. 23 to 32 and 34, respectively. Each of FIGS. 23 to 32 and 34 shows three graphs: a distribution map of all adjacent point orientation changes (labeled "(A)" in each figure), a distribution map of KAM values ​​(labeled "(B)" in each figure), and a distribution map of grain boundary orientation changes (labeled "(C)" in each figure). The distribution map of all adjacent point orientation changes shows all crystal orientation misorientation between two adjacent measurement points.

[0104] 23 to 32, when the peak near 10° in the distribution map of grain boundary orientation change increases, the peak in the distribution map of KAM values ​​shifts to near 5°. In the distribution maps of grain boundary orientation change in FIGS. 25 to 30, two peaks, including one near 10°, can be confirmed. In addition, in the distribution map of grain boundary orientation change in FIG. 31, a peak can be seen only near 10°. On the other hand, as shown in FIG. 34, no peak can be seen near 10° in the comparative example.

[0105] 23 to 32, the KAM value distribution diagrams clearly show KAM values ​​of 3° or more. Also, according to Figures 25 to 32, KAM values ​​are also present around 5°. On the other hand, in the KAM value distribution diagram of Figure 34, KAM values ​​of 3° or more are hardly observed.

[0106] Here, the ratio of the average value of the grain boundary orientation change to the average value of the KAM value is defined as the grain boundary parameter P ＧＢ The grain boundary parameter P ＧＢ ) = (average value of grain boundary orientation change) / (average value of KAM value)) Grain boundary parameter P ＧＢ is a parameter that represents the ratio of the amount of change in crystal orientation at the grain boundary to the amount of change in crystal orientation within the grain. ＧＢ When the grain boundary parameter P is large, it means that the local change in crystal orientation within the grain is small and the difference in crystal orientation between two adjacent measurement points across the grain boundary is large. ＧＢ The smaller the grain boundary parameter P is and the closer it is to 1, the greater the change in local crystal orientation within the grain, and the higher the lattice matching between two measurement points adjacent to each other across the grain boundary. ＧＢ As the value of σ becomes smaller and approaches 1, the oxide semiconductor film has higher lattice matching and contains more crystal grain boundaries with fewer defects.

[0107] The average KAM value, the average grain boundary orientation change, and the grain boundary parameter P ＧＢ is shown in Table 3.

[0108]

[0109] As shown in Table 3, the average KAM value was 1.0° or more in all of the oxide semiconductor films of the examples. On the other hand, the average KAM value of the oxide semiconductor films of the comparative examples was less than 1.0°. As can be seen from these results, the crystal orientation within the crystal grains hardly changes in the conventional oxide semiconductor film, whereas the crystal orientation within the crystal grains changes significantly in the Poly-OS film.

[0110] As shown in Table 3, the average value of the change in grain boundary orientation in any of the oxide semiconductor films of the Examples was 40° or less. On the other hand, the average value of the change in grain boundary orientation in the oxide semiconductor films of the Comparative Examples was more than 40°. Furthermore, in any of the oxide semiconductor films of the Examples, the grain boundary parameter P ＧＢ was 30 or less. On the other hand, the average value of the change in grain boundary orientation in the oxide semiconductor film of the comparative example was much greater than 30. As can be seen from this result, in a conventional oxide semiconductor film, the lattice matching between two adjacent crystal grains at the grain boundary is low. Therefore, in the conventional oxide semiconductor film, many defects exist at the grain boundary. In contrast, in the Poly-OS film, the crystal orientations in two adjacent crystal grains change so that the lattice matching at the grain boundary is improved. As a result, in the Poly-OS film, the lattice matching at the grain boundary is high and there are few defects.

[0111] [4. Electrical Characteristics] Thin film transistors including the oxide semiconductor films of the above-described Examples were fabricated using the manufacturing method described in the second embodiment, and their electrical characteristics were measured. Table 4 shows the field-effect mobility calculated from the electrical characteristics.

[0112]

[0113] As shown in Table 4, in all thin film transistors, ２ As can be seen from this result, when a Poly-OS film is used for a channel of a thin film transistor, the field-effect mobility is improved.

[0114] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0115] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0116] 10: Thin film transistor, 100: Substrate, 105: Light-shielding layer, 110: First insulating layer, 120: Second insulating layer, 140: Oxide semiconductor layer, 145: Oxide semiconductor film, 150: Gate insulating layer, 160: Gate electrode, 170: Third insulating layer, 171: Opening, 173: Opening, 180: Fourth insulating layer, 200: Source / drain electrode, 201: Source electrode, 203: Drain electrode, 1000: Electronic device, 1100: Display device

Claims

1. An oxide semiconductor film provided on a substrate, the oxide semiconductor film including a plurality of crystal grains, the oxide semiconductor film including indium (In) and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid elements, the plurality of crystal grains including a crystal grain boundary at which the difference in crystal orientation between two adjacent measurement points obtained by EBSD (electron backscatter diffraction) exceeds 5°, and the average KAM value calculated by the EBSD method is 1.0° or greater.

2. The oxide semiconductor film according to claim 1, wherein the average change in grain boundary orientation calculated by the EBSD method is 40° or less.

3. The oxide semiconductor film according to claim 1, wherein the ratio of the average value of the grain boundary orientation change calculated by the EBSD method to the average value of the KAM values ​​(average value of the grain boundary orientation change / average value of the KAM values) is 30 or less.

4. The oxide semiconductor film according to claim 1, wherein a distribution diagram of the change in grain boundary orientation calculated by the EBSD method has a peak at a crystal orientation difference of 15° or less.

5. The oxide semiconductor film according to claim 1, wherein the plurality of crystal grains include a first crystal grain and a second crystal grain adjacent to each other across the crystal grain boundary, the first crystal grain includes a first measurement point of two measurement points adjacent to each other across the crystal grain boundary, and the second crystal grain includes a second measurement point of the two measurement points adjacent to each other across the crystal grain boundary, and the crystal orientation in the normal direction to the film surface of the oxide semiconductor film at each of the first measurement point and the second measurement point is inclined by 15° or less from a crystal orientation <101>.

6. The oxide semiconductor film according to claim 1, wherein the plurality of crystal grains include a first crystal grain and a second crystal grain adjacent to each other across the crystal grain boundary, the first crystal grain includes a first measurement point of two measurement points adjacent to each other across the crystal grain boundary, and the second crystal grain includes a second measurement point of the two measurement points adjacent to each other across the crystal grain boundary, and the crystal orientation in the normal direction to the film surface of the oxide semiconductor film at each of the first measurement point and the second measurement point is inclined by 15° or less from a crystal orientation <111>.

7. The oxide semiconductor film according to claim 1, wherein the crystal orientation of at least one of the plurality of crystal grains in the normal direction to the film surface of the oxide semiconductor film changes from a crystal orientation <111> to a crystal orientation <101> from near the center of the crystal grain toward the crystal grain boundary.

8. The oxide semiconductor film according to claim 1, wherein the crystal orientation of at least one of the plurality of crystal grains in the normal direction to the film surface of the oxide semiconductor film changes from a crystal orientation <001> to a crystal orientation <101> from near the center of the crystal grain toward the crystal grain boundary.

9. The oxide semiconductor film according to claim 1, wherein the oxide semiconductor film contains at least one or more metal elements including the first metal element excluding the indium, and a ratio of the indium to the indium and the at least one or more metal elements is 50% or more.

10. The oxide semiconductor film according to claim 1, wherein the first metal element is gallium, the second metal element (M2) included in the at least one metal element is one metal element selected from the group consisting of aluminum, yttrium, scandium, and the lanthanoid elements, and the atomic ratios of the indium, the gallium, and the second metal element satisfy formulas (1), (2), and (3).

11. The oxide semiconductor film according to claim 1, wherein the crystal structure of the oxide semiconductor film is a bixbyite structure.

12. A thin film transistor comprising the oxide semiconductor film according to any one of claims 1 to 11 as a channel.

13. An electronic device comprising the thin film transistor according to claim 12.