Semiconductor device

Abstract

Provided is a novel semiconductor device. A vertical channel transistor is provided overlapping a capacitive element. A ferroelectric body is used as a dielectric layer of the capacitive element. It is preferable that the ferroelectric body contains hafnium, zirconium, or at least one element that is selected from among group 13 to 15 elements. Using an oxide semiconductor for a semiconductor layer of the vertical channel transistor makes it possible to raise the dielectric breakdown voltage between the source and drain and to reduce the channel length.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Therefore, examples of technical fields related to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, testing methods thereof, and methods of using thereof.

[0004] In recent years, development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories with various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include DRAM, SRAM, and flash memory.

[0005] Furthermore, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics is being actively carried out. For the next generation of ferroelectric memories, ferroelectric HfO ２ Research on ferroelectric hafnium oxide thin films (Non-Patent Document 3), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 4), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) and CMOS using hafnium oxide (Non-Patent Document 5).

[0006] T. S. Boescke, et al, “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al, “Ferroelectricity HfO▲2▼-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016 Jun Okuno, et al., "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2", VLSI 2020 Akira Toriumi, "Ferroelectricity of HfO2 thin film", The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 T. Francois, et al, “Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”, IEDM 2019

[0007] An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device that consumes low power.An object of one embodiment of the present invention is to provide a semiconductor device that has a large storage capacity.

[0008] It should be noted that the problems associated with one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. It should be noted that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. One embodiment of the present invention solves at least one of the problems listed above and other problems.

[0009] One embodiment of the present invention is a semiconductor device that includes a capacitor and a transistor on the capacitor. The capacitor includes a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer. The transistor includes a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, an opening provided in the second insulating layer and the third conductive layer, a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer. The opening overlaps with the second conductive layer, and the first insulating layer includes a ferroelectric.

[0010] Another aspect of the present invention is a semiconductor device having a plurality of stacked layers and a first electrode penetrating the plurality of layers, each of the plurality of layers having a capacitance element and a transistor on the capacitance element, the capacitance element having a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer, the transistor having a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, an opening provided in the second insulating layer and the third conductive layer, a semiconductor layer covering the opening, the third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer, the opening overlapping the second conductive layer, the first insulating layer including a ferroelectric, and the third conductive layer electrically connected to the first electrode.

[0011] The angle formed between the side surface of the second insulating layer and the bottom surface of the second insulating layer at the opening is preferably 45 degrees or more and 90 degrees or less.

[0012] Furthermore, it is preferable that the semiconductor device has a memory retention period of 10 days or more at an environmental temperature of 150°C.

[0013] The second insulating layer may include a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. For example, each of the fourth insulating layer and the sixth insulating layer may include nitrogen and silicon. For example, the fifth insulating layer may include oxygen and silicon. Furthermore, each of the fourth insulating layer and the sixth insulating layer may include hydrogen.

[0014] The semiconductor layer may be, for example, an oxide semiconductor. The semiconductor layer preferably contains at least one of indium and zinc, and oxygen. The first electrode may be configured to include a plurality of conductive layers. The first insulating layer preferably contains hafnium, zirconium, and oxygen. The first conductive layer and the second conductive layer preferably contain titanium and nitrogen.

[0015] According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a small occupation area can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a large storage capacity can be provided.

[0016] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above. The other effects are described below and are not mentioned in this section. Those skilled in the art can derive the other effects from the description in the specification or drawings, etc., and can extract them as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects.

[0017] FIGS. 1A and 1B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 1C and 1D are equivalent circuit diagrams of the semiconductor device. FIGS. 2A to 2C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 3A to 3E are diagrams illustrating a configuration example of a semiconductor device. FIGS. 4A and 4B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 5A and 5B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 6A to 6C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 7A to 7C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 8A to 8C are diagrams illustrating a configuration example of a semiconductor device. FIGS. 9A and 9B are diagrams illustrating a configuration example of a semiconductor device. FIG. 9C is an equivalent circuit diagram of a semiconductor device. FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. FIG. 11 is an equivalent circuit diagram of a semiconductor device. FIG. 12 is a diagram illustrating a configuration example of a semiconductor device. FIG. 13 is an equivalent circuit diagram of a semiconductor device. FIG. 14A is a diagram illustrating an example of a circuit configuration of a memory cell. FIG. 14B is a graph illustrating an example of hysteresis characteristics. FIG. 14C is a timing chart illustrating an example of a method for driving a memory cell. FIGS. 15A to 15C are diagrams illustrating a configuration example of a memory device. FIG. 16A is a diagram illustrating a configuration example of a memory device. FIG. 16B is a schematic diagram of a memory string included in the memory device. FIG. 17A is a diagram illustrating a configuration example of a memory device. FIG. 17B is a schematic diagram of a memory string included in the memory device. FIG. 18 is a diagram illustrating a cross-sectional configuration example of a memory device. FIGS. 19A and 19B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. FIGS. 20A and 20B are perspective views illustrating an example of an electronic component. FIGS. 21A to 21J are diagrams illustrating an example of an electronic device. FIGS. 22A to 22E are diagrams illustrating an example of an electronic device. FIGS. 23A to 23C are diagrams illustrating an example of an electronic device. FIG. 24 is a diagram illustrating an example of a space device.

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0020] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings.

[0021] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in perspective views, top views, etc.

[0022] In drawings and the like, arrows indicating the X direction (direction along the X axis), the Y direction (direction along the Y axis), and the Z direction (direction along the Z axis) may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and no distinction is made between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, the Y direction, and the Z direction are directions that intersect with each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, the Y direction, and the Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0023] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment, in the claims, etc. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment, in the claims, etc.

[0024] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0025] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0026] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0027] In this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0028] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" can be replaced with other terms without using them. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor." Or, the term "conductor" can be changed to the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator." Or, the term "insulator" can be changed to the term "insulating layer" or "insulating film."

[0029] Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a certain point. However, generally, the potential difference between the potential at a certain point and a reference potential (e.g., ground potential) is simply called potential or voltage, and potential and voltage are often used synonymously. For this reason, in this specification and elsewhere, potential may be read as voltage, and voltage may be read as potential, unless otherwise specified.

[0030] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0031] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0032] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the terms "capacitive element," "parasitic capacitance," or "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The term "one of the pair of terminals" can sometimes be referred to as "one terminal" or "first terminal." The term "the other of the pair of terminals" can sometimes be referred to as "the other terminal" or "second terminal." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Alternatively, it may be set to, for example, 1 pF or more and 10 μF or less.

[0033] The functions of the "source" and "drain" of a transistor may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification and the like.

[0034] In this specification and elsewhere, the term "gate" refers to a gate electrode and a part or all of a gate wiring. The gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0035] In this specification and elsewhere, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The source region refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The source electrode refers to a conductive layer including a portion connected to the source region. The source wiring refers to wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0036] In this specification and elsewhere, "drain" refers to a drain region, a drain electrode, and part or all of a drain wiring. A drain region refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. A drain electrode refers to a conductive layer that includes a portion connected to the drain region. A drain wiring refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or another wiring.

[0037] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) field-effect transistors. Furthermore, if the transistors described in this specification and the like are n-channel transistors, the threshold voltage (also referred to as "Vth") of the transistors is greater than 0 V unless otherwise specified. Furthermore, if the transistors described in this specification and the like are p-channel transistors, the threshold voltage (also referred to as "Vth") of the transistors is less than or equal to 0 V unless otherwise specified. Furthermore, unless otherwise specified, the Vth of multiple transistors of the same conductivity type is the same.

[0038] In this specification and the like, unless otherwise specified, off-state current refers to a current (also referred to as a "drain current" or "Id") that flows between the source and drain when the transistor is in an off state (also referred to as a "non-conducting state" or "cut-off state"). Unless otherwise specified, the off-state refers to a state in which the potential difference between the gate and the source (also referred to as a "gate voltage" or "Vg") with respect to the source is lower than the threshold voltage in an n-channel transistor, and a state in which Vg is higher than the threshold voltage in a p-channel transistor. For example, the off-state current of an n-channel transistor may refer to the drain current when Vg is lower than Vth.

[0039] In this specification, the term "leakage current" may be used to mean the same thing as "off-state current." In this specification, the term "off-state current" may refer to, for example, a current that flows between the source and drain of a transistor when the transistor is in an off state.

[0040] In this specification and the like, unless otherwise specified, the on-state current refers to Id when a transistor is in an on state (also referred to as a "conducting state"). Unless otherwise specified, the on state refers to a state in which Vg is equal to or greater than Vth for an n-channel transistor, and a state in which Vg is equal to or less than Vth for a p-channel transistor. For example, the on-state current of an n-channel transistor may refer to the drain current when Vg is equal to or greater than Vth.

[0041] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0042] In this specification and elsewhere, when referring to counting values ​​and measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, unless otherwise specified, and include an error of plus or minus 20%.

[0043] In this specification and the like, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the reference numeral. For example, the conductive layer 242 may be divided into a conductive layer 242a and a conductive layer 242b.

[0044] Embodiment 1 A semiconductor device 10A according to one embodiment of the present invention will be described. The semiconductor device 10A includes a capacitor 110 and a transistor 100 over the capacitor 110. FIG. 1A is a top view of the semiconductor device 10A. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A as viewed from the Y direction. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0045] 1C and 1D show equivalent circuit diagrams of the semiconductor device 10A. In FIGS. 1C and 1D, one of the source and drain of the transistor 100 is electrically connected to a wiring BL, and the other is electrically connected to one electrode of a capacitor 110. The gate of the transistor 100 is electrically connected to a wiring WL. The other electrode of the capacitor 110 is electrically connected to a wiring PL. The semiconductor device 10A functions as a memory circuit (also referred to as a "memory element" or a "memory cell").

[0046] 1C is an equivalent circuit diagram when the capacitance element 110 includes a ferroelectric material, and FIG. 1D is an equivalent circuit diagram when the capacitance element 110 does not include a ferroelectric material.

[0047] 2A is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in FIG. 1A as viewed from the X direction. Also, FIG. 2B is an enlarged view of the portion indicated by the dashed dotted line B1-B2 in FIG. 2A as viewed from the Z direction. Also, FIG. 2C is an enlarged view of the portion indicated by the dashed dotted line B3-B4 in FIG. 2A as viewed from the Z direction.

[0048] The semiconductor device 10A of one embodiment of the present invention includes an insulating layer 153 and conductive layers 151 and 152 formed to be embedded in the insulating layer 153. The conductive layers 151 and 152 can be formed simultaneously using the same material and in the same manufacturing process. Furthermore, it is preferable to use a chemical mechanical polishing (CMP) method or the like to make the positions (positions in the Z direction) of the top surfaces of the insulating layer 153, the conductive layer 151, and the conductive layer 152 coincide or approximately coincide with each other. The CMP treatment reduces unevenness on the sample surface, thereby improving the coverage of the insulating layer and the conductive layer to be formed later.

[0049] In addition, an insulating layer 154 is provided over the insulating layer 153, the conductive layer 151, and the conductive layer 152, and a conductive layer 155 is provided over the insulating layer 154. The conductive layer 151 and the conductive layer 155 have a region where they overlap with each other with the insulating layer 154 interposed therebetween.

[0050] Semiconductor device 10A also has insulating layer 157 on insulating layer 154 and conductive layer 155, insulating layer 158 on insulating layer 157, and insulating layer 159 on insulating layer 158. Insulating layers 157, 158, and 159 may be collectively referred to as insulating layer 156 or spacer layer. Also, semiconductor device 10A has conductive layer 161 on insulating layer 159.

[0051] Furthermore, an opening 162 is provided in conductive layer 161, insulating layer 159, insulating layer 158, and insulating layer 157 in a region overlapping with a portion of conductive layer 155 (see FIGS. 1B and 2A ). Semiconductor device 10A has a semiconductor layer 163 covering opening 162. Semiconductor layer 163 has a region overlapping with the bottom of opening 162 and a region overlapping with a side surface of opening 162. That is, semiconductor layer 163 has a region in contact with insulating layer 156. In FIG. 1B , semiconductor layer 163 has a region in contact with a side surface of insulating layer 157, a region in contact with a side surface of insulating layer 158, and a region in contact with a side surface of insulating layer 159.

[0052] The semiconductor layer 163 has a region in contact with the conductive layer 155 and a region in contact with the conductive layer 161. That is, a part of the semiconductor layer 163 is electrically connected to the conductive layer 155, and another part of the semiconductor layer 163 is electrically connected to the conductive layer 161. The semiconductor layer 163 may have a region that extends beyond an end of the conductive layer 161 (see FIGS. 1A and 2A).

[0053] Furthermore, an insulating layer 164 is provided over the insulating layer 159, the conductive layer 161, and the semiconductor layer 163. A conductive layer 165 is provided over the insulating layer 164. The conductive layer 165 has a region overlapping with the opening 162, and in this region, has regions overlapping with the side surfaces and bottom of the opening 162 with the insulating layer 164 and the semiconductor layer 163 interposed therebetween (see FIGS. 1B, 2A, 2B, and 2C).

[0054] The thickness of the semiconductor layer 163 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less. The thickness of the insulating layer 164 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is sufficient that at least a part of the insulating layer 164 has a region with the above-described thickness.

[0055] Furthermore, an insulating layer 166 is provided on the insulating layer 164. It is preferable that the positions (positions in the Z direction) of the upper surfaces of the conductive layer 165 and the insulating layer 166 are aligned or approximately aligned. For example, by performing a CMP process or the like to align or approximately align the positions (positions in the Z direction) of the upper surfaces of the conductive layer 165 and the insulating layer 166, it is possible to improve the coverage of the insulating layer and the conductive layer that will be formed subsequently.

[0056] Furthermore, an insulating layer 167 is provided over the conductive layer 165 and the insulating layer 166. Furthermore, in a region overlapping with the conductive layer 152, a conductive layer 168 is provided so as to be embedded in part of the insulating layer 167, the insulating layer 166, the insulating layer 164, the conductive layer 161, the insulating layer 159, the insulating layer 158, the insulating layer 157, and the insulating layer 154. The conductive layer 168 is electrically connected to the conductive layer 161 and the conductive layer 152. The conductive layer 168 and the conductive layer 152 function as contact plugs.

[0057] The conductive layer 155 functions as one electrode of the capacitor 110. The conductive layer 151 functions as the other electrode of the capacitor 110. A region of the insulating layer 154 which overlaps with the conductive layer 155 and the conductive layer 151 functions as a dielectric of the capacitor 110.

[0058] The conductive layer 165 and the conductive layer 151 each extend in the Y direction. The conductive layer 165 functions as a wiring WL or a part of the wiring WL, and the conductive layer 151 functions as a wiring PL or a part of the wiring PL. The conductive layer 168 and the conductive layer 152 function as a wiring BL or a part of the wiring BL.

[0059] In a semiconductor device 10A according to one embodiment of the present invention, a transistor 100 and a capacitor 110 overlap each other. By providing the transistor 100 and the capacitor 110 overlapping each other, the area occupied by the semiconductor device 10A can be reduced.

[0060] <Transistor 100> The conductive layer 161 functions as one of the source electrode and the drain electrode of the transistor 100. The conductive layer 155 functions as the other of the source electrode and the drain electrode of the transistor 100. For example, when the conductive layer 161 functions as the drain electrode of the transistor 100, the conductive layer 155 functions as the source electrode of the transistor 100. Note that it can also be said that the conductive layer 161 functions as a wiring BL or a part of the wiring BL.

[0061] The semiconductor layer 163 functions as a semiconductor layer (a semiconductor layer including a channel formation region) in which a channel of the transistor 100 is formed, the insulating layer 164 functions as a gate insulating layer, and the conductive layer 165 functions as a gate electrode. Therefore, it can be said that the transistor 100 is provided in a region including the opening 162.

[0062] The source electrode and drain electrode of the transistor 100 are arranged in the Z direction. That is, the source and drain of the transistor 100 are arranged at different heights. In other words, the source and drain of the transistor 100 are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0063] In a vertical channel transistor according to one embodiment of the present invention, a source electrode and a drain electrode are arranged in the Z direction. That is, a channel formation region, a source region, and a drain region are arranged in the Z direction. The vertical transistor can reduce the area occupied by the transistor 100 compared to a conventional transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane.

[0064] Furthermore, by using vertical channel transistors in a semiconductor device, the area occupied by the semiconductor device can be reduced. By using vertical channel transistors in a semiconductor device, the semiconductor device can be highly integrated. Furthermore, the storage capacity per unit area of ​​a storage device using the semiconductor device can be increased.

[0065] Furthermore, in conventional transistors, the channel length is set by the exposure limit of photolithography. In a vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 156 or 158. Therefore, the channel length of the transistor 100 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 100, thereby improving frequency characteristics. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.

[0066] The channel length L, channel width W, and the like of the transistor 100 will be described in detail later.

[0067] <Capacitor 110> A region where the conductive layer 151 and the conductive layer 155 overlap with each other via the insulating layer 154 functions as the capacitor 110. It is preferable to use a ferroelectric material for the insulating layer 154. A ferroelectric material has a property that polarization occurs inside when an electric field is applied from the outside, and the polarization remains even when the electric field is made zero. Therefore, a capacitor using such a material as a dielectric (also called a "ferroelectric capacitor") can be used to realize a nonvolatile memory element.

[0068] Furthermore, when the capacitance element 110 is made to function as a ferroelectric capacitor, it is preferable to use, as the conductive layers 151 and 155 that are in contact with the insulating layer 154, which is a ferroelectric, a material that easily generates polarization in the insulating layer 154. For example, it is preferable to use titanium nitride for the conductive layers 151 and 155.

[0069] A nonvolatile memory element using a ferroelectric capacitor may be called an “FeRAM” or a “ferroelectric memory.” Materials that can have ferroelectricity will be described in detail later.

[0070] Furthermore, a material with a high relative dielectric constant (also referred to as a "high-k material") may be used for the insulating layer 154. By using a high-k material for the insulating layer 154, the capacitance required for the capacitor 110 can be secured and the insulating layer 154 can be made thick. By making the insulating layer 154 thicker, the withstand voltage between the conductive layer 151 and the conductive layer 155 is increased, and electrostatic breakdown is suppressed. This improves the reliability of the capacitor 110. This improves the reliability of a semiconductor device using the capacitor 110.

[0071] <Constituent Materials of Semiconductor Device> Examples of materials that can be used for the semiconductor device 10A of one embodiment of the present invention will be described.

[0072] [Substrate] When the semiconductor device 10A is provided on a substrate, there are no significant limitations on the material used for the substrate. The material may be determined depending on the purpose, taking into consideration factors such as whether the substrate is light-transmitting or not and its heat resistance to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Semiconductor substrates, flexible substrates, resin substrates, and the like may also be used.

[0073] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0074] Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Other examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are also substrates in which a conductor or a semiconductor is provided on an insulator substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate.

[0075] Examples of materials that can be used for flexible substrates or resin substrates include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofiber.

[0076] By using the above material for the substrate, a lightweight semiconductor device including the transistor 100 can be provided. Furthermore, by using the above material for the substrate, a semiconductor device that is resistant to shocks can be provided. Furthermore, by using the above material for the substrate, a semiconductor device that is less likely to break can be provided.

[0077] Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0078] [Insulating Layer] The insulating layer can be made of an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like. For example, the insulating layer can be made of an insulating material selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like, in a single layer or a stacked layer. Alternatively, a mixture of two or more materials selected from oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

[0079] In this specification and elsewhere, a nitride oxide refers to a material containing more nitrogen than oxygen. An oxynitride refers to a material containing more oxygen than nitrogen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0080] As transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulating layers. By using high-k materials (high dielectric constant materials, materials with a high relative dielectric constant) for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant, such as BST, can be used. On the other hand, for the insulating layer that functions as an interlayer film, a material with a low dielectric constant can be used to reduce the parasitic capacitance that occurs between wirings. Therefore, it is best to select a material depending on the function required for the insulating layer.

[0081] Furthermore, examples of materials with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0082] Furthermore, materials with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin.

[0083] The method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0084] For example, the insulating layer 153 and the insulating layer 167 are preferably formed using an insulating material that is impermeable to impurities. For example, an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Examples of insulating materials that are impermeable to impurities include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.

[0085] By using an insulating material that is impervious to impurities for the insulating layer 153, diffusion of impurities from below the insulating layer 153 can be suppressed, thereby improving the reliability of the transistor 100. That is, the reliability of a semiconductor device including the transistor 100 can be improved. By using an insulating material that is impervious to impurities for the insulating layer 167, diffusion of impurities from above the insulating layer 167 can be suppressed, thereby improving the reliability of the transistor 100. That is, the reliability of a semiconductor device including the transistor 100 can be improved.

[0086] Alternatively, an insulating layer that can function as a planarizing layer may be used as the insulating layer. Examples of materials that function as a planarizing layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimideamide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors thereof. In addition to the above organic materials, low-k materials (low dielectric constant materials, materials with a small relative dielectric constant), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), and the like can also be used. Note that multiple insulating layers made of these materials may be stacked.

[0087] The siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane resin may have an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may also have a fluoro group.

[0088] Alternatively, a three-layer insulating layer (also referred to as "ZAZ") in which aluminum oxide is sandwiched between two layers of zirconium oxide may be used as the insulating layer 154 that functions as a dielectric of the capacitor 110. ZAZ is a material with a high relative dielectric constant, and by using ZAZ as the dielectric of the capacitor 110, the area occupied by the capacitor 110 can be reduced.

[0089] As described above, it is preferable to use a material that can have ferroelectricity as the insulating layer 154 so that the capacitance element 110 functions as a ferroelectric capacitor.

[0090] As a material capable of exhibiting ferroelectricity, it is preferable to use, for example, hafnium oxide. Alternatively, as a material capable of exhibiting ferroelectricity, it is preferable to use zirconium oxide, HfZrO. Ｘ (X is a real number greater than 0. Hereinafter, this will be referred to as "HfZrOx") or other metal oxides may be used. Alternatively, as a material that can have ferroelectricity, a material in which an element J1 (here, the element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide may be used.

[0091] Here, the ratio of the number of hafnium atoms to the element J1 can be set as appropriate. For example, the ratio of the number of hafnium atoms to the number of zirconium atoms may be set to 1:1 or close to 1:1. Alternatively, as a material that can have ferroelectricity, a material in which element J2 (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to zirconium oxide may be used. Furthermore, the ratio of the number of zirconium atoms to the element J2 can be set as appropriate. For example, the ratio of the number of zirconium atoms to the number of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0092] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al １−ａ Sc ａ N ｂ(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1; hereinafter, simply referred to as AlScN), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used. Furthermore, as a material that can have ferroelectricity, a metal nitride having an element M1, an element M2, and nitrogen can be used. Here, the element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc. The element M2 is one or more selected from the group consisting of boron (B), scandium (Sc), yttrium (Y), lanthanides (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), actinides (15 elements from actinium (Ac) to lawrencium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), and chromium (Cr). The ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be set as appropriate. Furthermore, a metal oxide containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, a material that can exhibit ferroelectricity may be a material obtained by adding element M3 to the above-mentioned metal nitride. The element M3 is one or more elements selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Since the above-mentioned metal nitride contains at least a Group 13 element and nitrogen, which is a Group 15 element, the metal nitride may be referred to as a Group 13-15 ferroelectric, a Group 13 nitride ferroelectric, etc.

[0093] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure３ etc. can be used.

[0094] Furthermore, the material capable of exhibiting ferroelectricity may be, for example, a mixture or compound made of a plurality of materials selected from the materials listed above. Alternatively, the material capable of exhibiting ferroelectricity may be a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure or properties of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity or a material that has ferroelectricity.

[0095] As a material that can have ferroelectricity, hafnium oxide or a material containing hafnium oxide and zirconium oxide (typically HfZrOx) is suitable because it can have ferroelectricity even when processed into a thin film of several nm.

[0096] Here, the thickness of the insulating layer 154 is preferably 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, the thickness of the insulating layer 154 is preferably 8 nm to 12 nm.

[0097] Alternatively, aluminum scandium nitride (AlScN) is suitable as a material that can have ferroelectricity because it can be formed by sputtering, and the impurity concentration in the film can be reduced or a dense film can be formed. When aluminum scandium nitride (AlScN) is used as a material that can have ferroelectricity, it is expected to be a highly reliable film.

[0098] Furthermore, the film thickness of the material capable of exhibiting ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, the film thickness is preferably 8 nm to 12 nm. By setting the film thickness of the material capable of exhibiting ferroelectricity as described above, it is possible to achieve a thin film and to exhibit ferroelectricity. By thinning the film, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitor element, and the capacitor element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In other words, it is easy to realize a semiconductor device with a reduced occupation area.

[0099] In this specification, a material that can have ferroelectricity may be referred to as a ferroelectric material. In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0100] Furthermore, when HfZrOx is used as the material that can have ferroelectricity, it is preferable to form the film using the ALD method, particularly the thermal ALD method. Furthermore, when forming a film of a material that can have ferroelectricity using the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons (also referred to as "hydrocarbons" or "HCs") as a precursor. If the material that can have ferroelectricity contains either or both hydrogen and carbon, crystallization of the material that can have ferroelectricity may be inhibited. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. When a material (HfZrOx) containing hafnium oxide and zirconium oxide is used as the material that can have ferroelectricity, the precursor may be HfCl. ４ and / or ZrCl ４On the other hand, a dopant (typically silicon, carbon, or the like) for controlling the polarization state may be added to a material that can have ferroelectricity. In this case, one method for adding carbon as a dopant may be to use a formation method using a material containing hydrocarbon as a precursor.

[0101] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0102] Furthermore, it is preferable that the impurity concentration of the material capable of having ferroelectricity is low. In particular, it is preferable that the concentrations of hydrogen (H) and carbon (C) are low. Specifically, the hydrogen concentration of the material capable of having ferroelectricity is 5×10 ２０ atoms / cm ３ Preferably, 1×10 ２０ atoms / cm ３ The carbon concentration of the material that can have ferroelectricity is preferably 5×10 １９ atoms / cm ３ Preferably, 1×10 １９ atoms / cm ３ The following is more preferred:

[0103] Furthermore, when HfZrOx is used as the material that can have ferroelectricity, it is preferable to use the ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0104] In addition, when a film of a material that can have ferroelectricity is formed using the ALD method, the oxidizing agent is H ２ O or O ３ However, the oxidizing agent for the ALD method is not limited to this. For example, O ２ , O ３ , N ２ O, NO ２ , H ２O and H ２ O ２ It may include one or more selected from the following.

[0105] In particular, a material capable of exhibiting ferroelectricity is preferably one having an orthorhombic crystal structure, since ferroelectricity is exhibited. It should be noted that other crystal structures may be included in addition to the orthorhombic crystal structure. For example, in addition to the orthorhombic crystal structure, the material may have one or more crystal structures selected from cubic, tetragonal, and monoclinic crystal structures. A layer for enhancing crystallinity may be formed before forming the material capable of exhibiting ferroelectricity. For example, when HfZrOx is used as the material capable of exhibiting ferroelectricity, a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium may be used as the layer for enhancing crystallinity.

[0106] Furthermore, when AlScN is used as a material capable of exhibiting ferroelectricity, it is preferable that it has a hexagonal crystal structure. It is also possible to include other crystal structures in addition to the hexagonal crystal structure. For the layer that enhances crystallinity, it is preferable to use a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium.

[0107] The layer for enhancing crystallinity may be formed after forming the material capable of exhibiting ferroelectricity, or the material capable of exhibiting ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.

[0108] [Conductive Layer] Examples of conductive materials that can be used for conductive layers such as various wirings and electrodes that constitute a semiconductor device include metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), and beryllium (Be), alloys containing the above-mentioned metal elements as components, and alloys combining the above-mentioned metal elements.

[0109] For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used. The method for forming the conductive material is not particularly limited, and various formation methods such as vapor deposition, atomic layer deposition (ALD), CVD, sputtering, and spin coating can be used.

[0110] Alternatively, a Cu-X alloy (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive material. A layer formed of a Cu-X alloy can be processed by a wet etching process, thereby reducing manufacturing costs. Alternatively, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.

[0111] In addition, conductive materials that can be used for the conductive layer include conductive materials containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon oxide has been added. Furthermore, conductive materials containing nitrogen, such as titanium nitride, tantalum nitride, and tungsten nitride, can also be used. The conductive layer can also have a stacked structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above-mentioned metal element are appropriately combined.

[0112] For example, the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a titanium nitride layer, a two-layer structure in which a tungsten layer is stacked on a tantalum nitride layer, or a three-layer structure in which a titanium layer, an aluminum layer is stacked on the titanium layer, and a titanium layer is further stacked on the aluminum layer.

[0113] Furthermore, a plurality of conductive layers formed from the above-described conductive materials may be stacked. For example, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined. Alternatively, the conductive layer may have a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

[0114] For example, the conductive layer may have a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen is stacked on a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen is further stacked on top of that. In this case, it is preferable that the side surface of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. Furthermore, for example, a plurality of conductive layers containing at least one of indium and zinc and oxygen may be stacked as the conductive layer.

[0115] Furthermore, when the capacitance element 110 is made to function as a ferroelectric capacitor, it is preferable to use, as the conductive layers 151 and 155 that are in contact with the insulating layer 154, which is a ferroelectric, a material that easily generates polarization in the insulating layer 154. For example, it is preferable to use titanium nitride for the conductive layers 151 and 155.

[0116] [Semiconductor Layer] For the semiconductor layer 163, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. Examples of compound semiconductors that can be used include organic materials having semiconductor properties and metal oxides (also referred to as oxide semiconductors) having semiconductor properties. Note that these semiconductor materials may contain impurities as dopants.

[0117] For example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon may be used for the semiconductor layer 163. As the polycrystalline silicon, for example, low temperature polysilicon (LTPS) may be used.

[0118] A transistor using amorphous silicon for the semiconductor layer 163 can be formed over a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 163 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 163 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0119] The semiconductor layer 163 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0120] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0121] Furthermore, since an oxide semiconductor has a band gap of 2 eV or more, a transistor (also referred to as an "OS transistor") using an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed has an extremely low off-state current. Therefore, the power consumption of a semiconductor device including an OS transistor can be reduced. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in its characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range from room temperature to 200° C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.

[0122] Therefore, even in a memory device that does not use a ferroelectric capacitor as a capacitance element, written data can be retained for a long time. For example, in a typical DRAM, the frequency of refresh operations must be approximately once per 60 msec. However, in a memory device according to one embodiment of the present invention, the frequency of refresh operations can be approximately once per 10 sec, which is 10 times or more or 100 times or more. Note that, with the memory device according to one embodiment of the present invention, the frequency of refresh operations can be set to 1 sec or more and 100 sec or less, preferably 5 sec or more and 50 sec or less.

[0123] Note that in this embodiment and the like, an OS transistor is preferably used as the transistor 100. Since an OS transistor has a high withstand voltage between the source and the drain, the channel length can be shortened. Therefore, the on-state current can be increased. An OS transistor is suitable for a vertical channel transistor.

[0124] Examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0125] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0126] For example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al-Zn oxide, also referred to as "AZO"), indium aluminum zinc oxide (In Indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide), or the like can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like can be used.

[0127] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0128] The metal oxide may contain one or more metal elements with a longer periodicity instead of indium. Alternatively, the metal oxide may contain one or more metal elements with a longer periodicity in addition to indium. The greater the overlap between the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a longer periodicity may improve the field-effect mobility of a transistor. Examples of metal elements with a longer periodicity include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0129] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0130] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0131] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0132] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be realized.

[0133] When an In-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc may be used. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a metal oxide in a range thereof, may be used.

[0134] When an In—Sn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin may be used, for example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a metal oxide in a range thereof may be used.

[0135] When an In-Sn-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of tin may be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of tin is preferably used. For example, the atomic ratios of metal elements may be In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn=6:1:6, Metal oxides having a ratio of In:Sn:Zn=10:1:3, In:Sn:Zn=10:1:6, In:Sn:Zn=10:1:7, In:Sn:Zn=10:1:8, In:Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10, or similar ratios may also be used.

[0136] When an In-Al-Zn oxide is used for a semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of aluminum may be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of aluminum may be used. For example, the atomic ratios of metal elements may be In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:6, Metal oxides having a composition of In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn=10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10, or similar metal oxides may also be used.

[0137] When an In—Ga—Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the sum of the atomic numbers of metal elements contained in the In—Ga—Zn oxide is higher than that of gallium may be used. Furthermore, a metal oxide in which the atomic ratio of zinc is higher than that of gallium is preferably used. For example, the semiconductor layer may have atomic ratios of metal elements of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, or In:Ga:Zn=6:1. :6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides thereof may also be used.

[0138] When an In-M-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium to the sum of the atomic numbers of metal elements contained in the In-M-Zn oxide is higher than the atomic ratio of the element M may be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer may have atomic ratios of metal elements of In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, or In:M:Zn=6:1: Alternatively, metal oxides of In:M:Zn=10:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides of these or similar ratios may be used.

[0139] When an In-M-Zn oxide is used for the semiconductor layer, the atomic ratio of the metal elements may be In:M:Zn = 1:3:2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:3:4 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:0.5 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:1.2 [atomic ratio] or a composition thereabout, In:M:Zn = 1:1:2 [atomic ratio] or a composition thereabout, or In:M:Zn = 4:2:3 [atomic ratio] or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as the element M.

[0140] When a plurality of metal elements are contained as the element M, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned ranges.

[0141] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In-M-Zn oxide is used for the semiconductor layer, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is in the above-mentioned range.

[0142] As described above, by increasing the ratio of the number of indium atoms to the total number of metal element atoms among the main component elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. By using the transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced.

[0143] The composition of the metal oxide can be analyzed by, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0144] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0145] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0146] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which the transistor is held in a state in which an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and the drain potential and the transistor is held at a high temperature is called a Positive Bias Temperature Stress (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate and the transistor is held at a high temperature is called a Negative Bias Temperature Stress (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and a NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0147] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on, and therefore the amount of variation in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0148] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS test can be obtained. Furthermore, when using a metal oxide that contains gallium, it is preferable to make the gallium content lower than the indium content. This allows for a highly reliable transistor to be realized.

[0149] One of the factors that causes the threshold voltage to fluctuate in the PBTS test is defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the defect level density, the more significant the degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0150] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0151] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than that of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In > Ga and Zn > Ga for the semiconductor layer.

[0152] For example, the semiconductor layer of the OS transistor may contain metal elements having an atomic ratio of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn= Examples of the composition include In:Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, and metal oxides thereof having similar ratios can be used.

[0153] The semiconductor layer of an OS transistor preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to a PBTS test can be obtained. Including gallium in the metal oxide can prevent oxygen deficiency (V) in the metal oxide. Ｏ This has the effect of making oxygen vacancy less likely to occur.

[0154] A metal oxide containing no gallium may be used for the semiconductor layer of an OS transistor. For example, In—Zn oxide may be used for the semiconductor layer. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability. Furthermore, a metal oxide containing no gallium or zinc, such as indium oxide, may be used for the semiconductor layer. The use of a metal oxide containing no gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0155] For example, the semiconductor layer can be made of an oxide containing indium and zinc, in which the atomic ratio of the metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or a ratio close to these values.

[0156] Although gallium has been used as a representative example in the description, the present invention can also be applied to a case where element M is used instead of gallium. For the semiconductor layer, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.

[0157] A transistor having high reliability against application of a positive bias can be realized by using a metal oxide having a low content of element M in a semiconductor layer. By applying the transistor to a transistor that requires high reliability against application of a positive bias, a highly reliable semiconductor device can be realized.

[0158] The semiconductor layer may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer may have the same or substantially the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0159] The two or more metal oxide layers included in the semiconductor layer may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a similar composition and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a similar composition provided on the first metal oxide layer can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0160] Alternatively, for example, a stacked structure may be used, which includes a first metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition close thereto, and a second metal oxide layer having an atomic ratio of In:Zn=4:1 or a composition close thereto, which is provided on the first metal oxide layer.

[0161] The semiconductor layer is preferably a crystalline metal oxide layer. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer, the density of defect states in the semiconductor layer can be reduced, and a highly reliable display device can be realized.

[0162] The higher the crystallinity of a metal oxide layer used in a semiconductor layer, the more the density of defect states in the semiconductor layer can be reduced.On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0163] When a metal oxide layer is formed by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the higher the crystallinity of the formed metal oxide layer.Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film formation gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the formed metal oxide layer.

[0164] The semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition. The stacked structure of metal oxide layers with the same composition can be formed using the same sputtering target, for example, which reduces manufacturing costs. For example, the stacked structure of two or more metal oxide layers with different crystallinity can be formed by using the same sputtering target and varying the oxygen flow rate. Note that the two or more metal oxide layers included in the semiconductor layer may have different compositions.

[0165] When an oxide semiconductor is used for the semiconductor layer 163, it is preferable to use a material containing hydrogen for the insulating layers 157 and 159. When the insulating layer containing hydrogen is in contact with the oxide semiconductor, the oxide semiconductor in the region in contact with the insulating layer becomes n-type and can function as a source region or a drain region. For example, a material containing silicon, nitrogen, and hydrogen may be used for the insulating layer. Specifically, silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen may be used.

[0166] The thicknesses of the insulating layers 157 and 159 are preferably 1 nm to 15 nm, more preferably 2 nm to 10 nm, still more preferably 3 nm to 7 nm, and further preferably 3 nm to 5 nm. When an oxide semiconductor is used for the semiconductor layer 163, a region of the semiconductor layer 163 in contact with the insulating layer 157 containing hydrogen and a region of the semiconductor layer 163 in contact with the insulating layer 159 containing hydrogen function as a source region or a drain region. The sizes of the source region and the drain region formed in the semiconductor layer 163 can be controlled by adjusting the thicknesses of the insulating layers 157 and 159.

[0167] The thickness of the insulating layer 158 is preferably 1 nm to 50 nm, more preferably 2 nm to 30 nm, and further preferably 3 nm to 2 nm. By adjusting the thickness of the insulating layer 158, the size of the channel formation region of the semiconductor layer 163 can be controlled.

[0168] The thicknesses of the insulating layers 157 , 158 , and 159 may be set as appropriate depending on the characteristics desired for the transistor 100 .

[0169] Furthermore, it is preferable that the insulating layers 157, 158, and 159 are successively formed without being exposed to the air environment during the formation of the insulating layers 157, 158, and 159. By successively forming the insulating layers 157, 158, and 159 without being exposed to the air environment during the formation of the insulating layers 157, 158, and 159, it is possible to prevent impurities or moisture from the air environment from adhering to the interface between the insulating layers 157 and 158 and the vicinity thereof, and to the interface between the insulating layers 158 and 159 and the vicinity thereof.

[0170] When an oxide semiconductor is used for the semiconductor layer 163, the conductive layer 155 in contact with the semiconductor layer 163 and the conductive layer 161 in contact with the semiconductor layer 163 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0171] On the other hand, it is preferable to use a material in which hydrogen is reduced and which contains oxygen for the insulating layer 158. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Because hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 163, which is an oxide semiconductor, and the insulating layer 158 in which hydrogen is reduced makes it difficult for the semiconductor layer 163 to become n-type. Furthermore, contact between the semiconductor layer 163, which is an oxide semiconductor, and the insulating layer 158 containing oxygen reduces oxygen vacancies in the semiconductor layer 163, thereby stabilizing the characteristics of the transistor 100 and improving its reliability.

[0172] When an oxide semiconductor is used for the semiconductor layer 163, the insulating layer 158 preferably contains excess oxygen. In this specification and the like, "excess oxygen" refers to oxygen that is released by heating. When a material containing excess oxygen is used for the insulating layer 158, a material that is impermeable to oxygen is preferably used for the insulating layers 157 and 159. Examples of the material that is impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, and a nitride of silicon. By using a material that is impermeable to oxygen for the insulating layers 157 and 159, the excess oxygen contained in the insulating layer 158 is less likely to be released to the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure may be used in which an insulating layer containing silicon and oxygen (insulating layer 158) is provided between two insulating layers containing silicon and nitrogen (insulating layer 157 and insulating layer 159).

[0173] Furthermore, by using an oxide semiconductor for the semiconductor layer 163 and using a material containing hydrogen for the insulating layers 157 and 159, hydrogen is supplied to a region of the semiconductor layer 163 in contact with the insulating layer 157 and a region of the semiconductor layer 163 in contact with the insulating layer 159, and each region of the semiconductor layer 163 becomes n-type. Therefore, the region of the semiconductor layer 163 in contact with the conductive layer 161 and the region of the semiconductor layer 163 in contact with the insulating layer 159 function as one of a source (source region) and a drain (drain region). Furthermore, the region of the semiconductor layer 163 in contact with the conductive layer 155 and the region of the semiconductor layer 163 in contact with the insulating layer 157 function as the other of the source (source region) and the drain (drain region).

[0174] In this case, the length of the side surface of the insulating layer 158 as viewed from the X direction or the Y direction becomes the channel length L (channel length L1) (see FIG. 3A). Therefore, the channel length L of the transistor 100 is determined depending on the thickness t of the insulating layer 158. FIG. 3A is an enlarged cross-sectional view of the transistor 100 shown in FIG. 1B. Also, FIGS. 4A and 4B are modified examples of FIG. 3A and correspond to enlarged cross-sectional views of the transistor 100 shown in FIG. 1B.

[0175] Alternatively, the insulating layers 157 and 159 may be formed using a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride or silicon nitride oxide containing very little hydrogen may be used. In this case, the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159 are not made n-type. Therefore, the region of the semiconductor layer 163 in contact with the conductive layer 161 functions as either a source (source region) or a drain (drain region). The region of the semiconductor layer 163 in contact with the conductive layer 155 functions as the other of the source (source region) or the drain (drain region). The region of the semiconductor layer 163 in contact with the insulating layer 158 functions as a channel formation region.

[0176] In this case, the sum of the lengths of the sides of insulating layer 157, insulating layer 158, and insulating layer 159 as viewed from the X direction or the Y direction is channel length L (channel length L2). Therefore, the channel length L of transistor 100 is determined according to the total thickness ts of insulating layer 157, insulating layer 158, and insulating layer 159.

[0177] Alternatively, the insulating layers 157 and 159 may not be provided, and only the insulating layer 158 may be provided so that the insulating layer 158 is in contact with the conductive layer 155 and the conductive layer 161 (see FIG. 4A ). In this case, the length of the side surface of the insulating layer 158 as viewed in the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 100 is determined depending on the thickness t of the insulating layer 158. In the configuration shown in FIG. 4A , the insulating layer 158 may be referred to as the insulating layer 156.

[0178] When an oxide semiconductor is used for the semiconductor layer 163, a material containing hydrogen is used for the insulating layers 157 and 159, and a material containing excess oxygen is used for the insulating layer 158, hydrogen contained in the insulating layers 157 and 159 and excess oxygen contained in the insulating layer 158 are bonded to each other, and sufficient hydrogen is not supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159, making it difficult to make the semiconductor layer 163 n-type. Similarly, sufficient oxygen is not supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.

[0179] To solve this problem, an insulating layer 171 that is impervious to oxygen and nitrogen may be provided between the insulating layers 157 and 158, and an insulating layer 172 that is impervious to oxygen and nitrogen may be provided between the insulating layers 159 and 158 (see FIG. 4B ). The material that is impervious to oxygen and nitrogen can be realized using, for example, silicon nitride. In the configuration shown in FIG. 4B , the insulating layers 157, 171, 158, 172, and 159 may be collectively referred to as the insulating layer 156.

[0180] By using a material that is difficult for oxygen to permeate for the insulating layers 171 and 172, bonding between hydrogen contained in the insulating layers 157 and 159 and excess oxygen contained in the insulating layer 158 is inhibited. Therefore, sufficient hydrogen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159. Similarly, sufficient oxygen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.

[0181] In this case, the sum of the lengths of the sides of the insulating layers 171, 158, and 172 as viewed from the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 100 is determined according to the total thickness tm of the insulating layers 171, 158, and 172.

[0182] In the transistor 100 according to one embodiment of the present invention, the channel length L is determined depending on the thickness of the insulating layer provided between the conductive layer 161 and the conductive layer 155. Therefore, a transistor with a short channel length L can be manufactured with high accuracy. Furthermore, the variation in characteristics among the plurality of transistors 100 is reduced. Therefore, the operation of a semiconductor device including the transistor 100 can be stabilized, and the reliability can be improved. Furthermore, the reduced variation in characteristics increases the degree of freedom in the circuit design of the semiconductor device, and the operating voltage can also be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0183] Although this embodiment shows a structure in which three insulating layers (insulating layer 157, insulating layer 158, and insulating layer 159) are provided between the conductive layer 155 and the conductive layer 161, the number of insulating layers between the conductive layer 155 and the conductive layer 161 is not limited to this. The number of insulating layers between the conductive layer 155 and the conductive layer 161 may be one, two, or four or more.

[0184] Furthermore, in order to improve the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165 formed in the opening 162, the taper angle θ of the side surface of the opening 162, i.e., the taper angle θ of each of the side surfaces of the insulating layer 157, the insulating layer 158, and the insulating layer 159, may be set to 45 degrees or more and 90 degrees or less, preferably 50 degrees or more and 75 degrees or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface and the side surface of the layer (see FIG. 3A).

[0185] Furthermore, because the semiconductor layer 163 is provided in the opening 162, the perimeter of the opening 162 when viewed in the Z direction is the channel width W of the transistor 100 (see FIG. 3B ). The perimeter may be determined, for example, at a position that is half the thickness t (t / 2) or half the thickness ts (ts / 2) of the insulating layer 158. Note that the perimeter at any position of the opening 162 may be the channel width W as needed. For example, the perimeter at the bottom of the opening 162 may be the channel width W, or the perimeter at the top of the opening 162 may be the channel width W.

[0186] In the memory device of one embodiment of the present invention, the channel length L is preferably smaller than at least the channel width W. In one embodiment of the present invention, the channel length L is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W.

[0187] In addition, although the outline (planar shape) of the opening 162 as viewed from the Z direction is shown as a circle in Fig. 3B, this is not limiting. For example, the outline of the opening 162 as viewed from the Z direction may be an ellipse (see Fig. 3C) or a rectangle (see Fig. 3D). Note that Fig. 3D shows a rectangle with rounded corners. In addition, for example, the outline of the opening 162 as viewed from the Z direction may have a shape including one or both of straight and curved portions (see Fig. 3E).

[0188] It is preferable that the opening 162 is minute. For example, the maximum width of the opening 162 as viewed from the Z direction (the maximum diameter if the opening 162 is circular) is preferably 60 nm or less, more preferably 50 nm or less, even more preferably 40 nm or less, and extremely preferably 30 nm or less. The maximum width of the opening 162 as viewed from the Z direction may be 20 nm or less. It is preferable that the minimum width of the opening 162 as viewed from the Z direction (the minimum diameter if the opening 162 is circular) is 1 nm or more, and more preferably 5 nm or more. To form such minute openings 162, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0189] 5A and 5B show an example of a planar layout in which semiconductor devices 10A are arranged in a matrix. Fig. 5A shows a planar layout in which there are regions in which conductive layers 168 and openings 162 (semiconductor devices 10A) are alternately arranged along the X direction, regions in which conductive layers 168 are repeatedly arranged along the Y direction, and regions in which openings 162 (semiconductor devices 10A) are repeatedly arranged along the Y direction. In the planar layout shown in Fig. 5A, the conductive layers 168 and openings 162 overlap when viewed from the X direction.

[0190] FIG. 5B shows a planar layout in which there are regions where conductive layers 168 are repeatedly arranged along the X direction, regions where openings 162 (semiconductor device 10A) are repeatedly arranged along the X direction, regions where conductive layers 168 are repeatedly arranged along the Y direction, and regions where openings 162 (semiconductor device 10A) are repeatedly arranged along the Y direction.

[0191] In the planar layout shown in FIG. 5B , the conductive layer 168 and the opening 162 are disposed at an angle. Also, in FIG. 5B , the conductive layer 161 electrically connecting the conductive layer 168 and the semiconductor device 10A is disposed at an angle. That is, when viewed from the Z direction, the line connecting the center of the conductive layer 168 and the center of the opening 162 is not perpendicular to the X direction or the Y direction. Disposing the conductive layer 168 and the opening 162 at an angle may enable the semiconductor device 10A to be disposed efficiently. This may improve the integration density of the semiconductor device 10A and increase the storage capacity per unit area of ​​a storage device including the semiconductor device 10A.

[0192] <Modification 1> Figures 6A and 6B show a semiconductor device 10B which is a modification of the semiconductor device 10A. Figure 6A is a top view of the semiconductor device 10B. Figure 6B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 6A. Figure 6C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 6A.

[0193] By reducing the area of ​​the bottom of opening 162, it is possible to increase the taper angle θ of the side surface of opening 162 without increasing the area occupied by semiconductor device 10B. By increasing the taper angle θ of the side surface of opening 162, it is possible to improve the coverage of semiconductor layer 163, insulating layer 164, and conductive layer 165.

[0194] Furthermore, when the area of ​​the bottom of the opening 162 is reduced, the conductive layer 165 may become thinner toward the bottom of the opening 162 within the opening 162. Such a shape of the conductive layer 165 may be called "needle-shaped" or "pyramid-shaped."

[0195] <Modification 2> Figures 7A and 7B show a semiconductor device 10C, which is a modification of the semiconductor device 10A. Figure 7A is a top view of the semiconductor device 10C. Figure 7B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 7A. Figure 7C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 7A.

[0196] In the semiconductor device 10C, the side surface of the opening 162 does not have a tapered angle. The side surface of the opening 162 may be vertical or approximately vertical as long as there is no problem with the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165. By making the side surface of the opening 162 vertical or approximately vertical, the area occupied by the transistor 100 can be reduced. Therefore, the area occupied by the semiconductor device including the transistor 100 can be reduced.

[0197] <Modification 3> Figures 8A and 8B show a semiconductor device 10D, which is a modification of the semiconductor device 10C. Figure 8A is a top view of the semiconductor device 10D. Figure 8B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 8A. Figure 8C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 8A.

[0198] 8 has a configuration in which the conductive layer 155 is removed from the semiconductor device 10A. By not providing the conductive layer 155, the manufacturing process of the semiconductor device 10D can be shortened compared to the semiconductor device 10A, thereby improving productivity. Note that in the semiconductor device 10D, a part of the semiconductor layer 163 functions as one electrode of the capacitor 110. Specifically, at the bottom of the opening 162, a region of the semiconductor layer 163 that overlaps with the insulating layer 154 and the conductive layer 151 functions as one electrode of the capacitor 110.

[0199] <Modification 4> Fig. 9A is a cross-sectional view showing a configuration example in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) are electrically connected to one wiring BL (conductive layer 168 and conductive layer 152). Fig. 9B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 9A as viewed from the Y direction. Fig. 9C is an equivalent circuit diagram of the cross-sectional view shown in Fig. 9B.

[0200] The semiconductor device 10Aa is electrically connected to the wiring WLa, the wiring PLa, and the wiring BL. The semiconductor device 10Ab is electrically connected to the wiring WLb, the wiring PLb, and the wiring BL. By configuring two semiconductor devices 10A to be electrically connected to one wiring BL, the area occupied by the semiconductor device including the semiconductor device 10A can be reduced.

[0201] The conductive layer 165 of the semiconductor device 10Aa functions as a part of the wiring WLa. The conductive layer 151 of the semiconductor device 10Aa functions as a part of the wiring PLa. The conductive layer 165 of the semiconductor device 10Ab functions as a part of the wiring WLb. The conductive layer 151 of the semiconductor device 10Ab functions as a part of the wiring PLb.

[0202] Note that when the same potential is supplied to the wirings PLa and PLb, they may be electrically connected to each other.

[0203] Furthermore, the conductive layer 165 extending in the Y direction can be used as the conductive layer 165 of multiple semiconductor devices 10A arranged in the Y direction (see FIG. 9A ). In other words, the conductive layer 165 of the semiconductor device 10Aa may be electrically connected to the conductive layer 165 of another semiconductor device 10Aa arranged in the Y direction.

[0204] Furthermore, the conductive layer 151 extending in the Y direction can be used as the conductive layer 151 of multiple semiconductor devices 10A arranged in the Y direction. In other words, the conductive layer 151 of the semiconductor device 10Aa may be electrically connected to the conductive layer 151 of another semiconductor device 10Aa arranged in the Y direction.

[0205] <Modification 5> By stacking a plurality of semiconductor devices 10A, it is possible to reduce the area occupied by the semiconductor devices 10A. For example, by stacking two semiconductor devices 10A, the area occupied by each semiconductor device 10A can be halved.

[0206] FIG. 10 is a cross-sectional view showing an example of a configuration in which four semiconductor devices 10A (semiconductor device 10A[1], semiconductor device 10A[2], semiconductor device 10A[3], and semiconductor device 10A[4]) are stacked in the Z direction. FIG. 11 is an equivalent circuit diagram of the example stacked configuration shown in FIG. 10. In FIGS. 10 and 11, the semiconductor device 10A formed in the first layer is referred to as semiconductor device 10A[1], the semiconductor device 10A formed in the second layer is referred to as semiconductor device 10A[2], the semiconductor device 10A formed in the third layer is referred to as semiconductor device 10A[3], and the semiconductor device 10A formed in the fourth layer is referred to as semiconductor device 10A[4]. In the present embodiment and the like, the first layer may be referred to as the "first layer," the second layer as the "second layer," the third layer as the "third layer," and the fourth layer as the "fourth layer."

[0207] The semiconductor device 10A[1] is electrically connected to the wiring WL[1], the wiring PL[1], and the wiring BL (see FIG. 11). The semiconductor device 10A[2] is electrically connected to the wiring WL[2], the wiring PL[2], and the wiring BL. The semiconductor device 10A[3] is electrically connected to the wiring WL[3], the wiring PL[3], and the wiring BL. The semiconductor device 10A[4] is electrically connected to the wiring WL[4], the wiring PL[4], and the wiring BL.

[0208] The conductive layer 165 of the semiconductor device 10A[1] is electrically connected to the wiring WL[1]. The conductive layer 165 of the semiconductor device 10A[1] may function as the wiring WL[1] or a part of the wiring WL[1]. The conductive layer 151 of the semiconductor device 10A[1] is electrically connected to the wiring PL[1]. The conductive layer 151 of the semiconductor device 10A[1] may function as the wiring PL[1] or a part of the wiring PL[1].

[0209] The conductive layer 165 of the semiconductor device 10A[2] is electrically connected to the wiring WL[2]. The conductive layer 165 of the semiconductor device 10A[2] may function as the wiring WL[2] or a part of the wiring WL[2]. The conductive layer 151 of the semiconductor device 10A[2] is electrically connected to the wiring PL[2]. The conductive layer 151 of the semiconductor device 10A[2] may function as the wiring PL[2] or a part of the wiring PL[2].

[0210] The conductive layer 165 of the semiconductor device 10A[3] is electrically connected to the wiring WL[3]. The conductive layer 165 of the semiconductor device 10A[3] may function as the wiring WL[3] or a part of the wiring WL[3]. The conductive layer 151 of the semiconductor device 10A[3] is electrically connected to the wiring PL[3]. The conductive layer 151 of the semiconductor device 10A[3] may function as the wiring PL[3] or a part of the wiring PL[3].

[0211] The conductive layer 165 of the semiconductor device 10A[4] is electrically connected to the wiring WL[4]. The conductive layer 165 of the semiconductor device 10A[4] may function as the wiring WL[4] or a part of the wiring WL[4]. The conductive layer 151 of the semiconductor device 10A[4] is electrically connected to the wiring PL[4]. The conductive layer 151 of the semiconductor device 10A[4] may function as the wiring PL[4] or a part of the wiring PL[4].

[0212] 10, a semiconductor device 10A[2] is provided on a semiconductor device 10A[1], a semiconductor device 10A[3] is provided on the semiconductor device 10A[2], and a semiconductor device 10A[4] is provided on the semiconductor device 10A[3]. Each of the semiconductor devices 10A[1] to 10A[4] shown in FIG. 10 has a conductive layer 152 and a conductive layer 168. The conductive layer 168 of each of the semiconductor devices 10A[1] to 10A[4] shown in FIG. 10 is electrically connected via the conductive layer 152 of each of the semiconductor devices 10A[1] to 10A[4].

[0213] 10 , the conductive layer 152 of the semiconductor device 10A[1] is electrically connected to the conductive layer 152 of the semiconductor device 10A[2] via the conductive layer 168 of the semiconductor device 10A[1]. The conductive layer 152 of the semiconductor device 10A[2] is electrically connected to the conductive layer 152 of the semiconductor device 10A[3] via the conductive layer 168 of the semiconductor device 10A[2]. The conductive layer 152 of the semiconductor device 10A[3] is electrically connected to the conductive layer 152 of the semiconductor device 10A[4] via the conductive layer 168 of the semiconductor device 10A[3]. As shown in FIG. 10 , the multiple conductive layers 168 and the multiple conductive layers 152 are electrically connected to each other, thereby functioning as a single electrode extending in the Z direction. In other words, the multiple conductive layers 168 and the multiple conductive layers 152 function as a single wiring BL.

[0214] 10 and 11 , the transistor 100 included in each of the semiconductor devices 10A[1] to 10A[4] is electrically connected to a wiring BL. Specifically, one of the source or the drain of the transistor 100 included in the semiconductor device 10A[1], one of the source or the drain of the transistor 100 included in the semiconductor device 10A[2], one of the source or the drain of the transistor 100 included in the semiconductor device 10A[3], and one of the source or the drain of the transistor 100 included in the semiconductor device 10A[4] are electrically connected to the wiring BL.

[0215] By electrically connecting multiple semiconductor devices 10A to one wiring BL, i.e., by sharing one wiring BL among multiple semiconductor devices 10A, the occupied area of ​​a semiconductor device including the semiconductor device 10A can be reduced. Furthermore, by stacking multiple semiconductor devices 10A in the Z direction, the occupied area of ​​the semiconductor device 10A can be reduced. Therefore, the occupied area of ​​a semiconductor device including the semiconductor device 10A can be further reduced. Furthermore, by stacking multiple semiconductor devices 10A in the Z direction, the storage capacity per unit area of ​​a storage device including the semiconductor device 10A can be increased.

[0216] <Modification 6> By combining Modifications 4 and 5, the area occupied by each semiconductor device 10A can be further reduced.

[0217] Fig. 12 is a cross-sectional view showing an example of a stacked configuration of a plurality of semiconductor devices 10A. Fig. 13 is an equivalent circuit diagram of the example configuration shown in Fig. 12. Note that Figs. 12 and 13 show an example in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) formed on the same plane are set as a group, and the pair of semiconductor devices 10A are stacked in four layers (also referred to as "tiers").

[0218] 12 and 13, the semiconductor device 10Aa included in the first layer is indicated as semiconductor device 10Aa[1], and the semiconductor device 10Ab is indicated as semiconductor device 10Ab[1]. The semiconductor device 10Aa included in the second layer is indicated as semiconductor device 10Aa[2], and the semiconductor device 10Ab is indicated as semiconductor device 10Ab[2]. The semiconductor device 10Aa included in the third layer is indicated as semiconductor device 10Aa[3], and the semiconductor device 10Ab is indicated as semiconductor device 10Ab[3]. The semiconductor device 10Aa included in the fourth layer is indicated as semiconductor device 10Aa[4], and the semiconductor device 10Ab is indicated as semiconductor device 10Ab[4].

[0219] The semiconductor device 10Aa[1] is electrically connected to the wiring WLa[1], the wiring PLa[1], and the wiring BL (see FIG. 13). The semiconductor device 10Ab[1] is electrically connected to the wiring WLb[1], the wiring PLb[1], and the wiring BL. The semiconductor device 10Aa[2] is electrically connected to the wiring WLa[2], the wiring PLa[2], and the wiring BL. The semiconductor device 10Ab[2] is electrically connected to the wiring WLb[2], the wiring PLb[2], and the wiring BL. The semiconductor device 10Aa[3] is electrically connected to the wiring WLa[3], the wiring PLa[3], and the wiring BL. The semiconductor device 10Ab[3] is electrically connected to the wiring WLb[3], the wiring PLb[3], and the wiring BL. The semiconductor device 10Aa[4] is electrically connected to the wiring WLa[4], the wiring PLa[4], and the wiring BL. The semiconductor device 10Ab[4] is electrically connected to the wiring WLb[4], the wiring PLb[4], and the wiring BL.

[0220] 12 and 13, the area occupied by a semiconductor device including the semiconductor device 10A can be further reduced, and the storage capacity per unit area of ​​a storage device including the semiconductor device 10A can be increased.

[0221] <Operation Example of Semiconductor Device 10> Next, an operation example of the semiconductor device 10 (semiconductor device 10A, semiconductor device 10C, and semiconductor device 10D) will be described. Fig. 14A shows an equivalent circuit diagram of the semiconductor device 10. The semiconductor device 10 shown in Fig. 14A functions as a DRAM-type (1Tr1C-type) storage element (memory cell) having one transistor M and one capacitance element Cfe.

[0222] 14A , the transistor M corresponds to the transistor 100, and the capacitance element Cfe corresponds to the capacitance element 110.

[0223] Various semiconductor materials can be used for the semiconductor layer in which the channel of the transistor M is formed. For example, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination as the semiconductor layer in which the channel of the transistor M is formed. Furthermore, for example, silicon or germanium can be used as the semiconductor material. Furthermore, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can also be used.

[0224] In particular, it is preferable to use an OS transistor as the transistor M. An OS transistor has a characteristic of high withstand voltage between the source and drain. Therefore, by using an OS transistor as the transistor M, a high voltage can be applied to the transistor M even when the transistor M is miniaturized. Miniaturizing the transistor M can reduce the area occupied by the semiconductor device 10. For example, the area occupied by one semiconductor device 10 shown in FIG. 14A can be 1 / 3 to 1 / 6 of the area occupied by one cell of a static random access memory (SRAM). Therefore, the semiconductor devices 10 can be arranged at high density. This allows a memory device with a large storage capacity to be realized.

[0225] When an OS transistor is used as a transistor constituting a memory cell, the memory cell can be called an "OS memory." In particular, a DRAM-type OS memory may be called a DOSRAM (registered trademark). Furthermore, an FeRAM using an OS transistor as a transistor constituting a memory cell may be called an FeDOSRAM.

[0226] The wiring WL functions as a word line, and the on / off state of the transistor M can be controlled by controlling the potential of the wiring WL. For example, when the transistor M is an n-channel transistor, the transistor M can be turned on by setting the potential of the wiring WL to a high potential, and the transistor M can be turned off by setting the potential of the wiring WL to a low potential.

[0227] The wiring BL functions as a bit line, and when the transistor M is on, the potential of the wiring BL is supplied to one electrode of the capacitor Cfe.

[0228] The wiring PL functions as a plate line. A potential is supplied to the other electrode of the capacitor Cfe through the wiring PL.

[0229] <Hysteresis Characteristics of Ferroelectric Layer> The ferroelectric layer of the capacitance element Cfe has hysteresis characteristics. Fig. 14B is a graph showing an example of the hysteresis characteristics. In Fig. 14B, the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode of the capacitance element Cfe.

[0230] 14B, the vertical axis represents the polarization of the ferroelectric layer, and a positive value indicates that positive charges are biased toward one electrode of the capacitance element Cfe and negative charges are biased toward the other electrode of the capacitance element Cfe. On the other hand, a negative value indicates that positive charges are biased toward the other electrode of the capacitance element Cfe and negative charges are biased toward one electrode of the capacitance element Cfe.

[0231] The voltage shown on the horizontal axis of the graph in Fig. 14B may be the difference between the potential of the other electrode of the capacitance element Cfe and the potential of one electrode of the capacitance element Cfe. Also, the polarization shown on the vertical axis of the graph in Fig. 14B may be a positive value when positive charges are biased toward the other electrode of the capacitance element Cfe and negative charges are biased toward one electrode of the capacitance element Cfe, and a negative value when positive charges are biased toward one electrode of the capacitance element Cfe and negative charges are biased toward the other electrode of the capacitance element Cfe.

[0232] 14B, the hysteresis characteristic of the ferroelectric layer can be represented by a curve 51 and a curve 52. The voltages at the intersections of the curves 51 and 52 are defined as VSP and −VSP. It can be said that VSP and −VSP have opposite polarities.

[0233] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 51. On the other hand, when a voltage equal to or greater than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 52. Therefore, VSP and -VSP can be referred to as saturation polarization voltages. Note that, for example, VSP may be referred to as the first saturation polarization voltage, and -VSP may be referred to as the second saturation polarization voltage. Also, while FIG. 14B shows a case where the absolute values ​​of the first and second saturation polarization voltages are equal, the absolute values ​​of the two may be different.

[0234] Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 51 and the polarization of the ferroelectric layer is zero. Furthermore, −Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 52 and the polarization of the ferroelectric layer is zero. Vc and −Vc can be referred to as coercive voltages. The values ​​of Vc and −Vc can be said to be values ​​between −VSP and VSP. For example, Vc may be referred to as the first coercive voltage, and −Vc may be referred to as the second coercive voltage. Furthermore, although FIG. 14B shows that the absolute values ​​of the first coercive voltage and the second coercive voltage are equal, the absolute values ​​of the two may be different.

[0235] Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called "residual polarization Pr" and the minimum value is called "residual polarization -Pr". Furthermore, the difference between the remanent polarization Pr and the remanent polarization -Pr is called "residual polarization 2Pr".

[0236] As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be expressed by the difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode of the capacitance element Cfe. Also, as described above, the other electrode of the capacitance element Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be controlled.

[0237] An example of a method for driving the semiconductor device 10 functioning as a memory cell will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitance element Cfe is the potential difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode (wiring PL) of the capacitance element Cfe. The transistor M is an n-channel transistor.

[0238] 14C is a timing chart showing an example of a method for driving the semiconductor device 10. FIG. 14C shows an example of writing and reading binary digital data to the semiconductor device 10. Specifically, FIG. 14C shows an example in which data "1" is written to the semiconductor device 10 from time T01 to time T02, read and rewrite are performed from time T03 to time T05, read and write data "0" to the semiconductor device 10 from time T11 to time T13, read and rewrite are performed from time T14 to time T16, and read and write data "1" to the semiconductor device 10 from time T17 to time T19.

[0239] A reference potential Vref is supplied to the sense amplifier electrically connected to the wiring BL. In the read operation shown in FIG. 14C etc., when the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

[0240] From time T01 to time T02, the potential of the wiring WL is set to a high potential. This turns on the transistor M. Furthermore, the potential of the wiring BL is set to Vw. Since the transistor M is on, the potential of one electrode of the capacitor Cfe becomes Vw. Furthermore, the potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe becomes "Vw-GND." This allows data "1" to be written to the semiconductor device 10. Therefore, the period from time T01 to time T02 can be said to be a period during which a write operation is performed.

[0241] Here, Vw is preferably equal to or greater than VSP, for example. Furthermore, although GND is a ground potential in this specification and the like, it does not necessarily have to be a ground potential as long as the semiconductor device 10 can be driven to satisfy the spirit of one aspect of the present invention. For example, if the absolute values ​​of the first and second saturation polarization voltages are different and the absolute values ​​of the first and second coercive voltages are different, GND can be a potential other than ground.

[0242] From time T02 to time T03, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Since the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe from time T01 to time T02 can be set to VSP or higher, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 52 shown in FIG. 14B from time T02 to time T03. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe from time T02 to time T03.

[0243] After the potentials of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns off the transistor M. This completes the write operation, and data "1" is stored in the semiconductor device 10. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or greater than the second coercive voltage -Vc.

[0244] From time T03 to time T04, the potential of the wiring WL is set to a high potential. This turns on the transistor M. The potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" from time T01 to time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. During polarization reversal, a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in the semiconductor device 10. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may be higher than Vw, for example.

[0245] Because the above read is destructive read, the data "1" held in the semiconductor device 10 is lost. Therefore, from time T04 to time T05, the potential of the wiring BL is set to Vw, and the potential of the wiring PL is set to GND. As a result, the data "1" is rewritten to the semiconductor device 10. Therefore, the period from time T04 to time T05 can be considered a period in which a rewrite operation is performed.

[0246] From time T05 to time T11, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the rewrite operation is completed, and data "1" is held in the semiconductor device 10.

[0247] From time T11 to time T12, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Because data "1" is stored in the semiconductor device 10, the potential of the wiring BL becomes higher than Vref, and the data "1" stored in the semiconductor device 10 is read. Therefore, the period from time T11 to time T12 can be considered a period in which a read operation is performed.

[0248] From time T12 to time T13, the potential of the wiring BL is set to GND. Since the transistor M is on, the potential of one electrode of the capacitor Cfe is set to GND. Also, the potential of the wiring PL is set to Vw. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe is "GND-Vw." This allows data "0" to be written to the semiconductor device 10. Therefore, the period from time T12 to time T13 can be said to be a period during which a write operation is performed.

[0249] From time T13 to time T14, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0 V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe from time T12 to time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to the curve 51 shown in FIG. 14B from time T13 to time T14. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe from time T13 to time T14.

[0250] After the potentials of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns off the transistor M. This completes the write operation, and data "0" is stored in the semiconductor device 10. The potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

[0251] From time T14 to time T15, the potential of the wiring WL is set to a high potential. This turns on the transistor M. The potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" from time T12 to time T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. As a result, the increase in the potential of the wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Specifically, the potential of the wiring BL is equal to or lower than Vref. This allows the bit line driver circuit to read the data "0" stored in the semiconductor device 10. Therefore, the period from time T14 to time T15 can be said to be a period during which a read operation is performed.

[0252] From time T15 to time T16, the potential of the wiring BL is set to GND, and the potential of the wiring PL is set to Vw, thereby rewriting data "0" to the semiconductor device 10. Therefore, the period from time T15 to time T16 can be considered a period in which a rewrite operation is performed.

[0253] From time T16 to time T17, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. Thus, the rewrite operation is completed, and data "0" is held in the semiconductor device 10.

[0254] From time T17 to time T18, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Because data "0" is stored in the semiconductor device 10, the potential of the wiring BL becomes lower than Vref, and the data "0" stored in the semiconductor device 10 is read. Therefore, the period from time T17 to time T18 can be considered a period in which a read operation is performed.

[0255] From time T18 to time T19, the potential of the wiring BL is set to Vw. Because the transistor M is on, the potential of one electrode of the capacitor Cfe is Vw. The potential of the wiring PL is set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitor Cfe is "Vw-GND." This allows data "1" to be written to the semiconductor device 10. Therefore, the period from time T18 to time T19 can be considered a period during which a write operation is performed.

[0256] After time T19, the potentials of the wiring BL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to low. This completes the write operation, and data "1" is held in the semiconductor device 10.

[0257] The semiconductor device 10 using a ferroelectric layer for the capacitance element Cfe functions as a nonvolatile memory element that can retain written information even when the power supply is stopped.

[0258] Furthermore, while a DRAM (Dynamic Random Access Memory) requires periodic refresh operations, which increases power consumption, the semiconductor device 10, which uses a ferroelectric layer for the capacitance element Cfe, does not require refresh operations and therefore can reduce power consumption.

[0259] In this specification and the like, a memory element or memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Therefore, the semiconductor device 10 is both a ferroelectric memory and an FE memory. The FE memory has a capacitance of 1×10 １０ or more, preferably 1×10 １２ or more, more preferably 1×10 １５ Furthermore, the FE memory is expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

[0260] Furthermore, in FE memory, there is a correlation between the remanent polarization 2Pr and data retention capacity, and as the remanent polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remanent polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more at an environmental temperature of 150°C or 200°C.

[0261] The FE memory can also be applied to cache memories and registers of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc. By combining the FE memory with the cache memory and registers of a CPU, a Nomally Off CPU (Noff-CPU) can be realized. By combining the FE memory with the cache memory and registers of a GPU, a Nomally Off GPU (Noff-GPU) can be realized.

[0262] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0263] Second Embodiment In this embodiment, a configuration example of a memory device 300 using the semiconductor device 10 as a memory cell will be described.

[0264] 15A is a block diagram illustrating a configuration example of a memory device 300 according to one embodiment of the present invention. The memory device 300 illustrated in FIG. 15A includes a driver circuit 21 and a memory array 20. The memory array 20 includes a plurality of semiconductor devices 10. FIG. 15A illustrates an example in which the memory array 20 includes a plurality of semiconductor devices 10 arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 2).

[0265] The rows and columns extend in directions perpendicular to each other. In this embodiment, the Y direction is referred to as the "rows" and the X direction is referred to as the "columns," but the Y direction may also be referred to as the "columns" and the X direction as the "rows."

[0266] In FIG. 15A , the semiconductor device 10 in the first row and first column is indicated as semiconductor device 10[1,1], and the semiconductor device 10 in the mth row and nth column is indicated as semiconductor device 10[m,n]. Furthermore, in the present embodiment and the like, an arbitrary row may be referred to as row i. Furthermore, an arbitrary column may be referred to as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. Furthermore, in the present embodiment and the like, the semiconductor device 10 in the ith row and jth column is indicated as semiconductor device 10[i,j]. Furthermore, in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is used, "j+α" is not less than 1 or more than n.

[0267] The memory array 20 also includes m wirings WL extending in the row direction (Y direction), m wirings PL extending in the row direction (Y direction), and n wirings BL extending in the Z direction. Note that although the n wirings BL extend in the Z direction, in order to make it easier to understand the relationship between the wirings WL and PL and the wirings BL, in FIG. 15A the n wirings BL are shown extending in the column direction (X direction).

[0268] In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0269] The plurality of semiconductor devices 10 provided in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of semiconductor devices 10 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0270] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0271] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0272] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0273] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0274] The voltage generating circuit 33 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a voltage.

[0275] The peripheral circuit 41 is a circuit for writing and reading data to and from the semiconductor device 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0276] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the semiconductor device 10, the function of reading data from the semiconductor device 10, the function of holding the read data, etc.

[0277] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the semiconductor device 10. The data (Dout) read from the semiconductor device 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0278] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW22 is controlled by signal PON1, and the on / off of PSW23 is controlled by signal PON2. In FIG. 15A, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0279] The drive circuit 21 and the memory array 20 may be provided on the same plane. Alternatively, as shown in FIG. 15B, a layer including the memory array 20 may be provided directly above a layer including the drive circuit 21. By providing the drive circuit 21 and the memory array 20 in an overlapping manner, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, thereby reducing power consumption and signal delay. Furthermore, the memory device 300 can be made smaller.

[0280] 15B shows one layer of memory array 20 stacked on drive circuit 21, but multiple layers of memory arrays 20 may be stacked on drive circuit 21. Fig. 15C shows an example in which k layers (k is an integer of 2 or more) of memory arrays 20 are stacked on drive circuit 21. In Fig. 15C etc., the memory array 20 provided in the first layer is indicated as memory array 20[1], the memory array 20 provided in the second layer is indicated as memory array 20[2], and the memory array 20 provided in the kth layer is indicated as memory array 20[k].

[0281] 16A is a schematic diagram illustrating an example configuration of a memory device 300. The memory device 300 shown in FIG. 16A has six layers of memory arrays 20 provided on a drive circuit 21. As described above, in FIG. 16A and other figures, the memory array 20 provided in the third layer is indicated as memory array 20[3], the memory array 20 provided in the fourth layer is indicated as memory array 20[4], the memory array 20 provided in the fifth layer is indicated as memory array 20[5], and the memory array 20 provided in the sixth layer is indicated as memory array 20[6].

[0282] The memory arrays 20 in each layer each have a plurality of semiconductor devices 10 arranged in a matrix, and wiring WL and wiring PL extending in the Y direction. To make the drawing easier to understand, the wiring WL and wiring PL of each of the memory arrays 20 in the first to fifth layers are omitted from the drawing.

[0283] 16A also has a plurality of wirings BL extending in the Z direction. The wirings BL are formed through each of the six layers of memory arrays 20 and are electrically connected to the drive circuits 21. When viewed from the Z direction, the plurality of wirings BL are arranged in a matrix.

[0284] By extending the wiring BL in the Z direction and electrically connecting it to the drive circuit 21, the connection distance between the semiconductor device 10 and the drive circuit 21 can be made shorter than when the wiring BL is extended in the X or Y direction. This shortens the signal propagation distance between the semiconductor device 10 and the drive circuit 21, thereby increasing the operating speed of the memory device. Furthermore, the parasitic capacitance associated with the wiring BL is reduced, thereby reducing power consumption.

[0285] In addition, in each memory array 20 in each layer, one of the plurality of semiconductor devices 10 included in the memory array 20 is electrically connected to one of the plurality of wirings BL. Therefore, in the memory device 300 shown in Figure 16A, one semiconductor device 10 from each memory array 20 in each layer is electrically connected to one wiring BL, a total of six semiconductor devices 10.

[0286] A configuration in which multiple memory cells (semiconductor device 10) are electrically connected to one wiring BL is also called a “memory string.” Therefore, it can be said that the memory device 300 shown in FIG. 16A is configured to include multiple memory strings.

[0287] Fig. 16B shows a schematic diagram of a memory string included in the memory device 300 shown in Fig. 16A. To make the drawing easier to understand, the wiring WL and wiring PL electrically connected to the semiconductor device 10 are omitted from the schematic diagram of the memory string shown in Fig. 16B. A part of an equivalent circuit of the memory string is also shown in Fig. 16B.

[0288] Fig. 17A is a schematic diagram illustrating an example of the configuration of a storage device 300. The storage device 300 shown in Fig. 17A is a modified example of the storage device 300 shown in Fig. 16A. Therefore, to reduce repetition of explanation, differences from the storage device 300 shown in Fig. 16A will be mainly described.

[0289] 17A differs from the memory device 300 shown in Fig. 16A in that, in each memory array 20 on each layer, two of the plurality of semiconductor devices 10 included in the memory array 20 are electrically connected to one of the plurality of wirings BL. In other words, a total of 12 semiconductor devices 10 are electrically connected to one wiring BL.

[0290] Fig. 17B is a schematic diagram of a memory string included in the memory device 300 shown in Fig. 17A. A part of an equivalent circuit of the memory string is also shown in Fig. 17B.

[0291] 17A, the number of wirings BL can be reduced compared to the memory device 300 shown in FIG. 16A. Therefore, the area occupied by the memory device 300 is reduced.

[0292] The semiconductor device 10 according to one embodiment of the present invention is an FE memory, which can retain written data for a long period of time even when power supply is stopped. Furthermore, since the semiconductor device 10 does not require a refresh operation that is required for a DRAM, the semiconductor device 10 can achieve a low-power consumption memory device 300.

[0293] [Configuration Example of Semiconductor Device] FIG. 18 shows a cross-sectional configuration example of a memory device 300 according to one embodiment of the present invention. The memory device 300 shown in FIG. 18 has k memory arrays 20 above a driver circuit 21. In FIG. 18, the configurations shown in FIGS. 11 and 17 are illustrated as examples of the k memory arrays 20. To reduce repetition of the description, the description of the k memory arrays 20 will be omitted here.

[0294] 18 illustrates a transistor 400 included in the driver circuit 21. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 400 may be a p-channel transistor or an n-channel transistor. The substrate 311 may be, for example, a single-crystal silicon substrate.

[0295] Here, in the transistor 400 shown in FIG. 18 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described, a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0296] Note that the transistor 400 illustrated in FIG. 18 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0297] Between each structure, a wiring layer including an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0298] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328, a conductive layer 330, and the like that are electrically connected to the conductive layer 152 are embedded in the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. Note that the conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0299] The insulating layer 322 may be formed on a surface of the insulating layer 322 by a CMP process or the like to improve the flatness of the insulating layer 322.

[0300] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 18 , an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a contact plug or a wiring. The conductive layer 356 is electrically connected to the conductive layer 152.

[0301] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0302] Embodiment 3 In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0303] The metal oxide used in the OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, antimony, and tin, and more preferably gallium.

[0304] The metal oxide can be formed by a sputtering method, a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method, or an atomic layer deposition (ALD) method.

[0305] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0306] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0307] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0308] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0309] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0310] [Structure of Oxide Semiconductor] Note that oxide semiconductors may be classified differently from the above when focusing on their structure. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0311] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0312] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0313] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0314] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0315] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31 degrees in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type, composition, and the like of the metal elements constituting the CAAC-OS.

[0316] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the observed spots are at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0317] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0318] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0319] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities and / or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0320] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0321] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0322] [Structure of Oxide Semiconductor] Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0323] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0324] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0325] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0326] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0327] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0328] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0329] The CAC-OS can be formed by sputtering, for example, without intentionally heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0330] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0331] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0332] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0333] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0334] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0335] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0336] <OS Transistor> By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. Furthermore, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.

[0337] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ or less, more preferably 1 × 10 １５ cm −３ or less, more preferably 1 × 10 １３ cm −３or less, more preferably 1 × 10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0338] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0339] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0340] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0341] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0342] Furthermore, in a Si transistor (a transistor using silicon in a semiconductor layer in which a channel is formed), a short channel effect (also referred to as SCE) occurs as the transistor is miniaturized. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0343] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0344] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0345] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0346] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0347] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation.

[0348] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0349] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0350] <Impurities in OS> Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0351] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0352] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0353] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Less than.

[0354] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0355] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0356] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0357] 19A and 19B , an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0358] As shown in FIG. 19A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0359] 19B, the chip 1200 is provided with bumps (not shown), which are connected to a first surface of a package substrate 1201. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, which are connected to a motherboard 1203.

[0360] The motherboard 1203 may be provided with a storage device such as a storage device 1221 and a flash memory 1222. For example, the semiconductor device 10 may be used as the storage device 1221. Furthermore, for example, the semiconductor device 10 may be used instead of the flash memory 1222.

[0361] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The semiconductor device 10 may be used for this memory. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate operation circuit using an oxide semiconductor, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0362] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0363] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0364] The memory controller 1214 has a circuit that functions as a controller for the storage device 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0365] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0366] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0367] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0368] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a storage device 1221, and a motherboard 1203 on which a flash memory 1222 is provided can be called a GPU module 1204.

[0369] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0370] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0371] Embodiment Mode 5 In this embodiment mode, an example of an electronic component in which the semiconductor device or the like shown in the above embodiment modes is incorporated will be described.

[0372] <Electronic Component> Fig. 20A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Fig. 20A has a memory device 720 inside a mold 711. Fig. 20A omits a portion of the interior of the electronic component 700 to show it. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 720 by wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0373] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722. The memory device 300 according to one embodiment of the present invention can be used for the memory device 720. Therefore, the driver circuit layer 721 can be referred to as a layer including a driver circuit 21. Furthermore, the memory circuit layer 722 can be referred to as a single-layer or multi-layer memory array 20. Therefore, the driver circuit layer 721 can be referred to as a layer including the memory array 20.

[0374] 20B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 provided on interposer 731.

[0375] In the electronic component 730, the storage device 720 is used as a high bandwidth memory (HBM), and the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0376] The package substrate 732 may be made of a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be made of a silicon interposer, a resin interposer, etc.

[0377] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0378] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation on a silicon interposer can be performed using a semiconductor process, it is easy to form fine wiring that is difficult to form on a resin interposer.

[0379] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0380] Furthermore, in SiP, MCM, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0381] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0382] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 20B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0383] The electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0384] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0385] Embodiment 6 In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described.

[0386] The semiconductor device according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, Internet of Things (IoT), healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0387] 21A to 21J and 22A to 22E illustrate examples of electronic devices including an electronic component 700 or an electronic component 730 including the semiconductor device according to one embodiment of the present invention.

[0388] 21A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0389] By applying the semiconductor device according to one embodiment of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0390] 21B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0391] Like the information terminal 5500 described above, the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0392] 21C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0393] Like the information terminal 5500 described above, the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0394] 21A to 21C are taken as examples of electronic devices, and are illustrated in Fig. 21A to 21C, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0395] 21D also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0396] A semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.

[0397] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0398] 21E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0399] FIG. 21F further illustrates a stationary game console 7500, an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in FIG. 21F , the controller 7522 can include a display unit for displaying game images and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob. The shape of the controller 7522 is not limited to the shape shown in FIG. 21F , and the shape of the controller 7522 may be varied depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller with a trigger button and shaped like a gun can be used. For example, in a music game, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures or voice.

[0400] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television devices, personal computer displays, game displays, and head-mounted displays.

[0401] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0402] Furthermore, by applying the semiconductor device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations that occur during game execution can be stored.

[0403] 21E shows a portable game machine as an example of a game machine. Also, FIG. 21F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an amusement facility (such as an arcade game center or an amusement park) and a pitching machine for batting practice installed in a sports facility.

[0404] [Mobile Object] The semiconductor device described in the above embodiment can be applied to a mobile object, such as an automobile, and the vicinity of the driver's seat of the automobile.

[0405] FIG. 21G illustrates an automobile 5700 as an example of a moving object.

[0406] An instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0407] In particular, the display device can enhance safety by displaying an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for a field of view obstructed by a pillar or the like, a blind spot on the driver's seat, etc. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be enhanced.

[0408] The semiconductor device described in the above embodiment can temporarily store information, and therefore, for example, the semiconductor device can be used to store necessary temporary information in a system that performs automatic driving, road guidance, hazard prediction, or the like of the automobile 5700. The display device may be configured to display temporary information such as road guidance and hazard prediction. Furthermore, the display device may be configured to store video images from a driving recorder installed in the automobile 5700.

[0409] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects may include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0410] [Camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0411] 21H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, here, the digital camera 6240 is configured so that the lens 6246 can be detached from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured so that a strobe device, a viewfinder, etc. can be separately attached.

[0412] The digital camera 6240 with low power consumption can be realized by applying the semiconductor device described in the above embodiment to the digital camera 6240. In addition, the low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0413] [Video Camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0414] 21I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0415] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the semiconductor device described above, the video camera 6300 can store temporary files generated during encoding.

[0416] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0417] 21J is a cross-sectional schematic diagram showing an example of an ICD. The ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0418] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0419] The ICD main body 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment with an electric shock is administered.

[0420] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 700 heart rate data acquired by the sensor, the number of pacing treatments performed, the duration of the treatment, and the like.

[0421] Furthermore, power can be received by the antenna 5404, and the power is charged in the battery 5401. Furthermore, the ICD main body 5400 has multiple batteries, thereby improving safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.

[0422] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0423] [Expansion Device for PC] The semiconductor device described in the above embodiment can be applied to an expansion device for a computer such as a PC (Personal Computer) or an information terminal.

[0424] Fig. 22A shows an example of such an expansion device: a portable expansion device 6100 equipped with a chip capable of storing information and externally attached to a PC. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). While Fig. 22A illustrates a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0425] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0426] [SD Card] The semiconductor device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0427] FIG. 22B is a schematic diagram of the external appearance of an SD card, and FIG. 22C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. The connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in the housing 5111. A semiconductor device and a circuit for driving the semiconductor device are provided on the board 5113. For example, an electronic component 700 and a controller chip 5115 are attached to the board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 700.

[0428] The capacity of the SD card 5110 can be increased by providing the electronic component 700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 700.

[0429] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0430] FIG. 22D is a schematic diagram of the external appearance of an SSD, and FIG. 22E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a memory device and a circuit for driving the memory device. For example, the circuit board 5153 is equipped with an electronic component 700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0431] [Computer] The computer 5600 shown in Fig. 23A is an example of a large computer (supercomputer) mainly used for scientific and technological calculations. Scientific and technological calculations require high speed processing of huge amounts of calculations, which results in high power consumption and heat generation from the chip. For example, in a data center with multiple computers 5600, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is estimated to be 10 ２４ (yotta) byte, or 10 ３０ It is expected to exceed quetta bytes.

[0432] By applying the semiconductor device of one embodiment of the present invention to the computer 5600, a supercomputer with low power consumption can be realized. Furthermore, the low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and significantly contribute to combating global warming.

[0433] The computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The computer 5620 can have the configuration shown in the perspective view of FIG. 23B, for example. In FIG. 23B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0434] PC card 5621 shown in Figure 23C is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 23C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0435] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0436] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0437] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0438] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0439] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0440] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0441] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be miniaturized and consume less power. Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which reduces heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.

[0442] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0443] Embodiment 7 A semiconductor device of one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. In this embodiment, a specific example of application of the semiconductor device of one embodiment of the present invention to space equipment will be described with reference to FIG. 24 .

[0444] Fig. 24 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 24, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0445] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0446] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0447] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0448] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0449] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0450] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0451] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0452] 100: transistor, 110: capacitor, 151: conductive layer, 152: conductive layer, 153: insulating layer, 154: insulating layer, 155: conductive layer, 157: insulating layer, 158: insulating layer, 159: insulating layer, 161: conductive layer, 162: opening, 163: semiconductor layer

Claims

1. It comprises a capacitive element and a transistor on the capacitive element, The aforementioned capacitive element is It comprises a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer. The aforementioned transistor is A second insulating layer on the second conductive layer, and a third conductive layer on the second insulating layer, The openings provided in the second insulating layer and the third conductive layer, The device comprises a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer. The aforementioned opening overlaps with the second conductive layer, The first insulating layer contains a ferroelectric material. The aforementioned second insulating layer comprises a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. Each of the fourth insulating layer and the sixth insulating layer contains nitrogen and silicon, The fifth insulating layer is a semiconductor device having oxygen and silicon.

2. It comprises a capacitive element and a transistor on the capacitive element, The aforementioned capacitive element is It comprises a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer. The aforementioned transistor is A second insulating layer on the second conductive layer, and a third conductive layer on the second insulating layer, The openings provided in the second insulating layer and the third conductive layer, The device comprises a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer. The aforementioned opening overlaps with the second conductive layer, The first insulating layer contains a ferroelectric material. The aforementioned second insulating layer comprises a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. Each of the fourth insulating layer and the sixth insulating layer contains nitrogen and silicon, The fifth insulating layer has oxygen and silicon, A semiconductor device in which the angle between the side surface of the second insulating layer and the bottom surface of the second insulating layer in the opening is 45 degrees or more and 90 degrees or less.

3. In Claim 1 or Claim 2, The semiconductor device comprises hydrogen in each of the fourth and sixth insulating layers.

4. Multiple layers stacked together, It has a first electrode that penetrates the plurality of layers, Each of the aforementioned layers is It comprises a capacitive element and a transistor on the capacitive element, The aforementioned capacitive element is It comprises a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer. The aforementioned transistor is A second insulating layer on the second conductive layer, and a third conductive layer on the second insulating layer, The openings provided in the second insulating layer and the third conductive layer, The device comprises a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer. The aforementioned opening overlaps with the second conductive layer, The first insulating layer contains a ferroelectric material. The third conductive layer is electrically connected to the first electrode, The aforementioned second insulating layer comprises a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. Each of the fourth insulating layer and the sixth insulating layer contains nitrogen and silicon, The fifth insulating layer is a semiconductor device having oxygen and silicon.

5. Multiple layers stacked together, It has a first electrode that penetrates the plurality of layers, Each of the aforementioned layers is It comprises a capacitive element and a transistor on the capacitive element, The aforementioned capacitive element is It comprises a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer. The aforementioned transistor is A second insulating layer on the second conductive layer, and a third conductive layer on the second insulating layer, The openings provided in the second insulating layer and the third conductive layer, The device comprises a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer. The aforementioned opening overlaps with the second conductive layer, The first insulating layer contains a ferroelectric material. The third conductive layer is electrically connected to the first electrode, The angle between the side surface of the second insulating layer and the bottom surface of the second insulating layer in the opening is 45 degrees or more and 90 degrees or less. The aforementioned second insulating layer comprises a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. Each of the fourth insulating layer and the sixth insulating layer contains nitrogen and silicon, The fifth insulating layer is a semiconductor device having oxygen and silicon.

6. In claim 4 or claim 5, The semiconductor device comprises hydrogen in each of the fourth and sixth insulating layers.