Oxide semiconductor film, thin film transistor and electronic device

Abstract

An oxide semiconductor film according to the present invention has a polycrystalline structure and is provided on a substrate; the crystal structure of the oxide semiconductor film is a bixbyite structure; and with respect to the out-of-plane XRD diffraction pattern of the oxide semiconductor film as obtained using a Cu-Kα ray, the ratio of the peak intensity of the (222) plane to the peak intensity of the (422) plane is 3.0 or less. The crystallite diameter as calculated from the peak of the (222) plane may be 10 nm or more.

Description

Oxide semiconductor film, thin film transistor, and electronic device

[0001] One embodiment of the present invention relates to an oxide semiconductor (Poly-OS) film having a polycrystalline structure, a thin film transistor including the Poly-OS film, and an electronic device including the thin film transistor.

[0002] In recent years, development of thin film transistors using oxide semiconductor films as channels has been progressing, instead of silicon semiconductor films using amorphous silicon, low-temperature polysilicon, single-crystal silicon, etc. (see, for example, Patent Documents 1 to 6). Thin film transistors including such oxide semiconductor films can be formed using a simple structure and a low-temperature process, similar to thin film transistors including amorphous silicon films. Furthermore, thin film transistors including oxide semiconductor films are known to have higher field-effect mobility than thin film transistors including amorphous silicon films.

[0003] JP 2021-141338 A JP 2014-099601 A JP 2021-153196 A JP 2018-006730 A JP 2016-184771 A JP 2021-108405 A

[0004] However, the field-effect mobility of a thin film transistor including a conventional oxide semiconductor film is not so high even when a crystalline oxide semiconductor film is used. Therefore, it has been desired to improve the crystalline structure of the oxide semiconductor film used in the thin film transistor and thereby increase the field-effect mobility of the thin film transistor.

[0005] In view of the above problems, an object of one embodiment of the present invention is to provide an oxide semiconductor film having a novel crystal structure. Another object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having the novel crystal structure. Another embodiment of the present invention relates to an electronic device including a thin film transistor.

[0006] An oxide semiconductor film according to one embodiment of the present invention is an oxide semiconductor film having a polycrystalline structure provided on a substrate, wherein the crystalline structure of the oxide semiconductor film is a bixbyite structure, and the oxide semiconductor film has an out-of-plane XRD diffraction pattern using Cu-Kα radiation in which the ratio of the peak intensity of the (222) plane to the peak intensity of the (422) plane is 3.0 or less.

[0007] A thin film transistor according to one embodiment of the present invention includes an oxide semiconductor layer including the oxide semiconductor film, a gate electrode provided on the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode.

[0008] An electronic device according to one embodiment of the present invention includes the thin film transistor.

[0009] 1 is a schematic cross-sectional view showing the configuration of a thin film transistor according to one embodiment of the present invention; FIG. 2 is a schematic plan view showing the configuration of a thin film transistor according to one embodiment of the present invention; FIG. 3 is a flowchart showing a method for manufacturing a thin film transistor according to one embodiment of the present invention; FIG. 4 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention; FIG. 5 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention; FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention; FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention; FIG. 8 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention; FIG. 9 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention; FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention;

[0010] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." For convenience of explanation, the terms "up" and "downward" are used in the description. However, for example, the hierarchical relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the hierarchical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When referring to a pixel electrode above a thin film transistor, the thin film transistor and the pixel electrode may not overlap in a planar view. On the other hand, when referring to a pixel electrode vertically above a thin film transistor, the thin film transistor and the pixel electrode may overlap in a planar view.

[0012] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0013] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0014] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0015] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0016] First Embodiment An oxide semiconductor film according to one embodiment of the present invention will be described.

[0017] [1. Composition of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment contains indium (In) and at least one metal element (M) other than indium. That is, the metal element other than indium contained in the oxide semiconductor film may be one type of metal element or multiple types of metal elements. The composition ratio of the oxide semiconductor film preferably satisfies formula (1) in terms of the atomic ratio of indium and at least one metal element. In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, an oxide semiconductor film having crystallinity can be formed. Furthermore, the crystal structure of the oxide semiconductor film preferably has a bixbyite structure. By increasing the ratio of indium, an oxide semiconductor film having a bixbyite structure can be formed.

[0018]

[0019] Although a detailed method for manufacturing an oxide semiconductor film will be described later in conjunction with a method for manufacturing a thin film transistor, the oxide semiconductor film can be formed by a sputtering method. The composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target. With a sputtering target having the above-described composition, an oxide semiconductor film without compositional deviation of metal elements can be formed by sputtering. Therefore, the composition of metal elements (indium and other metal elements) in the oxide semiconductor film may be the same as the composition of metal elements in the sputtering target. For example, the composition of metal elements in the oxide semiconductor film can be specified based on the composition of metal elements in the sputtering target. Note that this is not limited to the above because the oxygen contained in the oxide semiconductor film varies depending on the sputtering process conditions, etc.

[0020] The composition of metal elements in the oxide semiconductor film can also be determined by X-ray fluorescence analysis, electron probe microanalyzer (EPMA) analysis, or the like. Furthermore, since the oxide semiconductor film has a polycrystalline structure, the composition of the oxide semiconductor film may be determined by X-ray diffraction (XRD). Specifically, the composition of metal elements in the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained by XRD.

[0021] [2. Crystal Structure of Oxide Semiconductor Film] The oxide semiconductor film according to this embodiment has a polycrystalline structure including a plurality of crystal grains. Although the details will be described later, by using a Poly-crystalline Oxide Semiconductor (Poly-OS) technique, an oxide semiconductor film having a novel polycrystalline structure different from conventional oxide semiconductor films can be formed. Therefore, hereinafter, the oxide semiconductor film having a polycrystalline structure according to this embodiment may be referred to as a Poly-OS film to distinguish it from conventional oxide semiconductor films having a polycrystalline structure.

[0022] The crystal structure of the Poly-OS film is not particularly limited, but is preferably a bixbyite structure. The crystal structure of the Poly-OS film can be identified by XRD or electron beam diffraction.

[0023] The crystal structure of a Poly-OS film is different from the crystal structure of a conventional oxide semiconductor film having a polycrystalline structure. Specifically, the inventors found that although the Poly-OS film has a polycrystalline structure, the polycrystalline structure of the Poly-OS film is different from the polycrystalline structure of a conventional oxide semiconductor film. That is, as a result of various trials and errors, the inventors have completed an oxide semiconductor film (Poly-OS film) having a novel polycrystalline structure that is different from conventional oxide semiconductor films. The crystallinity characteristics of the Poly-OS film can be obtained by an XRD method.

[0024] There are two types of XRD measurement: out-of-plane measurement and in-plane measurement. Out-of-plane measurement evaluates lattice planes parallel to the film surface, while in-plane measurement evaluates lattice planes perpendicular to the film surface. The characteristics of a Poly-OS film can be obtained through out-of-plane measurement.

[0025] Here, the crystal plane (001) of the bixbite structure in this specification includes (001) and its equivalents (100) and (010). Similarly, the crystal plane (101) includes (101) and its equivalents (110) and (011). Furthermore, the crystal plane (111) represents (111). Furthermore, in each plane, "1" may be "-1", and is considered to be an equivalent plane to each plane.

[0026] In addition to (001), (101), and (111), there are other crystal planes such as (hk0) (h≠k, h and k are natural numbers), (hhl) (h≠l, h and l are natural numbers), and (hkl) (h≠k≠l, h, k, and l are natural numbers).

[0027] [2-1. Peak Intensity] When an oxide semiconductor film has crystallinity, peaks appear at predetermined diffraction angles in the XRD diffraction pattern obtained by out-of-plane measurement. For example, a conventional crystalline oxide semiconductor film containing 50% or more indium and having a bixbite structure has peaks at diffraction angles (2θ) of around 31° and around 44° in the XRD diffraction pattern. The peak at a diffraction angle around 31° is attributed to the (222) plane of the bixbite structure. The peak at a diffraction angle around 44° is attributed to the (422) plane of the bixbite structure. Furthermore, the peak intensity at a diffraction angle around 31° is significantly greater than the peak intensity at a diffraction angle around 44°. This means that many crystals having a (222) plane parallel to the surface of the oxide semiconductor film are present.

[0028] Note that the diffraction angle of the XRD diffraction pattern of an oxide semiconductor film may vary depending on the composition of metal elements contained in the oxide semiconductor film or the manufacturing conditions of the oxide semiconductor film, and therefore, in this specification, the vicinity of the diffraction angle peak is defined to include a range of ±2° of the diffraction angle of the peak.

[0029] The XRD diffraction pattern of a Poly-OS film having a bixbite structure also has a peak at a diffraction angle of around 31°, which corresponds to the (222) plane of the bixbite structure. However, the peak intensity at the diffraction angle of around 31° of the Poly-OS film is smaller than the peak intensity at the diffraction angle of around 31° of a conventional crystalline oxide semiconductor film with the same film thickness. For example, the peak intensity at the diffraction angle of around 31° of the Poly-OS film is less than half the peak intensity at the diffraction angle of around 31° of a conventional crystalline oxide semiconductor film with the same film thickness.

[0030] In the XRD diffraction pattern of the Poly-OS film, a peak may appear at a diffraction angle around 44°. When a peak appears at a diffraction angle around 44°, the ratio of the peak intensity at a diffraction angle around 31° to the peak intensity at a diffraction angle around 44° (hereinafter referred to as the "peak intensity ratio") is 3.0 or less. In the XRD diffraction pattern of the Poly-OS film, no peak may appear at a diffraction angle around 44°. Furthermore, in the XRD diffraction pattern of the Poly-OS film, a peak may appear at a diffraction angle around 52°, which corresponds to the (440) plane of the bixbyite structure. These phenomena indicate that the Poly-OS film contains few crystals with the (222) plane parallel to the surface of the Poly-OS film, and thus has a relaxed orientation. As a result, the Poly-OS film contains many crystals with the (440) plane parallel to the surface, and the film has a unique crystal arrangement that is different from conventional crystals.

[0031] As described above, the Poly-OS film exhibits a characteristic XRD diffraction pattern different from that of conventional crystalline oxide semiconductor films. Specifically, when the Poly-OS film has a bixbyite structure, the peak intensity of the (222) plane in the XRD diffraction pattern is small. When a peak of the (422) plane appears, the peak intensity ratio of the (222) plane to the (422) plane is 3.0 or less, preferably 2.0 or less. In addition, the Poly-OS film may have a small overall peak intensity, and the (422) plane peak may not appear. Furthermore, the Poly-OS film may exhibit a peak of the (440) plane, which means that the orientation of the (222) plane with respect to the surface of the Poly-OS film is relaxed and the (440) plane is aligned parallel to the surface of the Poly-OS film. In other words, the crystals contained in the Poly-OS film have a characteristic crystal arrangement different from conventional crystal arrangements.

[0032] [2-2. Crystallite Diameter] A crystal grain in a Poly-OS film may be composed of multiple crystallites. The crystallite diameter D can be calculated by the Scherrer formula shown in Equation (2) using the peak width of an XRD diffraction pattern. Here, K is the Scherrer constant, λ is the wavelength of the X-ray, β is the half-width of the peak, and θ is the Bragg angle (corresponding to ½ of the diffraction angle 2θ).

[0033]

[0034] For a Poly-OS film having a bixbyite structure, the crystallite diameter D of crystal grains contained in the Poly-OS film can be calculated using the half-width of the peak corresponding to the (222) plane. In an out-of-plane XRD diffraction pattern using Cu-Kα radiation, the crystallite diameter D is 10 nm or more, preferably 15 nm or more, and more preferably 20 nm or more. Furthermore, when the thickness of the Poly-OS film is 20 nm or less, the crystallite diameter D is preferably 0.95 times or more the thickness d of the Poly-OS film. That is, the crystallite diameter D is preferably approximately equal to the thickness of the Poly-OS film. Note that when the thickness of the Poly-OS film is small, the crystallite diameter D may exceed the thickness of the Poly-OS film. In this case, if the crystallite diameter D is close to the thickness of the Poly-OS film, it means that the crystallite diameter D is almost equal to the thickness of the Poly-OS film, and can be determined to be 0.95 times or more the thickness d of the Poly-OS film.

[0035] As described above, the peak intensity of the (222) plane in the XRD diffraction pattern of the Poly-OS film is small. However, the crystallite diameter of the Poly-OS film is comparable to that of a conventional crystalline oxide semiconductor film. Therefore, the Poly-OS film has a novel crystal structure in which the crystal orientation is more relaxed than in a conventional crystalline oxide semiconductor film, while maintaining the long-range atomic order in the film thickness direction (perpendicular to the film surface).

[0036] As described above, the oxide semiconductor film according to one embodiment of the present invention, that is, the Poly-OS film, has a novel crystal structure. As will be described in detail later, even when a Poly-OS film having such a novel crystal structure is used as a channel of a thin film transistor, the field-effect mobility is not reduced but is actually improved. Therefore, the electrical characteristics of a thin film transistor including the Poly-OS film are improved.

[0037] 1 to 10, a thin film transistor 10 according to one embodiment of the present invention will be described. The thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (MPU), or a memory circuit.

[0038] [1. Configuration of Thin Film Transistor 10] The configuration of a thin film transistor 10 according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a schematic cross-sectional view showing the configuration of a thin film transistor 10 according to one embodiment of the present invention. Figure 2 is a schematic plan view showing the configuration of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 1 is a cross-sectional view taken along line AA' in Figure 2.

[0039] As shown in FIG. 1 , the thin film transistor 10 includes a substrate 100, a light-shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203. The light-shielding layer 105 is provided on the substrate 100. The first insulating layer 110 covers the upper surface and end surfaces of the light-shielding layer 105 and is provided on the substrate 100. The second insulating layer 120 is provided on the first insulating layer 110. The oxide semiconductor layer 140 is provided on the second insulating layer 120. The gate insulating layer 150 covers the upper surface and end surfaces of the oxide semiconductor layer 140 and is provided on the second insulating layer 120. The gate electrode 160 overlaps the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surfaces of the gate electrode 160 and is provided on the gate insulating layer 150. The fourth insulating layer 180 is provided on the third insulating layer 170. The gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 have openings 171 and 173 through which part of the upper surface of the oxide semiconductor layer 140 is exposed. The source electrode 201 is provided on the fourth insulating layer 180 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. Note that hereinafter, when the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrodes 200.

[0040] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with respect to the gate electrode 160. That is, the oxide semiconductor layer 140 includes the channel region CH overlapping with the gate electrode 160, as well as the source region S and the drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has semiconductor properties. The source region S and the drain region D each have conductor properties. Therefore, the electrical conductivities of the source region S and the drain region D are greater than that of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a stacked-layer structure.

[0041] 2 , each of the light-shielding layer 105 and the gate electrode 160 has a constant width in the D1 direction and extends in the D2 direction perpendicular to the D1 direction. In the D1 direction, the width of the light-shielding layer 105 is larger than the width of the gate electrode 160. The channel region CH completely overlaps with the light-shielding layer 105. In the thin-film transistor 10, the D1 direction corresponds to the direction in which current flows from the source electrode 201 to the drain electrode 203 via the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0042] The substrate 100 can support each layer constituting the thin film transistor 10. The substrate 100 can be, for example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate. Alternatively, a rigid substrate having no light-transmitting properties, such as a silicon substrate, can also be used. Alternatively, a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used. Impurities may be introduced into the resin substrate in order to improve the heat resistance of the substrate 100. A substrate in which a silicon oxide film or a silicon nitride film is formed on the rigid or flexible substrate described above can also be used as the substrate 100.

[0043] The light-shielding layer 105 can reflect or absorb external light. As described above, the light-shielding layer 105 has an area larger than the channel region CH of the oxide semiconductor layer 140, and therefore can block external light from entering the channel region CH. The light-shielding layer 105 can be made of, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy or compound thereof. Furthermore, if electrical conductivity is not required, the light-shielding layer 105 does not necessarily need to contain a metal. For example, a black matrix made of a black resin can also be used as the light-shielding layer 105. The light-shielding layer 105 may have a single-layer structure or a multilayer structure. For example, the light-shielding layer 105 may have a multilayer structure of red, green, and blue color filters.

[0044] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (e.g., water) entering from the outside. Each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can be made of, for example, silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon oxynitride (SiN ｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ), aluminum oxide nitride (AlN ｘ O ｙ ), aluminum nitride (AlN ｘ ) is used. Here, silicon oxynitride (SiO ｘ N ｙ ) and aluminum oxynitride (AlO ｘ N ｙ ) are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than oxygen (O) (x>y), respectively. Silicon oxynitride (SiN ｘ O ｙ ) and aluminum oxide nitride (AlN ｘ O ｙ ) is a silicon compound and an aluminum compound containing a smaller ratio of oxygen than nitrogen (x>y). Furthermore, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single-layer structure or a multilayer structure.

[0045] Furthermore, each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarizing function or a function of releasing oxygen by heat treatment. However, when the second insulating layer 120 includes a silicon oxide film or a silicon oxynitride film, it is preferable that the hydrogen concentrations of the silicon oxide film and the silicon oxynitride film be reduced. For example, the hydrogen concentration of the silicon oxide film used in the second insulating layer 120 is lower than the hydrogen concentration of the silicon oxide film used in the third insulating layer 170.

[0046] The silicon oxide film or silicon oxynitride film included in the second insulating layer 120 may or may not be in contact with the oxide semiconductor layer 140. When the silicon oxide film and the oxide semiconductor layer 140 are not in contact with each other, it is preferable to provide another oxide insulating film between the silicon oxide film and the oxide semiconductor layer 140. For example, the oxide insulating film may be a metal oxide containing one or more metal elements selected from aluminum (Al), magnesium (Mg), calcium (Ca), scandium (Sc), gallium (Ga), germanium (Ge), strontium (Sr), nickel (Ni), tantalum (Ta), yttrium (Y), zirconium (Zr), barium (Ba), hafnium (Hf), cobalt (Co), and lanthanoid elements. In particular, it is preferable to use a metal oxide containing aluminum (e.g., aluminum oxide) as the metal oxide. Aluminum-containing metal oxides have high barrier properties against gases such as hydrogen and water.

[0047] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof, may be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a multilayer structure.

[0048] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, the gate insulating layer 150 includes silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), aluminum oxide (AlO ｘ ), or aluminum oxynitride (AlO ｘ N ｙ ) is used. The gate insulating layer 150 preferably has a composition close to the stoichiometric ratio. The gate insulating layer 150 also preferably has few defects. For example, the gate insulating layer 150 may be made of an oxide in which no defects are observed when evaluated by electron spin resonance (ESR).

[0049] The oxide semiconductor layer 140 can be the Poly-OS film described in the first embodiment.

[0050] The configuration of the thin-film transistor 10 has been described above. The thin-film transistor 10 described above is a so-called top-gate transistor. Various modifications of the thin-film transistor 10 are possible. For example, if the light-shielding layer 105 is conductive, the thin-film transistor 10 may be configured such that the light-shielding layer 105 functions as a gate electrode, and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin-film transistor 10 is a so-called dual-gate transistor. Furthermore, if the light-shielding layer 105 is conductive, the light-shielding layer 105 may be a floating electrode or may be connected to the source electrode 201. Furthermore, the thin-film transistor 10 may be a so-called bottom-gate transistor in which the light-shielding layer 105 functions as a main gate electrode.

[0051] 2. Manufacturing Method of Thin Film Transistor 10 A method of manufacturing the thin film transistor 10 according to one embodiment of the present invention will be described with reference to Fig. 3 to Fig. 10. Fig. 3 is a flowchart showing a method of manufacturing the thin film transistor 10 according to one embodiment of the present invention. Fig. 4 to Fig. 10 are schematic cross-sectional views showing a method of manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0052] 3, the method for manufacturing the thin-film transistor 10 includes steps S1010 to S1110. Steps S1010 to S1110 will be described in order below, but the order of the steps may be reversed in the method for manufacturing the thin-film transistor 10. Furthermore, the method for manufacturing the thin-film transistor 10 may include additional steps.

[0053] In step S1010, a light-shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light-shielding layer 105 is patterned using photolithography. A first insulating layer 110 and a second insulating layer 120 are formed on the light-shielding layer 105 (see FIG. 4 ). The first insulating layer 110 and the second insulating layer 120 are formed using CVD. For example, a silicon nitride film and a silicon oxide film are formed as the first insulating layer 110 and the second insulating layer 120, respectively. When a silicon nitride film is used as the first insulating layer 110, the first insulating layer 110 can block impurities diffusing from the substrate 100 side into the oxide semiconductor layer 140. When a silicon oxide film is used as the second insulating layer 120, the second insulating layer 120 can release oxygen by heat treatment.

[0054] The silicon oxide film used as the second insulating layer 120 is formed by adjusting the gas flow ratio so that the hydrogen concentration is reduced. ４ ) gas and nitrous oxide (N ２ When a film is formed using a monosilane gas and a dinitrogen monoxide gas, for example, the gas flow ratio of the monosilane gas and the dinitrogen monoxide gas is SiH ４ :N ２ O=1:50-200 (50 or more and 200 or less).

[0055] In step S1020, an oxide semiconductor film 145 is formed over the second insulating layer 120 (see FIG. 5 ). The oxide semiconductor film 145 is formed by a sputtering method. The thickness of the oxide semiconductor film 145 is, for example, 10 nm to 100 nm, preferably 15 nm to 70 nm, and more preferably 15 nm to 40 nm.

[0056] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order for the oxide semiconductor layer 140 to have a uniform polycrystalline structure in the substrate plane, the oxide semiconductor film 145 is preferably amorphous after deposition and before heat treatment. Therefore, the deposition conditions for the oxide semiconductor film 145 are preferably such that the oxide semiconductor layer 140 immediately after deposition is as little crystallized as possible. When the oxide semiconductor film 145 is deposited by a sputtering method, the oxide semiconductor film 145 is deposited while controlling the temperature of the deposition target (the substrate 100 and the layer formed on the substrate 100) to 100° C. or lower, preferably 80° C. or lower, and more preferably 50° C. or lower. The oxide semiconductor film 145 is deposited under a low oxygen partial pressure condition. The oxygen partial pressure is 2% to 20%, preferably 3% to 15%, and more preferably 3% to less than 10%.

[0057] In step S1030, the oxide semiconductor film 145 is patterned (see FIG. 6 ). The oxide semiconductor film 145 is patterned by photolithography. The oxide semiconductor film 145 may be etched by wet etching or dry etching. In the wet etching, an acidic etchant may be used. Examples of the etchant that may be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide, and hydrofluoric acid.

[0058] In step S1040, heat treatment is performed on the oxide semiconductor film 145. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing." In OS annealing, the oxide semiconductor film 145 is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or higher and 500° C. or lower, preferably 350° C. or higher and 450° C. or lower. The holding time at the temperature is 15 minutes or higher and 120 minutes or lower, preferably 30 minutes or higher and 60 minutes or lower. By the OS annealing, the oxide semiconductor film 145 is crystallized, and the oxide semiconductor layer 140 having a polycrystalline structure (i.e., the oxide semiconductor layer 140 including a Poly-OS film) is formed.

[0059] In the OS annealing, hydrogen or water contained in the oxide semiconductor layer 140 is removed. However, hydrogen or water contained in the second insulating layer 120 may also be removed through the oxide semiconductor layer 140. Hydrogen or water diffusing from the second insulating layer 120 to the oxide semiconductor layer 140 can inhibit or promote crystallization. When such a crystallization factor is used for crystallization, a conventional crystalline oxide semiconductor layer is formed. Therefore, in this embodiment, to eliminate the above-described crystallization factor, the hydrogen concentration of the silicon oxide film contained in the second insulating layer 120 is reduced in step S1010. As a result, diffusion of hydrogen or water from the second insulating layer 120 to the oxide semiconductor layer 140 is suppressed during the OS annealing, and a Poly-OS film having a novel crystal structure different from conventional ones can be formed.

[0060] Note that in Step S1010, an aluminum oxide film is preferably formed over the silicon oxide film as the second insulating layer 120. The aluminum oxide film can block hydrogen or water from the silicon oxide film, and thus can further suppress diffusion of hydrogen or water from the second insulating layer 120 to the oxide semiconductor layer 140 during OS annealing.

[0061] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see FIG. 7 ). The gate insulating layer 150 is formed using a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm. After the gate insulating layer 150 is formed, a process of introducing oxygen into a part of the gate insulating layer 150 may be performed.

[0062] In step S1060, a heat treatment is performed on the oxide semiconductor layer 140. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing." When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are generated on the top surface and side surfaces of the oxide semiconductor layer 140. When the oxidation annealing is performed, oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, and the oxygen defects are repaired.

[0063] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see FIG. 8). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned using photolithography.

[0064] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see FIG. 8 ). The source region S and the drain region D are formed by ion implantation. Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask. Examples of the implanted impurities include argon (Ar), phosphorus (P), and boron (B). In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen vacancies are generated by the ion implantation, and hydrogen is trapped in the generated oxygen vacancies. This reduces the resistance of the source region S and the drain region D. On the other hand, in the channel region that overlaps with the gate electrode 160, impurities are not implanted, so no oxygen vacancies are generated and the resistance of the channel region CH does not decrease.

[0065] In the thin-film transistor 10, impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150, and therefore the gate insulating layer 150 may also contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0066] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see FIG. 9 ). The third insulating layer 170 and the fourth insulating layer 180 are formed using a CVD method. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the fourth insulating layer 180 is also 50 nm or more and 500 nm or less.

[0067] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 (see FIG. 10 ). By forming the openings 171 and 173, the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0068] In step S1110, a source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171, and a drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a single conductive film that has been deposited. Through the above steps, the thin film transistor 10 shown in FIG. 1 is manufactured.

[0069] Although the method for manufacturing the thin film transistor 10 has been described above, the method for manufacturing the thin film transistor 10 is not limited to this.

[0070] In the thin film transistor 10 according to this embodiment, the oxide semiconductor layer 140 includes a Poly-OS film having a novel crystal structure. As will be described in detail later, the thin film transistor 10 including the Poly-OS film having such a novel crystal structure has improved electrical characteristics. For example, the field-effect mobility of the thin film transistor 10 is improved.

[0071] Third Embodiment An electronic device according to a third embodiment of the present invention will be described with reference to FIG.

[0072] FIG. 11 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Specifically, FIG. 11 shows a smartphone as an example of the electronic device 1000. The electronic device 1000 includes a display device 1100 with curved sides. The display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit, a drive circuit, and the like. The pixel circuit and the drive circuit include the thin-film transistor 10 described in the second embodiment. The thin-film transistor 10 has high field-effect mobility, which improves the responsiveness of the pixel circuit and the drive circuit, thereby improving the performance of the electronic device 1000.

[0073] The electronic device 1000 according to this embodiment is not limited to a smartphone. The electronic device 1000 also includes electronic devices having a display device, such as a watch, a tablet, a laptop computer, a car navigation system, or a television. The thin-film transistor 10 described in the first embodiment can be applied to any electronic device, regardless of whether or not it has a display device.

[0074] The Poly-OS film will be described in more detail based on the fabricated samples.

[0075] [1. Sample Fabrication] For the samples described below, oxide semiconductor films were fabricated on substrates using a sputtering process and an OS annealing process. In the sputtering process, a sputtering target with an atomic ratio of indium of 70% relative to all metal elements contained in the sintered body was used in both the example and the comparative example. In both samples, the chemical composition of the oxide semiconductor film after the OS annealing process was similar to that of the sputtering target. In addition, in the OS annealing process, the ultimate temperature was controlled between 350° C. and 450° C. in both the example and the comparative example.

[0076] Example 1 A silicon oxide film (SiO ｘ The silicon oxide film was formed using monosilane (SiH ４ ) gas and nitrous oxide (N ２The film was formed by plasma CVD using monosilane gas. The flow rate of monosilane gas was controlled so as to reduce the hydrogen concentration in the silicon oxide film. Specifically, the gas flow rate ratio of monosilane gas to dinitrogen monoxide gas in the formation of the silicon oxide film was set to SiH ４ :N ２ The ratio was 0:100.

[0077] An oxide semiconductor film was formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process was performed on the formed oxide semiconductor film in an air atmosphere.

[0078] Example 2 A laminated film (AlO ｘ / SiO ｘ The silicon oxide film was formed using monosilane (SiH ４ ) gas and nitrous oxide (N ２ The film was formed by plasma CVD using monosilane gas. The flow rate of monosilane gas was controlled so as to reduce the hydrogen concentration in the silicon oxide film. Specifically, the gas flow rate ratio of monosilane gas to dinitrogen monoxide gas in the formation of the silicon oxide film was set to SiH ４ :N ２ The ratio of aluminum oxide to aluminum oxide was 1:100. The aluminum oxide film was formed by sputtering using an aluminum (Al) target.

[0079] An oxide semiconductor film was formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process was performed on the formed oxide semiconductor film in an air atmosphere.

[0080] [Example 3-1], [Example 3-2] A laminated film (AlO ｘ / SiO ｘ The silicon oxide film was formed using monosilane (SiH ４ ) gas and nitrous oxide (N ２The film was formed by plasma CVD using monosilane gas. The flow rate of monosilane gas was controlled so as to reduce the hydrogen concentration in the silicon oxide film. Specifically, the gas flow rate ratio of monosilane gas to dinitrogen monoxide gas in the formation of the silicon oxide film was set to SiH ４ :N ２ The ratio of aluminum oxide to aluminum oxide was 1:100. The aluminum oxide film was formed by sputtering using an aluminum (Al) target.

[0081] An oxide semiconductor film was formed on the base film to a thickness of 15 nm by a sputtering process, and then an OS annealing process was performed on the formed oxide semiconductor film in an air atmosphere.

[0082] Comparative Example 1 A silicon oxide film (SiO ｘ The silicon oxide film was formed using monosilane (SiH ４ ) gas and nitrous oxide (N ２ The film was formed by plasma CVD using monosilane gas. The monosilane gas was used under normal gas flow conditions. Specifically, the gas flow ratio of monosilane gas to dinitrogen monoxide gas in forming the silicon oxide film was SiH ４ :N ２ The ratio was 0:1:30.

[0083] An oxide semiconductor film was formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process was performed on the formed oxide semiconductor film in an air atmosphere.

[0084] Comparative Example 2 A laminated film (AlO ｘ / SiO ｘ The silicon oxide film was formed using monosilane (SiH ４ ) gas and nitrous oxide (N ２ The film was formed by plasma CVD using monosilane gas. The monosilane gas was used under normal gas flow conditions. Specifically, the gas flow ratio of monosilane gas to dinitrogen monoxide gas in forming the silicon oxide film was SiH ４ :N２ The ratio of aluminum oxide to aluminum oxide was 1:30. The aluminum oxide film was formed by sputtering using an aluminum (Al) target.

[0085] An oxide semiconductor film was formed on the base film to a thickness of 30 nm by a sputtering process, and then an OS annealing process was performed on the formed oxide semiconductor film in an air atmosphere.

[0086] The differences between the prepared samples are summarized in Table 1.

[0087]

[0088] [2. Crystal Structure Analysis by XRD Method] The crystal structure of the oxide semiconductor film of each sample was analyzed by XRD method. The crystal structure analysis by XRD method was performed using a SmartLab device (manufactured by Rigaku Corporation) under the conditions shown in Table 2.

[0089]

[0090] To confirm the presence of a crystalline structure from the measurement results, peak smoothing was performed using an analysis program (JADE 6), and then the crystalline phase was identified using the crystalline structure file for bixbyite-type structure 14388 in the Inorganic Crystal Structure Database (ICSD: Chemical Information Association). After that, broad patterns that could not be indexed were determined to be background from the substrate and were removed by three-dimensional approximation.

[0091] 12 to 17 show XRD diffraction patterns of Examples 1 to 3-2 and Comparative Examples 1 and 2, respectively. All of the oxide semiconductor films had a peak at a diffraction angle (2θ) of around 31°. The diffraction angle around 31° is attributed to the (222) plane of the bixbite structure, and it was found that all of the oxide semiconductor films had a bixbite crystal structure.

[0092] As shown in FIG. 12 , no clear peak was observed in the oxide semiconductor film of Example 1 other than at a diffraction angle near 31°. As shown in FIG. 13 , the oxide semiconductor film of Example 2 had a peak at a diffraction angle near 52° in addition to the diffraction angle near 31°. The diffraction angle near 52° was attributed to the (440) plane of the bixbyite structure. As shown in FIG. 14 , the oxide semiconductor film of Example 3-1 had a peak at a diffraction angle near 44° in addition to the diffraction angle near 31°. The diffraction angle near 44° was attributed to the (422) plane of the bixbyite structure. As shown in FIG. 15 , the oxide semiconductor film of Example 3-2 had a peak at a diffraction angle near 52° in addition to the diffraction angle near 31°.

[0093] 16 , the oxide semiconductor film of Comparative Example 1 had a peak at a diffraction angle of about 44° in addition to a diffraction angle of about 31°, and as shown in FIG. 17 , the oxide semiconductor film of Comparative Example 2 also had a peak at a diffraction angle of about 44° in addition to a diffraction angle of about 31°.

[0094] The results of the XRD diffraction patterns in FIGS. 12 to 17 are summarized in Table 3. Table 2 shows the peak intensity of the (222) plane relative to the peak intensity of the (422) plane as a peak intensity ratio. Table 2 also shows the crystallite diameters calculated from the XRD diffraction patterns. The crystallite diameters were calculated based on the half-width of the peak at a diffraction angle of approximately 31.2° (corresponding to the (222) plane) that was confirmed in each oxide semiconductor film.

[0095]

[0096] As can be seen from Table 3, the oxide semiconductor films of Example 1 to Example 3-2 have smaller peak intensities of the (222) plane than the oxide semiconductors of Comparative Example 1 and Comparative Example 2. Example 1 and Comparative Example 1 differ only in the gas flow rate of monosilane gas in the film formation conditions for the silicon oxide film serving as the base film, but the peak intensity of the (222) plane of Example 1 is less than half of the peak intensity of the (222) plane of Comparative Example 1. Similarly, Example 2 and Comparative Example 2 differ only in the gas flow rate of monosilane gas in the film formation conditions for the silicon oxide film serving as the base film, but the peak intensity of the (222) plane of Example 2 is less than half of the peak intensity of the (222) plane of Comparative Example 2.

[0097] Furthermore, in Comparative Examples 1 and 2, a peak of the (422) plane is observed, but in Examples 1, 2, and 3-2, a peak of the (422) plane is not observed. In Example 3-1, a peak of the (422) plane is observed. However, in Example 3-1, the peak intensity ratio is smaller than in Comparative Examples 1 and 2. While the peak intensity ratios of Comparative Examples 1 and 2 are each greater than 3.0, the peak intensity ratio of Example 3-1 is 3.0 or less.

[0098] In Examples 1 and 2, in which the oxide semiconductor film has a thickness of 30 nm, the crystallite diameter is 20 nm or more. In Examples 3-1 and 3-2, in which the oxide semiconductor film has a thickness of 15 nm, the crystallite diameter is 1.2 times the thickness of the oxide semiconductor. That is, the crystallite diameter of the oxide semiconductor films in Examples 3-1 and 3-2 is 0.95 times or more that of the oxide semiconductor film, and is almost the same as the thickness of the oxide semiconductor film.

[0099] [3. Electrical Characteristics] Thin film transistors including the oxide semiconductor films of the above-mentioned Examples and Comparative Examples were fabricated using the manufacturing method described in the second embodiment, and their electrical characteristics were measured. Table 4 shows the field-effect mobility calculated from the electrical characteristics.

[0100]

[0101] As shown in Table 4, in the thin film transistors of all the examples, ２A field-effect mobility exceeding 1 / Vs was obtained. Furthermore, although Example 1 and Comparative Example 1 differ only in the gas flow rate of monosilane gas in the film-forming conditions for the silicon oxide film serving as the base film, the field-effect mobility of the thin-film transistor of Example 1 is greater than that of the thin-film transistor of Comparative Example 1. Similarly, although Example 2 and Comparative Example 2 differ only in the gas flow rate of monosilane gas in the film-forming conditions for the silicon oxide film serving as the base film, the field-effect mobility of the thin-film transistor of Example 2 is greater than that of the thin-film transistor of Comparative Example 2.

[0102] As can be seen from the results, when a Poly-OS film is used for the channel of a thin film transistor, the field-effect mobility is not reduced but is actually improved.

[0103] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits processes or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0104] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0105] 10: Thin film transistor, 100: Substrate, 105: Light-shielding layer, 110: First insulating layer, 120: Second insulating layer, 140: Oxide semiconductor layer, 145: Oxide semiconductor film, 150: Gate insulating layer, 160: Gate electrode, 170: Third insulating layer, 171: Opening, 173: Opening, 180: Fourth insulating layer, 200: Source / drain electrode, 201: Source electrode, 203: Drain electrode, 1000: Electronic device, 1100: Display device