Semiconductor device and method for manufacturing same

Abstract

A semiconductor device comprises a gate trench (22) formed in an active region (50); a gate insulating film (10) and a gate electrode layer (11) formed inside the gate trench (22); a gate wiring electrode (15) formed on an interlayer insulating film (13) that covers the gate electrode layer (11); and an external trench (6) formed in a drift layer (2) in an end region (60). A potential fixing layer (8) that covers an upper end corner section (6a) of the external trench (6), and an insulating layer (9) formed on the potential fixing layer (8), are formed inside the external trench (6). The gate insulating film (10) and the gate electrode layer (11) extend into the external trench (6), and the gate electrode layer (11) is connected to the gate wiring electrode (15) via a contact hole formed in the interlayer insulating film (13) inside the external trench (6).

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a trench gate semiconductor device and a manufacturing method thereof, and in particular to the structure of a gate electrode on the outer periphery of a semiconductor device.

[0002] BACKGROUND ART Semiconductor devices having a trench gate structure, such as insulated gate bipolar transistors (IGBTs) and insulated gate field effect transistors (MOSFETs), are used in power control applications in in-vehicle devices, industrial equipment, and the like.

[0003] Semiconductor devices with a trench gate structure are provided with a "gate pull-out portion" that extends a trench (hereinafter referred to as a "gate trench") in which a gate electrode is buried from the active region where the main current flows to the outer termination region. Although the drain voltage is low when the semiconductor device is turned on, a voltage is applied to the gate electrode, which increases the electric field generated in the gate insulating film, and the electric field tends to concentrate particularly at the upper corners of the gate trench.

[0004] The following Patent Document 1 discloses a technology for reducing electric field concentration at the upper corners of a gate trench in a gate pull-out portion by forming a gate insulating film so as to be in contact with a thick field insulating film formed by LOCOS (Local Oxidation of Silicon) oxidation.

[0005] Furthermore, Patent Document 2 listed below discloses a technique in which a field plate electrode is provided together with a gate electrode in a gate trench in a gate extraction portion, and the potential of the field plate electrode is set to the gate potential or the source potential.

[0006] JP 2001-102572 A JP 2011-199109 A

[0007] Even if an attempt is made to improve the breakdown voltage of the gate insulating film in the gate pull-out portion by using a field insulating film as in Patent Document 1, if, for example, the upper corner of the gate trench has an eave-like portion that deviates from a right angle, then locally thin portions of the field insulating film will be formed, and the effect of improving the breakdown voltage of the gate insulating film will not be fully achieved.

[0008] In the gate pull-out section disclosed in Patent Document 2, if the potential of the field plate electrode is set to the gate potential, there is a risk of gate insulating film breakdown at the upper corner of the gate trench unless the gate insulating film is sufficiently thick. On the other hand, if the potential of the field plate electrode is set to the source potential, there is a risk of gate-source leakage current occurring through the insulating film between the gate electrode and field plate electrode. Furthermore, depending on the shape of the field plate electrode, thin portions of the gate insulating film formed on the field plate electrode may be formed locally, which may lead to gate insulating film breakdown.

[0009] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can prevent breakdown of the gate insulating film at the upper corners of the gate trench in the gate pull-out portion.

[0010] a gate insulating film formed in contact with an inner surface of the gate trench; a gate electrode layer formed on the gate insulating film; an interlayer insulating film covering the gate electrode layer; a gate wiring electrode formed on the interlayer insulating film and connected to the gate electrode layer; an external trench formed in the drift layer in a termination region outside the active region; a potential fixing layer formed in the external trench and covering an upper end corner of the external trench; and an insulating layer formed on the potential fixing layer;

[0011] According to the present disclosure, since the upper corners of the external trench are covered with the potential fixing layer and the insulating layer, the gate electrode and gate insulating film extended to the external trench are formed on the insulating layer and are separated from the upper corners of the external trench, thereby preventing the gate insulating film from being destroyed by electric field concentration resulting from the shape of the upper corners of the external trench.

[0012] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0013] 2 is a schematic plan view showing a schematic configuration of a semiconductor device according to a first embodiment. FIG. 2 is a schematic view showing a schematic configuration of a boundary portion between an active region 50 and a termination region 60 in the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment taken along line A1-A2 of FIG. 2. FIG. 4 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment taken along line B1-B2 of FIG. 2. FIG. 5 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment taken along line C1-C2 of FIG. 2. FIG. 6 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the first embodiment taken along line D1-D2 of FIG. 2. FIG. 7 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment taken along line B1-B2 of FIG. 2. FIG. 8 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment taken along line B1-B2 of FIG. 2. FIG. 9 is a partial cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment taken along line B1-B2 of FIG. 2. 2A is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device taken along line B1-B2 of FIG. 2 in the first embodiment. FIG. 3A is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device taken along line D1-D2 of FIG. 2 in the first embodiment. FIG. 4A is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device taken along line D1-D2 of FIG. 2 in the first embodiment. FIG. 5A is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device taken along line D1-D2 of FIG. 2 in the first embodiment. FIG. 6A is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device taken along line D1-D2 of FIG. 2 in the first embodiment. FIG. 7A is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device taken along line D1-D2 of FIG. 2 in the first embodiment. FIG. 8A is a partial cross-sectional view illustrating a method of manufacturing a semiconductor device taken along line D1-D2 of FIG. 2 in the first embodiment.2 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line C1-C2 of FIG. 2 in a second embodiment. FIG. 3 is a partial cross-sectional view showing a manufacturing method of a semiconductor device taken along line B1-B2 of FIG. 2 in a second embodiment. FIG. 4 is a partial cross-sectional view showing a manufacturing method of a semiconductor device taken along line B1-B2 of FIG. 2 in a second embodiment. FIG. 5 is a partial cross-sectional view showing a manufacturing method of a semiconductor device taken along line B1-B2 of FIG. 2 in a second embodiment. FIG. 6 is a partial cross-sectional view showing a manufacturing method of a semiconductor device taken along line B1-B2 of FIG. 2 in a second embodiment. FIG. 7 is a partial cross-sectional view showing a manufacturing method of a semiconductor device taken along line B1-B2 of FIG. 2 in a second embodiment. 39 is a partial cross-sectional view showing a method for manufacturing a semiconductor device taken along line C1-C2 of FIG. 2 in a second embodiment. FIG. 40 is a partial cross-sectional view showing a method for manufacturing a semiconductor device taken along line C1-C2 of FIG. 2 in a second embodiment. FIG. 41 is a partial cross-sectional view showing a method for manufacturing a semiconductor device taken along line C1-C2 of FIG. 2 in a second embodiment. FIG. 42 is a partial cross-sectional view showing a method for manufacturing a semiconductor device taken along line C1-C2 of FIG. 2 in a second embodiment. FIG. 43 is a plan view schematic showing a schematic configuration of a semiconductor device according to a third embodiment. FIG. 44 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to the third embodiment. FIG. 45 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 39 in a third embodiment. FIG. 46 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 41 in a fourth embodiment. FIG. 47 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 2 in a fifth embodiment. FIG. 48 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 39 in a fifth embodiment. FIG. 49 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 41 in a fifth embodiment.2, 39 or 41 in accordance with a sixth embodiment. FIG. 4 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 2 in accordance with a sixth embodiment. FIG. 5 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 39 in accordance with a sixth embodiment. FIG. 6 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device taken along line D1-D2 of FIG. 41 in accordance with a sixth embodiment.

[0014] Hereinafter, embodiments of the technology according to the present disclosure will be described with reference to the drawings. The drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Furthermore, similar components are depicted with the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0015] In the description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "bottom," "front," or "back," may be used; however, these terms are used for convenience to facilitate understanding of the embodiments and have no relation to the positions and directions in actual use.

[0016] Unless a contradiction arises, a component described as including "one" may be included "one or more." Furthermore, a component is a conceptual unit, and one component may consist of multiple structures, or one component may correspond to a part of a structure.

[0017] In the following embodiments, the first conductivity type of the semiconductor will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. Although a MOSFET will be described as an example of a semiconductor device, the semiconductor device may also be an IGBT. The semiconductor substrate and drift layer will be described as being made of silicon carbide (SiC), a wide bandgap semiconductor with a wider bandgap than silicon. However, they may be made of silicon, other wide bandgap semiconductors such as gallium nitride or diamond, or a combination thereof.

[0018] In the following description, the "impurity concentration" refers to the peak value of the impurity concentration in each region.

[0019] First Embodiment FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. FIG. 2 is a schematic view showing a schematic configuration of a boundary portion between an active region 50 and a termination region 60 in the semiconductor device according to the first embodiment, showing a portion of region 40 surrounded by a dashed line in FIG. 1. For simplicity of explanation, FIG. 2 omits illustration of interlayer insulating film 13, surface electrode 14, surface ohmic electrode 19, and the like. Furthermore, FIGS. 3 to 6 are schematic views showing a cross-sectional configuration of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view taken along line A1-A2 in FIG. 2 , FIG. 4 is a cross-sectional view taken along line B1-B2 in FIG. 2 , FIG. 5 is a cross-sectional view taken along line C1-C2 in FIG. 2 , and FIG. 6 is a cross-sectional view taken along line D1-D2 in FIG. 2 .

[0020] The active region 50 is a region where a channel is formed when the semiconductor device is in an on-state, and a termination region 60 is a region surrounding the active region 50. The termination region 60 is provided on the periphery of the chip of the semiconductor device so as to surround the active region 50, and within the termination region 60, a p-type termination field reduction region 18 such as a field limiting ring (FLR) and an n-type channel stop region 31 that suppresses the spread of a depletion layer toward the edge of the chip are formed.

[0021] A gate trench 22 is provided in the drift layer 2 in the active region 50, and an external trench 6 corresponding to the gate trench of the gate pull-out portion is provided in the drift layer 2 in the termination region 60. As shown in FIG. 2 , the gate trenches 22 are formed in a striped pattern in a plan view. A cell is formed in each of a plurality of regions partitioned by the gate trenches 22 in the active region 50. While FIG. 2 shows an example in which a plurality of rectangular cells are arranged in a striped pattern, the shape of the cells may be circular or polygonal, such as hexagonal, and the cells may be arranged in a grid pattern, houndstooth check pattern, or the like.

[0022] As shown in FIGS. 3 to 6 , a drift layer 2, a well region 3, an impurity region 4, a contact region 5, and the like are provided on the front side of a semiconductor substrate 1 constituting a semiconductor device. A gate trench 22, a trench bottom electric field relaxation region 16, a gate insulating film 10, and a gate electrode layer 11 are provided in an active region 50. A termination region 60 is provided with an external trench 6, a trench bottom electric field relaxation region 16, a trench bottom high-concentration well region 17, a termination electric field relaxation region 18, an underlying insulating film 7, a potential fixing layer 8, an insulating layer 9, a gate insulating film 10, a gate electrode layer 11, a field insulating film 12, and a gate wiring electrode 15. The gate electrode layer 11 formed in the external trench 6 of the termination region 60 extends to surround the gate trench 22 in a plan view. A surface ohmic electrode 19, an interlayer insulating film 13, and a surface electrode 14 are provided on the front surface of the semiconductor substrate 1, and are shared by both the active region 50 and the termination region 60. On the back surface of the semiconductor substrate 1, a back surface ohmic electrode 20 and a back surface electrode 21 are provided in common to the active region 50 and the termination region 60.

[0023] The drift layer 2 is provided on the semiconductor substrate 1 made of n-type silicon carbide and is made of n-type silicon carbide. The n-type impurity of the drift layer 2 may be nitrogen or phosphorus, and the impurity concentration of the drift layer 2 is 1×10 １４ cm －３ That's it, 1 x 10 １８ cm －３ The thickness of the drift layer 2 may be set to about 5 μm or more and 300 μm or less.

[0024] The well region 3 is a p-type region provided in the surface layer of the drift layer 2 and is made of silicon carbide. The p-type impurity in the well region 3 may be aluminum, boron, or gallium, and the impurity concentration in the well region 3 is 1×10 １５ cm －３ That's it, 1 x 10 ２０ cm －３ The impurity concentration of the well region 3 may or may not be constant in the depth direction. The thickness of the well region 3 may be about 0.3 μm or more and 3 μm or less.

[0025] The impurity region 4 is an n-type region provided in the surface layer of the well region 3 and is made of silicon carbide. The n-type impurity of the impurity region 4 may be nitrogen or phosphorus, and the impurity concentration of the impurity region 4 is 1×10 １７ cm －３ That's it, 1 x 10 ２２ cm －３ The thickness of the impurity region 4 may be equal to or less than the thickness of the well region 3.

[0026] The contact region 5 is provided in the surface layer of the well region 3, and is a p-type region having a higher impurity concentration than the well region 3, and is made of silicon carbide. The p-type impurity of the contact region 5 may be aluminum, boron, or gallium, and the impurity concentration of the contact region 5 is 1×10 １８ cm －３ That's it, 1 x 10 ２２ cm －３ The thickness of the contact region 5 may be equal to or less than the thickness of the well region 3.

[0027] A contact hole 25 (hereinafter referred to as a "source contact hole 25") reaching the impurity region 4 and the contact region 5 is formed in the interlayer insulating film 13, and a surface ohmic electrode 19 connected to the impurity region 4 and the contact region 5 is formed at the bottom of the source contact hole 25. The impurity region 4 and the contact region 5 are electrically connected to the surface electrode 14, which is a main electrode, through the surface ohmic electrode 19 in the source contact hole 25.

[0028] Here, the contact region 5 is connected to the impurity region 4 by the surface ohmic electrode 19. When the contact region 5 is formed, a path is formed that connects the well region 3 to the surface ohmic electrode 19 via the contact region 5, thereby improving the electrical connection from the well region 3 to the surface ohmic electrode 19. The contact region 5 may be omitted.

[0029] The gate trenches 22 extend from the surface of the impurity region 4, penetrating the well region 3, and reaching the drift layer 2. As shown in FIG. 2 , the gate trenches 22 are provided in a striped pattern (i.e., in the form of multiple parallel lines) in the active region 50. When the gate trenches 22 are provided in a striped pattern, if the semiconductor device is a trench-gate silicon carbide MOSFET, a surface with high channel mobility, such as a (1-100) plane, can be used as a channel, thereby improving the characteristics of the semiconductor device. The gate trenches 22 also extend toward the termination region 60. Hereinafter, the direction in which the gate trenches 22 extend will be referred to as the "extension direction" of the gate trenches 22.

[0030] The width of the gate trench 22 may be, for example, 0.5 μm or more and 10 μm or less. If the gate trench 22 has a tapered cross-sectional shape, the width of the gate trench 22 refers to the width of the widest part of the tapered shape. The depth of the gate trench 22 may be, for example, 0.5 μm or more and 6 μm or less.

[0031] The trench bottom electric field relaxation region 16 is a p-type region provided below the bottom surface of the gate trench 22 and is made of silicon carbide. The trench bottom electric field relaxation region 16 has a conductivity type opposite to that of the drift layer 2 and functions to relax the electric field applied to the gate insulating film 10 formed on the bottom surface of the gate trench 22 when the semiconductor device is in operation, thereby preventing breakdown of the gate insulating film 10. The depth of the trench bottom electric field relaxation region 16 may be approximately 0.1 μm or more and 3.0 μm or less downward from the bottom surface of the gate trench 22. The trench bottom electric field relaxation region 16 may be in contact with the bottom surface of the gate trench 22. The p-type impurity in the trench bottom electric field relaxation region 16 may be aluminum, boron, or gallium, and the impurity concentration of the trench bottom electric field relaxation region 16 may be 1×10 １５ cm －３ That's it, 1 x 10 １９ cm －３ The following should be sufficient.

[0032] The external trench 6 is a wide trench formed in the termination region 60 to a depth similar to that of the gate trench 22. A trench bottom electric field relaxation region 16 is also provided below the external trench 6.

[0033] The trench bottom high-concentration well region 17 has a conductivity type opposite to that of the drift layer 2 and is provided in the trench bottom electric field relaxation region 16 below the external trench 6. The trench bottom high-concentration well region 17 is a p-type region with a higher concentration than the trench bottom electric field relaxation region 16 and is made of silicon carbide. A contact hole 26 (hereinafter referred to as the "periphery well region contact hole 26") is formed in the interlayer insulating film 13, reaching the trench bottom high-concentration well region 17. A surface ohmic electrode 19 connected to the trench bottom high-concentration well region 17 is formed at the bottom of the peripheral well region contact hole 26. The trench bottom electric field relaxation region 16 is electrically connected to the surface electrode 14 via the trench bottom high-concentration well region 17 and the surface ohmic electrode 19 at the peripheral well region contact hole 26.

[0034] The trench bottom high-concentration well region 17 has the effect of reducing the contact resistance between the trench bottom electric field relaxation region 16 and the surface ohmic electrode 19, as well as the effect of reducing the sheet resistance of the surface of the trench bottom electric field relaxation region 16. The depth of the trench bottom high-concentration well region 17 may be approximately 0.1 μm or more and 2.0 μm or less downward from the bottom surface of the external trench 6. The trench bottom high-concentration well region 17 may be in contact with the bottom surface of the external trench 6. The p-type impurity in the trench bottom high-concentration well region 17 may be aluminum, boron, or gallium, and the impurity concentration of the trench bottom high-concentration well region 17 may be 1×10 １８ cm －３ That's it, 1 x 10 ２２ cm －３ The following should be sufficient.

[0035] The terminal field relaxation region 18 is a p-type field relaxation region, such as a field limiting ring (FLR), that is formed continuously or intermittently to surround the active region 50. The terminal field relaxation region 18 is formed, for example, by ion implantation of aluminum, boron, gallium, or the like from the surface of the drift layer 2 to a depth of about 0.2 μm to 3 μm, which does not exceed the depth of the drift layer 2. The p-type impurity concentration of the terminal field relaxation region 18 is set to exceed the impurity concentration of the drift layer 2 and is set to 1×10 １５ cm －３ That's it, 1 x 10 １９ cm －３ The following would suffice.

[0036] The field insulating film 12 is formed from inside the external trench 6 to the chip edge so as to be in contact with the surface of the drift layer 2. The field insulating film 12 can be made of an insulating material such as silicon dioxide. The thickness of the field insulating film 12 can be set to, for example, 0.1 μm or more and 5.0 μm or less.

[0037] The underlying insulating film 7 is formed so as to cover the inside of the external trench 6 and the upper corners 6a of the external trench 6 (hereinafter referred to as "external trench upper corners 6a"), and is in contact with the well region 3, the drift layer 2, the trench bottom electric field relaxation region 16, and the trench bottom high-concentration well region 17. A portion of the underlying insulating film 7 is also formed on the field insulating film 12. The underlying insulating film 7 is made of an insulating material such as silicon dioxide. The thickness of the underlying insulating film 7 is, for example, approximately 10 nm or more and 1000 nm or less.

[0038] The potential fixing layer 8 is a conductive layer such as polysilicon, and is formed on the underlying insulating film 7. It covers the inside of the external trench 6 and the upper corners 6a of the external trench via the underlying insulating film 7. A portion of the potential fixing layer 8 is also formed on the field insulating film 12. In this embodiment, the potential fixing layer 8 is a first polysilicon layer made of polysilicon. A contact hole 27 (hereinafter referred to as the "potential fixing layer connection contact hole 27") is formed in the interlayer insulating film 13, reaching the potential fixing layer 8 on the field insulating film 12. The potential fixing layer 8 is connected to the surface electrode 14 through the potential fixing layer connection contact hole 27. Since the potential of the surface electrode 14 is the source potential, the potential of the potential fixing layer 8 is also the source potential. The potential fixing layer 8 has a thickness greater than that of the gate insulating film 10, and preferably has a thickness greater than three times that of the gate insulating film 10.

[0039] The insulating layer 9 is formed to cover the potential fixing layer 8. The insulating layer 9 suppresses gate leakage current from flowing between the potential fixing layer 8 and the gate electrode layer 11. The insulating layer 9 is made of an insulating material such as silicon dioxide. The thickness of the insulating layer 9 is, for example, about 10 nm or more and 1000 nm or less, and it is preferable that the thickness of the insulating layer 9 is greater than or equal to the gate insulating film 10.

[0040] The gate insulating film 10 is made of silicon dioxide and is formed so as to be in contact with the inner surface of the gate trench 22, part of the surface of the drift layer 2, the insulating layer 9, and the field insulating film 12. The thickness of the gate insulating film 10 can be, for example, about 10 nm or more and 200 nm or less.

[0041] The gate electrode layer 11 is formed on the gate insulating film 10 in the gate trench 22 and on the gate insulating film 10 formed on the insulating layer 9 in the external trench 6. In this manner, the gate insulating film 10 and the gate electrode layer 11 extend from inside the gate trench 22 to inside the external trench 6. The height of the upper end of the gate electrode layer 11 in the gate trench 22 is preferably equal to or lower than the surface level of the drift layer 2, and more preferably lower than the surface level of the drift layer 2. In this embodiment, the gate electrode layer 11 is a second polysilicon layer made of polysilicon. The gate electrode layer 11 formed in the termination region 60 has a thickness greater than that of the gate insulating film 10, for example. A contact hole 28 (hereinafter referred to as the "gate contact hole 28") reaching the gate electrode layer 11 is formed in the interlayer insulating film 13, and the gate electrode layer 11 is connected to a gate wiring electrode 15 connected to a gate electrode pad 29 via the gate contact hole 28.

[0042] The surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29 are formed on the interlayer insulating film 13 and are made of a metal material such as aluminum. The surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29 are arranged at a distance from each other.

[0043] The back surface ohmic electrode 20 is formed on the back surface of the semiconductor substrate 1 and is made of, for example, nickel silicide, a reaction product between a metal film containing nickel as a main component and the semiconductor substrate 1. The back surface electrode 21 is formed in contact with the back surface ohmic electrode 20 and is made of titanium, nickel, silver, gold, aluminum, or the like.

[0044] The semiconductor device according to the first embodiment is configured by the above-described components.

[0045] Next, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to Fig. 7 to Fig. 21. Fig. 7 to Fig. 21 are explanatory views of the respective manufacturing stages of a semiconductor device, of which Fig. 7 to Fig. 12 correspond to cross sections taken along line B1-B2 in Fig. 2, and Fig. 13 to Fig. 21 correspond to cross sections taken along line D1-D2 in Fig. 2.

[0046] First, an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type drift layer 2 is epitaxially grown thereon by chemical vapor deposition (CVD). At this time, the impurity concentration of the n-type drift layer 2 is 1×10 １４ cm －３ From 1 x 10 １８ cm －３ In this range, the thickness of the drift layer 2 is set to 5 μm to 300 μm.

[0047] Next, using a resist mask formed on the drift layer 2 by photolithography, aluminum, boron, or gallium ions are implanted to form a p-type well region 3 in the surface portion of the drift layer 2. The well region 3 may be formed by epitaxial growth.

[0048] Subsequently, using a resist mask formed on the well region 3 by photolithography, nitrogen or phosphorus ions are implanted to form an n-type impurity region 4 in the surface layer of the well region 3 .

[0049] Next, a silicon dioxide film having a thickness of about 1 μm to 2 μm is formed on the well region 3 and the impurity region 4, and reactive ion etching (RIE) is performed to form an etching mask having openings in regions for forming the gate trench 22 and the external trench 6. Then, when the gate trench 22 and the external trench 6 are formed by RIE, the state shown in FIGS.

[0050] Next, with the etching mask remaining, a resist mask is formed by photolithography to cover part of the external trench 6, and then aluminum, boron, or gallium ions are implanted from the surface side of the drift layer 2 to form a trench bottom electric field relaxation region 16 below the gate trench 22 and the external trench 6.

[0051] Next, the etching mask and resist mask are removed, and a resist mask is formed by photolithography. Then, aluminum, boron, or gallium is ion-implanted from the surface side of the drift layer 2 to form a termination field reduction region 18 in the termination region 60.

[0052] Subsequently, a resist mask is formed by photolithography, and then aluminum, boron, or gallium ions are implanted to form a p-type contact region 5 in the surface layer portion of the well region 3 and a trench bottom high-concentration well region 17 in the surface layer portion of the trench bottom electric field relaxation region 16. The heating temperature of the semiconductor substrate 1 during this ion implantation is preferably 150° C. or higher. A heating temperature of 150° C. or higher can lower the electrical resistance of the contact region 5 and reduce resistance loss during operation of the semiconductor device.

[0053] Next, after removing the etching mask, an annealing process is performed to activate the implanted impurities. The annealing process is performed in an inert gas atmosphere such as argon, or in a vacuum, at a temperature of approximately 1500°C or higher and 1900°C or lower, for a time period of approximately 30 seconds to 1 hour. Here, to prevent deterioration of the silicon carbide, i.e., surface roughness, due to high-temperature heating, a carbon film may be formed on the semiconductor substrate 1 before the annealing process. In this way, the state shown in FIGS. 8 and 14 is obtained.

[0054] Next, an insulating film such as silicon dioxide that will become the field insulating film 12 is formed by a method such as CVD, and a resist mask is formed on this insulating film by photolithography. Then, openings are made in this insulating film by etching to form the field insulating film 12, and the resist mask is removed. This results in the state shown in FIG.

[0055] Next, an underlying insulating film 7 is formed by thermal oxidation, CVD, or the like to cover the inside and upper corners of the external trench 6 and to be in contact with the well region 3, the drift layer 2, the trench bottom electric field relaxation region 16, and the trench bottom high-concentration well region 17. A part of the underlying insulating film 7 is also formed on the field insulating film 12.

[0056] Next, a conductive material such as polysilicon that will become the potential fixed layer 8 is formed on the underlying insulating film 7 by a method such as CVD, and a resist mask is formed on the polysilicon by photolithography. The polysilicon is then etched to form the potential fixed layer 8 in the termination region 60. A portion of the potential fixed layer 8 is also formed on the field insulating film 12. At this time, the polysilicon in the active region 50 is all etched away by an etch-back process until the underlying insulating film 7 is exposed. The resist mask is then removed. This results in the state shown in FIG. 16.

[0057] Next, a layer of silicon dioxide or the like that will become the insulating layer 9 is formed by CVD or the like so as to cover the potential fixing layer 8. If the potential fixing layer 8 is made of polysilicon, this layer of silicon dioxide or the like may be formed by thermally oxidizing the surface of the potential fixing layer 8. Next, a resist mask is formed by photolithography, and the insulating layer 9 is formed by etching. The underlying insulating film 7 and insulating layer 9 in the gate trench 22 in the active region 50 are all removed by etching to expose the drift layer 2. In this way, the state shown in FIG. 17 is obtained.

[0058] Next, gate insulating film 10 is formed by thermal oxidation, CVD, or the like on the surface of drift layer 2, the inner surface of gate trench 22, and on insulating layer 9 and field insulating film 12 in termination region 60. In this way, the state shown in FIGS.

[0059] Then, a conductive material such as polysilicon that will become gate electrode layer 11 is formed by CVD or the like, and a resist mask is formed on the polysilicon by photolithography. Subsequently, the polysilicon is etched to form gate electrode layer 11, and the resist mask is removed. At this time, the polysilicon in active region 50 is etched by an etch-back process so that the upper end of gate electrode layer 11 in gate trench 22 is lower than the surface level of drift layer 2. In this way, the state shown in FIGS. 10 and 19 is obtained.

[0060] Next, the interlayer insulating film 13 is formed by low-pressure CVD or the like, and a resist mask is formed by photolithography on the interlayer insulating film 13. Subsequently, the interlayer insulating film 13 is etched to form a source contact hole 25 that reaches the impurity region 4 and the contact region 5, and a peripheral well region contact hole 26 that reaches the high-concentration well region 17 at the bottom of the trench.

[0061] Then, a metal film containing Ni or the like as a main component is formed on the impurity region 4 and contact region 5 exposed in the source contact hole 25 and on the trench bottom high-concentration well region 17 exposed in the peripheral well region contact hole 26, and annealing is performed to form the surface ohmic electrode 19. Then, the metal film on the interlayer insulating film 13 is removed by etching, and the resist mask is removed.

[0062] Furthermore, a metal film containing Ni or the like as a main component is formed on the back surface of the semiconductor substrate 1, and annealing is performed to form the back surface ohmic electrode 20. Here, the heating temperature for each annealing treatment may be set to about 600° C. or higher and 1100° C. or lower.

[0063] Next, a resist mask is formed on the interlayer insulating film 13 by photolithography, and the interlayer insulating film 13 is etched to form a potential fixed layer connecting contact hole 27 reaching the potential fixed layer 8 and a gate contact hole 28 reaching the gate electrode layer 11, and the resist mask is then removed. In this way, the state shown in FIGS. 11 and 20 is obtained.

[0064] Then, a metal film such as aluminum is formed on the interlayer insulating film 13 and the surface ohmic electrode 19, and inside the potential fixing layer connection contact hole 27 and the gate contact hole 28, by sputtering or vapor deposition, and a resist mask is formed on the metal film by photolithography. Subsequently, the metal film is patterned by etching to form the surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29, and then the resist mask is removed. In this way, the state shown in FIGS. 12 and 21 is obtained.

[0065] Finally, a back electrode 21 is formed on the back ohmic electrode 20 by sputtering, vapor deposition, or the like, thereby completing the structure of the semiconductor device shown in FIGS.

[0066] 1, the termination region 60 may be provided with a channel stop region 31 that suppresses the expansion of a depletion layer toward the edge of the semiconductor device. The channel stop region 31 is an n-type region provided on the outer periphery side of the external trench 6 and is made of silicon carbide. The n-type impurity in the channel stop region 31 may be nitrogen or phosphorus, and the impurity concentration of the channel stop region 31 may be 1×10 １７ cm －３ That's it, 1 x 10 ２２ cm －３ The thickness of the channel stop region 31 may be about 1 / 2 mm or less. The thickness of the channel stop region 31 may be the same as or different from the thickness of the impurity region 4. The channel stop region 31 may be formed by ion implantation, and may be formed simultaneously with the impurity region 4 using a resist mask for providing the impurity region 4, or may be formed before or after the formation of the impurity region 4. When the channel stop region 31 is formed simultaneously with the impurity region 4, the channel stop region 31 and the impurity region 4 may be formed, for example, after the gate trench 22 and the external trench 6 are formed.

[0067] The order of the step of forming well region 3 and the step of forming impurity region 4 may be reversed. The method of forming well region 3 and impurity region 4 may be such that n-type impurity ions are implanted into the surface layer of well region 3 to provide impurity region 4, a resist mask is then formed thereon by photolithography, and p-type impurity ions are implanted into positions other than impurity region 4 to form well region 3.

[0068] In the manufacturing method described above, the thickness of the etching mask and the RIE process are adjusted so that the etching mask remains after the gate trench 22 and the external trench 6 are formed, and the electric field relaxation region 16 at the bottom of the trench is formed by ion implantation using the remaining etching mask and a resist mask formed by photolithography. However, the etching mask may be removed without remaining, and the electric field relaxation region 16 at the bottom of the trench may be formed by ion implantation using only the resist mask formed by photolithography.

[0069] Furthermore, trench bottom electric field relaxation region 16 below external trench 6 may be formed simultaneously with trench bottom electric field relaxation region 16 below gate trench 22, or may be formed before or after the formation of trench bottom electric field relaxation region 16 below gate trench 22. Furthermore, p-type impurities may be ion-implanted obliquely into gate trench 22 to form a p-type semiconductor layer in drift layer 2 that contacts the side surface of gate trench 22, and trench bottom electric field relaxation region 16 and well region 3 may be electrically connected via this semiconductor layer. When trench bottom electric field relaxation region 16 and well region 3 are electrically connected, trench bottom electric field relaxation region 16 is connected to surface electrode 14 via well region 3 and grounded, compared to a state in which trench bottom electric field relaxation region 16 is floating, and therefore the frequency characteristics of the semiconductor device are improved.

[0070] Furthermore, in this embodiment, an example has been shown in which the semiconductor device is a MOSFET, but if the semiconductor device is an IGBT, the conductivity type of the semiconductor substrate 1 may be p-type, and the thickness of the semiconductor substrate 1 may be reduced by polishing.

[0071] Next, the operation of the semiconductor device of this embodiment will be described.

[0072] When a gate voltage equal to or greater than the threshold value is applied between the gate electrode pad 29 and the front surface electrode 14, a channel is formed in the well region 3 facing the gate electrode layer 11, and electrons flow from the impurity region 4 to the drift layer 2. When a voltage is applied between the front surface electrode 14 and the back surface electrode 21 to generate an electric field, the electrons reach the back surface electrode 21 via the drift layer 2 and the semiconductor substrate 1. In other words, a current flows from the back surface electrode 21 to the front surface electrode 14, and the semiconductor device is turned on.

[0073] Here, when the gate insulating film 10 is formed in contact with the inner surfaces of the gate trench 22 and the external trench 6, an electric field is generated in the upper corners 22a of the external trench 6 (hereinafter referred to as "gate trench upper corners 22a") and in the gate insulating film 10 near the upper corners 6a of the external trench. However, in the active region 50, the gate electrode layer 11 is formed at a position lower than the upper corners 22a of the gate trench, which suppresses electric field concentration due to the shape of the upper corners 22a of the gate trench and prevents breakdown of the gate insulating film 10.

[0074] On the other hand, in the termination region 60, the gate insulating film 10 is formed on the insulating layer 9 and is separated from the upper corners 6 a of the external trench, so that the gate insulating film 10 is prevented from being destroyed by electric field concentration resulting from the shape of the upper corners 6 a of the external trench. Although the upper corners 6 a of the external trench are covered with the underlying insulating film 7, the well region 3 and the potential fixed layer 8 are at the source potential, and the potential fixed layer 8 is insulated from the gate electrode layer 11 by the insulating layer 9 and the gate insulating film 10, so that the underlying insulating film 7 at the upper corners 6 a of the external trench is not destroyed by the gate voltage.

[0075] Here, if the potential fixing layer 8 is sufficiently thick, the potential fixing layer 8 covers the upper corners and the inside of the external trench 6 via the underlying insulating film 7, and therefore the step of the external trench 6 can increase the curvature of the upper part of the potential fixing layer 8. Increasing the curvature of the upper part of the potential fixing layer 8 can prevent the film thicknesses of the insulating layer 9 and gate insulating film 10 formed on the potential fixing layer 8 from becoming locally thin, further improving the effect of preventing breakdown of the insulating layer 9 and gate insulating film 10 due to electric field concentration.

[0076] Furthermore, if the insulating layer 9 is thin, the insulation between the potential fixing layer 8 and the gate electrode layer 11 will be insufficient, and as in Patent Document 2, when the potential of the field plate electrode is set to the source potential, gate-source leakage will increase, and there is a risk of breakdown and short-circuiting between the potential fixing layer 8 and the gate electrode layer 11 due to an electric field. To avoid this, it is preferable to make the thickness of the insulating layer 9 greater than that of the gate insulating film 10. By doing so, the potential fixing layer 8 and the gate electrode layer 11 can be insulated to a thickness at least twice that of the gate insulating film 10, and the insulation between the gate and source in the termination region 60 can be made higher than that in the active region 50. This suppresses gate-source leakage current in the termination region 60 and further enhances the effect of preventing breakdown of the insulating layer 9 and the gate insulating film 10.

[0077] On the other hand, when a voltage less than the threshold is applied between the gate electrode pad 29 and the front surface electrode 14, no channel is formed in the well region 3 facing the gate electrode layer 11, no current flows from the back surface electrode 21 to the front surface electrode 14, and the semiconductor device is in the off state. In the off state of the semiconductor device, a voltage higher than the voltage in the on state is applied between the front surface electrode 14 and the back surface electrode 21, and a depletion layer expands from the well region 3 to the drift layer 2.

[0078] At this time, the depletion layer also spreads from the trench bottom electric field relaxation region 16 to the drift layer 2. As a result, breakdown of the gate insulating film 10 at the bottom or bottom corners of the gate trench 22 and the external trench 6 due to an electric field generated by the high voltage applied between the front surface electrode 14 and the back surface electrode 21 is suppressed.

[0079] When the semiconductor device transitions from the off state to the on state, the voltage applied between the front electrode 14 and the back electrode 21 decreases, and the depletion layer that had expanded into the drift layer 2 shrinks. The semiconductor device operates by alternately repeating the on state and the off state described above.

[0080] According to the semiconductor device of the first embodiment, it is possible to prevent breakdown of the gate insulating film 10 at the upper corners 22a of the gate trench and the upper corners 6a of the external trench.

[0081] 22 and 23 are diagrams showing the configuration of a semiconductor device according to a second embodiment, with Fig. 22 corresponding to a cross-sectional view taken along line B1-B2 in Fig. 2 and Fig. 23 corresponding to a cross-sectional view taken along line C1-C2 in Fig. 2. In this embodiment, the cross-sectional configurations taken along lines A1-A2 and D1-D2 in Fig. 2 are similar to those in the first embodiment.

[0082] In the second embodiment, an underlying insulating film 7 and a potential fixing layer 8 are provided below the gate insulating film 10 and the gate electrode layer 11 in the gate trench 22 of the active region 50. In the gate trench 22, the underlying insulating film 7 is formed in contact with the inner surface of the gate trench 22, and the potential fixing layer 8 is formed on the underlying insulating film 7. The gate insulating film 10 is formed in contact with the inner surface of the gate trench 22 and the upper surface of the potential fixing layer 8, and the gate electrode layer 11 is formed on the gate insulating film 10.

[0083] In this embodiment, the potential of the potential fixed layer 8 formed in the gate trench 22 is a floating potential. The underlying insulating film 7 is formed thicker than the gate insulating film 10 to mitigate the effect of the electric field generated at the bottom of the gate trench 22 by the drain voltage.

[0084] 22 , trench bottom electric field relaxation region 16 is formed below gate trench 22, but trench bottom electric field relaxation region 16 may be omitted. If trench bottom electric field relaxation region 16 is not formed, the electric field generated at the bottom of gate trench 22 by the drain voltage when the semiconductor device is off is shared by the depletion layer formed between well region 3 and drift layer 2, underlying insulating film 7, and potential fixed layer 8. Reducing the phosphorus concentration in the polysilicon of potential fixed layer 8 increases the depletion of polysilicon, thereby improving the electric field relaxation effect.

[0085] Furthermore, when trench bottom electric field relaxation region 16 is not formed, current constriction when the semiconductor device is on, which is caused by the depletion layer extending from well region 3 to drift layer 2 and the depletion layer extending from trench bottom electric field relaxation region 16 to drift layer 2, is eliminated, resulting in an effect of improving on-state characteristics.

[0086] Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to Figures 24 to 37. Figures 24 to 37 are explanatory views of the respective manufacturing stages of a semiconductor device, of which Figures 24 to 30 correspond to cross sections taken along line B1-B2 in Figure 2, and Figures 31 to 37 correspond to cross sections taken along line C1-C2 in Figure 2.

[0087] First, as in the first embodiment, an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type drift layer 2 is epitaxially grown thereon by chemical vapor deposition (CVD), thereby forming well regions 3, impurity regions 4, gate trenches 22, and trench bottom electric field relaxation regions 16. In this way, the state shown in FIGS.

[0088] Next, an insulating film such as silicon dioxide that will become the field insulating film 12 is formed by a CVD method or the like, and a resist mask is formed on this insulating film by photolithography. Then, openings are made in this insulating film by etching to form the field insulating film 12, and the resist mask is removed.

[0089] Then, the underlying insulating film 7 is formed by thermal oxidation, CVD, or the like, resulting in the state shown in FIGS.

[0090] Next, a conductive material such as polysilicon that will become the potential fixed layer 8 is formed on the underlying insulating film 7 by a method such as CVD, and is then etched by an etch-back process so that a desired thickness remains in the gate trench 22. After that, a resist mask is formed by photolithography, and the potential fixed layer 8 in the active region 50 and the potential fixed layer 8 in the termination region 60 are separated by etching so that the potential fixed layer 8 in the active region 50 has a floating potential, and the resist mask is then removed. In this way, the state shown in FIGS. 26 and 33 is obtained.

[0091] Next, an insulating layer 9 such as silicon dioxide is formed by CVD or the like so as to cover the potential fixed layer 8. If the potential fixed layer 8 is made of polysilicon, the insulating layer 9 may be formed by thermally oxidizing the potential fixed layer 8. In this way, the state shown in FIGS. 27 and 34 is obtained.

[0092] Next, a resist mask is formed by photolithography, and etching is performed until the upper side of the sidewall and the upper end of the potential fixing layer 8 in the gate trench 22 are exposed. Thereafter, a gate insulating film 10 is formed on the surface of the drift layer 2, the inside of the gate trench 22, and on the insulating layer 9 by thermal oxidation, CVD, or the like. In this way, the state shown in FIGS. 28 and 35 is obtained.

[0093] Then, a conductive material such as polysilicon that will become gate electrode layer 11 is formed by CVD or the like, and a resist mask is formed on the polysilicon by photolithography. Subsequently, the polysilicon is etched to form gate electrode layer 11, and the resist mask is removed. At this time, the polysilicon in active region 50 is etched by an etch-back process so that the upper end of gate electrode layer 11 in gate trench 22 is lower than the surface level of drift layer 2. In this way, the state shown in FIGS. 29 and 36 is obtained.

[0094] Next, the interlayer insulating film 13 is formed by low-pressure CVD or the like, and a resist mask is formed by photolithography on the interlayer insulating film 13. Subsequently, the interlayer insulating film 13 is etched to form a source contact hole 25 that reaches the impurity region 4 and the contact region 5, and a peripheral well region contact hole 26 that reaches the high-concentration well region 17 at the bottom of the trench.

[0095] Then, a metal film containing Ni or the like as a main component is formed on the impurity region 4 and contact region 5 exposed in the source contact hole 25 and on the trench bottom high-concentration well region 17 exposed in the peripheral well region contact hole 26, and annealing is performed to form the surface ohmic electrode 19. Then, the metal film on the interlayer insulating film 13 is removed by etching, and the resist mask is removed.

[0096] Furthermore, a metal film containing Ni or the like as a main component is formed on the back surface of semiconductor substrate 1, and annealing is performed to form back surface ohmic electrode 20. Here, the heating temperature for each annealing treatment may be set to about 600° C. or higher and 1100° C. or lower. In this way, the state shown in FIGS. 30 and 37 is obtained.

[0097] Then, a metal film such as aluminum is formed by sputtering or vapor deposition on the interlayer insulating film 13 and the surface ohmic electrode 19, and inside the potential fixing layer connection contact hole 27 and the gate contact hole 28, and a resist mask is formed on the metal film by photolithography. Subsequently, the metal film is patterned by etching to form the surface electrode 14, the gate wiring electrode 15, and the gate electrode pad 29, and then the resist mask is removed.

[0098] Finally, a back electrode 21 is formed on the back ohmic electrode 20 by sputtering, vapor deposition, or the like, thereby completing the structure of the semiconductor device shown in FIGS.

[0099] In the second embodiment, an example was described in which the potential fixing layer 8 of the active region 50 and the potential fixing layer 8 of the termination region 60 are separated by etching so that the potential fixing layer 8 in the active region 50 is at a floating potential. However, as will be described in the fourth embodiment, in the case of a configuration in which the potential fixing layer 8 of the termination region 60 is at a floating potential without being connected to an external electrode, the potential fixing layer 8 of the active region 50 and the potential fixing layer 8 of the termination region 60 may be connected to each other.

[0100] The semiconductor device according to the second embodiment also provides the same effects as those of the first embodiment. Furthermore, the thickness of the underlying insulating film 7 formed on the bottom surface of the gate trench 22 is thicker than the gate insulating film 10, and the gate electrode layer 11 is not located on the bottom surface of the gate trench 22. Therefore, compared to the case where only the gate insulating film 10 is formed on the bottom surface of the gate trench 22, the influence of the electric field generated in the insulating film (silicon dioxide or the like) on the bottom surface of the gate trench 22 due to the drain voltage, the gate voltage, or the like when the semiconductor device is in the off state is mitigated.

[0101] <Third Embodiment> Figures 38 to 40 are diagrams showing the configuration of a semiconductor device according to a third embodiment. Figure 38 is a plan view showing the general configuration of a semiconductor device according to the third embodiment, and Figure 39 shows the configuration of a region 41 surrounded by a dashed line in Figure 38. Figure 40 is a cross-sectional view taken along line D1-D2 in Figure 39. For the sake of simplicity, the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. are omitted from Figure 39.

[0102] The semiconductor device according to the third embodiment includes a ground electrode pad 30 to which a ground potential of 0 V is supplied and a ground wiring electrode 23 connected thereto. In the first and second embodiments, the potential fixing layer 8 is connected to the surface electrode 14, and the potential of the potential fixing layer 8 is set to the source potential. In the third embodiment, the potential fixing layer 8 is connected to the ground wiring electrode 23, and the potential of the potential fixing layer 8 is set to the ground potential. The rest of the configuration is the same as in the first embodiment.

[0103] Even when the potential fixing layer 8 is set to ground potential, the gate insulating film 10 is formed in the termination region 60 at a distance from the upper corners 6 a of the external trench, thereby suppressing electric field concentration due to the shape of the upper corners 6 a of the external trench and preventing breakdown of the gate insulating film 10. Although the upper corners 6 a of the external trench are covered with the underlying insulating film 7, the well region 3 is at source potential, the potential fixing layer 8 is at ground potential, and the potential fixing layer 8 is insulated from the gate electrode layer 11 by the insulating layer 9 and the gate insulating film 10, so the underlying insulating film 7 at the upper corners 6 a of the external trench will not be broken down by the gate voltage.

[0104] <Fourth Embodiment> Figures 41 and 42 are diagrams showing the configuration of a semiconductor device according to a fourth embodiment. Figure 41 is a schematic diagram showing the outline configuration of a semiconductor device according to the fourth embodiment, and shows the configuration of a region 40 surrounded by a dashed line in Figure 1. Figure 42 is a cross-sectional view taken along line D1-D2 in Figure 41. For the sake of simplicity, the interlayer insulating film 13, the surface electrode 14, the surface ohmic electrode 19, etc. are omitted from Figure 41.

[0105] In the fourth embodiment, the potential fixed layer connection contact hole 27 is not formed in the interlayer insulating film 13, and the potential fixed layer 8 is not connected to any other electrode. In other words, the potential of the potential fixed layer 8 is set to a floating potential. The rest of the configuration is the same as in the first to third embodiments.

[0106] Even when the potential fixing layer 8 is set to a floating potential, the gate insulating film 10 is formed in the termination region 60 at a distance from the upper corners 6 a of the external trench, thereby suppressing electric field concentration due to the shape of the upper corners 6 a of the external trench and preventing breakdown of the gate insulating film 10. Although the upper corners 6 a of the external trench are covered with the underlying insulating film 7, the well region 3 is at the source potential, the potential fixing layer 8 is at a floating potential, and the potential fixing layer 8 is insulated from the gate electrode layer 11 by the insulating layer 9 and the gate insulating film 10, so the underlying insulating film 7 at the upper corners 6 a of the external trench will not be broken down by the gate voltage.

[0107] 43 to 45 are diagrams showing the configuration of a semiconductor device according to a fifth embodiment. Fig. 43 is a cross-sectional view taken along the line D1-D2 in Fig. 2, Fig. 44 is a cross-sectional view taken along the line D1-D2 in Fig. 39, and Fig. 45 is a cross-sectional view taken along the line D1-D2 in Fig. 41.

[0108] In the first to fourth embodiments, examples have been shown in which the well region 3 and the trench bottom electric field relaxation region 16 are separated from each other in the termination region 60. In the fifth embodiment, the well region 3 and the trench bottom electric field relaxation region 16 are connected to each other by a p-type external trench side surface connection layer 24 formed on the side surface of the external trench 6. The remaining configuration is the same as that of the first to fourth embodiments. Note that FIG. 43 corresponds to the configuration of FIG. 6 in which the external trench side surface connection layer 24 is provided, FIG. 44 corresponds to the configuration of FIG. 40 in which the external trench side surface connection layer 24 is provided, and FIG. 45 corresponds to the configuration of FIG. 42 in which the external trench side surface connection layer 24 is provided.

[0109] The external trench side surface connection layer 24 is formed by, for example, ion implantation after the formation of the trench bottom electric field relaxation region 16, and the p-type impurity may be aluminum, boron, or gallium, and the impurity concentration may be 1×10 １７ cm －３That's it, 1 x 10 ２２ cm －３ The following should be sufficient.

[0110] The well region 3 and the trench bottom electric field relaxation region 16 are connected at the side surface of the external trench 6, which increases the number of paths through which the displacement current generated at turn-off flows to the surface electrode 14. This suppresses the potential rise in the underlying insulating film 7 at the upper corner 6 a of the external trench due to the displacement current, preventing breakdown of the underlying insulating film 7.

[0111] 46 to 49 are diagrams showing the configuration of a semiconductor device according to a sixth embodiment. Fig. 46 is a cross-sectional view taken along line B1-B2 in Fig. 2, 39 or 41, Fig. 47 is a cross-sectional view taken along line D1-D2 in Fig. 2, Fig. 48 is a cross-sectional view taken along line D1-D2 in Fig. 39, and Fig. 49 is a cross-sectional view taken along line D1-D2 in Fig. 41.

[0112] In the sixth embodiment, the underlying insulating film 7 is not formed, and the potential fixing layer 8 contacts the inner surface of the external trench 6 and the upper corners 6a of the external trench. Other configurations are the same as those of the first to fifth embodiments. Note that Fig. 47 corresponds to the configuration of Fig. 43 from which the underlying insulating film 7 has been omitted, Fig. 48 corresponds to the configuration of Fig. 44 from which the underlying insulating film 7 has been omitted, and Fig. 49 corresponds to the configuration of Fig. 45 from which the underlying insulating film 7 has been omitted.

[0113] Even when the underlying insulating film 7 is omitted, the gate insulating film 10 is formed in the termination region 60 at a distance from the upper corners 6 a of the external trench, thereby suppressing electric field concentration due to the shape of the upper corners 6 a of the external trench and preventing breakdown of the gate insulating film 10.

[0114] As in the first to fifth embodiments, the potential of the potential fixed layer 8 is set to any one of the source potential, the ground potential, and the floating potential. Even if the potential of the potential fixed layer 8 is the source potential or the ground potential, current does not easily flow from the back electrode 21 to the potential fixed layer 8 due to the influence of the PN junctions between the well region 3, the external trench side surface connection layer 24, the trench bottom electric field relaxation region 16, and the trench bottom high-concentration well region 17 and the drift layer 2, and therefore the influence on loss is small.

[0115] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0116] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0117] 1 semiconductor substrate, 2 drift layer, 3 well region, 4 impurity region, 5 contact region, 6 external trench, 6a external trench upper end corner, 7 underlying insulating film, 8 potential fixing layer, 9 insulating layer, 10 gate insulating film, 11 gate electrode layer, 12 field insulating film, 13 interlayer insulating film, 14 surface electrode, 15 gate wiring electrode, 16 trench bottom electric field relaxation region, 17 trench bottom high concentration well region, 18 termination electric field relaxation region, 19 surface ohmic electrode, 20 back surface ohmic electrode, 21 back surface electrode, 22 gate trench, 22a gate trench upper end corner, 23 ground wiring electrode, 24 external trench side connection layer, 25 source contact hole, 26 peripheral well region contact hole, 27 potential fixing layer connection contact hole, 28 gate contact hole, 29 gate electrode pad, 30 ground electrode pad, 31 channel stop region, 50 active region, 60 termination region.

Claims

1. A drift layer of a first conductivity type; a well region of a second conductivity type formed in a surface portion of the drift layer; an impurity region of a first conductivity type formed in a surface layer portion of the well region; a gate trench formed to penetrate the impurity region and the well region of the active region and reach the drift layer; a gate insulating film formed in contact with an inner surface of the gate trench; a gate electrode layer formed on the gate insulating film; an interlayer insulating film covering the gate electrode layer; a gate wiring electrode formed on the interlayer insulating film and connected to the gate electrode layer; an outer trench formed in the drift layer in a termination region outside the active region; a potential fixing layer formed in the outer trench and covering an upper end corner of the outer trench; an insulating layer formed on the potential fixing layer; an underlying insulating film formed under the potential fixing layer; Equipped with the gate insulating film and the gate electrode layer extend into the external trench in the termination region, and the gate electrode layer is connected to the gate wiring electrode through a contact hole formed in the interlayer insulating film within the external trench; the underlying insulating film is formed uniformly along inner walls of the gate trench and the outer trench without having an opening through which the potential fixing layer is exposed; Semiconductor device.

2. The potential fixing layer has a thickness greater than that of the gate insulating film. The semiconductor device according to claim 1 .

3. the thickness of the underlying insulating film is equal to or greater than the thickness of the gate insulating film; 3. The semiconductor device according to claim 1 or 2.

4. a portion of the potential fixing layer is formed at a bottom of the gate trench, and the gate insulating film and the gate electrode layer in the gate trench are formed on the potential fixing layer; The potential fixing layer at the bottom of the gate trench is configured to have a floating potential.

3. The semiconductor device according to claim 1 or 2.

5. a trench bottom electric field relaxation region of a second conductivity type formed below the outer trench; an external trench side connection layer of a second conductivity type formed on a side surface of the external trench and connecting the well region and the trench bottom electric field relaxation region; Further comprising:

3. The semiconductor device according to claim 1 or 2.

6. a surface electrode formed on the interlayer insulating film and connected to the well region; the potential fixing layer is connected to the surface electrode through a contact hole formed in the interlayer insulating film; 3. The semiconductor device according to claim 1 or 2.

7. a ground wiring electrode formed on the interlayer insulating film, the potential fixing layer is connected to the ground wiring electrode through a contact hole formed in the interlayer insulating film; 3. The semiconductor device according to claim 1 or 2.

8. The potential fixing layer is configured to have a floating potential.

3. The semiconductor device according to claim 1 or 2.

9. the gate electrode layer in the termination region surrounds the gate trench in a plan view; 3. The semiconductor device according to claim 1 or 2.

10. The thickness of the potential fixing layer is three times or more the thickness of the gate insulating film.

3. The semiconductor device according to claim 1 or 2.

11. The thickness of the insulating layer is equal to or greater than the thickness of the gate insulating film.

3. The semiconductor device according to claim 1 or 2.

12. The position of the upper end of the gate electrode layer in the gate trench is lower than the upper end of the gate trench.

3. The semiconductor device according to claim 1 or 2.

13. forming a drift layer of a first conductivity type; forming a well region of a second conductivity type in a surface layer portion of the drift layer; forming an impurity region of a first conductivity type in a surface layer portion of the well region; forming a gate trench penetrating the impurity region and the well region of the active region to reach the drift layer; forming an outer trench in the drift layer in a termination region outside the active region; forming a potential fixing layer in the outer trench so as to cover an upper end corner of the outer trench; forming an insulating layer on the potential fixing layer; forming a gate insulating film in the gate trench and in the outer trench; forming a gate electrode layer on the gate insulating film in the gate trench and in the outer trench; forming an interlayer insulating film covering the gate electrode layer; forming a contact hole in the interlayer insulating film in the outer trench, the contact hole reaching the gate electrode layer; forming a gate wiring electrode on the interlayer insulating film, the gate wiring electrode being connected to the gate electrode layer through the contact hole; Equipped with Before forming the potential fixing layer, a step of forming an underlying insulating film provided under the potential fixing layer is further included; the underlying insulating film is formed uniformly along inner walls of the gate trench and the outer trench without having an opening through which the potential fixing layer is exposed; A method for manufacturing a semiconductor device.

14. The potential fixing layer is formed to a thickness greater than a thickness of the gate insulating film. The method for manufacturing a semiconductor device according to claim 13.

15. In the step of forming the potential fixing layer, a portion of the potential fixing layer is formed within the gate trench. The method for manufacturing a semiconductor device according to claim 13 or 14.