Semiconductor-type quantum bit device

Abstract

[Problem] The present invention addresses the problem of providing a semiconductor-type quantum bit device having reduced variations in characteristics of quantum bit operations when multiple units thereof are integrated. [Solution] A semiconductor-type quantum bit device 10 is characterized by comprising at least: a support substrate 1 including a first conductivity type semiconductor layer; a fringe electric field formation layer 2 that is formed on the support substrate 1, and that includes a second conductivity type semiconductor layer which has a conductivity type different from that of the first conductivity type semiconductor layer or a metal layer which, together with the support substrate, forms a Schottky barrier wall; an embedded oxide layer 3 that is formed on the fringe electric field formation layer 2; and a quantum dot semiconductor layer 4 that is formed on the embedded oxide layer 3 and in which quantum dots are formed.

Description

Semiconductor quantum bit device

[0001] The present invention relates to a semiconductor quantum bit device in which fluctuations in quantum bit operation characteristics are suppressed by fringe electric fields.

[0002] Quantum computers are being developed in various forms, including superconducting, ion trap, photon, and semiconductor types. Of these, semiconductor quantum bit devices are compatible with existing semiconductor device manufacturing facilities for classical computers, and research is underway into large-scale integration that utilizes integration technologies developed for classical computers.

[0003] For example, with regard to semiconductor quantum bit devices, a technology has been proposed in which the area required for forming one quantum bit is reduced and high integration is achieved by embedding a micromagnet, which is necessary for spin manipulation by electron dipole spin resonance (EDSR), in a semiconductor layer (see Non-Patent Document 1). According to this proposal, it is possible to realize a one-qubit gate with excellent quantum bit manipulation characteristics by arranging the micromagnet, and an integrated circuit that highly integrates this gate.

[0004] In large-scale integration of the semiconductor-type quantum bit devices, in order to perform meaningful quantum computations with fewer errors, it is essential to not only achieve high integration but also to suppress the characteristic variations of the individual integrated semiconductor-type quantum bit devices. In this regard, similar to classical transistors and the like, if variations in device dimensions occur during the manufacturing process, the quantum bit operations will also vary between individual devices. In particular, with the semiconductor-type quantum bit devices, even slight variations in dimensions on the order of a few nanometers can cause large variations in quantum bit operations. Since slight variations in dimensions are difficult to avoid even with the most advanced manufacturing equipment, it is necessary to develop new technologies that suppress the individual characteristic variations when integrating multiple devices, even with dimensional variations.

[0005] S. Iizuka et al., VLSI Tech. Dig. 2021, JFS5-5.

[0006] The present invention aims to solve the above-mentioned problems in the prior art and to achieve the following object: That is, the present invention aims to provide a semiconductor quantum bit device in which the variation in the characteristics of quantum bit operation is suppressed when multiple quantum bit devices are integrated.

[0007] The present invention is based on the above findings and provides the following means for solving the above problems. That is, <1> A semiconductor quantum bit device comprising at least a support substrate made of a first conductivity type semiconductor layer, a fringe field forming layer formed on the support substrate and composed of either a second conductivity type semiconductor layer of a different conductivity type from the first conductivity type semiconductor layer or a metal layer forming a Schottky barrier with the support substrate, a buried oxide layer formed on the fringe field forming layer, and a quantum dot semiconductor layer formed on the buried oxide layer, in which quantum dots are formed. <2> The semiconductor quantum bit device according to <1>, which has a back gate electrode capable of applying a voltage to the support substrate. <3> The semiconductor quantum bit device according to <1> or <2>, in which the buried oxide layer has a thickness of 10 nm to 100 nm. <4> The semiconductor quantum bit device according to any of <1> to <3>, in which the quantum dot semiconductor layer is formed in the shape of an elongated strip in a top view, and the width of the elongated strip in the short direction is at most 100 nm. <5> The semiconductor quantum bit device according to any one of <1> to <4>, wherein the quantum dot semiconductor layer has a thickness of 2.5 nm to 50 nm. <6> The support substrate has a first conductivity type impurity concentration of 1×10 １９ cm －３ or more, the fringe field forming layer is made of a second conductivity type semiconductor layer, and the second conductivity type impurity concentration is 1×10 １９ cm －３ The semiconductor quantum bit device according to any one of <1> to <5> above. <7> The semiconductor quantum bit device according to <6> above, in which the support substrate is made of Si and the second conductivity type semiconductor layer is made of Si. <8> The semiconductor quantum bit device according to any one of <1> to <7> above, in which the quantum dot semiconductor layer is made of any one of Si, SiGe, and Ge. <9> The buried oxide layer is made of SiO ２ and GeO ２<10> The semiconductor quantum bit device according to any one of <1> to <9>, comprising: a structure in which three barrier gate electrodes and two plunger gate electrodes are formed on a quantum dot semiconductor layer via a gate insulating layer, the two plunger gate electrodes are disposed one by one between two adjacent barrier gate electrodes and spaced apart from the barrier gate electrodes, and quantum dots are formed at two positions on the quantum dot semiconductor layer facing the plunger gate electrodes, respectively; and a static magnetic field application unit capable of applying a static magnetic field to the quantum dots.

[0008] According to the present invention, it is possible to solve the above-mentioned problems in the prior art, and to provide a semiconductor quantum bit device in which the characteristic variations in quantum bit operation are suppressed when multiple quantum bit devices are integrated.

[0009] FIG. 1(a) is a perspective view showing the basic configuration of a semiconductor-type quantum bit device of the present invention. FIG. 1(a) is a cross-sectional view in the y-z plane. FIG. 2(a) is a perspective view showing an example of the configuration of a semiconductor-type spin quantum bit device. FIG. 2(a) is a cross-sectional view in the y-z plane. FIG. 2(a) is an explanatory diagram for explaining the problem of dimensional deviation during SWAP gate operation. FIG. 2(a) is a perspective view showing an example of the configuration of a semiconductor-type charge quantum bit device. FIG. 2(a) is an explanatory diagram for explaining the problem of dimensional deviation during SWAP gate operation. FIG. 2(a) is an explanatory diagram for explaining the problem of dimensional deviation during SWAP gate operation. FIG. 2(a) is an explanatory diagram for explaining the problem of dimensional deviation during SWAP gate operation. FIG. 2(a) is an explanatory diagram for explaining the problem of dimensional deviation during SWAP gate operation. ｓｕｂ = 0.3V” condition (J ｅｘ) is a diagram showing the calculation results. It is a diagram showing the calculation results of SWAP operation fidelity. It is an explanatory diagram showing the relationship between the exchange interaction between two quantum bits and the potential barrier area. It is a diagram showing the potential distribution on the y-z plane in the test target device and the comparative test target device. It is a diagram showing the electron density distribution in bit 1 and bit 2 based on the wave functions of the electrons in bit 1 and bit 2. d Ｂ , h Ｂ , S Ｂ Δd normalized by Ｂ , Δh Ｂ , ΔS Ｂ and ΔW.

[0010] (Semiconductor-Type Quantum Bit Device) First, the basic configuration of a semiconductor-type quantum bit device of the present invention will be described with reference to the drawings. Fig. 1(a) is a perspective view showing the basic configuration of a semiconductor-type quantum bit device of the present invention, and Fig. 1(b) is a cross-sectional view taken along the y-z plane in Fig. 1(a). As shown in Figs. 1(a) and 1(b), a semiconductor-type quantum bit device 10 has at least a support substrate 1, a fringe field-forming layer 2, a buried oxide layer 3, a quantum dot semiconductor layer 4, and a back gate electrode 5.

[0011] The support substrate 1 is composed of a first conductivity type semiconductor layer. There are no particular limitations on the material from which the support substrate 1 is formed, and known semiconductor substrates can be used. Among these, Si (silicon) is preferred from the viewpoints of processability and availability. Examples of impurities that impart the first conductivity type include known impurities such as B (boron) in the case of P-type, and known dopant materials such as P (phosphorus) in the case of N-type. The first conductivity type semiconductor layer can be obtained, for example, by adding these dopant materials to a melt of a semiconductor material such as Si when manufacturing an ingot material by the Czochralski method, and the support substrate 1 can be obtained by cutting this ingot material to the desired size. There are no particular limitations on the concentration of the first conductivity type impurities in the support substrate 1, and it is preferred to use an impurity concentration of 1×10 １９ cm －３ More than 1×10 is preferable. ２０ cm －３If the impurity concentration is too low, the strength of the fringe field obtained by providing the fringe field forming layer 2 may be insufficient. The upper limit of the impurity concentration of the first conductivity type is 1×10 ２１ cm －３ That's about it.

[0012] The fringe field forming layer 2 is a layer formed on the support substrate 1. By forming the fringe field forming layer 2 on the support substrate 1, a fringe field is generated that curves and wraps around from the outer edge corners extending in the longitudinal direction (x direction in the figure) of the top surface of the fringe field forming layer 2 toward the buried oxide layer 3, inward (y direction in the figure) of the top surface of the fringe field forming layer 2.

[0013] One configuration for generating such a fringe field is to use a second conductivity type semiconductor layer as the fringe field forming layer 2, which is a conductivity type different from that of the first conductivity type semiconductor layer. There are no particular limitations on the material for forming the second conductivity type semiconductor layer, and known semiconductor substrates can be used. Among these, Si is preferred from the viewpoints of processability and availability. The impurity imparting the second conductivity type is an impurity of opposite polarity to the impurity imparting the first conductivity type, and examples thereof include known impurities such as B in the case of P-type and known dopant materials such as P in the case of N-type. The second conductivity type semiconductor layer can be obtained by known formation methods such as ion implantation of these dopant materials or formation of an epitaxial growth layer to which a dopant material is added. There are no particular limitations on the concentration of the second conductivity type impurity in the second conductivity type semiconductor layer, and examples thereof include 1×10 １９ cm －３ More than 1×10 is preferable. ２０ cm －３ If the impurity concentration is too low, the strength of the fringe field obtained by providing the fringe field forming layer 2 may be insufficient. The upper limit of the impurity concentration of the second conductivity type is 1×10 ２１ cm －３When the fringe field forming layer 2 is formed of the second conductivity type semiconductor layer, the support substrate 1 and the fringe field forming layer 2 can be formed using a known N / P substrate or P / N substrate, simplifying the manufacturing process. In particular, when the support substrate 1 is formed of Si and the fringe field forming layer 2 is formed of the second conductivity type semiconductor layer made of Si, a general-purpose Si N / P substrate or Si P / N substrate can be used. Note that when the semiconductor-type quantum bit device 10 is configured as an electron-type quantum bit device using electrons as semiconductor carriers, the conductivity type of the first conductivity type semiconductor layer (support substrate 1) is P-type, and the conductivity type of the second conductivity type semiconductor layer (fringe field forming layer 2) is N-type. Conversely, when the semiconductor-type quantum bit device is configured as a hole-type quantum bit device using holes as semiconductor carriers, the conductivity type of the first conductivity type semiconductor layer (support substrate 1) is N-type, and the conductivity type of the second conductivity type semiconductor layer (fringe field forming layer 2) is P-type.

[0014] Another configuration for generating a fringe field is one in which the fringe field-forming layer 2 is a metal layer that forms a Schottky barrier between the support substrate 1 and the fringe field-forming layer 2. To form a Schottky barrier between the support substrate 1 and the fringe field-forming layer 2, the metal layer is configured to have a work function equivalent to that of the second conductivity-type semiconductor layer. That is, in order to generate a fringe field, the metal layer is required to play a role in place of the second conductivity-type semiconductor layer in an N / P substrate configuration or a P / N substrate configuration formed by the support substrate 1 and the second conductivity-type semiconductor layer. For example, using the Fermi level, which governs the work function, when the second conductivity-type semiconductor layer is made of silicon, the Fermi level when the conductivity type is N-type is approximately 4.0 eV to 4.3 eV, and the Fermi level when the conductivity type is P-type is approximately 4.8 eV to 5.1 eV. The Fermi level is similar when the support substrate 1 (the first conductivity-type semiconductor layer) is made of silicon. In view of these relationships, when the support substrate 1 is made up of an N-type silicon semiconductor layer, the material for forming the metal layer (which serves as a substitute for a P-type semiconductor layer) may be a metal material having a Fermi level of approximately 4.6 eV to 6.0 eV, such as Au (gold) or Pt (platinum). When the support substrate 1 is made up of a P-type silicon semiconductor layer, the material for forming the metal layer (which serves as a substitute for an N-type semiconductor layer) may be a metal material having a Fermi level of approximately 3.0 eV to 4.4 eV, such as Al (aluminum) or W (tungsten). The method for forming the metal layer is not particularly limited, and examples thereof include known vapor deposition and CVD methods.

[0015] The buried oxide layer 3 is a layer formed on the fringe field forming layer 2. There are no particular limitations on the buried oxide layer 3, but SiO 2 is preferred because it can be easily formed using existing manufacturing equipment. ２ and GeO ２The buried oxide layer 3 is preferably formed by any one of the methods described above. There are no particular limitations on the method for forming the buried oxide layer 3, and known methods for forming a BOX layer in an SOI substrate can be applied. The thickness of the buried oxide layer 3 (thickness in the vertical direction (z direction in the figure)) is preferably 10 nm to 100 nm. If the thickness is less than 10 nm, the fringe electric field is less likely to penetrate into the buried oxide layer 3, and if the thickness exceeds 100 nm, the penetrated fringe electric field may become uniform, reducing its effect on the quantum dot semiconductor layer 4.

[0016] The quantum dot semiconductor layer 4 is formed on the buried oxide layer 3, and is a layer in which quantum dots are formed. There are no particular limitations on the material for forming the quantum dot semiconductor layer 4, as long as it is a semiconductor material. However, since it can be easily formed using existing manufacturing equipment, it is preferable to form it from any of Si, Ge (germanium), and SiGe, a mixed crystal of these. There are no particular limitations on the method for forming the quantum dot semiconductor layer 4, and known SOI layer formation methods for SOI substrates and methods equivalent thereto can be applied. The quantum dot semiconductor layer 4 may be either the first conductivity type or the second conductivity type, and the matters described for the first conductivity type semiconductor layer and the second conductivity type semiconductor layer can be applied to impart these conductivity types. Furthermore, there are no particular limitations on the impurity concentration in the quantum dot semiconductor layer 4, and it is preferable to form it from any of 1×10 １１ cm －３ ~1 x 10 １８ cm －３ That's about it.

[0017] The quantum dot semiconductor layer 4 is formed in the shape of a long strip when viewed from above (x-y top view in the figure) to form a dot row of multiple quantum dots along the longitudinal direction of the strip (x direction in the figure). The width (W) of the long strip in the short direction (y direction in the figure) is not particularly limited, but is preferably 100 nm or less. If the width (W) exceeds 100 nm, it may be difficult to form the quantum dots. The lower limit of the width (W) is approximately 2 nm. The thickness of the quantum dot semiconductor layer 4 (thickness in the vertical direction (z direction in the figure)) is not particularly limited, but is preferably 2.5 nm to 50 nm. If the thickness is less than 2.5 nm, it may be difficult to obtain the designed device characteristics, and if it exceeds 50 nm, it may be difficult to exert a fringe electric field on the quantum dots due to shielding by the body of the thick quantum dot semiconductor layer 4.

[0018] The quantum dots and quantum bits formed by the quantum dots are formed by arranging and controlling the voltage of electrodes formed on the quantum dot semiconductor layer 4 via a gate insulating layer. By adding these electrode configurations, the configuration of the semiconductor-type quantum bit device 10 can be applied to both a spin quantum bit device and a charge quantum bit device, which will be described later. In addition, the electric field based on the gate insulating layer and the electrodes generates a fringe electric field around the fringe field-forming layer 2.

[0019] The semiconductor-type quantum bit device 10 has a trench structure cut in the x direction from the quantum dot semiconductor layer 4 to a midpoint on the support substrate 1. The trench structure regulates the widths of the buried oxide layer 3 and the fringe field-forming layer 2 in the lateral direction to match the width (W) of the quantum dot semiconductor layer 4 in the lateral direction. The trench structure may be formed by any method, including known lithography processing methods. In the illustrated example of the semiconductor-type quantum bit device 10, multiple quantum dots can be formed along the longitudinal direction (x direction) of the quantum dot semiconductor layer 4, which is formed in a long strip shape when viewed from above, allowing for the formation of a one-dimensional quantum bit array. However, by forming the long strip-shaped quantum dot semiconductor layer 4 and the buried oxide layer 3 and fringe field-forming layer 2 of the same shape in the y direction in addition to the x direction and crossing these long strips, a two-dimensional quantum bit array can also be easily formed. The configuration of these quantum bit arrays can be realized in any structure using known integration techniques, and the technical concept of the present invention is not limited to the illustrated example. Furthermore, although the illustrated example shows a single element structure of a two-qubit gate, large-scale integration is possible by applying a plurality of two-qubit gate structures to the quantum bit string.

[0020] The back gate electrode 5 is an electrode that allows a voltage to be applied to the support substrate 1. The arrangement of the back gate electrode 5 is not limited to the example shown in the figure, but if it is configured as an electrode layer formed on the surface of the support substrate 1 opposite to the surface on which the fringe field forming layer 2 is formed, the wiring structure of the semiconductor quantum bit device 10 can be simplified. The back gate electrode 5 is an optional structure in the semiconductor quantum bit device 10, but as will be verified in the Examples section described later, it has the effect of significantly reducing the characteristic variability of quantum bit operation. There are no particular limitations on the method for forming the back gate electrode 5, and it can be formed by appropriately selecting from known electrode materials and electrode layer forming methods.

[0021] 2(a) and 2(b), an example in which a semiconductor-type spin qubit device of the present invention is configured as a spin qubit device capable of two-qubit gate operation will be described as a first embodiment. Fig. 2(a) is a perspective view showing an example of the configuration of a semiconductor-type spin qubit device, and Fig. 2(b) is a cross-sectional view taken along the y-z plane in Fig. 2(a).

[0022] 2( a) and 2(b), the semiconductor-type spin quantum bit device 20 includes a support substrate 21, a fringe field-forming layer 22, a buried oxide layer 23, a quantum dot semiconductor layer 24, and a back gate electrode 25, which are configured in the same manner as the support substrate 1, fringe field-forming layer 2, buried oxide layer 3, quantum dot semiconductor layer 4, and back gate electrode 5 in the semiconductor-type quantum bit device 10. In addition, three barrier gate electrodes 27a, 27b, and 27c and two plunger gate electrodes 28a and 28b are formed on the quantum dot semiconductor layer 24 via a gate insulating layer 26. The semiconductor-type spin quantum bit device 20 also includes a static magnetic field application unit and an embedded magnet layer 29, which are not shown.

[0023] The plunger gate electrode 28a (28b) is disposed between two adjacent barrier gate electrodes 27a, 27b (27b, 27c) and spaced apart from the barrier gate electrodes 27a, 27b (27b, 27c). The barrier gate electrodes 27a, 27b, 27c and the plunger gate electrodes 28a, 28b act on the behavior of semiconductor carriers (electrons or holes; hereinafter, electrons are used as a model) in the two quantum dot regions of the quantum dot semiconductor layer 24, and quantum dots Q are disposed at two positions facing the plunger gate electrodes 28a, 28b of the quantum dot semiconductor layer 24. １ , Q ２ In the two-qubit gate operation, the plunger gate electrodes 28a and 28b are connected to the quantum dot Q １ , Q ２ The potential of the quantum dot Q is changed to control the number of electrons in the dot. １ , Q ２The quantum dot Q changes the tunnel barrier (potential barrier) between the quantum dots, thereby controlling the exchange interaction between the quantum dots. １ , Q ２ If the distance between the quantum dots is too large, there may be problems in performing two-qubit gate operations. １ , Q ２ It is preferable to appropriately set the factors governing the distance between the plunger gate electrodes 28a and 28b. Specifically, it is preferable that the length of the plunger gate electrodes 28a and 28b in the direction along the longitudinal direction of the quantum dot semiconductor layer 24 (x direction in the drawing) is 2 nm to 100 nm, the length of the barrier gate electrodes 27a, 27b, and 27c in the direction along the longitudinal direction of the quantum dot semiconductor layer 24 is 2 nm to 100 nm, and the separation distance between the plunger gate electrode 28a (28b) and the two adjacent barrier gate electrodes 27a and 27b (27b and 27c) is 2 nm to 50 nm.

[0024] There are no particular limitations on the method for forming the gate insulating layer 26, the barrier gate electrodes 27a, 27b, 27c, and the plunger gate electrodes 28a, 28b, and they can be formed by applying known gate electrode materials and gate electrode formation methods used in classical CMOS transistors, etc.

[0025] The static magnetic field applying unit is a quantum dot Q １ , Q ２ The quantum dots Q are arranged in a direction perpendicular to the magnet layer 29. The static magnetic field is uniform throughout the device. １ , Q ２ The static magnetic field B ０ When is applied, the energy level becomes gμ Ｂ B ０ (μ Ｂ : Bohr magneton, g: g-factor of electron spin) energy difference causes Zeeman splitting, and quantum dot Q １ , Q ２A quantum two-level system represented by two quantum states, a |0> state and a |1> state, is generated in the static magnetic field applying unit. There are no particular limitations on the static magnetic field applying unit, and it can be appropriately selected from members composed of known magnets and coils.

[0026] In the semiconductor spin quantum bit device 20 configured as above, the quantum dot Q １ , Q ２ By changing the tunnel barrier between the quantum dots Q and providing an exchange interaction between the two quantum bits, a SWAP gate operation, which is a two-qubit gate operation, becomes possible. １ , Q ２ The two electrons, one in each atom, overlap each other in their orbits, and affect each other's electron spins. ｅｘ is given as the energy difference between the aligned and staggered spin cases.

[0027] The specific SWAP gate operation is １ , Q ２ By applying an exchange interaction of an appropriate magnitude to the initial two quantum states |0>|1> (or |1>|0>) in the state, the respective quantum states are swapped (SWAP) to be inverted to the two quantum states |1>|0> (or |0>|1>). That is, as shown in FIG. 3, the execution of the SWAP gate operation requires an exchange interaction (J ｅｘ ) is involved, and this exchange interaction (J ｅｘ ) as the standard (J ０ ) and a constant voltage (V ＢＧ At this time, if there is a dimensional deviation (ΔW) in the width (W) of the quantum dot semiconductor layer 24 in the short-side direction, in a configuration in which the dimensional deviation is not taken into consideration, the exchange interaction (J ｅｘ ) change from the standard (J ０ From J ０'), and as a result, the initial two quantum states |0>|1> (or |1>|0>) are not inverted to the two quantum states |1>|0> (or |0>|1>), and the SWAP gate operation results in an error. However, in the semiconductor spin qubit device 20, the fringe field generated by providing the fringe field forming layer 22 has an exchange interaction (J ｅｘ ) to J ０ ' to the standard J ０ Therefore, when a plurality of two-qubit gate structures using semiconductor-type spin qubit devices 20 are integrated, even if there is a dimensional misalignment (ΔW) between them, the compensation action of the fringe field forming layer 22 suppresses the characteristic variations, and a constant voltage (V ＢＧ ) control, SWAP gate operation can be performed with fewer errors. Note that Fig. 3 is an explanatory diagram for explaining the problem of dimensional deviation during SWAP gate operation.

[0028] 2(a) and 2(b) , the description will be continued. The embedded magnet layer 29 is a layer embedded in a recess formed in the bottom (trench groove) of the trench structure of the support substrate 21. The material for forming the embedded magnet layer 29 is not particularly limited, and examples thereof include known magnetic materials that are magnetized by the external magnetic field applied from the static magnetic field application unit. Among these, a magnetic material containing at least one of iron, cobalt, nickel, and manganese is preferred. The method for forming the embedded magnet layer 29 is also not particularly limited, and examples thereof include a combination of a known lithography processing method for forming a recess with a known CVD method, ALD method, CMP method, or the like for forming the embedded magnet layer 29 in the recess.

[0029] The embedded magnet layer 29 is irradiated with the static magnetic field B ０ The magnetization M generated locally in the magnet part is １ , Q ２ The gradient magnetic field B whose magnetic field strength changes spatially at the position ＳＬ In this state, when an AC voltage is applied to the plunger gate electrode 28a (or 28b), the quantum dot Q １(or Q ２ The center of gravity of the electron in the gradient magnetic field B ＳＬ By oscillating in the ０ The semiconductor spin qubit device 20 senses the oscillation of a transverse magnetic field component perpendicular to the quantum mechanical transition between two levels, up spin and down spin. In other words, electron spin manipulation can be controlled by an electrical signal via the plunger gate electrode 28a (or 28b) to perform a one-qubit gate (X gate) operation. The embedded magnet layer 29 is an optional component for performing such one-qubit gate operations. By providing this component, the semiconductor spin qubit device 20 can simultaneously perform one-qubit gate operations in addition to two-qubit gate operations. Any quantum operation can be performed by combining a universal gate set, which combines a one-qubit gate and a two-qubit gate, as a single element. In this sense, the configuration of the semiconductor spin qubit device 20, which allows for the construction of a universal gate set that takes into account characteristic variations, is of extremely important technical significance in realizing any quantum operation. The magnets constituting the embedded magnet layer 29 are quantum dot Qs. １ , Q ２ A gradient magnetic field B is applied to the position ＳＬ The quantum dots Q may be arranged at other positions as long as they form the １ , Q ２ In addition to the spin manipulation method using the Electron Dipole Spin Resonance (EDSR) with the gradient magnetic field of the magnet, one quantum bit gate operation for the quantum dot Q can also be performed by applying microwaves through wiring. １ (or Q ２ ) and quantum dot Q １ (or Q ２ A spin manipulation method using electron spin resonance (ESR), which vibrates electrons in a quantum bit, can also be applied, and further modifications based on the electron spin resonance method can be provided for the semiconductor spin quantum bit device 20.

[0030] [Second embodiment: semiconductor-type charge quantum bit device] Next, an example in which the semiconductor-type quantum bit device of the present invention is configured as a charge quantum bit device will be described as a second embodiment with reference to Figures 4(a) to 4(c). Figure 4(a) is a perspective view showing an example of the configuration of a semiconductor-type charge quantum bit device, and Figures 4(b) and 4(c) are explanatory diagrams for explaining one-qubit gate operation in the semiconductor-type charge quantum bit device.

[0031] 4( a), the semiconductor-type charge quantum bit device 30 has, as its basic structure, a support substrate 31, a fringe field-forming layer 32, a buried oxide layer 33, a quantum dot semiconductor layer 34, and a back gate electrode 35, which are configured similarly to the support substrate 1, fringe field-forming layer 2, buried oxide layer 3, quantum dot semiconductor layer 4, and back gate electrode 5 of the semiconductor-type quantum bit device 10. The semiconductor-type charge quantum bit device 30 also has a gate insulating layer 36, barrier gate electrodes 37a, 37b, 37c, and plunger gate electrodes 38a, 38b, which are configured similarly to the gate insulating layer 26, barrier gate electrodes 27a, 27b, 27c, and plunger gate electrodes 28a, 28b of the semiconductor-type spin quantum bit device 20. Briefly stated, the semiconductor-type charge quantum bit device 30 has a configuration similar to that of the semiconductor-type spin quantum bit device 20, except that the static magnetic field application unit and the embedded magnet layer 29, which are not required for device operation of the charge quantum bit device, are removed.

[0032] The semiconductor-type charge qubit device 30 and the semiconductor-type spin qubit device 20 basically have at least two quantum dots (Q ) formed in a common quantum dot semiconductor layer ( 24 , 34 ). １ , Q ２ ) and the various electrodes corresponding to the quantum operation by these two quantum dots, and a plurality of the structural parts can be integrated in one device. However, the quantum information of the quantum two-level system in the semiconductor-type spin qubit device 20 is transmitted by the quantum dots (Q １ , Q ２ ) is determined by the spin state (up spin, down spin) of the electron in the quantum dot (Q１ , Q ２ That is, in the semiconductor-type charge quantum bit device 30, the state of an electron present in one of the two quantum dots (Q １ , Q ２ ) structure, and one electron is introduced into the quantum dot (Q １ , Q ２ ) is present in either

[0033] Specifically, first, the voltages of the barrier gate electrodes 27a, 27b, and 27c are adjusted to form quantum dots, and then the voltages of the plunger gate electrodes 38a and 38b are adjusted to control the quantum dots so that one electron is present in one of the quantum dots (see FIG. 4B). Next, a pulse voltage is applied to the plunger gate electrodes 38a and 38b for a certain period of time to form two quantum dots (Q １ , Q ２ ) are aligned, and electrons are controlled to be able to move between the levels by tunneling only during that time (see FIG. 4(c)). As a result, in the semiconductor spin qubit device 20, electrons are able to move between the quantum two-level system (the left and right quantum dots Q １ , Q ２ ) and the quantum information can be defined by the two levels and their superposition state. １ , Q ２ ) to perform one-qubit gate (X-gate) operations.

[0034] Here, the operation time of the X gate operation (see FIG. 4(c)) is the time required for the two quantum dots (Q １ , Q ２) and is determined based on the reference value when there is no dimensional deviation (ΔW) in the width (W) in the short-side direction of the quantum dot semiconductor layer 34. In reality, when one-qubit gates (X gates) are integrated using a common electrode structure using a plurality of quantum dot semiconductor layers 34 (X gate arrays), each X gate structure will have some degree of dimensional deviation (ΔW). As a result, in a configuration that does not take this dimensional deviation (ΔW) into consideration, the magnitude of the potential barrier will vary from the reference value, causing variations in characteristics between different X gates and resulting in errors in the calculation results. However, in the semiconductor-type charge quantum bit device 30, the fringe field generated by providing the fringe field-forming layer 32 compensates for the deviation in the magnitude of the potential barrier due to the dimensional deviation (ΔW) so that it approaches the reference value. In other words, the starting point for considering the characteristic deviation in the semiconductor-type charge quantum bit device 30 is the size of the potential barrier between the two quantum dots (Q １ , Q ２ ) deviates from a standard, which is the same origin as the reason for considering the characteristic variations in semiconductor-type spin qubit device 20, and therefore, for the same reasons as those explained for semiconductor-type spin qubit device 20, the deviation in the magnitude of the potential barrier from the standard is subject to a compensation action by the fringe electric field. Therefore, even if semiconductor-type charge qubit device 30 is configured by integrating multiple X-gate structures with dimensional variations (ΔW), the compensation action by fringe electric field forming layer 32 suppresses the characteristic variations, and X-gate operation can be performed with fewer errors.

[0035] In order to examine the effectiveness and preferable conditions of the present invention, simulation tests were carried out on the quantum mechanical interaction (exchange interaction) between two quantum bits and the fidelity of the two-qubit gate (SWAP gate) operation.

[0036] <Test Conditions> The simulation test was carried out using the MOS-type Si spin qubit device (test target device) shown in Figures 5(a) to 5(c) as a basic assumption. Note that Figure 5(a) is a perspective view showing an overview of the semiconductor-type spin qubit device related to the settings for the simulation test, Figure 5(b) is an explanatory diagram for explaining the configuration of the y-z plane in Figure 5(a), and Figure 5(c) is a top view for explaining the configuration of the x-y plane in Figure 5(a).

[0037] This test target device is configured in accordance with the semiconductor quantum bit device according to the basic configuration shown in Fig. 1, and includes a support substrate (N / P substrate) in which a P-type support layer (P substrate) and an N-type support layer (N dope) are stacked on a back gate electrode, a BOX layer and an SOI layer are stacked on the support substrate, and a PG (plunger gate) electrode and a BG (barrier gate) electrode are formed at predetermined positions on the SOI layer via a gate oxide layer. The back gate electrode is composed of an Al (aluminum) electrode, and receives a voltage (V ｓｕｂ The P-type support layer has an acceptor density of 1×10 ２０ cm －３ The N-type support layer is set as a Si layer having a donor density of 2×10 ２０ cm －３The P-type support layer and the N-type support layer are set as Si layers with a thickness of 5 nm in the z direction. A trench structure is provided in these P-type support layers and the trench groove formed from the top surface of the N-type support layer along the z direction toward the bottom surface of the P-type support layer is set to a depth of 100 nm. The width (W) in the y direction of the P-type support layer and the N-type support layer remaining after the trench groove is formed is set to 48 nm. As a result, the width (W) in the y direction of the BOX layer, the SOI layer, the gate oxide layer, the PG electrode, and the BG electrode formed on the N-type support layer is also set to 48 nm. In this simulation test, several numerical changes (ΔW) are made based on this y direction width (W = 48 nm) to confirm the effects. The BOX layer is formed as a buried oxide layer using SiO ２ The SOI layer is a silicon layer formed as a silicon on insulator (Si layer) on an insulating layer, and its thickness in the z direction is set to 12 nm. In this SOI layer, quantum dots constituting two quantum bits (Bit 1 and Bit 2) are formed directly below the PG electrode in the z direction by controlling the voltage applied to the PG electrode and the BG electrode. The gate oxide layer is made of SiO ２ The thickness in the z direction is set to 10 nm. The BG electrodes are made of Al (aluminum) electrodes, and as shown in FIG. 5(c), three BG electrodes are arranged spaced apart from each other in the x direction, with one BG electrode arranged at the center between the two BG electrodes on both ends. The length (L ＢＧ ) are all set to 36 nm. The PG electrodes are made of Al (aluminum) electrodes, and as shown in FIG. 5C, two of them are arranged in the x direction, with one at the center of each of the two adjacent BG electrodes. The length (L ＰＧ) are all set to 48 nm. The PG electrode and the BG electrode are spaced apart from each other by a distance of 6 nm in the x direction (see FIG. 5(c)). The P-type support layer, located above the trench groove, is covered with an insulating material. In this simulation test, a static magnetic field of up to about 0.1 T is assumed as the condition for the magnetic field applied to the quantum bit.

[0038] In the test device configured in this manner, a SWAP operation can be performed that uses quantum mechanical exchange interaction to invert the quantum state of the two electron states (up spin, down spin) in the two quantum bits, bit 1 and bit 2, formed in the SOI layer (for example, inverting from the |0>|1> state to the |1>|0> state).

[0039] <Simulator> The simulation test was conducted using a simulator (see Reference 1 for details) that is a TCAD simulator developed by the applicant and equipped with a function to analyze the quantum state of semiconductor quantum bits. Reference 1: H. Asai et al., EDTM Tech. Dig. 2021, p. 238.

[0040] <Verification of Variation in Exchange Interaction> For each of the test target device and a comparative test target device in which the N-type support layer (N dope) is not formed in the test target device and the region where the N-type support layer is formed is set to be part of the P-type support layer (P substrate), bit 1 and bit 2 are formed in the SOI layer by controlling the voltage between the PG electrode and the BG electrode, and the exchange interaction (J ｅｘ ) was calculated using the simulator. Here, for the test device, there were two conditions: an "N / P substrate" condition in which no voltage was applied to the back gate electrode, and an "N / P substrate & V" condition in which a voltage of 0.3 V was applied to the back gate electrode. ｓｕｂFor the comparative test device, calculations were performed under "P substrate" conditions in which no voltage was applied to the back gate electrode. For each condition, calculations were performed under three conditions: a basic condition (ΔW=0) in which the width W was 48 nm shown in FIG. 5(b) and size-change conditions in which the width W was changed in two ways, ±3 nm (ΔW=-3 nm, ΔW=+3 nm).

[0041] As a specific method for calculating the exchange interaction, first, following Reference 1, the wave functions of electrons in bits 1 and 2 were calculated so that the electron distribution within the quantum dot region in the SOI layer and the carrier distribution outside the quantum dot region were self-consistent. Next, using the obtained wave functions, the exchange interaction between bits 1 and 2 was calculated using a method similar to the Heitler-London method for molecular orbitals. This calculation method was performed in accordance with Reference 2 below, by calculating the exchange interaction between bits 1 and 2 using the following steps (a) and (b). The energy difference between the spin singlet state and the triplet state in (b) corresponds to the exchange interaction. (a) Extract the wave functions of the orbitals into which electrons enter for bits 1 and 2, respectively. (b) Construct a Hamiltonian for the two-electron state taking spin into account, and calculate the energy difference between the spin singlet state and the triplet state from its diagonalization. Reference 2: Physical Review B, 59 2070 (1999).

[0042] The "P substrate" condition in the comparative test target device, and the "N / P substrate" condition and "N / P substrate & V" condition in the test target device ｓｕｂ = 0.3V” condition (J ｅｘ) are shown in Figure 6. As shown in the lower part of Figure 6, under the "P substrate" condition in the comparative test target device, the exchange interaction under the two size change conditions (ΔW = -3 nm, ΔW = +3 nm) varies by as much as ±35% compared to the exchange interaction under the basic condition (ΔW = 0). On the other hand, as shown in the center of Figure 6, under the "N / P substrate" condition in the test target device, the range of variation is limited to ±20%, and as shown in the upper part of Figure 6, under the "N / P substrate & V" condition in the test target device, the range of variation is limited to ±20%. ｓｕｂ In this way, in FIG. 6, the fluctuation range of the exchange interaction due to the influence of the two size change conditions (ΔW=-3 nm, ΔW=+3 nm) narrows in the order of the left, center, and right sides. In addition, the exchange interaction obtained under the size change conditions in this order is smaller than that of the basic condition (ΔW=0). ｅｘ This result indicates that in the test device, the exchange interaction (J ｅｘ ) can be suppressed by introducing an "N / P substrate," and furthermore, this suppression effect becomes more pronounced when a voltage is applied to the back gate electrode.

[0043] <Verification of fidelity> As explained with reference to FIG. 6, a dimensional error of only 3 nm is enough to confirm a large fluctuation in the exchange interaction. Therefore, the influence of this fluctuation in the exchange interaction on the device is of great interest. In this simulation test, the degree of inaccuracy in the quantum operation of a device with a dimensional error compared to that of a device with the correct dimensions as a reference is measured as the "gate operation fidelity F" expressed by the following formula (1): Ｇ The results were evaluated using the index "

[0044] However, in the formula (1), ρ ０ denotes a density matrix showing the initial two-electron state, U denotes a quantum operation in a device with correct dimensions, and K denotes a quantum operation in a device with dimensional errors. Here, the effect of decoherence is ignored and the fidelity of the quantum gate operation to the quantum mechanical pure state is evaluated. In the above formula (1), the fidelity FＧ takes a value between 0 and 1, and when K = U (no dimensional error), it represents ideal gate operation, and the fidelity F Ｇ becomes 1.

[0045] Fidelity F Ｇ First, the test target device and the comparison test target device that are the objects of calculation are two-qubit spin qubit devices, and the Hamiltonian of the two-qubit state in the two-qubit spin qubit device can be described by the following equations (2) to (4).

[0046] In these formulas, g represents the g-factor of the electron in the quantum dot, μ represents the Bohr magneton, and B ｚ，ｉ denotes the magnetic field applied to the i-th (where i is 1 or 2) qubit, and σ ｘ，ｉ , σ ｙ，ｉ , σ ｚ，ｉ , denotes the Pauli operator acting on the i-th (where i is 1 or 2) quantum bit, and J denotes the exchange interaction between two quantum bits.

[0047] Next, the SWAP operation in the two-qubit spin qubit device is performed in the Hamiltonian over a fixed time τ (= h / 2J ０ ) to the BG (barrier gate) electrode, and J(t) = J ０ That is, in this case, the quantum state of the two quantum bits changes so that |0>|1>, where bit 1 is in the 0 state and bit 2 is in the 1 state, swaps (SWAPs) to |1>|0>, where bit 1 is in the 1 state and bit 2 is in the 0 state.

[0048] From this relationship, the SWAP operation of a device with the correct dimensions as a reference can be performed by applying an ideal square wave pulse voltage of τ = h / 2J when the initial quantum state of the two quantum bits is |0>|1>. ０ In this case, the quantum operation K in a device with dimensional errors can be defined as J for a device with correct dimensions. ０ and J of the device with dimensional error ０', and the fidelity F Ｇ The above equation (1) for finally reduces to the simple equations expressed by the following equations (5) and (6).

[0049]

[0050] Therefore, for the test target device and the comparative test target device, (1) when the dimensions are correct (W=0), τ=h / 2J ０ The exchange interaction J obtained by applying a pulse voltage to the BG (barrier gate) electrode for a period of time ０ (2) τ=h / 2J when there is a dimensional error. ０ The exchange interaction J obtained by applying a pulse voltage to the BG (barrier gate) electrode for a period of time ０ (3) calculating the obtained exchange interaction J ０ , J ０ ', and the gate operation fidelity F Ｇ This F Ｇ can be called SWAP operation fidelity, since the operation to be performed is a SWAP operation.

[0051] The calculation of SWAP operation fidelity was performed under the "P substrate" condition and the "P substrate & V" condition in the comparative test device. ｓｕｂ =0.3V” condition, and the “N / P substrate” condition and “N / P substrate &V” condition in the test target device. ｓｕｂ The test was carried out under four conditions: "P substrate & V = 0.3V". ｓｕｂ The "=0.3V" condition is a condition in which a voltage of 0.3V is applied to the back gate electrode in the comparative test target device. Figure 7 shows the calculation results of the SWAP operation fidelity. Generally, a fidelity of 99% or more is the standard required for quantum error correction (see Reference 3). However, as shown in Figure 7, under the "N / P substrate" condition in the test target device, the fidelity is 99% or more, which is lower than the "P substrate" condition and the "P substrate & V" condition in the comparative test target device. ｓｕｂCompared with the "=0.3V" condition, a SWAP operation fidelity of 99% or more can be achieved with a wider range of dimensional variations (ΔW). ｓｕｂ Under the "=0.3V" condition, a SWAP operation fidelity of 99% or more can be achieved with a significantly wider range of dimensional variation (ΔW) compared to other conditions, and the SWAP operation fidelity is dramatically improved. ｓｕｂ Under the "V = 0.3V" condition, a dimensional variation (ΔW) of ±5 nm is tolerated with 99% or higher fidelity. This significantly exceeds the 0.9 nm 3σ gate dimension variation of cutting-edge semiconductor manufacturing technology (the target value for 2022 in the IEEE's International Roadmap for Devices and Systems (IRDS)), enabling large-scale integration of more than 1 million qubits. This dramatic improvement in SWAP operation fidelity due to the application of a voltage to the backgate electrode was not observed in the comparative test device, clearly indicating the influence of the "N / P substrate" condition of the test device. Reference 3: A.G. Fowler et al., Phys. Rev. A, 86, 032324 (2012).

[0052] <Consideration of the principle of suppressing characteristic variations> Based on these simulation results, the "N / P substrate" condition and the "N / P substrate & V" condition for the above-mentioned test target device were ｓｕｂ Further verification was carried out to determine why the "=0.3V" condition can suppress characteristic variations due to the influence of dimensional variations.

[0053] First, let us consider the cause of characteristic variations due to the influence of dimensional variations (ΔW). The exchange interaction between two quantum bits in a semiconductor-type two-qubit device is affected by the potential barrier area between the two quantum bits, as shown in FIG. 8. FIG. 8 is an explanatory diagram showing the relationship between the exchange interaction between two quantum bits and the potential barrier area. If there is a dimensional variation (ΔW) in the width of the SOI layer, the energy levels of the two quantum bits change. This change is also caused by the potential barrier height (hＢ ) and the distance between the bottom of the potential of one qubit and the bottom of the potential of another qubit (d Ｂ ) and the potential barrier (h Ｂ ) and distance (d Ｂ ) and the potential barrier area (S Ｂ This causes a change in the potential barrier area (S Ｂ ) causes an exponential change in the exchange interaction between the two quantum bits. That is, the dimensional variation (ΔW) is proportional to the variation in the potential barrier area (ΔS Ｂ ), which in turn causes an exponential change in the exchange interaction between the two quantum bits. In other words, this finding indicates that even if there is a dimensional variation (ΔW), the variation in the potential barrier area (ΔS Ｂ ) can be suppressed, it means that the change in the exchange interaction between the two quantum bits can be suppressed. In order to obtain the calculation results shown in Figure 8, the potential Ψ is weighted by the electron density ρ in the quantum dot to extract the effective potential distribution between the two quantum bits, and the effective one-dimensional potential distribution Ψ in the direction along the bit string of the quantum bits (x direction) is １Ｄ The calculation results shown in FIG. 8 are the two-dimensional electron density (ρ ２Ｄ Effective one-dimensional potential distribution Ψ weighted by (y, z) １Ｄ (x) is calculated by the following equation (8), and the obtained effective one-dimensional potential distribution Ψ １Ｄ From (x), the potential barrier (h Ｂ ) and the distance between the bottom of the potential of one qubit and the bottom of the potential of another qubit (d Ｂ ) and the potential barrier area (S Ｂ ) is calculated.

[0054]

[0055] Next, even if there is a dimensional variation (ΔW), the variation in the potential barrier area (ΔS Ｂ) can be suppressed, the change in the exchange interaction between the two quantum bits can be suppressed. This will be verified with reference to FIG. 9 . FIG. 9 shows the potential distributions in the y-z plane for the test device and the comparative test device, calculated by the above calculation. In the comparative test device, as shown on the left side of FIG. 9 , it is confirmed that the quantum bit region of the SOI layer is subjected to linear potential control from the P-type support layer. On the other hand, in the test device, as shown on the right side of FIG. 9 , it is confirmed that the quantum bit region of the SOI layer is subjected to potential control in a manner that wraps around from the corners of the outer edge of the upper surface of the N-type support layer toward the interior of the upper surface. This is thought to be due to the fringe field generated by the N / P substrate, which modulates the quantum bit region. That is, the fringe field, like the potential distribution shown in FIG. 9 , is generated in a manner that wraps around from the corners of the outer edge of the upper surface of the N-type support layer toward the interior of the upper surface, and therefore, it can be thought that potential modulation is applied to the quantum bit region in this manner. The fringe electric field varies depending on the variation in the potential barrier area (ΔS Ｂ That is, since the strength of the fringe electric field varies depending on the width W, the variation in the potential barrier area (ΔS Ｂ ) as the reference potential barrier area (S Ｂ The fringing fields compensate for the potential barrier modulation so that the potential barrier approaches

[0056] Next, "N / P substrate & V ｓｕｂ The reason why the SWAP operation fidelity is dramatically improved under the "V = 0.3 V" condition will be examined. FIG. 10 shows the electron density distributions in bit 1 and bit 2 based on the wave functions of the electrons in bit 1 and bit 2 obtained during the calculation of the exchange interaction. As shown in the upper part of FIG. 10, in the "N / P substrate" where no voltage is applied to the back gate electrode, the electrons in bit 1 and bit 2 are attracted to the plunger gate electrode side, resulting in an angular electron density distribution biased toward the interface with the gate oxide layer. On the other hand, in the "N / P substrate & V ｓｕｂ= 0.3 V condition, the electrons in bit 1 and bit 2 are attracted to the back gate electrode side, resulting in an electron density distribution in which the electrons move from the upper surface side of the SOI layer to the center. As a result, the action of compensating for potential barrier modulation by the "N / P substrate" in a manner that wraps around toward the inside of the N-type support layer and the action of eliminating bias in the electron density distribution in the thickness direction (z direction) of the N-type support layer act in a superimposed manner, and it is thought that this further minimizes the influence of the dimensional variation (ΔW) in width W on the potential of bit 1 and bit 2.

[0057] Finally, d Ｂ , h Ｂ , S Ｂ Δd normalized by Ｂ , Δh Ｂ , ΔS Ｂ The relationship between ΔW and Δh is shown in Fig. 11. As shown in Fig. 11, under the "P substrate" condition (P sub.) in the comparative test device, as the variation in ΔW increases, Δh Ｂ / h Ｂ and ΔS Ｂ / S Ｂ While the value of Δh changes significantly under the "N / P substrate" condition (N / P sub.) in the device under test, Ｂ / h Ｂ and ΔS Ｂ / S Ｂ In particular, the change in "N / P substrate & V ｓｕｂ = 0.3V” condition (N / P sub. & V sub = 0.3V), Δh Ｂ / h Ｂ and ΔS Ｂ / S Ｂ This result is consistent with the results of previous studies and provides solid evidence supporting the effectiveness of the present invention.

[0058] 1, 21, 31 Support substrate 2, 22, 32 Fringe field forming layer 3, 23, 33 Buried oxide layer 4, 24, 34 Quantum dot semiconductor layer 5, 25, 35 Back gate electrode 10 Semiconductor type quantum bit device 20 Semiconductor type spin quantum bit device 27a, 27b, 27c, 37a, 37b, 37c Barrier gate electrode 28a, 28b, 38a, 38b Plunger gate electrode 29 Buried magnet layer 30 Semiconductor type charge quantum bit device

Claims

1. A support substrate including at least a first conductive type semiconductor layer; a fringe field forming layer formed on the support substrate and composed of either a second conductive type semiconductor layer having a conductive type different from that of the first conductive type semiconductor layer or a metal layer forming a Schottky barrier with the support substrate; a buried oxide layer formed on the fringe field forming layer; a quantum dot semiconductor layer formed on the buried oxide layer, in which quantum dots are formed; A semiconductor quantum bit device comprising:

2. 2. The semiconductor quantum bit device according to claim 1, further comprising a back gate electrode capable of applying a voltage to the support substrate.

3. 3. The semiconductor quantum bit device according to claim 1, wherein the buried oxide layer has a thickness of 10 nm to 100 nm.

4. 3. The semiconductor-type quantum bit device according to claim 1, wherein the quantum dot semiconductor layer is formed in a long strip shape when viewed from above, and the width of the long strip in the short direction is at most 100 nm.

5. 3. The semiconductor quantum bit device according to claim 1, wherein the quantum dot semiconductor layer has a thickness of 2.5 nm to 50 nm.

6. The first conductive type impurity concentration of the support substrate is 1×10 １９ cm －３ or more, the fringe field forming layer is made of a second conductive type semiconductor layer, and the second conductive type impurity concentration is 1×10 １９ cm －３ 3. The semiconductor quantum bit device according to claim 1 or 2.

7. 7. The semiconductor quantum bit device according to claim 6, wherein the support substrate is made of Si, and the second conductive type semiconductor layer is made of Si.

8. 3. The semiconductor quantum bit device according to claim 1, wherein the quantum dot semiconductor layer is made of any one of Si, SiGe and Ge.

9. The buried oxide layer is SiO ２ and GeO ２ 3. The semiconductor quantum bit device according to claim 1, wherein the semiconductor quantum bit device is formed of any one of the following:

10. At least, three barrier gate electrodes and two plunger gate electrodes are formed on a quantum dot semiconductor layer via a gate insulating layer, the two plunger gate electrodes are disposed between two adjacent barrier gate electrodes, one at a time, and spaced apart from the barrier gate electrodes, and quantum dots are formed at two positions facing the plunger gate electrodes of the quantum dot semiconductor layer, respectively; 3. The semiconductor quantum bit device according to claim 1, further comprising a static magnetic field application unit capable of applying a static magnetic field to the quantum dot.