Semiconductor device

Abstract

This semiconductor device (10) is provided with: a semiconductor layer (12); a cell trench (14) which is formed in the shape of a mesh in the semiconductor layer (12), while comprising a plurality of first trenches (24) that extend in a first direction when viewed in plan and a plurality of second trenches (26) that extend in a second direction that intersects with the first direction when viewed in plan so that the plurality of first trenches (24) and the plurality of second trenches (26) intersect with and in communication with each other; an insulating layer (16) which is formed on the semiconductor layer (12); a plurality of gate electrodes (28) which are respectively buried in the plurality of first trenches (24) by the intermediary of the insulating layer (16), while extending in the first direction; and a plurality of field plate electrodes (30) which are respectively buried in the plurality of second trenches (26) by the intermediary of the insulating layer (16), while extending in the second direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device having a plurality of trench gate structures formed in a stripe pattern, each of which includes a gate trench and two electrodes embedded in the gate trench and spaced apart in the depth direction.

[0003] Japanese Patent Application Laid-Open No. 2021-125649

[0004] When the gate electrode and the field plate electrode are embedded separately in the gate trench, the gate electrode and the field plate electrode extend into the gate trench while facing each other. If the capacitance generated by the gate electrode and the field plate electrode is relatively large, undesirable behavior of the semiconductor device, such as self-turn-on, may occur.

[0005] A semiconductor device according to one aspect of the present disclosure includes: a semiconductor layer; cell trenches formed in the semiconductor layer and arranged in a mesh pattern, the cell trenches including a plurality of first trenches extending in a first direction in a planar view and a plurality of second trenches extending in a second direction intersecting the first direction in a planar view, the plurality of first trenches and the plurality of second trenches intersecting and communicating with each other; an insulating layer formed on the semiconductor layer; a plurality of gate electrodes embedded in the plurality of first trenches via the insulating layer and extending in the first direction; and a plurality of field plate electrodes embedded in the plurality of second trenches via the insulating layer and extending in the second direction.

[0006] According to the semiconductor device of the present disclosure, the capacitance generated by the gate electrode and the field plate electrode can be reduced.

[0007] FIG. 1 is a schematic cross-sectional perspective view of an exemplary semiconductor device according to one embodiment. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 2. FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. 2. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 2. FIG. 6 is a schematic cross-sectional view of the semiconductor device taken along line F6-F6 in FIG. 2. FIG. 7 is a schematic cross-sectional perspective view of an exemplary semiconductor device according to a comparative example. FIG. 8 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7. FIG. 9 is a schematic plan view of a semiconductor device according to a modified example.

[0008] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] FIG. 1 is a schematic cross-sectional perspective view of an exemplary semiconductor device 10 according to one embodiment. FIG. 2 is a schematic plan view of the semiconductor device 10. The semiconductor device 10 may be, for example, a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) having a trench gate structure. The semiconductor device 10 includes a semiconductor layer 12, a cell trench 14 formed in the semiconductor layer 12, and an insulating layer 16 formed on the semiconductor layer 12. As shown in FIG. 1, the semiconductor layer 12 may include a semiconductor substrate 18 and an epitaxial layer 20, and the cell trench 14 may be formed in the epitaxial layer 20. In this embodiment, the semiconductor substrate 18 may be a silicon (Si) substrate. The epitaxial layer 20 may be a Si epitaxial layer. A top surface 12A of the semiconductor layer 12 may be included in the epitaxial layer 20, while a bottom surface 12B of the semiconductor layer 12 may be included in the semiconductor substrate 18. The insulating layer 16 may be formed of silicon oxide (SiO ２ ) layer and / or silicon nitride (SiN) layer.

[0011] 1 and 2 show a cross-sectional view and a plan view, respectively, of the semiconductor device 10 taken along the upper surface 12A of the semiconductor layer 12 (see line F1-F1 in FIG. 3). Note that, as shown in FIG. 3, the insulating layer 16 is formed not only in the cell trench 14 but also on the upper surface 12A of the semiconductor layer 12.

[0012] The semiconductor device 10 may further include a drain electrode 22 formed on the bottom surface 12B of the semiconductor layer 12. The drain electrode 22 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0013] (Details of Cell Trench) As shown in FIGS. 1 and 2 , the cell trench 14 includes a plurality of first trenches 24 extending in a first direction in a plan view and a plurality of second trenches 26 extending in a second direction intersecting the first direction in a plan view. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIGS. 1 and 2 is a direction perpendicular to the surface of the semiconductor layer 12. As used herein, the term "plan view" refers to viewing the semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise. The first direction is the longitudinal direction of the first trenches 24, and the second direction is the longitudinal direction of the second trenches 26. In the example shown in FIGS. 1 and 2 , the first direction may be the Y-axis direction, and the second direction may be the X-axis direction. Therefore, in the illustrated example, the angle between the first direction and the second direction is 90 degrees. As will be described later with reference to FIG. 9 , the first direction and the second direction do not necessarily have to coincide with the Y-axis direction and the X-axis direction, respectively. The cell trench 14 has an opening in the upper surface 12A of the semiconductor layer 12 and has a depth in the Z-axis direction. The multiple first trenches 24 and the multiple second trenches 26 intersect and communicate with each other. As a result, the cell trenches 14 are arranged in a mesh pattern.

[0014] As shown in FIG. 2 , the cell trench 14 includes a plurality of intersection regions 14A where a plurality of first trenches 24 and a plurality of second trenches 26 intersect with each other, and a plurality of non-intersection regions 14B where a plurality of first trenches 24 and a plurality of second trenches 26 do not intersect with each other. The plurality of first trenches 24 may be arranged in a stripe pattern. In one example, each of the plurality of first trenches 24 has a width W1. The width W1 of the first trench 24 corresponds to the dimension of the first trench 24 in the short direction (i.e., the direction perpendicular to the first direction) in a plan view. The plurality of first trenches 24 may be arranged parallel to each other at a constant interval S1. Similarly, the plurality of second trenches 26 may be arranged in a stripe pattern. In one example, each of the plurality of second trenches 26 has a width W2. The width W2 of the second trench 26 corresponds to the dimension of the second trench 26 in the short direction (i.e., the direction perpendicular to the second direction) in a plan view. The plurality of second trenches 26 can be arranged parallel to one another at regular intervals S2.

[0015] In one example, the interval S1 between the first trenches 24 may be larger than the width W1 of each of the first trenches 24. In another example, the interval S2 between the second trenches 26 may be larger than the width W2 of each of the second trenches 26.

[0016] In one example, the width W2 of each of the multiple second trenches 26 may be larger than the width W1 of each of the multiple first trenches 24. Also, in one example, the interval S2 at which the multiple second trenches 26 are arranged may be larger than the interval S1 at which the multiple first trenches 24 are arranged. Therefore, the pitch P2 of the second trenches 26 (the sum of the width W2 and the interval S2) may be larger than the pitch P1 of the first trenches 24 (the sum of the width W1 and the interval S1). In one example, the pitch P1 of the first trenches 24 may be approximately the same as the interval S2 of the second trenches 26.

[0017] 1 and 2 , the semiconductor device 10 further includes a plurality of gate electrodes 28 embedded in the plurality of first trenches 24 with the insulating layer 16 interposed therebetween. The plurality of gate electrodes 28 extend in a first direction. The semiconductor device 10 also includes a plurality of field plate electrodes 30 embedded in the plurality of second trenches 26 with the insulating layer 16 interposed therebetween. The plurality of field plate electrodes 30 extend in a second direction. In one example, the gate electrodes 28 and the field plate electrodes 30 may be formed from conductive polysilicon. In another example, the gate electrodes 28 and the field plate electrodes 30 may be formed from any other metallic material.

[0018] The multiple gate electrodes 28 are located in the cell trench 14 above the multiple field plate electrodes 30 (closer to the upper surface 12A of the semiconductor layer 12). The multiple gate electrodes 28 are separated from the multiple field plate electrodes 30 by the insulating layer 16. Each of the multiple gate electrodes 28 passes above the multiple field plate electrodes 30, thereby intersecting with the multiple field plate electrodes 30. Each of the multiple field plate electrodes 30 passes below the multiple gate electrodes 28, thereby intersecting with the multiple gate electrodes 28.

[0019] 2 , in each of the plurality of intersection regions 14A, one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30. In each of the plurality of non-intersection regions 14B, one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is disposed in the cell trench 14.

[0020] The semiconductor layer 12 may include a plurality of mesh regions 32 (see FIG. 2 ) surrounded by cell trenches 14 arranged in a mesh pattern. Each of the plurality of mesh regions 32 may have a rectangular shape in a plan view. The semiconductor device 10 may further include a plurality of source contact plugs 34 arranged in the plurality of mesh regions 32, respectively. Details of the source contact plugs 34 will be described later with reference to FIG. 3 .

[0021] (Cross-sectional structure of semiconductor device) Fig. 3 is a schematic cross-sectional view of the semiconductor device 10 taken along line F3-F3 in Fig. 2. Fig. 3 shows a cross section of the first trench 24 in the XZ plane in the non-intersection region 14B (see Fig. 2), which corresponds to a cross section of the first trench 24 taken along the short direction.

[0022] The epitaxial layer 20 includes a drift region 36 formed on the semiconductor substrate 18 corresponding to the drain region, a body region 38 formed on the drift region 36, and a source region 40 formed on the body region 38.

[0023] The drain region formed by the semiconductor substrate 18 may be an n-type region containing n-type impurities. The n-type impurity concentration of the semiconductor substrate 18 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The semiconductor substrate 18 may have a thickness of 50 μm or more and 450 μm or less.

[0024] The drift region 36 may be an n-type region containing n-type impurities at a concentration lower than that of the semiconductor substrate 18 (drain region). The n-type impurity concentration of the drift region 36 is 1×10 １５ cm －３ 1x10 or more１８ cm －３ The drift region 36 may have a thickness of 1 μm or more and 25 μm or less.

[0025] The body region 38 may be a p-type region containing p-type impurities. The p-type impurity concentration of the body region 38 may be 1×10 １６ cm －３ 1x10 or more １８ cm －３ The body region 38 may have a thickness of not less than 0.2 μm and not more than 1.0 μm.

[0026] The source region 40 may be an n-type region containing n-type impurities at a higher concentration than the drift region 36. The n-type impurity concentration of the source region 40 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The source region 40 may have a thickness of 0.1 μm or more and 1 μm or less.

[0027] In this disclosure, n-type is also referred to as a first conductivity type, and p-type is also referred to as a second conductivity type. The n-type impurity may be, for example, phosphorus (P), arsenic (As), etc. The p-type impurity may be, for example, boron (B), aluminum (Al), etc.

[0028] The first trench 24 has an opening in the upper surface 12A of the semiconductor layer 12 and has sidewalls 24A and a bottom wall 24B. The first trench 24 penetrates the source region 40 and the body region 38 of the epitaxial layer 20 to reach the drift region 36. Therefore, the bottom wall 24B of the first trench 24 is adjacent to the drift region 36. The first trench 24 may have a depth of 1 μm or more and 10 μm or less. The depth of the first trench 24 may correspond to the distance in the Z-axis direction from the upper surface 12A of the semiconductor layer 12 to the bottom wall 24B of the first trench 24.

[0029] The sidewall 24A of the first trench 24 may extend in the Z-axis direction (a direction perpendicular to the top surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the sidewall 24A may be inclined with respect to the Z-axis direction so that the width of the first trench 24 decreases toward the bottom wall 24B. In this case, the width W1 of the first trench 24 shown in FIG. 2 may be the width of the first trench 24 at the position of the top surface 12A of the semiconductor layer 12. In addition, the bottom wall 24B of the first trench 24 does not necessarily have to be flat, and may be curved in part or entirely, for example.

[0030] The gate electrode 28 is buried in the first trench 24 via the insulating layer 16. The gate electrode 28 is separated from the semiconductor layer 12 (epitaxial layer 20) by the insulating layer 16. A gate voltage may be applied to the gate electrode 28. At least a portion of the gate electrode 28 may be disposed to face the body region 38 in the second direction with the insulating layer 16 interposed therebetween.

[0031] The gate electrode 28 may include an upper surface 28A covered with the insulating layer 16 and a bottom surface 28B opposite the upper surface 28A. In the non-intersection region 14B included in the first trench 24, the insulating layer 16 is buried between the bottom surface 28B of the gate electrode 28 and the bottom wall 24B of the first trench 24, and no field plate electrode 30 (see FIG. 1) is disposed therein.

[0032] The top surface 28A of the gate electrode 28 may be located lower than the top surface 12A of the semiconductor layer 12 in the Z-axis direction. The bottom surface 28B of the gate electrode 28 may be located near the interface between the drift region 36 and the body region 38 in the Z-axis direction, and preferably lower than the interface. The top surface 28A and the bottom surface 28B of the gate electrode 28 may be flat or curved.

[0033] The semiconductor device 10 may further include a source wiring 42 formed on the insulating layer 16. The source wiring 42 may be configured to receive a reference voltage (source voltage). The source wiring 42 is connected to the source contact plug 34.

[0034] The epitaxial layer 20 may further include a contact region 44 adjacent to the body region 38. The contact region 44 may be a p-type region containing p-type impurities. The p-type impurity concentration of the contact region 44 is higher than that of the body region 38, and is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The source contact plug 34 may be as follows: The source contact plug 34 extends through the insulating layer 16 and the source region 40 to contact the contact region 44. The contact region 44 may be adjacent to the bottom of the source contact plug 34. The contact region 44 is electrically connected to the source wiring 42 via the source contact plug 34.

[0035] The insulating layer 16 includes a gate insulating portion 46 interposed between the gate electrode 28 and the semiconductor layer 12 (epitaxial layer 20) and covering the sidewall 24A of the first trench 24. The gate insulating portion 46 is a portion of the insulating layer 16 located between the side surface 28C of the gate electrode 28 and the sidewall 24A of the first trench 24. The gate electrode 28 faces the semiconductor layer 12 via the gate insulating portion 46. When a predetermined voltage (gate voltage) is applied to the gate electrode 28, a channel is formed in the p-type body region 38 adjacent to the gate insulating portion 46. The semiconductor device 10 can control the flow of electrons in the Z-axis direction between the n-type source region 40 and the n-type drift region 36 via this channel.

[0036] Fig. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in Fig. 2. Fig. 4 shows a cross section of the second trench 26 in the YZ plane in the non-intersection region 14B (see Fig. 2), which corresponds to a cross section of the second trench 26 taken along the short direction.

[0037] The second trench 26 has an opening in the upper surface 12A of the semiconductor layer 12 and has sidewalls 26A and a bottom wall 26B. The second trench 26 penetrates the source region 40 and the body region 38 of the epitaxial layer 20 to reach the drift region 36. Therefore, the bottom wall 26B of the second trench 26 is adjacent to the drift region 36. The second trench 26 may have a depth of 1 μm or more and 10 μm or less. The depth of the second trench 26 may correspond to the distance in the Z-axis direction from the upper surface 12A of the semiconductor layer 12 to the bottom wall 26B of the second trench 26.

[0038] The sidewall 26A of the second trench 26 may extend in the Z-axis direction (a direction perpendicular to the top surface 12A of the semiconductor layer 12) or may be inclined with respect to the Z-axis direction. In one example, the sidewall 26A may be inclined with respect to the Z-axis direction so that the width of the second trench 26 decreases toward the bottom wall 26B. In this case, the width W2 of the second trench 26 shown in FIG. 2 may be the width of the second trench 26 at the position of the top surface 12A of the semiconductor layer 12. Furthermore, the bottom wall 26B of the second trench 26 does not necessarily have to be flat, and may be curved in part or entirely, for example.

[0039] The field plate electrode 30 is buried in the second trench 26 via the insulating layer 16. The field plate electrode 30 is separated from the semiconductor layer 12 (epitaxial layer 20) by the insulating layer 16. The field plate electrode 30 may be configured to receive a reference voltage (source voltage). Therefore, the field plate electrode 30 may be electrically connected to the source wiring 42. The field plate electrode 30 is disposed below the interface between the drift region 36 and the body region 38 in the depth direction (Z-axis direction) of the cell trench 14.

[0040] The field plate electrode 30 may include a top surface 30A covered with the insulating layer 16 and a bottom surface 30B opposite the top surface 30A. In the non-intersection region 14B included in the second trench 26, the insulating layer 16 is embedded in the second trench 26 above the top surface 30A of the field plate electrode 30, and the gate electrode 28 (see FIG. 1) is not disposed therein. The top surface 30A and the bottom surface 30B of the field plate electrode 30 may be flat or curved.

[0041] The dimension of each field plate electrode 30 in the first direction (Y-axis direction in the illustrated example) may be smaller than the dimension of each gate electrode 28 (see FIG. 3) in the second direction (X-axis direction in the illustrated example).

[0042] Fig. 5 is a schematic cross-sectional view of the semiconductor device 10 taken along line F5-F5 in Fig. 2. Fig. 5 shows a cross section of the first trench 24 in the YZ plane, which corresponds to a cross section along the longitudinal direction of the first trench 24.

[0043] 5, intersection regions 14A and non-intersection regions 14B included in the first trench 24 are arranged alternately in a first direction (the Y-axis direction in the illustrated example) in which the first trench 24 extends. In the intersection regions 14A, the gate electrode 28 passes above the field plate electrode 30. In the non-intersection regions 14B included in the first trench 24, the field plate electrode 30 is not disposed below the gate electrode 28.

[0044] Fig. 6 is a schematic cross-sectional view of the semiconductor device 10 taken along line F6-F6 in Fig. 2. Fig. 6 shows a cross section of the second trench 26 in the XZ plane, which corresponds to a cross section along the longitudinal direction of the second trench 26.

[0045] 6 , intersection regions 14A and non-intersection regions 14B included in the second trench 26 are arranged alternately in a second direction (the X-axis direction in the illustrated example) in which the second trench 26 extends. In the intersection regions 14A, the field plate electrode 30 passes below the gate electrode 28. In the non-intersection regions 14B included in the second trench 26, the gate electrode 28 is not disposed above the field plate electrode 30.

[0046] As shown in FIGS. 5 and 6 , in the intersection region 14A, a field plate electrode 30 is disposed below the gate electrode 28 within the cell trench 14. At least a portion of the bottom surface 28B of the gate electrode 28 faces the top surface 30A of the field plate electrode 30 across the insulating layer 16. As shown in FIG. 6 , in the intersection region 14A, the side surface 28C of the gate electrode 28 does not face the sidewall 24A of the first trench 24. Therefore, no channel is formed around the gate electrode 28 in the intersection region 14A. Therefore, the larger the ratio of the spacing S2 of the second trenches 26 to the pitch P2 of the second trenches 26, the wider the channel formed, thereby reducing the on-resistance of the semiconductor device 10 (see FIG. 2 ).

[0047] On the other hand, in the non-intersection region 14B, only one of the gate electrode 28 and the field plate electrode 30 is disposed in the cell trench 14. More specifically, as shown in FIG. 5 , in the non-intersection region 14B included in the first trench 24, only the gate electrode 28 is disposed in the cell trench 14. Also, as shown in FIG. 6 , in the non-intersection region 14B included in the second trench 26, only the field plate electrode 30 is disposed in the cell trench 14. Therefore, in the non-intersection region 14B, the gate electrode 28 and the field plate electrode 30 do not face each other in the depth direction (Z-axis direction) of the cell trench 14. As a result, the capacitance generated by the gate electrode 28 and the field plate electrode 30 can be reduced by increasing the ratio of the spacing S1 of the first trenches 24 to the pitch P1 of the first trenches 24 (see FIG. 2 ).

[0048] (Functions of Semiconductor Device) The following describes the functions of the semiconductor device 10 of this embodiment. According to this embodiment, within the cell trenches 14 arranged in a mesh pattern, the gate electrodes 28 extend in a first direction, while the field plate electrodes 30 extend in a second direction that intersects with the first direction. Because the gate electrodes 28 and the field plate electrodes 30 do not extend in the same direction but intersect with each other, the capacitance generated by the gate electrodes 28 and the field plate electrodes 30 can be reduced.

[0049] The operation of the semiconductor device 10 will be further described below with reference to a semiconductor device 100 according to a comparative example shown in FIG. 7. FIG. 7 is a schematic cross-sectional perspective view of an exemplary semiconductor device 100 according to a comparative example. In FIG. 7, components similar to those in the semiconductor device 10 shown in FIGS. 1 to 6 are denoted by the same reference numerals. Further, detailed descriptions of components similar to those in the semiconductor device 10 will be omitted.

[0050] The semiconductor device 100 may be a MISFET having a trench gate structure, similar to the semiconductor device 10. The semiconductor device 100 includes a drain electrode 22, a semiconductor layer 12 formed on the drain electrode 22, a plurality of cell trenches 102 formed in the semiconductor layer 12, and an insulating layer 16 formed on the semiconductor layer 12.

[0051] 7 shows a cross-sectional view of the semiconductor device 100 at the position of the upper surface 12A of the semiconductor layer 12. It should be noted that, as shown in FIG. 8, the insulating layer 16 is formed not only in the cell trench 102 but also on the upper surface 12A of the semiconductor layer 12.

[0052] Unlike the cell trenches 14 of the semiconductor device 10, which are arranged in a mesh pattern, the multiple cell trenches 102 are arranged in a stripe pattern. Each of the multiple cell trenches 102 extends in one direction (the Y-axis direction in the illustrated example), has an opening in the upper surface 12A of the semiconductor layer 12, and has a depth in the Z-axis direction.

[0053] The semiconductor device 100 includes a gate electrode 104 and a field plate electrode 106 embedded in each cell trench 102 via an insulating layer 16. The gate electrode 104 and the field plate electrode 106 extend in the direction in which the cell trench 102 extends (i.e., the Y-axis direction).

[0054] In each cell trench 102, the gate electrode 104 is located above (closer to the upper surface 12A of the semiconductor layer 12) the field plate electrode 106. The gate electrode 104 is separated from the field plate electrode 106 by an insulating layer 16. The gate electrode 104 and the field plate electrode 106 extend in the Y-axis direction, similar to the cell trench 102.

[0055] The semiconductor device 100 further includes a plurality of source contact plugs 108. Each source contact plug 108 is disposed between two cell trenches 102. Like the cell trenches 102, the source contact plugs 108 extend in the Y-axis direction.

[0056] Fig. 8 is a schematic cross-sectional view of the semiconductor device 100 shown in Fig. 7. Fig. 8 shows a cross section of the cell trench 102 in the XZ plane, which corresponds to a cross section along the short direction of the cell trench 102.

[0057] The semiconductor device 100 further includes a source wiring 42 formed on the insulating layer 16. The source wiring 42 is connected to a source contact plug 108. The cell trench 102 has sidewalls 102A and a bottom wall 102B. The cell trench 102 penetrates the source region 40 and the body region 38 of the epitaxial layer 20 to reach the drift region 36. Therefore, the bottom wall 102B of the cell trench 102 is adjacent to the drift region 36.

[0058] The gate electrode 104 includes a top surface 104A covered by the insulating layer 16 and a bottom surface 104B opposite the top surface 104A. A side surface 104C of the gate electrode 104 faces the sidewall 102A of the cell trench 102 via the gate insulating portion 46. The field plate electrode 106 includes a top surface 106A covered by the insulating layer 16 and a bottom surface 106B opposite the top surface 106A. The field plate electrode 106 is disposed below the gate electrode 104 within the cell trench 102. More specifically, the field plate electrode 106 is disposed between the bottom surface 104B of the gate electrode 104 and the bottom wall 102B of the cell trench 102. At least a portion of the bottom surface 104B of the gate electrode 104 faces the top surface 106A of the field plate electrode 106, with the insulating layer 16 sandwiched between them.

[0059] The gate electrode 104 and the field plate electrode 106 are surrounded by an insulating layer 16. The field plate electrode 106 has a width smaller than that of the gate electrode 104. Because the field plate electrode 106 has a relatively small width, the thickness of the insulating layer 16 surrounding the field plate electrode 106 is relatively large.

[0060] The gate electrode 104 is configured to receive a gate voltage. The field plate electrode 106 is configured to receive a reference voltage (source voltage). Therefore, the field plate electrode 106 can be electrically connected to the source wiring 42. In the semiconductor device 100, by disposing the field plate electrode 106 below the gate electrode 104, it is possible to alleviate electric field concentration in the cell trench 102 and reduce the gate-drain capacitance.

[0061] On the other hand, since the gate electrode 104 and the field plate electrode 106 face each other and extend in the same direction within the cell trench 102, the gate-source capacitance may be relatively large. If the gate-source capacitance is large, undesirable behavior of the semiconductor device 100, such as self-turn-on, may occur.

[0062] In this regard, in the semiconductor device 10 of this embodiment, in the cell trenches 14 arranged in a mesh pattern, the gate electrodes 28 extend in a first direction, while the field plate electrodes 30 extend in a second direction intersecting the first direction. Therefore, the capacitance generated by the gate electrodes 28 and the field plate electrodes 30 can be reduced.

[0063] More specifically, the cell trench 14 includes a plurality of intersection regions 14A where the plurality of first trenches 24 and the plurality of second trenches 26 intersect with one another, and a plurality of non-intersection regions 14B where the plurality of first trenches 24 and the plurality of second trenches 26 do not intersect with one another. In each of the plurality of intersection regions 14A, one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in a planar view. Furthermore, in each of the plurality of non-intersection regions 14B, one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is disposed within the cell trench 14.

[0064] In each non-intersection region 14B, only one of the gate electrode 28 and the field plate electrode 30 is arranged within the cell trench 14, so that the capacitance generated by the gate electrode 28 and the field plate electrode 30 can be reduced.

[0065] Meanwhile, in each intersection region 14A, a field plate electrode 30 is disposed below the gate electrode 28 within the cell trench 14. This allows the depletion layer to expand in the semiconductor layer 12 near the intersection region 14A, thereby reducing the gate-drain capacitance of the semiconductor device 10.

[0066] The semiconductor device 10 of this embodiment has the following advantages: (1) Within the cell trenches 14 arranged in a mesh pattern, the gate electrodes 28 extend in a first direction, while the field plate electrodes 30 extend in a second direction intersecting the first direction. Because the gate electrodes 28 and the field plate electrodes 30 do not extend in the same direction but intersect, the capacitance generated by the gate electrodes 28 and the field plate electrodes 30 can be reduced.

[0067] (2) The cell trench 14 includes a plurality of intersection regions 14A where the plurality of first trenches 24 and the plurality of second trenches 26 intersect with one another, and a plurality of non-intersection regions 14B where the plurality of first trenches 24 and the plurality of second trenches 26 do not intersect with one another. In each of the plurality of intersection regions 14A, one of the plurality of gate electrodes 28 intersects with one of the plurality of field plate electrodes 30 in a planar view. Furthermore, in each of the plurality of non-intersection regions 14B, one of the plurality of gate electrodes 28 or one of the field plate electrodes 30 is disposed within the cell trench 14. Thus, both the gate electrode 28 and the field plate electrode 30 can be disposed in the intersection region 14A, and only one of the gate electrode 28 and the field plate electrode 30 can be disposed in the non-intersection region 14B.

[0068] (3) In each of the multiple intersection regions 14A, one of the multiple field plate electrodes 30 is disposed below one of the multiple gate electrodes 28 within the cell trench 14. This allows the depletion layer to expand in the semiconductor layer 12 near the intersection region 14A, thereby reducing the gate-drain capacitance of the semiconductor device 10.

[0069] (4) The multiple first trenches 24 are arranged parallel to one another at a constant interval S1, and the interval S1 at which the multiple first trenches 24 are arranged may be larger than the width W1 of each of the multiple first trenches 24. This allows the ratio of the interval S1 of the first trenches 24 to the pitch P1 of the first trenches 24 to be increased, thereby further reducing the capacitance generated by the gate electrode 28 and the field plate electrode 30.

[0070] (5) The multiple second trenches 26 are arranged parallel to one another at a constant interval S2, and the interval S2 at which the multiple second trenches 26 are arranged may be larger than the width W2 of each of the multiple second trenches 26. This allows the ratio of the interval S2 of the second trenches 26 to the pitch P2 of the second trenches 26 to be increased, thereby forming a wider channel and, as a result, reducing the on-resistance of the semiconductor device 10.

[0071] (6) The width W2 of each of the multiple second trenches 26 may be larger than the width W1 of each of the multiple first trenches 24. The larger the width W2 of the second trench 26, the thicker the insulating layer 16 surrounding the field plate electrode 30 can be, thereby improving the breakdown voltage of the semiconductor device 10.

[0072] (7) The dimension in the first direction of each field plate electrode 30 may be smaller than the dimension in the second direction of each gate electrode 28. The smaller the dimension in the first direction of the field plate electrode 30, the thicker the insulating layer 16 surrounding the field plate electrode 30 can be, thereby improving the breakdown voltage of the semiconductor device 10.

[0073] [Modification of Cell Trench] Figure 9 is a schematic plan view of an exemplary semiconductor device 200 for explaining a modification of the cell trench. In Figure 9, the same components as those in the semiconductor device 10 shown in Figures 1 to 6 are denoted by the same reference numerals. Detailed description of the same components as those in the semiconductor device 10 will be omitted.

[0074] The semiconductor device 200 includes a cell trench 202 formed in the semiconductor layer 12. The cell trench 202 includes a plurality of first trenches 24 extending in a first direction in a plan view and a plurality of second trenches 26 extending in a second direction intersecting the first direction in a plan view. The cell trench 202 differs from the exemplary cell trench 14 shown in FIGS. 1 and 2 in that the first direction in which the first trenches 24 extend does not coincide with the Y-axis direction. In the illustrated example, the angle between the first direction and the second direction is not 90 degrees. That is, the first direction may be inclined with respect to a direction perpendicular to the second direction.

[0075] 9 , by tilting each of the multiple first trenches 24 with respect to the Y-axis direction, the length of the first trenches 24 that can be formed within a predetermined range of the semiconductor layer 12 can be increased compared to the example of FIG. 2 . Because a gate electrode 28 is disposed in the first trench 24, tilting each of the multiple first trenches 24 with respect to the Y-axis direction can lengthen the gate electrode 28. As a result, the on-resistance of the semiconductor device 200 can be reduced. Note that, from the viewpoint of preventing a decrease in the number of first trenches 24 that can be formed within a predetermined range of the semiconductor layer 12, the angle between the first direction in which the first trenches 24 extend and the second direction in which the second trenches 26 extend is preferably within a range of 90 degrees ±10 degrees.

[0076] [Other Modifications] The above-described embodiment and modifications can be implemented with the following modifications. In Figures 5 and 6, the depth of the cell trench 14 is shown as being constant in both the intersection region 14A and the non-intersection region 14B. However, the depth of the cell trench 14 does not necessarily have to be constant. For example, the depth of the cell trench 14 in the intersection region 14A may be greater than the depth of the cell trench 14 in the non-intersection region 14B. In another example, the depth of the cell trench 14 in the intersection region 14A may be smaller than the depth of the cell trench 14 in the non-intersection region 14B.

[0077] The depth of the first trench 24 may be the same as or different from the depth of the second trench 26. For example, the depth of the second trench 26 may be greater than the depth of the first trench 24. In another example, the depth of the second trench 26 may be less than the depth of the first trench 24.

[0078] In the semiconductor device 200 shown in FIG. 9, the source contact plug 34 extends in the Y-axis direction in plan view. However, the source contact plug 34 may be disposed so as to extend in the first direction parallel to the first trench 24 .

[0079] A structure in which the conductivity types of the regions in the semiconductor layer 12 are reversed may be adopted. That is, a p-type region may be made into an n-type region, and an n-type region may be made into a p-type region. An additional wiring structure may be formed on the layer including the source wiring 42.

[0080] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "only A, or only B, or both A and B."

[0081] As used herein, the term "on" includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0082] Directional terms used herein, such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," "rear," etc., depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0083] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, and does not necessarily have to completely coincide with the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0084] [Supplementary Note] The technical ideas that can be grasped from each of the above-described embodiments and modified examples are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the corresponding reference numerals in the embodiments are shown in parentheses for the configurations described in the Supplementary Note. The reference numerals are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference numerals.

[0085] (Supplementary Note 1) A semiconductor device comprising: a semiconductor layer (12); cell trenches (14) formed in the semiconductor layer (12) and arranged in a mesh pattern, the cell trenches (14) including a plurality of first trenches (24) extending in a first direction in a plan view and a plurality of second trenches (26) extending in a second direction intersecting the first direction in a plan view, the plurality of first trenches (24) and the plurality of second trenches (26) intersecting and communicating with each other; an insulating layer (16) formed on the semiconductor layer (12); a plurality of gate electrodes (28) embedded in the plurality of first trenches (24) via the insulating layer (16) and extending in the first direction; and a plurality of field plate electrodes (30) embedded in the plurality of second trenches (26) via the insulating layer (16) and extending in the second direction.

[0086] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the cell trench (14) includes a plurality of intersection regions (14A) where the plurality of first trenches (24) and the plurality of second trenches (26) intersect with each other, and a plurality of non-intersection regions (14B) where the plurality of first trenches (24) and the plurality of second trenches (26) do not intersect with each other, and in each of the plurality of intersection regions (14A), one of the plurality of gate electrodes (28) intersects with one of the plurality of field plate electrodes (30), and in each of the plurality of non-intersection regions (14B), one of the plurality of gate electrodes (28) or one of the field plate electrodes (30) is arranged within the cell trench (14).

[0087] (Supplementary Note 3) The semiconductor device according to Supplementary Note 2, wherein in each of the plurality of intersection regions (14A), one of the plurality of field plate electrodes (30) is arranged below one of the plurality of gate electrodes (28) within the cell trench (14).

[0088] (Supplementary Note 4) The semiconductor device according to Supplementary Note 2 or 3, wherein in each of the plurality of intersection regions (14A), one of the plurality of field plate electrodes (30) is separated from one of the plurality of gate electrodes (28) by the insulating layer (16).

[0089] (Supplementary Note 5) The semiconductor device according to Supplementary Note 2 or 3, wherein the intersection regions (14A) and the non-intersection regions (14B) included in each of the plurality of first trenches (24) are alternately aligned in the first direction, and the intersection regions (14A) and the non-intersection regions (14B) included in each of the plurality of second trenches (26) are alternately aligned in the second direction.

[0090] (Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the semiconductor layer (12) includes a drift region (36) of a first conductivity type, a body region (38) of a second conductivity type formed on the drift region (36), and a source region (40) of the first conductivity type formed on the body region (38), at least a portion of each gate electrode (28) is arranged to face the body region (38) in the second direction via the insulating layer (16), and each field plate electrode (30) is arranged below an interface between the drift region (36) and the body region (38) in the depth direction of the cell trench (14).

[0091] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 6, further comprising: a source wiring (42) formed on the insulating layer (16); and a plurality of source contact plugs (34) connected to the source wiring (42), wherein the semiconductor layer (12) includes a plurality of mesh regions (32) surrounded by the cell trenches (14) arranged in a mesh pattern, and the plurality of source contact plugs (34) are respectively arranged in the plurality of mesh regions (32).

[0092] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the first direction is perpendicular to the second direction.

[0093] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the first direction is inclined with respect to a direction orthogonal to the second direction.

[0094] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the angle between the first direction and the second direction is within a range of 90 degrees ±10 degrees.

[0095] (Appendix 11) The semiconductor device according to any one of Appendices 1 to 10, wherein the plurality of first trenches (24) are arranged parallel to one another at a constant interval (S1), and the interval (S1) at which the plurality of first trenches (24) are arranged is greater than the width (W1) of each of the plurality of first trenches (24).

[0096] (Appendix 12) The semiconductor device according to any one of Appendices 1 to 11, wherein the second trenches (26) are arranged parallel to one another at a constant interval (S2), and the interval (S2) at which the second trenches (26) are arranged is larger than the width (W2) of each of the second trenches (26).

[0097] (Supplementary Note 13) The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein a width (W2) of each of the plurality of second trenches (26) is greater than a width (W1) of each of the plurality of first trenches (24).

[0098] (Supplementary Note 14) The semiconductor device according to any one of Supplementary Notes 1 to 13, wherein the dimension of each field plate electrode (30) in the first direction is smaller than the dimension of each gate electrode (28) in the second direction.

[0099] 10, 100, 200...Semiconductor device 12...Semiconductor layer 12A...Top surface 12B...Bottom surface 14, 102, 202...Cell trench 14A...Intersection region 14B...Non-intersection region 16...Insulating layer 18...Semiconductor substrate 20...Epitaxial layer 22...Drain electrode 24...First trench 26...Second trench 28, 104...Gate electrode 30, 106...Field plate electrode 32...Mesh region 34, 108...Source contact plug 36...Drift region 38...Body region 40...Source region 42...Source wiring 44...Contact region 46...Gate insulating portion W1, W2...Width S1, S2...Spacing

Claims

1. A semiconductor layer; a cell trench formed in the semiconductor layer and arranged in a mesh pattern, the cell trench including a plurality of first trenches extending in a first direction in a plan view and a plurality of second trenches extending in a second direction intersecting the first direction in a plan view, the plurality of first trenches and the plurality of second trenches intersecting and communicating with each other; an insulating layer formed on the semiconductor layer; a plurality of gate electrodes respectively embedded in the plurality of first trenches via the insulating layer and extending in the first direction; a plurality of field plate electrodes respectively embedded in the plurality of second trenches via the insulating layer and extending in the second direction; A semiconductor device comprising:

2. The cell trench includes a plurality of intersection regions in which the plurality of first trenches and the plurality of second trenches intersect with each other, and a plurality of non-intersection regions in which the plurality of first trenches and the plurality of second trenches do not intersect with each other, In each of the plurality of intersection regions, one of the plurality of gate electrodes intersects with one of the plurality of field plate electrodes; The semiconductor device according to claim 1 , wherein in each of the non-intersecting regions, one of the gate electrodes or one of the field plate electrodes is disposed within the cell trench.

3. 3. The semiconductor device according to claim 2, wherein in each of the plurality of intersection regions, within the cell trench, one of the plurality of field plate electrodes is disposed below one of the plurality of gate electrodes.

4. 4. The semiconductor device according to claim 2, wherein in each of said plurality of intersection regions, one of said plurality of field plate electrodes is separated from one of said plurality of gate electrodes by said insulating layer.

5. the intersection regions and the non-intersection regions included in each of the plurality of first trenches are arranged alternately in the first direction, The semiconductor device according to claim 2 , wherein the intersection regions and the non-intersection regions included in each of the plurality of second trenches are arranged alternately in the second direction.

6. the semiconductor layer includes a drift region of a first conductivity type, a body region of a second conductivity type formed on the drift region, and a source region of the first conductivity type formed on the body region; At least a portion of each gate electrode is disposed to face the body region in the second direction with the insulating layer interposed therebetween; 4. The semiconductor device according to claim 1, wherein each field plate electrode is disposed below an interface between the drift region and the body region in a depth direction of the cell trench.

7. a source wiring formed on the insulating layer; a plurality of source contact plugs connected to the source wiring; Further equipped with the semiconductor layer includes a plurality of mesh regions surrounded by the cell trenches arranged in a mesh pattern, 4. The semiconductor device according to claim 1, wherein the plurality of source contact plugs are arranged in the plurality of mesh regions, respectively.

8. 4. The semiconductor device according to claim 1, wherein the first direction is perpendicular to the second direction.

9. 4. The semiconductor device according to claim 1, wherein the first direction is inclined with respect to a direction perpendicular to the second direction.

10. 4. The semiconductor device according to claim 1, wherein an angle between the first direction and the second direction is within a range of 90 degrees±10 degrees.

11. The first trenches are arranged parallel to one another at regular intervals, 4. The semiconductor device according to claim 1, wherein the interval at which the plurality of first trenches are arranged is larger than a width of each of the plurality of first trenches.

12. The second trenches are arranged parallel to each other at regular intervals, 4. The semiconductor device according to claim 1, wherein the interval at which the second trenches are arranged is greater than a width of each of the second trenches.

13. 4. The semiconductor device according to claim 1, wherein a width of each of the second trenches is greater than a width of each of the first trenches.

14. 4. The semiconductor device according to claim 1, wherein a dimension of each field plate electrode in the first direction is smaller than a dimension of each gate electrode in the second direction.