Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device including: a gate electrode embedded in a gate trench; a surface insulating layer that is formed on a first principal surface and that has a contact hole; a covering insulating layer that covers the gate electrode in the gate trench and that insulates the gate electrode from a contact electrode; and an embedded body that is embedded in a region on the covering insulating layer in the gate trench and that has etching selectivity with respect to the surface insulating layer.

Description

Semiconductor device and method for manufacturing the same Related Applications

[0001] This application corresponds to Patent Application No. 2022-143915 filed with the Japan Patent Office on September 9, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] Patent Document 1 discloses a semiconductor device including: a semiconductor layer having a main surface in which a trench is formed; a body region of a first conductivity type formed along a sidewall of the trench in a surface portion of the main surface of the semiconductor layer; an impurity region of a second conductivity type formed along the sidewall of the trench in a surface portion of the body region; a gate insulating layer formed on an inner wall of the trench; a gate electrode embedded in the trench and facing the body region and the impurity region with the gate insulating layer between them; a contact electrode extending from within the trench through the sidewall of the trench to a surface portion of the main surface of the semiconductor layer and electrically connected to the body region and the impurity region; and a buried insulating layer interposed in the trench between the gate electrode and the contact electrode and insulating the gate electrode and the contact electrode.

[0004] International Publication No. 2019 / 103135

[0005] An embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof that can improve the controllability of the capacitance between a gate electrode and a contact electrode.

[0006] An embodiment of the present disclosure provides a semiconductor device and a manufacturing method thereof that can suppress a reduction in channel width and reduce on-resistance in a structure including a contact trench intersecting a gate trench.

[0007] A semiconductor device according to an embodiment of the present disclosure includes a chip having a first main surface in which a gate trench extending in a first direction is formed, a body region of a first conductivity type formed along a sidewall of the gate trench in a surface portion of the first main surface, a first impurity region of a second conductivity type formed along the sidewall of the gate trench in a surface portion of the body region, a gate insulating layer formed on an inner wall of the gate trench, a gate electrode embedded in the gate trench and facing the body region and the first impurity region with the gate insulating layer interposed therebetween, and a second impurity region formed on the first main surface so as to cover the gate electrode and intersect with the first direction. The gate trench includes a surface insulating layer having contact holes extending from a region above the gate trench to the outside of the gate trench along two directions, a contact electrode electrically connected to the body region and the first impurity region via the contact holes and extending from within the gate trench to a surface portion of the first main surface via a sidewall of the gate trench, a covering insulating layer covering the gate electrode within the gate trench and providing insulation between the gate electrode and the contact electrode, and an embedded body embedded in a region above the covering insulating layer within the gate trench and having an etching selectivity with respect to the surface insulating layer.

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes the steps of: forming a gate insulating layer on an inner wall of a gate trench of a semiconductor wafer having a first main surface in which the gate trench is formed; embedding a gate electrode in the gate trench after forming the gate insulating layer; selectively removing the gate electrode from an upper surface side to form a recess in the gate trench; forming a covering insulating layer in the recess so as to cover an upper surface of the gate electrode; embedding an embedding body in a region on the covering insulating layer in the recess; selectively injecting impurities of a first conductivity type into a surface portion of the first main surface to form a body region along a sidewall of the gate trench; and selectively injecting impurities of a second conductivity type into a surface portion of the body region to form the gate insulating layer. forming a contact hole intersecting the gate trench so as to selectively expose the buried body and the first main surface by selectively etching the surface insulating layer; forming a contact trench in a surface portion of the first main surface so as to expose the body region and the first impurity region by etching through the contact hole; and forming a contact electrode connected to the body region and the first impurity so as to be embedded in the contact trench, wherein the buried body is formed of a material having an etching selectivity with respect to the surface insulating layer.

[0009] According to one embodiment of the present disclosure, the filling body is formed of a material having an etching selectivity with respect to the surface insulating layer. This allows the filling body to be used as an etching stop layer when forming contact holes in the surface insulating layer, thereby preventing etching of the covering insulating layer. Therefore, the thickness of the covering insulating layer can be easily controlled as a design value when forming the covering insulating layer. This prevents short circuits between the gate electrode and the contact electrode and a decrease in TZDB (Time Zero Dielectric Breakdown), while improving the controllability of the capacitance between the gate electrode and the contact electrode.

[0010] FIG. 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a view in which the structure on the first main surface of the chip has been removed from FIG. 1 . FIG. 3 is a view in which the emitter contact electrode layer has been removed from FIG. 2 . FIG. 4 is a schematic plan view of FIG. 3 as viewed from the first main surface of the chip. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 4 . FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4 . FIG. 7 is a cross-sectional perspective view taken along line VII-VII in FIG. 3 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4 . FIG. 9 is an enlarged view of a portion surrounded by a two-dot chain line IX in FIG. 6 . FIGS. 10A and 10B are views showing a portion of a manufacturing process of the semiconductor device. FIGS. 11A and 11B are views showing steps subsequent to those shown in FIGS. 10A and 10B , respectively. FIGS. 12A and 12B are views showing steps subsequent to those shown in FIGS. 11A and 11B , respectively. 13A and 13B are diagrams illustrating steps subsequent to those shown in FIGS. 12A and 12B, respectively. FIGS. 14A and 14B are diagrams illustrating steps subsequent to those shown in FIGS. 13A and 13B, respectively. FIGS. 15A and 15B are diagrams illustrating steps subsequent to those shown in FIGS. 14A and 14B, respectively. FIGS. 16A and 16B are diagrams illustrating steps subsequent to those shown in FIGS. 15A and 15B, respectively. FIGS. 17A and 17B are diagrams illustrating steps subsequent to those shown in FIGS. 16A and 16B, respectively. FIG. 18 is a schematic cross-sectional view showing a partial region of a semiconductor device according to a second embodiment of the present disclosure. FIG. 19 is a schematic cross-sectional view showing a partial region of a semiconductor device according to the second embodiment of the present disclosure. FIG. 20 is a schematic cross-sectional view showing a partial region of a semiconductor device according to the second embodiment of the present disclosure. FIG. 21 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a third embodiment of the present disclosure. FIG. 22 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 23 illustrates the steps involved in forming the structure of FIG.

[0011] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0012] Fig. 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 1 according to a first embodiment of the present disclosure. Fig. 2 is a view in which the structure on a first main surface 3 of a chip 2 is removed from Fig. 1. Fig. 3 is a view in which the emitter contact electrode layer 51 is removed from Fig. 2.

[0013] FIG. 4 is a schematic plan view of FIG. 3 as viewed from the first main surface 3 of the chip 2. FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional perspective view taken along line VII-VII shown in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 4. FIG. 9 is an enlarged view of the portion surrounded by the two-dot chain line IX in FIG. 6. FIGS. 5, 6, and 8 also show the structure on the first main surface 3 of the chip 2.

[0014] In this embodiment, the semiconductor device 1 has a basic configuration including a trench gate type IGBT (Insulated Gate Bipolar Transistor). － The chip 2 includes a chip of type n － The silicon single crystal substrate is made of n-type single crystal silicon manufactured by the FZ (Floating Zone) method. － The chip 2 is formed using a single crystal silicon semiconductor wafer. The chip 2 may be called a semiconductor chip or a semiconductor layer.

[0015] The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The thickness of the chip 2 may be 50 μm or more and 300 μm or less. The thickness of the chip 2 may be 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less.

[0016] 1 to 3, a p-type collector region 5 is formed in a surface portion of the second main surface 4. An n-type charge accumulation region 6 is formed in a surface portion of the first main surface 3. The charge accumulation region 6 is formed on the first main surface 3 side with a gap between it and the collector region 5.

[0017] 1 to 3, in the chip 2, the region between the collector region 5 and the charge storage region 6 has n － A p-type drift region 7 is formed on the chip 2. The drift region 7 is formed by a region located between the collector region 5 and the charge storage region 6 in the chip 2. A p-type body region 8 is formed in the surface portion of the charge storage region 6. A plurality of trench gate electrode structures 10 and a plurality of trench emitter electrode structures 11 are formed at intervals on the surface portion of the first main surface 3.

[0018] 1 to 7 show only one adjacent trench gate electrode structure 10 and one adjacent trench emitter electrode structure 11. Below, the structure of the semiconductor device 1 will be described focusing on the structure of this one trench gate electrode structure 10 and this one adjacent trench emitter electrode structure 11.

[0019] In a plan view, the trench gate electrode structure 10 and the trench emitter electrode structure 11 extend in a strip shape along an arbitrary first direction X. The trench gate electrode structure 10 and the trench emitter electrode structure 11 are formed at intervals along a second direction Y that intersects with the first direction X.

[0020] More specifically, the planar view refers to a planar view seen from the normal direction Z (hereinafter simply referred to as the "normal direction Z") of the first main surface 3. More specifically, the second direction Y is a direction perpendicular to the first direction X. The first direction X and the second direction Y are also tangential directions of the first main surface 3.

[0021] The trench pitch P0 between the trench gate electrode structure 10 and the trench emitter electrode structure 11 may be 0.1 μm or more and less than 0.6 μm. The trench pitch P0 may be 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, or 0.5 μm or more and less than 0.6 μm. The trench pitch P0 is preferably 0.2 μm or more and 0.4 μm or less (for example, approximately 0.25 μm).

[0022] The trench gate electrode structure 10 includes a gate trench 12, a gate insulating layer 13, a gate electrode layer 14, a plurality of gate electrode recesses 15, a plurality of gate covering insulating layers 16, a plurality of gate buried bodies 9, and a plurality of gate intermediate insulating layers 22. The gate trench 12 extends from the first main surface 3 through the body region 8 and the charge storage region 6 to the drift region 7.

[0023] The depth of the gate trench 12 may be 2.0 μm or more and 4.0 μm or less. The depth of the gate trench 12 may be 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, or 3.5 μm or more and 4.0 μm or less. The depth of the gate trench 12 is preferably 2.5 μm or more and 3.5 μm or less (for example, about 3.0 μm).

[0024] The second direction width of the gate trench 12 may be 0.5 μm or more and 1.5 μm or less. The second direction width of the gate trench 12 may be 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1.0 μm or less, 1.0 μm or more and 1.25 μm or less, or 1.25 μm or more and 1.5 μm or less. The second direction width of the gate trench 12 is preferably 0.5 μm or more and 1.0 μm or less (for example, about 0.75 μm).

[0025] The gate insulating layer 13 may be made of silicon oxide. The gate insulating layer 13 is formed in a film shape along the inner wall of the gate trench 12. The gate insulating layer 13 defines a recessed space within the gate trench 12.

[0026] The gate electrode layer 14 may be formed of conductive polysilicon. The gate electrode layer 14 is controlled by a gate voltage. The gate electrode layer 14 is embedded in the gate trench 12 with the gate insulating layer 13 sandwiched therebetween. More specifically, the gate electrode layer 14 is embedded in a concave space defined by the gate insulating layer 13 within the gate trench 12.

[0027] In this embodiment, the plurality of gate electrode recesses 15 are formed on the upper surface of the gate electrode layer 14 at intervals along the first direction X. As a result, the upper end of the gate electrode layer 14 has an uneven structure including the plurality of gate electrode recesses 15.

[0028] The interval between adjacent gate electrode recesses 15 may be greater than 0 μm and less than or equal to 10 μm. The interval between adjacent gate electrode recesses 15 is also the width in the first direction X of a portion of the gate electrode layer 14 that is sandwiched between two adjacent gate electrode recesses 15. The interval between adjacent gate electrode recesses 15 may be greater than 0 μm and less than or equal to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm.

[0029] In this embodiment, the side walls of each gate electrode recess 15 are formed by the gate insulating layer 13 and the gate electrode layer 14. A pair of side walls opposing each other in the first direction X is formed by the gate electrode layer 14, and a pair of side walls opposing each other in the second direction Y is formed by the gate insulating layer 13. The bottom wall of each gate electrode recess 15 is formed by the gate electrode layer 14. With reference to FIG. 8 , the bottom wall of each gate electrode recess 15 may be located in a region between the first main surface 3 and the bottom of an emitter region 25 (described later) in relation to the normal direction Z, or may be located in a portion deeper than the bottom of the emitter region 25.

[0030] 8 , each gate electrode recess 15 is formed in a tapered shape with a bottom area smaller than an opening area. The angle θ formed by the upper surface of gate electrode layer 14 and the sidewall of gate electrode recess 15 within gate electrode layer 14 may be greater than 90° and less than or equal to 120° (for example, approximately 102°).

[0031] The plurality of gate covering insulating layers 16 are formed on the upper surface of the gate electrode layer 14 and on the side walls of the gate electrode recess 15 in the gate trench 12. More specifically, the plurality of gate covering insulating layers 16 are formed independently in the plurality of gate electrode recesses 15. Each gate covering insulating layer 16 covers the gate electrode layer 14 in the gate trench 12, is formed along the side walls of the gate electrode recess 15, and is exposed from the opening of the gate trench 12. Each gate covering insulating layer 16 defines a concave space in each gate electrode recess 15. The concave space in the gate electrode recess 15 is surrounded by the gate covering insulating layer 16 from below and laterally.

[0032] 9 , the gate-coating insulating layer 16 includes a bottom portion 23 covering the upper surface of the gate electrode layer 14 and a side portion 24 extending upward from the bottom portion 23 along the sidewall of the gate trench 12. The bottom portion 23 of the gate-coating insulating layer 16 has a thickness of 150 nm or more and 300 nm or less. Meanwhile, the side portion 24 of the gate-coating insulating layer 16 has a first thickness T1 at a lower end 47 in the depth direction of the gate trench 12 and a second thickness T2 thinner than the first thickness T1 at an upper end 48 in the depth direction of the gate trench 12. The first thickness T1 is, for example, 300 nm or less, and the second thickness T2 is, for example, 50 nm or less. Furthermore, the width W1 of the upper end of the gate embedded body 9 may be narrower than the width W2 of the upper end of the gate electrode layer 14.

[0033] In a cross-sectional view, the side portion 24 of the gate-coating insulating layer 16 has a tapered shape in which an outer side surface 29 closer to the sidewall of the gate trench 12 and an inner side surface 30 opposite the outer side surface 29 are inclined toward each other from a lower end 47 to an upper end 48 of the gate-coating insulating layer 16. A step S may be formed between the upper end of the side portion 24 of the gate-coating insulating layer 16 and the first main surface 3. In other words, the upper end of the side portion 24 of the gate-coating insulating layer 16 may be located at a lower height than the first main surface 3 in the depth direction of the gate trench 12.

[0034] In this embodiment, the plurality of gate embedding bodies 9 may be formed from the same material as the gate electrode layer 14. That is, the plurality of gate embedding bodies 9 may be formed from conductive polysilicon. The gate embedding bodies 9 are conductive, but may be electrically floating in this embodiment. The gate embedding bodies 9 are embedded in the gate electrode recess 15 with the gate covering insulating layer 16 sandwiched therebetween. More specifically, the gate embedding bodies 9 are embedded in a recessed space defined by the gate covering insulating layer 16 within the gate electrode recess 15.

[0035] The multiple gate intermediate insulating layers 22 may be formed of silicon oxide. Each gate intermediate insulating layer 22 is interposed between the gate electrode layer 14 and the gate covering insulating layer 16 in each gate electrode recess 15. Referring to FIG. 9 , in this embodiment, the gate intermediate insulating layer 22 is formed between the upper surface of the gate electrode layer 14 and the bottom 23 of the gate covering insulating layer 16. The thickness (third thickness T3) of the gate intermediate insulating layer 22 may be, for example, 20 nm or more and 150 nm or less. In the drawing, the gate intermediate insulating layer 22 is clearly distinguished from the gate covering insulating layer 16 (bottom 23). Depending on the manufacturing process conditions, the gate intermediate insulating layer 22 may be indistinguishable from the gate covering insulating layer 16 and may be integrated with the gate covering insulating layer 16 in appearance.

[0036] The trench emitter electrode structure 11 includes an emitter trench 17, an emitter insulating layer 18, an emitter electrode layer 19, an emitter electrode recess 20, an emitter covering insulating layer 21, an emitter buried body 27, and an emitter intermediate insulating layer 28. The emitter trench 17 extends from the first main surface 3, through the body region 8 and the charge accumulation region 6, and reaches the drift region 7.

[0037] The depth of the emitter trench 17 may be 2.0 μm or more and 4.0 μm or less. The depth of the emitter trench 17 may be 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, or 3.5 μm or more and 4.0 μm or less. The depth of the emitter trench 17 is preferably 2.5 μm or more and 3.5 μm or less (for example, about 3.0 μm). The depth of the emitter trench 17 is preferably approximately equal to the depth of the gate trench 12.

[0038] The width in the second direction of the emitter trench 17 may be 0.5 μm or more and 1.5 μm or less. The width in the second direction of the emitter trench 17 may be 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1.0 μm or less, 1.0 μm or more and 1.25 μm or less, or 1.25 μm or more and 1.5 μm or less. The width in the second direction of the emitter trench 17 is preferably 0.5 μm or more and 1.0 μm or less (for example, approximately 0.75 μm). The width in the second direction of the emitter trench 17 is preferably approximately equal to the width in the second direction of the gate trench 12.

[0039] The emitter insulating layer 18 may be made of silicon oxide. The emitter insulating layer 18 is formed in the form of a film along the inner wall of the emitter trench 17. The emitter insulating layer 18 defines a recessed space within the emitter trench 17.

[0040] The emitter electrode layer 19 may be formed of conductive polysilicon. The emitter electrode layer 19 is controlled by an emitter voltage. The emitter voltage has a voltage value less than the gate voltage. The emitter voltage may be a reference voltage (e.g., ground voltage). The emitter electrode layer 19 is embedded in the emitter trench 17 with the emitter insulating layer 18 sandwiched therebetween. More specifically, the emitter electrode layer 19 is embedded in a concave space defined by the emitter insulating layer 18 within the emitter trench 17.

[0041] In this embodiment, the emitter electrode recess 20 is formed so as to dig down almost the entire upper surface of the emitter electrode layer 19. In other words, the emitter electrode layer 19 is embedded up to a midpoint in the depth direction of the recessed space defined by the emitter insulating layer 18.

[0042] In this embodiment, the sidewalls of the emitter electrode recesses 20 are formed by the emitter insulating layer 18. The bottom walls of the emitter electrode recesses 20 are formed by the emitter electrode layer 19. With reference to FIGS. 5 and 6 , the bottom walls of the emitter electrode recesses 20 may be located in a region between the first main surface 3 and the bottoms of the emitter regions 25 (described later) in the normal direction Z, or may be located in a portion deeper than the bottoms of the emitter regions 25. In other words, the upper end of the emitter electrode layer 19 is located closer to the first main surface 3 than the bottoms of the emitter regions 25 (described later). The depth of the emitter electrode recesses 20 in the normal direction Z may be approximately equal to the depth of the gate electrode recesses 15.

[0043] The emitter-coating insulating layer 21 is formed on the upper surface of the emitter electrode layer 19 and on the side walls of the emitter electrode recess 20 in the emitter trench 17. That is, the emitter-coating insulating layer 21 is formed along the inner wall of the emitter electrode recess 20. The emitter-coating insulating layer 21 covers the emitter electrode layer 19 in the emitter trench 17, is formed along the side walls of the emitter electrode recess 20, and is exposed from the opening of the emitter trench 17. The emitter-coating insulating layer 21 defines a recessed space in the emitter electrode recess 20. The recessed space in the emitter electrode recess 20 is surrounded by the emitter-coating insulating layer 21 from below and from the sides. Although not explained further, the emitter-coating insulating layer 21 has the same cross-sectional shape as the gate-coating insulating layer 16 shown in FIG.

[0044] In this embodiment, the emitter embedding body 27 may be formed from the same material as the emitter electrode layer 19. That is, the emitter embedding body 27 may be formed from conductive polysilicon. Although the emitter embedding body 27 is conductive, in this embodiment it may be electrically floating. The emitter embedding body 27 is embedded in the emitter electrode recess 20 with the emitter-coating insulating layer 21 sandwiched therebetween. More specifically, the emitter embedding body 27 is embedded in a recessed space defined by the emitter-coating insulating layer 21 within the emitter electrode recess 20.

[0045] The emitter intermediate insulating layer 28 may be made of silicon oxide and is interposed between the emitter electrode layer 19 and the emitter-coating insulating layer 21 in the emitter electrode recess 20.

[0046] In the surface portion of the body region 8, the region along the sidewall of the gate trench 12 has n ＋ An emitter region 25 (impurity region) of a type is formed in the gate trench 12. More specifically, a plurality of emitter regions 25 are formed along one sidewall and the other sidewall of the gate trench 12 in the first direction X. The plurality of emitter regions 25 are each formed in a strip shape extending along the first direction X. The emitter region 25 is in contact with the sidewall of the gate trench 12. The emitter region 25 is also in contact with the sidewall of the emitter trench 17.

[0047] In a region along the sidewall of gate trench 12 in the surface portion of first main surface 3, emitter region 25, body region 8, charge storage region 6, and drift region 7 are formed in this order from first main surface 3 toward second main surface 4. A channel CH of the IGBT is formed in a region of body region 8 facing gate electrode layer 14 with gate insulating layer 13 sandwiched therebetween.

[0048] 3 to 6 and 7, a plurality of contact trenches 31 are formed in a surface portion of the first main surface 3. The plurality of contact trenches 31 are formed at intervals along the first direction X. The plurality of contact trenches 31 are each formed in a strip shape extending along the second direction Y. The width in the first direction of each contact trench 31 is smaller than the width in the second direction of the gate trench 12.

[0049] More specifically, each contact trench 31 is extended from an inner region of the corresponding gate-coating insulating layer 16 to the surface portion of the first main surface 3, penetrating the sidewall of the gate trench 12. In this embodiment, each contact trench 31 penetrates one sidewall and the other sidewall of the gate trench 12 from an inner region of the gate-coating insulating layer 16 in the second direction Y.

[0050] Each contact trench 31 includes a first intersection region 33 that intersects with the gate electrode layer 14 in a plan view. In the first intersection region 33, the bottom wall of each contact trench 31 is formed by the gate-coating insulating layer 16, and the side wall of each contact trench 31 is formed by the gate embedded body 9.

[0051] Each contact trench 31 includes a second intersection region 34 that intersects with the emitter electrode layer 19 in a plan view. In the second intersection region 34, the bottom wall of each contact trench 31 is formed by the emitter-coating insulating layer 21, and the side wall of each contact trench 31 is formed by the emitter embedding body 27.

[0052] Each contact trench 31 further includes a contact region 35 extending from the first intersection region 33 to the outside of the gate trench 12. The contact region 35 may also be referred to as a connection region that connects the first intersection region 33 and the second intersection region 34 in a region between the gate trench 12 and the emitter trench 17 in a plan view. In the contact region 35, the bottom wall of each contact trench 31 is formed by the body region 8, and the sidewall of each contact trench 31 is formed by the body region 8 and the emitter region 25. That is, in the contact region 35, the stacked structure of the body region 8 and the emitter region 25 is exposed on the sidewall of the contact trench 31.

[0053] Each contact trench 31 further has a lead-out portion 32 led out from one sidewall of the emitter trench 17. Each lead-out portion 32 penetrates one sidewall of the emitter trench 17 from the surface portion of the first main surface 3 and reaches the inside of the emitter trench 17.

[0054] 7 , a first depth D1 from the first main surface 3 to the upper surface of the gate electrode layer 14 in the first intersection region 33 is shallower than a second depth D2 of the contact trench 31 in the contact region 35. Therefore, the contact trench 31 has an uneven structure in which the gate electrode layer 14 and the emitter electrode layer 19 selectively protrude in the second direction Y. For example, the first depth D1 is 1 μm or less, and preferably 0.5 μm or more and 1 μm or less. The second depth D2 is 0.3 μm or more and 1.0 μm or less.

[0055] In the first intersection region 33, the upper end of the gate electrode layer 14 is located closer to the first main surface 3 than the bottom of the emitter region 25. As a result, the gate electrode layer 14 has facing portions 40 that face the emitter region 25 via the gate insulating layer 13, near both sides of the first intersection region 33 in the first direction X. The facing portions 40 are regions indicated by horizontal hatching in FIG. 7. The facing portions 40 are located below the pair of gate embedded bodies 9 in the normal direction Z.

[0056] The contact trench 31 includes a first bottom wall 37 in the first intersection region 33 and the second intersection region 34, and a second bottom wall 38 in the contact region 35 and the lead-out portion 32. A step 39 is formed between the first bottom wall 37 and the second bottom wall 38 due to the difference between the first depth D1 and the second depth D2.

[0057] The arrangement of the multiple contact trenches 31 is arbitrary. The multiple contact trenches 31 may be formed at equal intervals along the first direction X. The multiple contact trenches 31 may be formed at unequal intervals along the first direction X.

[0058] In the body region 8, the region along the bottom wall of each contact trench 31 is ＋ A contact region 36 of the type is formed in the body region 8. The contact region 36 may be formed in a region along the bottom wall and side wall of each contact trench 31 in the body region 8. The contact region 36 is formed in a region deeper than the emitter region 25 in the normal direction Z in the body region 8.

[0059] The contact region 36 has an exposed surface exposed from the bottom wall of the contact trench 31. The exposed surface of the contact region 36 is formed in a region between the first main surface 3 and the bottom of the body region 8. More specifically, the exposed surface of the contact region 36 is formed in a region between the bottom of the body region 8 and the bottom of the emitter region 25. More specifically, the exposed surface of the contact region 36 is formed lower than the upper surface of the gate electrode layer 14 and the upper surface of the emitter electrode layer 19.

[0060] An interlayer insulating layer 41 is formed on the first main surface 3. The interlayer insulating layer 41 covers the trench gate electrode structure 10 and the trench emitter electrode structure 11. The interlayer insulating layer 41 covers the gate-coating insulating layer 16 and the gate buried body 9 exposed from the gate trench 12, and the emitter-coating insulating layer 21 and the emitter buried body 27 exposed from the emitter trench 17.

[0061] The interlayer insulating layer 41 may be formed of silicon oxide or silicon nitride.２ The insulating film may have a laminated structure including an oxide film (SiO ２ The film may include a non-doped silicon glass (NSG) film that does not contain impurities and / or a phosphorus silicon glass (PSG) film that contains phosphorus.

[0062] Interlayer insulating layer 41 may have a layered structure including an NSG film and a PSG film stacked in this order from first main surface 3. The thickness of the NSG film may be 2000 Å or more and 8000 Å or less (e.g., about 5000 Å). The thickness of the PSG film may be 2000 Å or more and 6000 Å or less (e.g., about 4000 Å).

[0063] A plurality of contact holes 42 are formed in the interlayer insulating layer 41. Each of the plurality of contact holes 42 communicates with a corresponding contact trench 31. That is, the plurality of contact holes 42 are formed at intervals along the first direction X and are each formed in a strip shape extending along the second direction Y.

[0064] The plurality of contact holes 42 penetrate the interlayer insulating layer 41 and communicate with the corresponding contact trenches 31. As a result, the plurality of contact holes 42 form one emitter contact trench 31, 42 between themselves and the corresponding contact trenches 31.

[0065] The first direction width of each contact hole 42 may be equal to or greater than the first direction width of each contact trench 31. That is, the first direction width of each contact hole 42 may be equal to the first direction width of each contact trench 31, or may be greater than the first direction width of each contact trench 31. When the first direction width of each contact hole 42 exceeds the first direction width of each contact trench 31, the inner wall of each contact hole 42 may surround the inner wall of the corresponding contact trench 31.

[0066] The arrangement of the multiple contact holes 42 is arbitrary and is adjusted according to the arrangement of the contact trenches 31. The multiple contact holes 42 may be formed at equal intervals along the first direction X. The multiple contact holes 42 may be formed at unequal intervals along the first direction X.

[0067] An emitter principal surface electrode layer 43 is formed on the interlayer insulating layer 41. The emitter principal surface electrode layer 43 extends from above the interlayer insulating layer 41 into the contact hole 42 and the contact trench 31 (i.e., the emitter contact trenches 31, 42). The emitter principal surface electrode layer 43 may include, for example, a stacked structure of a barrier layer such as titanium and an electrode layer such as tungsten. In this embodiment, portions of the emitter principal surface electrode layer 43 located within the contact trenches 31 form multiple emitter contact electrode layers 51. This forms a structure in which multiple emitter contact electrode layers 51 are embedded in the surface portion of the chip 2.

[0068] The plurality of emitter contact electrode layers 51 each have an arrangement and a shape corresponding to the arrangement and shape of the plurality of contact trenches 31. That is, the plurality of emitter contact electrode layers 51 are formed at intervals along the first direction X and each have a strip shape extending along the second direction Y.

[0069] In a first intersection region 33 where the emitter contact electrode layer 51 intersects with the gate electrode layer 14 in a plan view, each emitter contact electrode layer 51 faces the gate electrode layer 14 with the gate-coating insulating layer 16 interposed therebetween in the normal direction Z and the first direction X. Each emitter contact electrode layer 51 is insulated from the gate electrode layer 14 by the gate-coating insulating layer 16.

[0070] In the first intersection region 33, the gate embedded body 9 is interposed between the emitter contact electrode layer 51 and the gate covering insulating layer 16. In this embodiment, in the first intersection region 33, the gate embedded body 9 includes a pair of gate embedded bodies 9 provided on both sides of the first intersection region 33 in the first direction X, sandwiching the emitter contact electrode layer 51 from both sides in the first direction X. Therefore, in the first intersection region 33, the emitter contact electrode layer 51 is in direct contact with the gate covering insulating layer 16 in the normal direction Z, and in contact with the gate embedded body 9 in the first direction X. The emitter contact electrode layer 51 is surrounded on three sides by the underlying gate covering insulating layer 16 and the gate embedded bodies 9 on both sides.

[0071] In a second intersection region 34 where each emitter contact electrode layer 51 intersects with the emitter electrode layer 19 in a plan view, each emitter contact electrode layer 51 faces the emitter electrode layer 19 with the emitter-covering insulating layer 21 interposed therebetween in the normal direction Z and the first direction X. Each emitter contact electrode layer 51 is insulated from the emitter electrode layer 19 by the emitter-covering insulating layer 21.

[0072] In the second intersection region 34, the emitter buried body 27 is interposed between the emitter contact electrode layer 51 and the emitter-covering insulating layer 21. In this embodiment, in the second intersection region 34, the emitter buried body 27 includes a pair of emitter buried bodies 27 provided on both sides of the second intersection region 34 in the first direction X, sandwiching the emitter contact electrode layer 51 from both sides in the first direction X. Therefore, in the second intersection region 34, the emitter contact electrode layer 51 is in direct contact with the emitter-covering insulating layer 21 in the normal direction Z, and in contact with the emitter buried body 27 in the first direction X. The emitter contact electrode layer 51 is surrounded on three sides by the emitter-covering insulating layer 21 below and the emitter buried bodies 27 on both sides.

[0073] A collector electrode layer 61 is formed on the second main surface 4 of the chip 2. The collector electrode layer 61 is connected to the collector region 5. Although not shown, a gate main surface electrode layer having a structure similar to that of the emitter main surface electrode layer 43 may be formed on the interlayer insulating layer 41. The gate main surface electrode layer may be electrically connected to the gate electrode layer 14 via a gate contact hole formed in the interlayer insulating layer 41.

[0074] 10A, 10B to 17A, 17B are diagrams sequentially showing some of the manufacturing processes of the semiconductor device 1. In Figures 10A, 10B to 17A, 17B, the figures with "A" added to the drawing correspond to the cross section of Figure 5, and the figures with "B" added to the drawing correspond to the cross section of Figure 8.

[0075] Referring to FIGS. 10A and 10B, first, － A semiconductor wafer 26 having a type of chip 2 is prepared. The semiconductor wafer 26 has the first main surface 3 and second main surface 4 (not shown) of the chip 2 described above. Next, a p-type collector region 5 (not shown) and an n-type charge accumulation region 6 are formed in the semiconductor wafer 26. The collector region 5 is formed by introducing p-type impurities into the second main surface 4 of the semiconductor wafer 26. The collector region 5 may be formed in the surface portion of the second main surface 4 of the semiconductor wafer 26 by ion implantation using an ion implantation mask (not shown). The charge accumulation region 6 is formed by introducing n-type impurities into the first main surface 3. The charge accumulation region 6 may be formed in the surface portion of the first main surface 3 by ion implantation using an ion implantation mask (not shown).

[0076] Next, unnecessary portions of the semiconductor wafer 26 are selectively removed from the first main surface 3 using a mask having a predetermined pattern. The unnecessary portions of the semiconductor wafer 26 may be removed by etching (e.g., wet etching). As a result, the gate trench 12 and the emitter trench 17 are formed. The mask is then removed. Next, a gate insulating layer 13 and an emitter insulating layer 18 are formed on the inner walls of the gate trench 12 and the inner walls of the emitter trench 17, respectively, by, for example, thermal oxidation or wet oxidation. Next, a gate electrode layer 14 and an emitter electrode layer 19 are buried in the gate trench 12 and the emitter trench 17, respectively, by, for example, CVD. As a result, the trench gate electrode structure 10 and the trench emitter electrode structure 11 are formed.

[0077] 11A and 11B , gate electrode layer 14 and emitter electrode layer 19 are selectively removed from first main surface 3 via a mask having a predetermined pattern. This forms gate electrode recesses 15 and emitter electrode recesses 20. Unnecessary portions of gate electrode layer 14 and emitter electrode layer 19 may be removed by etching (e.g., wet etching).

[0078] 12A and 12B , a first base insulating layer 44 that serves as the base of the gate intermediate insulating layer 22 and the emitter intermediate insulating layer 28, and a second base insulating layer 45 that serves as the base of the gate covering insulating layer 16 and the emitter covering insulating layer 21, are formed. The first base insulating layer 44 may be formed, for example, by thermal oxidation treatment of the surfaces of the gate electrode layer 14 and the emitter electrode layer 19 and the surface of the semiconductor wafer 26. On the other hand, the second base insulating layer 45 may be formed by depositing an insulating material on the first base insulating layer 44, for example, by CVD. The first base insulating layer 44 and the second base insulating layer 45 are formed in the gate trench 12 and the emitter trench 17, and are also formed so as to cover the first main surface 3 of the semiconductor wafer 26.

[0079] 13A and 13B , a polysilicon layer serving as the base of the gate buried body 9 and the emitter buried body 27 is deposited, for example, by CVD over the entire surface of the first main surface 3. Thereafter, the polysilicon layer is planarized by etch-back, thereby obtaining the gate buried body 9 and the emitter buried body 27 that are buried in the gate electrode recess 15 and the emitter electrode recess 20, respectively.

[0080] Next, a p-type body region 8 and an n-type body region 9 are formed in the semiconductor wafer 26. ＋ In this case, an n-type emitter region 25 is formed. The body region 8 is formed by introducing p-type impurities into the first main surface 3. The body region 8 may be formed in the surface portion of the first main surface 3 by ion implantation using an ion implantation mask (not shown). The emitter region 25 is formed by introducing n-type impurities into the first main surface 3. The emitter region 25 may be formed in the surface portion of the first main surface 3 by ion implantation using an ion implantation mask (not shown).

[0081] 14A and 14B , an interlayer insulating layer 41 is formed on first main surface 3. Interlayer insulating layer 41 is formed on first main surface 3 so as to cover trench gate electrode structure 10 and trench emitter electrode structure 11. This step may include the step of forming an NSG film (e.g., 5000 Å) and a PSG film (e.g., 4000 Å) in this order from above first main surface 3 by a CVD method.

[0082] 15A and 15B , unnecessary portions of interlayer insulating layer 41, unnecessary portions of gate-coating insulating layer 16, and unnecessary portions of emitter-coating insulating layer 21 are selectively removed using a mask having a predetermined pattern. The unnecessary portions of interlayer insulating layer 41, etc. may be removed by etching (e.g., dry etching). This forms contact hole 42.

[0083] 16A and 16B , unnecessary portions of the semiconductor wafer 26 are removed using the mask used to form the contact holes 42. The unnecessary portions of the semiconductor wafer 26 may be removed by, for example, an etching method (e.g., dry etching). As a result, contact trenches 31 are formed in the first main surface 3. In FIG. 16A , the structure visible behind the contact trenches 31 is indicated by dashed hatching.

[0084] In this embodiment, since the semiconductor wafer 26 is a silicon single crystal substrate and the gate filling body 9 is polysilicon, the gate filling body 9 is also etched simultaneously when the contact trench 31 is formed. In addition, the second depth D2 of the contact trench 31 is greater than the thickness T4 of the gate filling body 9 (see FIGS. 15A and 15B ). Therefore, in the first intersection region 33, the gate filling body 9 is etched so that it penetrates from the first main surface 3 to the bottom wall of the gate electrode recess 15.

[0085] Next, the contact region 36 is formed in the surface portion of the first main surface 3. More specifically, the contact region 36 is formed in a region along the bottom wall of the contact trench 31 in the surface layer portion of the body region 8. The contact region 36 may also be formed in regions along the sidewall and bottom wall of the contact trench 31. The contact region 36 is formed by introducing p-type impurities into the contact trench 31. The contact region 36 may be introduced into the contact trench 31 by ion implantation using an ion implantation mask (not shown). This forms the contact region 36 along the bottom wall of the contact trench 31.

[0086] 17A and 17B , an emitter main surface electrode layer 43 is formed on the interlayer insulating layer 41. The emitter main surface electrode layer 43 may be formed by sputtering or CVD. The emitter contact electrode layer 51 is formed by the portion of the emitter main surface electrode layer 43 that extends into the contact trench 31. A collector electrode layer 61 is also formed on the second main surface 4 of the semiconductor wafer 26. The semiconductor device 1 is obtained through the steps including those described above.

[0087] As described above, according to the semiconductor device 1, the gate embedding body 9 is made of polysilicon and has an etching selectivity with respect to the interlayer insulating layer 41 made of silicon oxide or silicon nitride. The gate embedding body 9 having an etching selectivity with respect to the interlayer insulating layer 41 means, for example, that the etching selectivity (a / b) expressed as the ratio of the etching amount (a) of the interlayer insulating layer 41 to the etching amount (b) of the gate embedding body 9 is, for example, 1.5 or more, preferably 5 or more, and more preferably 10 or more.

[0088] This allows the gate buried body 9 to be used as an etching stopper when forming the contact hole 42 in the interlayer insulating layer 41 (see FIGS. 15A and 15B ). The gate intermediate insulating layer 22 can be prevented from being exposed to etching gas during the formation of the contact hole 42. Therefore, the thickness of the gate intermediate insulating layer 22 can be easily controlled to a design value by adjusting the formation conditions of the gate intermediate insulating layer 22 (e.g., thermal oxidation conditions, CVD conditions, etc.). This prevents short circuits between the gate electrode layer 14 and the emitter contact electrode layer 51 and a decrease in TZDB (Time Zero Dielectric Breakdown), and improves the controllability of the capacitance between the gate electrode layer 14 and the emitter contact electrode layer 51.

[0089] Furthermore, the gate intermediate insulating layer 22 is not etched during the formation of the contact hole 42. Therefore, it is not necessary to form the gate intermediate insulating layer 22 excessively thick to prevent a gate-emitter short circuit due to over-etching of the gate intermediate insulating layer 22. Furthermore, it is not necessary to form the gate electrode recess 15 deep in order to form a thick gate intermediate insulating layer 22. This allows the gate electrode recess 15 to be formed relatively shallow, ensuring that the opposing portions 40 of the gate electrode layer 14 facing the emitter region 25 via the gate insulating layer 13 are secured near both sides of the first intersection region 33. As a result, the region near the first intersection region 33 can be used as a channel formation region 46 (see FIG. 3 ), thereby suppressing reduction in channel width. This makes it possible to provide a semiconductor device 1 capable of reducing on-resistance.

[0090] Fig. 18 is a schematic cross-sectional view showing a partial region of a semiconductor device 71 according to a second embodiment of the present disclosure. Fig. 19 is a schematic cross-sectional view showing a partial region of a semiconductor device 71 according to a second embodiment of the present disclosure. Fig. 20 is a schematic cross-sectional view showing a partial region of a semiconductor device 71 according to a second embodiment of the present disclosure. Fig. 18 corresponds to the cross section of Fig. 5, Fig. 19 corresponds to the cross section of Fig. 6, and Fig. 20 corresponds to the cross section of Fig. 8. In the following, structures corresponding to the structures described with respect to the semiconductor device 1 according to the first embodiment are assigned the same reference numerals, and descriptions thereof will be omitted.

[0091] 18 to 20 , in the second embodiment, a first depth D1 from the first main surface 3 to the upper surface of the gate electrode layer 14 in the first intersection region 33 is deeper than a second depth D2 of the contact trench 31 in the contact region 35. Furthermore, a stacked structure of the gate-coating insulating layer 16 and the gate embedded body 9 is formed on the bottom wall of the contact trench 31 in the first intersection region 33. As a result, the gate embedded body 9 is formed to straddle from one side to the other side of the first intersection region 33 in the first direction X, as shown in FIG. 20 , and surrounds the emitter contact electrode layer 51 from three sides, namely, the lateral sides and the bottom, in the first direction X.

[0092] In addition, in the first intersection region 33, the upper end of the gate electrode layer 14 is located on the second main surface 4 side (opposite the first main surface 3) of the bottom of the emitter region 25. Therefore, in the semiconductor device 71 according to the second embodiment, the opposing portion 40 shown in FIG. 7 does not exist, and the gate electrode layer 14 does not oppose the emitter region 25 via the gate insulating layer 13 in the vicinity of both sides of the first intersection region 33 in the first direction X.

[0093] As described above, the semiconductor device 71 according to the second embodiment can also achieve the same effects as those described for the semiconductor device 1. The semiconductor device 71 can be manufactured by the method for manufacturing the semiconductor device 1, simply by changing the depths of the gate electrode recesses 15 and the emitter electrode recesses 20.

[0094] 21 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 81 according to a third embodiment of the present disclosure. In the following, structures corresponding to those described with respect to the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0095] In the above-described semiconductor device 1, an example has been described in which a p-type collector region 5 is formed in the surface portion of the second main surface 4. In contrast, in the semiconductor device 81, an n-type drain region 82 is formed in the surface portion of the second main surface 4 instead of the p-type collector region 5. As a result, the semiconductor device 81 has a basic configuration including a trench gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor). The above-described description of the semiconductor device 1 applies mutatis mutandis to the description of the semiconductor device 81, with "emitter" replaced with "source" and "collector" replaced with "drain."

[0096] As described above, semiconductor device 81 can also achieve the same effects as those described for semiconductor device 1. Semiconductor device 81 can be manufactured by the manufacturing method of semiconductor device 1, simply by forming n-type drain region 82 instead of p-type collector region 5 and changing the layout of each mask.

[0097] Fig. 22 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 91 according to a fourth embodiment of the present disclosure. Fig. 23 is a diagram showing steps related to the formation of the structure of Fig. 22. Figs. 22 and 23 show cross sections corresponding to Fig. 9 of the semiconductor device 1 described above. In the following, structures corresponding to those described with respect to the semiconductor device 1 will be assigned the same reference numerals and descriptions thereof will be omitted.

[0098] In the semiconductor device 1 described above, the width W1 of the upper end of the gate embedment 9 is narrower than the width W2 of the upper end of the gate electrode layer 14. In contrast, in the semiconductor device 91, the width W1 of the upper end of the gate embedment 9 is wider than the width W2 of the upper end of the gate electrode layer 14. More specifically, the gate trench 12 is formed in a tapered shape whose bottom area is smaller than its opening area. The angle θ2 formed by the sidewall of the gate trench 12 with respect to a plane 92 parallel to the first main surface 3 may be, for example, greater than 80° and less than 90°, preferably greater than 85° and less than 90°. Therefore, the width W1 of the gate embedment 9 formed at a position closer to the opening end of the gate trench 12 than the depth position of the gate electrode layer 14 in the depth direction of the gate trench 12 is wider than the width W2 of the gate electrode layer 14.

[0099] In the semiconductor device 1 described above, the side portion 24 of the gate-coating insulating layer 16 has a second thickness T2 at the upper end 48 that is thinner than the first thickness T1 at the lower end 47. In contrast, in the semiconductor device 91, the outer side surface 29 and the inner side surface 30 come into contact with each other at the upper end 48, so that the second thickness T2 may be 0 (zero). The upper end 48 of the side portion 24 of the gate-coating insulating layer 16 may have a sharp tip that points upward.

[0100] As described above, the semiconductor device 91 can also achieve the same effects as those described for the semiconductor device 1. The semiconductor device 91 can be manufactured by forming the gate trench 12 by etching under conditions that result in a tapered shape in the manufacturing method of the semiconductor device 1, and by forming the side portion 24 of the gate-coating insulating layer 16 so as to have a tapered shape. Although not described above, the mesa structure 93 of the chip 2 formed on the side of the gate trench 12 (the portion where the emitter region 25, etc., is formed) may be trapezoidal in cross section and have a rounded upper end portion 94. By forming the gate-coating insulating layer 16 on such a mesa structure 93 under conditions that result in a tapered shape, the width W1 of the gate embedded body 9 can be made wider than the width W2 of the gate electrode layer 14.

[0101] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0102] For example, in each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0103] In the above-described embodiments, the chip 2 is made of single crystal silicon. However, the chip 2 may contain SiC. Alternatively, the chip 2 may be made of single crystal SiC.

[0104] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0105] The following characteristics can be extracted from the description of this specification and the drawings.

[0106] [Supplementary Note 1-1] A chip (2) having a first main surface (3) in which a gate trench (12) extending in a first direction (X) is formed; a body region (8) of a first conductivity type formed along a sidewall of the gate trench (12) in a surface portion of the first main surface (3); a first impurity region (25) of a second conductivity type formed along a sidewall of the gate trench (12) in a surface portion of the body region (8); a gate insulating layer (13) formed on an inner wall of the gate trench (12); and a gate electrode (14) embedded in the gate trench (12) and facing the body region (8) and the first impurity region (25) across the gate insulating layer (13); the surface insulating layer (41) being formed on the first main surface (3) so as to cover the gate electrode (14), and having a contact hole (42) drawn from a region above the gate trench (12) to the outside of the gate trench (12) along a second direction (Y) intersecting the first direction (X); a contact electrode (51) being electrically connected to the body region (8) and the first impurity region (25) via the contact hole (42), and drawn from within the gate trench (12) to a surface portion of the first main surface (3) via a sidewall of the gate trench (12); and a covering insulating layer (16) covering the gate electrode (14) within the gate trench (12) and providing insulation between the gate electrode (14) and the contact electrode (51); a buried body (9) buried in a region above the covering insulating layer (16) in the gate trench (12) and having an etching selectivity with respect to the surface insulating layer (41).

[0107] [Appendix 1-2] The semiconductor device (1, 71, 81) according to Appendix 1-1, wherein the covering insulating layer (16) includes a bottom portion (23) covering an upper surface of the gate electrode (14) and a side portion (24) extending upward from the bottom portion (23) along a sidewall of the gate trench (12).

[0108] [Appendix 1-3] The semiconductor device (1, 71, 81) according to Appendix 1-2, wherein the bottom (23) of the covering insulating layer (16) has a thickness of 150 nm or more and 300 nm or less.

[0109] [Appendix 1-4] The semiconductor device (1, 71, 81) according to Appendix 1-2 or Appendix 1-3, wherein the side portion (24) of the covering insulating layer (16) has a first thickness (T1) at a lower end (47) in the depth direction of the gate trench (12), and a second thickness (T2) thinner than the first thickness (T1) at an upper end (48) in the depth direction of the gate trench (12).

[0110] [Supplementary Note 1-5] The semiconductor device (1, 71, 81) according to any one of Supplementary Note 1-2 to Supplementary Note 1-4, wherein the side portion (24) of the covering insulating layer (16) has a tapered shape in cross section, in which an outer side surface (29) on the side closer to the sidewall of the gate trench (12) and an inner side surface (30) on the opposite side of the outer side surface (29) are inclined toward each other from the lower end (47) to the upper end (48).

[0111] [Supplementary Note 1-6] The semiconductor device (1, 71, 81) according to any one of Supplementary Note 1-1 to Supplementary Note 1-5, comprising: a contact trench (31) formed in a surface portion of the first main surface (3) so as to extend along the contact hole (42), the contact trench having a bottom wall (37, 38) and a sidewall; the body region (8) being formed along at least the bottom wall (37, 38) of the contact trench (31); the first impurity region (25) being formed along at least the sidewall of the contact trench (31); and the contact electrode (51) being embedded in the contact trench (31) and connected to the body region (8) and the first impurity region (25) inside the contact trench (31).

[0112] [Appendix 1-7] The semiconductor device (1, 81) according to Appendix 1-6, wherein the contact trench (31) includes an intersection region (33) that intersects with the gate trench (12), and a contact region (35) that is drawn out from the intersection region (33) to the outside of the gate trench (12) and exposes the body region (8) and the first impurity region (25), and a depth (D1) from the first main surface (3) to an upper surface of the gate electrode (14) in the intersection region (33) is shallower than a depth (D2) from the first main surface (3) to a bottom wall of the contact trench (31) in the contact region (35).

[0113] [Appendix 1-8] The semiconductor device (1, 81) according to Appendix 1-7, wherein the bottom (23) of the covering insulating layer (16) is exposed at the bottom wall (37) of the contact trench (31) in the intersection region (33), and the embedded bodies (9) include a pair of embedded bodies (9) provided on both sides of the intersection region (33) in the first direction (X) and sandwiching the contact electrode (51) from both sides in the first direction (X).

[0114] [Appendix 1-9] The semiconductor device (1, 81) according to appendix 1-7 or appendix 1-8, wherein a depth (D1) from the first main surface (3) to an upper surface of the gate electrode (14) in the intersection region (33) is 1 μm or less.

[0115] [Appendix 1-10] The semiconductor device (71) according to Appendix 1-6, wherein the contact trench (31) includes an intersection region (33) that intersects with the gate trench (12), and a contact region that is drawn out from the intersection region (33) to the outside of the gate trench (12) and exposes the body region (8) and the first impurity region (25), and a depth (D1) from the first main surface (3) to an upper surface of the gate electrode (14) in the intersection region (33) is deeper than a depth (D2) from the first main surface (3) to a bottom wall of the contact trench (31) in the contact region.

[0116] [Appendix 1-11] The semiconductor device (71) according to Appendix 1-10, wherein a laminated structure of the bottom (23) of the covering insulating layer (16) and the embedded body (9) is formed on the bottom wall (37) of the contact trench (31) in the intersection region (33), and the embedded body (9) is formed so as to straddle from one side of the intersection region (33) to the other side in the first direction (X) and surrounds the contact electrode (51) from three sides, i.e., from below and to the sides on both sides in the first direction (X).

[0117] [Appendix 1-12] The semiconductor device (1, 71, 81) according to any one of Appendices 1-1 to 1-11, wherein the etching selectivity of the embedded body (9) to the surface insulating layer (41) is 1.5 or more.

[0118] [Supplementary Note 1-13] The semiconductor device (1, 71, 81) according to any one of Supplementary Note 1-1 to Supplementary Note 1-12, wherein the buried body (9) is formed from the same material as the gate electrode (14).

[0119] [Appendix 1-14] The semiconductor device (1, 71, 81) according to any one of Appendices 1-1 to 1-12, wherein the surface insulating layer (41) is formed of silicon oxide, and the gate electrode (14) and the buried body (9) are formed of polysilicon.

[0120] [Supplementary Note 1-15] A semiconductor wafer (26) having a first main surface (3) in which a gate trench (12) is formed includes a step of forming a gate insulating layer (13) on an inner wall of the gate trench (12); a step of embedding a gate electrode (14) in the gate trench (12) after forming the gate insulating layer (13); a step of selectively removing the gate electrode (14) from an upper surface side to form a recess (15) in the gate trench (12); a step of forming a covering insulating layer (16) in the recess (15) so as to cover an upper surface of the gate electrode (14); a step of embedding a buried body (9) in a region on the covering insulating layer (16) in the recess (15); and a step of selectively implanting a first conductivity type impurity into a surface portion of the first main surface (3) to form a body region (8) along a sidewall of the gate trench (12). the step of selectively implanting a second conductivity type impurity into a surface portion of the body region (8) to form a first impurity region (25) along a sidewall of the gate trench (12); the step of forming a surface insulating layer (41) on the first main surface (3) so as to cover the gate electrode (14) and the buried body (9); the step of selectively etching the surface insulating layer (41) to form a contact hole (42) intersecting the gate trench (12) so as to selectively expose the buried body (9) and the first main surface (3); the step of forming a contact trench (31) in a surface portion of the first main surface (3) so as to expose the body region (8) and the first impurity region (25) by etching through the contact hole (42); and the step of forming a contact electrode (51) connected to the body region (8) and the first impurity so as to be embedded in the contact trench (31), A method for manufacturing a semiconductor device (1, 71, 81), wherein the embedded body (9) is formed of a material having an etching selectivity with respect to the surface insulating layer (41).

[0121] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5: Collector region 6: Charge storage region 7: Drift region 8: Body region 9: Gate buried body 10: Trench gate electrode structure 11: Trench emitter electrode structure 12: Gate trench 13: Gate insulating layer 14: Gate electrode layer 15: Gate electrode recess 16: Gate coating insulating layer 17: Emitter trench 18: Emitter insulating layer 19: Emitter electrode layer 20: Emitter electrode recess 21: Emitter coating insulating layer 22: Gate intermediate insulating layer 23: Bottom 24: Side 25: Emitter region 26: Semiconductor wafer 27: Emitter buried body 28: Emitter intermediate insulating layer 29: Outer side surface 30: Inner side surface 31: Contact trench 32: Lead-out portion 33: First intersection region 34: Second intersection region 35: Contact region 36: Contact region 37: First bottom wall 38: Second bottom wall 39: Step 40: Facing portion 41: Interlayer insulating layer 42: Contact hole 43: Emitter main surface electrode layer 44: First base insulating layer 45: Second base insulating layer 46: Channel forming region 47: Lower end portion 48: Upper end portion 51: Emitter contact electrode layer 61: Collector electrode layer 71: Semiconductor device 81: Semiconductor device 82: Drain region 91: Semiconductor device 92: Parallel surface 93: Mesa structure 94: Upper end portion CH: Channel D1: First depth D2: Second depth P0: Trench pitch S: Step T1: First thickness T2: Second thickness T3: Third thickness T4: Thickness W1: Width W2: Width X: First direction Y: Second direction Z: Normal direction

Claims

1. a chip having a first main surface with a gate trench formed therein extending in a first direction; a first conductivity type body region formed along a sidewall of the gate trench in a surface portion of the first main surface; a first impurity region of a second conductivity type formed along a sidewall of the gate trench in a surface portion of the body region; a gate insulating layer formed on an inner wall of the gate trench; a gate electrode embedded in the gate trench and facing the body region and the first impurity region with the gate insulating layer interposed therebetween; the surface insulating layer is formed on the first main surface so as to cover the gate electrode, and has a contact hole extending from a region on the gate trench to an outside of the gate trench along a second direction intersecting the first direction; a contact electrode electrically connected to the body region and the first impurity region through the contact hole and extending from within the gate trench to a surface portion of the first main surface through a sidewall of the gate trench; a covering insulating layer that covers the gate electrode in the gate trench and provides insulation between the gate electrode and the contact electrode; a buried body buried in a region on the covering insulating layer within the gate trench and having an etching selectivity with respect to the surface insulating layer.

2. 2 . The semiconductor device according to claim 1 , wherein said covering insulating layer includes a bottom portion covering an upper surface of said gate electrode, and a side portion extending upward from said bottom portion along a sidewall of said gate trench.

3. The semiconductor device according to claim 2 , wherein the bottom portion of the covering insulating layer has a thickness of 150 nm or more and 300 nm or less.

4. 4. The semiconductor device according to claim 2, wherein the side of the covering insulating layer has a first thickness at a lower end in the depth direction of the gate trench, and a second thickness thinner than the first thickness at an upper end in the depth direction of the gate trench.

5. 4. The semiconductor device according to claim 2, wherein the side of the covering insulating layer has a tapered shape in which an outer side surface closer to the sidewall of the gate trench and an inner side surface opposite the outer side surface are inclined toward each other from the lower end to the upper end in a cross-sectional view.

6. a contact trench formed in a surface portion of the first main surface so as to extend along the contact hole, the contact trench having a bottom wall and a side wall; the body region is formed along at least the bottom wall of the contact trench; the first impurity region is formed at least along the sidewall of the contact trench; 4. The semiconductor device according to claim 1, wherein the contact electrode is embedded in the contact trench and is connected to the body region and the first impurity region inside the contact trench.

7. the contact trench includes an intersection region that intersects with the gate trench, and a contact region that is drawn out from the intersection region to the outside of the gate trench and exposes the body region and the first impurity region; 7. The semiconductor device according to claim 6, wherein a depth from said first main surface to an upper surface of said gate electrode in said intersection region is shallower than a depth from said first main surface to a bottom wall of said contact trench in said contact region.

8. the bottom of the covering insulating layer is exposed to the bottom wall of the contact trench in the intersection region; 8. The semiconductor device according to claim 7, wherein the embedded body includes a pair of embedded bodies provided on both sides of the intersection region in the first direction, sandwiching the contact electrode from both sides in the first direction.

9. 8. The semiconductor device according to claim 7, wherein a depth from said first main surface to an upper surface of said gate electrode in said intersection region is 1 [mu]m or less.

10. the contact trench includes an intersection region that intersects with the gate trench, and a contact region that is drawn out from the intersection region to the outside of the gate trench and exposes the body region and the first impurity region; 7. The semiconductor device according to claim 6, wherein a depth from said first main surface to an upper surface of said gate electrode in said intersection region is greater than a depth from said first main surface to a bottom wall of said contact trench in said contact region.

11. a laminated structure of the bottom of the covering insulating layer and the filling body is formed on the bottom wall of the contact trench in the intersection region, 11. The semiconductor device according to claim 10, wherein the buried body is formed so as to span from one side of the intersection region to the other side in the first direction and surrounds the contact electrode from three sides, including both lateral sides and below, in the first direction.

12. 4. The semiconductor device according to claim 1, wherein an etching selectivity of said filling body to said surface insulating layer is 1.5 or more.

13. 4. The semiconductor device according to claim 1, wherein the buried body is made of the same material as the gate electrode.

14. the surface insulating layer is formed of silicon oxide, 4. The semiconductor device according to claim 1, wherein the gate electrode and the buried body are made of polysilicon.

15. forming a gate insulating layer on an inner wall of a gate trench of a semiconductor wafer having a first main surface in which the gate trench is formed; After forming the gate insulating layer, embedding a gate electrode in the gate trench; selectively removing the gate electrode from a top surface side to form a recess in the gate trench; forming a covering insulating layer in the recess so as to cover an upper surface of the gate electrode; embedding an embedding body in a region on the covering insulating layer within the recess; forming a body region along a sidewall of the gate trench by selectively implanting an impurity of a first conductivity type into a surface portion of the first major surface; forming a first impurity region along a sidewall of the gate trench by selectively implanting an impurity of a second conductivity type into a surface portion of the body region; forming a surface insulating layer on the first main surface so as to cover the gate electrode and the buried body; forming a contact hole intersecting the gate trench by selectively etching the surface insulating layer so as to selectively expose the buried body and the first main surface; forming a contact trench in a surface portion of the first main surface by etching through the contact hole so that the body region and the first impurity region are exposed; forming a contact electrode connected to the body region and the first impurity so as to be embedded in the contact trench; The method for manufacturing a semiconductor device, wherein the buried body is formed of a material having an etching selectivity with respect to the surface insulating layer.