Semiconductor device

Abstract

Provided is a semiconductor device comprising: a gate electrode layer embedded in a gate trench; a contact trench including a first intersecting region intersecting the gate trench; and an emitter contact electrode layer embedded in the contact trench. A gate electrode recess is formed in the first intersecting region and a peripheral portion to the first intersecting region of the gate trench. A gate-coating insulation layer is embedded in the gate electrode recess. The emitter region is formed deeper than the upper surface of the gate electrode layer in the peripheral portion to the first intersecting region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Patent Application No. 2022-143916 filed with the Japan Patent Office on September 9, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including: a semiconductor layer having a main surface in which a trench is formed; a body region of a first conductivity type formed along a sidewall of the trench in a surface portion of the main surface of the semiconductor layer; an impurity region of a second conductivity type formed along the sidewall of the trench in a surface portion of the body region; a gate insulating layer formed on an inner wall of the trench; a gate electrode embedded in the trench and facing the body region and the impurity region with the gate insulating layer between them; a contact electrode extending from within the trench through the sidewall of the trench to a surface portion of the main surface of the semiconductor layer and electrically connected to the body region and the impurity region; and a buried insulating layer interposed in the trench between the gate electrode and the contact electrode and insulating the gate electrode and the contact electrode.

[0004] International Publication No. 2019 / 103135

[0005] An embodiment of the present disclosure provides a semiconductor device that can improve the degree of freedom in designing the dimensions of a first impurity region such as an emitter region and a source region, thereby improving breakdown resistance.

[0006] An embodiment of the present disclosure provides a semiconductor device that can suppress a reduction in channel width and reduce on-resistance in a structure including a contact trench that intersects with a gate trench.

[0007] A semiconductor device according to an embodiment of the present disclosure includes a chip having a first main surface in which a gate trench having a bottom wall and a sidewall is formed, the gate trench extending in a first direction, a body region of a first conductivity type formed along the sidewall of the gate trench in a surface portion of the first main surface, a first impurity region of a second conductivity type formed along the sidewall of the gate trench in a surface portion of the body region, a gate insulating layer formed on the bottom wall and the sidewall of the gate trench, a gate electrode embedded in the gate trench and facing the body region and the first impurity region with the gate insulating layer interposed therebetween, and an intersection region that intersects with the gate trench, the intersection region extending along a second direction that intersects with the first direction. The gate trench includes a contact trench extending from the difference region to the outside of the gate trench, and a contact electrode embedded in the contact trench and electrically connected to the body region and the first impurity region inside the contact trench, wherein a space region is formed on the gate electrode at least in the intersection region and the periphery of the intersection region in the gate trench, and a covering insulating layer is embedded in the space region, covering the upper surface of the gate electrode in the intersection region and the periphery of the intersection region, and providing insulation between the gate electrode and the contact electrode, and the first impurity region is formed deeper than the upper surface of the gate electrode in the periphery of the intersection region.

[0008] According to an embodiment of the present disclosure, the first impurity region is formed deeper than the top surface of the gate electrode in the peripheral portion of the intersection region, thereby allowing a channel to be formed in the peripheral portion of the intersection region, thereby suppressing a reduction in the channel width and reducing the on-resistance.

[0009] According to an embodiment of the present disclosure, the first impurity region is formed deeper than the top surface of the gate electrode. This allows a channel to be formed in a lower region around the intersection region. This eliminates the need to consider patterning margins during etching and contact pattern formation, improving design flexibility for the dimensions of the first impurity region and thereby improving breakdown voltage.

[0010] FIG. 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a view in which a structure on a first main surface of a chip is removed from FIG. 1 . FIG. 3 is a view in which an emitter contact electrode layer is removed from FIG. 2 . FIG. 4 is a schematic plan view of FIG. 3 as viewed from the first main surface of the chip. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 4 . FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4 . FIG. 8A is a view showing an example of a method for manufacturing the semiconductor device. FIG. 8B is a view showing a process subsequent to FIG. 8A . FIG. 8C is a view showing a process subsequent to FIG. 8B . FIG. 8D is a view showing a process subsequent to FIG. 8C . FIG. 8E is a view showing a process subsequent to FIG. 8D . FIG. 8F is a view showing a process subsequent to FIG. 8E . FIG. 8G is a view showing a process subsequent to FIG. 8F . FIG. 8H is a view showing a process subsequent to FIG. 8G . FIG. 8I is a view showing a process subsequent to FIG. 8H . FIG. 8J is a diagram illustrating a process subsequent to FIG. 8I. FIG. 8K is a diagram illustrating a process subsequent to FIG. 8J. FIG. 8L is a diagram illustrating a process subsequent to FIG. 8K. FIG. 8M is a diagram illustrating a process subsequent to FIG. 8L. FIG. 8N is a diagram illustrating a process subsequent to FIG. 8M. FIG. 9A is a diagram illustrating channel formation in a semiconductor device according to condition 1. FIG. 9B is a diagram illustrating an arrangement pattern of emitter regions and contact regions in a semiconductor device according to condition 1. FIG. 10A is a diagram illustrating channel formation in a semiconductor device according to condition 2. FIG. 10B is a diagram illustrating an arrangement pattern of emitter regions and contact regions in a semiconductor device according to condition 2. FIG. 11 is a graph illustrating short-circuit waveforms of semiconductor devices according to conditions 1 and 2, obtained by simulation. FIG. 12 is a graph illustrating current-voltage characteristics of semiconductor devices according to conditions 1 and 2, obtained by simulation. FIG. 13 is a diagram illustrating an enlarged portion of the graph of FIG. 12. FIG. 14 is a graph illustrating current-voltage characteristics of semiconductor devices according to conditions 1 and 2, obtained by simulation. Fig. 15 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a second embodiment of the present disclosure. Fig. 16 is a schematic cross-sectional view showing a portion of the semiconductor device of Fig. 15. Fig. 17 is a schematic cross-sectional view showing a portion of the semiconductor device of Fig. 15.FIG. 18 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device according to a third embodiment of the present disclosure.

[0011] <<Description of the Structure of Semiconductor Device 1 (First Embodiment)>> Fig. 1 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 1 according to a first embodiment of the present disclosure. Fig. 2 is a view in which the structure above a first main surface 3 of a chip 2 is removed from Fig. 1. Fig. 3 is a view in which an emitter contact electrode layer 51 is removed from Fig. 2.

[0012] 4 is a schematic plan view of FIG. 3 as viewed from the first main surface 3 of the chip 2. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIGS. 5 to 7 also show the structure on the first main surface 3 of the chip 2.

[0013] In this embodiment, the semiconductor device 1 has a basic configuration including a trench gate type IGBT (Insulated Gate Bipolar Transistor). － The chip 2 includes a chip of type n － The silicon single crystal substrate is made of n-type single crystal silicon manufactured by the FZ (Floating Zone) method. － The chip 2 is formed using a single crystal silicon semiconductor wafer. The chip 2 may be called a semiconductor chip or a semiconductor layer.

[0014] The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The thickness of the chip 2 may be 50 μm or more and 300 μm or less. The thickness of the chip 2 may be 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, or 250 μm or more and 300 μm or less.

[0015] A p-type collector region 5 is formed in the surface portion of the second main surface 4. An n-type charge accumulation region 6 is formed in the surface portion of the first main surface 3. The charge accumulation region 6 is formed on the first main surface 3 side with a gap between it and the collector region 5.

[0016] In the chip 2, the region between the collector region 5 and the charge storage region 6 is － A p-type drift region 7 is formed on the chip 2. The drift region 7 is formed by a region located between the collector region 5 and the charge storage region 6 in the chip 2. A p-type body region 8 is formed in the surface portion of the charge storage region 6. A plurality of trench gate electrode structures 10 and a plurality of trench emitter electrode structures 11 are formed at intervals on the surface portion of the first main surface 3.

[0017] 1 to 7 show only one adjacent trench gate electrode structure 10 and one adjacent trench emitter electrode structure 11. Below, the structure of the semiconductor device 1 will be described focusing on the structure of this one trench gate electrode structure 10 and this one adjacent trench emitter electrode structure 11.

[0018] In a plan view, the trench gate electrode structure 10 and the trench emitter electrode structure 11 extend in a strip shape along an arbitrary first direction X. The trench gate electrode structure 10 and the trench emitter electrode structure 11 are formed at intervals along a second direction Y that intersects with the first direction X.

[0019] More specifically, the planar view refers to a planar view seen from the normal direction Z (hereinafter simply referred to as the "normal direction Z") of the first main surface 3. More specifically, the second direction Y is a direction perpendicular to the first direction X. The first direction X and the second direction Y are also tangential directions of the first main surface 3.

[0020] The trench pitch P0 between the trench gate electrode structure 10 and the trench emitter electrode structure 11 may be 0.1 μm or more and less than 0.6 μm. The trench pitch P0 may be 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, or 0.5 μm or more and less than 0.6 μm. The trench pitch P0 is preferably 0.2 μm or more and 0.4 μm or less (for example, approximately 0.25 μm).

[0021] The trench gate electrode structure 10 includes a gate trench 12, a gate insulating layer 13, a gate electrode layer 14, a plurality of gate electrode recesses 15 (space regions), and a plurality of gate covering insulating layers 16. The gate trench 12 extends from the first main surface 3, through the body region 8 and the charge storage region 6, and reaches the drift region 7.

[0022] The depth of the gate trench 12 may be 2.0 μm or more and 4.0 μm or less. The depth of the gate trench 12 may be 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, or 3.5 μm or more and 4.0 μm or less. The depth of the gate trench 12 is preferably 2.5 μm or more and 3.5 μm or less (for example, about 3.0 μm).

[0023] The second direction width of the gate trench 12 may be 0.5 μm or more and 1.5 μm or less. The second direction width of the gate trench 12 may be 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1.0 μm or less, 1.0 μm or more and 1.25 μm or less, or 1.25 μm or more and 1.5 μm or less. The second direction width of the gate trench 12 is preferably 0.5 μm or more and 1.0 μm or less (for example, about 0.75 μm).

[0024] The gate insulating layer 13 may be made of silicon oxide. The gate insulating layer 13 is formed in a film shape along the inner wall of the gate trench 12. The gate insulating layer 13 defines a recessed space within the gate trench 12.

[0025] The gate electrode layer 14 may be formed of conductive polysilicon. The gate electrode layer 14 is controlled by a gate voltage. The gate electrode layer 14 is embedded in the gate trench 12 with the gate insulating layer 13 sandwiched therebetween. More specifically, the gate electrode layer 14 is embedded in a concave space defined by the gate insulating layer 13 within the gate trench 12. The upper end of the gate electrode layer 14 is located on the first main surface 3 side relative to the bottom of the body region 8.

[0026] In this embodiment, the plurality of gate electrode recesses 15 are formed in the main surface of the gate electrode layer 14 at intervals along the first direction X. As a result, the upper end of the gate electrode layer 14 has an uneven structure including the plurality of gate electrode recesses 15.

[0027] The interval between adjacent gate electrode recesses 15 may be greater than 0 μm and less than or equal to 10 μm. The interval between adjacent gate electrode recesses 15 is also the width in the first direction X of a portion of the gate electrode layer 14 that is sandwiched between two adjacent gate electrode recesses 15. The interval between adjacent gate electrode recesses 15 may be greater than 0 μm and less than or equal to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm.

[0028] In this embodiment, the sidewalls of each gate electrode recess 15 are formed by the gate insulating layer 13 and the gate electrode layer 14. The bottom wall 22 of each gate electrode recess 15 is formed by the gate electrode layer 14. With reference to Figures 6 and 7, the bottom wall 22 of each gate electrode recess 15 is located in a region between the first main surface 3 and a bottom 50 of an emitter region 25 (described later) in relation to the normal direction Z.

[0029] 6 , each gate electrode recess 15 is formed in a tapered shape with a bottom area smaller than an opening area. The angle θ formed between the main surface of gate electrode layer 14 and the sidewall of gate electrode recess 15 within gate electrode layer 14 may be greater than 90° and less than or equal to 105° (for example, approximately 102°).

[0030] The plurality of gate-coating insulating layers 16 are respectively embedded in the upper end of the gate electrode layer 14 in the gate trench 12. More specifically, the gate-coating insulating layers 16 are embedded independently in each gate electrode recess 15. Each gate-coating insulating layer 16 is exposed from the opening of the gate trench 12.

[0031] The trench emitter electrode structure 11 includes an emitter trench 17, an emitter insulating layer 18, an emitter electrode layer 19, an emitter electrode recess 20, and an emitter covering insulating layer 21. The emitter trench 17 extends from the first main surface 3, through the body region 8 and the charge accumulation region 6, and reaches the drift region 7.

[0032] The depth of the emitter trench 17 may be 2.0 μm or more and 4.0 μm or less. The depth of the emitter trench 17 may be 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, or 3.5 μm or more and 4.0 μm or less. The depth of the emitter trench 17 is preferably 2.5 μm or more and 3.5 μm or less (for example, about 3.0 μm). The depth of the emitter trench 17 is preferably approximately equal to the depth of the gate trench 12.

[0033] The width in the second direction of the emitter trench 17 may be 0.5 μm or more and 1.5 μm or less. The width in the second direction of the emitter trench 17 may be 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1.0 μm or less, 1.0 μm or more and 1.25 μm or less, or 1.25 μm or more and 1.5 μm or less. The width in the second direction of the emitter trench 17 is preferably 0.5 μm or more and 1.0 μm or less (for example, approximately 0.75 μm). The width in the second direction of the emitter trench 17 is preferably approximately equal to the width in the second direction of the gate trench 12.

[0034] The emitter insulating layer 18 may be made of silicon oxide. The emitter insulating layer 18 is formed in the form of a film along the inner wall surface of the emitter trench 17. The emitter insulating layer 18 defines a recessed space within the emitter trench 17.

[0035] The emitter electrode layer 19 may be formed of conductive polysilicon. The emitter electrode layer 19 is controlled by an emitter voltage. The emitter voltage has a voltage value less than the gate voltage. The emitter voltage may be a reference voltage (e.g., ground voltage). The emitter electrode layer 19 is embedded in the emitter trench 17 with the emitter insulating layer 18 sandwiched therebetween. More specifically, the emitter electrode layer 19 is embedded in a concave space defined by the emitter insulating layer 18 within the emitter trench 17.

[0036] In this embodiment, the emitter electrode recess 20 is formed so as to dig down almost the entire main surface of the emitter electrode layer 19. In other words, the emitter electrode layer 19 is embedded up to a midpoint in the depth direction of the recessed space defined by the emitter insulating layer 18.

[0037] In this embodiment, the sidewalls of the emitter electrode recesses 20 are formed by the emitter insulating layer 18. The bottom walls of the emitter electrode recesses 20 are formed by the emitter electrode layer 19. The bottom walls of the emitter electrode recesses 20 are located in a region between the first main surface 3 and the bottoms 50 of the emitter regions 25 (described later) in the normal direction Z. In other words, the upper end of the emitter electrode layer 19 is located on the first main surface 3 side of the bottoms 50 of the emitter regions 25. In the normal direction Z, the depth of the emitter electrode recesses 20 may be approximately equal to the depth of the gate electrode recesses 15.

[0038] The emitter-coating insulating layer 21 is embedded in the emitter trench 17 on the upper surface of the emitter electrode layer 19. More specifically, the emitter-coating insulating layer 21 is embedded in the emitter electrode recess 20. In this way, the emitter-coating insulating layer 21 seals the emitter electrode layer 19. The emitter-coating insulating layer 21 is exposed from the opening of the emitter trench 17.

[0039] In the surface portion of the body region 8, the region along the sidewall of the gate trench 12 has n ＋A plurality of emitter regions 25 (first impurity regions) of the type are formed in the gate trench 12. More specifically, the emitter regions 25 are formed along one sidewall and the other sidewall of the gate trench 12 in the first direction X. The plurality of emitter regions 25 are each formed in a strip shape extending along the first direction X. The emitter regions 25 are in contact with the sidewall of the gate trench 12. The emitter regions 25 are also in contact with the sidewall of the emitter trench 17.

[0040] In a region along the sidewall of gate trench 12 in the surface portion of first main surface 3, emitter region 25, body region 8, charge storage region 6, and drift region 7 are formed in this order from first main surface 3 toward second main surface 4. A channel CH of the IGBT is formed in a region of body region 8 facing gate electrode layer 14 with gate insulating layer 13 sandwiched therebetween.

[0041] 3 , 4 , 6 and 7 , a plurality of contact trenches 31 are formed in a surface portion of the first main surface 3. The plurality of contact trenches 31 are formed at intervals along the first direction X. The plurality of contact trenches 31 are each formed in a strip shape extending along the second direction Y. The width in the first direction of each contact trench 31 is smaller than the width in the second direction of the gate trench 12. The width in the first direction of each contact trench 31 may be, for example, not less than 0.3 μm and not more than 1.0 μm.

[0042] More specifically, each contact trench 31 extends from an inner region of the corresponding gate-coating insulating layer 16 through the sidewall of the gate trench 12 to the surface portion of the first main surface 3. In this embodiment, each contact trench 31 extends from an inner region of the gate-coating insulating layer 16 through one sidewall and the other sidewall of the gate trench 12 in the first direction X. The width in the first direction of each contact trench 31 is smaller than the width in the first direction of the corresponding gate-coating insulating layer 16.

[0043] Each contact trench 31 includes a first intersection region 33 that intersects with the gate electrode layer 14 in a plan view. In the first intersection region 33, the sidewalls and bottom wall of each contact trench 31 are formed by the gate-coating insulating layer 16.

[0044] Each contact trench 31 includes a second intersection region 34 that intersects with the emitter electrode layer 19 in plan view. In the second intersection region 34, the sidewalls and bottom wall of each contact trench 31 are formed by the emitter-coating insulating layer 21.

[0045] Each contact trench 31 further includes a contact region 35 extended from the first intersection region 33 to the outside of the gate trench 12. The contact region 35 may also be referred to as a connection region that connects the first intersection region 33 and the second intersection region 34 in a region between the gate trench 12 and the emitter trench 17 in a plan view. In the contact region 35, the bottom wall of each contact trench 31 is formed by the body region 8, and the sidewall of each contact trench 31 is formed by the emitter region 25. That is, the emitter region 25 is exposed on the sidewall of the contact trench 31 in the contact region 35.

[0046] Each contact trench 31 further has a lead-out portion 32 led out from one sidewall of the emitter trench 17. Each lead-out portion 32 penetrates one sidewall of the emitter trench 17 from the surface portion of the first main surface 3 and reaches the inside of the emitter trench 17.

[0047] The sidewalls of each contact trench 31 are formed flush with each other in the first intersection region 33, the second intersection region 34, and the contact region 35. The bottom wall of each contact trench 31 is formed flush with each other in the first intersection region 33, the second intersection region 34, and the contact region 35.

[0048] In the first intersection region 33, the upper end of the gate electrode layer 14 is located closer to the first main surface 3 than the bottom 50 of the emitter region 25. As a result, referring to Figures 6 and 7, the emitter region 25 has opposing portions 40 that oppose the gate electrode layer 14 with the gate insulating layer 13 interposed therebetween below the peripheral portions 9 on both sides of the first intersection region 33 in the first direction X.

[0049] The gate electrode layer 14 has an electrode unevenness structure formed by gate electrode recesses 15 formed in the first intersection regions 33 and peripheral portions 9 of each contact trench 31 along the first direction X. A part of the upper surface of the gate electrode layer 14 (upper surfaces 23 of the protrusions of the electrode unevenness structure) is exposed between adjacent contact trenches 31.

[0050] The gate electrode recess 15 is formed across the peripheral portion 9 on one side and the peripheral portion 9 on the other side of the first intersection region 33 in the first direction X. As a result, referring to Figures 6 and 7, the gate-coating insulating layer 16 has a first portion 47 arranged in the first intersection region 33, and second portions 48 arranged in the peripheral portion 9 on one side and the peripheral portion 9 on the other side of the first portion 47 in the first direction X.

[0051] The peripheral portion 9 of the first intersection region 33 may be, for example, a region from the sidewall of the contact trench 31 to the sidewall of the gate electrode recess 15. The peripheral portion 9 may be, for example, a region in a range of 0.05 μm to 0.5 μm from the sidewall of the first intersection region 33. That is, in this embodiment, the sidewalls of the gate electrode recess 15 are formed on both sides of the contact trench 31 in the first direction X, with an interval of 0.05 μm to 0.5 μm between them.

[0052] The arrangement of the multiple contact trenches 31 is arbitrary. The multiple contact trenches 31 may be formed at equal intervals along the first direction X. The multiple contact trenches 31 may be formed at unequal intervals along the first direction X.

[0053] In the body region 8, the region along the bottom wall of each contact trench 31 is ＋ The contact region 36 may be formed in the body region 8 along the bottom wall and sidewall of each contact trench 31.

[0054] The contact region 36 has an exposed surface exposed from the bottom wall of the contact trench 31. The exposed surface of the contact region 36 is formed in a region between the first main surface 3 and the bottom of the body region 8. More specifically, the exposed surface of the contact region 36 is formed in a region between the first main surface 3 and a bottom 50 of the emitter region 25. In this embodiment, the body region 8 has a body region protrusion 49 that selectively protrudes toward the first main surface 3 along the contact trench 31. The contact region 36 is formed at the tip of the body region protrusion 49. The body region protrusion 49 is sandwiched between the emitter regions 25 in the first direction X.

[0055] 1 to 3 show an example in which the contact region 36 is shallowly formed on the bottom surface of the contact trench 31 by a single ion implantation. However, the contact region 36 may be formed deeper by adjusting the number of ion implantations or the energy of the ion implantation. For example, the contact region 36 may be formed deeper than the bottom 50 of the emitter region 25.

[0056] An interlayer insulating layer 41 is formed on the first main surface 3. The interlayer insulating layer 41 covers the trench gate electrode structure 10 and the trench emitter electrode structure 11. The interlayer insulating layer 41 covers the gate-coating insulating layer 16 exposed from the gate trench 12 and the emitter-coating insulating layer 21 exposed from the emitter trench 17.

[0057] The interlayer insulating layer 41 may be formed of silicon oxide or silicon nitride. ２ The insulating film may have a laminated structure including an oxide film (SiO ２ The film may include a non-doped silicon glass (NSG) film that does not contain impurities and / or a phosphorus silicon glass (PSG) film that contains phosphorus.

[0058] Interlayer insulating layer 41 may have a layered structure including an NSG film and a PSG film stacked in this order from first main surface 3. The thickness of the NSG film may be 2000 Å or more and 8000 Å or less (e.g., about 5000 Å). The thickness of the PSG film may be 2000 Å or more and 6000 Å or less (e.g., about 4000 Å).

[0059] A plurality of contact holes 42 are formed in the interlayer insulating layer 41. Each of the plurality of contact holes 42 communicates with a corresponding contact trench 31. That is, the plurality of contact holes 42 are formed at intervals along the first direction X and are each formed in a strip shape extending along the second direction Y.

[0060] The plurality of contact holes 42 penetrate the interlayer insulating layer 41 and communicate with the corresponding contact trenches 31. As a result, the plurality of contact holes 42 form one emitter contact trench 31, 42 between themselves and the corresponding contact trenches 31.

[0061] The first direction width of each contact hole 42 may be equal to or greater than the first direction width of each contact trench 31. That is, the first direction width of each contact hole 42 may be equal to the first direction width of each contact trench 31, or may be greater than the first direction width of each contact trench 31. When the first direction width of each contact hole 42 exceeds the first direction width of each contact trench 31, the inner wall of each contact hole 42 may surround the inner wall of the corresponding contact trench 31.

[0062] The arrangement of the multiple contact holes 42 is arbitrary and is adjusted according to the arrangement of the contact trenches 31. The multiple contact holes 42 may be formed at equal intervals along the first direction X. The multiple contact holes 42 may be formed at unequal intervals along the first direction X.

[0063] An emitter principal surface electrode layer 43 is formed on the interlayer insulating layer 41. The emitter principal surface electrode layer 43 extends from above the interlayer insulating layer 41 into the contact hole 42 and the contact trench 31 (i.e., the emitter contact trenches 31, 42). The emitter principal surface electrode layer 43 may include, for example, a stacked structure of a barrier layer such as titanium and an electrode layer such as tungsten. In this embodiment, portions of the emitter principal surface electrode layer 43 located within the contact trenches 31 form multiple emitter contact electrode layers 51. This forms a structure in which multiple emitter contact electrode layers 51 are embedded in the surface portion of the chip 2.

[0064] The plurality of emitter contact electrode layers 51 each have an arrangement and a shape corresponding to the arrangement and shape of the plurality of contact trenches 31. That is, the plurality of emitter contact electrode layers 51 are formed at intervals along the first direction X and each have a strip shape extending along the second direction Y.

[0065] In a first intersection region 33 intersecting the gate electrode layer 14 in plan view, each emitter contact electrode layer 51 faces the gate electrode layer 14 across the gate-coating insulating layer 16 in the normal direction Z and the first direction X. Each emitter contact electrode layer 51 is insulated from the gate electrode layer 14 by the gate-coating insulating layer 16. The width of each emitter contact electrode layer 51 in the first direction is smaller than the width of the gate trench 12 in the first direction.

[0066] Each emitter contact electrode layer 51 is extended from an inner region of the corresponding gate-coating insulating layer 16 to the surface portion of the first main surface 3, penetrating the sidewalls of the gate trench 12. In this embodiment, each emitter contact electrode layer 51 penetrates from an inner region of the gate-coating insulating layer 16 to one sidewall and the other sidewall of the gate trench 12 in the second direction Y. The width in the first direction of each emitter contact electrode layer 51 is smaller than the width in the first direction of the corresponding gate-coating insulating layer 16.

[0067] In a second intersection region 34 that intersects with the emitter electrode layer 19 in a plan view, each emitter contact electrode layer 51 faces the emitter electrode layer 19 with the emitter-covering insulating layer 21 interposed therebetween in the normal direction Z and the first direction X. Each emitter contact electrode layer 51 is insulated from the emitter electrode layer 19 by the emitter-covering insulating layer 21. The width of each emitter contact electrode layer 51 in the first direction is smaller than the width of the emitter trench 17 in the first direction.

[0068] In the contact region 35 , each emitter contact electrode layer 51 is connected to the body region 8 (contact region 36 ) exposed from the bottom wall of the contact trench 31 , and is connected to the emitter region 25 exposed from the side wall of the contact trench 31 .

[0069] A collector electrode layer 61 is formed on the second main surface 4 of the chip 2. The collector electrode layer 61 is connected to the collector region 5. Although not shown, a gate main surface electrode layer having a structure similar to that of the emitter main surface electrode layer 43 may be formed on the interlayer insulating layer 41. The gate main surface electrode layer may be electrically connected to the gate electrode layer 14 via a gate contact hole formed in the interlayer insulating layer 41.

[0070] <<Description of Manufacturing Method of Semiconductor Device 1>> Figures 8A to 8N are diagrams showing an example of a manufacturing method of the semiconductor device 1. Figures 8A to 8N are cross-sectional perspective views of a portion corresponding to Figure 1.

[0071] Referring to FIG. 8A, first, n － A p-type chip 2 is prepared. Next, a p-type collector region 5 and an n-type charge accumulation region 6 are formed in the chip 2. The collector region 5 is formed by introducing p-type impurities into the second main surface 4 of the chip 2. The collector region 5 may be formed in the surface portion of the second main surface 4 of the chip 2 by ion implantation using an ion implantation mask (not shown).

[0072] The charge storage region 6 is formed by introducing n-type impurities into the first main surface 3. The charge storage region 6 may be formed in the surface portion of the first main surface 3 by ion implantation using an ion implantation mask (not shown).

[0073] 8B , a mask 71 having a predetermined pattern is formed on the first main surface 3. The mask 71 has a plurality of openings 72 that expose regions where the gate trenches 12 and the emitter trenches 17 are to be formed.

[0074] 8C , unnecessary portions of the chip 2 are removed from the first main surface 3. The unnecessary portions of the chip 2 may be removed by an etching method (e.g., wet etching) using a mask 71. This forms the gate trench 12 and the emitter trench 17. Thereafter, the mask 71 is removed.

[0075] 8D , a base insulating layer 73, which serves as a base for gate insulating layer 13 and emitter insulating layer 18, is formed to cover first main surface 3. Base insulating layer 73 may be formed by an oxidation treatment method for first main surface 3.

[0076] The oxidation treatment may be a thermal oxidation treatment or a wet oxidation treatment. The insulating base layer 73 may contain silicon oxide. The insulating base layer 73 may be formed by a chemical vapor deposition (CVD) method instead of the oxidation treatment.

[0077] 8E , a first base conductor layer 74, which serves as a base for gate electrode layer 14 and emitter electrode layer 19, is formed on first main surface 3. First base conductor layer 74 may be a conductive polysilicon layer. First base conductor layer 74 may be formed by a CVD method. The CVD method may be a low pressure CVD (LP-CVD) method.

[0078] Next, unnecessary portions of the first base conductor layer 74 are removed until at least the insulating base layer 73 is exposed. The unnecessary portions of the first base conductor layer 74 may be removed by an etching method (e.g., wet etching).

[0079] Unnecessary portions of the first base conductor layer 74 may be removed by etching (e.g., wet etching) after the main surface of the first base conductor layer 74 has been planarized by CMP (Chemical Mechanical Polishing).

[0080] 8F, a mask 75 having a predetermined pattern is formed on the first main surface 3. The mask 75 has a plurality of openings 76 that expose regions where the gate electrode recess 15 and the emitter electrode recess 20 are to be formed.

[0081] Next, unnecessary portions of the gate electrode layer 14 and the emitter electrode layer 19 are removed. The unnecessary portions of the gate electrode layer 14 and the emitter electrode layer 19 may be removed by etching (e.g., wet etching) using a mask 75. As a result, the gate electrode recess 15 and the emitter electrode recess 20 are formed.

[0082] 8G, the mask 75 is then removed. The gate electrode recess 15 and the emitter electrode recess 20 may be formed separately using different masks (not shown). That is, the gate electrode recess 15 and the emitter electrode recess 20 may have different depths.

[0083] 8H , a base insulating layer 77 that serves as a base for gate-coating insulating layer 16 and emitter-coating insulating layer 21 is formed on first main surface 3. Base insulating layer 77 may contain silicon oxide. Base insulating layer 77 may be formed by a CVD method. The CVD method may be an LP-CVD method.

[0084] 8I, unnecessary portions of base insulating layer 77 are removed. Unnecessary portions of base insulating layer 73 may be removed by etching (e.g., wet etching). As a result, gate-coating insulating layer 16 and emitter-coating insulating layer 21 are formed.

[0085] In this step, the portion of the base insulating layer 73 covering the first main surface 3 is also removed, thereby forming the gate insulating layer 13 and the emitter insulating layer 18. This also forms the trench gate electrode structure 10 and the trench emitter electrode structure 11.

[0086] Next, referring to FIG. 8J, a p-type body region 8 and an n-type ＋ A p-type emitter region 25 is formed in the first main surface 3. The body region 8 is formed by introducing a p-type impurity into the first main surface 3. The body region 8 may be formed in the surface portion of the first main surface 3 by ion implantation using an ion implantation mask (not shown).

[0087] The emitter region 25 is formed by introducing an n-type impurity into the first main surface 3. The emitter region 25 may be formed in the surface portion of the first main surface 3 by ion implantation using an ion implantation mask (not shown).

[0088] 8K , an interlayer insulating layer 41 is formed on first main surface 3. Interlayer insulating layer 41 is formed on first main surface 3 so as to cover trench gate electrode structure 10 and trench emitter electrode structure 11. This step may include the step of forming an NSG film (e.g., 5000 Å) and a PSG film (e.g., 4000 Å) in this order from above first main surface 3 by a CVD method.

[0089] 8L, a mask 78 having a predetermined pattern is formed on the interlayer insulating layer 41. The mask 78 has a plurality of openings 79 that expose regions where the contact trenches 31 and the contact holes 42 are to be formed.

[0090] 8M , unnecessary portions of interlayer insulating layer 41, unnecessary portions of gate-coating insulating layer 16, and unnecessary portions of emitter-coating insulating layer 21 are removed. The unnecessary portions of interlayer insulating layer 41, etc. may be removed by an etching method (e.g., dry etching) using a mask 78.

[0091] Furthermore, in this step, after unnecessary portions of the interlayer insulating layer 41 and the like are removed, unnecessary portions of the chip 2 are removed. The unnecessary portions of the chip 2 may be removed by an etching method (e.g., dry etching) using a mask 78.

[0092] As a result, contact trenches 31 are formed in the first main surface 3, and contact holes 42 communicating with the contact trenches 31 are formed in the interlayer insulating layer 41. Thereafter, the mask 78 is removed.

[0093] Next, the contact region 36 is formed in the surface portion of the first main surface 3. More specifically, the contact region 36 is formed in a region along the bottom wall of the contact trench 31 in the surface portion of the body region 8. The contact region 36 may also be formed in regions along the sidewall and bottom wall of the contact trench 31.

[0094] The contact region 36 is formed by introducing a p-type impurity into the contact trench 31. The contact region 36 may be introduced into the contact trench 31 by ion implantation through an ion implantation mask (not shown). This forms the contact region 36 along the bottom wall of the contact trench 31.

[0095] 8J, the contact region 36 may be formed by introducing a p-type impurity into the first main surface 3. In this case, the contact region 36 may be formed in the surface portion of the first main surface 3 by ion implantation using an ion implantation mask (not shown). This step also forms the contact region 36 along the bottom wall of the contact trench 31.

[0096] 8N, emitter main surface electrode layer 43 is formed on interlayer insulating layer 41. Then, an emitter contact electrode layer 51 is formed by a portion of emitter main surface electrode layer 43 that extends into contact trench 31. In addition, a collector electrode layer 61 is formed on second main surface 4 of chip 2. Through the steps including those described above, semiconductor device 1 is formed.

[0097] <Relationship Between Depth of Emitter Region 25 and Area of ​​Channel Formation Regions 102, 202> Fig. 9A is a diagram for explaining channel formation in semiconductor device 101 according to condition 1. Fig. 9B is a diagram for explaining the layout pattern of emitter region 25 and contact region 36 in semiconductor device 101 according to condition 1. Fig. 10A is a diagram for explaining channel formation in semiconductor device 201 according to condition 2. Fig. 10B is a diagram for explaining the layout pattern of emitter region 25 and contact region 36 in semiconductor device 201 according to condition 2. In semiconductor devices 101, 201, structures corresponding to those in semiconductor device 1 are assigned the same reference numerals, and descriptions thereof will be omitted.

[0098] 9A , the semiconductor device 101 has the same structure as the semiconductor device 1. The emitter region 25 is formed deeper than the upper surface of the gate electrode layer 14 in the gate electrode recess 15 (the bottom wall 22 of the gate electrode recess 15). That is, the bottom 50 of the emitter region 25 is located on the second main surface 4 side (opposite the first main surface 3) of the upper surface of the gate electrode layer 14 (the bottom wall 22 of the gate electrode recess 15) in the peripheral portion 9 on both sides of the first intersection region 33 in the first direction X. The depth D1 of the emitter region 25 from the first main surface 3 is greater than the depth D2 of the gate electrode recess 15 from the first main surface 3 (D1>D2). As a result, the emitter region 25 has an opposing portion 40 that faces the gate electrode layer 14 with the gate insulating layer 13 interposed therebetween below the peripheral portion 9 on both sides of the first intersection region 33 in the first direction X.

[0099] 9B , the width W1 of the emitter region 25 in the first direction X is, for example, 1.0 μm or less, and preferably 0.5 μm to 1.0 μm. The width W2 of the contact region 36 in the first direction X may be equal to or slightly wider than the width of the contact trench 31 in the first direction.

[0100] 10A , in the semiconductor device 201, the emitter region 25 is formed shallower than the upper surface of the gate electrode layer 14 in the gate electrode recess 15 (the bottom wall 22 of the gate electrode recess 15). That is, the bottom 50 of the emitter region 25 is located closer to the first main surface 3 than the upper surface of the gate electrode layer 14 (the bottom wall 22 of the gate electrode recess 15) in the peripheral portion 9 on both sides of the first intersection region 33 in the first direction X. The depth D1 of the emitter region 25 from the first main surface 3 is smaller than the depth D2 of the gate electrode recess 15 from the first main surface 3 (D1<D2). As a result, in the semiconductor device 201, the facing portion 40 shown in FIG. 9A does not exist, and the emitter region 25 does not face the gate electrode layer 14 below the peripheral portion 9 on both sides of the first intersection region 33 in the first direction X.

[0101] 10B , the width W3 of the emitter region 25 in the first direction X exceeds 1.0 μm, for example. The width W4 of the contact region 36 in the first direction X may be equal to or slightly wider than the width of the contact trench 31 in the first direction.

[0102] 9A and 10A, the first-direction width W5 of the gate electrode recess 15 is set wider than the first-direction width W6 of the contact trench 31. This is to ensure a margin in consideration of misalignment during patterning of the mask 78 for forming the contact trench 31 (see FIGS. 8L and 8M). By ensuring this margin, the emitter contact electrode layer 51 fits within the gate-coating insulating layer 16, and the emitter contact electrode layer 51 is reliably insulated from the gate electrode layer 14 by the gate-coating insulating layer 16. This prevents a short circuit between the emitter and the gate. In other words, the recess width of the gate electrode layer 14 (the width W5 of the gate electrode recess 15) needs to be wider than the contact dimension of the emitter contact electrode layer 51 (the width W6 of the contact trench 31).

[0103] Therefore, as in the semiconductor device 201 shown in FIG. 10A , if the depth D1 of the emitter region 25 is smaller than the depth D2 of the gate electrode recess 15 (D1<D2), the region below the peripheral portion 9 is a region where the emitter region 25 does not exist. Although a channel CH can be formed in this region, a main current path cannot be formed. Therefore, in the semiconductor device 201, the region of the body region 8 excluding the region below the gate electrode recess 15 is a region where a main current path can be formed within the channel formation region 202 where a channel CH can be formed, while the region below the gate electrode recess 15 is a region where a main current path is difficult to form. As a result, the channel width tends to shrink and the on-resistance tends to increase. In FIG. 10A , the channel formation region 202 is indicated by hatching including solid and dashed lines.

[0104] 10B , there is a constraint that the width W3 of the emitter region 25 must be designed to be relatively wide in consideration of the etching margin, because if the width W3 of the emitter region 25 is too narrow, the portion of the emitter region 25 facing the gate electrode layer 14 will be significantly reduced after the gate electrode recess 15 is formed.

[0105] In contrast, when the depth D1 of the emitter region 25 is greater than the depth D2 of the gate electrode recess 15 (D1>D2), as in the semiconductor device 101 of FIG. 9A , the emitter region 25 is also present in the region below the peripheral portion 9, and a main current path can be formed in this region. Therefore, in the semiconductor device 101, the entire region of the body region 8 in the first direction X, including the region below the gate electrode recess 15, is the channel formation region 102 in which a main current path can be formed. As a result, the channel width can be made larger than in the semiconductor device 201, and the on-resistance can be reduced. In FIG. 9A , the channel formation region 102 is indicated by hatching including solid and dashed lines.

[0106] Furthermore, when designing the width W1 of the emitter region 25, it is no longer necessary to consider the etching margin and the pattern of the gate electrode recess 15. This is because, even after the gate electrode recess 15 is formed, the opposing portion 40 of the emitter region 24 can be secured below the peripheral portion 9, thereby securing the channel formation region 102 having a sufficient channel width. Therefore, the width W1 of the emitter region 25 can be made narrower than the width W3 of the emitter region 25 of the semiconductor device 201.

[0107] <Relationship Between Depth of Emitter Region 25 and Characteristics of Semiconductor Devices 101 and 201> Next, the relationship between the depth of the emitter region 25 and the characteristics of the semiconductor devices 101 and 201 will be described with reference to FIGS.

[0108] 11 is a graph showing the short-circuit waveforms of the semiconductor device 101 under condition 1 and the semiconductor device 201 under condition 2, which were obtained by simulation. In FIG. 11, the vertical axis on the left represents the collector current IC [A], the vertical axis on the right represents the collector-emitter voltage VCE [V], and the horizontal axis represents time [s]. In FIG. 11, the gate voltages under conditions 1 and 2 are shown by dashed lines, the collector voltages under conditions 1 and 2 are shown by solid lines, and the collector currents under conditions 1 and 2 are shown by dashed lines.

[0109] With reference to the gate voltage, collector voltage, and collector current under condition 1, it was confirmed that in semiconductor device 101, the steady-state values ​​were not exceeded from the rise of the short-circuit wave, and latch-up behavior did not occur even with the passage of time. On the other hand, with reference to the gate voltage, collector voltage, and collector current under condition 2, it was confirmed that the collector current overshoots and greatly exceeds the steady-state value shown under condition 1, resulting in latch-up behavior.

[0110] As described above, it has been found that the semiconductor device 101 can improve the breakdown voltage by providing the emitter region 25 having a width W1 narrower than the width W3 of the emitter region 25 of the semiconductor device 201.

[0111] Fig. 12 is a graph showing the current-voltage characteristics of the semiconductor device 101 according to condition 1 and the semiconductor device 201 according to condition 2, which were obtained by simulation. Fig. 13 is a diagram showing an enlarged portion of the graph in Fig. 12. In Figs. 12 and 13, the vertical axis represents the collector current IC [A], and the horizontal axis represents the collector-emitter voltage VCE [V]. Fig. 13 shows a graph of the collector-emitter voltage VCE of Fig. 12 in the range of 0 to 2 V.

[0112] 12, the characteristics of the semiconductor device 101 under condition 1 are shown by a solid line graph, and the characteristics of the semiconductor device 201 under condition 2 are shown by a dashed line graph. For both condition 1 and condition 2, the current-voltage characteristics are shown when the collector-emitter voltage VCE is changed from 0 V to 10 V.

[0113] With reference to the characteristics under condition 1, in the semiconductor device 101, the collector-emitter voltages VCE were 1.26 V, 1.60 V, 1.91 V, 2.25 V, and 2.66 V when the collector current IC was 20 A, 40 A, 60 A, 80 A, and 100 A. On the other hand, with reference to the characteristics under condition 2, in the semiconductor device 201, the collector-emitter voltages VCE were 1.28 V, 1.65 V, 2.01 V, 2.42 V, and 3.20 V when the collector current IC was 20 A, 40 A, 60 A, 80 A, and 100 A, respectively.

[0114] As described above, it has been found that the semiconductor device 101 can reduce the collector-emitter voltage VCE required for start-up compared to the semiconductor device 201, and therefore can reduce on-loss.

[0115] 14 is a graph showing the current-voltage characteristics of the semiconductor device 101 under condition 1 and the semiconductor device 201 under condition 2, obtained by simulation. In FIG. 14, the vertical axis represents the collector current IC [A], and the horizontal axis represents the gate-emitter voltage VGE [V]. In FIG. 14, the characteristics of the semiconductor device 101 under condition 1 are shown by a solid line graph, and the characteristics of the semiconductor device 201 under condition 2 are shown by a dashed line graph. For both condition 1 and condition 2, the graph shows the current-voltage characteristics when the gate-emitter voltage VGE is changed from 0 V to 15 V.

[0116] <<Description of Structure of Semiconductor Device 81 (Second Embodiment)>> Fig. 15 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 81 according to a second embodiment of the present disclosure. Fig. 16 is a schematic cross-sectional view showing a portion of the semiconductor device 81 of Fig. 15. Fig. 17 is a schematic cross-sectional view showing a portion of the semiconductor device 81 of Fig. 15. In the following, structures corresponding to those described with respect to the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0117] In the semiconductor device 1 described above, an example was described in which the gate electrode layer 14 has an uneven structure including a plurality of gate electrode recesses 15. In contrast, in the semiconductor device 81, the gate electrode layer 14 has a flat structure formed by a constant depth position of the upper surface 82 throughout. More specifically, with reference to FIGS. 16 and 17 , the upper surface 82 of the gate electrode layer 14 is located in a region between the first main surface 3 and the bottom portion 50 of the emitter region 25 with respect to the normal direction Z. As a result, similar to the semiconductor device 1, the emitter region 25 has an opposing portion 40 that faces the gate electrode layer 14 with the gate insulating layer 13 interposed therebetween in the vicinity of the first intersection region 33 in the first direction X.

[0118] 16 , the gate-coating insulating layer 16 has an integral structure extending across the plurality of contact trenches 31 in the first direction X. The gate-coating insulating layer 16 has an insulating layer uneven structure formed by insulating layer recesses 83 formed in the first intersection regions 33 of each contact trench 31. The emitter contact electrode layer 51 is embedded in the insulating layer recesses 83. More specifically, the gate-coating insulating layer 16 may include a base portion 85 having a flat lower surface 84 in contact with the upper surface 82 of the gate electrode layer 14 in the first direction X, and protruding portions 86 protruding from the base portion 85 between adjacent insulating layer recesses 83. The uneven structure of the gate-coating insulating layer 16 is formed by alternately arranging the protruding portions 86 and the insulating layer recesses 83 in the first direction X.

[0119] As described above, the semiconductor device 81 can also achieve the same effects as those described for the semiconductor device 1. In other words, the entire region of the body region 8 in the first direction X can be used as the channel formation region 102 in which the channel CH can be formed. The semiconductor device 81 can be manufactured by digging down almost the entire main surface of the first base conductor layer 74 without patterning the first base conductor layer 74 when etching the first base conductor layer 74 (see FIG. 8F ) in the manufacturing method of the semiconductor device 1.

[0120] 18 is a schematic cross-sectional perspective view showing a partial region of a semiconductor device 91 according to a third embodiment of the present disclosure. In the following, structures corresponding to those described with respect to the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0121] In the above-described semiconductor device 1, an example has been described in which a p-type collector region 5 is formed in the surface portion of the second main surface 4. In contrast, in the semiconductor device 91, an n-type drain region 92 is formed in the surface portion of the second main surface 4 instead of the p-type collector region 5. As a result, the semiconductor device 91 has a basic configuration including a trench gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor). The above-described description of the semiconductor device 1 applies mutatis mutandis to the description of the semiconductor device 91, with "emitter" replaced with "source" and "collector" replaced with "drain."

[0122] As described above, the semiconductor device 91 can also achieve the same effects as those described for the semiconductor device 1. The semiconductor device 91 can be manufactured by the manufacturing method of the semiconductor device 1, by simply forming an n-type drain region 92 instead of the p-type collector region 5 and changing the layout of each mask.

[0123] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0124] For example, in each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0125] In the above-described embodiments, the chip 2 is made of single crystal silicon. However, the chip 2 may contain SiC. Alternatively, the chip 2 may be made of single crystal SiC.

[0126] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0127] The following characteristics can be extracted from the description of this specification and the drawings.

[0128] [Supplementary Note 1-1] A chip (2) having a first main surface (3) in which a gate trench (12) extending in a first direction (X) is formed, the gate trench (12) having a bottom wall and a sidewall; a body region (8) of a first conductivity type formed along the sidewall of the gate trench (12) in a surface portion of the first main surface (3); a first impurity region (25) of a second conductivity type formed along the sidewall of the gate trench (12) in a surface portion of the body region (8); a gate insulating layer (13) formed on the bottom wall and the sidewall of the gate trench (12); and a gate electrode (14) embedded in the gate trench (12) and facing the body region (8) and the first impurity region (25) across the gate insulating layer (13); a contact trench (31) including an intersection region (33) intersecting the gate trench (12) and extending from the intersection region (33) to the outside of the gate trench (12) along a second direction (Y) intersecting the first direction (X); and a contact electrode (51) embedded in the contact trench (31) and electrically connected to the body region (8) and the first impurity region (25) inside the contact trench (31), wherein a space region (15) is formed on the gate electrode (14) at least in the intersection region (33) and a peripheral portion (9) of the intersection region (33) in the gate trench (12), and a covering insulating layer (16) is embedded in the space region (15) to cover an upper surface (22) of the gate electrode (14) in the intersection region (33) and the peripheral portion (9) of the intersection region (33) and to provide insulation between the gate electrode (14) and the contact electrode (51), The semiconductor device (1, 81, 91, 101) comprises a first impurity region (25) formed deeper than an upper surface (22) of the gate electrode (14) in a peripheral portion (9) of the intersection region (33).

[0129] [Appendix 1-2] The semiconductor device (1, 81, 91, 101) according to Appendix 1-1, wherein the first impurity region (25) has an opposing portion (40) opposing the gate electrode (14) below the peripheral portion (9) of the intersection region (33).

[0130] [Appendix 1-3] The semiconductor device (1, 81, 91, 101) according to Appendix 1-1 or Appendix 1-2, wherein the contact electrode (51) is connected to the body region (8) at a bottom wall of the contact trench (31) and is connected to the first impurity region (25) at a side wall of the contact trench (31).

[0131] [Supplementary Note 1-4] The semiconductor device (1, 81, 91, 101) according to any one of Supplementary Note 1-1 to Supplementary Note 1-3, wherein the width (W1) of the first impurity region (25) in the first direction (X) is 1.0 μm or less.

[0132] [Appendix 1-5] The semiconductor device (1, 81, 91, 101) according to appendix 1-4, wherein the width (W1) of the first impurity region (25) is not less than 0.5 μm and not more than 1.0 μm.

[0133] [Supplementary Note 1-6] The semiconductor device (1, 81, 91, 101) according to any one of Supplementary Note 1-1 to Supplementary Note 1-5, wherein the peripheral portion (9) of the intersection region (33) includes a region ranging from 0.05 μm to 0.5 μm from the intersection region (33).

[0134] [Appendix 1-7] The semiconductor device (1, 91, 101) according to any one of Appendices 1-1 to 1-6, including a plurality of the contact trenches (31) formed at intervals along the first direction (X), the gate electrode (14) having an electrode unevenness structure formed by gate electrode recesses (15) formed in the intersection regions (33) of the contact trenches (31) and in peripheral portions (9) of the intersection regions (33) along the first direction (X), and the covering insulating layer (16) being embedded in the gate electrode recesses (15).

[0135] [Appendix 1-8] The semiconductor device (1, 91, 101) according to Appendix 1-7, wherein the covering insulating layer (16) is independently embedded in each of the gate electrode recesses (15), and a portion of the upper surface (23) of the gate electrode (14) is exposed between adjacent contact trenches (31).

[0136] [Supplementary Note 1-9] The semiconductor device (1, 91, 101) according to Supplementary Note 1-7 or Supplementary Note 1-8, wherein the gate electrode recess (15) is formed across a peripheral portion (9) on one side of the intersection region (33) in the first direction (X) and a peripheral portion (9) on the other side thereof, and the covering insulating layer (16) has a first portion (47) arranged in the intersection region (33) and second portions (48) arranged in the peripheral portion (9) on one side of the first direction (X) and the peripheral portion (9) on the other side thereof relative to the first portion (47).

[0137] [Appendix 1-10] The semiconductor device (1, 91, 101) according to any one of Appendices 1-7 to 1-9, wherein a width (W6) of the contact trench (31) in the first direction (X) is 0.3 μm or more and 1.0 μm or less, and sidewalls of the gate electrode recess (15) are formed on both sides of the contact trench (31) in the first direction (X) at intervals of 0.05 μm or more and 0.5 μm or less.

[0138] [Appendix 1-11] The semiconductor device (81) according to any one of Appendices 1-1 to 1-6, including a plurality of the contact trenches (31) formed at intervals along the first direction (X), and the gate electrode (14) has a flat structure formed by a depth position of the upper surface (82) being constant throughout.

[0139] [Appendix 1-12] The semiconductor device (81) according to Appendix 1-11, wherein the covering insulating layer (16) has an integral structure extending across the plurality of contact trenches (31) along the first direction (X), and has an insulating layer uneven structure formed by insulating layer recesses (83) formed in the intersection regions (33) of each of the contact trenches (31), and the contact electrodes (51) are embedded in the insulating layer recesses (83).

[0140] [Appendix 1-13] The semiconductor device (81) according to Appendix 1-12, wherein the covering insulating layer (16) includes a base portion (85) having a flat lower surface (84) in contact with the upper surface (82) of the gate electrode (14) along the first direction (X), and convex portions (86) protruding from the base portion (85) between adjacent insulating layer concave portions (83), and the convex portions (86) and the insulating layer concave portions (83) are alternately arranged along the first direction (X), thereby forming the insulating layer concave-convex structure.

[0141] [Appendix 1-14] The semiconductor device (1, 81, 101) according to any one of Appendices 1-1 to 1-13, wherein the first impurity region (25) includes an emitter region (25), and the contact electrode (51) includes an emitter contact electrode (51).

[0142] [Appendix 1-15] The semiconductor device (91) according to any one of Appendices 1-1 to 1-13, wherein the first impurity region (25) includes a source region (25), and the contact electrode (51) includes a source contact electrode (51).

[0143] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5: Collector region 6: Charge storage region 7: Drift region 8: Body region 9: Peripheral portion 10: Trench gate electrode structure 11: Trench emitter electrode structure 12: Gate trench 13: Gate insulating layer 14: Gate electrode layer 15: Gate electrode recess 16: Gate coating insulating layer 17: Emitter trench 18: Emitter insulating layer 19: Emitter electrode layer 20: Emitter electrode recess 21: Emitter coating insulating layer 22: Bottom wall 23: Upper surface 24: Emitter region 25: Emitter region 31: Contact trench 32: Lead-out portion 33: First intersection region 34: Second intersection region 35: Contact region 36 : Contact region 40 : Opposing portion 41 : Interlayer insulating layer 42 : Contact hole 43 : Emitter main surface electrode layer 47 : First portion 48 : Second portion 49 : Body region convex portion 50 : Bottom portion 51 : Emitter contact electrode layer 61 : Collector electrode layer 71 : Mask 72 : Opening 73 : Base insulating layer 74 : First base conductor layer 75 : Mask 76 : Opening 77 : Base insulating layer 78 : Mask 79 : Opening 81 : Semiconductor device 82 : Upper surface 83 : Insulating layer concave portion 84 : Lower surface 85 : Base portion 86 : Convex portion 91 : Semiconductor device 92 : Drain region 101 : Semiconductor device 102 : Channel formation region 201 : Semiconductor device 202 : Channel formation region CH : Channel D1: Depth D2: Depth P0: Trench pitch W1: Width W2: Width W3: Width W4: Width W5: Width W6: Width X: First direction Y: Second direction Z: Normal direction θ: Angle

Claims

1. a chip having a first main surface with a gate trench formed therein, the gate trench having a bottom wall and a sidewall and extending in a first direction; a body region of a first conductivity type formed along the sidewall of the gate trench in a surface portion of the first main surface; a first impurity region of a second conductivity type formed along the sidewall of the gate trench in a surface portion of the body region; a gate insulating layer formed on the bottom wall and the side wall of the gate trench; a gate electrode embedded in the gate trench and facing the body region and the first impurity region with the gate insulating layer interposed therebetween; a contact trench including an intersection region intersecting with the gate trench, the contact trench being extended from the intersection region to an outside of the gate trench along a second direction intersecting with the first direction; a contact electrode embedded in the contact trench and electrically connected to the body region and the first impurity region inside the contact trench; a space region is formed on the gate electrode at least in the intersection region and a periphery of the intersection region in the gate trench, a covering insulating layer is embedded in the space region, the covering insulating layer covering an upper surface of the gate electrode in the intersection region and a periphery of the intersection region and providing insulation between the gate electrode and the contact electrode; the first impurity region is formed deeper than an upper surface of the gate electrode in a peripheral portion of the intersection region.

2. 2. The semiconductor device according to claim 1, wherein said first impurity region has an opposing portion facing said gate electrode below a periphery of said intersection region.

3. 3. The semiconductor device according to claim 2, wherein the contact electrode is connected to the body region at a bottom wall of the contact trench and is connected to the first impurity region at a side wall of the contact trench.

4. 4. The semiconductor device according to claim 3, wherein the width of said first impurity region in said first direction is 1.0 [mu]m or less.

5. 5. The semiconductor device according to claim 4, wherein the first impurity region has a width of not less than 0.5 [mu]m and not more than 1.0 [mu]m.

6. 6. The semiconductor device according to claim 1, wherein the periphery of the intersection region includes a region within a range of 0.05 μm to 0.5 μm from the intersection region.

7. The contact trenches are formed at intervals along the first direction, the gate electrode has an electrode unevenness structure formed by gate electrode recesses formed in the intersection regions of the contact trenches and in peripheral portions of the intersection regions along the first direction; 6. The semiconductor device according to claim 1, wherein the covering insulating layer is embedded in the gate electrode recess.

8. the covering insulating layer is embedded in each of the gate electrode recesses independently, The semiconductor device according to claim 7 , wherein a part of an upper surface of said gate electrode is exposed between adjacent ones of said contact trenches.

9. the gate electrode recess is formed across one side peripheral portion and the other side peripheral portion of the intersection region in the first direction, 8. The semiconductor device according to claim 7, wherein the covering insulating layer has a first portion arranged in the intersection region and a second portion arranged in each of a peripheral portion on one side and a peripheral portion on the other side of the first portion in the first direction.

10. The width of the contact trench in the first direction is not less than 0.3 μm and not more than 1.0 μm, 6. The semiconductor device according to claim 7, wherein the sidewalls of the gate electrode recess are formed on both sides of the contact trench in the first direction with an interval of 0.05 μm or more and 0.5 μm or less.

11. The contact trenches are formed at intervals along the first direction, 6. The semiconductor device according to claim 1, wherein said gate electrode has a flat structure formed by keeping the depth position of said upper surface constant over the entire gate electrode.

12. the covering insulating layer has an integral structure extending across the contact trenches along the first direction, and has an insulating layer uneven structure formed by insulating layer recesses formed in the intersection regions of the contact trenches; The semiconductor device according to claim 11 , wherein the contact electrode is embedded in the insulating layer recess.

13. the covering insulating layer includes a base portion having a flat lower surface in contact with the upper surface of the gate electrode along the first direction, and a convex portion protruding from the base portion between adjacent insulating layer concave portions, The semiconductor device according to claim 12 , wherein the insulating layer uneven structure is formed by alternately arranging the protrusions and the insulating layer recesses along the first direction.

14. the first impurity region includes an emitter region, 6. The semiconductor device according to claim 1, wherein the contact electrode includes an emitter contact electrode.

15. the first impurity region includes a source region, 6. The semiconductor device according to claim 1, wherein the contact electrode includes a source contact electrode.