Semiconductor device

Abstract

This semiconductor device comprises: a chip having a first main surface on one side and a second main surface on the other side; a first terminal that is disposed on the first main surface; a second terminal that is disposed on the second main surface; and a protection circuit that includes a protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the second terminal, and that forms a discharge path for overvoltage generated between the first terminal and the second terminal. The protection transistor includes a plurality of trench gate structures each having an upper electrode and a lower electrode buried in the vertical direction sandwiching an insulator inside a trench formed in the first main surface.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2022-142473 filed with the Japan Patent Office on September 7, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] US Pat. No. 6,274,908 (Patent Document 1) discloses a protection circuit with a lateral field effect transistor as a discharge path.

[0003] U.S. Patent No. 6,274,908

[0004] SUMMARY The present disclosure provides overvoltage protection through a novel layout.

[0005] The present disclosure provides a semiconductor device including: a chip having a main surface; an output region provided on the main surface; a protection region provided on the main surface; an output transistor having a plurality of first trench gate structures formed on the main surface at a first interval in the output region; and a protection transistor including a plurality of second trench gate structures formed on the main surface at a second interval in the protection region that is larger than the first interval, and forming a discharge path for an overvoltage.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; an output region provided on the main surface; a protection region provided on the main surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; a high-concentration drift region of the first conductivity type formed in the surface layer portion of the drift region in the output region and having a higher impurity concentration than the drift region; an output transistor having a first trench gate structure formed on the main surface to be located within the high-concentration drift region in the output region; and a protection circuit having a protection transistor including a second trench gate structure formed on the main surface to be located within the drift region in the protection region, and forming a discharge path for overvoltage.

[0007] The present disclosure provides a semiconductor device including: a chip having a first main surface on one side and a second main surface on the other side; a first terminal arranged on the first main surface; a second terminal arranged on the second main surface; and a protection circuit including a protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the second terminal, and forming a discharge path for an overvoltage generated between the first terminal and the second terminal, wherein the protection transistor includes a plurality of trench gate structures each having an upper electrode and a lower electrode vertically embedded in a trench formed in the first main surface with an insulator sandwiched therebetween.

[0008] The present disclosure provides a chip having a first main surface on one side and a second main surface on the other side, a first terminal disposed on the first main surface, a second terminal disposed on the first main surface, a third terminal disposed on the second main surface, a first protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the third terminal, and a first protection circuit forming a discharge path for an overvoltage occurring between the first terminal and the third terminal, and a second protection transistor formed on the first main surface so as to be electrically interposed between the second terminal and the third terminal. and a second protection circuit forming a discharge path for an overvoltage occurring between the second terminal and the third terminal, wherein the first protection transistor includes a plurality of first trench gate structures each having a first upper electrode and a first lower electrode vertically embedded in a first trench formed in the first main surface with a first insulator sandwiched therebetween, and the second protection transistor includes a plurality of second trench gate structures each having a second upper electrode and a second lower electrode vertically embedded in a second trench formed in the first main surface with a second insulator sandwiched therebetween.

[0009] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device shown in FIG. 1. FIG. 4 is a schematic circuit diagram showing the configuration of an output transistor. FIG. 5 is a circuit diagram showing the first overvoltage protection circuit shown in FIG. 3. FIG. 6 is a circuit diagram showing the second overvoltage protection circuit shown in FIG. 3. FIG. 7 is a plan view showing the output region shown in FIG. 1. FIG. 8 is an enlarged plan view showing a main portion of the output region shown in FIG. 7. FIG. 9 is an enlarged plan view showing further main portions of the output region shown in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 8. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 8. FIG. 15 is a plan view showing the first protection region shown in FIG. 1. FIG. 16 is an enlarged plan view showing a main portion of the first protection region shown in FIG. 15 . FIG. 17 is an enlarged plan view showing a further main portion of the first protection region shown in FIG. 15 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 16 . FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 16 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 16 . FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 16 . FIG. 22 is a cross-sectional view comparing the output region and the first protection region. FIG. 23 is a first graph showing the results of a TLP test. FIG. 24 is a second graph showing the results of a TLP test. FIG. 25 is a graph showing the test results of the gate threshold voltage. FIG. 26 is a plan view showing a first modified example of the first protection region. FIG. 27 is a cross-sectional view showing a second modified example of the first protection region.

[0011] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0012] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0013] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. With reference to Fig. 1 and Fig. 2, the semiconductor device 1 includes a chip 2 formed in a rectangular parallelepiped shape. In this embodiment, the chip 2 is a Si chip including a Si single crystal.

[0014] Of course, the chip 2 may be a wide bandgap semiconductor chip including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). For example, the chip 2 may be a SiC chip including a single crystal of SiC.

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2.

[0016] The first main surface 3 is a circuit surface on which various circuit structures constituting an electronic circuit are formed. The second main surface 4 is a non-circuit surface that does not have any circuit structures. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face (back to back) in a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face (back to back) in the first direction X.

[0017] The semiconductor device 1 includes an output region 6 provided on the first main surface 3. The output region 6 is a region having an electronic circuit (circuit device) configured to generate an output signal to be output to the outside. In this embodiment, the output region 6 is defined in a region on the first side surface 5A side of the first main surface 3. In a plan view, the output region 6 is defined in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0018] The position, size, planar shape, etc. of the output area 6 are arbitrary and are not limited to a specific layout. The output area 6 may have a planar area of ​​25% to 80% of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 30% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 40% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 50% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output area 6 may be 75% or less of the planar area of ​​the first main surface 3.

[0019] The semiconductor device 1 includes a control region 7 provided in a region on the first main surface 3 that is different from the output region 6. The control region 7 is a region having a plurality of types of electronic circuits (circuit devices) configured to generate control signals that control the output region 6. In this embodiment, the control region 7 is defined in a region on the second side surface 5B side of the output region 6, and faces the output region 6 in the second direction Y. In this embodiment, the control region 7 is defined in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0020] The position, size, planar shape, etc. of the control region 7 are arbitrary and are not limited to a specific layout. The control region 7 may have a planar area of ​​25% to 80% of the planar area of ​​the first main surface 3. The planar area of ​​the control region 7 may be 30% or more of the planar area of ​​the first main surface 3. The planar area of ​​the control region 7 may be 40% or more of the planar area of ​​the first main surface 3. The planar area of ​​the control region 7 may be 50% or more of the planar area of ​​the first main surface 3. The planar area of ​​the control region 7 may be 75% or less of the planar area of ​​the first main surface 3.

[0021] The planar area of ​​the control area 7 may be approximately equal to the planar area of ​​the output area 6. The planar area of ​​the control area 7 may be larger than the planar area of ​​the output area 6. The planar area of ​​the control area 7 may be smaller than the planar area of ​​the output area 6. The ratio of the planar area of ​​the control area 7 to the planar area of ​​the output area 6 may be 0.1 or more and 4 or less.

[0022] The semiconductor device 1 includes a first protection region 8 provided in a region on the first main surface 3 that is different from the output region 6. The first protection region 8 is a region having an electronic circuit (circuit device) configured to protect the protected region from an external overvoltage.

[0023] For example, the overvoltage may be a surge voltage caused by static electricity or the like. The first protection region 8 also protects the protected region from damage caused by ESD (Electro Static Discharge). The first protection region 8 may be referred to as a "first ESD protection region." The protected region includes the output region 6 and the control region 7.

[0024] The position, size, planar shape, etc. of the first protection area 8 are arbitrary and are not limited to a specific layout. The first protection area 8 preferably has a planar area smaller than the planar area of ​​the output area 6. In this form, the first protection area 8 has a planar area smaller than the planar area of ​​the control area 7 and is incorporated within the control area 7. The first protection area 8 may be considered as one component of the control area 7. In this form, the first protection area 8 is arranged inside the control area 7.

[0025] The planar area of ​​the first protection area 8 is preferably 1 / 10 or less of the planar area of ​​the output area 6. It is particularly preferable that the planar area of ​​the first protection area 8 is 1 / 25 or less of the planar area of ​​the output area 6. The planar area of ​​the first protection area 8 may be 1 / 50 or less of the planar area of ​​the output area 6. The planar area of ​​the first protection area 8 may be 1 / 100 or less of the planar area of ​​the output area 6.

[0026] The semiconductor device 1 includes a second protection region 9 provided in a region on the first main surface 3 that is different from the output region 6. The second protection region 9 is a region having an electronic circuit (circuit device) configured to protect the protected region from an external overvoltage.

[0027] For example, the overvoltage may be a surge voltage caused by static electricity or the like. The second protection region 9 also protects the protected region from destruction caused by ESD. The second protection region 9 may be referred to as a "second ESD protection region." The protected region includes the output region 6 and the control region 7.

[0028] The position, size, and planar shape of the second protection area 9 are arbitrary and are not limited to a specific layout. It is preferable that the second protection area 9 has a planar area smaller than the planar area of ​​the output area 6.

[0029] In this embodiment, the second protective region 9 has a planar area smaller than the planar area of ​​the control region 7, and is incorporated into a region of the control region 7 that is different from the first protective region 8. The second protective region 9 may be considered to be one component of the control region 7. In this embodiment, the second protective region 9 is arranged on the periphery of the control region 7. Specifically, the second protective region 9 is arranged closer to the periphery of the first main surface 3 than the first protective region 8.

[0030] The planar area of ​​the second protection area 9 is preferably 1 / 10 or less of the planar area of ​​the output area 6. It is particularly preferable that the planar area of ​​the second protection area 9 is 1 / 25 or less of the planar area of ​​the output area 6. The planar area of ​​the second protection area 9 may be 1 / 50 or less of the planar area of ​​the output area 6. The planar area of ​​the second protection area 9 may be 1 / 100 or less of the planar area of ​​the output area 6.

[0031] In this embodiment, the plane area of ​​the second protection area 9 is larger than the plane area of ​​the first protection area 8. Of course, the plane area of ​​the second protection area 9 may be approximately equal to the plane area of ​​the first protection area 8. Alternatively, the plane area of ​​the second protection area 9 may be smaller than the plane area of ​​the first protection area 8.

[0032] The semiconductor device 1 includes an n-type (first conductivity type) drain region 10 formed in a surface layer portion of the second main surface 4. The n-type impurity concentration of the drain region 10 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３The drain region 10 is formed in a layer shape extending along the second main surface 4 over the entire surface portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0033] The drain region 10 may have a thickness of 50 μm or more and 200 μm or less. The thickness of the drain region 10 is preferably 150 μm or less. In this embodiment, the drain region 10 is formed of an n-type semiconductor substrate (Si substrate).

[0034] The semiconductor device 1 includes an n-type drift region 11 formed in a surface layer portion of the first main surface 3. The drift region 11 has a lower n-type impurity concentration than the drain region 10. The n-type impurity concentration of the drift region 11 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0035] Drift region 11 is formed in a layer extending along first main surface 3 in output region 6, control region 7, first protection region 8, and second protection region 9. Specifically, drift region 11 is formed in a layer extending along first main surface 3 over the entire surface layer portion of first main surface 3, and is exposed from first main surface 3 and first to fourth side surfaces 5A to 5D.

[0036] The drift region 11 is electrically connected to the drain region 10 within the chip 2. The drift region 11 has a thickness less than that of the drain region 10. The thickness of the drift region 11 may be 1 μm or more and 20 μm or less. The thickness of the drift region 11 is preferably 5 μm or more and 15 μm or less. The thickness of the drift region 11 is particularly preferably 10 μm or less. In this embodiment, the drift region 11 is formed by an n-type epitaxial layer (Si epitaxial layer).

[0037] The semiconductor device 1 includes an interlayer insulating layer 12 covering the first main surface 3. The interlayer insulating layer 12 collectively covers the output region 6, the control region 7, the first protective region 8, and the second protective region 9. The interlayer insulating layer 12 may cover the entire first main surface 3 so as to be continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Of course, the interlayer insulating layer 12 may be formed at a distance inward from the periphery of the first main surface 3 so as to expose the periphery of the first main surface 3.

[0038] In this embodiment, the interlayer insulating layer 12 has a multilayer wiring structure in which multiple insulating layers and multiple wiring layers are alternately stacked. Each insulating layer may include at least one of a silicon oxide film and a silicon nitride film. Each wiring layer may include at least one of a pure Al layer (an Al layer with a purity of 99% or more), a Cu layer (a Cu layer with a purity of 99% or more), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0039] The semiconductor device 1 includes a plurality of terminals 13 to 15 arranged on either or both (in this embodiment, both) of the first main surface 3 and the second main surface 4. The plurality of terminals 13 to 15 includes a source terminal 13, a plurality of control terminals 14, and a drain terminal 15.

[0040] In this embodiment, source terminal 13 is provided as an output terminal electrically connected to a load, and is disposed on a portion of interlayer insulating layer 12 that covers output region 6. Source terminal 13 may cover the entire output region 6 in a plan view. Source terminal 13 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0041] The plurality of control terminals 14 are terminals electrically connected to various electronic circuits in the control region 7, and are arranged on a portion of the interlayer insulating layer 12 that covers the control region 7. The plurality of control terminals 14 each have a planar area smaller than the planar area of ​​the source terminal 13, and are arranged at intervals along the periphery of the control region 7 (the periphery of the first main surface 3).

[0042] The planar area of ​​each control terminal 14 is set within a range that allows connection of a bonding wire. The planar area of ​​each control terminal 14 may be 1 / 10 or less of the planar area of ​​the source terminal 13. The plurality of control terminals 14 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0043] The plurality of control terminals 14 include at least one ground terminal 14a fixed to a ground potential and at least one input terminal 14b that applies an electrical signal to the control region 7. The ground terminal 14a may be arranged in any location. In a plan view, the ground terminal 14a may be arranged inside the control region 7, along one side of the first main surface 3, or at a corner of the first main surface 3. The ground terminal 14a is connected to a bonding wire, and a ground potential is applied to the ground terminal 14a from the outside via the bonding wire.

[0044] The input terminal 14b may be disposed at any location. In plan view, the input terminal 14b may be disposed inside the control region 7, along one side of the first main surface 3, or at a corner of the first main surface 3. In this embodiment, the input terminal 14b is disposed adjacent to the second protection region 9 in plan view. Of course, the input terminal 14b may cover the second protection region 9.

[0045] In this embodiment, an example is shown in which the input terminal 14b is a test terminal to which a test signal for testing the electrical characteristics of the control circuit 23 during the manufacturing process is input. The test terminal is provided as a contact target for a probe of an electrical characteristic test device, and is configured to receive a test signal from the probe.

[0046] The input terminal 14b is a structure that is not to be connected with a bonding wire in the manufactured semiconductor device 1. In other words, the input terminal 14b is formed as an open terminal (dummy terminal). An open terminal is a terminal that does not receive a signal (electric potential) from the outside and is formed in an electrically floating state.

[0047] For example, when the semiconductor device 1 is mounted in a semiconductor package, the entire area of ​​the input terminal 14b is covered with an insulator (e.g., a sealing resin containing a plurality of fillers and a matrix resin) and is electrically insulated from other structures. Of course, the input terminal 14b may be electrically connected to a lead terminal of the semiconductor package via a bonding wire so that a test signal can be input even after the semiconductor device 1 is mounted in the semiconductor package.

[0048] In this embodiment, the drain terminal 15 is provided as a power supply terminal and directly covers the second main surface 4 of the chip 2. That is, in this embodiment, the semiconductor device 1 is a high-side switching device electrically interposed between a power supply and a load. The drain terminal 15 is electrically connected to the drain region 10 on the second main surface 4. The drain terminal 15 covers the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (the first to fourth side surfaces 5A to 5D).

[0049] Fig. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device 1 shown in Fig. 1. Fig. 4 is a schematic circuit diagram showing the configuration of the output transistor 20. Fig. 5 is a circuit diagram showing the first overvoltage protection circuit 39 shown in Fig. 3. Fig. 6 is a circuit diagram showing the second overvoltage protection circuit 49 shown in Fig. 3.

[0050] 3 shows an example of an operation of the semiconductor device 1, in which an inductive load L as an example of a load is electrically connected to the source terminal 13. The inductive load L is not a component of the semiconductor device 1. Therefore, a configuration including the semiconductor device 1 and the inductive load L may be referred to as an "inductive load driving device" or an "inductive load control device." Examples of the inductive load L include a relay, a solenoid, a lamp, and a motor. The inductive load L may be an inductive load for an automobile. That is, the semiconductor device 1 may be an inductive load for an automobile.

[0051] 3 and 4, semiconductor device 1 includes output transistor 20 formed in output region 6. In this embodiment, output transistor 20 is a gate split transistor including one main drain, one main source, and multiple main gates. The main drain is electrically connected to drain terminal 15. The main source is electrically connected to source terminal 13.

[0052] The multiple main gates are configured to receive multiple electrically independent gate signals (gate potentials) individually. The output transistor 20 generates a single output current Io (output signal) in response to the multiple gate signals. In other words, the output transistor 20 is a multi-input single-output switching device. The output current Io is a drain-source current that flows between the main drain and main source. The output current Io is output to the outside of the chip 2 (to an inductive load L) via the source terminal 13.

[0053] The output transistor 20 includes a plurality of (two or more) system transistors 21 that are electrically and independently controlled. In this embodiment, the plurality of system transistors 21 includes a first system transistor 21A and a second system transistor 21B. The plurality of system transistors 21 are formed together in the output region 6. The plurality of system transistors 21 are connected in parallel so that a plurality of gate signals are input individually, and are configured so that some system transistors 21 are in an on state and some are in an off state.

[0054] Each of the system transistors 21 includes a system drain, a system source, and a system gate. The system drains are electrically connected to a main drain (drain terminal 15). The system sources are electrically connected to a main source (source terminal 13). Each system gate is electrically connected to a respective main gate. In other words, each system gate constitutes a respective main gate.

[0055] The multiple system transistors 21 each generate a system current Is in response to a corresponding gate signal. Each system current Is is a drain-source current flowing between the system drain and the system source of the system transistor 21. The multiple system currents Is may have different values ​​or may have approximately the same value. The multiple system currents Is are added between the main drain and the main source. As a result, a single output current Io consisting of the added value of the multiple system currents Is is generated.

[0056] 4 , each of the plurality of system transistors 21 includes a single or multiple unit transistors 22 that are grouped together as individual control targets. Specifically, each of the plurality of system transistors 21 is configured by a parallel circuit including a single unit transistor 22 or multiple unit transistors 22.

[0057] In this embodiment, each of the plurality of unit transistors 22 is a trench gate vertical type. The plurality of system transistors 21 may be configured with the same number of unit transistors 22, or may be configured with different numbers of unit transistors 22.

[0058] Each unit transistor 22 includes a unit drain, a unit source, and a unit gate. The unit drain of each unit transistor 22 is electrically connected to the system drain of the corresponding system transistor 21. The unit source of each unit transistor 22 is electrically connected to the system source of the corresponding system transistor 21. The unit gate of each unit transistor 22 is electrically connected to the system gate of the corresponding system transistor 21.

[0059] The plurality of unit transistors 22 each generate a unit current Iu in response to a corresponding gate signal. Each unit current Iu is a drain-source current that flows between the unit drain and unit source of the unit transistor 22. The plurality of unit currents Iu may have different values ​​or may have approximately the same value. The plurality of unit currents Iu are added between the corresponding system drains and system sources. As a result, a system current Is consisting of the sum of the plurality of unit currents Iu is generated.

[0060] In this way, the output transistor 20 is configured so that the first system transistor 21A and the second system transistor 21B are electrically independent of each other and are controlled to be on and off. That is, the output transistor 20 is configured so that both the first system transistor 21A and the second system transistor 21B are simultaneously in the on state. Also, the output transistor 20 is configured so that either the first system transistor 21A or the second system transistor 21B is in the on state and the other is in the off state.

[0061] When both the first system transistor 21A and the second system transistor 21B are simultaneously turned on, the channel utilization rate of the output transistor 20 increases and the on-resistance decreases. When either the first system transistor 21A or the second system transistor 21B is turned on while the other is turned off, the channel utilization rate of the output transistor 20 decreases and the on-resistance increases. In other words, the output transistor 20 is a variable on-resistance switching device.

[0062] The semiconductor device 1 includes a control circuit 23 formed in the control region 7 so as to be electrically connected to the output transistor 20. The control circuit 23 may also be referred to as a "control IC." The control circuit 23 includes various functional circuits and, together with the output transistor 20, constitutes an IPD (Intelligent Power Device). The IPD may also be referred to as an "IPM (Intelligent Power Module)," an "IPS (Intelligent Power Switch)," a "smart power driver," a "smart MISFET (smart MOSFET)," or a "protected MISFET (protected MOSFET)."

[0063] In this embodiment, the control circuit 23 includes a gate control circuit 24, a current monitor circuit 25, an overcurrent protection circuit 26, an overheat protection circuit 27, an undervoltage malfunction avoidance circuit 28, an open load detection circuit 29, an active clamp circuit 30, a power supply reverse connection protection circuit 31, a logic circuit 32, and a test circuit 33. The control circuit 23 does not necessarily need to include all of these functional circuits at the same time, and it is sufficient if it includes at least one of these functional circuits.

[0064] The current monitor circuit 25 may be referred to as a CS circuit (Current Sense circuit). The overcurrent protection circuit 26 may be referred to as an OCP circuit (Over Current Protection circuit). The overheat protection circuit 27 may be referred to as a TSD circuit (Thermal Shut Down circuit). The low voltage malfunction prevention circuit 28 may be referred to as a UVLO circuit (Under Voltage Lock Out circuit). The open load detection circuit 29 may be referred to as an OLD circuit (Open Load Detection circuit). The power supply reverse connection protection circuit 31 may be referred to as an RBP circuit (Reverse Battery Protection circuit).

[0065] The gate control circuit 24 is configured to generate gate signals that control the on / off of the output transistors 20. Specifically, the gate control circuit 24 generates a plurality of gate signals that individually control the on / off of the plurality of system transistors 21. That is, in this embodiment, the gate control circuit 24 generates a first gate signal that individually controls the on / off of the first system transistors 21A, and a second gate signal that individually controls the on / off of the second system transistors 21B electrically independent of the first system transistors 21A.

[0066] The current monitor circuit 25 generates a monitor current that monitors the output current Io of the output transistor 20 and outputs the monitor current to another circuit. For example, the monitor circuit may include a transistor having a similar configuration to the output transistor 20, and be configured to generate a monitor current linked to the output current Io by being on / off controlled simultaneously with the output transistor 20. Of course, the current monitor circuit 25 may also be configured to generate a monitor current linked to one or more system currents Is.

[0067] The overcurrent protection circuit 26 generates an electrical signal for controlling the gate control circuit 24 based on the monitored current from the current monitor circuit 25 , and cooperates with the gate control circuit 24 to control the on / off state of the output transistor 20 .

[0068] For example, the overcurrent protection circuit 26 may be configured to determine that the output transistor 20 is in an overcurrent state when the monitor current is equal to or greater than a predetermined threshold, and to control some or all of the output transistors 20 (plurality of system transistors 21) to an off state in cooperation with the gate control circuit 24. Alternatively, the overcurrent protection circuit 26 may be configured to cooperate with the gate control circuit 24 to transition the output transistor 20 to normal operation when the monitor current is less than a predetermined threshold.

[0069] The overheat protection circuit 27 includes a first temperature sensing device (for example, a temperature sensing diode) that detects the temperature of the output region 6, and a second temperature sensing device (for example, a temperature sensing diode) that detects the temperature of the control region 7. The overheat protection circuit 27 generates an electrical signal that controls the gate control circuit 24 based on a first temperature detection signal from the first temperature sensing device and a second temperature detection signal from the second temperature sensing device, and cooperates with the gate control circuit 24 to control the on / off of the output transistor 20.

[0070] For example, the overheat protection circuit 27 may be configured to determine that the output region 6 is in an overheated state when the difference between the first temperature detection signal and the second temperature detection signal is equal to or greater than a predetermined threshold, and to control some or all of the output transistors 20 (plurality of system transistors 21) to an off state in cooperation with the gate control circuit 24. Alternatively, the overheat protection circuit 27 may be configured to switch the output transistors 20 to normal operation in cooperation with the gate control circuit 24 when the difference becomes less than a predetermined threshold.

[0071] Low voltage malfunction avoidance circuit 28 is configured to prevent malfunction of various functional circuits within control circuit 23 when the startup voltage for starting control circuit 23 is less than a predetermined value. For example, low voltage malfunction avoidance circuit 28 may be configured to start control circuit 23 when the startup voltage is equal to or greater than a predetermined threshold voltage, and to stop control circuit 23 when the startup voltage is less than the threshold voltage. The threshold voltage may have a hysteresis characteristic.

[0072] The open load detection circuit 29 determines the electrical connection state of the inductive load L. For example, the open load detection circuit 29 may be configured to monitor the voltage between the terminals of the output transistor 20 and determine that the inductive load L is in an open state when the voltage between the terminals is equal to or higher than a predetermined threshold. For example, the open load detection circuit 29 may be configured to determine that the inductive load L is in an open state when the monitor current is equal to or lower than a predetermined threshold.

[0073] The active clamp circuit 30 is electrically connected to the main drain and at least one main gate (for example, the system gate of the first system transistor 21A) of the output transistor 20. The active clamp circuit 30 includes a Zener diode and a pn junction diode connected in reverse bias series to the Zener diode. The pn junction diode is a backflow prevention diode that prevents backflow from the output transistor 20.

[0074] The active clamp circuit 30 is configured to cooperate with the gate control circuit 24 to control a part or all of the output transistor 20 to an ON state when a back electromotive force caused by the inductive load L is applied to the output transistor 20. Specifically, the output transistor 20 is controlled in a plurality of operation modes including a normal operation, a first OFF operation, an active clamp operation, and a second OFF operation.

[0075] In normal operation, both the first system transistor 21A and the second system transistor 21B are controlled to be in the ON state at the same time. This increases the channel utilization rate of the output transistor 20 and reduces the ON resistance. In the first OFF operation, both the first system transistor 21A and the second system transistor 21B are controlled to be changed from the ON state to the OFF state at the same time. This causes the back electromotive force caused by the inductive load L to be applied to both the first system transistor 21A and the second system transistor 21B.

[0076] The active clamp operation is an operation in which the output transistor 20 absorbs (consumes) the energy stored in the inductive load L, and is executed when the back electromotive force caused by the inductive load L exceeds a predetermined threshold voltage. In the active clamp operation, the first system transistor 21A is controlled to change from an off state to an on state, and at the same time, the second system transistor 21B is controlled (maintained) in an off state.

[0077] The channel utilization rate of the output transistor 20 during active clamp operation is less than the channel utilization rate of the output transistor 20 during normal operation. The on-resistance of the output transistor 20 during active clamp operation is greater than the on-resistance of the output transistor 20 during normal operation. This suppresses a sudden temperature rise of the output transistor 20 during active clamp operation, improving the active clamp withstand capability.

[0078] The second off operation is executed when the back electromotive force voltage becomes less than a predetermined threshold voltage. In the second off operation, the first system transistor 21A is controlled from the on state to the off state, and simultaneously the second system transistor 21B is controlled (maintained) in the off state. In this way, the back electromotive force (energy) of the inductive load L is absorbed by a part of the output transistor 20 (here, the first system transistor 21A). Of course, during active clamp operation, the first system transistor 21A may be controlled (maintained) in the off state, and simultaneously the second system transistor 21B may be controlled to the on state.

[0079] The power supply reverse connection protection circuit 31 is configured to detect a reverse voltage when the power supply is connected in reverse, and to protect the control circuit 23 and the output transistor 20 from the reverse voltage (reverse current). The logic circuit 32 is configured to generate an electrical signal to be supplied to various circuits in the control circuit 23.

[0080] The test circuit 33 is formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15, and is electrically connected to the input terminal 14b and the drain terminal 15. The test circuit 33 is formed to indirectly evaluate the electrical characteristics of the control circuit 23 during the manufacturing process. The test circuit 33 is preferably arranged in a region adjacent to the second protection region 9 and / or a region adjacent to the input terminal 14b in a plan view.

[0081] 1, 3, and 5, the semiconductor device 1 includes a first overvoltage protection circuit 39 formed in the first protection region 8. The first overvoltage protection circuit 39 may be referred to as a "first ESD protection circuit." The first overvoltage protection circuit 39 may be considered to be one component of the control circuit 23.

[0082] The first overvoltage protection circuit 39 is electrically connected between the ground terminal 14a (control terminal 14) and the drain terminal 15, and is configured to form a discharge path (first discharge path) for a first overvoltage Vs1 generated between the ground terminal 14a and the drain terminal 15. Specifically, the first overvoltage protection circuit 39 forms a discharge path for the first overvoltage Vs1 generated at the drain terminal 15, with the ground terminal 14a as the reference. An example of the first overvoltage Vs1 is a surge voltage caused by static electricity or the like from a power supply.

[0083] In this embodiment, the first overvoltage protection circuit 39 is configured to limit the first overvoltage Vs1 to a clamp voltage Vc that is less than the first overvoltage Vs1. Specifically, the first overvoltage protection circuit 39 includes a first protection transistor 40 and a clamp circuit 41. In this embodiment, the first protection transistor 40 is formed on the first main surface 3 in the first protection region 8, and the clamp circuit 41 is formed on the first main surface 3 in a region outside the first protection region 8. For example, the clamp circuit 41 may be formed in a region surrounding the first protection region 8 so as to be adjacent to the first protection region 8.

[0084] The first protection transistor 40 includes a drain, a source, a gate, and a back gate. With respect to the first protection transistor 40, the drain is electrically connected to the drain terminal 15, the source is electrically connected to the ground terminal 14 a, the gate forms a node portion for the clamp circuit 41, and the back gate is electrically connected to the ground terminal 14 a. In this embodiment, the source of the first protection transistor 40 is electrically connected to the ground terminal 14 a via the power supply reverse connection protection circuit 31.

[0085] The clamp circuit 41 includes a first diode stage 42 and a second diode stage 43. The first diode stage 42 includes a first anode portion and a first cathode portion. The first anode portion of the first diode stage 42 forms a node portion for the second diode stage 43. The first cathode portion of the first diode stage 42 is electrically connected to the drain (drain terminal 15) of the first protection transistor 40.

[0086] The first diode stage 42 includes m (m≧1) Zener diodes. The first diode stage 42 may be configured with a single Zener diode or multiple Zener diodes connected in series in the forward direction. The number of Zener diodes is adjusted depending on the terminal voltage Vz×m of the first diode stage 42 to be achieved.

[0087] The second diode stage 43 includes a second anode portion and a second cathode portion. The second anode portion of the second diode stage 43 is electrically connected to the first anode portion of the first diode stage 42. The second cathode portion of the second diode stage 43 is electrically connected to the gate of the first protection transistor 40.

[0088] The second diode stage 43 includes n (n≧1) pn junction diodes. The second diode stage 43 may be configured with a single pn junction diode or multiple pn junction diodes connected in series in the forward direction. The number of pn junction diodes is adjusted depending on the inter-terminal voltage Vf×n of the second diode stage 43 to be achieved. The second diode stage 43 is a backflow prevention diode that prevents backflow from the first protection transistor 40.

[0089] When a first overvoltage Vs1 equal to or greater than the breakdown voltage of the first diode stage 42 is applied to the drain terminal 15, the first diode stage 42 enters a breakdown state, and the gate voltage of the first protection transistor 40 becomes equal to or greater than the gate threshold voltage. This turns the first protection transistor 40 on, and an overcurrent (first overcurrent) flows from the drain terminal 15 to the ground terminal 14a via the first protection transistor 40. In other words, the overcurrent flows from the second main surface 4 to the first main surface 3 in the chip 2.

[0090] In this way, when the first overvoltage Vs1 occurs, the first overvoltage protection circuit 39 forms a bypass path (discharge path) for the overcurrent from the drain terminal 15 to the ground terminal 14a, and the inter-terminal voltage between the ground terminal 14a and the drain terminal 15 is limited to the clamp voltage Vc.

[0091] As a result, the control circuit 23 and the output transistor 20 are protected from the first overvoltage Vs1 by the first overvoltage protection circuit 39. The clamp voltage Vc includes the sum of the gate threshold voltage Vgth of the first protection transistor 40 and the inter-terminal voltage Vz×m of the first diode stage 42.

[0092] The first protection transistor 40 has a configuration in which a bias voltage resulting from the first overvoltage Vs1 is applied to the gate, but has a configuration different from the output transistor 20 in that a gate signal from the control circuit 23 (gate control circuit 24) or the like is not input to the gate.

[0093] 1, 3, and 6, the semiconductor device 1 includes a second overvoltage protection circuit 49 formed in the second protection region 9. The second overvoltage protection circuit 49 may be referred to as a "second ESD protection circuit." The second overvoltage protection circuit 49 may be considered to be one component of the control circuit 23.

[0094] The second overvoltage protection circuit 49 is electrically interposed between the input terminal 14b (control terminal 14) and the drain terminal 15, and is configured to form a discharge path (second discharge path) for the second overvoltage Vs2 that occurs between the input terminal 14b and the drain terminal 15. Specifically, the second overvoltage protection circuit 49 forms a discharge path for the second overvoltage Vs2 that occurs at the input terminal 14b, with the drain terminal 15 as the reference. An example of the second overvoltage Vs2 is a surge voltage caused by static electricity or the like that may occur when a probe is brought into contact with the input terminal 14b.

[0095] The second overvoltage protection circuit 49 has a different circuit configuration from the first overvoltage protection circuit 39. In this embodiment, the second overvoltage protection circuit 49 includes a second protection transistor 50. The second protection transistor 50 includes a drain, a source, a gate, and a back gate. With respect to the second overvoltage protection circuit 49, the drain is electrically connected to the drain terminal 15, the source is electrically connected to the input terminal 14b, the gate is electrically connected to the input terminal 14b, and the back gate is electrically connected to the input terminal 14b.

[0096] That is, the second protection transistor 50 has a gate that is diode-connected to the source. Therefore, in the second overvoltage protection circuit 49, the gate is fixed at the same potential as the source, so the gate voltage does not exceed the gate threshold voltage. The second protection transistor 50 functions as a diode that is forward-connected to the drain terminal 15 between the input terminal 14b and the drain terminal 15. Specifically, the diode is a body diode (pn junction diode) of the second protection transistor 50.

[0097] When a second overvoltage Vs2 equal to or greater than the forward threshold voltage of the second protection transistor 50 acting as a diode is applied to the input terminal 14b, the second protection transistor 50 is turned on, and an overcurrent (second overcurrent) flows from the input terminal 14b to the drain terminal 15 via the second protection transistor 50. In other words, the overcurrent flows from the first main surface 3 to the second main surface 4 in the chip 2. The direction of the current through the second protection transistor 50 is opposite to the direction of the current through the first protection transistor 40 with respect to the thickness direction of the chip 2.

[0098] In this way, when the second overvoltage Vs2 occurs, the second overvoltage protection circuit 49 forms a bypass path (discharge path) for the overcurrent from the input terminal 14b to the drain terminal 15. In this way, the second overvoltage protection circuit 49 protects the control circuit 23 and the output transistor 20 from the second overvoltage Vs2.

[0099] The second protection transistor 50 has a configuration in which a bias voltage resulting from the second overvoltage Vs2 is applied to the gate, but has a configuration different from the output transistor 20 in that a gate signal from the control circuit 23 (gate control circuit 24) or the like is not input to the gate.

[0100] 5 and 6 show examples in which the first overvoltage protection circuit 39 and the second overvoltage protection circuit 49 have different circuit configurations. However, the first overvoltage protection circuit 39 may have the same circuit configuration as the second overvoltage protection circuit 49 (see FIG. 6). Furthermore, the second overvoltage protection circuit 49 may have the same circuit configuration as the first overvoltage protection circuit 39 (see FIG. 5).

[0101] Of course, overvoltage protection circuits such as the first overvoltage protection circuit 39 and the second overvoltage protection circuit 49 may be provided for other control terminals 14 where an overvoltage may occur. Furthermore, the second overvoltage protection circuit 49 does not necessarily need to be electrically connected to the test circuit 33, and may be used only as a discharge path for static electricity caused by the probe.

[0102] The configuration of the output region 6 side will be described below with reference to FIGS. 7 to 14. FIG. 7 is a plan view showing the output region 6 shown in FIG. 1. FIG. 8 is an enlarged plan view showing a main portion of the output region 6 shown in FIG. 7. FIG. 9 is an enlarged plan view showing further main portions of the output region 6 shown in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX shown in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 8. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 8. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 8. FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. 8.

[0103] The semiconductor device 1 includes a first trench isolation structure 60 formed in the first main surface 3 to define the output region 6. The first trench isolation structure 60 may also be referred to as a "first region isolation structure." The first trench isolation structure 60 electrically isolates the output region 6 from the control region 7, the first protection region 8, and the second protection region 9 within the chip 2. A source potential is applied to the first trench isolation structure 60.

[0104] The first trench isolation structure 60 is formed in a ring shape surrounding the output region 6 in plan view. In this embodiment, the first trench isolation structure 60 is formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in plan view. The first trench isolation structure 60 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 with a part of the drift region 11 in between.

[0105] The first trench isolation structure 60 has a first width W1. The first width W1 is the width in a direction perpendicular to the extension direction of the first trench isolation structure 60. The first width W1 may be 0.4 μm or more and 2.5 μm or less. The first width W1 may have a value belonging to any one of the following ranges: 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The first width W1 is preferably 1.25 μm or more and 1.75 μm or less.

[0106] The first trench isolation structure 60 has a first depth D1. The first depth D1 may be 1 μm or more and 6 μm or less. The first depth D1 may have a value belonging to any one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The first depth D1 is preferably 3 μm or more and 5 μm or less.

[0107] The first trench isolation structure 60 includes a first isolation trench 61, a first isolation insulating film 62, and a first isolation electrode 63. In other words, the first trench isolation structure 60 has a single electrode structure including a single electrode (first isolation electrode 63) embedded in the first isolation trench 61 with an insulator (first isolation insulating film 62) sandwiched therebetween.

[0108] The first isolation trench 61 is formed in the first main surface 3 and defines the wall surface of the first trench isolation structure 60. The first isolation insulating film 62 covers the wall surface of the first isolation trench 61. The first isolation insulating film 62 may include a silicon oxide film. The first isolation insulating film 62 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The first isolation electrode 63 is embedded in the first isolation trench 61 with the first isolation insulating film 62 sandwiched therebetween. The first isolation electrode 63 may include conductive polysilicon.

[0109] The semiconductor device 1 includes an output transistor 20 formed on the first main surface 3 in the output region 6. The following components will be described as components of the semiconductor device 1, but they are also components of the output transistor 20.

[0110] The semiconductor device 1 includes an n-type high-concentration drift region 64 formed in the surface layer of the drift region 11 in the output region 6. The high-concentration drift region 64 has a higher n-type impurity concentration than the drift region 11. The n-type impurity concentration of the high-concentration drift region 64 may be lower than the n-type impurity concentration of the drain region 10. The n-type impurity concentration of the high-concentration drift region 64 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ The high concentration drift region 64 may be considered as a high concentration portion of the drift region 11.

[0111] The high-concentration drift region 64 forms a concentration gradient within the drift region 11 in which the n-type impurity concentration increases from the bottom side of the drift region 11 toward the first main surface 3. In other words, the drift region 11 of the output region 6 has a concentration gradient formed by the high-concentration drift region 64 in which the n-type impurity concentration increases from the bottom side toward the first main surface 3.

[0112] The heavily doped drift region 64 is formed in the inner part of the output region 6 at a distance from the first trench isolation structure 60. Therefore, the heavily doped drift region 64 is surrounded by the drift region 11 in the output region 6 and is not in contact with the first trench isolation structure 60. The heavily doped drift region 64 locally increases the n-type impurity concentration of the drift region 11 in the output region 6.

[0113] The heavily doped drift region 64 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a part of the drift region 11. The heavily doped drift region 64 has a bottom that is located closer to the bottom of the drift region 11 than the bottom wall of the first trench isolation structure 60. The bottom of the heavily doped drift region 64 meanders to one side and the other side in the thickness direction in a cross-sectional view.

[0114] Specifically, the bottom of the high-concentration drift region 64 has multiple bulges 65 and multiple recesses 66 in a cross-sectional view. The multiple bulges 65 are arc-shaped bulges extending toward the bottom of the drift region 11. The multiple bulges 65 are formed continuously in the first direction X in a plan view, and each bulge is formed in a strip shape extending in the second direction Y. Each bulge 65 is formed wider in the first direction X than the first trench isolation structure 60.

[0115] The multiple recesses 66 are each formed in a strip shape extending in the second direction Y in the region between the multiple bulging portions 65. The multiple recesses 66 are portions where the shallow portions of the multiple bulging portions 65 are connected to each other, and are located closer to the first main surface 3 than the deepest portions of the multiple bulging portions 65. Of course, the high-concentration drift region 64 may have a flat bottom that does not meander up and down in the thickness direction.

[0116] The high-concentration drift region 64 may be formed by increasing the concentration of the drift region 11 throughout the output region 6. This configuration reduces the on-resistance of the drift region 11 by increasing the concentration of the drift region 11. However, in this case, it should be noted that an increase in the carrier density in the drift region 11 may increase the likelihood of electric field concentration, resulting in a decrease in the breakdown voltage. Therefore, in order to reduce the on-resistance while suppressing a decrease in the breakdown voltage, it is preferable to introduce the high-concentration drift region 64 into a portion of the output region 6.

[0117] The semiconductor device 1 includes a p-type (second conductivity type) first body region 67 formed in a surface layer portion of the drift region 11 in the output region 6. The first body region 67 extends in a layered form along the first main surface 3 throughout the entire output region 6, and is connected to the wall surface of the first trench isolation structure 60. That is, in this embodiment, the first body region 67 is not formed in a region outside the first trench isolation structure 60.

[0118] The first body region 67 is formed shallower than the high-concentration drift region 64. Specifically, the first body region 67 is formed shallower than the first trench isolation structure 60, and has a bottom located closer to the first main surface 3 than the bottom wall of the first trench isolation structure 60. The bottom of the first body region 67 is preferably located closer to the first main surface 3 than the intermediate depth range of the first trench isolation structure 60.

[0119] The semiconductor device 1 includes a plurality of first trench gate structures 70 formed on the first main surface 3 in the output region 6. The plurality of first trench gate structures 70 are formed inward of the output region 6 at intervals from the first trench isolation structure 60. The plurality of first trench gate structures 70 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. In other words, the plurality of first trench gate structures 70 are arranged in a stripe shape extending in the second direction Y. The plurality of first trench gate structures 70 cross one end and the other end of the high-concentration drift region 64 in the longitudinal direction (second direction Y).

[0120] The plurality of first trench gate structures 70 have a first end on one side in the longitudinal direction (second direction Y) and a second end on the other side in the longitudinal direction (second direction Y). The first end is located in a region between the first trench isolation structure 60 and one end of the high-concentration drift region 64 in a plan view. The second end is located in a region between the first trench isolation structure 60 and the other end of the high-concentration drift region 64 in a plan view.

[0121] The multiple first trench gate structures 70 penetrate the first body region 67 in a cross-sectional view and are located in the high-concentration drift region 64. The multiple first trench gate structures 70 are formed at intervals from the bottom of the high-concentration drift region 64 toward the first main surface 3, and face the drift region 11 with a part of the high-concentration drift region 64 in between.

[0122] The first trench gate structures 70 are formed to be shifted in the first direction X with respect to the recessed portions 66, and face the bulging portions 65 in the thickness direction, respectively. The first trench gate structures 70 preferably face the deepest portions of the bulging portions 65. This configuration is obtained by introducing n-type impurities into the chip 2 from the wall surfaces of the first gate trenches 71 after the step of forming the first gate trenches 71.

[0123] The two first trench gate structures 70 located on both sides in the first direction X are preferably formed in regions outside the high-concentration drift region 64. That is, the outermost first trench gate structure 70 preferably penetrates the first body region 67 at a position spaced from the high-concentration drift region 64 toward the first trench isolation structure 60, and is located within the drift region 11. The outermost first trench gate structure 70 is formed spaced from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 with a part of the drift region 11 between them.

[0124] The plurality of first trench gate structures 70 have a second width W2. The second width W2 is the width in a direction perpendicular to the extension direction of the first trench gate structures 70 (i.e., the first direction X). The second width W2 may be approximately equal to the first width W1 of the first trench isolation structure 60. The second width W2 is preferably equal to or smaller than the first width W1. It is particularly preferable that the second width W2 be smaller than the first width W1.

[0125] The second width W2 may be 0.4 μm or more and 2 μm or less. The second width W2 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The second width W2 is preferably 0.8 μm or more and 1.2 μm or less.

[0126] The multiple first trench gate structures 70 are arranged at a first interval I1 in the first direction X. The first interval I1 is also the mesa width (first mesa width) of a mesa portion (first mesa portion) defined in a region between two adjacent first trench gate structures 70. The first interval I1 is preferably equal to or smaller than the first width W1 of the first trench isolation structure 60. The first interval I1 is preferably equal to or smaller than the second width W2. It is particularly preferable that the first interval I1 be smaller than the second width W2.

[0127] The first interval I1 may be 0.4 μm or more and 0.8 μm or less. The first interval I1 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.5 μm or less, 0.5 μm or more and 0.6 μm or less, 0.6 μm or more and 0.7 μm or less, and 0.7 μm or more and 0.8 μm or less. The first interval I1 is preferably 0.5 μm or more and 0.7 μm or less.

[0128] The first trench gate structure 70 has a second depth D2. The second depth D2 may be approximately equal to the first depth D1 of the first trench isolation structure 60. Preferably, the second depth D2 is equal to or less than the first depth D1. It is particularly preferred that the second depth D2 be less than the first depth D1.

[0129] The second depth D2 may be 1 μm or more and 6 μm or less. The second depth D2 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The second depth D2 is preferably 2.5 μm or more and 4.5 μm or less.

[0130] The following describes the internal configuration of one first trench gate structure 70. The first trench gate structure 70 includes a first gate trench 71, a first insulating film 72, a first upper electrode 73, a first lower electrode 74, and a first intermediate insulating film 75. In other words, the first trench gate structure 70 has a multi-electrode structure including multiple electrodes (first upper electrode 73 and first lower electrode 74) embedded vertically in the first gate trench 71 with an insulator (first insulating film 72 and first intermediate insulating film 75) sandwiched therebetween.

[0131] The first gate trench 71 is formed in the first main surface 3 and defines a wall surface of the first trench gate structure 70. The first insulating film 72 covers the wall surface of the first gate trench 71. The first insulating film 72 includes a first upper insulating film 76 and a first lower insulating film 77. The first upper insulating film 76 covers the wall surface of the first gate trench 71 on the opening side relative to the bottom of the first body region 67.

[0132] The first upper insulating film 76 partially covers the wall surface of the first gate trench 71 on the bottom wall side relative to the bottom of the first body region 67. The first upper insulating film 76 is thinner than the first isolation insulating film 62. The first upper insulating film 76 is formed as a gate insulating film. The first upper insulating film 76 may include a silicon oxide film. It is preferable that the first upper insulating film 76 include a silicon oxide film made of an oxide of the chip 2.

[0133] The first lower insulating film 77 covers the wall surface of the first gate trench 71 on the bottom wall side relative to the bottom of the first body region 67. The first lower insulating film 77 is thicker than the first upper insulating film 76. The thickness of the first lower insulating film 77 may be approximately equal to the thickness of the first isolation insulating film 62. The first lower insulating film 77 may include a silicon oxide film. The first lower insulating film 77 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0134] The first upper electrode 73 is embedded in the opening side of the first gate trench 71 with a first insulating film 72 sandwiched therebetween. Specifically, the first upper electrode 73 is embedded in the opening side of the first gate trench 71 with a first upper insulating film 76 sandwiched therebetween, and faces the first body region 67 and the high-concentration drift region 64 with the first upper insulating film 76 sandwiched therebetween. The first upper electrode 73 may include conductive polysilicon.

[0135] The first lower electrode 74 is embedded in the bottom wall of the first gate trench 71 with the first insulating film 72 sandwiched therebetween. Specifically, the first lower electrode 74 is embedded in the bottom wall of the first gate trench 71 with the first lower insulating film 77 sandwiched therebetween, and faces the high-concentration drift region 64 with the first lower insulating film 77 sandwiched therebetween. The first lower electrode 74 of the outermost first trench gate structure 70 faces the drift region 11 with the first lower insulating film 77 sandwiched therebetween.

[0136] The first lower electrode 74 has an upper end that protrudes from the first lower insulating film 77 toward the first upper electrode 73 so as to engage with the bottom of the first upper electrode 73. The upper end of the first lower electrode 74 faces the first upper insulating film 76 across the lower end of the first upper electrode 73 in the lateral direction along the first main surface 3. The first lower electrode 74 may include conductive polysilicon.

[0137] The first intermediate insulating film 75 is interposed between the first upper electrode 73 and the first lower electrode 74, and electrically insulates the first upper electrode 73 and the first lower electrode 74 within the first gate trench 71. The first intermediate insulating film 75 is continuous with the first upper insulating film 76 and the first lower insulating film 77. The first intermediate insulating film 75 is thinner than the first lower insulating film 77. The first intermediate insulating film 75 may include a silicon oxide film. The first intermediate insulating film 75 preferably includes a silicon oxide film made of an oxide of the first lower electrode 74.

[0138] The semiconductor device 1 includes a plurality of first channel cells 78 formed on both sides of each first trench gate structure 70 as control targets of each first trench gate structure 70. In this embodiment, the two first channel cells 78 arranged on both sides of one first trench gate structure 70 are controlled by that one first trench gate structure 70 and are not controlled by the other first trench gate structure 70.

[0139] The plurality of first channel cells 78 are formed in a region along the inner portion of the first trench gate structure 70 at intervals from both ends in the longitudinal direction (second direction Y) of the first trench gate structure 70. The plurality of first channel cells 78 expose the first body region 67 from a region of the first main surface 3 that is sandwiched between both ends of the plurality of first trench gate structures 70.

[0140] The first channel cells 78 face the high-concentration drift region 64 in the thickness direction, sandwiching a part of the first body region 67. The first channel cells 78 are preferably formed inward of the high-concentration drift region 64 relative to the periphery of the high-concentration drift region 64 in plan view.

[0141] Each first channel cell 78 includes a plurality of n-type first source regions 79 and a plurality of p-type first contact regions 80. In FIG. 8 , the first source regions 79 are hatched for clarity. The first contact regions 80 may also be referred to as "first back gate regions." Each first source region 79 has a higher n-type impurity concentration than the drift region 11. Each first source region 79 may also have a higher n-type impurity concentration than the high-concentration drift region 64. The n-type impurity concentration of each first source region 79 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0142] The multiple first source regions 79 are arranged at intervals along each first trench gate structure 70. The multiple first source regions 79 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3, and face the first upper electrode 73 with the first insulating film 72 (first upper insulating film 76) interposed therebetween.

[0143] Each first contact region 80 has a higher p-type impurity concentration than the first body region 67. The p-type impurity concentration of each first contact region 80 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The plurality of first contact regions 80 are arranged alternately with the plurality of first source regions 79 along each first trench gate structure 70. The plurality of first contact regions 80 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3, and face the first upper electrode 73 with the first insulating film 72 (first upper insulating film 76) interposed therebetween.

[0144] With respect to two first channel cells 78 formed on both sides of one first trench gate structure 70, the multiple first source regions 79 in one first channel cell 78 face the multiple first source regions 79 in the other first channel cell 78 across the first trench gate structure 70. Furthermore, the multiple first contact regions 80 in one first channel cell 78 face the multiple first contact regions 80 in the other first channel cell 78 across the first trench gate structure 70.

[0145] Of course, the plurality of first source regions 79 in one first channel cell 78 may face the plurality of first contact regions 80 in the other first channel cell 78 across the first trench gate structure 70. Also, the plurality of first contact regions 80 in one first channel cell 78 may face the plurality of first source regions 79 in the other first channel cell 78 across the first trench gate structure 70.

[0146] With respect to two first channel cells 78 interposed between two first trench gate structures 70, the plurality of first source regions 79 in one first channel cell 78 are connected in the first direction X to the plurality of first contact regions 80 in the other first channel cell 78. Also, the plurality of first contact regions 80 in one first channel cell 78 are connected in the first direction X to the plurality of first source regions 79 in the other first channel cell 78.

[0147] Of course, the plurality of first source regions 79 in one first channel cell 78 may be connected in the first direction X to the plurality of first source regions 79 in the other first channel cell 78. Also, the plurality of first contact regions 80 in one first channel cell 78 may be connected in the first direction X to the plurality of first contact regions 80 in the other first channel cell 78.

[0148] Of the two first channel cells 78 formed on both sides of the outermost first trench gate structure 70, the first channel cell 78 located on the inner side faces the drift region 11 across a part of the first body region 67 in the thickness direction. On the other hand, the first channel cell 78 located on the outer side does not include a first source region 79, but includes only a first contact region 80. This suppresses the formation of a current path in the region between the first trench isolation structure 60 and the outermost first trench gate structure 70.

[0149] The output transistor 20 includes a plurality of unit transistors 22. Each of the plurality of unit transistors 22 includes a first trench gate structure 70 and two first channel cells 78 formed on either side of the first trench gate structure 70. For each unit transistor 22, the first trench gate structure 70 constitutes a unit gate, the plurality of first source regions 79 (two first channel cells 78) constitute a unit source, and the drain region 10 (drift region 11 and high-concentration drift region 64) constitutes a unit drain.

[0150] The output transistors 20 include first system transistors 21A and second system transistors 21B. The first system transistors 21A include a plurality of unit transistors 22 that have been grouped together as targets of individual control from a plurality of unit transistors 22. The second system transistors 21B include a plurality of unit transistors 22 that have been grouped together as targets of individual control from a plurality of unit transistors 22 other than the first system transistors 21A.

[0151] In this embodiment, the output transistor 20 includes a plurality of block regions 81 provided in the output region 6. The plurality of block regions 81 include a plurality of first block regions 81A and a plurality of second block regions 81B. The plurality of first block regions 81A are regions in which one or more (a plurality in this embodiment) unit transistors 22 for the first system transistors 21A are arranged. The plurality of second block regions 81B are regions in which one or more (a plurality in this embodiment) unit transistors 22 for the second system transistors 21B are arranged.

[0152] The multiple first block regions 81A are arranged at intervals in the first direction X. The number of unit transistors 22 in each first block region 81A is arbitrary. In this embodiment, two unit transistors 22 are arranged in each first block region 81A. As the number of unit transistors 22 in each first block region 81A increases, the amount of heat generated in each first block region 81A increases. Therefore, it is preferable that the number of unit transistors 22 in each first block region 81A be between two and five.

[0153] The second block regions 81B are arranged alternately with the first block regions 81A along the first direction X so as to sandwich one first block region 81A therebetween. This allows the second block regions 81B to thin out heat generating locations caused by the first block regions 81A, and simultaneously allows the first block regions 81A to thin out heat generating locations caused by the second block regions 81B.

[0154] Each second block region 81B may have any number of unit transistors 22. In this embodiment, two unit transistors 22 are arranged in each second block region 81B. As the number of unit transistors 22 in each second block region 81B increases, the amount of heat generated in each second block region 81B increases.

[0155] Therefore, the number of unit transistors 22 in each second block region 81B is preferably between 2 and 5. In consideration of in-plane temperature variations in the output region 6, the number of unit transistors 22 in the second block region 81B is preferably the same as the number of unit transistors 22 in the first block region 81A.

[0156] The semiconductor device 1 includes a pair of first trench connection structures 90 that connect both ends of a plurality (two in this embodiment) of first trench gate structures 70 to be organized (grouped) in each block region 81. That is, the pair of first trench connection structures 90 connect both ends of the plurality of first trench gate structures 70 to be organized as system transistors 21, respectively.

[0157] The first trench connection structure 90 on one side connects, in an arch shape, first ends of a corresponding plurality of (two in this embodiment) first trench gate structures 70 in a plan view. The first trench connection structure 90 on the other side connects, in an arch shape, second ends of a corresponding plurality of (two in this embodiment) first trench gate structures 70 in a plan view.

[0158] Specifically, the first trench connection structure 90 on one side has a first portion extending in the first direction X and a plurality of (two in this embodiment) second portions extending in the second direction Y. The first portion faces first ends of the plurality of first trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

[0159] The other first trench connection structure 90 has a first portion extending in the first direction X and a plurality of (two in this embodiment) second portions extending in the second direction Y. The first portion faces the second ends of the plurality of first trench gate structures 70 in a plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends. The plurality of first trench connection structures 90 and the plurality of first trench gate structures 70 in each block region 81 form a ring-shaped or ladder-shaped trench structure.

[0160] The plurality of first trench connection structures 90 are formed in a region between the first trench isolation structure 60 and the heavily doped drift region 64 at intervals from the first trench isolation structure 60 and the heavily doped drift region 64. The plurality of first trench connection structures 90 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3, and face the drain region 10 with a part of the drift region 11 in between.

[0161] The plurality of first trench connection structures 90 may be formed with approximately the same width and depth as the first trench gate structure 70. Of course, the first and second portions of the first trench connection structure 90 may have different widths. For example, the second portion of the first trench connection structure 90 may be formed narrower than the first portion of the first trench connection structure 90.

[0162] In this case, the first portion may have a width approximately equal to the width of the first trench isolation structure 60, and the second portion may have a width approximately equal to the width of the first trench gate structure 70. Furthermore, in this case, the first portion may have a depth approximately equal to the depth of the first trench isolation structure 60, and the second portion may have a depth approximately equal to the depth of the first trench gate structure 70.

[0163] The first trench connection structure 90 on the other side has the same structure as the first trench connection structure 90 on one side, except that it is connected to the second end of the first trench gate structure 70. Below, the configuration of the first trench connection structure 90 on one side will be described, and a description of the configuration of the first trench connection structure 90 on the other side will be omitted.

[0164] The first trench connection structure 90 includes a first connection trench 91, a first connection insulating film 92, and a first connection electrode 93. The first connection trench 91 is formed in the first main surface 3 and defines the wall surface of the first trench connection structure 90. The first connection trench 91 is connected to a plurality of first gate trenches 71.

[0165] The first connection insulating film 92 covers the wall surface of the first connection trench 91. The first connection insulating film 92 is connected to the first upper insulating film 76, the first lower insulating film 77, and the first intermediate insulating film 75 at the communicating portion between the first connection trench 91 and the first gate trench 71. The first connection insulating film 92 is thicker than the first upper insulating film 76. The thickness of the first connection insulating film 92 may be approximately equal to the thickness of the first lower insulating film 77. The first connection insulating film 92 may include a silicon oxide film. The first connection insulating film 92 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0166] The first connection electrode 93 is buried in the first connection trench 91 with a first connection insulating film 92 interposed therebetween, and faces the drift region 11 and the first body region 67 with the first connection insulating film 92 interposed therebetween. The first connection electrode 93 is connected to the first lower electrode 74 at the communicating portion between the first connection trench 91 and the first gate trench 71, and is electrically insulated from the first upper electrode 73 by a first intermediate insulating film 75. The first connection electrode 93 is formed by an extension portion of the first lower electrode 74 that is extended from inside the first gate trench 71 into the first connection trench 91. The first connection electrode 93 may include conductive polysilicon.

[0167] The semiconductor device 1 includes a first main surface insulating film 94 that selectively covers the first main surface 3 in the output region 6. The first main surface insulating film 94 is connected to the first insulating film 72 (first upper insulating film 76) and the first connecting insulating film 92, and exposes the first isolated electrode 63, the first upper electrode 73, and the first connecting electrode 93.

[0168] The first main surface insulating film 94 is thinner than the first isolation insulating film 62. The first main surface insulating film 94 is thinner than the first lower insulating film 77. The first main surface insulating film 94 is thinner than the first connection insulating film 92. The first main surface insulating film 94 may have a thickness approximately equal to that of the first upper insulating film 76. The first main surface insulating film 94 may include a silicon oxide film. It is preferable that the first main surface insulating film 94 include a silicon oxide film made of an oxide of the chip 2.

[0169] The semiconductor device 1 includes a first field insulating film 95 that selectively covers the first main surface 3 inside and outside the output region 6. The first field insulating film 95 is thicker than the first main surface insulating film 94. The first field insulating film 95 is thicker than the first upper insulating film 76. The first field insulating film 95 may have a thickness approximately equal to that of the first isolation insulating film 62. The first field insulating film 95 may include a silicon oxide film. The first field insulating film 95 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0170] The first field insulating film 95 covers the first main surface 3 along the inner wall of the first trench isolation structure 60 within the output region 6, and is connected to the first isolation insulating film 62, the first connection insulating film 92, and the first main surface insulating film 94. The first field insulating film 95 covers the first main surface 3 along the outer wall of the first trench isolation structure 60 outside the output region 6, and is connected to the first isolation insulating film 62.

[0171] The interlayer insulating layer 12 described above covers the first trench isolation structure 60 , the first trench gate structure 70 , the first trench connection structure 90 , the first main surface insulating film 94 and the first field insulating film 95 in the output region 6 .

[0172] The semiconductor device 1 includes a plurality of first gate wirings 96 arranged in the interlayer insulating layer 12. The plurality of first gate wirings 96 are routed to the output region 6 and the control region 7, and are electrically connected to the output transistors 20 in the output region 6, and are electrically connected to the control circuit 23 (gate control circuit 24) in the control region 7. The plurality of first gate wirings 96 individually transmit a plurality of gate signals generated by the control circuit 23 (gate control circuit 24) to the output transistors 20.

[0173] The plurality of first gate wirings 96 include first-system gate wirings 96A and second-system gate wirings 96B. The first-system gate wirings 96A individually transmit gate signals to the first-system transistors 21A. The first-system gate wirings 96A are electrically connected to the plurality of first trench gate structures 70 for the first-system transistors 21A through a plurality of via electrodes 97 arranged in the interlayer insulating layer 12. Specifically, the first-system gate wirings 96A are electrically connected to the corresponding plurality of first upper electrodes 73 and the corresponding plurality of first connection electrodes 93 through the plurality of via electrodes 97.

[0174] That is, the first upper electrode 73 and the first lower electrode 74 for the first system transistor 21A are simultaneously turned on and off by the same gate signal. This suppresses the voltage drop between the first upper electrode 73 and the first lower electrode 74, thereby suppressing undesired electric field concentration. As a result, the decrease in breakdown voltage caused by the electric field concentration is suppressed.

[0175] The second-system gate wiring 96B transmits gate signals individually to the second-system transistors 21B, electrically independent from the first-system gate wiring 96A. The second-system gate wiring 96B is electrically connected to the plurality of first trench gate structures 70 for the second-system transistors 21B through a plurality of via electrodes 97 arranged in the interlayer insulating layer 12. Specifically, the second-system gate wiring 96B is electrically connected to the corresponding plurality of first upper electrodes 73 and the corresponding plurality of first connection electrodes 93 through the plurality of via electrodes 97.

[0176] That is, the first upper electrode 73 and the first lower electrode 74 for the second system transistor 21B are simultaneously turned on and off by the same gate signal. This suppresses the voltage drop between the first upper electrode 73 and the first lower electrode 74, thereby suppressing undesired electric field concentration. As a result, the decrease in breakdown voltage caused by the electric field concentration is suppressed.

[0177] The semiconductor device 1 includes a first source wiring 98 disposed in the interlayer insulating layer 12. The first source wiring 98 is electrically connected to the source terminal 13, the first trench isolation structure 60, and the plurality of first channel cells 78. Specifically, the first source wiring 98 is electrically connected to the first trench isolation structure 60 and the plurality of first channel cells 78 through a plurality of via electrodes 97 disposed in the interlayer insulating layer 12.

[0178] The via electrode 97 for each first channel cell 78 is arranged so as to straddle two adjacent first channel cells 78, and is formed in a strip shape extending along each first channel cell 78 in plan view. As a result, the source terminal 13 is electrically connected to the system sources of all the system transistors 21 (the unit sources of the unit transistors 22).

[0179] The configuration of the first protection region 8 (first protection transistor 40) side will be described below with reference to Figures 15 to 22. The configuration of the second protection region 9 (second protection transistor 50) side is the same as the configuration of the first protection region 8 side, except for differences in the electrical connection configuration, placement location, plane area, etc. (See also Figures 1 to 6).

[0180] Therefore, the description of the configuration on the second protection region 9 side will be omitted, assuming that the description of the configuration on the first protection region 8 side applies. The configuration on the second protection region 9 side can be obtained by replacing "first protection region 8" with "second protection region 9" and "first protection transistor 40" with "second protection transistor 50" in the following description.

[0181] In the attached drawings, in order to clarify that the configuration related to the first protection region 8 (first protection transistor 40) also applies to the configuration related to the second protection region 9 (second protection transistor 50), the symbol "9 (50)" related to the second protection region 9 (second protection transistor 50) is written alongside the symbol "8 (40)" related to the first protection region 8 (first protection transistor 40).

[0182] FIG. 15 is a plan view showing the first protection region 8 shown in FIG. 1. FIG. 16 is an enlarged plan view showing a main portion of the first protection region 8 shown in FIG. 15. FIG. 17 is an enlarged plan view showing a further main portion of the first protection region 8 shown in FIG. 15. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 16. FIG. 19 is a cross-sectional view taken along line XIX-XIX shown in FIG. 16. FIG. 20 is a cross-sectional view taken along line XX-XX shown in FIG. 16. FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 16. FIG. 22 is a cross-sectional view for comparing the configuration of the output region 6 side and the configuration of the first protection region 8 side.

[0183] 15 to 22, semiconductor device 1 includes second trench isolation structure 100 formed in first main surface 3 to define first protection region 8. Second trench isolation structure 100 may also be referred to as a "second region isolation structure." Second trench isolation structure 100 electrically isolates first protection region 8 from output region 6, control region 7, and second protection region 9 within chip 2. A source potential is applied to second trench isolation structure 100. Second trench isolation structure 100 is formed in a ring shape surrounding first protection region 8 in a plan view.

[0184] In this embodiment, the second trench isolation structure 100 is formed in a polygonal ring shape (a square ring shape in this embodiment) in plan view having four sides parallel to the periphery of the first main surface 3. The second trench isolation structure 100 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 with a part of the drift region 11 in between.

[0185] The second trench isolation structure 100 has a third width W3. The third width W3 is the width in a direction perpendicular to the extension direction of the second trench isolation structure 100. The third width W3 is preferably larger than the first interval I1 between the plurality of first trench gate structures 70. The third width W3 is preferably larger than the second width W2 of the first trench gate structures 70. It is particularly preferable that the third width W3 be approximately equal to the first width W1 of the first trench isolation structure 60. Of course, the third width W3 may be larger or smaller than the first width W1. Alternatively, the third width W3 may be approximately equal to the second width W2.

[0186] The third width W3 may be 0.4 μm or more and 2.5 μm or less. The third width W3 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The third width W3 is preferably 1.25 μm or more and 1.75 μm or less.

[0187] The second trench isolation structure 100 has a third depth D3. The third depth D3 is preferably greater than the second depth D2 of the first trench gate structure 70. It is particularly preferable that the third depth D3 be approximately equal to the first depth D1 of the first trench isolation structure 60. Of course, the third depth D3 may be greater than or smaller than the first depth D1. Alternatively, the third depth D3 may be approximately equal to the second depth D2.

[0188] The third depth D3 may be 1 μm or more and 6 μm or less. The third depth D3 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The third depth D3 is preferably 3 μm or more and 5 μm or less.

[0189] The second trench isolation structure 100 includes a second isolation trench 101, a second isolation insulating film 102, and a second isolation electrode 103. In other words, the second trench isolation structure 100 has a single electrode structure including a single electrode (second isolation electrode 103) embedded in the second isolation trench 101 with an insulator (second isolation insulating film 102) sandwiched therebetween.

[0190] The second isolation trench 101 is formed in the first main surface 3 and defines the wall surface of the second trench isolation structure 100. The second isolation insulating film 102 covers the wall surface of the second isolation trench 101. The second isolation insulating film 102 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0191] The second isolation insulating film 102 is thicker than the first upper insulating film 76. The thickness of the second isolation insulating film 102 is preferably approximately equal to the thickness of the first isolation insulating film 62. The second isolation electrode 103 is embedded in the second isolation trench 101 with the second isolation insulating film 102 sandwiched therebetween. The second isolation electrode 103 may contain conductive polysilicon.

[0192] The semiconductor device 1 includes a first protection transistor 40 formed on the first main surface 3 in the first protection region 8. The following components will be described as components of the semiconductor device 1, but they are also components of the first protection transistor 40.

[0193] Unlike the configuration on the output region 6 side, the semiconductor device 1 does not have a high-concentration drift region 64 in the surface layer portion of the drift region 11 in the first protection region 8. In other words, unlike the configuration on the output region 6 side, the drift region 11 in the first protection region 8 does not have a concentration gradient in which the impurity concentration increases from the bottom side toward the first main surface 3 side.

[0194] In other words, the drift region 11 of the first protection region 8 does not have a concentration gradient in which the impurity concentration increases in the thickness range between the bottom of the drift region 11 and the first trench gate structure 70. The drift region 11 of the first protection region 8 has an approximately constant n-type impurity concentration in the thickness direction.

[0195] The first protection region 8 is not a region that is always used, but a region that is used when the first overvoltage Vs1 (first overvoltage Vs1) occurs (is applied). Therefore, unlike the output region 6, the first protection region 8 is required to have a tolerance to overvoltage. In other words, the first protection region 8 is less required to have a low on-resistance and more required to have a high withstand voltage.

[0196] In the first protection region 8, if the drift region 11 is highly concentrated by the high-concentration drift region 64, undesirable electric field concentration due to overvoltage is caused, increasing the possibility of a decrease in breakdown voltage. Therefore, it is preferable that the first protection region 8 does not have the high-concentration drift region 64. Of course, the present disclosure does not exclude a configuration in which the first protection region 8 has the high-concentration drift region 64.

[0197] The semiconductor device 1 includes a p-type (second conductivity type) second body region 107 formed in the surface layer portion of the drift region 11 in the first protection region 8. The second body region 107 preferably has a p-type impurity concentration substantially equal to that of the first body region 67. The second body region 107 extends in a layered form along the first main surface 3 throughout the entire first protection region 8, and is connected to the wall surface of the second trench isolation structure 100.

[0198] That is, in this embodiment, the second body region 107 is not formed in a region outside the second trench isolation structure 100. The second body region 107 is formed shallower than the second trench isolation structure 100, and has a bottom located closer to the first main surface 3 than the bottom wall of the second trench isolation structure 100. The bottom of the second body region 107 is preferably located closer to the first main surface 3 than the intermediate portion of the depth range of the second trench isolation structure 100. The second body region 107 preferably has approximately the same thickness as the first body region 67.

[0199] The semiconductor device 1 includes a plurality of second trench gate structures 110 formed on the first main surface 3 in the first protection region 8. The number of the plurality of second trench gate structures 110 is less than the number of the plurality of first trench gate structures 70. Although not specifically illustrated, the number of the second trench gate structures 110 in the second protection region 9 may be different from the number of the second trench gate structures 110 in the first protection region 8.

[0200] The number of second trench gate structures 110 in the second protection region 9 may be greater than the number of second trench gate structures 110 in the first protection region 8. The number of second trench gate structures 110 in the second protection region 9 may be less than the number of second trench gate structures 110 in the first protection region 8. The number of second trench gate structures 110 in the second protection region 9 may be the same as the number of second trench gate structures 110 in the first protection region 8.

[0201] The second trench gate structures 110 are formed in the inner portion of the first protection region 8 at intervals from the second trench isolation structure 100. The second trench gate structures 110 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0202] That is, the multiple second trench gate structures 110 are arranged in stripes extending in the second direction Y. The lengths of the multiple second trench gate structures 110 are less than the lengths of the multiple first trench gate structures 70. The multiple second trench gate structures 110 have a first end on one side in the longitudinal direction (second direction Y) and a second end on the other side in the longitudinal direction (second direction Y).

[0203] The plurality of second trench gate structures 110 penetrate the second body region 107 in a cross-sectional view and are located within the drift region 11. The plurality of second trench gate structures 110 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3, and face the drain region 10 with a part of the drift region 11 interposed therebetween.

[0204] The plurality of second trench gate structures 110 have a fourth width W4 (see also FIG. 22 ). The fourth width W4 is the width in a direction perpendicular to the extension direction of the second trench gate structures 110 (i.e., the first direction X). The fourth width W4 is preferably less than the first width W1 of the first trench isolation structure 60. The fourth width W4 is preferably less than the third width W3 of the second trench isolation structure 100.

[0205] The fourth width W4 is preferably greater than the first spacing I1 between the plurality of first trench gate structures 70. The fourth width W4 is preferably approximately equal to the second width W2 of the first trench gate structures 70. Of course, the fourth width W4 may be greater than the second width W2 or less than the second width W2.

[0206] The fourth width W4 may be 0.4 μm or more and 2 μm or less. The fourth width W4 may have a value belonging to any one of the ranges of 0.4 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The fourth width W4 is preferably 0.8 μm or more and 1.2 μm or less.

[0207] The second trench gate structures 110 are arranged at second intervals I2 in the first direction X (see also FIG. 22 ). The second intervals I2 are also the mesa widths (second mesa widths) of mesa portions (second mesa portions) defined in regions between two adjacent second trench gate structures 110.

[0208] The second interval I2 is preferably equal to or greater than the second width W2 of the first trench gate structure 70. It is particularly preferable that the second interval I2 be greater than the second width W2. The second interval I2 is preferably equal to or greater than the fourth width W4 of the second trench gate structure 110. It is particularly preferable that the second interval I2 be greater than the fourth width W4.

[0209] The second interval I2 is preferably equal to or less than the first width W1 of the first trench isolation structure 60 (less than the first width W1). The second interval I2 is preferably less than the first width W1. The second interval I2 is preferably equal to or less than the third width W3 of the second trench isolation structure 100 (less than the third width W3). The second interval I2 is preferably less than the third width W3.

[0210] The second interval I2 is preferably equal to or greater than the first interval I1 between the plurality of first trench gate structures 70. It is particularly preferable that the second interval I2 be greater than the first interval I1. It is preferable that the second interval I2 be equal to or greater than 1.5 times and equal to or less than 4 times the first interval I1. It is particularly preferable that the second interval I2 be equal to or less than 2.5 times the first interval I1.

[0211] The second interval I2 may be 0.8 μm or more and 1.6 μm or less. The second interval I2 may have a value belonging to any one of the ranges of 0.8 μm or more and 1 μm or less, 1 μm or more and 1.2 μm or less, 1.2 μm or more and 1.4 μm or less, and 1.4 μm or more and 1.6 μm. The second interval I2 is preferably 1 μm or more and 1.4 μm or less.

[0212] The second trench gate structure 110 has a fourth depth D4 (see also FIG. 22 ). The fourth depth D4 may be approximately equal to the first depth D1 of the first trench isolation structure 60. Preferably, the fourth depth D4 is less than the first depth D1. The fourth depth D4 may be approximately equal to the third depth D3 of the second trench isolation structure 100. Preferably, the fourth depth D4 is less than the third depth D3. It is particularly preferred that the fourth depth D4 be approximately equal to the second depth D2 of the first trench gate structure 70. Of course, the fourth depth D4 may be greater than or less than the second depth D2.

[0213] The fourth depth D4 may be 1 μm or more and 6 μm or less. The fourth depth D4 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, and 5 μm or more and 6 μm or less. The fourth depth D4 is preferably 2.5 μm or more and 4.5 μm or less.

[0214] Although not specifically shown in the drawings, the fourth width W4 in the second protection region 9 may be different from the fourth width W4 in the first protection region 8. The fourth width W4 in the second protection region 9 may be larger than the fourth width W4 in the first protection region 8. The fourth width W4 in the second protection region 9 may be smaller than the fourth width W4 in the first protection region 8. Of course, the fourth width W4 in the second protection region 9 may be approximately equal to the fourth width W4 in the first protection region 8.

[0215] Furthermore, the second interval I2 in the second protection region 9 may be different from the second interval I2 in the first protection region 8. The second interval I2 in the second protection region 9 may be larger than the second interval I2 in the first protection region 8. The second interval I2 in the second protection region 9 may be smaller than the second interval I2 in the first protection region 8. Of course, the second interval I2 in the second protection region 9 may be approximately equal to the second interval I2 in the first protection region 8.

[0216] Furthermore, the fourth depth D4 in the second protection region 9 may be different from the fourth depth D4 in the first protection region 8. The fourth depth D4 in the second protection region 9 may be greater than the fourth depth D4 in the first protection region 8. The fourth depth D4 in the second protection region 9 may be smaller than the fourth depth D4 in the first protection region 8. Of course, the fourth depth D4 in the second protection region 9 may be approximately equal to the fourth depth D4 in the first protection region 8.

[0217] The following describes the internal configuration of one second trench gate structure 110. The second trench gate structure 110 includes a second gate trench 111, a second insulating film 112, a second upper electrode 113, a second lower electrode 114, and a second intermediate insulating film 115. In other words, the second trench gate structure 110 has a multi-electrode structure including multiple electrodes (the second upper electrode 113 and the second lower electrode 114) embedded in the second gate trench 111 in the vertical direction with an insulator (the second insulating film 112 and the second intermediate insulating film 115) sandwiched therebetween.

[0218] The second gate trench 111 is formed in the first main surface 3 and defines a wall surface of the second trench gate structure 110. The second insulating film 112 covers the wall surface of the second gate trench 111. The second insulating film 112 includes a second upper insulating film 116 and a second lower insulating film 117. The second upper insulating film 116 covers the wall surface of the second gate trench 111 on the opening side relative to the bottom of the second body region 107. The second upper insulating film 116 partially covers the wall surface of the second gate trench 111 on the bottom wall side relative to the bottom of the second body region 107.

[0219] The second upper insulating film 116 is thinner than the first isolation insulating film 62. The thickness of the second upper insulating film 116 is smaller than the thickness of the second isolation insulating film 102. The thickness of the second upper insulating film 116 is preferably approximately equal to the thickness of the first upper insulating film 76. The second upper insulating film 116 is formed as a gate insulating film. The second upper insulating film 116 may include a silicon oxide film. The second upper insulating film 116 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0220] The second lower insulating film 117 covers the wall surface of the second gate trench 111 on the bottom wall side relative to the bottom of the second body region 107. The second lower insulating film 117 is thicker than the second upper insulating film 116. It is preferable that the thickness of the second lower insulating film 117 is approximately equal to the thickness of the first lower insulating film 77.

[0221] The thickness of the second lower insulating film 117 may be approximately equal to the thickness of the first isolation insulating film 62 (second isolation insulating film 102). The second lower insulating film 117 may include a silicon oxide film. The second lower insulating film 117 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0222] The second upper electrode 113 is embedded in the opening side of the second gate trench 111 with the second insulating film 112 sandwiched therebetween. Specifically, the second upper electrode 113 is embedded in the opening side of the second gate trench 111 with the second upper insulating film 116 sandwiched therebetween, and faces the second body region 107 and the drift region 11 with the second upper insulating film 116 sandwiched therebetween. The second upper electrode 113 may include conductive polysilicon.

[0223] The second lower electrode 114 is embedded in the bottom wall of the second gate trench 111 with the second insulating film 112 interposed therebetween. Specifically, the second lower electrode 114 is embedded in the bottom wall of the second gate trench 111 with the second lower insulating film 117 interposed therebetween, and faces the drift region 11 with the second lower insulating film 117 interposed therebetween.

[0224] The second lower electrode 114 has an upper end portion that protrudes from the second lower insulating film 117 toward the second upper electrode 113 so as to engage with the bottom of the second upper electrode 113. The upper end portion of the second lower electrode 114 faces the second upper insulating film 116 across the lower end portion of the second upper electrode 113 in the lateral direction along the first main surface 3. The second lower electrode 114 may include conductive polysilicon.

[0225] The second intermediate insulating film 115 is interposed between the second upper electrode 113 and the second lower electrode 114, and electrically insulates the second upper electrode 113 and the second lower electrode 114 within the second gate trench 111. The second intermediate insulating film 115 is continuous with the second upper insulating film 116 and the second lower insulating film 117.

[0226] The second intermediate insulating film 115 is thinner than the second lower insulating film 117. The thickness of the second intermediate insulating film 115 is preferably approximately equal to the thickness of the first intermediate insulating film 75. The second intermediate insulating film 115 may include a silicon oxide film. The second intermediate insulating film 115 preferably includes a silicon oxide film made of an oxide of the second lower electrode 114.

[0227] The semiconductor device 1 includes a plurality of second channel cells 118 formed on both sides of each second trench gate structure 110 as control targets of each second trench gate structure 110. In other words, the two second channel cells 118 arranged on both sides of one second trench gate structure 110 are controlled by that one second trench gate structure 110.

[0228] The second channel cells 118 are formed in a region along an inner portion of the second trench gate structure 110 at intervals from both ends of the second trench gate structure 110 in the longitudinal direction (second direction Y). The second channel cells 118 expose the second body region 107 from a region of the first main surface 3 that is sandwiched between both ends of the second trench gate structures 110. The second channel cells 118 face the drift region 11 with a part of the second body region 107 sandwiched between them in the thickness direction.

[0229] Each second channel cell 118 includes a plurality of n-type second source regions 119 and a plurality of p-type second contact regions 120. For clarity, the second source regions 119 are hatched in Figure 16. The second contact regions 120 may also be referred to as "second back gate regions."

[0230] Each second source region 119 has a higher n-type impurity concentration than the drift region 11. Each second source region 119 may have a higher n-type impurity concentration than the high-concentration drift region 64. The n-type impurity concentration of each second source region 119 is preferably approximately equal to the n-type impurity concentration of each first source region 79. The n-type impurity concentration of each second source region 119 is preferably 1×10 １８ cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0231] The second source regions 119 are arranged at intervals along the second trench gate structures 110. The second source regions 119 are formed at intervals from the bottom of the second body region 107 toward the first main surface 3, and face the second upper electrode 113 with the second insulating film 112 (second upper insulating film 116) interposed therebetween. Each second source region 119 has a planar area larger than the planar area of ​​each first source region 79.

[0232] Each second contact region 120 has a higher p-type impurity concentration than the second body region 107. The p-type impurity concentration of each second contact region 120 is preferably approximately equal to the n-type impurity concentration of each first contact region 80. The p-type impurity concentration of each second contact region 120 is preferably 1×10１８ cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0233] The second contact regions 120 are arranged alternately with the second source regions 119 along each second trench gate structure 110. The second contact regions 120 are formed at intervals from the bottom of the second body region 107 toward the first main surface 3, and face the second upper electrode 113 with the second insulating film 112 (second upper insulating film 116) interposed therebetween. Each second contact region 120 has a planar area larger than the planar area of ​​each first contact region 80.

[0234] With respect to two second channel cells 118 formed on both sides of one second trench gate structure 110, the plurality of second source regions 119 in one second channel cell 118 face the plurality of second source regions 119 in the other second channel cell 118 across the second trench gate structure 110. Furthermore, the plurality of second contact regions 120 in one second channel cell 118 face the plurality of second contact regions 120 in the other second channel cell 118 across the second trench gate structure 110.

[0235] Of course, the plurality of second source regions 119 in one second channel cell 118 may face the plurality of second contact regions 120 in the other second channel cell 118 across the second trench gate structure 110. Also, the plurality of second contact regions 120 in one second channel cell 118 may face the plurality of second source regions 119 in the other second channel cell 118 across the second trench gate structure 110.

[0236] With respect to two second channel cells 118 interposed between two second trench gate structures 110, the plurality of second source regions 119 in one second channel cell 118 are connected in the first direction X to the plurality of second contact regions 120 in the other second channel cell 118. Also, the plurality of second contact regions 120 in one second channel cell 118 are connected in the first direction X to the plurality of second source regions 119 in the other second channel cell 118.

[0237] Of course, the plurality of second source regions 119 in one second channel cell 118 may be connected in the first direction X to the plurality of second source regions 119 in the other second channel cell 118. Also, the plurality of second contact regions 120 in one second channel cell 118 may be connected in the first direction X to the plurality of second contact regions 120 in the other second channel cell 118.

[0238] Of the two second channel cells 118 formed on both sides of the outermost second trench gate structure 110, the second channel cell 118 located on the inner side faces the drift region 11 across a part of the second body region 107 in the thickness direction. On the other hand, the second channel cell 118 located on the outer side does not include the second source region 119, but includes only the second contact region 120. This suppresses the formation of a current path in the region between the second trench isolation structure 100 and the outermost second trench gate structure 110.

[0239] The semiconductor device 1 includes a pair of second trench connection structures 130 that connect both ends of a plurality (in this embodiment, all) of the second trench gate structures 110 in the first protection region 8. The second trench connection structure 130 on one side connects first ends of the plurality (in this embodiment, all) of the second trench gate structures 110 together in an arch shape in plan view. The second trench connection structure 130 on the other side connects second ends of the plurality (in this embodiment, all) of the second trench gate structures 110 together in an arch shape in plan view.

[0240] Specifically, the second trench connection structure 130 on one side has a first portion extending in a first direction X and a plurality of second portions extending in a second direction Y. The first portion faces first ends of the plurality of second trench gate structures 110 in a plan view. The plurality of second portions extend from the first portion toward the plurality of first ends so as to be connected to the plurality of first ends.

[0241] The second trench connection structure 130 on the other side has a first portion extending in the first direction X and a plurality of second portions extending in the second direction Y. The first portion faces the second ends of the plurality of second trench gate structures 110 in a plan view. The plurality of second portions extend from the first portion toward the plurality of second ends so as to be connected to the plurality of second ends. The plurality of second trench connection structures 130 and the plurality of second trench gate structures 110 form a ladder-shaped trench structure in the first protection region 8.

[0242] The plurality of second trench connection structures 130 are connected to the plurality of second trench gate structures 110 at intervals from the second trench isolation structure 100. The plurality of second trench connection structures 130 are formed at intervals from the bottom of the drift region 11 toward the first main surface 3, and face the drain region 10 with a part of the drift region 11 interposed therebetween.

[0243] The plurality of second trench connection structures 130 may be formed with approximately the same width and depth as the second trench gate structures 110. Of course, the first and second portions of the second trench connection structures 130 may have different widths. For example, the second portions of the second trench connection structures 130 may be formed narrower than the first portions of the second trench connection structures 130.

[0244] In this case, the first portion may have a width approximately equal to the width of the second trench isolation structure 100, and the second portion may have a width approximately equal to the width of the second trench gate structure 110. Furthermore, in this case, the first portion may have a depth approximately equal to the depth of the second trench isolation structure 100, and the second portion may have a depth approximately equal to the depth of the second trench gate structure 110.

[0245] The first portion of the second trench connection structure 130 may have a width and depth that are approximately equal to the width and depth of the first portion of the first trench connection structure 90. The second portion of the second trench connection structure 130 may have a width and depth that are approximately equal to the width and depth of the second portion of the first trench connection structure 90.

[0246] The second trench connection structure 130 on the other side has the same structure as the second trench connection structure 130 on one side, except that it is connected to the second end of the second trench gate structure 110. Below, the configuration of the second trench connection structure 130 on one side will be described, and a description of the configuration of the second trench connection structure 130 on the other side will be omitted.

[0247] The second trench connection structure 130 includes a second connection trench 131, a second connection insulating film 132, and a second connection electrode 133. The second connection trench 131 is formed in the first main surface 3 and defines the wall surface of the second trench connection structure 130. The second connection trench 131 is connected to the plurality of second gate trenches 111.

[0248] The second connection insulating film 132 covers the wall surface of the second connection trench 131. The second connection insulating film 132 is connected to the second upper insulating film 116, the second lower insulating film 117, and the second intermediate insulating film 115 at the communicating portion between the second connection trench 131 and the second gate trench 111.

[0249] The second connection insulating film 132 is thicker than the second upper insulating film 116. The thickness of the second connection insulating film 132 may be approximately equal to the thickness of the second lower insulating film 117. The thickness of the second connection insulating film 132 may be approximately equal to the thickness of the first connection insulating film 92. The second connection insulating film 132 may include a silicon oxide film. The second connection insulating film 132 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0250] The second connection electrode 133 is embedded in the second connection trench 131 with the second connection insulating film 132 interposed therebetween, and faces the drift region 11 and the second body region 107 with the second connection insulating film 132 interposed therebetween.

[0251] The second connection electrode 133 is connected to the second lower electrode 114 at the communicating portion between the second connection trench 131 and the second gate trench 111, and is electrically insulated from the second upper electrode 113 by the second intermediate insulating film 115. The second connection electrode 133 is formed by an extension portion of the second lower electrode 114 that is extended from inside the second gate trench 111 into the second connection trench 131. The second connection electrode 133 may include conductive polysilicon.

[0252] The semiconductor device 1 includes a second main surface insulating film 134 that selectively covers the first main surface 3 in the first protection region 8. The second main surface insulating film 134 is connected to the second insulating film 112 (second upper insulating film 116) and the second connecting insulating film 132, and exposes the second isolated electrode 103, the second upper electrode 113, and the second connecting electrode 133.

[0253] The second main surface insulating film 134 is thinner than the second isolation insulating film 102. The second main surface insulating film 134 is thinner than the second lower insulating film 117. The second main surface insulating film 134 is thinner than the second connection insulating film 132. The second main surface insulating film 134 may have a thickness approximately equal to that of the second upper insulating film 116. The second main surface insulating film 134 preferably has a thickness approximately equal to that of the first main surface insulating film 94. The second main surface insulating film 134 may include a silicon oxide film. The second main surface insulating film 134 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0254] The semiconductor device 1 includes a second field insulating film 135 that selectively covers the first main surface 3 inside and outside the first protection region 8. The second field insulating film 135 is thicker than the second main surface insulating film 134. The second field insulating film 135 is thicker than the second upper insulating film 116. The second field insulating film 135 may have a thickness approximately equal to that of the second isolation insulating film 102.

[0255] The second field insulating film 135 preferably has a thickness substantially equal to that of the first field insulating film 95. The second field insulating film 135 may include a silicon oxide film. The second field insulating film 135 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.

[0256] The second field insulating film 135 covers the first main surface 3 along the inner wall of the second trench isolation structure 100 within the first protection region 8, and is connected to the second isolation insulating film 102, the second connection insulating film 132, and the second main surface insulating film 134. The second field insulating film 135 covers the first main surface 3 along the outer wall of the second trench isolation structure 100 outside the first protection region 8, and is connected to the second isolation insulating film 102.

[0257] The interlayer insulating layer 12 described above covers the second trench isolation structure 100 , the second trench gate structure 110 , the second trench connection structure 130 , the second main surface insulating film 134 and the second field insulating film 135 in the first protection region 8 .

[0258] The semiconductor device 1 includes a second gate wiring 136 disposed in the interlayer insulating layer 12. The second gate wiring 136 is electrically connected to a connection target and all of the second trench gate structures 110.

[0259] In the case of the first protection region 8, the second gate wiring 136 is electrically connected to the clamp circuit 41 as a connection target (see FIG. 5 ). That is, the plurality of second trench gate structures 110 are electrically connected to the drain terminal 15 via the second gate wiring 136 and the clamp circuit 41. The first protection transistor 40 is configured such that a bias voltage resulting from the first overvoltage Vs1 is applied to the second trench gate structure 110 via the second gate wiring 136, and a gate signal from the control circuit 23 (gate control circuit 24) or the like is not input to the second trench gate structure 110.

[0260] In the case of the second protection region 9, the second gate wiring 136 is electrically connected to the input terminal 14b as a connection target (see FIG. 6 ). That is, the plurality of second trench gate structures 110 are electrically connected to the input terminal 14b via the second gate wiring 136. The second protection transistor 50 is configured such that a bias voltage resulting from the second overvoltage Vs2 is applied to the second trench gate structure 110 via the second gate wiring 136, and a gate signal from the control circuit 23 (gate control circuit 24) or the like is not input to the second trench gate structure 110.

[0261] The second gate wiring 136 is electrically connected to the plurality of second trench gate structures 110 through a plurality of via electrodes 97 arranged in the interlayer insulating layer 12. Specifically, the second gate wiring 136 is electrically connected to the plurality of second upper electrodes 113 and the plurality of second connection electrodes 133 through the plurality of via electrodes 97.

[0262] That is, the second upper electrode 113 and the second lower electrode 114 are simultaneously turned on and off by the same bias voltage. This suppresses the voltage drop between the second upper electrode 113 and the second lower electrode 114, and suppresses undesired electric field concentration. As a result, a decrease in breakdown voltage caused by the electric field concentration is suppressed.

[0263] The semiconductor device 1 includes a second source wiring 138 disposed in the interlayer insulating layer 12. The second source wiring 138 is electrically connected to a connection target, the second trench isolation structure 100, and a plurality of second channel cells 118.

[0264] In the case of the first protection region 8, the second source wiring 138 is electrically connected to the power supply reverse connection protection circuit 31 (ground terminal 14a) as a connection target (see FIG. 5). In the case of the second protection region 9, the second source wiring 138 is electrically connected to the input terminal 14b as a connection target (see FIG. 6). In the case of the second protection region 9, the second source wiring 138 may be formed integrally with the second gate wiring 136 as the same wiring.

[0265] The second source wiring 138 is electrically connected to the second trench isolation structure 100 and the plurality of second channel cells 118 through a plurality of via electrodes 97. The via electrode 97 for each second channel cell 118 is arranged so as to straddle two adjacent second channel cells 118, and is formed in a strip shape extending along each second channel cell 118 in plan view.

[0266] FIG. 23 is a first graph showing the results of a known TLP (Transmission Line Pulse) test. In FIG. 23, the vertical axis represents the TLP breakdown current, and the horizontal axis represents the second interval I2 between the second trench gate structures 110. In the TLP test, an overvoltage (surge voltage) strong enough to cause breakdown was applied to the first protection transistor 40 (second protection transistor 50) in a pulsed manner, and the breakdown current was obtained. The graph shows the TLP breakdown current per unit area. The unit area is an area including two adjacent second trench gate structures 110.

[0267] 23 shows first to fourth plot points P1 to P4 indicated by black circles and fifth to sixth plot points P5 to P6 indicated by white circles. The first to fourth plot points P1 to P4 show characteristics when the fourth width W4 of the second trench gate structure 110 is fixed at 1 μm and the second interval I2 of the second trench gate structure 110 is changed. The second interval I2 is 0.6 μm, 0.7 μm, 0.8 μm, and 1.2 μm for the first to fourth plot points P1 to P4, respectively.

[0268] The fifth and sixth plot points P5 and P6 show the characteristics when the fourth width W4 of the second trench gate structure 110 is fixed at 1.2 μm and the second interval I2 of the second trench gate structure 110 is changed. The second interval I2 is 0.6 μm and 1.2 μm for the fifth and sixth plot points P5 and P6, respectively.

[0269] With reference to the first to sixth plot points P1 to P6, it was found that the TLP breakdown current increased as the second interval I2 increased and decreased as the second interval I2 decreased. The TLP breakdown current at the fifth plot point P5 was approximately equal to the TLP breakdown current at the first plot point P1, and the TLP breakdown current at the sixth plot point P6 was approximately equal to the TLP breakdown current at the fourth plot point P4.

[0270] When the second interval I2 is reduced, the carrier density between the second trench gate structures 110 can be increased, thereby reducing the on-resistance. However, when an overvoltage is applied, an overcurrent flows between the second trench gate structures 110, which makes it easier for the temperature to rise in the regions between the second trench gate structures 110. As a result, the breakdown current decreases.

[0271] Therefore, it is preferable that the first interval I1 be set to a relatively small value on the output transistor 20 side in order to reduce the on-resistance (power consumption).On the other hand, it is preferable that the second interval I2 be set to a value larger than the first interval I1 on the first protection transistor 40 (second protection transistor 50) side in order to suppress a decrease in breakdown resistance.

[0272] In such a configuration, the on-resistance of the first protection transistor 40 (second protection transistor 50) per unit area is higher than the on-resistance of the output transistor 20. On the other hand, the breakdown current of the first protection transistor 40 (second protection transistor 50) per unit area is higher than the breakdown current of the output transistor 20. This is because the temperature rise in the region between the multiple second trench gate structures 110 is suppressed, improving the breakdown resistance.

[0273] 23, it was found that the first interval I1 of the first trench gate structure 70 is preferably set to 0.8 μm or less (0.4 μm or more and 0.8 μm or less), and the second interval I2 of the second trench gate structure 110 is preferably set to 0.8 μm or more (0.8 μm or more and 1.6 μm or less).

[0274] 24 is a second graph showing the results of the TLP test. In this graph, the horizontal axis of FIG. 23 is changed to the fourth width W4 of the second trench gate structure 110. Here, the TLP breakdown current was examined when the second interval I2 of the second trench gate structure 110 was fixed and the fourth width W4 of the second trench gate structure 110 was changed.

[0275] That is, here, the first plot point P1 (fourth width W4 = 1 μm) and the fifth plot point P5 (fourth width W4 = 1.2 μm), both of which have a second interval I2 of 0.6 μm, are compared, and the fourth plot point P4 (fourth width W4 = 1 μm) and the sixth plot point P6 (fourth width W4 = 1.2 μm), both of which have a second interval I2 of 1.2 μm, are compared.

[0276] Comparing the first plot point P1 and the fifth plot point P5, the TLP breakdown current at the fifth plot point P5 was approximately equal to the TLP breakdown current at the first plot point P1. Comparing the fourth plot point P4 and the sixth plot point P6, the TLP breakdown current at the sixth plot point P6 was approximately equal to the TLP breakdown current at the fourth plot point P4.

[0277] From this result, it was found that the TLP breakdown current depends on the second interval I2 of the second trench gate structure 110, but is almost independent of the fourth width W4 of the second trench gate structure 110. In other words, even if the fourth width W4 is increased or decreased, the TLP breakdown current does not increase or decrease significantly. From this, it was found that the fourth width W4 of the second trench gate structure 110 can be set to a value approximately equal to the second width W2 of the first trench gate structure 70.

[0278] According to this configuration, the first trench gate structure 70 and the second trench gate structure 110 can be fabricated simultaneously. Furthermore, since the second width W2 and the fourth width W4 are approximately equal, the etching amount on the first trench gate structure 70 side relative to the chip 2 (first main surface 3) and the etching amount on the second trench gate structure 110 side relative to the chip 2 (first main surface 3) are approximately equal. Therefore, the second trench gate structure 110 can be formed having a fourth depth D4 that is approximately equal to the second depth D2 of the first trench gate structure 70.

[0279] That is, even if a second trench gate structure 110 having a configuration similar to that of the first trench gate structure 70 is formed in the first protection region 8, a relatively high breakdown resistance can be achieved. In other words, the breakdown resistance on the first protection region 8 side can be adjusted based on the configuration on the output region 6 side. Furthermore, since the same process conditions as those on the output region 6 side can be applied to the first protection region 8 (second protection region 9), management of the manufacturing process becomes easier.

[0280] FIG. 25 is a graph showing test results for gate threshold voltage. The vertical axis of FIG. 25 represents the drain-source current Ids [A], and the horizontal axis represents the gate voltage Vgs [V]. The "E" on the vertical axis represents the exponentiation of 10. FIG. 25 shows a first characteristic S1 and a second characteristic S2. The first characteristic S1 represents the characteristic of the output transistor 20. The second characteristic S2 represents the characteristic of the first protection transistor 40.

[0281] With reference to the first characteristic S1 and the second characteristic S2, the first gate threshold voltage Vth1 of the output transistor 20 was 1.46 V, and the second gate threshold voltage Vth2 of the first protection transistor 40 was 1.87 V. The second gate threshold voltage Vth2 is higher than the first gate threshold voltage Vth1 by 0.4 V or more. This indicates that the output transistor 20 has better switching response than the first protection transistor 40.

[0282] Here, the first gate threshold voltage Vth1 and the second gate threshold voltage Vth2 are defined by the voltage value at which the drain-source current Ids is 1×10 A. The first gate threshold voltage Vth1 may be defined by the voltage value at which the slope of the tangent to the rising curve of the first characteristic S1 is maximum. Similarly, the second gate threshold voltage Vth2 may be defined by the voltage value at which the slope of the tangent to the rising curve of the second characteristic S2 is maximum.

[0283] The difference (Vth1-Vth2) between the second gate threshold voltage Vth2 and the first gate threshold voltage Vth1 is preferably 0.1 V or more and 1 V or less. The difference (Vth1-Vth2) is particularly preferably 0.3 V or more and 0.7 V or less.

[0284] From the above results, it was found that the first protection transistor 40 has a second gate threshold voltage Vth2 that is higher than the first gate threshold voltage Vth1 of the output transistor 20. This is because the first protection transistor 40 has an on-resistance that is higher than the on-resistance of the output transistor 20.

[0285] As described above, the semiconductor device 1 includes the chip 2, the output region 6, the first protection region 8, the output transistor 20, and the first overvoltage protection circuit 39 (protection circuit). The chip 2 has a first main surface 3. The output region 6 is provided on the first main surface 3. The first protection region 8 is provided on the first main surface 3. The output transistor 20 is formed in the output region 6. The output transistor 20 includes a plurality of first trench gate structures 70 formed on the first main surface 3 with a first interval I1 between them.

[0286] The first overvoltage protection circuit 39 includes a first protection transistor 40 formed in the first protection region 8. The first protection transistor 40 includes a plurality of second trench gate structures 110 formed on the first main surface 3 at second intervals I2 that are larger than the first interval I1. The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 (see FIG. 5 ). This configuration makes it possible to provide a semiconductor device 1 that can achieve overvoltage protection using a novel layout.

[0287] From another perspective, the semiconductor device includes a chip 2, an output region 6, a second protection region 9, an output transistor 20, and a second overvoltage protection circuit 49 (protection circuit). The chip 2 has a first main surface 3. The output region 6 is provided on the first main surface 3. The second protection region 9 is provided on the first main surface 3. The output transistor 20 is formed in the output region 6. The output transistor 20 includes a plurality of first trench gate structures 70 formed on the first main surface 3 with a first interval I1 between them.

[0288] The second overvoltage protection circuit 49 includes a second protection transistor 50 formed in the second protection region 9. The second protection transistor 50 includes a plurality of second trench gate structures 110 formed on the first main surface 3 at second intervals I2 that are larger than the first interval I1. The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 (see FIG. 6 ). This configuration makes it possible to provide a semiconductor device 1 that can achieve overvoltage protection using a novel layout.

[0289] From another perspective, the semiconductor device 1 includes a chip 2, an output region 6, a first protection region 8, an n-type drift region 11, an n-type high-concentration drift region 64, an output transistor 20, and a first overvoltage protection circuit 39 (protection circuit). The chip 2 has a first main surface 3. The output region 6 is provided on the first main surface 3. The first protection region 8 is provided on the first main surface 3.

[0290] The drift region 11 is formed in a surface layer portion of the first main surface 3 in both the output region 6 and the first protection region 8. The high-concentration drift region 64 is formed in a surface layer portion of the drift region 11 in the output region 6, and has a higher impurity concentration than the drift region 11. The output transistor 20 is formed in the output region 6. The output transistor 20 has a first trench gate structure 70 formed in the first main surface 3 so as to be located within the high-concentration drift region 64.

[0291] The first overvoltage protection circuit 39 includes a first protection transistor 40 formed in the first protection region 8. The first protection transistor 40 includes a second trench gate structure 110 formed on the first main surface 3 so as to be positioned within the drift region 11. The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 (see FIG. 5 ). This configuration makes it possible to provide a semiconductor device 1 that can achieve overvoltage protection using a novel layout. It is preferable that the high-concentration drift region 64 is not formed in the first protection region 8.

[0292] From another perspective, the semiconductor device 1 includes a chip 2, an output region 6, a second protection region 9, an n-type drift region 11, an n-type high-concentration drift region 64, an output transistor 20, and a second overvoltage protection circuit 49 (protection circuit). The chip 2 has a first main surface 3. The output region 6 is provided on the first main surface 3. The first protection region 8 is provided on the first main surface 3.

[0293] The drift region 11 is formed in a surface layer portion of the first main surface 3 in both the output region 6 and the second protection region 9. The high-concentration drift region 64 is formed in a surface layer portion of the drift region 11 in the output region 6, and has a higher impurity concentration than the drift region 11. The output transistor 20 is formed in the output region 6. The output transistor 20 has a first trench gate structure 70 formed in the first main surface 3 so as to be located within the high-concentration drift region 64.

[0294] The second overvoltage protection circuit 49 includes a second protection transistor 50 formed in the second protection region 9. The second protection transistor 50 includes a second trench gate structure 110 formed on the first main surface 3 so as to be positioned within the drift region 11. The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 (see FIG. 6 ). This configuration makes it possible to provide a semiconductor device 1 that can achieve overvoltage protection using a novel layout. It is preferable that the high-concentration drift region 64 is not formed in the second protection region 9.

[0295] From another perspective, the semiconductor device 1 includes a chip 2, a ground terminal 14a (first terminal), a drain terminal 15 (second terminal), and a first overvoltage protection circuit 39 (protection circuit) (see FIG. 5 ). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The ground terminal 14a is disposed on the first main surface 3. The drain terminal 15 is disposed on the second main surface 4.

[0296] The first overvoltage protection circuit 39 includes a first protection transistor 40 formed on the first main surface 3 so as to be electrically interposed between the ground terminal 14 a and the drain terminal 15. The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 that occurs between the ground terminal 14 a and the drain terminal 15 (see FIG. 5 ).

[0297] In this configuration, the first protection transistor 40 includes a plurality of second trench gate structures 110 each having a second upper electrode 113 and a second lower electrode 114 vertically embedded in a second gate trench 111 formed in the first main surface 3 with an insulator sandwiched therebetween (see FIG. 18 ). This configuration makes it possible to provide a semiconductor device 1 that can achieve overvoltage protection with a novel layout.

[0298] From another perspective, the semiconductor device 1 includes a chip 2, an input terminal 14b (first terminal), a drain terminal 15 (second terminal), and a second overvoltage protection circuit 49 (protection circuit) (see FIG. 6 ). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The input terminal 14b is disposed on the first main surface 3. The drain terminal 15 is disposed on the second main surface 4.

[0299] The second overvoltage protection circuit 49 includes a second protection transistor 50 formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15. The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 generated between the input terminal 14b and the drain terminal 15 (see FIG. 6 ).

[0300] In this configuration, the second protection transistor 50 includes a plurality of second trench gate structures 110 each having a second upper electrode 113 and a second lower electrode 114 vertically embedded in a second gate trench 111 formed in the first main surface 3 with an insulator sandwiched therebetween (see FIG. 18 ). This configuration makes it possible to provide a semiconductor device 1 that can achieve overvoltage protection with a novel layout.

[0301] From another perspective, the semiconductor device 1 includes a chip 2, a ground terminal 14a (first terminal), an input terminal 14b (second terminal), a drain terminal 15 (third terminal), a first overvoltage protection circuit 39 (first protection circuit), and a second overvoltage protection circuit 49 (second protection circuit) (see FIGS. 5 and 6 ). The chip 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The ground terminal 14a is disposed on the first main surface 3. The input terminal 14b is disposed on the first main surface 3. The drain terminal 15 is disposed on the second main surface 4.

[0302] The first overvoltage protection circuit 39 includes a first protection transistor 40 formed on the first main surface 3 so as to be electrically interposed between the ground terminal 14 a and the drain terminal 15. The first overvoltage protection circuit 39 is configured to form a discharge path for the first overvoltage Vs1 that occurs between the ground terminal 14 a and the drain terminal 15 (see FIG. 5 ).

[0303] In this configuration, the first protection transistor 40 includes a plurality of second trench gate structures 110 each having a second upper electrode 113 and a second lower electrode 114 buried in a vertical direction with an insulator sandwiched between them in a second gate trench 111 formed in the first main surface 3 (see FIG. 18).

[0304] The second overvoltage protection circuit 49 includes a second protection transistor 50 formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15. The second overvoltage protection circuit 49 is configured to form a discharge path for the second overvoltage Vs2 generated between the input terminal 14b and the drain terminal 15 (see FIG. 6 ).

[0305] In this configuration, the second protection transistor 50 includes a plurality of second trench gate structures 110 each having a second upper electrode 113 and a second lower electrode 114 vertically embedded in a second gate trench 111 formed in the first main surface 3 with an insulator sandwiched therebetween (see FIG. 18 ). This configuration makes it possible to provide a semiconductor device 1 that can achieve overvoltage protection with a novel layout.

[0306] The semiconductor device 1 preferably includes a first protection region 8 and a second protection region 9. The first protection region 8 is provided on the first main surface 3. The second protection region 9 is provided in a region of the first main surface 3 different from the first protection region 8. The first protection transistor 40 is formed in the first protection region 8. The second protection transistor 50 is formed in the second protection region 9.

[0307] The semiconductor device 1 preferably includes an output region 6 and an output transistor 20. The output region 6 is provided on the first main surface 3. The output transistor 20 is formed in the output region 6. The output transistor 20 includes a plurality of first trench gate structures 70, each having a first upper electrode 73 and a first lower electrode 74 buried in a first gate trench 71 formed in the first main surface 3 in the vertical direction with an insulator sandwiched therebetween (see FIG. 10 ).

[0308] The output transistor 20 is preferably a gate-split transistor with variable on-resistance. That is, the output transistor 20 preferably includes a plurality of system transistors 21 formed on the first main surface 3 so as to be individually controllable, and is configured to generate a single output current Io (output signal) by selectively controlling the plurality of system transistors 21. This configuration makes it possible to provide an output transistor 20 whose on-resistance (channel utilization rate) is variable by individually controlling the plurality of system transistors 21.

[0309] Below, modified examples (first modified example and second modified example) that are applied to either or both of the first protection area 8 and the second protection area 9 are shown. Below, an example in which the modified example is applied to the first protection area 8 is shown, but the modified example can also be applied to the second protection area 9. The modified example may be applied to both the first protection area 8 and the second protection area 9 at the same time. The modified example may be applied to the first protection area 8 but not to the second protection area 9. The modified example may be applied to the second protection area 9 but not to the first protection area 8.

[0310] 26 is a plan view showing a first modified example of the first protection region 8. In the above-described embodiment, an example has been shown in which a pair of second trench connection structures 130 that connect both ends of all the second trench gate structures 110 in an arch shape are formed in the first protection region 8. However, the plurality of second trench connection structures 130 may have a similar form to the plurality of first trench connection structures 90.

[0311] That is, a plurality of second trench connection structures 130 may be provided on the first end side of the second trench gate structure 110, and at the same time, a plurality of second trench connection structures 130 may be provided on the second end side of the second trench gate structure 110.

[0312] Each second trench connection structure 130 on the first end side connects the first ends of the multiple (two in this embodiment) second trench gate structures 110 in an arch shape in plan view. Each second trench connection structure 130 on the first end side has a first portion extending in the first direction X and multiple (two in this embodiment) second portions extending in the second direction Y. The first portion faces the first ends of the multiple second trench gate structures 110 in plan view. The multiple second portions extend from the first portion toward the multiple first ends so as to be connected to the multiple first ends.

[0313] Each second trench connection structure 130 on the second end side connects, in an arch shape, second ends of the multiple (two in this embodiment) second trench gate structures 110 to which each first trench connection structure 90 is connected in a plan view. Each second trench connection structure 130 on the second end side has a first portion extending in the first direction X and multiple (two in this embodiment) second portions extending in the second direction Y. The first portion faces the second ends of the multiple second trench gate structures 110 in a plan view. The multiple second portions extend from the first portion toward the multiple second ends so as to be connected to the multiple second ends.

[0314] As a result, the second trench connection structure 130 on the first end side and the second trench connection structure 130 on the second end side form a ring-shaped or ladder-shaped trench structure together with the corresponding second trench gate structures 110. Other than that, the configuration of the second trench connection structure 130 is the same as in the above-described embodiment.

[0315] 27 is a cross-sectional view showing a second modified example of the first protection region 8. In the above-described embodiment, it has been explained that a configuration in which the first protection region 8 has a high-concentration drift region 64 is not excluded. Here, a configuration in which the first protection region 8 has a high-concentration drift region 64 is shown. However, it should be noted that in such a configuration, the breakdown voltage of the first protection region 8 is increased by the second interval I2 between the multiple second trench gate structures 110, while the breakdown voltage of the first protection region 8 is reduced by the high-concentration drift region 64.

[0316] Therefore, this configuration is preferably applied when the on-resistance of the first protection region 8 is to be reduced when the withstand voltage of the first protection region 8 is sufficient. Hereinafter, the high-concentration drift region 64 on the first protection region 8 side will be referred to as a second high-concentration drift region 144 to distinguish it from the high-concentration drift region 64 on the output region 6 side.

[0317] The semiconductor device 1 includes an n-type second high-concentration drift region 144 formed in the surface layer portion of the drift region 11 in the first protection region 8. The second high-concentration drift region 144 has a higher n-type impurity concentration than the drift region 11. The n-type impurity concentration of the second high-concentration drift region 144 may be lower than the n-type impurity concentration of the drain region 10.

[0318] The second heavily doped drift region 144 preferably has an n-type impurity concentration that is approximately equal to that of the heavily doped drift region 64. The n-type impurity concentration of the second heavily doped drift region 144 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ The second high-concentration drift region 144 may be considered as a high-concentration portion of the drift region 11.

[0319] The second high-concentration drift region 144 forms a concentration gradient within the drift region 11 in which the n-type impurity concentration increases from the bottom side of the drift region 11 toward the first main surface 3. That is, the drift region 11 of the first protection region 8 has a concentration gradient formed by the second high-concentration drift region 144 such that the n-type impurity concentration increases from the bottom side toward the first main surface 3. In other words, the drift region 11 of the first protection region 8 has a concentration gradient in which the impurity concentration increases in the thickness range between the bottom of the drift region 11 and the first trench gate structure 70 on the output region 6 side.

[0320] The second heavily doped drift region 144 is formed in the inner part of the first protection region 8 at a distance from the second trench isolation structure 100. Therefore, the second heavily doped drift region 144 is surrounded by the drift region 11 in the first protection region 8 and is not in contact with the second trench isolation structure 100. The second heavily doped drift region 144 locally increases the n-type impurity concentration of the drift region 11 in the first protection region 8.

[0321] The second heavily doped drift region 144 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a part of the drift region 11. The second heavily doped drift region 144 has a bottom that is located closer to the bottom of the drift region 11 than the bottom wall of the second trench isolation structure 100. The bottom (deepest part) of the second heavily doped drift region 144 is formed at a depth position substantially equal to the bottom of the heavily doped drift region 64. The bottom of the second heavily doped drift region 144 meanders on one side and the other side in the thickness direction in a cross-sectional view.

[0322] Specifically, the bottom of the second high-concentration drift region 144 has a plurality of second bulging portions 145 and a plurality of second recessed portions 146 in a cross-sectional view. The plurality of second bulging portions 145 are portions that bulge in an arc shape toward the bottom side of the drift region 11. The plurality of second bulging portions 145 are formed continuously in the first direction X in a plan view, and each is formed in a strip shape extending in the second direction Y. Each second bulging portion 145 is formed wider in the first direction X than the second trench isolation structure 100. The width of each second bulging portion 145 in the first direction X is greater than the width of each bulging portion 65 on the output region 6 side in the first direction X.

[0323] The second recesses 146 are each formed in a strip shape extending in the second direction Y in a region between the second bulging portions 145. The second recesses 146 are portions where the shallow portions of the second bulging portions 145 are connected to each other, and are located on the first main surface 3 side of the deepest portions of the second bulging portions 145. Of course, the second high-concentration drift region 144 may have a flat bottom that does not meander up and down in the thickness direction.

[0324] The second high-concentration drift region 144 may be formed by increasing the concentration of the drift region 11 throughout the first protection region 8. This configuration reduces the on-resistance of the drift region 11 by increasing the concentration of the drift region 11. However, it should be noted that in this case, an increase in the carrier density in the drift region 11 makes electric field concentration more likely to occur, resulting in a trade-off in which the breakdown voltage decreases. Therefore, in order to reduce the on-resistance while suppressing a decrease in the breakdown voltage, it is preferable to introduce the second high-concentration drift region 144 into a portion of the first protection region 8.

[0325] The aforementioned second body region 107 is formed shallower than the second high-concentration drift region 144. Specifically, the second body region 107 is formed shallower than the second trench isolation structure 100, and has a bottom located closer to the first main surface 3 than the bottom wall of the second trench isolation structure 100. The bottom of the second body region 107 is preferably located closer to the first main surface 3 than the intermediate depth range of the second trench isolation structure 100.

[0326] The plurality of second trench gate structures 110 described above penetrate the second body region 107 in a cross-sectional view and are located within the second heavily doped drift region 144. The plurality of second trench gate structures 110 are formed at intervals from the bottom of the second heavily doped drift region 144 toward the first main surface 3, and face the drift region 11 with a part of the second heavily doped drift region 144 in between.

[0327] The second trench gate structures 110 are formed to be shifted in the first direction X with respect to the second recesses 146, and face the second bulging portions 145 in the thickness direction, respectively. The second trench gate structures 110 preferably face the deepest portions of the second bulging portions 145. This configuration is obtained by introducing n-type impurities into the chip 2 from the wall surfaces of the second gate trenches 111 after the step of forming the second gate trenches 111.

[0328] The two second trench gate structures 110 located on both sides in the first direction X are preferably formed in regions outside the second heavily doped drift region 144. That is, the outermost second trench gate structure 110 is preferably located within the drift region 11, penetrating the second body region 107 at a position spaced from the second heavily doped drift region 144 toward the second trench isolation structure 100.

[0329] The outermost second trench gate structure 110 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a part of the drift region 11. The plurality of second channel cells 118 are preferably formed in the second heavily doped drift region 144, closer to the periphery of the second heavily doped drift region 144 in plan view.

[0330] The above-described embodiment can be implemented in other forms. For example, in the above-described embodiment, an example was shown in which the output region 6, the control region 7, the first protection region 8, and the second protection region 9 were formed on one chip 2. However, a semiconductor device 1 having the output region 6, the first protection region 8, and the second protection region 9, but not the control region 7, may be employed. Alternatively, a semiconductor device 1 having the control region 7, the first protection region 8, and the second protection region 9, but not the output region 6, may be employed. Alternatively, a semiconductor device 1 having the first protection region 8 and the second protection region 9, but not the output region 6 and the control region 7, may be employed.

[0331] Of course, these semiconductor devices 1 only need to include at least one of the first protection region 8 and the second protection region 9, and do not necessarily need to simultaneously include both the first protection region 8 and the second protection region 9. These semiconductor devices 1 may be incorporated into a semiconductor module, a semiconductor circuit, or the like together with other semiconductor devices 1 to form an IPD such as that shown in FIG.

[0332] In the above-described embodiment, multiple systems of output transistors 20 have been shown. However, a single system of output transistors 20 may be employed. In this case, the second system transistors 21B are formed as the first system transistors 21A, and all of the first trench gate structures 70 for the output transistors 20 are simultaneously controlled to be turned on and off.

[0333] Of course, the above-described embodiment may employ three or more systems of output transistors 20. In this case, a plurality of block regions 81 for the system transistors constituting the three or more systems are provided, and at the same time, three or more systems of first gate wirings 96 corresponding to the block regions 81 are provided.

[0334] In the above-described embodiment, a configuration including a current monitor circuit 25 has been described. The current monitor circuit 25 may be formed using at least one unit transistor 22 out of the plurality of unit transistors 22.

[0335] In the above-described embodiment, an example has been shown in which the first upper electrode 73 and the first lower electrode 74 are at the same potential. However, a source potential may be applied to the first lower electrode 74. In this case, the first source wiring 98 is electrically connected to the first connection electrode 93 through the via electrode 97.

[0336] In the above-described embodiment, an example has been shown in which the second upper electrode 113 and the second lower electrode 114 are at the same potential. However, a source potential may be applied to the second lower electrode 114. In this case, the second source wiring 138 is electrically connected to the second connection electrode 133 through the via electrode 97.

[0337] In the above-described embodiment, an example has been shown in which the second trench isolation structure 100 is electrically connected to the second source wiring 138. However, the second trench isolation structure 100 may be electrically connected to the first source wiring 98 instead of the second source wiring 138.

[0338] In the above-described embodiment, an example has been shown in which the plurality of first trench gate structures 70 are arranged in stripes extending in the second direction Y, and the plurality of second trench gate structures 110 are arranged in stripes extending in the second direction Y. However, the plurality of second trench gate structures 110 may extend in a direction different from the extension direction of the plurality of first trench gate structures 70.

[0339] For example, the plurality of first trench gate structures 70 may be arranged in stripes extending in the second direction Y, and the plurality of second trench gate structures 110 may be arranged in stripes extending in the first direction X. For example, the plurality of first trench gate structures 70 may be arranged in stripes extending in the first direction X, and the plurality of second trench gate structures 110 may be arranged in stripes extending in the second direction Y.

[0340] In the above-described embodiment, an example has been shown in which the source terminal 13 is an output terminal and the drain terminal 15 is a power supply terminal. However, a configuration in which the source terminal 13 is a ground terminal and the drain terminal 15 is an output terminal may also be adopted. In this case, the semiconductor device 1 becomes a low-side switching device electrically connected between a load (inductive load L) and ground.

[0341] In the above-described embodiment, an example was shown in which the first conductivity type was n-type and the second conductivity type was p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing the n-type regions with p-type regions and the p-type regions with n-type regions in the above description and the accompanying drawings.

[0342] In the above-described embodiment, the first direction X and the second direction Y are defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any directions as long as they maintain a mutually intersecting (specifically, perpendicular) relationship. For example, the first direction X may be the extending direction of the third side surface 5C (fourth side surface 5D), and the second direction Y may be the extending direction of the first side surface 5A (second side surface 5B). Furthermore, the first direction X may be a direction intersecting the first to fourth side surfaces 5A to 5D, and the second direction Y may be a direction intersecting the first to fourth side surfaces 5A to 5D.

[0343] Below are examples of features extracted from this specification and the accompanying drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-described embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "semiconductor protection device," "semiconductor overvoltage protection device," "semiconductor switching device," "semiconductor control device," "semiconductor module," "electronic circuit," "semiconductor circuit," "intelligent power device," "intelligent power module," "intelligent power switch," etc., as necessary.

[0344] [A1] A semiconductor device (1) comprising: a chip (2) having a main surface (3); an output region (6) provided on the main surface (3); protection regions (8, 9) provided on the main surface (3); an output transistor (20) having a plurality of first trench gate structures (70) formed on the main surface (3) in the output region (6) with a first interval (I1) between them; and a protection transistor (40, 50) including a plurality of second trench gate structures (110) formed on the main surface (3) in the protection region (8, 9) with a second interval (I2) larger than the first interval (I1), and a protection circuit (39, 49) forming a discharge path for overvoltages (Vs1, Vs2).

[0345] [A2] The semiconductor device (1) according to A1, wherein the second interval (I2) is four times or less the first interval (I1).

[0346] [A3] The semiconductor device (1) according to A1 or A2, wherein the first interval (I1) is 0.4 μm or more and 0.8 μm or less, and the second interval (I2) is 0.8 μm or more and 1.6 μm or less.

[0347] [A4] A semiconductor device (1) according to any one of A1 to A3, wherein the plurality of first trench gate structures (70) have a width (W2) of 0.4 μm or more and 2 μm or less, and the plurality of second trench gate structures (110) have a width (W4) of 0.4 μm or more and 2 μm or less.

[0348] [A5] A semiconductor device (1) according to any one of A1 to A4, wherein the first interval (I1) is less than the width (W2) of each of the first trench gate structures (70), and the second interval (I2) is greater than or equal to the width (W4) of each of the second trench gate structures (110).

[0349] [A6] A semiconductor device (1) according to any one of A1 to A5, wherein the plurality of second trench gate structures (110) have a width (W4) approximately equal to the width (W2) of the plurality of first trench gate structures (70).

[0350] [A7] A semiconductor device (1) according to any one of A1 to A6, wherein the plurality of first trench gate structures (70) have a depth (D2) of 1 μm or more and 6 μm or less, and the plurality of second trench gate structures (110) have a depth (D4) of 1 μm or more and 6 μm or less.

[0351] [A8] A semiconductor device (1) according to any one of A1 to A7, wherein the plurality of second trench gate structures (110) have a depth (D4) approximately equal to the depth (D2) of the plurality of first trench gate structures (70).

[0352] [A9] A semiconductor device (1) described in any one of A1 to A8, wherein the output region (6) has a first planar area, and the protection region (8, 9) has a second planar area less than the first planar area.

[0353] [A10] The semiconductor device (1) according to A9, wherein the second planar area is 1 / 10 or less of the first planar area.

[0354] [A11] A semiconductor device (1) according to any one of A1 to A10, wherein the output transistor (20) has a first breakdown current per unit area, and the protection transistor (40, 50) has a second breakdown current per unit area that is greater than the first breakdown current.

[0355] [A12] The semiconductor device (1) described in any one of A1 to A11, wherein the output transistor (20) has a first on-resistance per unit area, and the protection transistor (40, 50) has a second on-resistance per unit area that is greater than the first on-resistance.

[0356] [A13] The semiconductor device (1) described in any one of A1 to A12, wherein the plurality of first trench gate structures (70) each have an electrode structure including a first upper electrode (73) and a first lower electrode (74) embedded in the first trench (71) in the vertical direction with an insulator (72, 75) sandwiched therebetween, and the plurality of second trench gate structures (110) each have an electrode structure including a second upper electrode (113) and a second lower electrode (114) embedded in the second trench (111) in the vertical direction with an insulator (112, 115) sandwiched therebetween.

[0357] [A14] The semiconductor device (1) according to any one of A1 to A13, further including: a first conductivity type (n-type) drift region (11) formed in a surface layer portion of the main surface (3) in both the output region (6) and the protection region (8, 9); and a first conductivity type (n-type) high-concentration drift region (64) formed in a surface layer portion of the drift region (11) in the output region (6) and having a higher impurity concentration than the drift region (11), wherein a plurality of the first trench gate structures (70) are formed in the main surface (3) so as to be located within the high-concentration drift region (64), and a plurality of the second trench gate structures (110) are formed in the main surface (3) so as to be located within the drift region (11).

[0358] [A15] The semiconductor device (1) according to A14, wherein the high-concentration drift region (64) is not formed in the protection region (8, 9).

[0359] [A16] The semiconductor device (1) according to A14 or A15, wherein the high-concentration drift region (64) is formed at intervals from a bottom of the drift region (11) toward the main surface (3), and the plurality of first trench gate structures (70) are formed at intervals from a bottom of the high-concentration drift region (64) toward the main surface (3).

[0360] [A17] A chip (2) having a main surface (3), an output region (6) provided on the main surface (3), protection regions (8, 9) provided on the main surface (3), a drift region (11) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3), a high-concentration drift region (64) of the first conductivity type (n-type) formed in a surface layer portion of the drift region (11) in the output region (6) and having a higher impurity concentration than the drift region (11), and a protection circuit (39, 49) having a protection transistor (40, 50) including a second trench gate structure (110) formed on the main surface (3) so as to be positioned within the drift region (11) in the protection region (8, 9), the protection circuit (39, 49) forming a discharge path for overvoltages (Vs1, Vs2).

[0361] [A18] The semiconductor device (1) according to A17, wherein the high-concentration drift region (64) is not formed in the protection region (8, 9).

[0362] [A19] A semiconductor device (1) according to A17 or A18, wherein the output region (6) has a first planar area, and the protection region (8, 9) has a second planar area less than the first planar area.

[0363] [A20] The semiconductor device (1) according to any one of A17 to A19, wherein the high-concentration drift region (64) is formed at a distance from a bottom of the drift region (11) toward the main surface (3), the first trench gate structure (70) is formed at a distance from a bottom of the high-concentration drift region (64) toward the main surface (3), and the second trench gate structure (110) is formed at a distance from a bottom of the drift region (11) toward the main surface (3).

[0364] [B1] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, first terminals (14, 14a, 14b) arranged on the first main surface (3), second terminals (15) arranged on the second main surface (4), and protection transistors (40, 50) formed on the first main surface (3) so as to be electrically interposed between the first terminals (14, 14a, 14b) and the second terminals (15), and a protection circuit (39, 49) that forms a discharge path for an overvoltage (Vs1, Vs2) generated between the first terminal (14a, 14b) and the second terminal (15), and the protection transistor (40, 50) includes a plurality of trench gate structures (110) each having an upper electrode (113) and a lower electrode (114) that are vertically embedded in a trench (111) formed in the first main surface (3) with an insulator (112, 115) sandwiched therebetween.

[0365] [B2] The semiconductor device (1) according to B1, wherein the plurality of trench gate structures (110) are arranged at intervals (I2) that are equal to or greater than the width (W4) of each trench gate structure (110).

[0366] [B3] The semiconductor device (1) according to B1 or B2, wherein the plurality of trench gate structures (110) are arranged at intervals (I2) of 0.8 μm or more and 1.6 μm or less.

[0367] [B4] The semiconductor device (1) according to any one of B1 to B3, wherein the plurality of trench gate structures (110) each have a width (W4) of 0.4 μm or more and 2 μm or less.

[0368] [B5] The semiconductor device (1) described in any one of B1 to B4, wherein the protection transistor (40, 50) includes a drift region (11) of a first conductivity type (n-type) formed in a surface layer portion of the first main surface (3), and the plurality of trench gate structures (110) are formed in the first main surface (3) so as to be positioned within the drift region (11).

[0369] [B6] The semiconductor device (1) according to B5, wherein the drift region (11) does not have a concentration gradient in which the impurity concentration increases from the bottom side toward the first main surface (3).

[0370] [B7] The semiconductor device (1) according to B5, wherein the drift region (11) has a constant impurity concentration in the thickness direction.

[0371] [B8] The semiconductor device (1) described in any one of B1 to B7, wherein the protection circuit (39) forms a discharge path for the overvoltage (Vs1) generated at the second terminal (15) based on the first terminal (14, 14a).

[0372] [B9] The semiconductor device (1) described in B8, wherein the protection circuit (39) includes a clamp circuit (41) formed on the first main surface (3) so as to be electrically connected to the second terminal (15), and the protection transistor (40, 50) has a drain electrically connected to the second terminal (15), a source electrically connected to the first terminal (14, 14a), and a plurality of the trench gate structures (110) as gates electrically connected to the second terminal (15) via the clamp circuit (41).

[0373] [B10] The semiconductor device (1) according to B8 or B9, wherein the first terminal (14, 14a) is a ground terminal (14a).

[0374] [B11] The semiconductor device (1) according to any one of B1 to B7, wherein the protection circuit (49) forms a discharge path for the overvoltage (Vs2) generated at the first terminal (14, 14b) based on the second terminal (15).

[0375] [B12] The semiconductor device (1) described in B11, wherein the protection transistor (50) has a drain electrically connected to the second terminal (15), a source electrically connected to the first terminal (14, 14b), and a plurality of the trench gate structures (110) as gates electrically connected to the first terminal (14, 14b).

[0376] [B13] A semiconductor device (1) according to any one of B1 to B12, further including an output region (6) provided on the first main surface (3), protection regions (8, 9) provided in a region of the first main surface (3) different from the output region (6), an output terminal (13) arranged on the first main surface (3), and an output transistor (20) formed on the first main surface (3) of the output region (6) so as to be electrically connected to the second terminal (15) and the output terminal (13), and the protection transistor (40, 50) is formed on the first main surface (3) of the protection region (8, 9).

[0377] [B14] The semiconductor device (1) described in B13, wherein the output transistor (20) includes a plurality of second trench gate structures (70), each having a second upper electrode (73) and a second lower electrode (74) buried in the vertical direction within a second trench (71) formed in the first main surface (3), with a second insulator (72, 75) sandwiched therebetween.

[0378] [B15] The semiconductor device (1) according to B13 or B14, wherein the output region (6) has a first planar area, and the protection region (8, 9) has a second planar area less than the first planar area.

[0379] [B16] The semiconductor device (1) according to any one of B13 to B15, further including: a control region (7) provided in a region different from the output region (6) on the first main surface (3); and a control circuit (23) formed in the control region (7) so as to be electrically connected to the output transistor (20), and controlling the output transistor (20).

[0380] [B17] The semiconductor device (1) according to B16, wherein the protection region (8, 9) is provided within the control region (7).

[0381] [B18] A chip (2) having a first main surface (3) on one side and a second main surface (4) on the other side, a first terminal (14, 14a) arranged on the first main surface (3), a second terminal (14, 14b) arranged on the first main surface (3), a third terminal (15) arranged on the second main surface (4), a first protection transistor (40) formed on the first main surface (3) so as to be electrically interposed between the first terminal (14, 14a) and the third terminal (15), and forming a discharge path for an overvoltage (Vs1) generated between the first terminal (14, 14a) and the third terminal (15), and a second protection transistor (50) formed on the first main surface (3) so as to be electrically interposed between the second terminal (14, 14b) and the third terminal (15). and a second protection circuit (49) that forms a discharge path for an overvoltage (Vs2) generated between the second terminal (14, 14b) and the third terminal (15), wherein the first protection transistor (40) includes a plurality of first trench gate structures (110), each having a first upper electrode (113) and a first lower electrode (114) that are vertically embedded in a first trench (111) formed in the first main surface (3) with a first insulator (112, 115) sandwiched therebetween, and the second protection transistor (40, 50) includes a plurality of second trench gate structures (110), each having a second upper electrode (113) and a second lower electrode (114) that are vertically embedded in a second trench (111) formed in the first main surface (3) with a second insulator (112, 115) sandwiched therebetween.

[0382] [B19] The semiconductor device (1) described in B18, wherein the first protection transistor (40) forms a discharge path for the overvoltage (Vs1) generated at the third terminal (15) with the first terminal (14, 14a) as a reference, and the second protection transistor (50) forms a discharge path for the overvoltage (Vs2) generated at the second terminal (14, 14b) with the third terminal (15) as a reference.

[0383] [B20] A semiconductor device (1) according to B18 or B19, further comprising: an output terminal (13) arranged on the first main surface (3); and an output transistor (20) formed on the first main surface (3) so as to be electrically connected to the third terminal (15) and the output terminal (13), wherein the output transistor (20) includes a plurality of third trench gate structures (70), each having a third upper electrode (73) and a third lower electrode (74) buried in a third trench (71) formed in the first main surface (3) in the vertical direction with a third insulator (72, 75) sandwiched therebetween.

[0384] [B21] The semiconductor device (1) described in B20, wherein the output transistor (20) includes a plurality of system transistors (21, 21A, 21B) each formed on the first main surface (3) so as to be individually controllable, and is configured to generate a single output signal (Io) by selectively controlling the plurality of system transistors (21, 21A, 21B).

[0385] [B22] The semiconductor device (1) according to B21, wherein the output transistor (20) is configured so that the on-resistance is changed by individual control of the plurality of system transistors (21, 21A, 21B).

[0386] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification and the accompanying drawings can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0387] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 4 second main surface 6 output region 7 control region 8 first protection region 9 second protection region 11 drift region 13 source terminal (output terminal) 14 control terminal 14a ground terminal 14b input terminal 15 drain terminal 20 output transistor 21 system transistor 21A first system transistor 21B second system transistor 23 control circuit 39 first overvoltage protection circuit (first protection circuit) 40 first protection transistor 41 clamp circuit 49 second overvoltage protection circuit (second protection circuit) 50 second protection transistor 64 high-concentration drift region 70 first trench gate structure 71 first gate trench 72 first insulating film 73 first upper electrode 74 second lower electrode 75 first intermediate insulating film 110 second trench gate structure 111 second gate trench 112 second insulating film 113 Second upper electrode 114 Second lower electrode 115 Second intermediate insulating film I1 First interval of first trench gate structure I2 Second interval of second trench gate structure W2 Second width of first trench gate structure W4 Fourth width of second trench gate structure D2 Second depth of first trench gate structure D4 Fourth depth of second trench gate structure Io Output current Vs1 First overvoltage Vs2 Second overvoltage

Claims

1. a chip having a first major surface on one side and a second major surface on the other side; a first terminal disposed on the first main surface; a second terminal disposed on the second main surface; a protection circuit including a protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the second terminal, and forming a discharge path for an overvoltage occurring between the first terminal and the second terminal; The semiconductor device includes a plurality of trench gate structures, each of which has an upper electrode and a lower electrode vertically embedded in a trench formed in the first main surface with an insulator therebetween.

2. The semiconductor device according to claim 1 , wherein the plurality of trench gate structures are arranged at intervals equal to or greater than the width of each of the trench gate structures.

3. The semiconductor device according to claim 1 , wherein the plurality of trench gate structures are arranged at intervals of 0.8 μm or more and 1.6 μm or less.

4. The semiconductor device according to claim 1 , wherein each of said plurality of trench gate structures has a width of not less than 0.4 μm and not more than 2 μm.

5. the protection transistor includes a drift region of a first conductivity type formed in a surface layer portion of the first main surface, The semiconductor device according to claim 1 , wherein the trench gate structures are formed on the first main surface so as to be located within the drift region.

6. The semiconductor device according to claim 5 , wherein the drift region does not have a concentration gradient in which the impurity concentration increases from a bottom side toward the first main surface side.

7. The semiconductor device according to claim 5 , wherein said drift region has a constant impurity concentration in a thickness direction.

8. 2 . The semiconductor device according to claim 1 , wherein the protection circuit forms a discharge path for the overvoltage occurring at the second terminal with respect to the first terminal.

9. the protection circuit includes a clamp circuit formed on the first main surface to be electrically connected to the second terminal; 9. The semiconductor device according to claim 8, wherein the protection transistor has a drain electrically connected to the second terminal, a source electrically connected to the first terminal, and a plurality of the trench gate structures as a gate electrically connected to the second terminal via the clamp circuit.

10. The semiconductor device according to claim 8 , wherein the first terminal is a ground terminal.

11. 2 . The semiconductor device according to claim 1 , wherein the protection circuit forms a discharge path for the overvoltage occurring at the first terminal with respect to the second terminal.

12. 12. The semiconductor device according to claim 11, wherein the protection transistor has a drain electrically connected to the second terminal, a source electrically connected to the first terminal, and a plurality of the trench gate structures as a gate electrically connected to the first terminal.

13. an output region provided on the first main surface; a protection region provided in a region different from the output region on the first main surface; an output terminal disposed on the first main surface; an output transistor formed on the first main surface of the output region so as to be electrically connected to the second terminal and the output terminal, 13. The semiconductor device according to claim 1, wherein the protection transistor is formed on the first main surface of the protection region.

14. 14. The semiconductor device according to claim 13, wherein the output transistor includes a plurality of second trench gate structures each having a second upper electrode and a second lower electrode vertically embedded in a second trench formed in the first main surface with a second insulator therebetween.

15. the output area has a first planar area; The semiconductor device according to claim 13 , wherein the protection region has a second planar area less than the first planar area.

16. a control region provided in a region different from the output region on the first main surface; The semiconductor device according to claim 13 , further comprising: a control circuit formed in said control region so as to be electrically connected to said output transistor, said control circuit controlling said output transistor.

17. The semiconductor device according to claim 16 , wherein the protection region is provided within the control region.

18. a chip having a first major surface on one side and a second major surface on the other side; a first terminal disposed on the first main surface; a second terminal disposed on the first main surface; a third terminal disposed on the second main surface; a first protection circuit including a first protection transistor formed on the first main surface so as to be electrically interposed between the first terminal and the third terminal, the first protection circuit forming a discharge path for an overvoltage generated between the first terminal and the third terminal; a second protection circuit including a second protection transistor formed on the first main surface so as to be electrically interposed between the second terminal and the third terminal, and forming a discharge path for an overvoltage generated between the second terminal and the third terminal; the first protection transistor includes a plurality of first trench gate structures each having a first upper electrode and a first lower electrode vertically embedded in a first trench formed in the first main surface with a first insulator therebetween; the second protection transistor includes a plurality of second trench gate structures each having a second upper electrode and a second lower electrode vertically embedded in a second trench formed in the first main surface with a second insulator therebetween.

19. the first protection transistor forms a discharge path for the overvoltage occurring at the third terminal with respect to the first terminal; 20. The semiconductor device according to claim 18, wherein the second protection transistor forms a discharge path for the overvoltage occurring at the second terminal with respect to the third terminal.

20. an output terminal disposed on the first main surface; an output transistor formed on the first main surface so as to be electrically connected to the third terminal and the output terminal, 20. The semiconductor device according to claim 18 or 19, wherein the output transistor includes a plurality of third trench gate structures each having a third upper electrode and a third lower electrode buried in a third trench formed in the first main surface in a vertical direction with a third insulator sandwiched therebetween.