Semiconductor device

Abstract

Provided is a semiconductor device configured to allow miniaturization or an advanced degree of integration. This semiconductor device has a first transistor, a connection part, a first insulator, a second insulator, and first wiring. The connection part has a first electrode and a second electrode. The first transistor has second and third electrodes, a first semiconductor, a gate insulator, and a first gate electrode. The first insulator has a first opening that reaches the first wiring. The first electrode is in contact with a side surface in the first opening and an upper surface of the first wiring. The second electrode is in contact with the first electrode in the first opening. The second insulator has a second opening that reaches the second electrode. The third electrode is provided on the second insulator. The first semiconductor is in contact with the third electrode, a side surface in the second opening in the second insulator, and an upper surface of the second electrode. The gate insulator is in contact with the first semiconductor in the second opening. The first gate electrode faces the first semiconductor via the gate insulator.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing the memory device or the semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0007] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a need for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose techniques for increasing the density of integrated circuits by providing a plurality of memory cells each including a transistor using an oxide semiconductor film in a stacked manner.

[0008] Furthermore, if a transistor can be made vertical, it is possible to increase the density of an integrated circuit. For example, Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated. Another object is to separately form a memory element and a peripheral circuit in a memory device at low cost. Another object is to provide a memory device that can reduce a load on wiring. Another object is to provide a memory device with high operating speed. Another object is to provide a memory device with good electrical characteristics. Another object is to provide a memory device with little variation in the electrical characteristics of transistors. Another object is to provide a memory device with good reliability. Another object is to provide a memory device with large on-state current. Another object is to provide a memory device with low power consumption. Another object is to provide a novel memory device. Another object is to provide a manufacturing method of a novel memory device. An object of one embodiment of the present invention is to at least alleviate at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a semiconductor device including a first transistor, a connection portion, a first insulator, a second insulator, and a first wiring. The connection portion includes a first electrode and a second electrode. The first transistor includes a second electrode, a third electrode, a first semiconductor, a gate insulator, and a first gate electrode. The first insulator is provided on the first wiring and has a first opening reaching the first wiring. The first electrode has a first portion in contact with a side surface of the first insulator in the first opening and a second portion in contact with a top surface of the first wiring. The second electrode is embedded in the first opening and is in contact with the second portion of the first electrode. The second insulator is provided on the first insulator and has a second opening reaching the second electrode. The third electrode is provided on the second insulator. The first semiconductor has a third portion in contact with the third electrode, a fourth portion in contact with a side surface of the second insulator within the second opening, and a fifth portion in contact with a top surface of the second electrode. The gate insulator is located within the second opening and in contact with the fourth and fifth portions of the first semiconductor. The first gate electrode is located within the second opening and faces the third, fourth, and fifth portions of the first semiconductor via the gate insulator.

[0014] In the above, it is preferable that the semiconductor device further includes a capacitor and a second wiring. The capacitor includes a fourth electrode, a fifth electrode, and a third insulator. The first insulator has a third opening that reaches the second wiring. The fourth electrode has a sixth portion that contacts a sidewall within the third opening of the first insulator and a seventh portion that contacts an upper surface of the second wiring. The third insulator is located within the third opening and contacts the sixth and seventh portions of the fourth electrode. The fifth electrode is embedded in the third opening and faces the sixth and seventh portions of the fourth electrode via the third insulator.

[0015] In the above, it is preferable that the semiconductor device further includes a second transistor on the capacitor. The second transistor has a fifth electrode, a sixth electrode, a second semiconductor, a gate insulator, and a second gate electrode. The second insulator has a fourth opening reaching the fifth electrode. The sixth electrode is provided on the second insulator. The second semiconductor has an eighth portion in contact with the sixth electrode, a ninth portion in contact with a sidewall in the fourth opening of the second insulator, and a tenth portion in contact with an upper surface of the fifth electrode. The gate insulator is located in the fourth opening and in contact with the eighth, ninth, and tenth portions of the second semiconductor. The second gate electrode is located in the fourth opening and faces the ninth and tenth portions of the second semiconductor via the gate insulator.

[0016] In any of the above, the second electrode preferably contacts the first portion of the first electrode.

[0017] Alternatively, in any of the above, it is preferable that the semiconductor device further includes a fourth insulator. In this case, it is preferable that the fourth insulator is located within the first opening and contacts the first portion of the first electrode. Furthermore, it is preferable that the second electrode contacts the fourth insulator.

[0018] In any of the above, the second electrode preferably includes a first conductor and a second conductor on the first conductor, wherein the first conductor is embedded in the first opening and contacts the second portion of the first electrode, and the second conductor contacts the first semiconductor.

[0019] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a memory element and a peripheral circuit can be separately formed at low cost in a memory device. Alternatively, a memory device that can reduce the load on wiring can be provided. Alternatively, a memory device with high operating speed can be provided. Alternatively, a memory device with high reliability can be provided. Alternatively, a memory device with little variation in the electrical characteristics of transistors can be provided. Alternatively, a memory device with good electrical characteristics can be provided. Alternatively, a memory device with large on-state current can be provided. Alternatively, a memory device with low power consumption can be provided. Alternatively, a novel memory device can be provided. Alternatively, a manufacturing method of a novel memory device can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0020] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0021] FIGS. 1A to 1D are configuration examples of a memory device. FIGS. 2A to 2D are configuration examples of a memory device. FIGS. 3A and 3B are configuration examples of a memory device. FIGS. 4A to 4D are configuration examples of a memory device. FIGS. 5A to 5D are configuration examples of a memory device. FIGS. 6A and 6B are configuration examples of a memory device. FIGS. 7A to 7D are configuration examples of a memory device. FIGS. 8A to 8C are configuration examples of a memory device. FIGS. 9A and 9B are configuration examples of a memory device. FIGS. 10A to 10D are configuration examples of a memory device. FIGS. 11A and 11B are configuration examples of a memory device. FIGS. 12A to 12C are diagrams illustrating a method for manufacturing a memory device. FIGS. 13A to 13C are diagrams illustrating a method for manufacturing a memory device. FIGS. 14A to 14C are diagrams illustrating a method for manufacturing a memory device. FIGS. 15A to 15C are diagrams illustrating a method for manufacturing a memory device. FIGS. 16A to 16C are diagrams illustrating a method for manufacturing a memory device. FIGS. 17A to 17C are diagrams illustrating a method for manufacturing a memory device. FIGS. 18A to 18C are diagrams illustrating a method for manufacturing a memory device. FIGS. 19A to 19C are diagrams illustrating a method for manufacturing a memory device. FIGS. 20A to 20C are diagrams illustrating a method for manufacturing a memory device. FIGS. 21A to 21C are diagrams illustrating a method for manufacturing a memory device. FIGS. 22A to 22C are diagrams illustrating a method for manufacturing a memory device. FIGS. 23A to 23C are diagrams illustrating a method for manufacturing a memory device. FIGS. 24A and 24B are structural examples of a memory device. FIGS. 25A and 25B are structural examples of a memory device. FIGS. 26A and 26B are structural examples of a memory device. FIGS. 27A and 27B are structural examples of a memory device. FIGS. 28A to 28C are structural examples of a memory device. FIGS. 29A to 29C are structural examples of a memory device. Fig. 30 is a configuration example of a storage device. Fig. 31 is a configuration example of a storage device. Fig. 32 is a block diagram showing an example of a storage device. Figs. 33A and 33B are schematic diagrams showing an example of a storage device. Figs. 34A to 34D are circuit diagrams showing an example of a storage device. Fig. 35 is a circuit diagram showing an example of a storage device. Figs. 36A and 36B are diagrams showing an example of an electronic component. Figs. 37A and 37B are diagrams showing an example of an electronic device.Fig. 37C to Fig. 37E are diagrams showing an example of a mainframe computer, Fig. 38A is a diagram showing an example of space equipment, and Fig. 38B is a diagram showing an example of a storage system applicable to a data center.

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0023] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, they are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may unintentionally be thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular symbol may be assigned.

[0024] In order to make the invention easier to understand, particularly in plan views (also called "top views") and perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0025] In addition, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for explanation. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification and the like.

[0026] Furthermore, in this specification, terms indicating position, such as "above" and "below," are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0027] For example, in this specification, "X and Y are connected" refers to an electrical connection between X and Y. Here, "X and Y are electrically connected" refers to a connection in which an electrical signal can be transmitted between X and Y when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between X and Y. Note that "X and Y are electrically connected" also includes a case in which X and Y are directly connected. Here, "X and Y are directly connected" refers to a connection in which an electrical signal can be transmitted between X and Y via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection refers to a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0028] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0029] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0030] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor, reduce the crystallinity, and so on. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. Ｏ Oxygen vacancies (also called oxygen vacancies) may be formed.

[0031] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride. Also, a nitride oxide is a material whose composition contains more nitrogen than oxygen. Examples of nitride oxides include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.

[0032] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0033] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0034] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0035] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0036] In this specification, the term "equal heights" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a manufacturing process for a memory device, a planarization process (typically a CMP (Chemical Mechanical Polishing) process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process are configured to have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also considered to be "equal heights." For example, when there are two layers (here, a first layer and a second layer) with different heights relative to the reference surface, and the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also considered to be "equal heights."

[0037] In this specification, "edges coincide" means that, in a plan view, at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges coincide" is also used.

[0038] Generally, it is difficult to clearly distinguish between an "exact match" and an "approximate match." For this reason, in this specification, "match" includes both an exact match and an approximate match.

[0039] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no potential is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0040] In this specification, the term "leakage current" may be used to mean the same thing as "off-state current." In this specification, the term "off-state current" may refer to, for example, a current that flows between the source and drain of a transistor when the transistor is in an off state.

[0041] Embodiment 1 In this embodiment, a configuration example of a memory device according to one embodiment of the present invention and a manufacturing method thereof will be described. One embodiment of the present invention has a memory cell and a functional element on the same plane.

[0042] The memory cell has a capacitive element and a transistor on the capacitive element. The capacitive element has a so-called MIM (Metal-Insulator-Metal) structure, which includes a pair of conductors and a dielectric sandwiched between them. On the other hand, the functional element has a connection portion and a transistor on the connection portion. Here, the connection portion has a configuration in which a portion of the dielectric in the capacitive element has been removed. In the connection portion, the pair of conductors are electrically connected in the portion where the dielectric is not provided. In other words, the memory cell and the functional element have the same configuration except for the configuration of the dielectric. With this configuration, by adding only the process of processing the dielectric, it is possible to separately create memory cells and functional elements including transistors on the same surface.

[0043] In the functional element, one of the source electrode and the drain electrode of the transistor included in the functional element can be electrically connected to a wiring located below the connection portion. The transistor can be used as a switch for controlling electrical connection or non-conduction between the other of the source electrode and the drain electrode and the wiring. Various peripheral circuits can be configured by combining such functional elements.

[0044] 1A shows a cross-sectional perspective view of a region including memory cell 150. The left side of FIG. 1A shows a perspective view including a cut surface of memory cell 150 cut along the X-Z plane, and the right side of FIG. 1A shows a perspective view including a cut surface of memory cell 150 cut along the Y-Z plane. In FIG. 1A, only the outlines of some components (insulator 180, insulator 280, etc.) are shown by solid lines.

[0045] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0046] The memory cell 150 includes a capacitor 100 on a conductor 110 and a transistor 200 on the capacitor 100 .

[0047] The capacitor element includes a conductor 115, a conductor 120, and an insulator 130 therebetween. The conductor 115, the insulator 130, and the conductor 120 are embedded inside an opening provided in the insulator 180.

[0048] The transistor 200 includes a conductor 120 functioning as one of a source electrode and a drain electrode, an oxide semiconductor 230, an insulator 250 functioning as a gate insulator, a conductor 260 functioning as a gate electrode, and a conductor 240 functioning as the other of the source electrode and drain electrode. The conductor 240 is provided over an insulator 280. An opening reaching the conductor 120 is provided in the insulator 280. The oxide semiconductor 230 is provided along an inner wall of the opening and is in contact with the conductor 240 and the conductor 120.

[0049] In the transistor 200 having the above-described structure, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the semiconductor in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like.

[0050] Since the transistor 200 can have a source electrode, a semiconductor, and a drain electrode that are stacked on top of each other, the area occupied by the transistor 200 can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (Lateral FET)), in which the semiconductor is arranged on a plane.

[0051] Furthermore, the channel length of the transistor 200 can be precisely controlled by the thickness of the insulator 280, which functions as a spacer. This allows for extremely small variations in the channel length compared to planar transistors. Furthermore, by thinning the insulator 280, transistors with extremely short channel lengths can be manufactured. For example, transistors with channel lengths of 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be manufactured. Therefore, even with a conventional exposure tool for mass production, a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure tool used in cutting-edge LSI technology.

[0052] 1B shows a circuit diagram corresponding to the memory cell 150. The transistor 200 corresponds to the transistor Tr, and the capacitor 100 corresponds to the capacitor C. The conductor 110 corresponds to the wiring PL, the conductor 240 corresponds to the wiring BL, and the conductor 260 corresponds to the wiring WL. The memory cell 150 is composed of one transistor Tr and one capacitor C, and can also be expressed as 1Tr1C.

[0053] 1C shows a schematic perspective view of a region including the functional element 155. The functional element 155 has a connection portion 101 and a transistor 200 on the connection portion 101. The transistors in the functional element 155 have the same configuration as the transistors in the memory cell 150, and therefore are denoted by the same reference numerals and redundant description will be omitted.

[0054] The connection portion 101 has a configuration in which a portion of the insulator 130 in the above-described capacitor element 100 is opened, and the conductor 115 and the conductor 120 are in contact with each other through the opening. Fig. 1C shows an example in which a portion of the insulator 130 located at the bottom of the opening in the insulator 180 is removed, while a portion along the side of the opening remains. Such a configuration can be produced, for example, by anisotropically etching the insulator 130.

[0055] Since the conductor 120 and the conductor 115 are electrically connected, the conductor 120 and the conductor 110 are electrically connected via the conductor 115. That is, one of the source electrode and the drain electrode of the transistor 200 is electrically connected to the conductor 110.

[0056] 1D shows a circuit diagram corresponding to the functional element 155. The conductor 110 corresponds to the wiring CL, the conductor 240 corresponds to the wiring BL, and the conductor 260 corresponds to the wiring WL. In this manner, the functional element 155 can function as a switch for controlling conduction and non-conduction between the wiring BL and the wiring CL. The functional element 155 can also be regarded as a single transistor.

[0057] In one embodiment of the present invention, the memory cell 150 and the functional element 155 can be separately formed on the same plane. For example, a memory cell array including a plurality of memory cells 150 and a peripheral circuit can be manufactured on the same plane through the same process.

[0058] A more specific example will be described below.

[0059] <Configuration Example of Memory Device> An example of a memory device having a memory cell 150 and a functional element 155 will be described below. Fig. 2A is a plan view of the memory cell 150, and Fig. 2B is a schematic cross-sectional view taken along the cutting line A1-A2 in Fig. 2A. Fig. 2C is a plan view of the functional element 155, and Fig. 2D is a schematic cross-sectional view taken along the cutting line A3-A4 in Fig. 2C. Note that some elements are omitted from the plan views of Figs. 2A and 2C for clarity.

[0060] The memory device includes an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell 150 and a functional element 155 on the conductor 110, an insulator 180 and an insulator 280 on the conductor 110, and an insulator 283 on the memory cell 150 and the functional element 155. The insulators 140, 180, 280, and 283 function as interlayer films. The conductor 110 functions as a wiring. Note that the conductor 110 electrically connected to the memory cell 150 and the conductor 110 electrically connected to the functional element 155 may function as independent wirings, or may be electrically connected to each other. Similarly, the conductor 240 and the conductor 260 of the memory cell 150 and the conductive layer 240 and the conductive layer 260 of the functional element 155 may function as independent wirings, or two or more of them may be electrically connected to each other.

[0061] The memory cell 150 includes a capacitor 100 over a conductor 110 and a transistor 200 over the capacitor 100. The functional element 155 includes a connection portion 101 over the conductor 110 and the transistor 200 over the connection portion 101.

[0062] The capacitor 100 has a conductor 115 on the conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130. The conductor 120 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductor 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulator 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0063] As shown in FIG. 2B , the insulator 180 has an opening 190 that reaches the conductor 110. At least a portion of the conductor 115 is disposed in the opening 190. The conductor 115 has a region that contacts the upper surface of the conductor 110 in the opening 190, a region that contacts the side surface of the insulator 180 in the opening 190, and a region that contacts at least a portion of the upper surface of the insulator 180. The insulator 130 is disposed so that at least a portion of it is located in the opening 190. The conductor 120 is disposed so that at least a portion of it is located in the opening 190. As shown in FIG. 2B , the conductor 120 is preferably disposed so as to fill the opening 190.

[0064] 3A is a plan view selectively showing the conductor 110, the conductor 115, the conductor 120, and the opening 190. The opening 190 provided in the insulator 180 is indicated by a dashed line. As shown in FIG. 3A, the conductor 115 has the opening 190 in a region overlapping with the conductor 110.

[0065] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface of the opening 190, making it possible to increase the capacitance per unit area. Therefore, the deeper the opening 190, the greater the capacitance of the capacitor 100. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device.

[0066] The sidewall of the opening 190 is preferably perpendicular to the upper surface of the conductor 110. In this case, the opening 190 has a cylindrical shape. By adopting such a configuration, miniaturization or high integration of the memory device can be achieved.

[0067] A conductor 115 and an insulator 130 are stacked along the sidewall of the opening 190 and the upper surface of the conductor 110. In addition, a conductor 120 is provided on the insulator 130 so as to fill the opening 190. The capacitor element 100 having such a configuration may be called a trench-type capacitor or a trench capacitor.

[0068] An insulator 280 is disposed on the capacitor element 100. That is, the insulator 280 is disposed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is disposed below the insulator 280.

[0069] The transistor 200 includes a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. The oxide semiconductor 230 functions as a semiconductor layer, the conductor 260 functions as a gate electrode, the insulator 250 functions as a gate insulator, the conductor 120 functions as one of a source electrode and a drain electrode, and the conductor 240 functions as the other of the source electrode and the drain electrode.

[0070] As shown in FIG. 2B , the insulator 280 and the conductor 240 have openings 290 that reach the conductor 120. At least a portion of the oxide semiconductor 230 is disposed in the openings 290. Note that the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 in the openings 290, a region in contact with the side surface of the conductor 240 in the openings 290, and a region in contact with at least a portion of the top surface of the conductor 240. The insulator 250 is disposed so that at least a portion of it is located in the openings 290. The conductor 260 is disposed so that at least a portion of it is located in the openings 290. Note that the conductor 260 is preferably disposed so as to fill the openings 290, as shown in FIG. 2B .

[0071] 3B is a plan view selectively illustrating the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290. Note that the opening 290 provided in the insulator 280 is indicated by a dashed line. As shown in FIG. 3B , the conductor 240 has the opening 290 in a region overlapping with the conductor 120. Furthermore, it is preferable that the conductor 240 is not provided inside the opening 290. In other words, it is preferable that the conductor 240 does not have a region in contact with the side surface of the insulator 280 on the opening 290 side.

[0072] The oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with part of the top surface of the conductor 240. When the oxide semiconductor 230 is in contact with not only the side surface but also the top surface of the conductor 240 in this manner, the area in which the oxide semiconductor 230 and the conductor 240 are in contact can be increased.

[0073] As shown in FIG. 2B , the transistor 200 is provided so as to overlap with the capacitor 100. Furthermore, an opening 290 in which part of the structure of the transistor 200 is provided overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. In particular, the conductor 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the storage device. In other words, the storage device can be highly integrated.

[0074] 2C and 2D includes a transistor 200 and a connection portion 101. The transistor 200 has a configuration similar to that of the memory cell 150. The functional element 155 has a configuration generally similar to that of the memory cell 150, except that the configuration of the insulator 130 is different, the functional element 155 includes an insulator 131, and the conductor 115 and the conductor 120 are in contact with each other.

[0075] In the functional element 155, an opening overlapping the opening 190 is provided in the insulator 130. The opening of the insulator 130 is preferably provided so as to encompass the opening 190. That is, in a plan view, the opening 190 is preferably located inside the opening of the insulator 130.

[0076] Furthermore, inside the opening 190, an insulator 131 is provided along a portion of the conductor 115 that is provided along the inner wall of the insulator 180. The insulator 131 is in contact with the conductor 115 and the conductor 120. The insulators 130 and 131 are formed by processing the same insulating film and contain the same elements. The insulator 131 is formed when a portion of the insulator 130 located at the bottom of the opening 190 is removed by anisotropic etching, with part of the insulator 130 remaining. The insulator 131 can also be referred to as a sidewall insulator.

[0077] Note that the insulator 131 may not be formed depending on the processing method of the insulating film that becomes the insulator 130. In that case, the contact area between the conductor 120 and the conductor 115 becomes large, which is preferable.

[0078] [Capacitor 100] The capacitor 100 includes a conductor 115, an insulator 130, and a conductor 120. The conductor 110 is provided below the conductor 115. The conductor 115 has a region in contact with the conductor 110.

[0079] The conductor 110 is provided on the insulator 140. The conductor 110 functions as a wiring and can be provided in a planar shape, for example. The conductor 110 can be a single layer or a stacked layer of the conductors described in the section [Conductor] below. For example, the conductor 110 can be a conductive material with high conductivity, such as tungsten.

[0080] The conductor 115 is preferably made of a conductive material that is resistant to oxidation or a conductive material through which oxygen does not easily diffuse, and the like, in a single layer or a stacked layer. This can prevent an increase in resistance due to oxidation even when an oxide insulator is used for the insulators (insulators 130 and 180) in contact with the conductor 115. For example, nitrides such as titanium nitride and tantalum nitride may be used. Alternatively, oxides such as indium tin oxide or indium tin oxide with silicon added may be used. Alternatively, a stacked structure such as a structure in which titanium nitride is stacked on tungsten, or a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used.

[0081] The insulator 130 is provided on the conductor 115. The insulator 130 is provided so as to contact the top and side surfaces of the conductor 115. In other words, the insulator 130 is preferably structured to cover the side end portions of the conductor 110. This can prevent the conductor 115 and the conductor 120 from shorting out.

[0082] Alternatively, a structure may be used in which the side edge of the insulator 130 coincides with the side edge of the conductor 115. With such a structure, the insulator 130 and the conductor 115 can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

[0083] It is preferable to use a material with a high relative dielectric constant, a so-called high-k material, as described in the section [Insulator] below, as the insulator 130. By using a high-k material as the insulator 130, the insulator 130 can be made thick enough to suppress leakage current and the capacitance of the capacitor element 100 can be sufficiently ensured.

[0084] Furthermore, the insulator 130 is preferably a laminate of insulators made of high-k materials, and preferably a laminate structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material is used. For example, the insulator 130 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order. Alternatively, the insulator 130 can be an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order. Alternatively, the insulator 130 can be an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0085] Furthermore, a material exhibiting ferroelectricity may be used as the insulator 130. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide doped with element J1 (here, element J1 is one or more elements selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). The ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide doped with element J2 (here, element J2 is one or more elements selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). The ratio of the number of zirconium atoms to the number of element J2 atoms can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0086] Furthermore, examples of materials exhibiting ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials exhibiting ferroelectricity include materials obtained by adding element M3 to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0087] Furthermore, as a material exhibiting ferroelectricity, SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0088] Although the above description has been given with reference to metal oxides and metal nitrides, the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0089] Furthermore, the ferroelectric material may be, for example, a mixture or compound of multiple materials selected from the materials listed above. Alternatively, the insulator 130 may have a layered structure made of multiple materials selected from the materials listed above. The crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification, the term "ferroelectric" may refer not only to materials that exhibit ferroelectricity or materials that exhibit ferroelectricity, but also to materials that can have ferroelectricity.

[0090] Metal oxides containing one or both of hafnium and zirconium are preferable because they can exhibit ferroelectricity even when processed into a thin film of a few nanometers. Here, the film thickness of the insulator 130 is 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0091] Furthermore, a metal oxide containing one or both of hafnium and zirconium is preferable because it can exhibit ferroelectricity even in a small area. ２ Below, 10μm ２ Below, 1μm ２ Below, 0.1 μm ２ Below, 10000nm ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0092] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0093] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, the manifestation of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer, and the insulator 130 must contain crystals to manifest ferroelectricity. In particular, the insulator 130 preferably contains crystals having an orthorhombic crystal structure, since this manifests ferroelectricity. The crystal structure of the crystals contained in the insulator 130 may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, monoclinic, and hexagonal. The insulator 130 may also have an amorphous structure. In this case, the insulator 130 may have a composite structure having an amorphous structure and a crystalline structure.

[0094] The conductor 120 is provided in contact with a portion of the upper surface of the insulator 130. Furthermore, as shown in FIG. 2B , the side end of the conductor 120 is preferably located more inward than the side end of the conductor 115 in both the X direction and the Y direction. Note that in a structure in which the insulator 130 covers the side end of the conductor 115, the side end of the conductor 120 may be located more outward than the side end of the conductor 115.

[0095] The conductor 120 can be a single layer or a stack of conductors described in the section [Conductor] below. It is preferable to use a conductive material that is resistant to oxidation or a conductive material through which oxygen does not easily diffuse as the conductor 120. For example, titanium nitride or tantalum nitride can be used. Alternatively, for example, a structure in which tantalum nitride is stacked on titanium nitride may be used. In this case, the titanium nitride is in contact with the insulator 130, and the tantalum nitride is in contact with the oxide semiconductor 230. This structure can prevent the conductor 120 from being excessively oxidized by the oxide semiconductor 230. Furthermore, when an oxide insulator is used as the insulator 130, the insulator 130 can prevent the conductor 120 from being excessively oxidized. Alternatively, the conductor 120 may have a structure in which tungsten is stacked on titanium nitride, for example.

[0096] Furthermore, since the conductor 120 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section [Conductor] described later. By using a conductive material containing oxygen as the conductor 120, the conductor 120 can maintain its conductivity even when it absorbs oxygen. Furthermore, even when an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 is preferable because it can maintain its conductivity. For example, indium tin oxide (also referred to as ITO), indium tin oxide doped with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), or the like can be used as the conductor 120 in a single layer or a stacked layer.

[0097] Since the insulator 180 functions as an interlayer film, it preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. As the insulator 180, an insulator containing a material with a low dielectric constant, as described in the [Insulator] section below, can be used in a single layer or a stacked layer. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In this case, the insulator 180b contains at least silicon and oxygen.

[0098] 2B and 2D, the insulator 180 is shown as a single layer, but the present invention is not limited to this. The insulator 180 may have a multilayer structure.

[0099] For example, as shown in FIGS. 4A and 4B, the insulator 180 may have a laminated structure of an insulator 180a and an insulator 180b on the insulator 180a.

[0100] The insulator 180b may be made of any of the insulating materials applicable to the insulator 180 described above.

[0101] For the insulator 180a, it is preferable to use an insulator having oxygen barrier properties, as described in the section [Insulator] below. When the insulator 180b comes into contact with the conductor 110, the oxygen contained in the insulator 180b may oxidize the conductor 110, resulting in an increase in resistance. For this reason, it is preferable to provide the insulator 180a between the insulator 180b and the conductor 110.

[0102] If impurities such as hydrogen are mixed into the insulator 130, the leakage current occurring between the upper electrode and the lower electrode may increase. Furthermore, when a ferroelectric material is used as the insulator 130, the inclusion of impurities such as hydrogen in the ferroelectric material may reduce the crystallinity of the ferroelectric material. Therefore, it is preferable to prevent impurities such as hydrogen from being mixed into the insulator 130.

[0103] Therefore, it is preferable to use an insulator having a barrier property against hydrogen, as described in the section [Insulator] below, for the insulator 180a. This can prevent hydrogen from diffusing into the insulator 130 through the insulator 180b and the conductor 115. Silicon nitride and silicon nitride oxide each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulator 180a. In this case, the insulator 180a contains at least silicon and nitrogen.

[0104] Furthermore, it is preferable to use, as the insulator 180a, an insulator having a function of capturing or fixing hydrogen, as described in the section [Insulator] below. With such a structure, hydrogen in the insulator 130 can be captured or fixed, thereby reducing the hydrogen concentration in the insulator 130. Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used as the insulator 180a. For example, the insulator 180a may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0105] 4A and 4B show the insulator 180 having a two-layer stacked structure, one embodiment of the present invention is not limited to this. The insulator 180 may have a three or more layer stacked structure.

[0106] For example, when the insulator 180 has a three-layer structure, in addition to the insulators 180a and 180b, an insulator may be provided between the conductor 115 and the insulator 130 and the insulator 180b. An insulator that can be used for the insulator 180a can be used as the insulator. This can prevent hydrogen from diffusing into the insulator 130 through the insulator 180b.

[0107] 4A and 4B, it is preferable to provide an insulator 185 between the conductor 115 and the insulator 180. It is also preferable that the insulator 185 be provided so as to contact the side surface of the insulator 180 at the opening 190. In other words, it is preferable that the insulator 185 be provided between the side surface of the insulator 180 at the opening 190 and the conductor 115.

[0108] The insulator 185 is preferably an insulator having a barrier property against hydrogen as described above. This can prevent hydrogen from diffusing from the outside of the capacitor 100 to the insulator 130 through the insulator 180. Furthermore, the insulator 185 is preferably an insulator having a function of capturing or fixing hydrogen as described above. This can capture or fix hydrogen in the insulator 130, thereby reducing the hydrogen concentration in the insulator 130.

[0109] 4A and 4B, the insulator 185 is provided so as to contact the side surface of the insulator 180a in the opening 190 and the side surface of the insulator 180b in the opening 190, but the present invention is not limited to this. For example, as shown in Figures 4C and 4D, the insulator 185 may be provided so as to contact a part of the upper surface of the insulator 180a and the side surface of the insulator 180b in the opening 190.

[0110] 2B and 2D, the conductor 120 is located inside the conductor 115 with the insulator 130 interposed therebetween, but the present invention is not limited to this. For example, the conductor 120 may be located outside the conductor 115 with the insulator 130 interposed therebetween.

[0111] For example, as shown in Figures 5A and 5B, insulator 130 has a region that contacts the inside of the recess of conductor 115, a region that contacts the top surface of conductor 115, and a region that is located on the outer side of conductor 115.

[0112] The conductor 120 is provided so as to fill the recess of the conductor 115 with the insulator 130 interposed therebetween. Furthermore, the conductor 120 has a region facing a part of the outer side surface of the conductor 115 with the insulator 130 interposed therebetween.

[0113] By adopting the above-described configuration, the capacitance per unit area can be increased.

[0114] As shown in FIGS. 5A and 5B, an insulator 135 may be provided between the outer side surface of the conductor 115 and the insulators 130 and 180.

[0115] An insulator 182 may be provided over the conductor 120 and the insulator 130. Planarization treatment is preferably performed on the insulator 182 so that the top surface of the conductor 120 is exposed. By performing planarization treatment on the insulator 182, the transistor 200 can be suitably formed over the capacitor 100.

[0116] The insulator 182 preferably has a low dielectric constant because it functions as an interlayer film. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulator 182, an insulator applicable to the insulator 180 can be used.

[0117] As shown in Figures 5A and 5B, if a configuration in which conductor 120 is provided facing the inside and outside of conductor 115 can ensure sufficient capacitance as a memory cell, the configuration may not require insulator 180.

[0118] 5C and 5D differ from the memory device illustrated in FIG. 5A and 5B in that the insulator 180b is not provided. By not providing the insulator 180b, the manufacturing process of the memory device can be simplified.

[0119] [Transistor 200] As shown in FIGS. 2A to 2D , the transistor 200 can have a structure including a conductor 120, a conductor 240 on an insulator 280, an oxide semiconductor 230 provided in contact with at least a part of the top surface of the conductor 120 exposed in an opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the top surface of the conductor 240, an insulator 250 provided in contact with the top surface of the oxide semiconductor 230, and a conductor 260 provided in contact with the top surface of the insulator 250.

[0120] At least some of the components of the transistor 200 are disposed in the opening 290. Here, the bottom of the opening 290 is the top surface of the conductor 120, and the sidewalls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240.

[0121] The sidewall of the opening 290 is preferably perpendicular to the upper surface of the conductor 110. In this case, the opening 290 has a cylindrical shape. By adopting such a configuration, miniaturization or high integration of the memory device can be achieved.

[0122] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. For example, the opening 290 may be circular, elliptical, rectangular, or other shapes in plan view. It may also be a regular polygon, such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon. Furthermore, a concave polygon, such as a star-shaped polygon, in which at least one interior angle exceeds 180 degrees, can increase the channel width. Other shapes include an ellipse, a polygon with rounded corners, and a closed curve combining straight and curved lines. In this case, the maximum width of the opening 290 may be calculated appropriately according to the shape of the top of the opening 290. For example, if the opening is square or rectangular in plan view, the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.

[0123] The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290. Thus, the oxide semiconductor 230 is provided so as to cover the bottom and sidewall of the opening 290, the insulator 250 is provided so as to cover the oxide semiconductor 230, and the conductor 260 is provided so as to fill the recess of the insulator 250 that reflects the shape of the opening 290.

[0124] 6A shows an enlarged view of the oxide semiconductor 230 and its vicinity in FIG. 2B. FIG. 6B shows a cross-sectional view in the XY plane including the conductor 240.

[0125] As illustrated in FIG. 6A, the oxide semiconductor 230 includes a region 230i and regions 230na and 230nb that sandwich the region 230i.

[0126] The region 230na is a region of the oxide semiconductor 230 that is in contact with the conductor 120. At least a part of the region 230na functions as one of the source region and the drain region of the transistor 200. The region 230nb is a region of the oxide semiconductor 230 that is in contact with the conductor 240. At least a part of the region 230nb functions as the other of the source region and the drain region of the transistor 200. As shown in FIG. 6B , the conductor 240 is in contact with the entire periphery of the oxide semiconductor 230. Thus, the other of the source region and the drain region of the transistor 200 can be formed on the entire periphery of a portion of the oxide semiconductor 230 that is formed in the same layer as the conductor 240.

[0127] The region 230i is a region between the regions 230na and 230nb in the oxide semiconductor 230 and functions as a channel formation region. The channel formation region of the transistor 200 can also be referred to as a region in contact with the insulator 280 or a region in the vicinity of the insulator 280.

[0128] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, the channel length of the transistor 200 can be determined by the thickness of the insulator 280 on the conductor 120. In FIG. 6A , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the oxide semiconductor 230 and the conductor 120 contact each other and the edge of the region where the oxide semiconductor 230 and the conductor 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in a cross-sectional view.

[0129] In a planar transistor, the channel length is set by the exposure limit of photolithography. However, in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving frequency characteristics. Therefore, the read speed and write speed of the memory cell 150 can be improved, and a memory device with high operating speed can be provided.

[0130] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This allows the area occupied by the transistor 200 to be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for higher integration of the memory device, thereby increasing the memory capacity per unit area.

[0131] 6A and 6B , the maximum width D of the opening 290 (or the diameter if the opening 290 is circular in plan view) is determined. In FIGS. 6A and 6B , the maximum width D of the opening 290 is indicated by a double-headed, dashed arrow. In FIG. 6B , the channel width W of the transistor 200 is indicated by a double-headed, dashed arrow. Increasing the maximum width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current.

[0132] When the opening 290 is formed by photolithography, the maximum width D of the opening 290 is set by the exposure limit of photolithography. The maximum width D of the opening 290 is set by the film thickness of each of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290. The maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 has a circular shape in a plan view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0133] In the memory device of one embodiment of the present invention, the channel length L of the transistor 200 is preferably smaller than at least the channel width W of the transistor 200. The channel length L of the transistor 200 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0134] Furthermore, by forming the opening 290 so as to have a circular shape in a plan view, the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged concentrically. This makes the distance between the conductor 260 and the oxide semiconductor 230 approximately uniform, allowing a gate electric field to be applied to the oxide semiconductor 230 approximately uniformly.

[0135] It is preferable that the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ H) and generate electrons that become carriers. Therefore, in the channel formation region, V Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0136] In addition, the source and drain regions of a transistor using an oxide semiconductor for a semiconductor layer have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of a transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, and metal elements.

[0137] 2B and 2D, the opening 290 is provided so that the sidewall of the opening 290 is perpendicular to the upper surface of the conductor 110, but the present invention is not limited to this. For example, the sidewall of the opening 290 may have a tapered shape.

[0138] The storage device shown in Figures 7A and 7B has a configuration in which the side walls of the opening 290 are tapered. Note that Figure 2A can be referred to for the plan views of the storage device shown in Figures 7A and 7B.

[0139] By tapering the sidewall of the opening 290, coverage by the oxide semiconductor 230, the insulator 250, or the like can be improved, and defects such as voids can be reduced. For example, the angle formed between the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120 (angle θ1 shown in FIG. 7A ) is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.

[0140] In this specification, a tapered shape refers to a shape in which at least a portion of the side of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, the angle between the inclined side and the substrate surface (hereinafter, sometimes referred to as the taper angle) is less than 90 degrees. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be substantially planar with a slight curvature or a slight unevenness.

[0141] 7A and 7B has a truncated cone shape. In this case, the opening 290 is circular in a plan view and trapezoidal in a cross-sectional view. The area of ​​the upper base of the truncated cone (e.g., the opening provided in the conductor 240) is smaller than the area of ​​the lower base of the truncated cone (the upper surface of the conductor 120 exposed at the opening 290). In this case, the maximum diameter of the opening 290 may be calculated based on the upper base of the truncated cone.

[0142] When the sidewall of the opening 290 has a tapered shape, the channel length can be set by the film thickness of the insulator 280 and the angle θ1 formed between the side surface of the insulator 280 at the opening 290 and the top surface of the conductor 120. The perimeter of the oxide semiconductor 230 may be determined, for example, in a region facing the conductor 240 or at a position halfway through the film thickness of the insulator 280. Note that the perimeter at any position of the opening 290 may be the channel width of the transistor 200 as needed. For example, the perimeter at the bottom of the opening 290 may be the channel width, or the perimeter at the top of the opening 290 may be the channel width.

[0143] 7A and 7B show a configuration in which the side surface of the conductor 240 in the opening 290 coincides with the side surface of the insulator 280 in the opening 290, but the present invention is not limited to this. For example, the side surface of the conductor 240 in the opening 290 may be discontinuous with the side surface of the insulator 280 in the opening 290. The inclination of the side surface of the conductor 240 in the opening 290 may differ from the inclination of the side surface of the insulator 280 in the opening 290. For example, the angle formed between the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 120 is preferably smaller than angle θ1. Such a configuration improves coverage of the oxide semiconductor 230 on the side surface of the conductor 240 in the opening 290, thereby reducing defects such as voids.

[0144] As shown in Figures 7A and 7B, the bottom of the conductor 260 located in the opening 290 has a flat region. Note that depending on the maximum width of the opening 290 (the diameter when the opening 290 is circular in plan view), the film thickness of the insulator 280 (corresponding to the depth of the opening 290), the film thickness of the oxide semiconductor 230, and the film thickness of the insulator 250, the bottom of the conductor 260 located in the opening 290 may not have a flat region. For example, as shown in Figures 7C and 7D, the shape of the bottom of the conductor 260 located in the opening 290 may be needle-like. Note that Figure 2A can be referred to for the plan views of the memory device shown in Figures 7C and 7D.

[0145] Here, the term "needle-shaped" refers to a shape that becomes thinner as it approaches the tip (approaching the bottom of the conductor 260 located in the opening 290). The tip of the needle may be acute-angled or may have a downwardly convex curved shape. Among needle-shaped shapes, a shape with an acute-angled tip may be called a V-shape.

[0146] Of the conductor 260 located in the opening 290, a region facing the oxide semiconductor 230 with the insulator 250 interposed therebetween functions as a gate electrode. Therefore, the conductor 260 that fills the opening 290 and has a needle-shaped bottom may be referred to as a needle-shaped gate. Furthermore, as shown in FIGS. 7A and 7B , even if the conductor 260 has a shape with a flat bottom, it may also be referred to as a needle-shaped gate in some cases.

[0147] 2B and 2D, the opening 190 is provided so that the sidewall of the opening 190 is perpendicular to the upper surface of the conductor 110, but the present invention is not limited to this. For example, like the opening 290, the sidewall of the opening 190 may have a tapered shape or a reverse tapered shape.

[0148] By tapering the sidewall of the opening 190, the coverage of the conductor 115 or the insulator 130 can be improved, and defects such as voids can be reduced. For example, the angle formed between the side surface of the insulator 180 in the opening 190 and the top surface of the conductor 110 (angle θ2 shown in FIG. 7A ) is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.

[0149] As shown in Figures 7A and 7B, the bottom of the conductor 120 located in the opening 190 has a flat region. Note that depending on the maximum width of the opening 190 (the diameter if the opening 190 is circular in plan view), the film thickness of the insulator 180 (corresponding to the depth of the opening 190), the film thickness of the conductor 115, and the film thickness of the insulator 130, the bottom of the conductor 120 located in the opening 190 may not have a flat region. For example, as shown in Figures 7C and 7D, the shape of the bottom of the conductor 120 located in the opening 190 may be needle-like. Note that Figure 2A can be referred to for the plan views of the memory device shown in Figures 7C and 7D.

[0150] Furthermore, when the insulators 180 and 280 are made of the same material, the angles θ1 and θ2 are the same or approximately the same. Note that the angles θ1 and θ2 may be different depending on the materials used for the insulators 180 and 280, the methods for forming the openings 190 and 290, and the like. For example, the angle θ1 may be greater than or smaller than the angle θ2. Furthermore, one of the angles θ1 and θ2 may be 90 degrees or a value close to it.

[0151] Or, for example, the sidewalls of opening 290 may have a reverse tapered shape.

[0152] Here, the inverse tapered shape refers to a shape having a side or top that protrudes more than the bottom in a direction parallel to the substrate. In this case, the shape of the opening 290 is a truncated cone. In this case, the opening 290 is circular in a plan view and trapezoidal in a cross-sectional view. Furthermore, the area of ​​the upper bottom surface of the truncated cone (e.g., the opening provided in the conductor 240) is larger than the area of ​​the lower bottom surface of the truncated cone (the upper surface of the conductor 120 exposed in the opening 290). With this configuration, the area of ​​contact between the oxide semiconductor 230 and the conductor 120 can be increased.

[0153] 7B and 7D show an example in which the connection portion 101 of the functional element 155 does not have the insulator 131. In this way, when the sidewall of the opening 190 has a tapered shape, even if anisotropic etching is performed as an etching method for the insulator 130, the insulator 131 often does not remain. Not having the insulator 131 is preferable because it increases the contact area between the conductor 120 and the conductor 115 and reduces electrical resistance. Note that the sidewall of the opening 190 may have a tapered shape and may have the insulator 131.

[0154] 2B and 2D, a portion of the oxide semiconductor 230 is located outside the opening 290, i.e., above the conductor 240. Note that while FIG. 2B shows a configuration in which the oxide semiconductor 230 is divided in the X direction, the present invention is not limited to this. For example, as shown in FIGS. 8A and 8B, the oxide semiconductor 230 may be provided extending in the X direction. Note that even in the configurations shown in FIGS. 8A and 8B, the oxide semiconductor 230 is divided in the Y direction.

[0155] The band gap of the metal oxide used for the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a low off-state current in a memory cell, stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. While a typical DRAM requires a refresh operation frequency of approximately once every 60 msec, the memory device of one embodiment of the present invention can perform a refresh operation frequency of approximately once every 10 sec, which is 10 times or more or 100 times or more higher. In the memory device of one embodiment of the present invention, the refresh operation can be performed every 1 sec to 100 sec, preferably once every 5 sec to 50 sec.

[0156] Note that as the oxide semiconductor 230, a metal oxide described in the section [Metal Oxide] below can be used as a single layer or a stacked layer.

[0157] Specifically, the oxide semiconductor 230 may be a metal oxide having an atomic ratio of In:M:Zn = 1:3:2 or a composition thereof, an atomic ratio of In:M:Zn = 1:3:4 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:0.5 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:1 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:1.2 or a composition thereof, an atomic ratio of In:M:Zn = 1:1:2 or a composition thereof, or an atomic ratio of In:M:Zn = 4:2:3 or a composition thereof. Note that a composition having an atomic ratio in the vicinity thereof includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0158] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0159] For example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used to analyze the composition of the metal oxide used in the oxide semiconductor 230. Alternatively, a combination of these techniques may be used for the analysis. For elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0160] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may be reduced to about 50% of that of the sputtering target.

[0161] The oxide semiconductor 230 preferably has crystallinity. Examples of crystalline oxide semiconductors include c-axis aligned crystalline oxide semiconductor (CAAC-OS), nanocrystalline oxide semiconductor (nc-OS), polycrystalline oxide semiconductor, single-crystalline oxide semiconductor, and the like. It is preferable to use a CAAC-OS or an nc-OS as the oxide semiconductor 230, and it is particularly preferable to use a CAAC-OS.

[0162] The CAAC-OS preferably has multiple layered crystalline regions whose c-axes are oriented in the normal direction to the surface where the oxide semiconductor 230 is formed. For example, the oxide semiconductor 230 preferably has layered crystals that are substantially parallel to the sidewall of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 230 are formed substantially parallel to the channel length direction of the transistor 200, which enables the on-state current of the transistor to be increased.

[0163] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide is not polycrystallized after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0164] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0165] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, it is possible to suppress extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode. Thus, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0166] The crystallinity of the oxide semiconductor 230 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0167] 2B and 2D, the oxide semiconductor 230 is shown as a single layer, but the present invention is not limited to this. The oxide semiconductor 230 may have a stacked structure of multiple oxide layers with different chemical compositions. For example, the oxide semiconductor 230 may have a structure in which multiple types of oxides selected from the above metal oxides are appropriately stacked.

[0168] For example, as shown in FIGS. 9A and 9B, the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b on the oxide semiconductor 230a.

[0169] The conductivity of the material used for the oxide semiconductor 230a is preferably different from the conductivity of the material used for the oxide semiconductor 230b.

[0170] For example, the oxide semiconductor 230a can be made of a material having higher conductivity than the oxide semiconductor 230b. By using a material having high conductivity for the oxide semiconductor 230a which is in contact with the conductor 120 and the conductor 240 which function as a source electrode or a drain electrode, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with high on-state current can be obtained.

[0171] Here, if a material with high conductivity is used for the oxide semiconductor 230b provided on the conductor 260 side functioning as the gate electrode, the threshold voltage of the transistor may shift, and the drain current that flows when the gate voltage is 0 V (hereinafter also referred to as cutoff current) may become large. Specifically, if the transistor 200 is an n-channel transistor, the threshold voltage may be reduced. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b. As a result, if the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current is sometimes referred to as a normally-off transistor.

[0172] As described above, by using a material having higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a normally-off transistor with a large on-state current can be obtained. Therefore, a memory device with both low power consumption and high performance can be provided.

[0173] Note that the carrier concentration of the oxide semiconductor 230a is preferably higher than that of the oxide semiconductor 230b. Increasing the carrier concentration of the oxide semiconductor 230a increases the conductivity, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, resulting in a transistor with a large on-state current. Reducing the carrier concentration of the oxide semiconductor 230b decreases the conductivity, resulting in a normally-off transistor.

[0174] Here, an example is shown in which the oxide semiconductor 230a is made of a material having higher conductivity than the oxide semiconductor 230b, but one embodiment of the present invention is not limited to this. The oxide semiconductor 230a may be made of a material having lower conductivity than the oxide semiconductor 230b. The carrier concentration of the oxide semiconductor 230a can be lower than the carrier concentration of the oxide semiconductor 230b.

[0175] The band gap of the first metal oxide used in the oxide semiconductor 230 a is preferably different from the band gap of the second metal oxide used in the oxide semiconductor 230 b. For example, the difference between the band gaps of the first metal oxide and the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0176] The band gap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used for the oxide semiconductor 230b. As a result, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and the transistor can have a large on-state current. Furthermore, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.

[0177] Although an example in which the band gap of the first metal oxide is smaller than that of the second metal oxide is shown here, one embodiment of the present invention is not limited thereto. The band gap of the first metal oxide may be larger than that of the second metal oxide.

[0178] As described above, the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b. The composition of the first metal oxide is preferably different from that of the second metal oxide. The band gap can be controlled by differentiating the compositions of the first metal oxide and the second metal oxide. For example, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. Specifically, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or a similar ratio, and the second metal oxide can have a composition of In:M:Zn=1:3:2 (atomic ratio) or a similar ratio. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M.

[0179] The first metal oxide may not contain the element M. For example, the first metal oxide used for the oxide semiconductor 230a may be an In—Zn oxide, and the second metal oxide used for the oxide semiconductor 230b may be an In-M-Zn oxide. Specifically, the first metal oxide may be an In—Zn oxide, and the second metal oxide may be an In—Ga—Zn oxide. More specifically, the first metal oxide may have an atomic ratio of In:Zn=1:1 or a ratio thereof therebetween, or an atomic ratio of In:Zn=4:1 or a ratio thereof therebetween, and the second metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a ratio thereof therebetween.

[0180] Here, an example is shown in which the content of the element M in the first metal oxide is lower than the content of the element M in the second metal oxide, but one embodiment of the present invention is not limited to this. The content of the element M in the first metal oxide may be higher than the content of the element M in the second metal oxide. Note that the first metal oxide and the second metal oxide may have different compositions, and the contents of elements other than the element M may be different.

[0181] The thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0182] The thickness of each layer (here, the oxide semiconductor 230a and the oxide semiconductor 230b) constituting the oxide semiconductor 230 may be determined so that the thickness of the oxide semiconductor 230 falls within the above-described range. The thickness of the oxide semiconductor 230a can be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 fall within the desired range. The thickness of the oxide semiconductor 230b can be determined so that the threshold voltage of the transistor falls within the desired range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.

[0183] 9A and 9B show a configuration in which the oxide semiconductor 230 has a two-layer stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b, but the present invention is not limited to this. The oxide semiconductor 230 may have a three-layer or more stacked structure.

[0184] When the oxide semiconductor 230 has a three-layer structure, for example, a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereof near the conductor 120 side may be provided, in this order from the conductor 120 side. This structure enables the transistor 200 to have a high on-state current and a highly reliable transistor structure with little variation.

[0185] The insulators described in the section [Insulator] below can be used as a single layer or a stacked layer as the insulator 250. For example, silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferable because they are stable to heat.

[0186] Furthermore, a material with a high relative dielectric constant, a so-called high-k material, which will be described later in the section [Insulator], may be used as the insulator 250. For example, hafnium oxide or aluminum oxide may be used.

[0187] The thickness of the insulator 250 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. The insulator 250 may have a region with the above thickness in at least a portion thereof.

[0188] The concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.

[0189] 2B and 2D , a portion of the insulator 250 is located outside the opening 290, i.e., on the conductor 240 and the insulator 280. In this case, the insulator 250 preferably covers the side edge of the oxide semiconductor 230. This can prevent the conductor 260 and the oxide semiconductor 230 from shorting out. The insulator 250 also preferably covers the side edge of the conductor 240. This can prevent the conductor 260 and the conductor 240 from shorting out.

[0190] 2B and 2D, the insulator 250 is shown as a single layer, but the present invention is not limited to this. The insulator 250 may have a multilayer structure.

[0191] For example, as shown in FIGS. 9A and 9B, the insulator 250 may have a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

[0192] It is preferable that the insulator 250b be made of a material with a low dielectric constant as described above. Silicon oxide and silicon oxynitride are particularly preferable because they are stable against heat. This reduces the parasitic capacitance between the conductor 260 and the conductor 240. It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 250b be reduced.

[0193] The insulator 250a is preferably an insulator having a barrier property against oxygen as described above. The insulator 250a is in contact with the oxide semiconductor 230, and thus has a barrier property against oxygen. This can prevent oxygen from being released from the oxide semiconductor 230 and prevent oxygen vacancies from being formed in the oxide semiconductor 230 during heat treatment or the like. This can improve the electrical characteristics and reliability of the transistor 200. For example, aluminum oxide is preferably used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.

[0194] The insulator 250c is preferably an insulator having a barrier property against hydrogen, as described above. This can prevent impurities contained in the conductor 260 from diffusing into the oxide semiconductor 230. Silicon nitride is particularly suitable for the insulator 250c because it has a high barrier property against hydrogen.

[0195] The insulator 250c may further have a barrier property against oxygen. The insulator 250c is provided between the insulator 250b and the conductor 260. Therefore, the oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Furthermore, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.

[0196] Alternatively, an insulator may be provided between the insulator 250b and the insulator 250c. The above-described insulator having a function of trapping or fixing hydrogen is preferably used as the insulator. In this way, hydrogen contained in the oxide semiconductor 230 can be trapped or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor 230.

[0197] In order to miniaturize the transistor 200, the thicknesses of the insulators 250a to 250c are preferably small and preferably within the above-described range. Typically, the thicknesses of the insulator 250a, the insulator 250b, the insulator having a function of capturing or fixing hydrogen, and the insulator 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor 200 can have good electrical characteristics even when miniaturized or highly integrated.

[0198] 9A and 9B show the insulator 250 having a three-layer structure of insulators 250a to 250c, but the present invention is not limited to this. The insulator 250 may have a two-layer structure or a four-layer or more layer structure. In this case, each layer included in the insulator 250 may be appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.

[0199] A single layer or a stack of conductors described in the section [Conductor] below can be used as the conductor 260. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductor 260.

[0200] It is also preferable to use a conductive material that is resistant to oxidation or a conductive material through which oxygen is resistant to diffusion as the conductor 260. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can prevent the conductivity of the conductor 260 from decreasing.

[0201] 2B and 2D, the conductor 260 is shown as a single layer, but the present invention is not limited to this. The conductor 260 may have a laminated structure. For example, as shown in FIGS. 9A and 9B, the conductor 260 may have a laminated structure of a conductor 260a and a conductor 260b on the conductor 260a. In this case, for example, titanium nitride may be used as the conductor 260a, and tungsten may be used as the conductor 260b. By providing tungsten in a laminated structure in this manner, the conductivity of the conductor 260 can be improved, allowing it to function sufficiently as the wiring WL.

[0202] 9A and 9B show a configuration in which the conductor 260 has a two-layer structure of the conductor 260a and the conductor 260b, but the present invention is not limited to this. The conductor 260 may have a three or more layer structure.

[0203] 2B and 2D , the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this. For example, a recess that reflects the shape of the opening 290 may be formed in the center of the conductor 260, and a part of the recess may be located in the opening 290. In this case, the recess may be filled with an inorganic insulating material or the like.

[0204] 2B and 2D , a portion of the conductor 260 is located outside the opening 290, that is, on the conductor 240 and the insulator 280. In this case, as shown in FIG. 2B , the side edge of the conductor 260 is preferably located inside the side edge of the oxide semiconductor 230. This can prevent a short circuit between the conductor 260 and the oxide semiconductor 230. Note that the side edge of the conductor 260 may coincide with the side edge of the oxide semiconductor 230, or may be located outside the side edge of the oxide semiconductor 230.

[0205] 2B and 2D show a configuration in which the top surface of the conductor 120 is flat, but the present invention is not limited to this. For example, a configuration in which a recess that overlaps with the opening 290 is formed on the top surface of the conductor 120 may be used. By forming at least a portion of the oxide semiconductor 230, the insulator 250, and the conductor 260 so as to fill the recess, it becomes easier to apply the gate electric field of the conductor 260 up to the vicinity of the conductor 120 on the oxide semiconductor 230.

[0206] A single layer or a multilayer of the conductors described in the section [Conductor] below can be used as the conductor 240. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductor 240.

[0207] Like the conductor 260, the conductor 240 is preferably made of a conductive material that is resistant to oxidation or a conductive material through which oxygen does not easily diffuse. For example, titanium nitride or tantalum nitride can be used. Such a structure can prevent the conductor 240 from being excessively oxidized by the oxide semiconductor 230. Alternatively, for example, a structure in which tungsten is stacked on titanium nitride may be used. Stacking tungsten in this manner improves the conductivity of the conductor 240, allowing it to function sufficiently as the wiring BL.

[0208] Furthermore, when the conductor 240 has a stacked structure of a first conductor and a second conductor, for example, the first conductor may be formed using a conductive material with high conductivity, and the second conductor may be formed using a conductive material containing oxygen. By using a conductive material containing oxygen as the second conductor of the conductor 240 that is in contact with the insulator 250, it is possible to prevent oxygen in the insulator 250 from diffusing into the first conductor of the conductor 240. For example, tungsten may be used as the first conductor of the conductor 240, and an oxide conductor may be used as the second conductor of the conductor 240. As the oxide conductor, ITO, ITSO, IZO (registered trademark), or the like may be used in a single layer or a stacked layer.

[0209] When the oxide semiconductor 230 and the conductor 120 come into contact with each other, a metal compound or oxygen vacancy is formed, and the resistance of a region 230na of the oxide semiconductor 230 decreases. When the oxide semiconductor 230 comes into contact with the conductor 120, the resistance of the region 230na of the oxide semiconductor 230 decreases, thereby reducing the contact resistance between the oxide semiconductor 230 and the conductor 120. Similarly, when the oxide semiconductor 230 and the conductor 240 come into contact with each other, the resistance of a region 230nb of the oxide semiconductor 230 decreases. Therefore, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.

[0210] Since the insulators 140 and 280 function as interlayer films, they preferably have a low dielectric constant. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. As the insulators 140 and 280, insulators containing the above-mentioned materials with a low dielectric constant can be used in a single layer or stacked layers. Silicon oxide and silicon oxynitride are preferred because they are thermally stable.

[0211] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulator 140 and the insulator 280. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.

[0212] The insulator 280 disposed near the channel formation region preferably contains oxygen that is released by heating (hereinafter may be referred to as excess oxygen). By performing heat treatment on the insulator 280 containing excess oxygen, oxygen is supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor 200 and improve its reliability.

[0213] Alternatively, the above-described insulator having a function of capturing or fixing hydrogen may be used as the insulator 280. With such a structure, hydrogen can be captured or fixed in the oxide semiconductor 230, thereby reducing the hydrogen concentration in the oxide semiconductor 230. As the insulator 280, magnesium oxide, aluminum oxide, or the like can be used.

[0214] 2B and 2D, the insulator 280 is shown as a single layer, but the present invention is not limited to this. The insulator 280 may have a multilayer structure.

[0215] For example, as shown in FIGS. 10A and 10B, the insulator 280 may have a layered structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b.

[0216] The insulator 280b preferably contains oxygen. The insulator 280b preferably has a region containing more oxygen than at least one of the insulators 280a and 280c. In particular, the insulator 280b preferably has a region containing more oxygen than each of the insulators 280a and 280c. Increasing the oxygen content of the insulator 280b facilitates the formation of an i-type region in the oxide semiconductor 230 in contact with the insulator 280b and in the vicinity thereof.

[0217] It is more preferable that the insulator 280b be a film that releases oxygen by heating. The insulator 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, and oxygen can be supplied to the oxide semiconductor 230. By supplying oxygen from the insulator 280b to the oxide semiconductor 230, particularly to the channel formation region of the oxide semiconductor 230, oxygen vacancies and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0218] For example, oxygen can be supplied to the insulator 280b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulator 280b by forming an oxide film on the top surface of the insulator 280b by a sputtering method in an oxygen atmosphere. The oxide film may then be removed.

[0219] The insulator 280b is preferably formed by a deposition method such as a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, when the insulator 280b is formed by a sputtering method without using hydrogen gas as a deposition gas, the hydrogen content can be extremely low. Therefore, the supply of hydrogen to the oxide semiconductor 230 can be suppressed, and the electrical characteristics of the transistor 200 can be stabilized.

[0220] When the channel length of the transistor 200 is short, oxygen vacancies in the channel formation region and V Ｏ The influence of H on the electrical characteristics and reliability is particularly large. By supplying oxygen from the insulator 280b to the oxide semiconductor 230, oxygen vacancies and V are reduced at least in the region of the oxide semiconductor 230 in contact with the insulator 280b. Ｏ It is possible to suppress an increase in H. Therefore, a transistor having a short channel length, good electrical characteristics, and high reliability can be realized.

[0221] The insulators 280a and 280c are preferably made of an insulator having a barrier property against oxygen, as described in the section [Insulator] below. This can prevent oxygen contained in the insulator 280b from diffusing to the substrate side through the insulator 280a and to the insulator 250 side through the insulator 280c due to heating. In other words, by sandwiching the insulator 280b from above and below with the insulators 280a and 280c, through which oxygen does not easily diffuse, the oxygen contained in the insulator 280b can be trapped. This allows oxygen to be effectively supplied to the oxide semiconductor 230.

[0222] Furthermore, oxygen contained in the insulator 280b may oxidize the conductor 120 and the conductor 240, resulting in an increase in resistance. By providing the insulator 280a between the insulator 280b and the conductor 120, it is possible to prevent the conductor 120 from being oxidized and the resistance from increasing. By providing the insulator 280c between the insulator 280b and the conductor 240, it is possible to prevent the conductor 240 from being oxidized and the resistance from increasing. At the same time, the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, thereby reducing oxygen vacancies in the oxide semiconductor 230.

[0223] Furthermore, the region of the oxide semiconductor 230 in contact with the insulator 280a and the region of the oxide semiconductor 230 in contact with the insulator 280c receives a smaller amount of oxygen than the region of the oxide semiconductor 230 in contact with the insulator 280b. Therefore, the region of the oxide semiconductor 230 in contact with the insulator 280a and the region of the oxide semiconductor 230 in contact with the insulator 280c may have low resistance. In other words, by adjusting the thickness of the insulator 280a, the range of the region 230na that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb that functions as the other of the source region and the drain region can be controlled.

[0224] As described above, the source and drain regions can be controlled by the film thickness of the insulators 280a and 280c, so the film thickness of the insulators 280a and 280c can be set appropriately to match the characteristics desired for the transistor 200.

[0225] For example, as shown in Figures 10A and 10B, the thickness of the insulator 280c may be approximately the same as the thickness of the insulator 280a. Alternatively, as shown in Figures 10C and 10D, the thickness of the insulator 280c may be smaller than the thickness of the insulator 280a. By using the configuration shown in Figures 10C and 10D, the region 230na can be brought closer to the bottom of the conductor 260 in the opening 290. This configuration can also be said to narrow the range of the region 230i. This can improve the on-current of the transistor 200.

[0226] 10C and 10D show a structure in which the insulator 280c is provided on the planarized insulator 280b, but the present invention is not limited to this. For example, the insulator 280c may be formed without performing planarization treatment on the insulator 280b. Eliminating the planarization treatment can reduce manufacturing costs and increase production yields. Furthermore, the insulators 280a, 280b, and 280c can be successively formed without exposure to the atmospheric environment. Forming the insulators 280a to 280c without exposing them to the atmospheric environment can prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and can keep the vicinity of the interface between the insulators 280a and 280b and the vicinity of the interface between the insulators 280b and 280c clean.

[0227] The insulator 280a and the insulator 280c are preferably made of the above-described insulator having a barrier property against hydrogen. This can prevent hydrogen from diffusing from the outside of the transistor to the oxide semiconductor 230 through the insulator 280a or the insulator 280c. A silicon nitride film and a silicon nitride oxide film are suitable for use as the insulator 280a and the insulator 280c because they release little impurities (e.g., water and hydrogen) and are less permeable to oxygen and hydrogen. Note that the insulator 280a and the insulator 280c may be made of the same material or different materials.

[0228] Furthermore, it is preferable to use the above-described insulator having the function of capturing hydrogen or fixing hydrogen as the insulator 280a. This can suppress diffusion of hydrogen from below the insulator 280a to the oxide semiconductor 230, and further capture or fix hydrogen in the oxide semiconductor 230, thereby reducing the hydrogen concentration in the oxide semiconductor 230. Furthermore, it can suppress diffusion of hydrogen from above the insulator 280a to the insulator 130, and further capture or fix hydrogen in the insulator 130, thereby reducing the hydrogen concentration in the insulator 130. Magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used as the insulator 280a. For example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 280a.

[0229] The thickness of the insulator 280a is preferably smaller than that of the insulator 280b. The thickness of the insulator 280c is preferably smaller than that of the insulator 280b. The thicknesses of the insulators 280a and 280c are each preferably 1 nm to 15 nm, more preferably 2 nm to 10 nm, more preferably 3 nm to 7 nm, and further preferably 3 nm to 5 nm. The thickness of the insulator 280b is preferably 3 nm to 30 nm, more preferably 5 nm to 20 nm, and still more preferably 7 nm to 15 nm. When the thicknesses of the insulators 280a to 280c are within the above ranges, oxygen vacancies in the oxide semiconductor 230, particularly in the channel formation region, can be reduced.

[0230] For example, it is preferable to use silicon nitride for the insulators 280a and 280c and silicon oxide for the insulator 280b. In this case, the insulators 280a and 280c each contain at least silicon and nitrogen. The insulator 280b contains at least silicon and oxygen.

[0231] 10A and 10B show the insulator 280 having a three-layer stacked structure, one embodiment of the present invention is not limited to this. The insulator 280 may have a two-layer or four or more-layer stacked structure.

[0232] The above-described insulator having a barrier property against hydrogen is preferably used for the insulator 283. This can prevent hydrogen from diffusing from the outside of the transistor to the oxide semiconductor 230 through the insulator 250.

[0233] The above-described insulator having a function of capturing or fixing hydrogen is preferably used as the insulator 283. With such a structure, diffusion of hydrogen from above the insulator 283 to the oxide semiconductor 230 can be suppressed, and further, hydrogen in the oxide semiconductor 230 can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor 230.

[0234] 2B and 2D show a configuration in which the upper surface of the conductor 120 and the lower surface of the oxide semiconductor 230 are in contact with each other, but the present invention is not limited to this. For example, a conductor may be provided between the conductor 120 and the oxide semiconductor 230.

[0235] 11A and 11B , a conductor 125 may be provided between the conductor 120 and the oxide semiconductor 230. The above-described conductive material containing oxygen is preferably used as the conductor 125. By using a conductive material containing oxygen as the conductor 125, the conductor 125 can maintain its conductivity even when it absorbs oxygen. Furthermore, oxygen in the oxide semiconductor 230 can be prevented from diffusing into the conductor 120. For example, indium tin oxide, indium tin oxide to which silicon is added, indium zinc oxide, or the like can be used as the conductor 125 in a single layer or a stacked layer.

[0236] 2B and 2D show a configuration in which the conductor 240 is provided on the insulator 280. Also, a configuration is shown in which a region of the insulator 250 that does not overlap with the conductor 240 has a region that is in contact with the upper surface of the insulator 280. Note that the present invention is not limited to this.

[0237] For example, the conductor 240 may be configured to be embedded in the insulator. In this case, it is preferable that the height of the upper surface of the conductor 240 is the same as the height of the upper surface of the insulator. By configuring in this way, the physical distance from the conductor 260 to the conductor 240 (particularly the side end of the conductor 240) can be increased, and a short circuit between the conductor 260 and the conductor 240 can be prevented.

[0238] Since the insulator functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulator, an insulator containing the above-mentioned material with a low dielectric constant can be used in a single layer or a multilayer configuration.

[0239] <Constituent Materials of Storage Device> Constituent materials that can be used for the storage device will be described below.

[0240] [Substrate] The substrate on which the transistor 200 and the capacitor 100 are formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0241] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0242] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function. Note that materials with a low dielectric constant also have high dielectric strength.

[0243] Examples of high-dielectric-constant (high-k) materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0244] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other examples of inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0245] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0246] Furthermore, an insulator such as a gate insulator that is in contact with a semiconductor or that is provided near a semiconductor layer is preferably an insulator that has a region containing excess oxygen. For example, by providing an insulator that has a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.

[0247] Examples of insulators having a barrier property against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0248] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0249] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0250] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0251] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function to suppress the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., which are difficult to diffuse.

[0252] [Conductor] As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metal element as a component, or an alloy combining the aforementioned metal elements, etc., may be used. As the alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. may be used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0253] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide with added silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0254] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0255] Furthermore, a plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0256] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0257] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0258] [Metal Oxide] Metal oxides may have lattice defects. Examples of lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids. Factors that cause lattice defects include a discrepancy in the ratio of the number of atoms of the constituent elements (excess or deficiency of constituent atoms) and impurities.

[0259] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0260] In particular, a transistor using a metal oxide has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect (V Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the metal oxide, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the metal oxide. In other words, it is preferable that the carrier concentration of the channel formation region of the metal oxide is reduced and the channel formation region of the metal oxide is made i-type (intrinsic) or substantially i-type.

[0261] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects present vary depending on the structure of the metal oxide or the method for forming the metal oxide film.

[0262] The structure of metal oxides can be divided into single crystal structures and other structures (non-single crystal structures). Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures. The a-like structure has a structure between the nc structure and the amorphous structure. The classification of crystal structures will be described later.

[0263] Furthermore, metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Furthermore, metal oxides having an a-like structure have a higher hydrogen concentration than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.

[0264] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide with a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0265] Furthermore, it is preferable to use a metal oxide for the channel formation region of a transistor, which increases the on-state current of the transistor. To increase the on-state current of the transistor, it is preferable to increase the carrier mobility of the metal oxide used in the transistor. To increase the carrier mobility of a metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0266] Here, it is preferable to use a metal oxide with high crystallinity for the metal oxide including the channel formation region. Furthermore, the crystal preferably has a crystal structure in which multiple layers (e.g., a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked. Examples of metal oxides having such crystals include single-crystal oxide semiconductors and CAAC-OS.

[0267] It is also preferable that the c-axis of the crystal is oriented in the normal direction to the surface on which the metal oxide is to be formed or the film surface, so that the layers are arranged parallel or approximately parallel to the surface on which the metal oxide is to be formed or the film surface, i.e., the layers extend in the channel length direction.

[0268] For example, the above-described three-layered crystal structure may have the following structure: The first layer has an octahedral oxygen atomic coordination structure with the metal contained in the first layer at the center; The second layer has a trigonal bipyramidal or tetrahedral oxygen atomic coordination structure with the metal contained in the second layer at the center; and The third layer has a trigonal bipyramidal or tetrahedral oxygen atomic coordination structure with the metal contained in the third layer at the center.

[0269] The crystal structure of the above crystal is, for example, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ There are various types of structures, including modified structures.

[0270] Furthermore, each of the first to third layers is preferably composed of one metal element or multiple metal elements having the same valence and oxygen. The valence of the one or more metal elements constituting the first layer is preferably the same as the valence of the one or more metal elements constituting the second layer. The first layer and the second layer may contain the same metal element. The valence of the one or more metal elements constituting the first layer is preferably different from the valence of the one or more metal elements constituting the third layer.

[0271] The above structure can improve the crystallinity of the metal oxide and increase the carrier mobility of the metal oxide. Therefore, by using the metal oxide in a channel formation region of a transistor, the on-state current of the transistor can be increased, and the electrical characteristics of the transistor can be improved.

[0272] Examples of metal oxides according to one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0273] Examples of metal oxide semiconductors of one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium Examples of usable materials include aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable materials include silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0274] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0275] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0276] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0277] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0278] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0279] Furthermore, by increasing the ratio of the number of In atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0280] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0281] In order to form a metal oxide having the above-described layered crystal structure, it is preferable to deposit atoms layer by layer. In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used, and therefore, it is easy to form a metal oxide having the above-described layered crystal structure.

[0282] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0283] The ALD method can deposit atoms layer by layer, which allows for the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. Furthermore, the PEALD method may be preferable because it utilizes plasma, allowing for film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs a high substrate temperature during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0284] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as a sputtering method or a CVD method, which have a faster film formation rate. For example, a method may be used in which a first metal oxide film is formed by sputtering, and a second metal oxide film is formed on the first metal oxide by ALD. For example, if the first metal oxide has crystalline portions, the second metal oxide may grow as crystals using the crystalline portions as nuclei.

[0285] The ALD method can control the composition of the resulting film by adjusting the amount of source gas introduced. For example, the ALD method can form a film of any composition by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Furthermore, for example, the ALD method can form a film whose composition changes continuously by changing the source gas while forming the film. When forming a film while changing the source gas, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of memory devices can be improved in some cases.

[0286] [Transistor Having Metal Oxide] Next, a case where a metal oxide (oxide semiconductor) is used as a transistor will be described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer will be referred to as an OS transistor, and a transistor using silicon for a semiconductor layer will be referred to as a Si transistor.

[0287] By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. Furthermore, a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.

[0288] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ Less than 1×10, more preferably 1×10 １５ cm −３ Less than 1×10, more preferably 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0289] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0290] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0291] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0292] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0293] Furthermore, in Si transistors, a short channel effect (also referred to as SCE) occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0294] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0295] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0296] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0297] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0298] By using the above structure, the OS transistor can have good electrical characteristics even when miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, since a short-channel effect occurs in a Si transistor, it may be difficult to achieve a gate length of 20 nm or less or 15 nm or less. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation.

[0299] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0300] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0301] [Impurities in Metal Oxides] Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0302] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0303] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm３ The following applies.

[0304] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Less than.

[0305] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0306] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0307] [Other Semiconductor Materials] The oxide semiconductor 230 can be rephrased as a semiconductor layer including a channel formation region of a transistor. The semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor layer. For example, a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used as the semiconductor material.

[0308] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0309] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0310] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0311] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0312] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a memory device with a large on-current can be provided.

[0313] <Example of Manufacturing Method of Memory Device> Next, a manufacturing method of the memory device of one embodiment of the present invention illustrated in FIGS. 2A to 2D will be described with reference to FIGS. 12A to 22C.

[0314] A in each figure shows a plan view of a region having a memory cell 150. B in each figure corresponds to FIG. 2B and is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A in each figure. C in each figure corresponds to a cross-sectional view of the functional element 155 corresponding to FIG. 2D. Note that in the plan view of A in each figure, some elements are omitted for clarity. The plan view of the functional element 155 corresponding to FIG. 2C is similar to the memory cell 150, and therefore is omitted since it can be referred to.

[0315] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0316] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0317] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0318] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that does not use plasma and can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the memory device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of memory devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0319] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0320] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0321] Furthermore, in the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the raw material gases. For example, in the CVD method, by changing the flow rate ratio of the raw material gases while forming a film, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers, since no time is required for transport or pressure adjustment. Therefore, the productivity of memory devices can be improved in some cases.

[0322] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0323] First, a substrate (not shown) is prepared, and an insulator 140 is formed over the substrate (see FIGS. 12A to 12C). The insulating material described above may be used as appropriate for the insulator 140. The insulator 140 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

[0324] Next, the conductor 110 is formed on the insulator 140. The above-mentioned conductive material may be used as the conductor 110 as appropriate. The conductor 110 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the conductor 110 may be formed as a stacked film in which tungsten and titanium nitride are deposited in this order by a CVD method.

[0325] The conductor 110 may be processed to have a shape extending in the X direction or the Y direction. The conductor 110 may be processed using lithography. The processing may be performed using dry etching or wet etching. Processing using dry etching is suitable for microfabrication. By performing this processing, the side end portions of the conductor 110 are covered with the insulator 130 to be formed later.

[0326] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process a conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0327] Furthermore, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0328] Next, the insulator 180 is formed on the conductor 110 (see FIGS. 12A to 12C). The insulator 180 may be formed using any of the insulating materials described above as appropriate. The insulator 180 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the insulator 180 may be formed as a silicon oxide film by a sputtering method. Note that it is preferable to perform a CMP process after the insulator 180 is formed to planarize the top surface. Note that there are cases where the CMP process is not necessary. In this case, the top surface of the insulator 180 has an upwardly convex curved shape. By not performing the planarization process, the manufacturing cost can be reduced and the production yield can be increased.

[0329] Here, the film thickness of the insulator 180 corresponds to the capacitance of the capacitance element 100 , and therefore the film thickness of the insulator 180 may be appropriately set in accordance with the design value of the capacitance of the capacitance element 100 .

[0330] Furthermore, by forming the insulator 180 by a sputtering method that does not require the use of molecules containing hydrogen in a deposition gas, the hydrogen concentration in the insulator 180 can be reduced.

[0331] Next, a portion of the insulator 180 is processed to form an opening 190 that reaches the conductor 120 (see FIGS. 13A to 13C ). The opening 190 may be formed using lithography. Note that the shape of the opening 190 is circular in plan view, but is not limited to this. For example, the shape of the opening 190 may be a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in plan view.

[0332] As described above, the sidewalls of the opening 190 are preferably perpendicular to the upper surface of the conductor 110. Such a configuration allows for miniaturization or high integration of the memory device. The sidewalls of the opening 190 may be tapered. Tapering the sidewalls of the opening 190 improves the coverage of a conductive film that will become the conductor 115 described below, and reduces defects such as voids.

[0333] The maximum width of opening 190 (or the diameter when opening 190 is circular in plan view) is preferably very small. For example, the maximum width of opening 190 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 1 nm or more, or 5 nm or more. In this way, to process opening 190 very finely, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0334] Because the opening 190 has a large aspect ratio, it is preferable to use anisotropic etching to process a portion of the insulator 280. In particular, processing by dry etching is preferable because it is suitable for fine processing.

[0335] Next, a conductive film to be the conductor 115 is formed in contact with the bottom and sidewalls of the opening 190 and at least a part of the top surface of the insulator 180. Any of the above-described conductors applicable to the conductor 115 may be used as the conductive film. The conductive film may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. The conductive film is preferably formed in contact with the bottom and sidewalls of the opening 190 having a large aspect ratio. Therefore, the conductive film is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like. For example, a titanium nitride film may be formed by a CVD method.

[0336] Next, the conductive film that will become the conductor 115 is processed by lithography to form the conductor 115 (see FIGS. 14A to 14C ). As a result, a part of the conductor 115 is formed in the opening 190. The conductor 115 also comes into contact with a part of the side surface and top surface of the insulator 180.

[0337] Next, the insulator 130 is formed over the conductor 115 and the insulator 180 (see FIGS. 15A to 15C ). The insulator 130 may be formed using any of the above-described high-k materials or ferroelectric materials as appropriate. The insulator 130 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the insulator 130 may be formed by an ALD method to form a stacked film in which zirconium oxide, aluminum oxide, and zirconium oxide are deposited in this order.

[0338] Next, a resist mask 145 is formed on the insulator 130 (see FIGS. 15A to 15C). The resist mask 145 is formed so as to provide an opening 146 in a region that will become the functional element 155 and overlaps with an opening 190 (see FIG. 15C). On the other hand, in a region that will become the memory cell 150, the resist mask 145 is formed so as to cover the opening 190.

[0339] The shape of opening 146 in resist mask 145 does not matter as long as it encompasses opening 190 in a plan view. Even if opening 190 has a circular shape, opening 146 does not necessarily have to have a circular shape and may have, for example, a rectangular shape.

[0340] Next, the portion of the insulator 130 that is not covered with the resist mask 145 is removed by etching (see FIGS. 16A to 16C). Here, an example is shown in which anisotropic etching is used. By using anisotropic etching, the insulator 131 remains in the opening 190. Note that if isotropic etching is used, the insulator 131 may not remain.

[0341] Here, when the aspect ratio of the opening 190 is high (for example, 2 or more), if an attempt is made to completely remove the insulator 130 in the opening 190, it takes longer to etch the insulator 130 located on the inner wall of the opening 190 than the insulator 130 located at the bottom of the opening 190. Therefore, the insulator 130 at the bottom of the opening 190 disappears first, and the conductor 115 may be exposed to the etching and damaged. On the other hand, in one embodiment of the present invention, etching can be performed to the extent that at least the insulator 130 located at the bottom of the opening 190 is removed, thereby mitigating damage to the conductor 115. Furthermore, the remaining insulator 131 may improve the adhesion of the conductor 120 formed thereon.

[0342] Next, the conductive film 120A is formed (see FIGS. 17A to 17C). The conductive film 120A may be formed using any of the above-described conductive materials. The conductive film 120A may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate. For example, the conductive film 120A may be formed as a stacked film by depositing titanium nitride and tantalum nitride in this order by a CVD method. Alternatively, the conductive film 120A may be formed as a stacked film by depositing titanium nitride and tungsten in this order by a CVD method.

[0343] Next, the conductive film 120A is processed to form the conductor 120 (see FIGS. 18A to 18C). The conductor 120 may be formed by lithography. The conductive film 120A can be processed by dry etching or wet etching. Dry etching is suitable for fine processing.

[0344] In this manner, the capacitor 100 including the conductor 115, the insulator 130, and the conductor 120, and the connection portion 101 can be separately formed.

[0345] Next, the insulator 280 is formed over the insulator 130 and the conductor 120 (see FIGS. 19A to 19C ). The insulator 280 may be formed using any of the insulating materials described above as appropriate. The insulator 280 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. For example, the insulator 280 may be formed as a silicon oxide film by a sputtering method. Note that the insulator 280 is preferably planarized by performing a chemical mechanical polishing (CMP) process after the formation to planarize the top surface. By performing a planarization process on the insulator 280, the conductor 240 that functions as a wiring can be suitably formed. Alternatively, aluminum oxide may be formed on the insulator 280 by a sputtering method, and then CMP may be performed until the aluminum oxide reaches the insulator 280. The CMP process can planarize and smooth the surface of the insulator 280. By disposing the aluminum oxide on the insulator 280 and performing the CMP process, it becomes easier to detect the end point of the CMP process.

[0346] In some cases, the CMP process may not be necessary. In this case, the upper surface of the insulator 280 has an upwardly convex curved shape. By not performing the planarization process, the manufacturing cost can be reduced and the production yield can be increased.

[0347] Here, since the thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200 , the thickness of the insulator 280 can be set appropriately according to the design value of the channel length of the transistor 200 .

[0348] Furthermore, by depositing the insulator 280 by a sputtering method in an atmosphere containing oxygen, the insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. By depositing the insulator 280 in this manner, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V Ｏ H can be reduced.

[0349] Next, a conductive film 240A is formed over the insulator 280 (see FIGS. 19A to 19C). The conductive film 240A may be formed using any of the above-described conductive materials as appropriate. The conductive film 240A may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

[0350] Next, a portion of the conductive film 240A and a portion of the insulator 280 are processed to form an opening 290 that reaches the conductor 120 (see FIGS. 20A to 20C ). The opening 290 may be formed using lithography. Note that the shape of the opening 290 shown in FIG. 20A is circular in plan view, but is not limited to this. For example, the shape of the opening 290 may be a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in plan view.

[0351] As described above, the sidewall of the opening 290 is preferably perpendicular to the top surface of the conductor 110. Such a configuration enables miniaturization or high integration of the memory device. The sidewall of the opening 290 may be tapered. Tapering the sidewall of the opening 290 improves coverage with an oxide semiconductor film that will become the oxide semiconductor 230 described later, and reduces defects such as voids.

[0352] The maximum width of the opening 290 (maximum diameter when the opening 290 is circular in plan view) is preferably minute. For example, the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 1 nm or more, or 5 nm or more. In this way, to process the opening 290 minutely, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0353] Because the opening 290 has a large aspect ratio, it is preferable to process a portion of the conductive film 240A and a portion of the insulator 280 using anisotropic etching. Processing by dry etching is particularly preferable because it is suitable for fine processing. Furthermore, the processing may be performed under different conditions. As described above, depending on the conditions for processing the portion of the conductive film 240A and the portion of the insulator 280, the inclination of the side surface of the conductor 240 at the opening 290 may differ from the inclination of the side surface of the insulator 280 at the opening 290.

[0354] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water contained in the insulator 280 or the like can be reduced before the formation of an oxide semiconductor film that becomes the oxide semiconductor 230 described later.

[0355] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulator 280, etc., as much as possible.

[0356] Next, an oxide semiconductor film to be the oxide semiconductor 230 is formed in contact with the bottom and sidewall of the opening 290 and at least a part of the top surface of the conductive film 240A. The oxide semiconductor film may be formed using any of the above-described metal oxides applicable to the oxide semiconductor 230. The oxide semiconductor film may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide semiconductor film is preferably formed in contact with the bottom and sidewall of the opening 290, which has a large aspect ratio. Therefore, the oxide semiconductor film is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like. For example, an In—Ga—Zn oxide film may be formed by an ALD method. Details of the metal oxide film formation method using the ALD method will be described in a later embodiment.

[0357] Note that when the sidewall of the opening 290 has a tapered shape, the method for forming the oxide semiconductor film to be the oxide semiconductor 230 is not limited to the CVD method or the ALD method. For example, a sputtering method may be used.

[0358] Furthermore, during or after the formation of an oxide semiconductor film, microwave treatment is preferably performed in an atmosphere containing oxygen to reduce the impurity concentration in the oxide semiconductor film. Examples of impurities include hydrogen and carbon. The microwave treatment can improve the crystallinity of the oxide semiconductor film in some cases. Here, the microwave treatment refers to treatment using, for example, an apparatus having a power supply that generates high-density plasma using microwaves.

[0359] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be used. Oxygen acting on an oxide semiconductor can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). The oxygen acting on an oxide semiconductor may take one or more of the above forms, and oxygen radicals are particularly preferred.

[0360] Furthermore, when the microwave treatment is performed in the oxygen-containing atmosphere, the substrate is preferably heated to a temperature of 100° C. to 650° C., preferably 200° C. to 600° C., and more preferably 300° C. to 450° C., because the impurity concentration in the oxide semiconductor can be further reduced by heating the substrate.

[0361] By heating the substrate during the microwave treatment in the oxygen-containing atmosphere, the carbon concentration in the oxide semiconductor measured by SIMS can be increased to 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 1×10 １８ atoms / cm ３ It can be less than.

[0362] Although the microwave treatment is performed on the oxide semiconductor in an atmosphere containing oxygen in the above example, the present invention is not limited to this. For example, an insulating film, more specifically, a silicon oxide film, located near the oxide semiconductor may be subjected to the microwave treatment in an atmosphere containing oxygen. This converts hydrogen contained in the silicon oxide film into H ２ The hydrogen can be released to the outside as O. By releasing hydrogen from the silicon oxide film located in the vicinity of the oxide semiconductor, a highly reliable memory device can be provided.

[0363] 9A and 9B , when the oxide semiconductor 230 has a stacked structure, the layers included in the oxide semiconductor 230 may be formed by the same or different methods. For example, when the oxide semiconductor 230 has a two-layer stacked structure, the lower layer of the oxide semiconductor film may be formed by sputtering, and the upper layer of the oxide semiconductor film may be formed by ALD. Oxide semiconductor films formed by sputtering tend to have crystallinity. Therefore, by providing a crystalline oxide semiconductor film as the lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved. Even if pinholes or discontinuities are formed in the lower layer of the oxide semiconductor film formed by sputtering, the overlapping portions can be blocked by the upper layer of the oxide semiconductor film formed by ALD, which has good coverage.

[0364] Here, the oxide semiconductor film to be the oxide semiconductor 230 is preferably formed in contact with the top surface of the conductor 120 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the top surface of the conductor 240. When the oxide semiconductor film is formed in contact with the conductor 120, the conductor 120 functions as one of the source electrode and drain electrode of the transistor 200. When the oxide semiconductor film is formed in contact with the conductor 240, the conductor 240 functions as the other of the source electrode and drain electrode of the transistor 200.

[0365] Next, heat treatment is preferably performed. The heat treatment may be performed at a temperature range in which the oxide semiconductor film does not become polycrystallized, such as 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for desorbed oxygen.

[0366] The gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain moisture of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film and the like as much as possible.

[0367] Here, the heat treatment is preferably performed in a state where the insulator 280 containing excess oxygen is provided in contact with the oxide semiconductor film. By performing the heat treatment in this manner, oxygen can be supplied from the insulator 280 to a channel formation region of the oxide semiconductor 230, thereby reducing oxygen vacancies and VoH.

[0368] Although the heat treatment is performed after the oxide semiconductor film is formed in the above example, the present invention is not limited to this example and may be configured to perform the heat treatment in a later step.

[0369] Next, the oxide semiconductor film to be the oxide semiconductor 230 is processed by lithography to form the oxide semiconductor 230 (see FIGS. 21A to 21C ). As a result, part of the oxide semiconductor 230 is formed in the opening 290. The oxide semiconductor 230 is in contact with part of the side surface and top surface of the conductor 240. Therefore, the area of ​​the region where the oxide semiconductor 230 and the conductor 240 are in contact with each other can be increased.

[0370] Next, the conductive film 240A is processed to form the conductor 240. The conductor 240 may be formed by lithography. The conductive film 240A can be processed by dry etching or wet etching. Dry etching is suitable for fine processing.

[0371] Although the method of processing the oxide semiconductor 230 and then processing the conductive film 240A to form the conductor 240 has been described here, the processing of the conductive film 240A may be performed first. That is, the conductive film 240A may be formed on the insulator 280, and then the conductive film 240A may be processed to form the conductor 240, and then the opening 290 may be formed in the conductor 240 and the insulator 280, and then an oxide semiconductor film may be formed and processed to form the oxide semiconductor 230.

[0372] Next, the insulator 250 is formed over the oxide semiconductor 230, the conductor 240, and the insulator 280 (see FIGS. 22A to 22C ). The insulator 250 may be formed using any of the above-described insulating materials as appropriate. The insulator 250 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. The insulator 250 is preferably formed in contact with the oxide semiconductor 230 provided in the opening 290 having a large aspect ratio. Therefore, the insulator 250 is preferably formed by a film formation method with good coverage, more preferably a CVD method, an ALD method, or the like. For example, the insulator 250 may be formed by depositing silicon oxide by an ALD method.

[0373] When the sidewall of the opening 290 has a tapered shape, the method for forming the insulator 250 is not limited to the CVD method or the ALD method, and for example, sputtering may be used.

[0374] By forming the insulator 250 after the oxide semiconductor 230, the side edge of the oxide semiconductor 230 is covered with the insulator 250. Therefore, it is possible to prevent a short circuit between the oxide semiconductor 230 and the conductor 260. Furthermore, by using the above configuration, the side edge of the conductor 240 is covered with the insulator 250. Therefore, it is possible to prevent a short circuit between the conductor 240 and the conductor 260.

[0375] Next, a conductive film 260A is formed to fill the recesses of the insulator 250 (see FIGS. 22A to 22C ). The conductive film 260A may be formed using any of the above-described conductive materials as appropriate. The conductive film 260A may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Here, the conductive film 260A is preferably formed in contact with the insulator 250 provided in the opening 290 with a large aspect ratio. Therefore, the conductive film 260A is preferably formed by a film formation method with good coverage or filling properties, and more preferably by a CVD method, an ALD method, or the like. For example, the conductive film 260A may be formed by depositing titanium nitride using a CVD method or an ALD method.

[0376] Note that when the conductive film 260A is formed using a CVD method, the average surface roughness of the upper surface of the conductive film 260A may become large. In this case, it is preferable to planarize the conductive film 260A using a CMP method. Before performing the CMP process, a silicon oxide film or a silicon oxynitride film may be formed on the conductive film 260A, and the CMP process may be performed until the silicon oxide film or the silicon oxynitride film is removed.

[0377] In the above description, the conductive film 260A is provided so as to fill the opening 290, but the present invention is not limited to this. For example, a recess that reflects the shape of the opening 290 may be formed in the center of the conductive film 260A. Alternatively, the recess may be filled with an inorganic insulating material or the like.

[0378] Next, the conductive film 260A is processed to form the conductor 260 (see FIGS. 23A to 23C). The conductor 260 may be formed by lithography. The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for fine processing.

[0379] 2A and 2B , the side edge of the conductor 260 is preferably located inside the side edge of the oxide semiconductor 230 in plan view, which can prevent the conductor 260 and the oxide semiconductor 230 from shorting out.

[0380] In this manner, the transistor 200 including the conductor 120, the conductor 240, the oxide semiconductor 230, the insulator 250, and the conductor 260 can be formed.

[0381] Next, the insulator 283 is formed to cover the conductor 260 and the insulator 250. Any of the above-described insulating materials may be used as appropriate for the insulator 283. The insulator 283 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

[0382] In this manner, a memory device having the memory cell 150 and the functional element 155 shown in FIGS. 2A to 2D can be manufactured.

[0383] According to one embodiment of the present invention, a novel transistor, a novel semiconductor device, and a novel memory device can be provided. Alternatively, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a memory device with favorable frequency characteristics can be provided. Alternatively, a memory device with high operating speed can be provided. Alternatively, a memory device with favorable reliability can be provided. Alternatively, a memory device with low power consumption can be provided. Alternatively, a memory device including a transistor with large on-state current can be provided. Alternatively, a memory device with little variation in transistor characteristics can be provided. Alternatively, a memory device with favorable electrical characteristics can be provided.

[0384] The memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a storage device. Furthermore, a functional element including the transistor 200 and the connection portion 101 can be used as a peripheral circuit of the storage device. The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Because the off-state current of the transistor 200 is low, stored data can be retained for a long period of time by using the transistor 200 in a storage device. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200 enable high-speed reading and writing of data from and to the storage device.

[0385] An example of a memory device in which two memory cells 150 (hereinafter referred to as memory cell 150a and memory cell 150b) are connected to a common wiring will be described with reference to Figures 24A and 24B. Figure 24A is a plan view of the memory device. Figure 24B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Figure 24A. Note that some elements have been omitted from the plan view of Figure 24A for clarity.

[0386] 24A and 24B have the same configuration as the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b.

[0387] 24A and 24B , a conductor 260 functioning as a wiring WL is provided in each of the memory cell 150a and the memory cell 150b. A conductor 240 functioning as part of a wiring BL is provided in common to the memory cell 150a and the memory cell 150b. That is, the conductor 240 is in contact with the oxide semiconductor 230 in the memory cell 150a and the oxide semiconductor 230 in the memory cell 150b.

[0388] 24A and 24B includes conductors 245 and 246 that are electrically connected to memory cells 150a and 150b and function as plugs (which can also be called connection electrodes). Conductor 245 is disposed in openings formed in insulator 180, insulating layer 130, insulator 280, and insulator 140, and contacts the bottom surface of conductor 240. Conductor 246 is disposed in openings formed in insulators 287, insulator 283, and insulator 250, and contacts the top surface of conductor 240. Conductor 245 and conductor 246 can be made of a conductive material that can be used for conductor 240.

[0389] The insulator 287 preferably has a low dielectric constant because it functions as an interlayer film. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 287 can be formed as a single layer or a stack of insulators containing the above-described material with a low dielectric constant. The insulator 287 preferably has a low concentration of impurities such as water and hydrogen. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.

[0390] The conductor 245 can be electrically connected to a sense amplifier (not shown) provided below the memory device shown in Figure 24B, for example, and the conductor 246 can be electrically connected to a similar memory device (not shown) provided above the memory device shown in Figure 24B. In this case, the conductors 245 and 246 function as part of the wiring BL. In this way, by providing a memory device above or below the memory device shown in Figure 24B, the memory capacity per unit area can be increased.

[0391] The memory cell 150a and the memory cell 150b are arranged at line-symmetric positions with the conductor 245 and the conductor 246 sandwiched therebetween. The transistor 200a and the transistor 200b share the conductor 245 and the conductor 246, which function as plugs. In this way, by configuring the connection between the two transistors and the plugs as described above, a memory device that can be miniaturized or highly integrated can be provided.

[0392] Note that the conductor 110 functioning as the wiring PL may be provided in each of the memory cells 150 a and 150 b, or may be provided in common to the memory cells 150 a and 150 b. However, as shown in FIG. 24B , the conductor 110 is provided apart from the conductor 245 to prevent the conductor 110 and the conductor 245 from shorting out.

[0393] Furthermore, a memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix. As an example of a memory cell array, FIGS. 25A and 25B show an example of a memory device in which 4×2×4 memory cells 150 are arranged in the X, Y, and Z directions. FIG. 25A is a plan view of the memory device. FIG. 25B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 25A. Note that some elements have been omitted from the plan view of FIG. 25A for clarity.

[0394] 25A and 25B have the same configuration as the memory cell 150. The memory cell 150c includes a capacitor 100c and a transistor 200c, and the memory cell 150d includes a capacitor 100d and a transistor 200d.

[0395] Hereinafter, a memory device consisting of memory cells 150a to 150d will be referred to as a memory unit. 25A and 25B show memory unit 160[1,1] to memory unit 160[2,4] among the memory units included in the memory device. Note that, below, when describing matters common to each memory unit, they may be referred to as memory units 160. In memory unit 160[a,b] (a and b are positive integers), a indicates an address in the Y direction, and b indicates an address in the Z direction.

[0396] 25B, memory unit 160 has memory cell 150c arranged outside memory cell 150a and memory cell 150d arranged outside memory cell 150b, with conductor 245 at the center. In other words, it can be said that this is a memory device in which memory cell 150c is provided adjacent to memory cell 150a and memory cell 150d is provided adjacent to memory cell 150b in the memory device shown in FIGS. 24A and 24B.

[0397] 25A and 25B , the conductor 260 functioning as the wiring WL is shared by the memory cells 150 adjacent in the Y direction. The conductor 240 functioning as part of the wiring BL is shared within the same memory unit. That is, the conductor 240 is in contact with the oxide semiconductor 230 of each of the memory cells 150a to 150d.

[0398] A conductor 245 is provided between the conductors 240 of memory units 160 adjacent in the Z direction. The conductors 240 and 245 provided in each memory unit 160 form a wiring BL. The conductors 245 are electrically connected to a sense amplifier (not shown) provided below the memory device shown in Figures 25A and 25B. In this way, by stacking multiple memory units in the memory device shown in Figures 25A and 25B, the memory capacity per unit area can be increased.

[0399] Furthermore, the memory cells 150a and 150c and the memory cells 150b and 150d are arranged in line symmetry with the conductor 245 in between. In this way, by configuring the connections between the four transistors and the plugs as described above, it is possible to provide a memory device that can be miniaturized or highly integrated.

[0400] As shown in Figure 25B, by stacking multiple memory cells, cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured. Note that Figure 25B illustrates an example of a configuration in which four layers, each having two memory units, are stacked, but the present invention is not limited to this. The memory device may have one layer having at least one memory cell 150, or two or more layers may be stacked.

[0401] 25B shows a configuration in which the conductor 245 functioning as a plug is arranged between the memory cells 150. In other words, the configuration shows a configuration in which the conductor 245 functioning as a plug is arranged inside the memory unit 160. However, the present invention is not limited to this. The conductor 245 may also be arranged outside the memory unit.

[0402] As an example of a memory cell array, Figures 26A and 26B show an example of a memory device in which 3 x 3 x 4 memory cells 150 are arranged in the X, Y, and Z directions. Figure 26A is a plan view of the memory device. Figure 26B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Figure 26A. Note that some elements have been omitted from the plan view of Figure 26A for clarity.

[0403] 26A and 26B has a structure in which m (m is an integer of 2 or more) layers including memory cells 150 are stacked. Here, the layer provided as the first layer (bottom) is referred to as layer 170[1], and the layer provided as the mth layer (top) is referred to as layer 170[m] in FIG. 26B . In other words, the memory device of one embodiment of the present invention may have a structure in which multiple layers including memory cells 150 are stacked.

[0404] As shown in Figures 26A and 26B, the conductor 245 may be provided outside the memory unit. Furthermore, the conductor 245 may be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] is electrically connected to a wiring provided in the layer 170[2]. The wiring provided in the layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[2]. That is, the wiring can be formed in the same process as the conductor 110.

[0405] 26B shows a configuration in which the conductor 245 is electrically connected to a wiring provided in an upper layer of the layer including the conductor 245, but the present invention is not limited to this. For example, the conductor 245 may be electrically connected to a wiring provided in the layer including the conductor 245. For example, the conductor 245 provided in the layer 170[1] may be electrically connected to a wiring provided in the layer 170[1]. Note that the wiring provided in the layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of the memory cell 150 included in the layer 170[1]. In other words, the wiring can be formed in the same process as the conductor 110.

[0406] 27A and 27B show an example in which a functional element 155 is provided that functions as a selector circuit, which is one of the peripheral circuits. Here, one functional element 155 is provided on each layer 170. Fig. 27A shows a circuit diagram corresponding to one layer 170.

[0407] The transistor Tr1 corresponds to the transistor 200 included in the memory cell 150, and the capacitor C corresponds to the capacitor 100. The transistor Tr2 corresponds to the functional element 155 and the transistor 200 included in the functional element 155.

[0408] A wiring WL that functions as a word line is connected to the gate of each transistor Tr1. Here, an example is shown in which any one of WL[1] to WL[n] (n is a positive integer) is connected to the transistor Tr1. One of the source electrode and the drain electrode of the transistor Tr1 is connected to the capacitor C, and the other is connected to the wiring BL1. The wiring BL1 functions as a first bit line and corresponds to the conductor 240.

[0409] The transistor Tr2 has a gate connected to a wiring S that functions as a selection signal line, one of a source electrode and a drain electrode connected to a wiring BL1, and the other connected to a wiring BL2. The wiring BL2 functions as a second bit line and is electrically connected to, for example, a sense amplifier (not shown) provided below the memory device in FIG. 27B.

[0410] The transistor Tr2 is controlled by a signal applied to the wiring S and functions as a switch for controlling conduction or non-conduction between the first bit line and the second bit line. The second bit line is electrically connected to the first bit lines of all the stacked layers 170 via the transistor Tr2.

[0411] With this configuration, when accessing (reading, writing, or refreshing) one layer 170, the first bit line and the second bit line of that layer 170 are made conductive, and the second bit lines of all other layers 170 are made non-conductive with the first bit lines, thereby significantly reducing the load on the second bit lines, and thus significantly shortening the time required for access.

[0412] Next, another example of a planar layout will be described. First, a planar layout of a memory device corresponding to FIG. 26A is shown in FIG. 28A. FIG. 28A shows a region including 4×4 memory cells 150. Also shown are a conductor 260 functioning as a wiring WL, a conductor 240 functioning as a wiring BL, and an opening 290. The memory cell 150 is provided in a region where the conductor 260, the conductor 240, and the opening 290 overlap (intersect).

[0413] 28A shows a configuration in which memory cells 150 are arranged at the intersections of orthogonal lattices. Conductors 260 extend in the Y direction, and conductors 240 extend in the X direction. The distance between two adjacent memory cells 150 is equal in the X and Y directions. Also shown is a configuration in which the width of conductors 260 in the X direction is uniform, and the width of conductors 240 in the Y direction is uniform. However, the present invention is not limited to this.

[0414] Fig. 28B is another example of a planar layout of a memory device. Similar to Fig. 28A, the planar layout of Fig. 28B illustrates conductors 260, conductors 240, memory cells 150, and openings 290. The memory device shown in Fig. 28B differs from the memory device shown in Fig. 28A mainly in the arrangement of memory cells 150 (openings 290), the shape of conductors 240, and the direction in which conductors 260 extend.

[0415] As shown in FIG. 28B , the memory cells 150 (openings 290) may be arranged in a zigzag pattern in the Y direction. In FIG. 28B , the memory cell adjacent to the first memory cell in the X direction is the second memory cell, and the memory cell adjacent to the first and second memory cells in the Y direction is the third memory cell. For example, the center of the third memory cell may be located on a line that passes through the middle between the first and second memory cells and is parallel to the Y direction. In this case, the third memory cell can be said to be located at a position that is halfway offset in the X direction from the first and second memory cells.

[0416] As shown in FIG. 28B , the conductor 240 has a first region that is wide in the X direction and a second region that is narrow. The first region is the opening 290 and the region in its vicinity. In plan view, the first region can be said to have a rectangular shape with rounded corners. The second region is the region between adjacent openings 290 in one conductor 240. With this configuration, when the memory cells 150 (openings 290) are arranged in a zigzag pattern in the Y direction, the physical distance between the conductors 240 can be reduced. This allows for miniaturization and high integration of the memory device.

[0417] 28B, the extension direction of the conductor 260 is inclined with respect to the Y direction. That is, depending on the arrangement of the memory cell 150 (opening 290), the extension direction of the conductor 260 is not perpendicular to the extension direction of the conductor 240.

[0418] Fig. 28C shows another example of a planar layout of a memory device. The memory device shown in Fig. 28C differs from the memory device shown in Fig. 28B mainly in the shape of the first region of the conductor 240.

[0419] The first region of the conductor 240 shown in Figure 28B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X or Y direction. On the other hand, the first region of the conductor 240 shown in Figure 28C has a rectangular shape with rounded corners in a plan view, and the diagonal of the rectangle is parallel to the X or Y direction. With this configuration, when the memory cells 150 (openings 290) are arranged in a zigzag pattern in the Y direction, the physical distance between the conductors 240 can be reduced. This allows for miniaturization and high integration of the memory device.

[0420] 28B and 28C show an example in which the first region of the conductor 240 has a rectangular shape with rounded corners in a plan view, but the present invention is not limited to this.

[0421] Fig. 29A shows another example of a planar layout of a memory device. The memory device shown in Fig. 29A differs from the memory devices shown in Figs. 28B and 28C mainly in the shape of the first region of the conductor 240.

[0422] 29B has a circular shape in plan view. With this configuration, when the memory cells 150 (openings 290) are arranged in a zigzag pattern in the Y direction, the physical distance between the conductors 240 can be reduced. This allows for miniaturization and high integration of the memory device.

[0423] The shape of the first region of the conductor 240 in plan view is not limited to the above-described shape. For example, the first region of the conductor 240 in plan view may be a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners.

[0424] Furthermore, although FIG. 28A shows a configuration in which the width of the conductor 260 in the direction perpendicular to the direction in which the conductor 260 extends is uniform, the present invention is not limited to this.

[0425] Fig. 29B is another example of a planar layout of a memory device. The memory device shown in Fig. 29B differs from the memory device shown in Fig. 29A mainly in the shape of the conductors 260.

[0426] The conductor 260 shown in FIG. 29B has a first region and a second region, similar to the conductor 240. The first region is circular in plan view. The first region of the conductor 260 overlaps with the first region of the conductor 240. With this configuration, when the memory cells 150 (openings 290) are arranged in a zigzag pattern in the Y direction, the physical distance between the conductors 240 can be reduced. This allows for miniaturization and high integration of the memory device.

[0427] Fig. 29C is another example of a planar layout of a memory device. The memory device shown in Fig. 29C differs from the memory device shown in Fig. 29A mainly in the shape and extension direction of the conductors 260.

[0428] The conductor 260 shown in Figure 29C has a meandering shape like a triangular wave in plan view, and is provided extending in the Y direction. With this configuration, when the memory cells 150 (openings 290) are arranged in a zigzag pattern in the Y direction, the physical distance between the conductors 240 can be reduced. This allows for miniaturization and high integration of the memory device. Note that the conductor 260 in plan view is not limited to the above, and may have a meandering shape, etc.

[0429] With the above configuration, one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240 can be reduced, thereby enabling miniaturization and high integration of the memory device.

[0430] FIG. 30 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0431] 30, the capacitor 100 is provided above the transistor 300, and the transistor 200 is provided above the transistor 300 and the capacitor 100. The transistor 300 is one of the transistors included in the sense amplifier.

[0432] The configuration of the memory cell 150 (the transistor 200 and the capacitor 100) shown in FIG. 30 is as described above.

[0433] 30, the bit line can be shortened by providing a sense amplifier so as to overlap with the memory cell 150. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0434] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not subjected to a thermal history during the manufacture of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0435] 30 can correspond to a memory device 80 described below. Specifically, the transistor 300 corresponds to a transistor included in the sense amplifier 46 in the memory device 80. The memory cell 150 corresponds to the memory cell 32, the transistor 200 corresponds to the transistor 37, and the capacitor 100 corresponds to the capacitor 38.

[0436] The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0437] Here, in the transistor 300 shown in FIG. 30 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0438] Note that the transistor 300 illustrated in FIG. 30 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0439] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0440] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328 is embedded in the insulators 320 and 322, and a conductor 330 is embedded in the insulators 324 and 326. The conductors 328 and 330 function as plugs or wirings.

[0441] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0442] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 30, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0443] The insulators 352, 354, and the like, which function as interlayer films, can be any of the above-mentioned insulators that can be used in a memory device.

[0444] The conductors that function as plugs or wiring, such as the conductors 328, 330, and 356, can be any of the conductors described above. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0445] The conductor 240 of the transistor 200 is electrically connected to the low-resistance region 314b, which functions as the source region or drain region of the transistor 300, via the conductors 643, 642, 644, 645, 646, conductor 356, conductor 330, and conductor 328.

[0446] The conductor 643 is embedded in the insulator 280. The conductor 642 is provided on the insulator 130 and embedded in the insulator 641. The conductor 642 can be manufactured using the same material and in the same process as the conductor 120. The conductor 644 is embedded in the insulator 180 and the insulator 130. The conductor 645 is embedded in the insulator 647. The conductor 645 can be manufactured using the same material and in the same process as the conductor 110. The conductor 646 is embedded in the insulator 648. The insulator 648 electrically insulates the transistor 300 from the conductor 110.

[0447] 31 shows an example in which a functional element 155 functioning as a peripheral circuit is provided instead of the conductors 642, 643, and 644 in Fig. 30. Specifically, the transistor 200 included in the functional element 155 functions as a switch that controls conduction / non-conduction between the conductor 645 electrically connected to one of the source and drain of the transistor 300 and the conductor 240 functioning as a bit line.

[0448] According to one embodiment of the present invention, a novel transistor, a semiconductor device, and a memory device can be provided. Alternatively, a transistor, a semiconductor device, and a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a highly reliable transistor, a semiconductor device, and a memory device can be provided. Alternatively, a transistor with high on-state current and a semiconductor device and a memory device including the transistor can be provided. Alternatively, a semiconductor device and a memory device with little variation in transistor characteristics can be provided. Alternatively, a transistor with good electrical characteristics and a semiconductor device and a memory device including the transistor can be provided. Alternatively, a semiconductor device and a memory device with low power consumption can be provided. Alternatively, a memory device with good frequency characteristics can be provided. Alternatively, a memory device with high operating speed can be provided.

[0449] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0450] 32 to 35. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided will be described.

[0451] 32 is a block diagram illustrating a configuration example of a memory device 80 according to one embodiment of the present invention. The memory device 80 illustrated in FIG. 32 includes a layer 20 and a stacked layer 70.

[0452] The layer 20 is a layer including a Si transistor. In the stacked layer 70, element layers 30[1] to 30[m] (m is an integer of 2 or more) are stacked. The element layers 30[1] to 30[m] are layers including an OS transistor. The layer 70 including a stacked layer of layers including an OS transistor can be stacked on the layer 20.

[0453] The elements such as OS transistors and capacitors included in the element layers 30[1] to 30[m] constitute memory cells. In FIG. 32, the element layers 30[1] to 30[m] each have a plurality of memory cells 32 arranged in a matrix of m rows and n columns (n ​​is an integer of 2 or greater).

[0454] In FIG. 32 , the memory cell 32 in the first row and first column is indicated as memory cell 32[1,1], and the memory cell 32 in the mth row and nth column is indicated as memory cell 32[m,n]. In the present embodiment and the like, an arbitrary row may be referred to as row i. An arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In the present embodiment and the like, the memory cell 32 in the ith row and jth column is indicated as memory cell 32[i,j]. In the present embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is used, "j+α" is not less than 1 or more than n.

[0455] 32 illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n]. Note that the number of element layers 30[1] to 30[m] and the number of wirings WL (and wirings PL) do not necessarily have to be the same.

[0456] The memory cells 32 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 32 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0457] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring CL (not shown) can be separately provided as a wiring for transmitting a back gate potential.

[0458] The memory cells 32 included in each of the element layers 30[1] to 30[m] are connected to the sense amplifier 46 via wiring BL. The wiring BL can be arranged horizontally and vertically on the substrate surface on which the layer 20 is provided. By configuring the wiring BL extending from the memory cells 32 included in the element layers 30[1] to 30[m] with wiring arranged vertically in addition to wiring arranged horizontally on the substrate surface, the length of the wiring between the element layer 30 and the sense amplifier 46 can be shortened. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby realizing reduced power consumption and signal delay. Therefore, the power consumption and signal delay of the memory device 80 can be reduced. Furthermore, it is possible to operate even if the capacitance of the capacitor included in the memory cell 32 is reduced. Therefore, the memory device 80 can be made smaller.

[0459] The layer 20 has a PSW 71 (power switch), a PSW 72, and a peripheral circuit 22. The peripheral circuit 22 has a drive circuit 40, a control circuit 73, and a voltage generation circuit 74. Each circuit in the layer 20 has a Si transistor.

[0460] In the storage device 80, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0461] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 73.

[0462] The control circuit 73 is a logic circuit that has the function of controlling the overall operation of the storage device 80. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the storage device 80. Alternatively, the control circuit 73 generates a control signal for the drive circuit 40 so that this operation mode is executed.

[0463] The voltage generating circuit 74 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 74. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 74, and the voltage generating circuit 74 generates a negative voltage.

[0464] The drive circuit 40 is a circuit for writing and reading data to and from the memory cells 32. The drive circuit 40 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and the sense amplifier 46 described above.

[0465] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cells 32, reading data from the memory cells 32, and holding the read data.

[0466] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 32. The data (Dout) read from the memory cell 32 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 80. The data output from the output circuit 48 is a signal RDA.

[0467] The PSW 71 has a function of controlling the supply of VDD to the peripheral circuit 22. The PSW 72 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 80 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 71 is controlled by the signal PON1, and the on / off of the PSW 72 is controlled by the signal PON2. In FIG. 32, the number of power domains to which VDD is supplied in the peripheral circuit 22 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0468] The layer 70 may be provided with the selector circuit exemplified in the first embodiment. This reduces the load on the bit lines, enabling a memory device with extremely high operating speeds (write speeds and read speeds) to be realized.

[0469] The element layers 30[1] to 30[m] can be stacked on the layer 20. Figure 33A shows a perspective view of the memory device 80 showing five (m = 5) element layers 30[1] to 30[5] stacked on the layer 20.

[0470] In Figure 33A, the element layer 30 provided in the first layer is shown as element layer 30[1], the element layer 30 provided in the second layer is shown as element layer 30[2], and the element layer 30 provided in the fifth layer is shown as element layer 30[5]. Also shown in Figure 33A are wiring WL and wiring PL extending in the X direction, and wiring BL and wiring BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the driver circuit is provided). Wiring BLB is an inversion bit line. Note that, to make the drawing easier to understand, the wiring WL and wiring PL of each element layer 30 are partially omitted.

[0471] 33B is a schematic diagram illustrating a configuration example of the sense amplifier 46 connected to the wiring BL and the wiring BLB shown in FIG. 33A and the memory cells 32 included in the element layers 30[1] to 30[5] connected to the wiring BL and the wiring BLB. Note that a configuration in which a plurality of memory cells (memory cells 32) are electrically connected to one wiring BL and one wiring BLB is also referred to as a “memory string.”

[0472] 33B illustrates an example of a circuit configuration of the memory cell 32 connected to the wiring BLB. The memory cell 32 includes a transistor 37 and a capacitor 38. Regarding the transistor 37, the capacitor 38, and the wirings (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] may also be referred to as wiring BL and wiring WL. The memory cell 150 exemplified in the above embodiment can be applied to the memory cell 32. That is, the transistor 200 can be used as the transistor 37, and the capacitor 100 can be used as the capacitor 38. The transistor 300 (see FIG. 30) can be used as the transistor included in the sense amplifier 46.

[0473] In the memory cell 32, one of the source and the drain of the transistor 37 is connected to a wiring BL. The other of the source and the drain of the transistor 37 is connected to one electrode of a capacitor 38. The other electrode of the capacitor 38 is connected to a wiring PL. The gate of the transistor 37 is connected to a wiring WL.

[0474] Note that in the case where the selector circuit exemplified in Embodiment 1 is applied, the above-described functional element 155 may be connected between the wiring BL and the memory cell 32 .

[0475] The wiring PL is a wiring that applies a constant potential for maintaining the potential of the capacitor 38. The number of wirings can be reduced by connecting the plurality of wirings PL to each other as one wiring.

[0476] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged in a direction perpendicular to the surface of the substrate on which the layer 20 is provided. Additionally, the transistor 37 and the capacitor 38 included in the memory cell 32 are arranged side by side in a direction perpendicular to the surface of the substrate on which the layer 20 is provided. By providing each element and each wiring in a direction perpendicular to the surface of the substrate, the length of the wiring between element layers can be shortened and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent storage capacity and reduced power consumption can be obtained.

[0477] 34A and 34B show circuit diagrams corresponding to the memory cell 32 described above and diagrams for explaining circuit blocks corresponding to the circuit diagrams. As shown in FIGS. 34A and 34B, the memory cell 32 may be represented as a block in the drawings. Note that the wiring BL shown in FIGS. 34A and 34B can be represented in the same way even when replaced with wiring BLB.

[0478] 34C and 34D show a circuit diagram corresponding to the sense amplifier 46 and a diagram for explaining a circuit block corresponding to the circuit diagram. The sense amplifier 46 includes a switch circuit 82, a precharge circuit 83, a precharge circuit 84, and an amplifier circuit 85. In addition to the wiring BL and the wiring BLB, the diagram also shows wirings SA_OUT and SA_OUTB for outputting read signals.

[0479] 34C, the switch circuit 82 includes, for example, n-channel transistors 82_1 and 82_2. The transistors 82_1 and 82_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.

[0480] 34C , the precharge circuit 83 is formed of n-channel transistors 83_1 to 83_3. The precharge circuit 83 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQ.

[0481] 34C, the precharge circuit 84 is formed of p-channel transistors 84_1 to 84_3. The precharge circuit 84 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQB.

[0482] 34C , the amplifier circuit 85 includes p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN has a function of supplying VDD or VSS. The transistors 85_1 to 85_4 are transistors that form an inverter loop.

[0483] 34D shows a diagram for explaining a circuit block corresponding to the sense amplifier 46 described in FIG. 34C etc. As shown in FIG. 34D, the sense amplifier 46 may be represented as a block in the drawings etc.

[0484] Fig. 35 is a circuit diagram of the memory device 80 of Fig. 32. Fig. 35 illustrates the circuit blocks described in Fig. 34A to Fig. 34D.

[0485] 35, a layer 70 including an element layer 30[m] includes a memory cell 32. The memory cell 32 illustrated in FIG. 35 is connected to a pair of wirings BL[1] and BLB[1] or wirings BL[2] and BLB[2], for example. The memory cell 32 connected to the wiring BL is a memory cell to which data is written or read.

[0486] The wiring BL[1] and the wiring BLB[1] are connected to a sense amplifier 46[1], and the wiring BL[2] and the wiring BLB[2] are connected to a sense amplifier 46[2]. The sense amplifier 46[1] and the sense amplifier 46[2] can read data in response to various signals described with reference to FIG.

[0487] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0488] Embodiment 3 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0489] [Electronic Component] FIG. 36A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 36A has semiconductor device 710 inside mold 711. FIG. 36A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0490] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0491] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0492] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0493] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0494] 36B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on interposer 731.

[0495] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0496] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0497] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0498] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0499] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0500] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0501] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0502] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 36B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0503] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0504] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 37A . The electronic device 6500 shown in FIG. 37A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0505] 37B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0506] [Mainframe] Next, Fig. 37C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 37C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0507] The computer 5620 can have the configuration shown in the perspective view in Fig. 37D, for example. In Fig. 37D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0508] PC card 5621 shown in Figure 37E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that although Figure 37E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referenced for information on these semiconductor devices.

[0509] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0510] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0511] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0512] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0513] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0514] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0515] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0516] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0517] Fig. 38A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 38A shows a planet 6804 in space as an example.

[0518] 38A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0519] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0520] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0521] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0522] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0523] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0524] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0525] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0526] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0527] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0528] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0529] Fig. 38B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 38B has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0530] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0531] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0532] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0533] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced.

[0534] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0535] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0536] 100: capacitor, 101: connection, 110: conductor, 115: conductor, 120A: conductive film, 120: conductor, 125: conductor, 130: insulator, 131: insulator, 135: insulator, 140: insulator, 145: resist mask, 146: opening, 150a: memory cell, 150b: memory cell, 150c: memory cell, 150d: memory cell, 150: memory cell, 155: functional element, 160: memory unit, 170: layer, 180a: insulator, 180b: insulator, 180: insulator, 182: insulator, 185: insulator, 190: opening, 200a: transistor transistor, 200b: transistor, 200: transistor, 230a: oxide semiconductor, 230b: oxide semiconductor, 230i: region, 230na: region, 230nb: region, 230: oxide semiconductor, 240A: conductive film, 240: conductor, 245: conductor, 246: conductor, 250a: insulator, 250b: insulator, 250c: insulator, 250: insulator, 260a: conductor, 260A: conductive film, 260b: conductor, 260: conductor, 280a: insulator, 280b: insulator, 280c: insulator, 280: insulator, 283: insulator, 287: insulator, 290: opening

Claims

1. It comprises a first transistor, a connector, a first insulator, a second insulator, and a first wiring. The connecting portion has a first electrode and a second electrode, The first transistor comprises the second electrode, the third electrode, the first semiconductor, the gate insulator, and the first gate electrode. The first insulator is provided on the first wiring and has a first opening that reaches the first wiring. The first electrode has a first portion that contacts the side surface of the first opening of the first insulator, and a second portion that contacts the upper surface of the first wiring. The second electrode is embedded in the first opening and in contact with the second portion of the first electrode. The second insulator is provided on the first insulator and has a second opening that reaches the second electrode. The third electrode is provided on the second insulator, The first semiconductor has a third portion that contacts the third electrode, a fourth portion that contacts the side surface of the second opening of the second insulator, and a fifth portion that contacts the upper surface of the second electrode. The gate insulator is located within the second opening and is in contact with the fourth and fifth portions of the first semiconductor. The first gate electrode is located within the second opening and faces the third, fourth, and fifth portions of the first semiconductor via the gate insulator. A fourth insulator is provided, The fourth insulator is located within the first opening and in contact with the first portion of the first electrode. The second electrode is in contact with the fourth insulator. Semiconductor equipment.

2. In claim 1, It further comprises a capacitive element and a second wiring, The capacitive element has a fourth electrode, a fifth electrode, and a third insulator. The first insulator has a third opening that reaches the second wiring, The fourth electrode has a sixth portion that contacts the side wall within the third opening of the first insulator, and a seventh portion that contacts the upper surface of the second wiring. The third insulator is located within the third opening and is in contact with the sixth and seventh portions of the fourth electrode. The fifth electrode is embedded in the third opening and faces the sixth and seventh portions of the fourth electrode via the third insulator. Semiconductor equipment.

3. In claim 2, The capacitive element further comprises a second transistor, The second transistor has the fifth electrode, the sixth electrode, the second semiconductor, the gate insulator, and the second gate electrode. The second insulator has a fourth opening that reaches the fifth electrode, The sixth electrode is provided on the second insulator, The second semiconductor has an eighth portion that contacts the sixth electrode, a ninth portion that contacts the side wall within the fourth opening of the second insulator, and a tenth portion that contacts the upper surface of the fifth electrode. The gate insulator is located within the fourth opening and is in contact with the ninth and tenth portions of the second semiconductor. The second gate electrode is located within the fourth opening and faces the eighth, ninth, and tenth portions of the second semiconductor via the gate insulator. Semiconductor equipment.

4. In any one of claims 1 to 3, The second electrode is in contact with the first portion of the first electrode, Semiconductor equipment.

5. In any one of claims 1 to 3, The second electrode comprises a first conductor and a second conductor on the first conductor. The first conductor is embedded in the first opening and in contact with the second portion of the first electrode. The second conductor is in contact with the first semiconductor. Semiconductor equipment.