Quantum device, quantum computer, and method for manufacturing quantum device

Abstract

This quantum device includes: a substrate; a first superconductor layer provided on the substrate; and a first wiring that is electrically connected to the first superconductor layer. The first superconductor layer includes: a first lower surface that is in contact with the substrate; a first side surface that is continuous with the first lower surface; and a first upper surface that is continuous with the first side surface. The first side surface includes: a first flat surface that is continuous with the first upper surface; and a first curved surface that is continuous with the first flat surface and the first lower surface. The center of curvature of the first curved surface is located on the first superconductor layer-side when viewed from the first curved surface. The first wiring is in contact with the first upper surface and the first flat surface.

Description

Quantum device, quantum computing device, and method of manufacturing quantum device

[0001] The present disclosure relates to quantum devices, quantum processing apparatus, and methods for manufacturing quantum devices.

[0002] Quantum computing devices such as quantum computers are known to use superconductors. In quantum computing devices using superconductors, quantum bits, signal readout units, filter units, resonator units, etc. are configured using a superconductor layer formed on a substrate. When in use, the quantum bits, signal readout units, filter units, resonator units, etc. are cooled to extremely low temperatures using a dilution refrigerator or the like.

[0003] US Patent Application Publication No. 2020 / 0328338 US Patent Application Publication No. 2017 / 0084813 JP 2008-218439 A JP 61-42179 A

[0004] In quantum computing devices, electric fields tend to concentrate near the boundary between the side surfaces of the superconductor layer and the top surface of the substrate. When electric field concentration occurs in the superconductor layer, decoherence is likely to occur. Furthermore, simply changing the shape of the superconductor layer to mitigate electric field concentration can lead to disconnections in the wiring connected to the superconductor layer.

[0005] An object of the present disclosure is to provide a quantum device, a quantum processing apparatus, and a method for manufacturing a quantum device that can mitigate electric field concentration in a superconductor layer while suppressing disconnection of wiring.

[0006] According to one aspect of the present disclosure, there is provided a quantum device comprising: a substrate; a first superconductor layer provided on the substrate; and first wiring electrically connected to the first superconductor layer, wherein the first superconductor layer has a first lower surface in contact with the substrate, a first side surface continuous with the first lower surface, and a first upper surface continuous with the first side surface, the first side surface having a first plane continuous with the first upper surface and a first curved surface continuous with the first plane and the first lower surface, the center of curvature of the first curved surface being on the first superconductor layer side as viewed from the first curved surface, and the first wiring contacting the first upper surface and the first plane.

[0007] According to the present disclosure, it is possible to reduce electric field concentration in a superconductor layer while suppressing disconnection of wiring.

[0008] FIG. 1 is a plan view showing a quantum device according to the first embodiment. FIG. 2 is a cross-sectional view showing a quantum device according to the first embodiment. FIG. 3 is a cross-sectional view (part 1) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 4 is a cross-sectional view (part 2) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 5 is a cross-sectional view (part 3) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 6 is a cross-sectional view (part 4) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 7 is a cross-sectional view (part 5) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 8 is a cross-sectional view (part 6) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 9 is a cross-sectional view (part 7) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 10 is a plan view (part 1) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 11 is a plan view (part 2) showing a first example of a method for manufacturing a quantum device according to the first embodiment. FIG. 12 is a plan view (part 3) showing a first example of the method for manufacturing a quantum device according to the first embodiment. FIG. 13 is a cross-sectional view (part 1) showing a second example of the method for manufacturing a quantum device according to the first embodiment. FIG. 14 is a cross-sectional view (part 2) showing the second example of the method for manufacturing a quantum device according to the first embodiment. FIG. 15 is a cross-sectional view (part 3) showing the second example of the method for manufacturing a quantum device according to the first embodiment. FIG. 16 is a cross-sectional view (part 4) showing the second example of the method for manufacturing a quantum device according to the first embodiment. FIG. 17 is a cross-sectional view (part 5) showing the second example of the method for manufacturing a quantum device according to the first embodiment. FIG. 18 is a cross-sectional view (part 6) showing the second example of the method for manufacturing a quantum device according to the first embodiment. FIG. 19 is a diagram showing a quantum processing apparatus according to the second embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description may be omitted.

[0010] (First Embodiment) A first embodiment will be described. The first embodiment relates to a quantum device. FIG. 1 is a plan view showing a quantum device according to the first embodiment. FIG. 2 is a cross-sectional view showing the quantum device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0011] As shown in Figures 1 and 2, the quantum device 1 according to the first embodiment has a substrate 10, a first superconductor layer 21, a second superconductor layer 22, a first wiring 31, and a second wiring 32.

[0012] The substrate 10 is, for example, a silicon substrate. The first superconductor layer 21 and the second superconductor layer 22 are provided on the substrate 10. The first superconductor layer 21 and the second superconductor layer 22 are spaced apart from each other. The material of the first superconductor layer 21 and the second superconductor layer 22 is, for example, niobium. The thickness of the first superconductor layer 21 and the second superconductor layer 22 is, for example, 200 nm.

[0013] The first superconductor layer 21 has a first lower surface 21A, a first upper surface 21B, and a first side surface 21C. The first lower surface 21A is in contact with the substrate 10. The first side surface 21C is continuous with the first lower surface 21A. The first upper surface 21B is continuous with the first side surface 21C. The first lower surface 21A and the first upper surface 21B are, for example, planes parallel to each other. The first side surface 21C has a first flat surface 51A and a first curved surface 51B. The first flat surface 51A is continuous with the first upper surface 21B. The first curved surface 51B is continuous with the first flat surface 51A and the first lower surface 21A. A first interior angle θ1 of the first superconductor layer 21 at the boundary between the first upper surface 21B and the first flat surface 51A is, for example, 90 degrees or more, preferably 90 degrees or more and 100 degrees or less, and more preferably 90 degrees or more and 95 degrees or less. The center of curvature of the first curved surface 51B is on the first superconductor layer 21 side as viewed from the first curved surface 51B. Therefore, the first curved surface 51B is a curved surface that is convex outward. For example, the curvature of the first curved surface 51B changes continuously from the boundary with the first flat surface 51A to the boundary with the first lower surface 21A.

[0014] The second superconductor layer 22 has a second lower surface 22A, a second upper surface 22B, and a second side surface 22C. The second lower surface 22A is in contact with the substrate 10. The second side surface 22C is continuous with the second lower surface 22A. The second upper surface 22B is continuous with the second side surface 22C. The second lower surface 22A and the second upper surface 22B are, for example, planes parallel to each other. The second side surface 22C has a second flat surface 52A and a second curved surface 52B. The second flat surface 52A is continuous with the second upper surface 22B. The second curved surface 52B is continuous with the second flat surface 52A and the second lower surface 22A. A second interior angle θ2 of the second superconductor layer 22 at the boundary between the second upper surface 22B and the second flat surface 52A is 90 degrees or more, preferably 90 degrees or more and 100 degrees or less, and more preferably 90 degrees or more and 95 degrees or less. The center of curvature of the second curved surface 52B is on the second superconductor layer 22 side as viewed from the second curved surface 52B. Therefore, the second curved surface 52B is a curved surface that is convex outward. For example, the curvature of the second curved surface 52B changes continuously from the boundary with the second flat surface 52A to the boundary with the second lower surface 22A.

[0015] The first wiring 31 has a base 31A and a fine wiring portion 31B. The base 31A contacts the first upper surface 21B and the first plane 51A of the first superconductor layer 21. The first wiring 31 is electrically connected to the first superconductor layer 21. The base 31A also contacts the substrate 10. The base 31A has a substantially rectangular planar shape in a planar view. When the planar shape of the base 31A is approximated to a rectangle, the length of the shortest side is several μm. The base 31A extends from the first superconductor layer 21 toward the second superconductor layer 22. The fine wiring portion 31B extends from the end of the base 31A on the second superconductor layer 22 side toward the second superconductor layer 22. When the planar shape of the fine wiring portion 31B is approximated to a rectangle, the length of the shortest side is several nm. The fine wiring portion 31B contacts the substrate 10.

[0016] The first wiring 31 includes a metal layer 31X and a metal layer 31Y. The metal layers 31X and 31Y are made of a superconductor such as aluminum. The thickness of each of the metal layers 31X and 31Y is, for example, several tens of nanometers. The metal layer 31X is provided across the base 31A and the micro-wiring portion 31B. An insulator layer 41 is formed on the surface of the metal layer 31X, except for the portion in contact with the first superconductor layer 21. The insulator layer 41 has a first region 41A and a second region 41B. The first region 41A covers the portion of the metal layer 31X within the base 31A. The second region 41B covers the portion of the metal layer 31X within the micro-wiring portion 31B. The metal layer 31Y is provided on the first region 41A within the base 31A. The thickness of the insulator layer 41 is approximately several nanometers. In the base portion 31A, the first region 41A does not substantially electrically insulate the metal layer 31X from the metal layer 31Y, and the metal layer 31X and the metal layer 31Y are electrically connected to each other.

[0017] The second wiring 32 has a base 32A and a fine wiring portion 32B. The base 32A contacts the second upper surface 22B and the second plane 52A of the second superconductor layer 22. The second wiring 32 is electrically connected to the second superconductor layer 22. The base 32A also contacts the substrate 10. The base 32A has a substantially rectangular planar shape in a planar view. When the planar shape of the base 32A is approximated to a rectangle, the length of the shortest side is several μm. The base 32A extends from the second superconductor layer 22 toward the first superconductor layer 21. The fine wiring portion 32B extends from near the end of the base 32A on the first superconductor layer 21 side toward the fine wiring portion 31B of the first wiring 31. In a planar view, the fine wiring portion 32B intersects with the fine wiring portion 31B. When the planar shape of the fine wiring portion 32B is approximated to a rectangle, the length of the shortest side is several nanometers.

[0018] The second wiring 32 includes a metal layer 32X and a metal layer 32Y. The metal layers 32X and 32Y are made of a superconductor such as aluminum. The thickness of each of the metal layers 32X and 32Y is, for example, several tens of nanometers. The metal layer 32X is provided on the base 31A. An insulator layer 42 is formed on the surface of the metal layer 32X, except for the portion that contacts the second superconductor layer 22. The metal layer 32Y is provided on the insulator layer 42 across the base 32A and the micro-wiring portion 32B. The thickness of the insulator layer 42 is approximately several nanometers. The insulator layer 42 does not substantially electrically insulate the metal layer 32X from the metal layer 32Y, and the metal layer 32X and the metal layer 32Y are electrically connected to each other.

[0019] The portion of the fine wiring portion 32B that intersects with the fine wiring portion 31B in a plan view is located on the second region 41B of the insulator layer 41. That is, a part of the second region 41B is provided between the fine wiring portion 31B of the first wiring 31 and the fine wiring portion 32B of the second wiring 32. Because the portions of the fine wiring portions 31B and 32B that face each other via the second region 41B are very small, the fine wiring portions 31B and 32B are not electrically connected, and a Josephson junction 5 is formed by the fine wiring portion 31B, the second region 41B of the insulator layer 41, and the fine wiring portion 32B.

[0020] Next, a first example of a method for manufacturing the quantum device 1 according to the first embodiment will be described. Figures 3 to 9 are cross-sectional views showing the first example of a method for manufacturing the quantum device 1 according to the first embodiment. Figures 10 to 12 are plan views showing the first example of a method for manufacturing the quantum device 1 according to the first embodiment. Figures 3 to 9 show changes in the cross section taken along line II-II in Figure 1.

[0021] First, as shown in FIG. 3, a substrate 11 is prepared. The substrate 11 includes a substrate 10 and a silicon oxide film 12. The substrate 11 is a silicon substrate with an oxide film, and the silicon oxide film 12 is formed on the substrate 10. For example, the substrate 11 can be formed by thermal oxidation of a silicon substrate. A commercially available silicon substrate with an oxide film may be used as the substrate 11. The thickness of the silicon oxide film 12 is, for example, 300 nm. The silicon oxide film 12 is an example of a sacrificial layer.

[0022] Next, a photoresist pattern 71 is formed on the silicon oxide film 12. The thickness of the pattern 71 is, for example, 700 nm. The pattern 71 can be formed by photolithography. The pattern 71 is formed so as to expose a region where the first superconductor layer 21 and a region where the second superconductor layer 22 are to be formed. The pattern 71 is an example of a first mask.

[0023] 4, the silicon oxide film 12 is processed to a thickness of 200 nm by reactive ion etching (RIE) using the pattern 71 as an etching mask. In the RIE, for example, a parallel plate type RIE apparatus is used, and CF 4 is used as an etching gas. ４ The etching gas is used, with a gas flow rate of 10 sccm, an etching power of 300 W, and an etching pressure of 0.5 Pa. RIE is performed from a direction perpendicular to the top surface of the substrate 10, and the side surface of the portion covered by the pattern 71 becomes a plane perpendicular to the top surface of the substrate 10. Following the RIE, the silicon oxide film 12 is processed to a thickness of 100 nm by wet etching using the pattern 71 as an etching mask. A hydrofluoric acid solution with a concentration of 5% by mass is used as the etchant in the wet etching. The top surface of the substrate 10 is exposed by the wet etching. The side surface of the remaining portion 12A of the silicon oxide film 12 has a third plane 13A perpendicular to the top surface of the substrate 10 and a third curved surface 13B below it.

[0024] Subsequently, as shown in FIG. 5 , the pattern 71 is removed. Next, a superconductor layer 26 is formed on the substrate 10 and the remaining portion 12A of the silicon oxide film 12, the superconductor layer 26 being thinner than the remaining portion 12A. The material of the superconductor layer 26 is, for example, niobium. The thickness of the superconductor layer 26 is, for example, 200 nm. The superconductor layer 26 can be formed by, for example, a sputtering method. When forming the superconductor layer 26 by a sputtering method, for example, the flow rate of argon gas is set to 20 sccm, the process pressure is set to 0.25 Pa, and the direct current (DC) value is set to 3 A.

[0025] Next, as shown in FIG. 6 , the remaining portion 12A of the silicon oxide film 12 is removed. The remaining portion 12A can be removed using, for example, a 5% by mass hydrofluoric acid solution. By removing the remaining portion 12A, the superconductor layer 26 on the upper surface of the remaining portion 12A is also removed. As a result, the first superconductor layer 21 and the second superconductor layer 22 are formed. The first side surface 21C of the first superconductor layer 21 has a first flat surface 51A that conforms to one of the third flat surfaces 13A and a first curved surface 51B that conforms to one of the third curved surfaces 13B. The second side surface 22C of the second superconductor layer 22 has a second flat surface 52A that conforms to the other of the third flat surfaces 13A and a second curved surface 52B that conforms to the other of the third curved surfaces 13B.

[0026] Then, a lift-off deposition mask (not shown) is formed to form the first wiring 31 and the second wiring 32. The deposition mask has a two-layer structure including a polymer mask and a resist mask thereon. Then, as shown in FIGS. 7 and 10 , metal layers 31X and 32X are formed by vapor deposition. When forming the metal layers 31X and 32X, as shown in FIG. 10 , raw material 81 is supplied from a direction tilted from a direction perpendicular to the upper surface of the substrate 10. More specifically, in a plan view, raw material 81 is supplied so that the raw material 81 flows from the end of the micro-wiring portion 31B on the base 31A side to the end of the micro-wiring portion 31B on the second superconductor layer 22 side. When raw material 81 is supplied from this direction, the raw material 81 does not reach the region of the second wiring 32 where the micro-wiring portion 32B is to be formed, and no metal layer is formed. For example, the deposition rate of the metal layers 31X and 32X is 0.5 nm / sec, and the thickness of the metal layers 31X and 32X is several tens of nanometers. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG.

[0027] 8 and 11, the surfaces of the metal layers 31X and 32X are oxidized to form an insulator layer 41 on the surface of the metal layer 31X and an insulator layer 42 on the surface of the metal layer 32X. In forming the insulator layers 41 and 42, for example, the process pressure in the chamber of the vapor deposition apparatus used to form the metal layers 31X and 32X is set to 1 Torr (approximately 133.32 Pa), and oxygen gas is supplied into the chamber. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG. 11.

[0028] Next, as shown in FIGS. 9 and 12 , metal layers 31Y and 32Y are formed by vapor deposition. When forming the metal layers 31Y and 32Y, raw material 82 is supplied from a direction inclined relative to the direction perpendicular to the upper surface of the substrate 10. More specifically, in a plan view, raw material 82 is supplied so that the raw material 82 flows from the end of the micro-wiring portion 32B on the base 32A side to the end of the micro-wiring portion 31B side. When raw material 82 is supplied from this direction, the raw material 82 does not reach the region of the first wiring 31 where the micro-wiring portion 31B is to be formed, and no metal layer is formed. For example, the deposition rate of the metal layers 31Y and 32Y is 0.5 nm / sec, and the thickness of the metal layers 31Y and 32Y is several tens of nanometers. FIG. 9 corresponds to a cross-sectional view taken along line IX-IX in FIG. 12 .

[0029] Thereafter, the resist mask of the film formation mask is removed. As the resist mask is removed, the metal layer formed on the resist mask is also removed. Subsequently, the polymer mask of the film formation mask is removed.

[0030] In this manner, the quantum device 1 according to the first embodiment can be manufactured.

[0031] Next, a second example of the method for manufacturing the quantum device 1 according to the first embodiment will be described. Figures 13 to 18 are cross-sectional views showing the second example of the method for manufacturing the quantum device 1 according to the first embodiment. Figures 13 to 18 show changes in the cross section taken along line II-II in Figure 1.

[0032] First, as shown in FIG. 13 , a substrate 11 is prepared in the same manner as in the first example. The substrate 11 includes a substrate 10 and a silicon oxide film 12. The silicon oxide film 12 has a thickness of, for example, 300 nm. Next, a photoresist pattern 71 is formed on the silicon oxide film 12. The silicon oxide film 12 is an example of a sacrificial layer. The pattern 71 is an example of a first mask.

[0033] 14, the silicon oxide film 12 is processed to a thickness of 300 nm by wet etching using the pattern 71 as an etching mask. In the wet etching, a hydrofluoric acid solution with a concentration of 5% by mass is used as an etchant. The wet etching exposes the top surface of the substrate 10. The side surface of the remaining portion 12A of the silicon oxide film 12 has a fourth curved surface 13C.

[0034] Subsequently, as shown in FIG. 15 , the pattern 71 is removed. Next, a stencil mask 72 is formed on the remaining portion 12A of the silicon oxide film 12. The stencil mask 72 is formed to be wider than the remaining portion 12A in a plan view. The stencil mask 72 is formed so as to expose the region where the first superconductor layer 21 is to be formed and the region where the second superconductor layer 22 is to be formed. The stencil mask 72 has a side surface 72A that is perpendicular to the upper surface of the substrate 10. For example, in a plan view, the edge of the stencil mask 72 is located 150 nm outward from the edge of the upper surface of the remaining portion 12A. The material of the stencil mask 72 is, for example, a metal such as nickel. The stencil mask 72 is an example of a second mask.

[0035] 16, a superconductor layer 26 is formed on the substrate 10, the remaining portion 12A of the silicon oxide film 12, and the stencil mask 72 so as to be thinner than the remaining portion 12A. The thickness of the superconductor layer 26 is, for example, 200 nm.

[0036] 17, the stencil mask 72 is removed. By removing the stencil mask 72, the superconductor layer 26 on the stencil mask 72 is removed. As a result, the first superconductor layer 21 and the second superconductor layer 22 are formed. The first side surface 21C of the first superconductor layer 21 has a first flat surface 51A that follows the side surface 72A of the stencil mask 72 and a first curved surface 51B that follows one of the fourth curved surfaces 13C. The second side surface 22C of the second superconductor layer 22 has a second flat surface 52A that follows the side surface 72A of the stencil mask 72 and a second curved surface 52B that follows the other of the fourth curved surfaces 13C.

[0037] 18, the remaining portion 12A of the silicon oxide film 12 is removed. The remaining portion 12A can be removed using, for example, a hydrofluoric acid solution with a concentration of 5 mass %.

[0038] Thereafter, the first wiring 31 and the second wiring 32 are formed in the same manner as in the first example.

[0039] In this manner, the quantum device 1 according to the first embodiment can be manufactured.

[0040] In the quantum device 1 according to the first embodiment, the first side surface 21C of the first superconductor layer 21 has a first plane 51A, and the first wiring 31 contacts the first top surface 21B of the first superconductor layer 21 and the first plane 51A. Furthermore, the first interior angle θ1 of the first superconductor layer 21 at the boundary between the first top surface 21B and the first plane 51A is 90 degrees or greater. If the first interior angle θ1 were less than 90 degrees, a large stress would act on the first wiring 31 near the boundary between the first top surface 21B and the first plane 51A, potentially causing a break in the first wiring 31. In contrast, in the present embodiment, the first interior angle θ1 is 90 degrees or greater, thereby preventing breakage of the first wiring 31.

[0041] Furthermore, when the first plane 51A reaches the upper surface of the substrate 10, electric field concentration is likely to occur in the first superconductor layer 21 near the lower end of the first plane 51A. In contrast, in this embodiment, the first plane 51A does not reach the upper surface of the substrate 10, but the first curved surface 51B continuing from the first plane 51A reaches the upper surface of the substrate 10. Furthermore, the center of curvature of the first curved surface 51B is on the first superconductor layer 21 side when viewed from the first curved surface 51B. Therefore, electric field concentration in the first superconductor layer 21 can be alleviated.

[0042] As described above, according to the first embodiment, it is possible to alleviate the electric field concentration in the first superconductor layer 21 while suppressing the breakage of the first wiring 31. Similarly, it is possible to alleviate the electric field concentration in the second superconductor layer 22 while suppressing the breakage of the second wiring 32.

[0043] The first interior angle θ1 is 90 degrees or more, but the larger the first interior angle θ1, the smaller the interior angle of the first superconductor layer 21 at the boundary between the first flat surface 51A and the first curved surface 51B becomes, and if the first interior angle θ1 is too large, there is a risk of breakage of the first wiring 31 occurring in this vicinity. The first interior angle θ1 is preferably 90 degrees or more and 100 degrees or less, and more preferably 90 degrees or more and 95 degrees or less. For the same reason, the second interior angle θ2 is preferably 90 degrees or more and 100 degrees or less, and more preferably 90 degrees or more and 95 degrees or less.

[0044] Furthermore, if the dimension L1 of the first plane 51A in the thickness direction of the first superconductor layer 21 is too small, a large stress is likely to act on the first wiring 31 near the first plane 51A, which may result in disconnection. The dimension L1 is preferably 50 nm or more, and more preferably 100 nm or more. For the same reason, the dimension L2 of the second plane 52A in the thickness direction of the second superconductor layer 22 is preferably 50 nm or more, and more preferably 100 nm or more.

[0045] The quantum device 1 may also include a filter, a resonator, or the like that includes a superconductor layer on the substrate 10. This superconductor layer can be formed simultaneously with the first superconductor layer 21 and the second superconductor layer 22, and like the first superconductor layer 21 and the second superconductor layer 22, its side surface may include flat and curved surfaces.

[0046] In the method for manufacturing the quantum device 1, a commercially available silicon substrate with an oxide film may be used as the substrate 11.

[0047] Second Embodiment A second embodiment will be described. The second embodiment relates to a quantum processing device including Josephson devices. Fig. 19 is a diagram showing a quantum processing device according to the second embodiment.

[0048] As shown in FIG. 19 , the quantum processing device 2 according to the second embodiment includes a quantum bit chip 810, a signal generator 820, a signal demodulator 830, and a cryogenic dilution refrigerator 840. The quantum bit chip 810 is housed in the cryogenic dilution refrigerator 840 and cooled to a temperature of 10 mK or less. The signal generator 820 generates a microwave pulse signal, and the microwave pulse signal is input to the quantum bit chip 810. The quantum bit chip 810 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 830 demodulates the signal output from the quantum bit chip 810. The signal generator 820 and the signal demodulator 830 are used at a temperature of, for example, about room temperature.

[0049] The quantum bit chip 810 includes a plurality of superconducting quantum bits 850, and each superconducting quantum bit 850 has a Josephson element 851 and a capacitor 852 electrically connected in parallel to the Josephson element 851. The Josephson element 851 has a configuration similar to that of the quantum device 1 according to the first embodiment, and includes a Josephson junction 5, with the first superconductor layer 21 and the second superconductor layer 22 connected to the capacitor 852. The quantum bit chip 810 may further include a filter, a resonator, and the like.

[0050] The Josephson junction 851 included in the quantum processing device 2 according to the second embodiment has a configuration similar to that of the quantum device 1, and therefore, it is possible to mitigate electric field concentration in the superconductor layer while suppressing disconnection of wiring. Therefore, it is possible to suppress decoherence and perform quantum computing with excellent reliability.

[0051] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0052] 1: Quantum device 2: Quantum processing device 5: Josephson junction 10: Substrate 12: Silicon oxide film 13A: Third plane 13B: Third curved surface 13C: Fourth curved surface 21: First superconductor layer 21A: First lower surface 21B: First upper surface 21C: First side surface 22: Second superconductor layer 22A: Second lower surface 22B: Second upper surface 22C: Second side surface 26: Superconductor layer 31: First wiring 32: Second wiring 31A, 32A: Base 31B, 32B: Micro-wiring portion 31X, 31Y, 32X, 32Y: Metal layer 41, 42: Insulator layer 51A: First plane 51B: First curved surface 52A: Second plane 52B: Second curved surface 71: Pattern 72: Stencil mask 72A: Side surface 850: Superconducting quantum bit 851: Josephson element

Claims

1. A substrate; a first superconductor layer disposed on the substrate; a first wiring electrically connected to the first superconductor layer; having The first superconductor layer is a first lower surface in contact with the substrate; a first side surface connected to the first lower surface; a first upper surface connected to the first side surface; having The first aspect is a first plane connected to the first upper surface; a first curved surface connected to the first flat surface and the first lower surface; having a center of curvature of the first curved surface is on the first superconductor layer side as viewed from the first curved surface; A quantum device, characterized in that the first wiring is in contact with the first top surface and the first plane.

2. 2. The quantum device according to claim 1, wherein the first wiring is made of a superconductor.

3. 3. The quantum device according to claim 1, wherein a first interior angle of the first superconductor layer at a boundary between the first top surface and the first plane is greater than or equal to 90 degrees and less than or equal to 100 degrees.

4. a second superconductor layer disposed on the substrate; a second wiring electrically connected to the second superconductor layer; having The second superconductor layer is a second lower surface in contact with the substrate; a second side surface connected to the second lower surface; a second upper surface connected to the second side surface; having The second side surface is a second plane connected to the second upper surface; a second curved surface connected to the second plane and the second lower surface; having a center of curvature of the second curved surface is on the second superconductor layer side as viewed from the second curved surface; the second wiring is in contact with the second upper surface and the second flat surface; 3. The quantum device according to claim 1, further comprising an insulating layer provided between the first wiring and the second wiring.

5. 5. The quantum device according to claim 4, wherein the second wiring is made of a superconductor.

6. 5. The quantum device of claim 4, wherein a second interior angle of the second superconductor layer at a boundary between the second top surface and the second plane is greater than or equal to 90 degrees and less than or equal to 100 degrees.

7. A quantum computing apparatus comprising the quantum device according to claim 1 or 2.

8. forming a first mask on a sacrificial layer provided on a substrate; forming, on a side surface of the sacrificial layer, a third curved surface continuous with the upper surface of the substrate and a third plane continuous with the upper surface of the sacrificial layer and the third curved surface by etching the sacrificial layer using the first mask; removing the first mask after the step of forming the third curved surface and the third flat surface; forming a third superconductor layer on the substrate and the sacrificial layer, the third superconductor layer being thinner than the sacrificial layer; removing the sacrificial layer and the third superconductor layer on an upper surface of the sacrificial layer to form a first superconductor layer from the third superconductor layer formed on the substrate; forming a first wiring connected to the first superconductor layer after removing the sacrificial layer and the third superconductor layer on the upper surface of the sacrificial layer; having The first superconductor layer is a first lower surface in contact with the substrate; a first side surface connected to the first lower surface; a first upper surface connected to the first side surface; having The first aspect is a first plane that corresponds to the third plane and is continuous with the first upper surface; a first curved surface following the third curved surface and continuing to the first flat surface and the first lower surface; having a center of curvature of the first curved surface is on the first superconductor layer side as viewed from the first curved surface; A method for manufacturing a quantum device, wherein the first wiring is in contact with the first top surface and the first flat surface.

9. forming a first mask on a sacrificial layer provided on a substrate; forming a fourth curved surface, which is continuous with an upper surface of the substrate, on a side surface of the sacrificial layer by etching the sacrificial layer using the first mask; removing the first mask after the step of forming the fourth curved surface; forming a second mask on the sacrificial layer such that an edge of the second mask is positioned outside an edge of the sacrificial layer in a plan view; forming a third superconductor layer on the substrate and the second mask, the third superconductor layer being thinner than the sacrificial layer; removing the second mask and the third superconductor layer on an upper surface of the second mask to form a first superconductor layer from the third superconductor layer formed on the substrate; removing the sacrificial layer after the step of forming the first superconductor layer; forming a first wiring connected to the first superconductor layer after the step of removing the sacrificial layer; having The first superconductor layer is a first lower surface in contact with the substrate; a first side surface connected to the first lower surface; a first upper surface connected to the first side surface; having The first aspect is a first plane extending along the side surface of the second mask and connected to the first upper surface; a first curved surface following the fourth curved surface and continuing to the first flat surface and the first lower surface; having a center of curvature of the first curved surface is on the first superconductor layer side as viewed from the first curved surface; A method for manufacturing a quantum device, wherein the first wiring is in contact with the first top surface and the first flat surface.