Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device (1) includes a plurality of standard cell rows (10) having a plurality of standard cells (11) arranged in the X direction and a plurality of power supply wirings (L1) extending in the X direction and supplying power to the plurality of standard cells (11), a plurality of strap power supply wirings (30) extending in the Y direction, a plurality of sub-strap power supply wirings (40) extending in the Y direction and each connected to each of the plurality of power supply wirings (L1), and a plurality of switch cells (SW) provided at intersections of the plurality of strap power supply wirings (30) and the plurality of power supply wirings (L1). The plurality of standard cell rows (10) have standard cell rows (10b) in which the switch cells (SW) are not arranged at positions corresponding to one or more standard cell columns other than the standard cell columns (21) and (22) at both ends of the plurality of standard cell columns (20).

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to semiconductor integrated circuit devices.

[0002] In order to achieve low power consumption in semiconductor integrated circuit devices, it is being considered to arrange a switch for switching between supplying and cutting off power in each standard cell row, and to cut off the power supply to standard cell rows that do not require power supply. Power is supplied to each standard cell from the strap power supply wiring via the switch and the standard cell power supply wiring.

[0003] However, placing switches on each standard cell power supply wiring poses a problem of increasing the area of ​​the circuit block including each standard cell row. To address this problem, Patent Document 1 discloses a semiconductor integrated circuit device that can reduce the number of switches to be placed.

[0004] International Publication No. 2017 / 208887

[0005] However, since various wirings are provided in a semiconductor integrated circuit device, it is desirable to improve the wiring efficiency, but Patent Document 1 does not disclose how to improve the wiring efficiency.

[0006] Therefore, the present disclosure provides a semiconductor integrated circuit device that can improve wiring efficiency while realizing low power consumption.

[0007] a plurality of strap power supply lines extending in a second direction perpendicular to the first direction in a layer above the plurality of power supply lines; a plurality of sub-strap power supply lines extending in the second direction in a layer above the plurality of power supply lines, each sub-strap power supply line being connected to one of the plurality of power supply lines; and a plurality of first switch cells provided at intersections of the plurality of strap power supply lines and the plurality of power supply lines, the first switch cells being configured to be able to switch, in response to a control signal, whether to electrically connect the strap power supply lines to the power supply lines;

[0008] According to one aspect of the present disclosure, it is possible to realize a semiconductor integrated circuit device that can improve wiring efficiency while realizing low power consumption.

[0009] FIG. 1 is a plan view showing the configuration of a semiconductor integrated circuit device according to an embodiment. FIG. 2 is a cross-sectional view showing the semiconductor integrated circuit device cut along line II-II shown in FIG. 1. FIG. 3 is a first plan view for explaining the layout of switch cells in the semiconductor integrated circuit device according to the embodiment. FIG. 4 is a second plan view for explaining the layout of switch cells in the semiconductor integrated circuit device according to the embodiment. FIG. 5 is a plan view showing the configuration of a semiconductor integrated circuit device according to a first modification of the embodiment. FIG. 6 is a plan view showing the configuration of a semiconductor integrated circuit device according to a second modification of the embodiment. FIG. 7 is a plan view showing the configuration of a semiconductor integrated circuit device according to a third modification of the embodiment.

[0010] Hereinafter, embodiments and the like will be specifically described with reference to the drawings.

[0011] The embodiments and the like described below are all comprehensive or specific examples. The numerical values, components, arrangement positions and connection forms of the components, etc. shown in the following embodiments and the like are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments and the like, components that are not recited in independent claims are described as optional components.

[0012] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0013] Furthermore, in this specification, terms indicating the relationship between elements, such as orthogonal, terms indicating the shape of elements, such as zigzag, as well as numerical values ​​and numerical ranges, are not expressions that express only the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about several percent (or about 10%).

[0014] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0015] (Embodiment) [1. Configuration of Semiconductor Integrated Circuit Device] A semiconductor integrated circuit device according to this embodiment will be described below with reference to FIGS. 1 to 4. FIG. 1 is a plan view showing the configuration of a semiconductor integrated circuit device 1 according to this embodiment. FIG. 1 shows a simplified layout pattern in a circuit block that performs power cutoff. Note that in each figure, switch cells SW and the like are shown with hatching for convenience, but this is not intended to show cross sections of the switch cells SW and the like. Also, in FIG. 1, the region in which standard cells 11 are arranged is shown with the reference numeral of the standard cells 11.

[0016] 1, the semiconductor integrated circuit device 1 includes a plurality of standard cell rows 10, a plurality of strap power supply lines 30, a plurality of sub-strap power supply lines 40, and a plurality of switch cells SW. Each component of the semiconductor integrated circuit device 1 is disposed on, for example, a substrate (not shown).

[0017] Each of the plurality of standard cell rows 10 includes a plurality of standard cells 11 arranged in an X direction (first direction), and a plurality of power supply wirings L1 and a plurality of ground power supply wirings L2 extending in the X direction (i.e., the direction in which the standard cells 11 are arranged). Furthermore, a plurality of standard cell rows 10 are arranged in a Y direction perpendicular to the X direction to form a plurality of standard cell columns 20.

[0018] The standard cells 11 are basic circuit elements having functions such as inverters and logic circuits, and a semiconductor integrated circuit device that achieves a predetermined function can be fabricated by combining and wiring the standard cells 11. The standard cells 11 each have, for example, an N-type region in which a P-type MOS (Metal Oxide Semiconductor) transistor (PMOS) is formed and a P-type region in which an N-type MOS transistor (NMOS) is formed. Furthermore, the standard cells 11 may have, for example, an N-type region and a P-type region arranged side by side in the Y direction. The internal structure of the standard cells 11 is not shown in the drawing.

[0019] The power supply wiring L1 and the ground power supply wiring L2 are alternately arranged between the standard cell rows 10. The power supply wiring L1 is connected to each of the plurality of standard cells 11 arranged in the standard cell row 10, and is a wiring that supplies power (power supply potential (VDD)) to each of the plurality of standard cells 11. The ground power supply wiring L2 is connected to each of the plurality of standard cells 11 arranged in the standard cell row 10, and is a wiring that supplies a ground potential (VSS) to each of the plurality of standard cells 11.

[0020] In this embodiment, the plurality of standard cell rows 10 include standard cell rows 10a1 and 10a2 (second standard cell rows) in which switch cells SW are arranged, and a standard cell row 10b in which no switch cells SW are arranged (the "row in which no SW is arranged" in FIG. 1, the first standard cell row). Note that it is sufficient that at least one standard cell row 10b is arranged.

[0021] One standard cell row 10 is formed by arranging two standard cells 11 vertically (Y direction) and then arranging them horizontally (X direction). For example, standard cell row 10b is formed by the area enclosed by the dashed line.

[0022] The strap power supply wiring 30 is provided so as to extend in the Y direction. The strap power supply wiring 30 may be provided, for example, in a layer above the standard cell row 20 and the power supply wiring L1. The strap power supply wiring 30 is also connected to the input terminals (not shown) of the switch cells SW arranged below it through a via structure (see FIG. 2). The strap power supply wiring 30 is also provided so as to overlap (electrically connect to) each of the switch cells SW arranged in the standard cell row 20 in a plan view.

[0023] The sub-strap power supply wiring 40 is provided so as to extend in the Y direction. The sub-strap power supply wiring 40 may be provided, for example, in a layer above the standard cell row 20 and the power supply wiring L1. The sub-strap power supply wiring 40 is connected to the power supply wiring L1 passing thereunder through a via structure (not shown). The sub-strap power supply wiring 40 is also provided at a position not overlapping the switch cells SW in plan view. For example, the sub-strap power supply wiring 40 and the strap power supply wiring 30 are arranged alternately along the X direction.

[0024] The sub-strap power supply wiring 40 is connected to the power supply wiring L1 provided in each of the standard cell rows 10a1, 10a2, and 10b. That is, the sub-strap power supply wiring 40 connects the power supply wiring L1 of the standard cell row in which the switch cell SW is arranged to the power supply wiring L1 of the standard cell row in which the switch cell SW is not arranged. For example, each of the multiple sub-strap power supply wirings 40 is connected to each of the multiple power supply wirings L1.

[0025] The sub-strap power supply wiring 40 and the strap power supply wiring 30 are not electrically connected.

[0026] The switch cell SW controls whether to cut off the power supply to the standard cell 11. The switch cell SW is provided at the intersection of the strap power line 30 and the power line L1 in a plan view, and is configured to be able to switch whether to electrically connect the strap power line 30 to the power line L1 in response to a control signal. That is, the switch cell SW switches between conduction and non-conduction between the strap power line 30 and the power line L1. For example, the switch cell SW is provided between one of the multiple strap power lines 30 and a wiring group consisting of N power lines L1 (N is an integer greater than or equal to 1), and is configured to be able to switch whether to electrically connect the strap power line 30 to the power line L1 belonging to the wiring group in response to a control signal. The control signal is input, for example, from a control device that controls power cutoff.

[0027] The switch cell SW has an input terminal to which the strap power supply wiring 30 is connected and a terminal for receiving a control signal for switching between conduction and non-conduction. The switch cell SW is a semiconductor switch having a source connected to the input terminal (i.e., the strap power supply wiring 30), a drain connected to the power supply wiring L1, and a gate connected to a terminal for receiving the control signal. The conduction and non-conduction between the strap power supply wiring 30 and the power supply wiring L1 are switched depending on whether the control signal is High or Low.

[0028] It should be noted that the switch cells SW are not arranged at all of the intersections between the strap power supply lines 30 and the power supply lines L1. The switch cells SW are an example of first switch cells.

[0029] In the semiconductor integrated circuit device 1 as described above, power is supplied to the standard cell row 10b via any one of the plurality of sub-strap power supply wirings 40. For example, when power is to be supplied to the standard cells 11 in the standard cell row 10b, the switch cell SW in a standard cell row (e.g., standard cell row 10a1 or 10a2) located close to (e.g., adjacent to) the standard cell row 10b is turned on, and power is supplied to the power supply wiring L1 of the standard cell row.

[0030] Since power supply line L1 is connected to sub-strap power supply line 40 via a via structure, the power supply is also provided to sub-strap power supply line 40. In other words, power is supplied along sub-strap power supply line 40. Since sub-strap power supply line 40 is also connected to power supply line L1 of standard cell row 10b via a via structure, power is supplied from power supply line L1 of the standard cell row in which switch cell SW is arranged to power supply line L1 of standard cell row 10b via sub-strap power supply line 40.

[0031] In this manner, power is supplied to the standard cells 11 in the standard cell row 10b in which no switch cell SW is arranged via the strap power supply wiring 30, the switch cell SW, the power supply wiring L1 of the standard cell row in which the switch cell SW is arranged, and the sub-strap power supply wiring 40. In this embodiment, power is supplied to the standard cell row 10b only via the sub-strap power supply wiring 40.

[0032] Next, the cross-sectional structure (layer structure) of the semiconductor integrated circuit device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view showing the semiconductor integrated circuit device 1 taken along line II-II shown in Fig. 1. Fig. 2 shows the cross-sectional structure at a location where the switch cell SW is arranged.

[0033] As shown in FIG. 2, the semiconductor integrated circuit device 1 has switch cells SW and five or more wiring layers on a substrate. For example, first to fifth wiring layers (Metal 1 to 5) are formed so as to be stacked in order from the substrate side. Each of the first to fifth wiring layers is electrically connected through vias (Via 1 to 4). The first wiring layer is a wiring layer for power supplies. For example, the power supply wiring L1 and the ground power supply wiring L2 are formed in the first wiring layer (Metal 1). The wiring of the first wiring layer (for example, the power supply wiring L1) is also connected to the switch cells SW.

[0034] The second and fourth wiring layers (Metal 2 and 4) are wiring layers for signal wiring arranged in the X direction. The preferred wiring direction of the second and fourth wiring layers is the X direction. The third and fifth wiring layers (Metal 3 and 5) are wiring layers for wiring arranged in the Y direction. The preferred wiring direction of the third and fifth wiring layers is the Y direction. The strap power supply wiring 30 and the sub-strap power supply wiring 40 are formed in either the third or fifth wiring layer. For example, the sub-strap power supply wiring 40 may be arranged in a layer lower than the strap power supply wiring 30.

[0035] Furthermore, in the cross-sectional structure of a position on the strap power supply wiring 30 where no switch cells SW are provided, for example, a wiring layer for the strap power supply wiring 30 (e.g., Metal 3 or 5) is formed, but no other wiring layers are formed. In other words, by reducing the number of switch cells SW provided, it is no longer necessary to form some of the first to fifth wiring layers (e.g., wiring layers 2 to 4) shown in Figure 2, and other wiring can be passed linearly through those portions. In other words, the semiconductor integrated circuit device 1 improves wiring efficiency.

[0036] Next, the layout position of the switch cells SW will be described with reference to FIGS. 3 and 4. First, an example in which the layout of the switch cells SW is repeated in the X direction will be described with reference to FIG. 3. FIG. 3 is a first plan view for explaining the layout of the switch cells SW in the semiconductor integrated circuit device 1 according to this embodiment. Note that FIG. 3 is a diagram for explaining that the layout positions of the switch cells SW are repeated in the same pattern in the X direction, and for convenience, some of the configuration shown in FIG. 1 is omitted. Also, for convenience, FIG. 3 illustrates a case in which the number of standard cell rows 10 and standard cell columns 20 is different from that shown in FIG. 1.

[0037] As shown in FIG. 3 , no switch cells SW are arranged in the standard cell row 10b. In the standard cell row 10b, no switch cells SW are arranged in positions corresponding to one or more standard cell columns 20 other than the standard cell columns 21 and 22 at both ends of the multiple standard cell columns 20, and in positions corresponding to the standard cell columns 21 and 22 at both ends. The standard cell row 10b has multiple standard cells 11 (power supply targets) but no switch cells SW (power supply source). For example, the standard cell row 10b is arranged between the standard cell rows 10a1 and 10a2, but this is not limiting. For example, the standard cell row 10b may or may not be arranged contiguously in the Y direction.

[0038] It is not essential that switch cells SW are not arranged at positions corresponding to the standard cell rows 21 and 22 at both ends. A configuration in which switch cells SW are arranged at positions corresponding to the standard cell rows 21 and 22 will be described later with reference to FIGS.

[0039] In this embodiment, the standard cell rows 10b are arranged every three rows. In this manner, the standard cell rows 10b may be arranged at equal intervals every predetermined number of rows. However, the standard cell rows 10b are not limited to being arranged at equal intervals, and may be arranged randomly.

[0040] In this embodiment, the plurality of strap power lines 30 include a strap power line 31 (first strap power line) and a strap power line 32 (second strap power line) that are adjacent to each other and have switch cells SW arranged at different positions in the Y direction. For example, in a plan view, the switch cells SW on the strap power lines 31 and 32 are arranged in a zigzag pattern. In this way, the switch cells SW may be arranged at different positions in the Y direction on adjacent strap power lines 30. For example, in this embodiment, no switch cells SW are arranged on both adjacent strap power lines 30 in one standard cell row 10.

[0041] Furthermore, in this embodiment, the arrangement positions in the X direction of the multiple switch cells SW are the same for every two strap power supply wires 30 (repeated unit R1 in FIG. 3). That is, the arrangement positions of the switch cells SW are repeated in the same arrangement pattern for every two strap power supply wires 30. In the example of FIG. 3, the strap power supply wires 31 and 32 are arranged alternately.

[0042] Note that the arrangement is not limited to being the same for every two lines, and may be the same for every three lines, etc. For example, the arrangement positions of the multiple switch cells SW in the X direction may be the same for every M (M is a natural number equal to or greater than 2) of the multiple strap power supply lines 30.

[0043] At least one standard cell row 10b is included in the repeat unit R1. In the example of Fig. 3, there is a standard cell row 10 in the repeat unit R1 in which the switch cell SW is not arranged. The standard cell row 10 in which the switch cell SW is not arranged is repeatedly arranged in the X direction in the repeat unit, thereby forming the standard cell row 10b.

[0044] Next, an example in which the arrangement of switch cells SW is repeated in the Y direction will be described with reference to Fig. 4. Fig. 4 is a second plan view for explaining the arrangement of switch cells SW in the semiconductor integrated circuit device 1 according to this embodiment. The configuration of the semiconductor integrated circuit device 1 shown in Fig. 4 is the same as that shown in Fig. 3.

[0045] 4, in this embodiment, the multiple standard cell rows 10 include a standard cell row 10a2 (fifth standard cell row) and a standard cell row 10a1 (fourth standard cell row) that are adjacent to each other and each include one or more switch cells SW among the multiple switch cells SW. The positions of the one or more switch cells SW arranged in the standard cell rows 10a1 and 10a2 in the X direction are different from each other. For example, in a plan view, the switch cells SW arranged in the standard cell rows 10a1 and 10a2 are arranged in a zigzag pattern. In this way, the positions of the switch cells SW in the X direction may be different from each other in adjacent standard cell rows 10.

[0046] Furthermore, in this embodiment, the layout positions of the switch cells SW in the Y direction are the same for every three standard cell rows 10 (repeated unit R2 in FIG. 4 ). That is, the same layout pattern of the switch cells SW is repeated for every three standard cell rows 10.

[0047] Note that the arrangement is not limited to being the same for every three cells, but may be the same for every two cells, every four cells, etc. For example, the arrangement positions of the multiple switch cells SW in the X direction may be the same for every N (N is a natural number equal to or greater than 2) standard cell rows 10 out of the multiple standard cell rows 10. Note that the N standard cell rows 10 (i.e., repeat unit R2) include a standard cell row 10b. In other words, the standard cell row 10b is arranged every predetermined number of rows.

[0048] In this embodiment, an example in which the placement positions of the switch cells SW are repeated in both the X direction and the Y direction has been described using FIGS. 3 and 4, but it is sufficient that the placement positions of the switch cells SW are repeated in at least one of the X direction and the Y direction.

[0049] [2. Effects, etc.] As described above, the semiconductor integrated circuit device 1 according to this embodiment includes: a plurality of standard cells 11 arranged side by side in the X direction (first direction); a plurality of standard cell rows 10 each having a plurality of power supply wires L1 that extend in the X direction and supply power to the plurality of standard cells 11; a plurality of strap power supply wires 30 that extend in the Y direction (second direction) orthogonal to the X direction in a layer above the plurality of power supply wires L1; a plurality of sub-strap power supply wires 40 that extend in the Y direction in a layer above the plurality of power supply wires L1 and are each connected to a respective one of the plurality of power supply wires L1; and a plurality of switch cells SW (first switch cells) that are provided at intersections of the plurality of strap power supply wires 30 and the plurality of power supply wires L1 and are configured to be able to switch whether or not to electrically connect the strap power supply wire 30 to the power supply wire L1 in response to a control signal. A plurality of standard cell rows 10 are arranged in the Y direction to form a plurality of standard cell columns 20, and the plurality of standard cell rows 10 include a standard cell row 10b (first standard cell row) in which a plurality of switch cells SW are not arranged at a position corresponding to one or more standard cell columns 23 other than the standard cell columns 21 and 22 at both ends of the plurality of standard cell columns 20.

[0050] As a result, the semiconductor integrated circuit device 1 is provided with a switch cell SW that can switch the connection between the strap power supply wiring 30 and the power supply wiring L1, i.e., a configuration that cuts off the power supply, thereby achieving low power consumption. Also, in the standard cell row 10b where no switch cell SW is arranged, a via structure for connecting the strap power supply wiring 30 and the power supply wiring L1 is not required, making it easier to form other wiring. Therefore, the semiconductor integrated circuit device 1 can improve wiring efficiency while achieving low power consumption.

[0051] Furthermore, in the standard cell row 10b, a plurality of switch cells SW are not arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the standard cell row 10b.

[0052] This allows the number of switch cells SW to be further reduced, that is, the number of via structures to be reduced, thereby further improving the ease of wiring.

[0053] Furthermore, power is supplied to standard cell row 10b via one of the plurality of sub-strap power supply wirings 40. For example, the plurality of standard cell rows 10 may include standard cell row 10a1 or 10a2 (second standard cell row) in which one or more switch cells SW are arranged at positions in standard cell row 10a1 or 10a2 corresponding to one or more other standard cell columns 23 of the plurality of standard cell columns 20. Each of the plurality of sub-strap power supply wirings 40 is connected to power supply wiring L1 arranged in standard cell row 10b and standard cell row 10a1 or 10a2, respectively.

[0054] This allows power to be supplied to standard cell rows 10 in which no switch cells SW are arranged via the sub-strap power supply wiring 40. In other words, it is possible to achieve low power consumption and improved wiring efficiency while enabling the standard cells 11 in standard cell rows 10 in which no switch cells SW are arranged to operate.

[0055] Furthermore, the plurality of strap power supply wirings 30 include adjacent strap power supply wirings 31 (first strap power supply wiring) and strap power supply wirings 32 (second strap power supply wiring), and the positions in the Y direction of the plurality of switch cells SW may be different between the strap power supply wirings 31 and 32. For example, the positions in the X direction of the plurality of switch cells SW may be the same for every M (M is a natural number equal to or greater than 2) of the plurality of strap power supply wirings 30.

[0056] The multiple standard cell rows 10 also include adjacent standard cell rows 10a1 (fourth standard cell row) and standard cell row 10a2 (fifth standard cell row), each of which includes one or more switch cells SW among the multiple switch cells SW. The positions in the X direction of the one or more switch cells SW in each of standard cell rows 10a1 and 10a2 may be different from each other. For example, the positions in the Y direction of the multiple switch cells SW may be the same for each of N standard cell rows (N is a natural number equal to or greater than 2) including standard cell row 10b among the multiple standard cell rows 10.

[0057] In this way, the layout of the switch cells SW can be set arbitrarily, which increases the degree of freedom in the layout of the switch cells SW.

[0058] (First Variation of the Embodiment) A semiconductor integrated circuit device according to this variation will be described below with reference to FIG. 5. FIG. 5 is a plan view showing the configuration of a semiconductor integrated circuit device 1a according to this variation. Note that the following description will focus on differences from the embodiment, and descriptions of content that is the same as or similar to the embodiment will be omitted or simplified. The semiconductor integrated circuit device 1a according to this variation differs from the semiconductor integrated circuit device 1 according to the embodiment in that the layout positions of the switch cells are repeated in different patterns in the Y direction. Note that the following description will be given of an example in which three standard cell rows 10 are considered to be one repeating unit, and the layout of the standard cell rows 10 in the Y direction differs between adjacent repeating units.

[0059] As shown in FIG. 5, the semiconductor integrated circuit device 1a has a configuration in which three standard cell rows 10 form one repeating unit (repeating units R11, R12, and R13), and the repeating units R11, R12, and R13 are arranged in the Y direction.

[0060] Each of the repeating units R11, R12, and R13 is formed by a plurality of standard cell rows 10. For example, the number of standard cell rows 10 included in each of the repeating units R11, R12, and R13 is equal to or different from each other.

[0061] 5, each of the repeating units R11, R12, and R13 is formed to include one standard cell row 10a1, one standard cell row 10a2, and one standard cell row 10b, and the arrangement of the standard cell rows 10a1, 10a2, and 10b in the Y direction is different. Each of the repeating units R11, R12, and R13 includes at least one standard cell row 10b.

[0062] The arrangement of the repeating units R11, R12, and R13 is not particularly limited, and may be set so that identical repeating units are not consecutively arranged in the Y direction. For example, the arrangement of the repeating units R11, R12, and R13 may be set randomly so that identical repeating units are not consecutively arranged in the Y direction. In the above example, the number of standard cell rows 10 included in each of the repeating units R11, R12, and R13 and the positions of the switch cells SW in the standard cell rows 10 are the same, but they may be different. Furthermore, the standard cell row 10 included in at least one of the repeating units R11, R12, and R13 may have switch cells SW arranged in positions corresponding to the standard cell columns 21 and 22 at both ends, for example.

[0063] (Variation 2 of the Embodiment) A semiconductor integrated circuit device according to this variation will be described below with reference to FIG. 6. FIG. 6 is a plan view showing the configuration of a semiconductor integrated circuit device 1b according to this variation. Note that the following description will focus on differences from the embodiment, and descriptions of content that is the same as or similar to the embodiment will be omitted or simplified. The semiconductor integrated circuit device 1b according to this variation differs from the semiconductor integrated circuit device 1 according to the embodiment in that switch cells SW1 are arranged in all of the standard cell columns 21 and 22 at both ends. Note that the hatching style of the switch cells SW1 arranged in the standard cell columns 21 and 22 at both ends is changed from the switch cells SW arranged in the embodiment. Also, in FIG. 6 and subsequent figures, the notation "rows in which no SW is arranged" is omitted.

[0064] 6, the semiconductor integrated circuit device 1b includes, in addition to the semiconductor integrated circuit device 1 shown in Figures 3 and 4, a switch cell SW1 and a strap power supply wiring 33 in the standard cell columns 21 and 22. The switch cell SW1 is placed in the standard cell columns 21 and 22 regardless of whether the switch cell SW is placed in a position corresponding to the standard cell column 23 other than the standard cell columns 21 and 22.

[0065] In this way, in the standard cell rows 10b1 (first standard cell row), 10a3, and 10a4 (second standard cell rows), switch cells SW1 are further arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the multiple standard cell columns 20 in the standard cell rows 10b1, 10a3, and 10a4. It can also be said that the switch cells SW1 are arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the standard cell row 10b1. The switch cells SW1 have the same configuration as the switch cells SW. The switch cells SW1 are also an example of a second switch cell.

[0066] The switch cell SW1 is not limited to being arranged in both the standard cell columns 21 and 22, and may be arranged in only one of them. The switch cell SW1 is not limited to being arranged in each standard cell column 20, and may be arranged only in the standard cell row 10b1. For example, the switch cell SW1 may be arranged in the standard cell row 10b1 at a position corresponding to at least one of the standard cell columns 21 and 22 at both ends of the multiple standard cell columns 20. The switch cell SW1 may also be arranged every predetermined number of rows in the standard cell columns 21 and 22. It is sufficient for the semiconductor integrated circuit device 1b to have at least one switch cell SW1 somewhere in the standard cell columns 21 and 22.

[0067] The strap power supply wiring 33 is provided in the standard cell columns 21 and 22 so as to extend in the Y direction. The strap power supply wiring 33 may be provided, for example, in an upper layer of the standard cell columns 21 and 22 and the power supply wiring L1. The strap power supply wiring 33 is connected to the input terminal (not shown) of the switch cell SW1 arranged below it through a via structure (see FIG. 2). The strap power supply wiring 33 is also provided so as to overlap (electrically connect to) each of the switch cells SW1 arranged in the standard cell columns 21 and 22 in a plan view.

[0068] As described above, the semiconductor integrated circuit device 1b according to this embodiment further includes the switch cell SW1 (second switch cell) arranged at a position corresponding to at least one of the standard cell columns 21 and 22 at both ends of the standard cell row 10b1 (first standard cell row). For example, the switch cell SW1 may be arranged at a position corresponding to each of the standard cell columns 21 and 22 at both ends of the standard cell row 10b1.

[0069] This allows the switch cell SW1 to be placed at a position corresponding to the standard cell rows 21 and 22 where the power supply is weakened, thereby preventing the power supply from being weakened in the semiconductor integrated circuit device 1b.

[0070] (Variation 3 of the Embodiment) A semiconductor integrated circuit device according to this variation will be described below with reference to FIG. 7 . FIG. 7 is a plan view showing the configuration of a semiconductor integrated circuit device 1c according to this variation. The following description will focus on differences from the embodiment, and descriptions of content that is the same as or similar to the embodiment will be omitted or simplified. The semiconductor integrated circuit device 1c according to this variation differs from the semiconductor integrated circuit device 1 according to the embodiment in that it further includes standard cell rows in which switch cells are arranged in positions corresponding to standard cell rows other than the standard cell rows at both ends. Furthermore, the hatching style of switch cell SW2, which is added to switch cell SW included in the semiconductor integrated circuit device 1 of the embodiment, is changed from that of switch cells SW and SW3. Switch cell SW3 corresponds to switch cell SW1 in Variation 2 of the embodiment.

[0071] As shown in FIG. 7, the standard cell row 10 of the semiconductor integrated circuit device 1c includes standard cell rows 10c1, 10c2, and 10c3 (third standard cell row), and each of the standard cell rows 10c1, 10c2, and 10c3 has a switch cell SW2 arranged at a position corresponding to one or more standard cell columns 23 other than the standard cell columns 21 and 22 at both ends of the multiple standard cell columns 20.

[0072] One or more switch cells SW2 are arranged in each of the standard cell rows 10c1, 10c2, and 10c3. In each of the standard cell rows 10c1, 10c2, and 10c3, switch cells SW are not arranged in positions corresponding to the standard cell columns 21 and 22 at both ends of the multiple standard cell columns 20 in the standard cell rows 10c1, 10c2, and 10c3, and switch cells SW2 are arranged in positions corresponding to one or more other standard cell columns 23, which are different from those in the standard cell rows 10a1 and 10a2.

[0073] The standard cell rows 10c1 and 10c2 each have one switch cell SW2 at a position corresponding to one or more other standard cell columns 23.

[0074] The standard cell row 10c3 has two switch cells SW2 at positions corresponding to one or more other standard cell columns 23.

[0075] The switch cell SW2 may be arranged at a random position in the standard cell rows 10c1, 10c2, and 10c3, for example. The switch cell SW2 may also be arranged next to the switch cell SW in the Y direction, for example. The number of switch cells SW2 arranged in the standard cell rows 10c1, 10c2, and 10c3 may be less than the number of switch cells SW arranged in the standard cell row 10a3 or 10a4. The switch cell SW2 is an example of one or more other switch cells among the multiple switch cells SW.

[0076] The semiconductor integrated circuit device 1c may include at least one of the standard cell rows 10c1, 10c2, and 10c3. For example, the standard cell row 10c may not include a switch cell SW3 at positions corresponding to the standard cell columns 21 and 22 at both ends of the multiple standard cell columns 20 in the standard cell row 10c, and may include one or more switch cells SW2 at positions corresponding to one or more other standard cell columns 23 that are different from the positions in the standard cell rows 10a1 and 10a2 (for example, random positions).

[0077] Furthermore, the semiconductor integrated circuit device 1c may include standard cell rows 10a5, 10a6, and 10b2, and a strap power supply wiring 33. The standard cell rows 10a5, 10a6, and 10b2 do not include the switch cell SW2.

[0078] In standard cell row 10a5, SW3 is arranged at a position corresponding to standard cell column 21 in standard cell row 10a1.

[0079] In the standard cell row 10a6, a switch SW3 is arranged at a position corresponding to the standard cell column 21 in the standard cell row 10a2.

[0080] In the standard cell row 10b2, a switch SW3 is arranged at a position corresponding to the standard cell column 21 in the standard cell row 10b1.

[0081] The switch cells SW2 and SW3 control whether or not to cut off the power supply to the standard cell 11. The switch cells SW2 and SW3 are provided at the intersection of the strap power line 30 and the power line L1 in a plan view, and are configured to be able to switch whether or not to electrically connect the strap power line 30 to the power line L1 in response to a control signal. That is, the switch cells SW2 and SW3 switch between conduction and non-conduction between the strap power line 30 and the power line L1. The switch cells SW2 and SW3 have the same configuration as the switch cell SW. The switch cell SW3 may be arranged in at least one of the standard cell rows 10c1, 10c2, and 10c3, for example.

[0082] The strap power supply wiring 33 is provided in the standard cell row 21 so as to extend in the Y direction. For example, of the standard cell rows 21 and 22 at both ends, the strap power supply wiring 33 is provided only in the standard cell row 21 in which the switch cell SW3 is arranged.

[0083] As described above, the plurality of standard cell rows 10 included in the semiconductor integrated circuit device 1c according to this embodiment further includes a standard cell row 10c1, 10c2 or 10c3 (third standard cell row) in which no switch cell SW3 is arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the plurality of standard cell columns 20 in the standard cell row 10c1, 10c2 or 10c3, and in which one or more other switch cells SW2 among the plurality of switch cells SW are arranged at positions corresponding to one or more other standard cell columns 23, different from the standard cell row 10a1 or 10a2 (second standard cell row).

[0084] This increases the degree of freedom in arranging the switch cells SW2.

[0085] (Other Embodiments) As above, semiconductor integrated circuit devices according to one or more aspects have been described based on embodiments, etc. However, the present disclosure is not limited to these embodiments, etc. As long as they do not deviate from the spirit of the present disclosure, various modifications that a person skilled in the art can conceive of to the present embodiments, and forms constructed by combining components in different embodiments may also be included in the present disclosure.

[0086] For example, in the above-described embodiments, the layout positions of the switch cells in the second direction are different between adjacent strap power supply lines (e.g., the first and second strap power supply lines), but this is not limiting, and for example, some or all of the switch cells may be the same between adjacent strap power supply lines.Furthermore, while the above-described embodiments, etc., the layout positions of the switch cells in the first direction are different between adjacent standard cell rows (e.g., the fourth and fifth standard cell rows), this is not limiting, and for example, some or all of the switch cells may be the same between adjacent standard cell rows.

[0087] Furthermore, the power cutoff method using the switch cells according to the above-described embodiments may be a method of cutting off the power supply potential (VDD) or a method of cutting off the ground potential (VSS).

[0088] The present disclosure is useful for a semiconductor integrated circuit device using a power cutoff technique.

[0089] 1, 1a, 1b, 1c Semiconductor integrated circuit device 10, 10a5, 10a6 Standard cell row 10a1 Standard cell row (second standard cell row, fourth standard cell row) 10a2 Standard cell row (second standard cell row, fifth standard cell row) 10a3, 10a4 Standard cell row (second standard cell row) 10b, 10b1, 10b2 Standard cell row (first standard cell row) 10c1, 10c2, 10c3 Standard cell row (third standard cell row) 11 Standard cell 20, 21, 22, 23 Standard cell column 30 Strap power supply wiring 31 Strap power supply wiring (first strap power supply wiring) 32 Strap power supply wiring (second strap power supply wiring) 33 Strap power supply wiring 40 Sub-strap power supply wiring L1 Power supply wiring L2 Ground power supply wiring R1, R2, R11, R12, R13 Repeat unit SW Switch cell (first switch cell) SW1, SW3 Switch cell (second switch cell) SW2 Switch cell

Claims

1. a plurality of standard cell rows, each of which has a plurality of standard cells arranged in a first direction and a plurality of power supply lines extending in the first direction and supplying power to the plurality of standard cells; a plurality of strap power supply wirings extending in a second direction perpendicular to the first direction in an upper layer of the plurality of power supply wirings; a plurality of sub-strap power supply wirings extending in the second direction in an upper layer of the plurality of power supply wirings, each of the sub-strap power supply wirings being connected to each of the plurality of power supply wirings; a plurality of first switch cells provided at intersections of the plurality of strap power supply wirings and the plurality of power supply wirings, the first switch cells being configured to be able to switch whether or not the strap power supply wirings and the power supply wirings are electrically connected in response to a control signal; the plurality of standard cell rows are arranged side by side in the second direction to form a plurality of standard cell columns; The plurality of standard cell rows include a first standard cell row in which the plurality of first switch cells are not arranged at positions corresponding to one or more standard cell columns other than the standard cell columns at both ends of the plurality of standard cell columns in the first standard cell row. Semiconductor integrated circuit device.

2. In the first standard cell row, the first switch cells are not arranged at positions corresponding to the standard cell columns at both ends of the first standard cell row.

2. The semiconductor integrated circuit device according to claim 1.

3. a second switch cell arranged at a position corresponding to at least one of the standard cell columns at both ends in the first standard cell row; 2. The semiconductor integrated circuit device according to claim 1.

4. The second switch cells are arranged at positions corresponding to the standard cell columns at both ends of the first standard cell row.

4. The semiconductor integrated circuit device according to claim 3.

5. Power is supplied to the first standard cell row via any one of the plurality of sub-strap power supply lines.

5. The semiconductor integrated circuit device according to claim 1.

6. the plurality of standard cell rows include a second standard cell row in which one or more first switch cells among the plurality of first switch cells are arranged at positions in the second standard cell row corresponding to the other one or more standard cell columns among the plurality of standard cell columns; Each of the sub-strap power supply lines is connected to a power supply line arranged in each of the first and second standard cell rows.

5. The semiconductor integrated circuit device according to claim 1.

7. the plurality of strap power supply wires include a first strap power supply wire and a second strap power supply wire adjacent to each other; The positions of the first switch cells in the second direction are different from each other in the first strap power supply wiring and the second strap power supply wiring.

5. The semiconductor integrated circuit device according to claim 1.

8. The positions of the first switch cells in the first direction are the same for each of M strap power supply wirings (M is a natural number equal to or greater than 2) among the plurality of strap power supply wirings.

5. The semiconductor integrated circuit device according to claim 1.

9. The plurality of standard cell rows further includes a third standard cell row in which no switch cells are arranged at positions corresponding to the two end standard cell columns among the plurality of standard cell columns in the third standard cell row, and one or more other first switch cells among the plurality of first switch cells are arranged at positions corresponding to the one or more other standard cell columns and different from the second standard cell row.

7. A semiconductor integrated circuit device according to claim 6.

10. the plurality of standard cell rows include a fourth standard cell row and a fifth standard cell row which are adjacent to each other and in which one or more first switch cells of the plurality of first switch cells are arranged, The positions of the one or more first switch cells in the fourth standard cell row and the fifth standard cell row in the first direction are different from each other.

5. The semiconductor integrated circuit device according to claim 1.

11. The positions of the first switch cells in the second direction are the same for each of N standard cell rows (N is a natural number equal to or greater than 2) including the first standard cell row among the plurality of standard cell rows.

5. The semiconductor integrated circuit device according to claim 1.