Nitride semiconductor device

Abstract

This nitride semiconductor device (10) comprises: a hexagonal SiC substrate (22) having a main surface (22A) inclined at an off angle of 2-6° in a specific crystal direction with respect to the c-plane; a nitride semiconductor layer (24) disposed on the main surface (22A) of the SiC substrate (22); and a gate electrode (20), a source electrode (38), and a drain electrode (40) disposed on the nitride semiconductor layer (24). The nitride semiconductor layer (24) includes an electron transport layer (30) and an electron injection layer (32) which is disposed on the electron transport layer (30) and has a band gap larger than that of the electron transport layer (30). The gate electrode (20) extends in a second direction and is disposed between the source electrode (38) and the drain electrode (40) which are isolated in a first direction. The first direction intersects a third direction, which matches the specific crystal direction in plan view, at an angle within the range of 90°±15°.

Description

nitride semiconductor devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] High electron mobility transistors (HEMTs) have been widely used as high-speed switching devices and high-frequency amplification devices. In particular, HEMTs using nitride semiconductors with a relatively large bandgap can achieve high-speed operation and high breakdown voltage. For example, Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a buffer layer located on the semiconductor substrate, an electron transit layer located on the buffer layer, and an electron supply layer located on the electron transit layer. The electron transit layer and the electron supply layer are made of nitride semiconductors with different bandgaps (Al compositions). The heterojunction between the electron transit layer and the electron supply layer generates a two-dimensional electron gas (2DEG) that can be used as a channel for the HEMT in the electron transit layer near the interface between the electron transit layer and the electron supply layer.

[0003] Japanese Patent Application Laid-Open No. 2020-077865

[0004] In nitride semiconductor HEMTs for high-frequency amplification devices, silicon carbide (SiC) substrates are often used to ensure heat dissipation. Because SiC substrates are generally expensive, the manufacturing cost of HEMTs using SiC substrates can be relatively high. However, among SiC substrates, off-axis SiC substrates, which are being developed for power device applications, are available at relatively low cost.

[0005] When a nitride semiconductor layer is epitaxially grown on a SiC substrate with an off-axis angle, the nitride semiconductor layer also grows while inheriting the off-axis angle of the SiC substrate. Therefore, in a HEMT using a SiC substrate with an off-axis angle, electron mobility may be reduced due to electron scattering near the interface between the electron transit layer and the electron supply layer compared to a case where a SiC substrate without an off-axis angle is used. Such a reduction in electron mobility may degrade the frequency characteristics of the HEMT.

[0006] A nitride semiconductor device according to one embodiment of the present disclosure includes: a hexagonal SiC substrate having a primary surface tilted at an off-angle of 2° to 6° relative to a c-plane in a specific crystal direction; a nitride semiconductor layer located on the primary surface of the SiC substrate, the nitride semiconductor layer including an electron transit layer and an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; and a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer. The primary surface is parallel to a first direction, a second direction orthogonal to the first direction, and a third direction coinciding with the specific crystal direction in a planar view. The gate electrode is located between the source electrode and the drain electrode, which are spaced apart in the first direction, and extends in the second direction. The first direction intersects with the third direction at an angle within a range of 90°±15°.

[0007] The nitride semiconductor device of the present disclosure can improve electron mobility.

[0008] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to an embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device taken along line F2-F2 shown in FIG. 1. FIG. 3 is a schematic diagram of the crystal structure of a SiC substrate having an off-angle. FIG. 4 is a schematic cross-sectional view showing a manufacturing process of a nitride semiconductor device. FIG. 5 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 4. FIG. 6 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 5. FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 6. FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 7. FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to the process shown in FIG. 8. FIG. 10 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a comparative example.

[0009] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] (Planar Layout of Nitride Semiconductor Device) FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to one embodiment. The nitride semiconductor device 10 may include an insulating layer 12, and a source wiring 14 and a drain wiring 16 located on the insulating layer 12. Note that the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 is a direction orthogonal to a main surface 22A (see FIG. 2 ) of a SiC substrate 22, which will be described later. As used herein, the term "planar view" refers to viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

[0012] The insulating layer 12 can be made of any insulating material that can insulate the source wiring 14 from the drain wiring 16. For example, the insulating layer 12 can be made of SiO ２ , SiN, SiON, Al ２ O ３ , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, or any combination thereof.

[0013] The source wiring 14 and the drain wiring 16 can be composed of one or more conductive materials. For example, the source wiring 14 and the drain wiring 16 can each include Au, Ti, TiN, Pt, Cu, Al, AlSiCu, AlCu, or any combination thereof.

[0014] As shown in FIG. 1 , the source wiring 14 may include a base portion 14A and a plurality of source fingers 14B connected to the base portion 14A. In the illustrated example, the base portion 14A extends in the X-axis direction, and the plurality of source fingers 14B extend in the Y-axis direction. Similarly, the drain wiring 16 may include a base portion 16A and a plurality of drain fingers 16B connected to the base portion 16A. In the illustrated example, the base portion 16A extends in the X-axis direction, and the plurality of drain fingers 16B extend in the Y-axis direction. Note that in this disclosure, the X-axis direction and the Y-axis direction are also referred to as the "first direction" and the "second direction," respectively. The plurality of source fingers 14B and the plurality of drain fingers 16B may be spaced apart from each other and alternately positioned. In the illustrated example, the plurality of source fingers 14B and the plurality of drain fingers 16B are arranged alternately in the X-axis direction.

[0015] The nitride semiconductor device 10 may further include a gate wiring 18 and a plurality of gate electrodes 20 connected to the gate wiring 18. The gate wiring 18 and the plurality of gate electrodes 20 may be located below the source wiring 14 and the drain wiring 16 and may be covered by the insulating layer 12. In the illustrated example, the gate wiring 18 extends in the X-axis direction, and the plurality of gate electrodes 20 extend in the Y-axis direction. Each gate electrode 20 may be located between one of the plurality of source fingers 14B and one of the plurality of drain fingers 16B in a plan view. In the illustrated example, each gate electrode 20 is located between the source finger 14B and the drain finger 16B that face each other in the X-axis direction in a plan view. The gate wiring 18 may extend between the base portion 14A of the source wiring 14 and the plurality of drain fingers 16B in a plan view. In another example, the gate wiring 18 may extend between the base portion 16A of the drain wiring 16 and the plurality of source fingers 14B in a plan view. Further details of the gate electrode 20 will be described below with reference to FIG.

[0016] (Cross-sectional Structure of Nitride Semiconductor Device) FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F2-F2 in FIG. 1 . The nitride semiconductor device 10 includes a hexagonal SiC substrate 22 having a primary surface 22A and a nitride semiconductor layer 24 located on the primary surface 22A of the SiC substrate 22. The SiC substrate 22 also has a back surface 22B opposite the primary surface 22A. Note that in this disclosure, the term "primary surface" refers to the surface of the SiC substrate 22 on which the nitride semiconductor layer 24 is epitaxially grown (the surface in contact with the nitride semiconductor layer 24, which is an epitaxial layer). The primary surface 22A is parallel to a first direction D1 (X-axis direction) and a second direction D2 (Y-axis direction) that is perpendicular to the first direction D1 in a plan view.

[0017] The SiC substrate 22 has an off angle θ ｏｆｆ The main surface 22A is a SiC substrate having an off angle θ in a specific crystal direction with respect to the c-plane. ｏｆｆ The off angle θ ｏｆｆ The off angle θ may be 2° or more and 6° or less. ｏｆｆ The angle may be 3° or more and 5° or less, and more preferably 3.5° or more and 4.5° or less. In this disclosure, the term "c-plane" is used to refer to the (0001) plane of a hexagonal SiC crystal.

[0018] In this embodiment, the specific crystal direction may be the [11-20] direction. That is, the main surface 22A has an off angle θ of 2° to 6° in the [11-20] direction with respect to the c-plane. ｏｆｆ In the indices representing crystal directions and planes in the present disclosure, a number preceded by a minus sign (for example, "2" in the case of the [11-20] direction) means the number with a bar above it.

[0019] The SiC substrate 22 may be a 4H—SiC substrate. Here, “4H” represents the polytype of SiC crystal. The SiC substrate 22 may be conductive. The resistivity of the SiC substrate 22 may be, for example, 0.01 Ω·cm (ohm-centimeter) (=1 Ω·m (ohm-meter)) or more and 0.03 Ω·cm (=3 Ω·m) or less. In this embodiment, the resistivity of the SiC substrate 22 may be approximately 0.02 Ω·cm (=2 Ω·m). The thickness of the SiC substrate 22 may be, for example, 30 μm (micrometers) or more and 300 μm or less. In this embodiment, the SiC substrate 22 may have a thickness of 150 μm.

[0020] The nitride semiconductor layer 24 is an epitaxial layer located on the primary surface 22A of the SiC substrate 22. In this embodiment, the nitride semiconductor layer 24 may include a buffer layer 26 located on the SiC substrate 22 and a semi-insulating layer 28 located on the buffer layer 26.

[0021] The buffer layer 26 may be made of any material that can suppress warping of the SiC substrate 22 due to a mismatch in thermal expansion coefficient between the SiC substrate 22 and the semi-insulating layer 28 and the occurrence of cracks in the nitride semiconductor device 10. For example, the buffer layer 26 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. The buffer layer 26 may also be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In this embodiment, the buffer layer 26 may include a first buffer layer that is an AlN layer located on the primary surface 22A of the SiC substrate 22, and a second buffer layer that is an AlGaN layer located on the AlN layer. The thickness of the buffer layer 26 may be 5 nm to 2 μm. In this embodiment, the buffer layer 26 may have a thickness of about 0.8 μm.

[0022] The semi-insulating layer 28 may be a GaN layer doped with an impurity. The semi-insulating layer 28 may be provided to reduce leakage current. The impurity may be, for example, carbon (C) or iron (Fe). Alternatively, the impurity may be both C and Fe. The impurity may be a GaN layer having a concentration such that the difference between the acceptor concentration Na and the donor concentration Nd (Na−Nd) is 1×10 １７ cm －３ The GaN layer may be doped to a thickness of about 1 μm to 10 μm. In this embodiment, the semi-insulating layer 28 may have a thickness of 2 μm.

[0023] The nitride semiconductor layer 24 further includes an electron transit layer 30 and an electron supply layer 32 located on the electron transit layer 30. The electron transit layer 30 may be located on the semi-insulating layer 28. The electron transit layer 30 may be made of GaN. In this embodiment, the electron transit layer 30 may be an n-type GaN layer doped with donor impurities. In another example, the electron transit layer 30 may be an undoped GaN layer. The thickness of the electron transit layer 30 may be 0.05 μm or more and 1 μm or less. In this embodiment, the electron transit layer 30 may have a thickness of approximately 0.2 μm.

[0024] The electron supply layer 32 has a larger band gap than the electron transit layer 30. In this embodiment, the electron supply layer 32 is made of Al ｘ Ga １－ｘ The electron supply layer 32 may be composed of N, where 0<x≦1, and more preferably 0.1<x<0.3. The band gap of AlGaN increases as the Al composition increases. In this embodiment, X=0.2. The thickness of the electron supply layer 32 may be 1 nm or more and 100 nm or less. In this embodiment, the electron supply layer 32 may have a thickness of approximately 20 nm.

[0025] The electron transit layer 30 and the electron supply layer 32 are made of nitride semiconductors with different lattice constants. Therefore, the junction between the nitride semiconductor (e.g., GaN) constituting the electron transit layer 30 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 32 is a lattice-mismatched heterojunction. Due to spontaneous polarization in the electron transit layer 30 and the electron supply layer 32 and piezoelectric polarization caused by crystal strain near the heterojunction interface, the energy level of the conduction band of the electron transit layer 30 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 34 is generated in the electron transit layer 30 near the heterojunction interface between the electron transit layer 30 and the electron supply layer 32 (e.g., within a range of several nanometers from the interface). The 2DEG 34 in the electron transit layer 30 functions as a channel of the nitride semiconductor device 10. The sheet carrier density of the 2DEG 34 generated in the electron transit layer 30 can be increased by increasing at least one of the Al composition and the thickness of the electron supply layer 32 .

[0026] The nitride semiconductor device 10 may further include a first insulating layer 36 located on the electron supply layer 32. The first insulating layer 36 has a source contact opening 36A, a drain contact opening 36B, and a gate contact opening 36C that expose the surface of the electron supply layer 32. The source contact opening 36A and the drain contact opening 36B are spaced apart in the X-axis direction. The gate contact opening 36C is located between the source contact opening 36A and the drain contact opening 36B that are spaced apart in the X-axis direction. The first insulating layer 36 is made of SiO ２ , SiN, SiON, Al ２ O ３ , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, or any combination thereof. In this embodiment, the first insulating layer 36 may be SiN. The thickness of the first insulating layer 36 may be, for example, not less than 10 nm and not more than 200 nm. In this embodiment, the first insulating layer 36 may have a thickness of approximately 100 nm. The first insulating layer 36 is part of the insulating layer 12.

[0027] The nitride semiconductor device 10 includes a gate electrode 20, a source electrode 38, and a drain electrode 40 located on a nitride semiconductor layer 24. The source electrode 38 and the drain electrode 40 are spaced apart in a first direction D1 (the X-axis direction). The gate electrode 20 is located between the source electrode 38 and the drain electrode 40, which are spaced apart in the first direction D1. The source electrode 38, the drain electrode 40, and the gate electrode 20 are located so as to allow electrons to travel in the first direction D1 via the 2DEG 34. The source electrode 38 is in contact with the electron supply layer 32 through a source contact opening 36A. The drain electrode 40 is in contact with the electron supply layer 32 through a drain contact opening 36B. The gate electrode 20 is in contact with the electron supply layer 32 through a gate contact opening 36C.

[0028] The source electrode 38 and the drain electrode 40 can be made of any material capable of forming an ohmic contact with the nitride semiconductor layer 24. In this embodiment, the source electrode 38 and the drain electrode 40 may include a Ti layer and an Al layer. In this case, the Ti layer may be located between the first insulating layer 36 and the Al layer. In one example, the Ti layer may have a thickness of approximately 20 nm, and the Al layer may have a thickness of approximately 300 nm. In another example, the source electrode 38 and the drain electrode 40 may include a Ta layer and an Al layer. In yet another example, the source electrode 38 and the drain electrode 40 may include a Ti layer, an Al layer, a Ni layer, and an Au layer, in this order from the bottom.

[0029] The gate electrode 20 may be made of any material capable of forming a Schottky junction with the nitride semiconductor layer 24. In this embodiment, the gate electrode 20 may include a Ni layer and an Au layer. In this case, the Ni layer may be located between the first insulating layer 36 and the Au layer. In one example, the Ni layer may have a thickness of 10 nm, and the Au layer may have a thickness of 600 nm.

[0030] The gate electrode 20 is located between a source electrode 38 and a drain electrode 40 that are spaced apart in a first direction D1 (X-axis direction) and extends in a second direction D2 (Y-axis direction) (see FIG. 1 ). The source electrode 38 and the drain electrode 40 also extend in the second direction D2. That is, the source electrode 38, the gate electrode 20, and the drain electrode 40 that extend in the second direction D2 are aligned in this order in the first direction D1. Therefore, electrons can travel in the first direction D1 between the source electrode 38 and the drain electrode 40 via the 2DEG 34 in the electron transit layer 30. The source electrode 38, the gate electrode 20, and the drain electrode 40 are located such that the first direction D1 (i.e., the electron transit direction) satisfies a predetermined relationship with a specific crystal orientation ([11-20]) of the SiC substrate 22. This predetermined relationship will be described later with reference to FIG. 3 .

[0031] The nitride semiconductor device 10 may further include a second insulating layer 42 located on the first insulating layer 36. The second insulating layer 42 has a first opening 42A exposing the surface of the source electrode 38 and a second opening 42B exposing the surface of the drain electrode 40. The second insulating layer 42 is made of SiO ２ , SiN, SiON, Al ２ O ３ , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, or any combination thereof. ２ The second insulating layer 42 may have a thickness of about 500 nm. The second insulating layer 42 is a part of the insulating layer 12. The insulating layer 12 includes the first insulating layer 36 and the second insulating layer 42.

[0032] The source wiring 14 and the drain wiring 16 are located on the second insulating layer 42. The source finger 14B of the source wiring 14 is connected to the source electrode 38 through the first opening 42A. The drain finger 16B of the drain wiring 16 is connected to the drain electrode 40 through the second opening 42B.

[0033] Although the above description with reference to FIG. 2 focuses on one source electrode 38, one drain electrode 40, and the gate electrode 20 located therebetween, the nitride semiconductor device 10 may include multiple gate electrodes 20, multiple source electrodes 38, and multiple drain electrodes 40 located on the nitride semiconductor layer 24. Each of the multiple source electrodes 38 can be connected to one of the multiple source fingers 14B (see FIG. 1) through a first opening 42A. Similarly, each of the multiple drain electrodes 40 can be connected to one of the multiple drain fingers 16B (see FIG. 1) through a second opening 42B. The multiple source electrodes 38 and the multiple drain electrodes 40 may be alternately positioned in the first direction D1 (X-axis direction). Furthermore, each of the multiple gate electrodes 20 may be positioned between one of the multiple source electrodes 38 and one of the multiple drain electrodes 40.

[0034] (Relationship between Electron Travel Direction and Specific Crystalline Direction of SiC Substrate) Next, the relationship between the first direction D1 (electron travel direction) and the specific crystalline direction ([11-20]) of the SiC substrate 22 will be described with reference to FIG. ｏｆｆ 3 is a schematic diagram of the surface structure of the SiC substrate 22 having an ideal crystal structure. Note that, for ease of explanation, FIG. 3 shows a schematic representation of the surface structure at the atomic level when the SiC substrate 22 has an ideal crystal structure.

[0035] As shown in FIG. 3 , the surface structure of the SiC substrate 22 may have a plurality of terraces 50 and a plurality of steps 52 connecting the terraces 50. Each terrace 50 is a flat surface at the atomic level. Each terrace 50 has a (0001) plane (i.e., a c-plane) that is perpendicular to the

[0001] direction of the hexagonal SiC crystal. The dashed line in the figure virtually represents the (0001) plane. Each step 52 connecting the terraces 50 may have a dimension equivalent to one or several atomic layers. For ease of understanding, the off-angle θ in FIG. 3 is ｏｆｆIt should be understood that the dimensions of the steps 52 are exaggerated. The SiC substrate 22 has a step-and-terrace structure as shown in Fig. 3 at the atomic level, but actually has a substantially flat primary surface 22A. For the sake of explanation, Fig. 3 shows an imaginary plane 54 parallel to the primary surface 22A.

[0036] FIG. 3 shows that the main surface 22A is oriented at an off angle θ in the [11-20] direction, which is a specific crystal direction, with respect to the c-plane. ｏｆｆ 1 shows an example in which the SiC substrate 22 is tilted at an angle of 0.05°. Here, a direction that coincides with a specific crystal direction in a plan view is defined as a third direction D3. That is, the third direction D3 is a direction obtained by projecting the specific crystal direction (the [11-20] direction in the illustrated example) onto the main surface 22A (or an imaginary plane 54 parallel to the main surface 22A). Therefore, the main surface 22A is parallel to the third direction D3. The third direction D3 can also be called the tilt direction of the SiC substrate 22. Because the third direction D3 is parallel to the main surface 22A, the angle formed between the third direction D3 and the specific crystal direction (the [11-20] direction) is an off angle θ ｏｆｆ is equivalent to

[0037] 2, the nitride semiconductor layer 24 is an epitaxial layer located on the primary surface 22A of the SiC substrate 22, and therefore the crystal structure of the primary surface 22A of the SiC substrate 22 can be inherited by the nitride semiconductor layer 24. ｏｆｆ The structure of the SiC substrate 22 having the terraces 50 and steps 52 alternately and continuously may also affect the electron mobility of the 2DEG 34 generated in the electron transit layer 30 included in the nitride semiconductor layer 24.

[0038] In this embodiment, the source electrode 38, the gate electrode 20, and the drain electrode 40 (see FIG. 2) are positioned such that the first direction D1 satisfies a predetermined relationship with a specific crystal direction of the SiC substrate 22. In this embodiment, the first direction D1 intersects with the third direction D3, which coincides with the specific crystal direction in a planar view, at an angle within a range of 90°±15°. As described above, the first direction D1 corresponds to the electron travel direction. Also, as shown in FIG. 3, the third direction D3 corresponds to a direction crossing the steps 52 in a planar view (see arrow B in FIG. 3). For example, when the first direction D1 intersects with the third direction D3 at 90°, electrons can travel in the direction of arrow A in FIG. 3, i.e., in a direction that does not cross the steps 52 in a planar view. When electrons travel in the direction of arrow A, scattering of the electrons is smaller than scattering of the electrons when electrons travel in the direction of arrow B. In this way, by making the first direction D1 intersect with the third direction D3 at an angle within the range of 90°±15°, it is possible to make the electrons travel in a direction in which the electrons are scattered relatively little.

[0039] (Method of Manufacturing Nitride Semiconductor Device) Next, an example of a method of manufacturing the nitride semiconductor device 10 will be described. Figures 4 to 9 are schematic cross-sectional views showing exemplary manufacturing steps of the nitride semiconductor device 10. For ease of understanding, in Figures 4 to 9, components similar to those in Figure 2 are denoted by the same reference numerals.

[0040] 4, a nitride semiconductor layer 24 is formed on a primary surface 22A of a SiC substrate 22. In this embodiment, the SiC substrate 22 may be a 4H—SiC substrate having a resistivity of approximately 2 Ω·m. The SiC substrate 22 is oriented at an off angle θ of 4° in the [11-20] direction with respect to the c-plane. ｏｆｆ The main surface 22A may be inclined at .

[0041] The nitride semiconductor layer 24 can be epitaxially grown on the primary surface 22A of the SiC substrate 22 using a metal-organic chemical vapor deposition (MOCVD) method. The nitride semiconductor layer 24 may include a buffer layer 26 formed on the primary surface 22A of the SiC substrate 22 and a semi-insulating layer 28 formed on the buffer layer 26. In this embodiment, the buffer layer 26 may include a first buffer layer that is an AlN layer formed on the primary surface 22A of the SiC substrate 22 and a second buffer layer that is an AlGaN layer formed on the AlN layer. The buffer layer 26 may have a thickness of approximately 0.8 μm. The semi-insulating layer 28 may be a GaN layer doped with C or Fe. In one example, the semi-insulating layer 28 may have a thickness of 2 μm.

[0042] The nitride semiconductor layer 24 further includes an electron transit layer 30 and an electron supply layer 32 formed on the electron transit layer 30. The electron transit layer 30 may be formed on the semi-insulating layer 28. In this embodiment, the electron transit layer 30 may be an n-type GaN layer doped with donor-type impurities. The electron transit layer 30 may have a thickness of about 0.2 μm. The electron supply layer 32 may be made of Al ｘ Ga １－ｘ N, where X=0.2. The electron supply layer 32 may have a thickness of approximately 20 nm. By forming a heterojunction between the electron transit layer 30 and the electron supply layer 32, a two-dimensional electron gas (2DEG) 34 is generated in the electron transit layer 30 near the interface between the electron transit layer 30 and the electron supply layer 32.

[0043] 5 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 5 . As shown in FIG. 5 , a first insulating layer 36 is formed on the nitride semiconductor layer 24. In this embodiment, the first insulating layer 36 may be a SiN layer having a thickness of approximately 100 nm. In one example, the first insulating layer 36 can be formed by a plasma-enhanced chemical vapor deposition (PECVD) method. In another example, the first insulating layer 36 may be formed by a low-pressure chemical vapor deposition (LPCVD) method, a sputtering method, an atomic layer deposition (ALD) method, or a molecular beam epitaxy (MBE) method.

[0044] Fig. 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 5. As shown in Fig. 6, a source contact opening 36A and a drain contact opening 36B are formed in the first insulating layer 36, and then a source electrode 38 and a drain electrode 40 are formed.

[0045] In this process, the first insulating layer 36 is selectively removed by etching to form a source contact opening 36A and a drain contact opening 36B that penetrate the first insulating layer 36. The source contact opening 36A and the drain contact opening 36B are positioned to be spaced apart from each other in a first direction D1 (the X-axis direction). Here, the first direction D1 intersects with a third direction D3, which coincides with the [11-20] direction of the SiC substrate 22 in a plan view, at an angle within a range of 90°±15°.

[0046] Next, a first metal layer (not shown) is formed on the first insulating layer 36 so as to fill the source contact opening 36A and the drain contact opening 36B. The source electrode 38 and the drain electrode 40 shown in FIG. 6 are composed of a portion of the first metal layer. In this embodiment, the first metal layer may include a Ti layer having a thickness of approximately 20 nm and an Al layer having a thickness of approximately 300 nm formed on the Ti layer. The Ti layer contacts the surface of the electron supply layer 32 exposed by the source contact opening 36A and the drain contact opening 36B. Next, annealing is performed at 500°C to 550°C, thereby forming ohmic contact between the first metal layer and the nitride semiconductor layer 24. The first metal layer is selectively removed by etching, thereby obtaining the source electrode 38 and the drain electrode 40 shown in FIG. 6.

[0047] Fig. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 6. As shown in Fig. 7, a gate contact opening 36C is formed in the first insulating layer 36, and then the gate electrode 20 is formed.

[0048] In this process, the first insulating layer 36 is selectively removed by etching to form a gate contact opening 36C that penetrates the first insulating layer 36. The gate contact opening 36C is provided between the source contact opening 36A and the drain contact opening 36B that are spaced apart from each other in the first direction D1.

[0049] Next, a second metal layer (not shown) is formed on the first insulating layer 36 so as to fill the gate contact opening 36C. The gate electrode 20 shown in FIG. 7 is composed of a portion of the second metal layer. In this embodiment, the second metal layer may include a Ni layer having a thickness of approximately 10 nm and an Au layer having a thickness of approximately 600 nm formed on the Ni layer. The Ni layer is in contact with the surface of the electron supply layer 32 exposed by the gate contact opening 36C. A Schottky junction is formed between the second metal layer and the nitride semiconductor layer 24. The second metal layer is selectively removed by etching to obtain the gate electrode 20 shown in FIG. 7.

[0050] 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 7. As shown in Fig. 8, a second insulating layer 42 is formed on the first insulating layer 36. The second insulating layer 42 covers the surfaces of the gate electrode 20, the source electrode 38, and the drain electrode 40. In this embodiment, the second insulating layer 42 is made of SiO2 having a thickness of about 500 nm. ２ In one example, the second insulating layer 42 can be formed by a PECVD process. In another example, the second insulating layer 42 can be formed by an LPCVD process, a sputtering process, an ALD process, or an MBE process.

[0051] 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 8. As shown in Fig. 9, a first opening 42A and a second opening 42B are formed in the second insulating layer 42. In this step, the second insulating layer 42 is selectively removed by etching to form the first opening 42A and the second opening 42B penetrating the second insulating layer 42. The first opening 42A exposes the surface of the source electrode 38. The second opening 42B exposes the surface of the drain electrode 40.

[0052] After this step, a third metal layer is formed on the second insulating layer 42 to fill the first opening 42A and the second opening 42B, and then the third metal layer is patterned by, for example, ion milling. In this embodiment, the third metal layer may include a Ti layer having a thickness of approximately 10 nm, a Pt layer having a thickness of approximately 50 nm formed on the Ti layer, and an Au layer having a thickness of approximately 3 μm formed on the Pt layer. As a result, the nitride semiconductor device 10 including the source wiring 14 and the drain wiring 16 shown in FIG. 2 can be obtained.

[0053] (Function of Nitride Semiconductor Device) In the nitride semiconductor device 10, the gate electrode 20 is located between the source electrode 38 and the drain electrode 40 that are spaced apart in a first direction D1, and extends in a second direction D2. The first direction D1 intersects with a third direction D3 that coincides with a specific crystal direction in a plan view, at an angle in the range of 90°±15°.

[0054] Because the source electrode 38, the gate electrode 20, and the drain electrode 40 are aligned in this order in the first direction D1, electrons can travel between the source electrode 38 and the drain electrode 40 in the first direction D1. Meanwhile, the third direction D3 is the inclination direction of the SiC substrate 22 and corresponds to the direction crossing the steps 52 in a planar view (see arrow B in FIG. 3 ). The first direction D1 intersects with the third direction D3 at an angle in the range of 90°±15°, thereby reducing the likelihood of electrons traveling in a direction crossing the steps 52 in a planar view. As a result, the increase in scattering of electrons traveling in the first direction D1 between the source electrode 38 and the drain electrode 40 is reduced, thereby increasing the electron mobility when electrons travel between the source electrode 38 and the drain electrode 40.

[0055] 10 is a schematic cross-sectional view of an exemplary nitride semiconductor device 100 according to a comparative example. To explain the electron mobility improvement effect in the nitride semiconductor device 10 according to this embodiment, FIG. 10 shows a comparative example in which the first direction D1 and the third direction D3 are parallel to each other. In FIG. 10, the same components as those in the nitride semiconductor device 10 shown in FIG. 2 are denoted by the same reference numerals. Further, detailed description of the same components as those in the nitride semiconductor device 10 will be omitted.

[0056] 10, the nitride semiconductor device 100 includes a SiC substrate 102 having a main surface 102A and a back surface 102B. The SiC substrate 102 has an off-angle θ ｏｆｆ That is, the main surface 102A has an off angle θ of 2° to 6° in a specific crystal direction with respect to the c-plane. ｏｆｆ In this example, the specific crystal direction is the [11-20] direction. In the comparative example, the third direction D3, which coincides with the specific crystal direction in a plan view, is parallel to the first direction D1 (X-axis direction). In the nitride semiconductor device 100, the source electrode 38, the gate electrode 20, and the drain electrode 40 are aligned in this order in the first direction D1, similar to the nitride semiconductor device 10. Therefore, in the comparative example, electrons travel in a direction that crosses the step 52 in a plan view (see arrow B in FIG. 3 ).

[0057] Because the nitride semiconductor layer 24 is an epitaxial layer located on the main surface 102A of the SiC substrate 102, the crystal structure of the main surface 102A of the SiC substrate 102 can be inherited by the nitride semiconductor layer 24. When the first direction D1 (electron travel direction) is parallel to the third direction D3 (tilt direction of the SiC substrate 102) as in the comparative example, scattering of electrons traveling in the first direction D1 via the 2DEG 104 generated in the electron travel layer 30 can be relatively large. As a result, electron mobility can be reduced in the nitride semiconductor device 100 of the comparative example.

[0058] In this regard, in the nitride semiconductor device 10 of this embodiment, the first direction D1 (electron travel direction) intersects with the third direction D3 (tilt direction of the SiC substrate 22) at an angle in the range of 90°±15°. Therefore, even if the crystal structure of the main surface 22A of the SiC substrate 22 is inherited by the nitride semiconductor layer 24, an increase in scattering of electrons traveling in the first direction D1 via the 2DEG 34 is reduced. As a result, the nitride semiconductor device 10 of this embodiment can increase electron mobility.

[0059] The nitride semiconductor device 10 of this embodiment has the following advantages: (1) The SiC substrate 22 has an off angle θ of 2° to 6° in a specific crystal direction with respect to the c-plane. ｏｆｆ The gate electrode 20 has a major surface 22A that is inclined at θ = 0.05. The gate electrode 20 is located between a source electrode 38 and a drain electrode 40 that are spaced apart in a first direction D1, and extends in a second direction D2. The first direction D1 intersects with a third direction D3 that coincides with a specific crystal direction in a plan view, at an angle within a range of 90°±15°. As a result, an increase in scattering of electrons traveling in the first direction D1 between the source electrode 38 and the drain electrode 40 is reduced, thereby increasing the electron mobility when the electrons travel between the source electrode 38 and the drain electrode 40.

[0060] (2) The first direction D1 may intersect with the third direction D3 at an angle within a range of 90°±10°. This further reduces the increase in scattering of electrons traveling in the first direction D1 between the source electrode 38 and the drain electrode 40, thereby further increasing the electron mobility when the electrons travel between the source electrode 38 and the drain electrode 40.

[0061] (3) The electron transit layer 30 is made of GaN, while the electron supply layer 32 is made of Al ｘ Ga １－ｘ N, and 0.1<x<0.3. This allows the 2DEG 34 having a desired sheet carrier density to be generated in the electron transit layer 30.

[0062] (4) The nitride semiconductor layer 24 may include a semi-insulating layer 28. Furthermore, the electron transit layer 30 may be located on the semi-insulating layer 28. This can reduce the leakage current of the nitride semiconductor device 10.

[0063] (5) The nitride semiconductor layer 24 may include a buffer layer 26 located on the primary surface 22A of the SiC substrate 22. This can prevent the SiC substrate 22 from warping and the nitride semiconductor device 10 from cracking.

[0064] [Modifications] The above embodiment can be modified as follows. The planar layout of the nitride semiconductor device 10 is not limited to the example in FIG. 1 . For example, the nitride semiconductor device 10 may include a back electrode located on the back surface 22B of the SiC substrate 22 and a contact plug penetrating the nitride semiconductor layer 24. When the back electrode is connected to the source electrode 38 via a contact plug, the source wiring 14 does not need to include the base portion 14A.

[0065] The polytype of the SiC substrate 22 is not limited to 4H. The SiC substrate 22 may be, for example, a 2H—SiC substrate or a 6H—SiC substrate. One or more of the various examples described in this specification may be combined to the extent that they are not technically inconsistent.

[0066] As used herein, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." The term "on" as used in this disclosure can mean both "on" and "above," unless the context clearly indicates otherwise. Thus, the expression "a first layer is located on a second layer" is intended to mean that in some embodiments, the first layer can be in contact with and directly located on the second layer, while in other embodiments, the first layer can be located above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is located between the first and second layers.

[0067] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0068] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0069] [Notes] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference symbols.

[0070] (Note 1) An off angle (θ) of 2° to 6° in a specific crystal direction relative to the c-plane ｏｆｆa hexagonal SiC substrate (22) having a main surface (22A) inclined in a direction perpendicular to the plane of the SiC substrate (22); a nitride semiconductor layer (24) located on the main surface (22A) of the SiC substrate (22), the nitride semiconductor layer (24) including: an electron transit layer (30); and an electron supply layer (32) located on the electron transit layer (30) and having a band gap larger than that of the electron transit layer (30); and a gate electrode (20), a source electrode (38), and a drain electrode (40) located on the nitride semiconductor layer (24), wherein the main surface (22A) is parallel to a first direction (D1), a second direction (D2) orthogonal to the first direction (D1), and a third direction (D3) coinciding with the specific crystal direction in a plan view, The gate electrode (20) is located between the source electrode (38) and the drain electrode (40) that are spaced apart in the first direction (D1) and extends in the second direction (D2), and the first direction (D1) intersects with the third direction (D3) at an angle within a range of 90°±15°.

[0071] (Note 2) The off angle (θ ｏｆｆ 2. The nitride semiconductor device according to claim 1, wherein the angle .theta.

[0072] (Note 3) The off angle (θ ｏｆｆ 2. The nitride semiconductor device according to claim 1, wherein the angle .theta.

[0073] (Supplementary Note 4) The nitride semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the specific crystal direction is a [11-20] direction.

[0074] (Supplementary Note 5) The nitride semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the first direction (D1) intersects with the third direction (D3) at an angle within a range of 90°±10°.

[0075] (Supplementary Note 6) The nitride semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the SiC substrate (22) is a 4H—SiC substrate.

[0076] (Supplementary Note 7) The nitride semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the resistivity of the SiC substrate (22) is 1 Ω·m or more and 3 Ω·m or less.

[0077] (Supplementary Note 8) The nitride semiconductor device according to any one of Supplementary Notes 1 to 7, wherein a two-dimensional electron gas (34) is generated in the electron transit layer (30).

[0078] (Supplementary Note 9) The nitride semiconductor device according to Supplementary Note 8, wherein the source electrode (38), the drain electrode (40), and the gate electrode (20) are positioned to enable electrons to travel in the first direction (D1) through the two-dimensional electron gas (34).

[0079] (Supplementary Note 10) The nitride semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the gate electrode (20) is one of a plurality of gate electrodes (20) located on the nitride semiconductor layer (24), the source electrode (38) is one of a plurality of source electrodes (38) located on the nitride semiconductor layer (24), and the drain electrode (40) is one of a plurality of drain electrodes (40) located on the nitride semiconductor layer (24), the plurality of source electrodes (38) and the plurality of drain electrodes (40) are alternately located in the first direction (D1), and each of the plurality of gate electrodes (20) is located between one of the plurality of source electrodes (38) and one of the plurality of drain electrodes (40).

[0080] (Note 11) The electron transit layer (30) is made of GaN, and the electron supply layer (32) is made of Al. ｘ Ga １－ｘ N, and 0.1<x<0.3.

[0081] (Supplementary Note 12) The nitride semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the electron transit layer (30) is an n-type GaN layer.

[0082] (Supplementary Note 13) The nitride semiconductor device according to any one of Supplementary Notes 1 to 12, wherein the nitride semiconductor layer (24) further includes a semi-insulating layer (28), and the electron transit layer (30) is located on the semi-insulating layer (28).

[0083] (Supplementary Note 14) The nitride semiconductor device according to Supplementary Note 13, wherein the semi-insulating layer (28) is a GaN layer doped with an impurity, and the impurity is carbon or iron.

[0084] (Supplementary Note 15) The nitride semiconductor device according to any one of Supplementary Notes 1 to 14, wherein the nitride semiconductor layer (24) is an epitaxial layer located on the main surface (22A) of the SiC substrate (22).

[0085] (Appendix 16) The nitride semiconductor device according to any one of Appendices 1 to 15, wherein the nitride semiconductor layer (24) further includes a buffer layer (26) located on the main surface (22A) of the SiC substrate (22).

[0086] (Supplementary Note 17) The nitride semiconductor device according to Supplementary Note 16, wherein the buffer layer (26) includes an AlN layer located on the main surface (22A) of the SiC substrate (22), and an AlGaN layer located on the AlN layer.

[0087] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0088] REFERENCE SIGNS LIST 10, 100...Nitride semiconductor device 12...Insulating layer 14...Source wiring 14A...Base portion 14B...Source finger 16...Drain wiring 16A...Base portion 16B...Drain finger 18...Gate wiring 20...Gate electrode 22, 102...SiC substrate 22A, 102A...Main surface 22B, 102B...Back surface 24...Nitride semiconductor layer 26...Buffer layer 28...Semi-insulating layer 30...Electron transit layer 32...Electron supply layer 34, 104...Two-dimensional electron gas (2DEG) 36...First insulating layer 36A...Source contact opening 36B...Drain contact opening 36C...Gate contact opening 38...Source electrode 40...Drain electrode 42...Second insulating layer 42A...First opening 42B...Second opening 50...Terrace 52...Step D1...First direction D2...Second direction D3...Third direction θ ｏｆｆ …Off angle

Claims

1. A hexagonal SiC substrate having a main surface inclined at an off angle of 2° to 6° in a specific crystal direction with respect to a c-plane; A nitride semiconductor layer located on the primary surface of the SiC substrate, An electron transport layer; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; A nitride semiconductor layer comprising: a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer; Equipped with the main surface is parallel to a first direction, a second direction perpendicular to the first direction, and a third direction coinciding with the specific crystal direction in a plan view; the gate electrode is located between the source electrode and the drain electrode spaced apart in the first direction and extends in the second direction; The nitride semiconductor device, wherein the first direction intersects with the third direction at an angle within a range of 90°±15°.

2. The nitride semiconductor device according to claim 1 , wherein the off angle is equal to or greater than 3° and equal to or less than 5°.

3. The nitride semiconductor device according to claim 1 , wherein the off angle is not less than 3.5° and not more than 4.5°.

4. 4. The nitride semiconductor device according to claim 1, wherein the specific crystal direction is a [11-20] direction.

5. 4. The nitride semiconductor device according to claim 1, wherein the first direction intersects with the third direction at an angle within a range of 90°±10°.

6. 4. The nitride semiconductor device according to claim 1, wherein the SiC substrate is a 4H-SiC substrate.

7. 4. The nitride semiconductor device according to claim 1, wherein the resistivity of said SiC substrate is not less than 1 Ω·m and not more than 3 Ω·m.

8. 4. The nitride semiconductor device according to claim 1, wherein a two-dimensional electron gas is generated in said electron transit layer.

9. The nitride semiconductor device according to claim 8 , wherein the source electrode, the drain electrode, and the gate electrode are positioned to enable transport of electrons in the first direction through the two-dimensional electron gas.

10. the gate electrode is one of a plurality of gate electrodes located on the nitride semiconductor layer; the source electrode is one of a plurality of source electrodes located on the nitride semiconductor layer; the drain electrode is one of a plurality of drain electrodes located on the nitride semiconductor layer; The plurality of source electrodes and the plurality of drain electrodes are alternately positioned in the first direction, 4. The nitride semiconductor device according to claim 1, wherein each of the plurality of gate electrodes is located between one of the plurality of source electrodes and one of the plurality of drain electrodes.

11. the electron transport layer is made of GaN; The electron supply layer is made of Al ｘ G １－ｘ N, where 0.1<x<0.3; 4. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is a nitride semiconductor layer.

12. 4. The nitride semiconductor device according to claim 1, wherein the electron transit layer is an n-type GaN layer.

13. The nitride semiconductor layer further includes a semi-insulating layer, 4. The nitride semiconductor device according to claim 1, wherein the electron transit layer is located on the semi-insulating layer.

14. the semi-insulating layer is a GaN layer doped with impurities; The nitride semiconductor device according to claim 13, wherein the impurity is carbon or iron.

15. 4. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor layer is an epitaxial layer located on the main surface of the SiC substrate.