Nitride semiconductor device

Abstract

This nitride semiconductor device (10) is provided with: a first nitride semiconductor layer (16); a second nitride semiconductor layer (18) which is formed on the first nitride semiconductor layer (16), and has a larger band gap than the first nitride semiconductor layer (16); and a gate electrode (32), a source electrode (24) and a drain electrode (26), which are formed above the second nitride semiconductor layer (18). The first nitride semiconductor layer (16) contains GaN. The half width of an X-ray rocking curve of the first nitride semiconductor layer (16) with respect to the (102) plane is 1,100 arcsec to 1,400 arcsec.

Description

nitride semiconductor devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Currently, high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) are being commercialized. Patent Document 1 describes an example of a normally-off type HEMT using a nitride semiconductor.

[0003] Japanese Patent Application Laid-Open No. 2017-73506

[0004] In a HEMT device using a nitride semiconductor, if the increase in on-resistance during device operation is large, given device characteristics may not be guaranteed. From the viewpoint of improving the reliability of HEMT products, it is required to suppress the increase in on-resistance in both normally-off and normally-on types.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed above the second nitride semiconductor layer. The first nitride semiconductor layer is a layer containing GaN. The full width at half maximum of an X-ray rocking curve for a (102) plane of the first nitride semiconductor layer is 1100 arcsec or more and 1400 arcsec or less.

[0006] The nitride semiconductor device according to one aspect can suppress an increase in on-resistance.

[0007] FIG. 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to an embodiment. FIG. 2 is a schematic cross-sectional view showing an exemplary structure of various nitride semiconductor layers formed on a semiconductor substrate in the nitride semiconductor device of FIG. 1. FIG. 3 is a diagram schematically showing the (102) plane of a first nitride semiconductor layer. FIG. 4 is a diagram schematically showing a screw dislocation. FIG. 5 is a diagram schematically showing an edge dislocation. FIG. 6 is a graph showing the relationship between the XRC half-width and the on-resistance variation rate for the (102) plane of the first nitride semiconductor layer, measured for various nitride semiconductor devices including first nitride semiconductor layers with different crystal defect densities.

[0008] Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. Note that, for simplicity and clarity of illustration and description, components shown in the drawings are not necessarily drawn to scale. For ease of understanding, features may be enlarged, and the dimensional ratios of each component may not be the same in each drawing. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to one embodiment. The nitride semiconductor device 10 is, for example, a GaN-based HEMT. The nitride semiconductor device 10 includes a semiconductor substrate 12, a buffer layer 14 formed on the semiconductor substrate 12, a first nitride semiconductor layer 16 formed on the buffer layer 14, and a second nitride semiconductor layer 18 formed on the first nitride semiconductor layer 16.

[0011] The semiconductor substrate 12 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. For example, the semiconductor substrate 12 is a Si substrate. The thickness of the semiconductor substrate 12 may be, for example, 200 μm or more and 1500 μm or less. Note that the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 is a direction perpendicular to the main surface (top surface in FIG. 1 ) of the semiconductor substrate 12. As used herein, the term "planar view" refers to viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise.

[0012] The buffer layer 14 includes one or more nitride semiconductor layers. For example, the buffer layer 14 may be made of any material that can suppress warping of the semiconductor substrate 12 and the occurrence of cracks in the nitride semiconductor device 10 due to a mismatch in thermal expansion coefficients between the semiconductor substrate 12 and the first nitride semiconductor layer 16.

[0013] In some embodiments, buffer layer 14 includes at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. Exemplary structures of buffer layer 14 are described below with reference to FIG. 2.

[0014] The first nitride semiconductor layer 16 is a layer containing GaN. In some embodiments, the first nitride semiconductor layer 16 includes a GaN composite layer in which a plurality of GaN layers are stacked. The thickness of the first nitride semiconductor layer 16 may be, for example, 0.5 μm to 2 μm. An exemplary structure of the first nitride semiconductor layer 16 will be described later with reference to FIG. 2 .

[0015] The second nitride semiconductor layer 18 is made of a nitride semiconductor having a larger band gap than the first nitride semiconductor layer 16. The second nitride semiconductor layer 18 may be, for example, an AlGaN layer. Since the band gap increases as the Al composition increases, the second nitride semiconductor layer 18, which is an AlGaN layer, has a larger band gap than the first nitride semiconductor layer 16, which includes a GaN composite layer. In one example, the second nitride semiconductor layer 18 is made of Al ｘ Ga １－ｘ The second nitride semiconductor layer 18 is made of N, where x is 0.1<x<0.4, and more preferably 0.1<x<0.3. The thickness of the second nitride semiconductor layer 18 can be, for example, 5 nm or more and 20 nm or less.

[0016] The first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (e.g., GaN) constituting the first nitride semiconductor layer 16 and the nitride semiconductor (e.g., AlGaN) constituting the second nitride semiconductor layer 18 form a lattice-mismatched heterojunction. Due to spontaneous polarization of the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 and piezoelectric polarization caused by crystal strain near the heterojunction interface, the energy level of the conduction band of the first nitride semiconductor layer 16 near the heterojunction interface is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads within the first nitride semiconductor layer 16 near the heterojunction interface between the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18 (e.g., within a range of about several nanometers from the interface).

[0017] The nitride semiconductor device 10 includes a gate structure 22, a source electrode 24, and a drain electrode 26 formed on the second nitride semiconductor layer 18, and a passivation layer 28 formed on the second nitride semiconductor layer 18 and covering the gate structure 22. The passivation layer 28 includes a source-side opening 28A and a drain-side opening 28B that each expose a portion of the top surface of the second nitride semiconductor layer 18. The passivation layer 28 may be made of, for example, silicon nitride (SiN), silicon dioxide (SiO ２ ), silicon oxynitride (SiON), aluminum oxide (Al ２ O ３ The passivation layer 28 may be made of at least one of aluminum oxynitride (AlON), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 28 may be, for example, 80 nm or more and 150 nm or less.

[0018] 1, in some embodiments, the gate structure 22 includes a gate layer 30 and a gate electrode 32 formed on the gate layer 30. The gate layer 30 may be, for example, a GaN layer doped with acceptor-type impurities, i.e., a p-type GaN layer. In this case, the acceptor-type impurities may be, for example, at least one of zinc (Zn), magnesium (Mg), and carbon (C). For example, the maximum concentration of the acceptor-type impurities in the gate layer 30 may be 7×10 １８ cm －３ 1x10 or more ２０ cm －３ It can be as follows:

[0019] 1, the gate layer 30 is located between the source-side opening 28A and the drain-side opening 28B of the passivation layer 28. The gate layer 30 is spaced apart from the source-side opening 28A and the drain-side opening 28B, and is located closer to the source-side opening 28A than the drain-side opening 28B.

[0020] The gate electrode 32 includes one or more metal layers. In some embodiments, the gate electrode 32 is formed of, for example, a titanium nitride (TiN) layer. In another embodiment, the gate electrode 32 is formed of a first metal layer made of Ti (titanium) and a second metal layer made of TiN provided on the first metal layer. The gate electrode 32 forms a Schottky junction with the gate layer 30. The thickness of the gate electrode 32 can be, for example, 50 nm to 200 nm.

[0021] The source electrode 24 and the drain electrode 26 include one or more metal layers. For example, the source electrode 24 and the drain electrode 26 may be formed of one or any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a portion of the source electrode 24 is filled in the source side opening 28A and makes ohmic contact with the 2DEG 20 immediately below the second nitride semiconductor layer 18 through the source side opening 28A. Similarly, at least a portion of the drain electrode 26 is filled in the drain side opening 28B and makes ohmic contact with the 2DEG 20 immediately below the second nitride semiconductor layer 18 through the drain side opening 28B. In the example of FIG. 1 , the semiconductor substrate 12 is connected to the source electrode 24, and a voltage having the same potential as that of the source electrode 24 is applied to the semiconductor substrate 12.

[0022] 1 , the gate structure 22 includes a gate layer 30 and a gate electrode 32. The gate layer 30 includes a top surface on which the gate electrode 32 is located and a bottom surface in contact with the second nitride semiconductor layer 18. In some embodiments, the gate layer 30 includes a gate layer body 34 that includes the top surface of the gate layer 30, and a source side extension 36 and a drain side extension 38 that are each thinner than the gate layer body 34. The gate layer body 34, the source side extension 36, and the drain side extension 38 are all in contact with the second nitride semiconductor layer 18.

[0023] The source-side extension 36 extends from the gate layer main body 34 toward the source-side opening 28A. A passivation layer 28 exists between the source electrode 24 embedded in the source-side opening 28A and the source-side extension 36. On the other hand, the drain-side extension 38 extends from the gate layer main body 34 toward the drain-side opening 28B. The passivation layer 28 exists between the drain electrode 26 embedded in the drain-side opening 28B and the drain-side extension 38.

[0024] The gate layer main body 34 is located between the source side extension 36 and the drain side extension 38 and is formed integrally with the source side extension 36 and the drain side extension 38. In the example of FIG. 1 , the gate layer main body 34 is formed to have a ridge-like (rectangular) cross section. However, the cross-sectional shape of the gate layer main body 34 is not particularly limited and may be, for example, a trapezoidal cross section or another cross-sectional shape. Due to the presence of the source side extension 36 and the drain side extension 38, the bottom surface of the gate layer 30 has a larger area than the top surface of the gate layer 30.

[0025] 1 , in some embodiments, the drain-side extension 38 extends further outward from the gate layer main body 34 in a plan view than the source-side extension 36. That is, the drain-side extension 38 may have a dimension in the X-axis direction that is larger than the source-side extension 36. The dimension (length) in the X-axis direction of the source-side extension 36 may be, for example, not less than 0.2 μm and not more than 0.3 μm. The dimension (length) in the X-axis direction of the drain-side extension 38 may be, for example, not less than 0.2 μm and not more than 0.6 μm.

[0026] The gate layer main body 34 corresponds to a relatively thick portion of the gate layer 30. The thickness of the gate layer main body 34 may be, for example, 80 nm or more and 150 nm or less. The thickness of the gate layer main body 34 may be determined taking into consideration various parameters including the gate threshold voltage. The source side extension 36 and the drain side extension 38 each have a thickness smaller than that of the gate layer main body 34. For example, the source side extension 36 and the drain side extension 38 may each have a thickness that is half or less of that of the gate layer main body 34.

[0027] The source side extension 36 and the drain side extension 38 may each include a flat portion of approximately constant thickness. The thickness of the flat portion of the source side extension 36 and the flat portion of the drain side extension 38 may be, for example, 5 nm to 25 nm. Note that, in this specification, "approximately constant thickness" refers to a thickness that is within a manufacturing variation range (e.g., 20%). Also, as shown in FIG. 1 , in some embodiments, the source side extension 36 and the drain side extension 38 may each include an intermediate portion between the flat portion and the gate layer main body 34 that is thicker than the flat portion. In one example, the intermediate portion may have a thickness that gradually decreases with increasing distance from the gate layer main body 34.

[0028] In the gate structure 22 of FIG. 1 , a gate layer 30 containing acceptor-type impurities is provided directly below a gate electrode 32. In this structure, when a gate input voltage applied to the gate electrode 32 causes the gate-source voltage to exceed a positive threshold voltage, a channel (current path) of the 2DEG 20 is formed in the region of the first nitride semiconductor layer 16 directly below the gate layer main body 34, thereby providing conduction between the source and drain. On the other hand, when the gate-source voltage does not exceed the threshold voltage, the 2DEG 20 disappears in at least a portion of the region of the first nitride semiconductor layer 16 directly below the gate layer main body 34 (see FIG. 1 ). This is because the gate layer main body 34 contains acceptor-type impurities, which raises the energy levels of the first nitride semiconductor layer 16 and the second nitride semiconductor layer 18, thereby depleting the 2DEG 20. As a result, the nitride semiconductor device 10 is realized as a normally-off HEMT.

[0029] 1 , in some embodiments, the nitride semiconductor device 10 includes a field plate electrode 40 formed on the passivation layer 28. In the example of FIG. 1 , the field plate electrode 40 is formed integrally with the source electrode 24 and covers the entire gate structure 22 in a plan view. In this structure, the field plate electrode 40 can also be considered as part of the source electrode 24, and a voltage having the same potential as the source electrode 24 is applied to the field plate electrode 40. However, the field plate electrode 40 may be provided separately from the source electrode 24, and a control voltage other than the source voltage may be applied to the field plate electrode 40.

[0030] The field plate electrode 40 is spaced apart from the drain electrode 26. The field plate electrode 40 includes an end 40A located between the gate layer 30 (drain-side extension 38) and the drain electrode 26 (drain-side opening 28B) in a plan view. The field plate electrode 40 serves to alleviate electric field concentration near the end of the gate electrode 32 and near the end of the gate layer 30 when a drain voltage is applied to the drain electrode 26 in a zero-bias state in which no gate input voltage is applied to the gate electrode 32.

[0031] 2 is a schematic cross-sectional view showing an exemplary structure of various nitride semiconductor layers formed on a semiconductor substrate 12. As described above, the buffer layer 14, first nitride semiconductor layer 16, second nitride semiconductor layer 18, and gate layer 30 (third nitride semiconductor layer) are formed in this order on the semiconductor substrate 12. Below, an exemplary structure of each layer will be described in order.

[0032] [4-1. Buffer Layer] First, an exemplary structure of the buffer layer 14 will be described. In some embodiments, the buffer layer 14 may include a first buffer layer 52 formed on the semiconductor substrate 12 and a second buffer layer 54 formed on the first buffer layer 52. The first buffer layer 52 may be, for example, an AlN layer. The thickness of the first buffer layer 52 may be, for example, not less than 100 nm and not more than 300 nm.

[0033] The second buffer layer 54 may be, for example, an AlGaN composite layer formed by stacking multiple AlGaN layers. In some embodiments, the second buffer layer 54 may be a graded AlGaN layer formed by stacking multiple AlGaN layers having different aluminum (Al) compositions. In the example of FIG. 2 , the second buffer layer 54 is formed as a graded AlGaN layer formed by stacking three AlGaN layers, namely, a first AlGaN layer 54A, a second AlGaN layer 54B, and a third AlGaN layer 54C, in that order. The thickness of each of the first to third AlGaN layers 54A, 54B, and 54C may be, for example, 100 nm to 300 nm.

[0034] The third AlGaN layer 54C is located on the top layer of the second buffer layer 54 (buffer layer 14). In some embodiments, the third AlGaN layer 54C may have a lower Al composition and a greater thickness than the second AlGaN layer 54B. On the other hand, the second AlGaN layer 54B may have a lower Al composition than the first AlGaN layer 54A and the same thickness as the first AlGaN layer 54A. For example, the thicknesses of the first and second AlGaN layers 54A and 54B may each be approximately 100 nm, and the thickness of the third AlGaN layer 54C may be at least twice the thickness of the second AlGaN layer 54B, for example, at least 200 nm. The Al composition ratios in the first to third AlGaN layers 54A, 54B, and 54C may be approximately 80% (±5%), approximately 50% (±5%), and approximately 20% (±5%), respectively.

[0035] The third AlGaN layer 54C has a different Al composition from the second AlGaN layer 54B (a lower Al composition than the second AlGaN layer 54B in the example of FIG. 2 ), and is therefore grown in a strained state with respect to the lattice constant of the second AlGaN layer 54B. The thickness of the third AlGaN layer 54C is greater than the thickness of the second AlGaN layer 54B. This promotes lattice relaxation (dislocations) in the third AlGaN layer 54C to relieve internal stress (distortion due to lattice mismatch) accumulated as strain in the third AlGaN layer 54C. As a result, the density of crystal defects due to lattice relaxation increases. Therefore, in some embodiments, in order to increase the crystal defect density of the buffer layer 14 (and thereby increase the crystal defect density of the first nitride semiconductor layer 16), for example, the third AlGaN layer 54C is configured to have a lower Al composition and a greater thickness than the second AlGaN layer 54B. Alternatively, in order to increase the crystal defect density of the buffer layer 14, the number of AlGaN layers forming the second buffer layer 54 and the thickness of each layer are adjusted.

[0036] The buffer layer 14 may contain impurities that form an acceptor level. The impurities in the buffer layer 14 may be, for example, at least one of carbon (C) and iron (Fe). The concentration of the impurities may be, for example, 4×10 １６ cm －３ The above configuration is possible. In some embodiments, by introducing such impurities into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating, leakage current in the buffer layer 14 can be suppressed and the breakdown voltage can be improved. For example, in the second buffer layer 54, the impurity may be introduced only into the third AlGaN layer 54C, or only into the second and third AlGaN layers 54B, 54C. Alternatively, the impurity may be introduced into all of the first to third AlGaN layers 54A, 54B, 54C of the second buffer layer 54. Of the first to third AlGaN layers 54A to 54C, the layers doped with impurities that form acceptor levels correspond to impurity-doped AlGaN layers.

[0037] [4-2. First Nitride Semiconductor Layer] Next, an exemplary structure of the first nitride semiconductor layer 16 will be described. As described above, the first nitride semiconductor layer 16 may include a GaN composite layer in which a plurality of GaN layers are stacked. In some embodiments, the GaN composite layer may be formed by alternately stacking impurity-doped GaN layers, which are doped with impurities that form acceptor levels, and undoped GaN layers one or more times. The uppermost layer of the GaN composite layer is an undoped GaN layer. Note that the term "undoped GaN layer" used in this disclosure is defined as a GaN layer to which no impurities are intentionally introduced.

[0038] In the GaN composite layer, the impurity in the impurity-doped GaN layer may be, for example, carbon (C). The concentration of the impurity in the impurity-doped GaN layer is 5×10 １７ cm －３ 5x10 or more １９ cm －３ In some embodiments, by introducing such impurities into a part of the first nitride semiconductor layer 16 to make at least a part of the first nitride semiconductor layer 16 semi-insulating other than the surface region thereof, it is possible to suppress leakage current in the first nitride semiconductor layer 16 and improve the breakdown voltage.

[0039] In the example of FIG. 2 , the first nitride semiconductor layer 16 is formed as a three-layer GaN composite layer in which three GaN layers, namely, a first GaN layer 62, a second GaN layer 64, and a third GaN layer 66, are stacked in this order. The first GaN layer 62 is an undoped GaN layer, the second GaN layer 64 is an impurity-doped GaN layer, and the third GaN layer 66 is an undoped GaN layer. The 2DEG 20 (see FIG. 1 ), which serves as the channel of the HEMT, is formed in the third GaN layer 66, which is located on the top layer of the GaN composite layer (first nitride semiconductor layer 16). The third GaN layer 66, in which the 2DEG 20 is generated, is also functionally referred to as an electron transit layer.

[0040] The first to third GaN layers 62, 64, 66 may have the same thickness or different thicknesses. The thickness of the first GaN layer 62 may be, for example, 50 nm to 300 nm, and the thickness of the second GaN layer 64 may be, for example, 300 nm to 600 nm. The thickness of the third GaN layer 66 may be, for example, 200 nm to 500 nm. The thickness of the GaN composite layer, i.e., the entire first nitride semiconductor layer 16, may be, as described above, for example, 0.5 μm to 2 μm.

[0041] In some embodiments, the number and thickness of one or more impurity-doped GaN layers (second GaN layer 64 in the example of FIG. 2 ) and / or the number and thickness of one or more undoped GaN layers (first GaN layer 62 and third GaN layer 66 in the example of FIG. 2 ) are adjusted to increase the crystal defect density of first nitride semiconductor layer 16. Crystal defects are formed as multiple dislocations (threading dislocations) that extend linearly in the stacking direction through both the impurity-doped GaN layer and the undoped GaN layer. These multiple dislocations tend to be bonded to each other and reduced as they propagate through the undoped GaN layer located on the impurity-doped GaN layer (or the impurity-doped AlGaN layer of buffer layer 14). Therefore, for example, by thinning the undoped GaN layer formed on the impurity-doped GaN layer (or the impurity-doped AlGaN layer of the buffer layer 14), it is possible to suppress a decrease in dislocations in the undoped GaN layer and maintain the crystal defect density of the first nitride semiconductor layer 16. The significance of controlling the crystal defect density of the first nitride semiconductor layer 16 will be described later.

[0042] 2, the second nitride semiconductor layer 18 is an AlGaN layer, and the gate layer 30 is a p-type GaN layer. The second nitride semiconductor layer 18 is also functionally referred to as an electron supply layer for the electron transit layer (third GaN layer 66) of the first nitride semiconductor layer 16. By providing the p-type GaN layer as the gate layer 30, the nitride semiconductor device 10 is configured as a normally-off HEMT as described above.

[0043] 3 to 6, acceptor compensation by controlling the crystal defect density will be described. In the nitride semiconductor device 10 configured as a HEMT, electron traps at deep acceptor levels in the crystal of the first nitride semiconductor layer 16 or the buffer layer 14 cause an increase in on-resistance.

[0044] Specifically, when electrons are trapped in the acceptor levels in the crystal, the carrier (electron) concentration of the 2DEG 20 generated in the first nitride semiconductor layer 16 (the electron supply layer formed by the third GaN layer 66 in the example of FIG. 2 ) decreases. This increases the channel potential, thereby increasing the on-resistance. In particular, electrons trapped in the deep acceptor levels in the crystal are not easily released, so the on-resistance can remain high. Such deep acceptor levels can be formed, for example, by implanting impurities into the first nitride semiconductor layer 16 and / or the buffer layer 14.

[0045] In order to suppress an increase in on-resistance by compensating for acceptors that cause the above-described electron traps, the first nitride semiconductor layer 16 is configured to maintain its crystal defect density within a predetermined range. Crystal defects caused by crystal distortion contribute to the formation of donor levels. From this perspective, the crystal defect density in the crystal of the first nitride semiconductor layer 16 and / or the crystal of the buffer layer 14 is controlled to form donor levels that compensate for the acceptors.

[0046] Here, X-ray rocking curve (XRC) measurement is generally used to evaluate the crystal defect density. The half-width of the XRC is used as an index value that quantifies the distortion of the crystal, and therefore has a correlation with the crystal defect density. More precisely, the half-width is the full width at half maximum (FWHM), but hereinafter it will be simply referred to as the half-width.

[0047] In some embodiments, the crystal defect density of the first nitride semiconductor layer 16 is controlled so that the XRC half-width for the (102) plane of the first nitride semiconductor layer 16 is 1100 arcsec or more and 1400 arcsec or less. Hereinafter, for simplicity, the "XRC half-width for the (102) plane" of the first nitride semiconductor layer 16 may be simply referred to as the "(102) half-width." By maintaining the (102) half-width within this range, the donor level caused by the crystal defects can compensate for the acceptors, thereby suppressing an increase in on-resistance. The relationship between the (102) half-width and the on-resistance variation rate will be described later.

[0048] Fig. 3 is a diagram schematically showing the (102) plane of the first nitride semiconductor layer 16. The (102) plane of the first nitride semiconductor layer 16 is a crystal plane with Miller indices (102) in a hexagonal crystal that is a unit lattice of GaN that forms the first nitride semiconductor layer 16, and corresponds to the crystal plane M102 of the hexagonal HC shown in Fig. 3. The X-ray rocking curve for the (102) plane refers to a rocking curve obtained by X-ray diffraction for the (102) plane.

[0049] Here, types of crystal defects (dislocations) include screw dislocations and edge dislocations, which are lattice misalignments formed in the stacking direction of a crystal stacking structure. Screw dislocations are dislocations formed at an angle with respect to the direction perpendicular to the stacking plane of the crystal stacking structure, and are formed specifically by tilting the crystal axis of the crystal growth direction. Edge dislocations are dislocations formed in the direction perpendicular to the stacking plane of the crystal stacking structure, and are formed specifically by twisting the crystal axis within the plane.

[0050] Fig. 4 is a diagram schematically showing a screw dislocation, and Fig. 5 is a diagram schematically showing an edge dislocation. Fig. 4 and Fig. 5 show only one layer in a hexagonal crystal system having a crystal stacking structure in the X-axis direction, with Fig. 4 being a front view of a portion of the crystal structure and Fig. 5 being a plan view of the crystal structure of Fig. 4.

[0051] As shown in Fig. 4, screw dislocations are formed by a tilt of the c-axis C2 of the hexagonal crystal HC2 with respect to the c-axis C1 of the hexagonal crystal HC1 (and the c-axis C4 of the hexagonal crystal HC4 in Fig. 5). As shown in Fig. 5, this tilt of the c-axis C2 causes a lattice misalignment D1 between the hexagonal crystal HC2 and the hexagonal crystals HC1 and HC4, which is inclined with respect to the direction perpendicular to the stacking plane of the crystal stacking structure (Z-axis direction). This lattice misalignment D1 is carried over in the thickness direction (X-axis direction) of the first nitride semiconductor layer 16, resulting in the formation of crystal defects (threading dislocations) caused by the screw dislocations.

[0052] 5, edge dislocations are formed by twisting around the c-axis C3 of the hexagonal crystal HC3. This twisting around the c-axis C3 causes a lattice misalignment D2 along the direction perpendicular to the stacking plane of the crystal stacking structure (the Z-axis direction) between the hexagonal crystal HC3 and the hexagonal crystals HC1 and HC4. This lattice misalignment D2 is carried over into the thickness direction (the X-axis direction) of the first nitride semiconductor layer 16, resulting in the formation of crystal defects (threading dislocations) caused by the edge dislocations.

[0053] The XRC half-width for the (102) plane of the first nitride semiconductor layer 16 is an index value that reflects both of these lattice misalignments D1 and D2, i.e., both of the crystal defects caused by screw dislocations and the crystal defects caused by edge dislocations.

[0054] 6 is a graph showing the relationship between the XRC half-width for the (102) plane of the first nitride semiconductor layer 16 and the on-resistance variation ΔRon, measured for various nitride semiconductor devices 10 including first nitride semiconductor layers 16 with different crystal defect densities. The on-resistance variation ΔRon is derived by measuring the on-resistance of the nitride semiconductor device 10 before and after a high-temperature reverse bias (HTRB) test is performed on the target nitride semiconductor device 10. The HTRB test is performed by applying a stress voltage (e.g., 80% of the rated voltage (e.g., 150 V)) to the drain electrode 26 of the HEMT in the off state in a high-temperature (e.g., approximately 150° C.) environment for a predetermined time (e.g., 60 hours or more).

[0055] As shown in Fig. 6, the on-resistance variation rate ΔRon varies depending on the XRC half-width for the (102) plane of the first nitride semiconductor layer 16. As the (102) half-width increases, that is, as the crystal defect density of the first nitride semiconductor layer 16 increases, the on-resistance variation rate ΔRon decreases. In some embodiments, the allowable range of the on-resistance variation rate ΔRon is set to 40% or less. In Fig. 6, the (102) half-width that satisfies this allowable range is not less than 1100 arcsec and not more than 1250 arcsec.

[0056] 6 , even if the (102) half-width is 1250 arcsec or more, the on-resistance variation rate ΔRon decreases as the (102) half-width increases. However, if excessive donor levels are formed in the crystal of first nitride semiconductor layer 16 or buffer layer 14 due to the introduction of a large number of crystal defects, the breakdown voltage of first nitride semiconductor layer 16 may decrease due to leakage current via the crystal defects (threading dislocations). In consideration of this point, the (102) half-width is set to be 1100 arcsec or more and 1400 arcsec or less.

[0057] [6. Operation of the Nitride Semiconductor Device] When a drain voltage is applied to the drain electrode 26 of the nitride semiconductor device 10 configured as a HEMT, electrons are trapped in acceptor levels present in the crystal of the first nitride semiconductor layer 16 or the buffer layer 14. These electron traps cause an increase in on-resistance. Therefore, the first nitride semiconductor layer 16 is configured to have a crystal defect density sufficient to provide a donor level that compensates for the acceptors. Specifically, the crystal defect density of the first nitride semiconductor layer 16 is controlled so that the (102) half-width of the first nitride semiconductor layer 16, which is an index representing the crystal defect density, is 1100 arcsec or more and 1400 arcsec or less.

[0058] The first nitride semiconductor layer 16 may include a GaN composite layer in which one or more undoped GaN layers and one or more impurity-doped GaN layers are alternately stacked. In such a GaN composite layer, the crystal defect density of the first nitride semiconductor layer 16 can be controlled by adjusting the number and thickness of the undoped GaN layers and / or the number and thickness of the impurity-doped GaN layers.

[0059] 2 , the first nitride semiconductor layer 16 includes a GaN composite layer formed by stacking a first GaN layer 62 (undoped GaN layer), a second GaN layer 64 (impurity-doped GaN layer), and a third GaN layer 66 (undoped GaN layer). The thickness of the first GaN layer 62 is, for example, 50 nm to 300 nm, the thickness of the second GaN layer 64 is, for example, 300 nm to 600 nm, and the thickness of the third GaN layer 66 is, for example, 200 nm to 500 nm.

[0060] Additionally or alternatively, the buffer layer 14 may include an AlGaN composite layer in which multiple AlGaN layers are stacked. In such an AlGaN composite layer, the crystal defect density of the buffer layer 14 can be controlled by adjusting the number of AlGaN layers, the thickness of each layer, and / or the Al composition ratio in each AlGaN layer. This allows the crystal defect density of the first nitride semiconductor layer 16 formed on the buffer layer 14 to be controlled.

[0061] 2, the buffer layer 14 includes a first buffer layer 52 formed of an AlN layer and a second buffer layer 54 formed of an AlGaN composite layer in which first to third AlGaN layers 54A, 54B, and 54C are stacked. The thickness of each of the first to third AlGaN layers 54A, 54B, and 54C is, for example, 100 nm to 300 nm. In this case, the thickness of the third AlGaN layer 54C may be, for example, twice the thickness of the second AlGaN layer 54B or more, for example, 200 nm or more. The Al composition ratios of the first to third AlGaN layers 54A, 54B, and 54C are approximately 80% (±5%), approximately 50% (±5%), and approximately 20% (±5%), respectively.

[0062] 2 , the third AlGaN layer 54C of the second buffer layer 54 (AlGaN composite layer) has a lower Al composition and a greater thickness than the second AlGaN layer 54B. This promotes the occurrence of lattice relaxation (dislocations) in the third AlGaN layer 54C, thereby increasing the density of crystal defects caused by lattice relaxation. As a result, the crystal defect density of the first nitride semiconductor layer 16 formed on the buffer layer 14 can be increased. In this way, by controlling the crystal defect density of the buffer layer 14, the crystal defect density of the first nitride semiconductor layer 16 can be controlled.

[0063] The nitride semiconductor device 10 of one embodiment has the following advantages. (1) The nitride semiconductor device 10 is configured so that the full width at half maximum of the XRC for the (102) plane of the first nitride semiconductor layer 16 is 1100 arcsec or more and 1400 arcsec or less. This configuration makes it possible to maintain the crystal defect density of the first nitride semiconductor layer 16 at a level sufficient to provide a donor level that compensates for acceptors that cause electron traps. This makes it possible to suppress a decrease in the carrier (electron) concentration of the 2DEG 20 generated in the first nitride semiconductor layer 16 and thereby suppress an increase in on-resistance.

[0064] (2) The half-width of the XRC for the (102) plane of the first nitride semiconductor layer 16 represents an index of the crystal defect density that reflects both crystal defects caused by edge dislocations and crystal defects caused by screw dislocations, thereby enabling precise control of the crystal defect density of the first nitride semiconductor layer 16.

[0065] (3) The first nitride semiconductor layer 16 includes a GaN composite layer in which first to third GaN layers 62, 64, and 66 are stacked. The first and third GaN layers 62, 66 are each undoped GaN layers, and the second GaN layer 64 is an impurity-doped GaN layer doped with carbon (C) as an impurity. In this configuration, the crystal defect density of the first nitride semiconductor layer 16 can be controlled by adjusting the thickness of each of the first to third GaN layers 62, 64, and 66. Furthermore, since the first nitride semiconductor layer 16 includes the impurity-doped GaN layer (second GaN layer 64), leakage current in the first nitride semiconductor layer 16 can be suppressed, thereby improving the breakdown voltage.

[0066] (4) The buffer layer 14 includes an AlGaN composite layer (second buffer layer 14) in which first to third AlGaN layers 54A, 54B, and 54C are stacked. The third AlGaN layer 54C is located at the top of the AlGaN composite layer and has a lower Al composition and a greater thickness than the second AlGaN layer 54B located immediately below it. For example, in this configuration, the crystal defect density of the buffer layer 14 can be controlled by adjusting the thickness and / or Al composition ratio of each of the first to third AlGaN layers 54A, 54B, and 54C. This allows the crystal defect density of the first nitride semiconductor layer 16 formed on the buffer layer 14 to be controlled.

[0067] (5) In the buffer layer 14, at least one of the first to third AlGaN layers 54A, 54B, 54C is an impurity-doped AlGaN layer doped with at least one of carbon (C) and iron (Fe) as an impurity. With this configuration, the buffer layer 14 includes an impurity-doped AlGaN layer, which can suppress leakage current in the buffer layer 14 and improve the breakdown voltage.

[0068] (6) In the nitride semiconductor device 10, the gate structure 22 includes a gate layer 30 formed on the second nitride semiconductor layer 18 and a gate electrode 32 formed on the gate layer 30. The gate layer 30 is formed of a GaN layer containing acceptor-type impurities, i.e., a p-type GaN layer. By providing such a gate layer 30, the nitride semiconductor device 10 can be configured as a normally-off type HEMT.

[0069] [Modifications] The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0070] The nitride semiconductor device 10 is not limited to the structure of the above embodiment described with reference to Fig. 1. For example, the nitride semiconductor device 10 of the above embodiment is configured as a normally-off type HEMT, but the configuration of the present disclosure is not limited to normally-off type HEMTs and can also be applied to normally-on type HEMTs. For example, the nitride semiconductor device 10 can be configured as a normally-on type HEMT by omitting the gate layer 30 from the nitride semiconductor device 10 (or by forming the gate layer 30 as a nitride semiconductor layer that does not contain acceptor-type impurities).

[0071] The first nitride semiconductor layer 16 is not limited to the structure of the embodiment described with reference to FIG. 2 . The first nitride semiconductor layer 16 may be any layer containing GaN, and is not necessarily limited to a structure containing a GaN composite layer. Of course, the number of layers and the structure of the GaN composite layer are not particularly limited. For example, the first nitride semiconductor layer 16 may include another nitride semiconductor layer (e.g., an AlN layer) in addition to the GaN layer, and the crystal defect density of the first nitride semiconductor layer 16 may be adjusted by another layer structure.

[0072] The buffer layer 14 is not limited to the structure of the embodiment described above with reference to Fig. 2, and may include other nitride semiconductor layers. Of course, the number of layers and the structure of the AlGaN composite layer are not particularly limited.

[0073] The gate layer 30 is not limited to a structure including the source-side extension 36 and the drain-side extension 38, but may be a structure including only the gate layer main body 34. In addition, the structures and shapes of the source electrode 24 and the drain electrode 26 are not limited to those shown in FIG.

[0074] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the phrase "a first element is mounted on a second element" is intended to mean that in some embodiments, the first element may be placed directly on the second element in contact with the second element, while in other embodiments, the first element may be placed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0075] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0076] The numerals such as "first", "second", etc. used in this disclosure are used simply to clearly distinguish between components, and do not necessarily require that the components be provided in the specified order.

[0077] [Notes] The technical ideas that can be understood from the above-described embodiments and modifications are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each note should not be limited to the components indicated by the reference numerals.

[0078] (Appendix A1) A nitride semiconductor device (10) comprising: a first nitride semiconductor layer (16); a second nitride semiconductor layer (18) formed on the first nitride semiconductor layer (16) and having a band gap larger than that of the first nitride semiconductor layer (16); and a gate electrode (32), a source electrode (24), and a drain electrode (26) formed above the second nitride semiconductor layer (18), wherein the first nitride semiconductor layer (16) is a layer containing GaN, and a full width at half maximum of an X-ray rocking curve for a (102) plane of the first nitride semiconductor layer (16) is not less than 1100 arcsec and not more than 1400 arcsec.

[0079] (Appendix A2) The nitride semiconductor device (10) according to Appendix A1, wherein the first nitride semiconductor layer (16) includes a GaN composite layer in which a plurality of GaN layers (62, 64, 66) are stacked, the GaN composite layer being formed by alternately stacking impurity-doped GaN layers (64) doped with impurities that form acceptor levels and undoped GaN layers (62; 66), the uppermost layer of the GaN composite layer being formed by the undoped GaN layer (66), and the second nitride semiconductor layer (18) being formed on the undoped GaN layer (66) located in the uppermost layer of the GaN composite layer.

[0080] (Appendix A3) The nitride semiconductor device (10) according to Appendix A2, further comprising: a semiconductor substrate (12); and a buffer layer (14) formed on the semiconductor substrate (12); wherein the GaN composite layer has a three-layer structure of a first GaN layer (62) located on the buffer layer (14), a second GaN layer (64) located on the first GaN layer (62), and a third GaN layer (66) located on the second GaN layer (64); wherein the first GaN layer (62) and the third GaN layer (66) are each formed of the non-doped GaN layer; the second GaN layer (64) is formed of the impurity-doped GaN layer; and the second nitride semiconductor layer (18) is formed on the third GaN layer (66).

[0081] (Appendix A4) The nitride semiconductor device (10) according to Appendix A3, wherein the first GaN layer (62) has a thickness of 50 nm or more and 300 nm or less.

[0082] (Appendix A5) The nitride semiconductor device (10) according to any one of Appendices A2 to A4, wherein the impurity in the impurity-doped GaN layer (64) is carbon (C).

[0083] (Appendix A6) The nitride semiconductor device (10) according to Appendix A1, further comprising: a semiconductor substrate (12); and a buffer layer (14) formed on the semiconductor substrate (12), wherein the first nitride semiconductor layer (16) is formed on the buffer layer (14), and the buffer layer (14) includes an AlGaN composite layer (54) in which a plurality of AlGaN layers (54A, 54B, 54C) are stacked, and the uppermost AlGaN layer (54C) of the plurality of AlGaN layers (54A, 54B, 54C) has a lower aluminum composition and a greater thickness than an AlGaN layer (54B) located immediately below the uppermost AlGaN layer (54C).

[0084] (Appendix A7) The nitride semiconductor device (10) according to Appendix A6, wherein at least one of the plurality of AlGaN layers (54A, 54B, 54C) is an impurity-doped AlGaN layer (54A; 54B; 54C) doped with an impurity that forms an acceptor level.

[0085] (Appendix A8) The nitride semiconductor device (10) according to Appendix A7, wherein the impurity in the impurity-doped AlGaN layer (54A; 54B; 54C) is at least one of carbon (C) and iron (Fe).

[0086] (Appendix A9) The nitride semiconductor device (10) according to any one of Appendices A6 to A8, wherein the first nitride semiconductor layer (16) includes a GaN composite layer in which a plurality of GaN layers (62, 64, 66) are stacked, and the plurality of GaN layers (62, 64, 66) include: a first GaN layer (62) located on the AlGaN composite layer (54) and formed of an undoped GaN layer; a second GaN layer (64) located on the first GaN layer (62) and formed of an impurity-doped GaN layer doped with an impurity that forms an acceptor level; and a third GaN layer (66) located on the second GaN layer (64) and formed of an undoped GaN layer, and the second nitride semiconductor layer (18) is formed on the third GaN layer (66).

[0087] (Appendix A10) The nitride semiconductor device (10) according to any one of Appendices A1 to A9, further comprising a third nitride semiconductor layer (30) formed on the second nitride semiconductor layer (18) and containing an acceptor-type impurity, and the gate electrode (32) is formed on the third nitride semiconductor layer (30).

[0088] (Appendix B1) A semiconductor device comprising: a semiconductor substrate (12); a buffer layer (14) formed on the semiconductor substrate (12); a first nitride semiconductor layer (16) formed on the buffer layer (14); a second nitride semiconductor layer (18) formed on the first nitride semiconductor layer (16) and having a band gap larger than that of the first nitride semiconductor layer (16); and a gate electrode (32), a source electrode (24), and a drain electrode (26) formed above the second nitride semiconductor layer (18), wherein the buffer layer (14) includes an AlGaN composite layer (54) in which a plurality of AlGaN layers (54A, 54B, 54C) are stacked; and the first nitride semiconductor layer (16) includes a GaN composite layer in which a plurality of GaN layers (62, 64, 66) are stacked. the GaN composite layer is formed by alternately stacking impurity-doped GaN layers (64) doped with impurities that form acceptor levels and undoped GaN layers (62; 66), an uppermost layer of the GaN composite layer is formed by the undoped GaN layer (66), the second nitride semiconductor layer (18) is formed on the undoped GaN layer (66) located at the uppermost layer of the GaN composite layer, and the uppermost AlGaN layer (54C) of the plurality of AlGaN layers (54A, 54B, 54C) has a lower aluminum composition and a greater thickness than an AlGaN layer (54B) located immediately below the uppermost AlGaN layer (54C).

[0089] (Appendix B2) The nitride semiconductor device (10) according to Appendix B1, wherein the GaN composite layer has a three-layer structure of a first GaN layer (62) located on the buffer layer (14), a second GaN layer (64) located on the first GaN layer (62), and a third GaN layer (66) located on the second GaN layer (64), wherein the first GaN layer (62) and the third GaN layer (66) are each formed of the non-doped GaN layer, the second GaN layer (64) is formed of the impurity-doped GaN layer, and the second nitride semiconductor layer (18) is formed on the third GaN layer (66).

[0090] (Appendix B3) The nitride semiconductor device (10) according to Appendix B1 or B2, wherein at least one of the plurality of AlGaN layers (54A, 54B, 54C) is an impurity-doped AlGaN layer (54A; 54B; 54C) doped with an impurity that forms an acceptor level.

[0091] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0092] REFERENCE SIGNS LIST 10...Nitride semiconductor device 12...Semiconductor substrate 14...Buffer layer 16...First nitride semiconductor layer 18...Second nitride semiconductor layer 20...Two-dimensional electron gas (2DEG) 22...Gate structure 24...Source electrode 26...Drain electrode 30...Gate layer (third nitride semiconductor layer) 32...Gate electrode 52...First buffer layer 54...Second buffer layer (AlGaN composite layer) 54A...First AlGaN layer 54B...Second AlGaN layer 54C...Third AlGaN layer 62...First GaN layer 64...Second GaN layer 66...Third GaN layer

Claims

1. A first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a gate electrode, a source electrode, and a drain electrode formed above the second nitride semiconductor layer; the first nitride semiconductor layer is a layer containing GaN, a half-width of an X-ray rocking curve for a (102) plane of the first nitride semiconductor layer is not less than 1100 arcsec and not more than 1400 arcsec.

2. The first nitride semiconductor layer includes a GaN composite layer in which a plurality of GaN layers are stacked, The GaN composite layer is formed by alternately stacking impurity-doped GaN layers doped with impurities that form an acceptor level and non-doped GaN layers, the uppermost layer of the GaN composite layer is formed by the non-doped GaN layer; The nitride semiconductor device according to claim 1 , wherein said second nitride semiconductor layer is formed on said undoped GaN layer located at said uppermost layer of said GaN composite layer.

3. Further comprising a semiconductor substrate and a buffer layer formed on the semiconductor substrate; the GaN composite layer has a three-layer structure including a first GaN layer located on the buffer layer, a second GaN layer located on the first GaN layer, and a third GaN layer located on the second GaN layer; the first GaN layer and the third GaN layer are each formed of the non-doped GaN layer; the second GaN layer is formed by the impurity-doped GaN layer; The nitride semiconductor device according to claim 2 , wherein said second nitride semiconductor layer is formed on said third GaN layer.

4. The nitride semiconductor device according to claim 3 , wherein the first GaN layer has a thickness of not less than 50 nm and not more than 300 nm.

5. The nitride semiconductor device according to claim 2 , wherein the impurity in said impurity-doped GaN layer is carbon (C).

6. Further comprising a semiconductor substrate and a buffer layer formed on the semiconductor substrate; the first nitride semiconductor layer is formed on the buffer layer; the buffer layer includes an AlGaN composite layer in which a plurality of AlGaN layers are stacked; 2 . The nitride semiconductor device according to claim 1 , wherein an uppermost AlGaN layer of said plurality of AlGaN layers has a lower aluminum composition and a greater thickness than an AlGaN layer located immediately below said uppermost AlGaN layer.

7. The nitride semiconductor device according to claim 6 , wherein at least one of said plurality of AlGaN layers is an impurity-doped AlGaN layer doped with an impurity that forms an acceptor level.

8. 8. The nitride semiconductor device according to claim 7, wherein the impurity in said impurity-doped AlGaN layer is at least one of carbon (C) and iron (Fe).

9. The first nitride semiconductor layer includes a GaN composite layer in which a plurality of GaN layers are stacked, The plurality of GaN layers are a first GaN layer located on the AlGaN composite layer and formed of a non-doped GaN layer; a second GaN layer located on the first GaN layer and formed of an impurity-doped GaN layer doped with an impurity that forms an acceptor level; a third GaN layer located on the second GaN layer and formed of a non-doped GaN layer; The nitride semiconductor device according to claim 6 , wherein said second nitride semiconductor layer is formed on said third GaN layer.

10. A third nitride semiconductor layer is formed on the second nitride semiconductor layer and contains an acceptor-type impurity.

10. The nitride semiconductor device according to claim 1, wherein said gate electrode is formed on said third nitride semiconductor layer.