Semiconductor device

Abstract

This semiconductor device includes: a chip that has a main surface; a trench electrode-type resistive structure that is formed on the main surface; and a resistive film that covers the resistive structure as a single coating target and is electrically connected to the resistive structure.

Description

Semiconductor Devices

[0001] This application claims priority to Japanese Patent Application No. 2022-178809 filed with the Japan Patent Office on November 8, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2020 / 0294989A1) discloses a semiconductor device including a semiconductor substrate, a MOS gate, a p-type region, an interlayer insulating film, a gate polysilicon layer, a gate pad, and a contact electrode. The MOS gate includes multiple gate electrodes embedded in multiple trenches formed in the semiconductor substrate. The p-type region is formed in a surface layer of the semiconductor substrate at a distance from the MOS gate. An interlayer insulating film covers the MOS gate and the p-type region on the semiconductor substrate.

[0003] The gate polysilicon layer is provided as a gate resistor. The gate polysilicon layer is disposed on a portion of the interlayer insulating film covering the p-type region at a distance from the MOS gate and faces the p-type region across the interlayer insulating film. The gate pad is disposed on the gate polysilicon layer and electrically connected to the gate polysilicon layer. The contact electrode is disposed on the gate polysilicon layer at a distance from the gate pad and electrically connected to the gate polysilicon layer.

[0004] US Patent Application Publication No. 2020 / 0294989

[0005] SUMMARY The present disclosure provides a semiconductor device having a novel layout associated with a resistor.

[0006] The present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type resistance structure formed on the main surface, and a resistance film that covers the resistance structure as a single coverage object and is electrically connected to the resistance structure.

[0007] The present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type resistance structure formed on the main surface, and a trench electrode type electrode structure formed on the main surface adjacent to the resistance structure and applied with a potential different from that of the resistance structure.

[0008] The present disclosure provides a semiconductor device including: a chip having a main surface; a trench electrode type resistance structure formed on the main surface; a trench electrode type first electrode structure formed on the main surface at a distance from the resistance structure in one direction and to which a potential different from that of the resistance structure is applied; and a trench electrode type second electrode structure formed on the main surface at a distance from the resistance structure in an orthogonal direction perpendicular to the one direction and to which a potential different from that of the resistance structure is applied.

[0009] The present disclosure provides a semiconductor device including a chip having a main surface, a first surface portion located inside the main surface, a second surface portion recessed in the thickness direction outside the first surface portion, and a mesa portion defined on the main surface by a connection surface portion connecting the first surface portion and the second surface portion, and a resistive film arranged on the first surface portion.

[0010] The present disclosure provides a semiconductor device including a chip having a main surface, a first surface portion located inside the main surface, a second surface portion recessed in the thickness direction outside the first surface portion, and a mesa portion defined on the main surface by a connection surface portion connecting the first surface portion and the second surface portion, and a trench electrode type resistor structure formed on the first surface portion.

[0011] The present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type resistor structure formed on the main surface, and a trench electrode type gate structure formed on the main surface adjacent to the resistor structure.

[0012] The present disclosure provides a semiconductor device including a chip having a main surface, a trench electrode type gate structure formed on the main surface, and a resistive film arranged on the main surface adjacent to the gate structure and spaced apart from the gate structure.

[0013] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0014] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing an example layout of an active region. FIG. 5 is an enlarged plan view showing an example layout of a first side end region. FIG. 6 is an enlarged plan view showing an example layout of a first termination region. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 5 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 5 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5 . FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 6 . FIG. 14 is a plan view showing an example layout of a gate electrode and a source electrode. FIG. 15 is an enlarged plan view showing a main portion of FIG. 14 . 16 is a plan view further enlarged of a main portion of FIG. 15 . FIG. 17 is an enlarged plan view showing a resistor region according to a first layout example. FIG. 18 is an enlarged plan view showing an example layout of an inner portion of the resistor region. FIG. 19 is an enlarged plan view showing an example layout of a peripheral portion of the resistor region. FIG. 20 is an enlarged plan view showing an example layout of a first dummy region. FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG. 18 . FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. 18 . FIG. 23 is a cross-sectional view taken along line XXIII-XXIII shown in FIG. 18 . FIG. 24 is a cross-sectional view taken along line XXIV-XXIV shown in FIG. 19 . FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 19 . FIG. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. 20 . FIG. 27 is a cross-sectional view taken along line XXVII-XXVII shown in FIG. 20 . 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in FIG. 20. FIG. 29 is a cross-sectional view showing the structure of the outer periphery region. FIG. 30 is a circuit diagram showing the electrical configuration of the gate resistor. FIG. 31 is an enlarged plan view showing the resistor region according to a second layout example. FIG. 32 is an enlarged plan view showing a layout example of the inner part of the resistor region. FIG. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in FIG. 32. FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in FIG. 32.FIG. 35 is a cross-sectional view taken along line XXXV-XXXV in FIG. 32 . FIG. 36 is an enlarged plan view showing a resistor region according to a third layout example. FIG. 37 is a circuit diagram showing the electrical configuration of a gate resistor. FIG. 38 is an enlarged plan view showing a resistor region according to a fourth layout example. FIG. 39 is an enlarged plan view showing a resistor region according to a fifth layout example. FIG. 40 is a plan view showing an example layout of a first main surface of a semiconductor device according to the second embodiment. FIG. 41 is an enlarged plan view showing a sub-resistor region according to the first layout example together with the resistor region according to the first layout example. FIG. 42 is an enlarged plan view showing an example layout of a peripheral portion of the resistor region. FIG. 43 is an enlarged plan view showing an example layout of a first side end region. FIG. 44 is a cross-sectional view taken along line XLIV-XLIV in FIG. 42 . FIG. 45 is an enlarged plan view showing a sub-resistor region according to the second layout example together with the resistor region according to the second layout example. FIG. 46 is an enlarged plan view showing a sub-resistor region according to the third layout example together with the resistor region according to the third layout example. Fig. 47 is an enlarged plan view showing a sub-resistor region according to a fourth layout example together with a resistor region according to the fourth layout example. Fig. 48 is an enlarged plan view showing a sub-resistor region according to a fifth layout example together with a resistor region according to the fifth layout example. Fig. 49 is a cross-sectional view showing another example of a chip. Fig. 50 is a cross-sectional view showing another example of a chip.

[0015] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0016] When the term "substantially equal" is used in a description in which a comparison target is present, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0017] In the following description, the conductivity type of a semiconductor region (impurity region) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." The "p-type" is a conductivity type resulting from a trivalent element, and the "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0018] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. The semiconductor device 1A is a semiconductor switching device including an insulated gate transistor structure. The transistor structure may be referred to as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure.

[0019] 1 to 3, in this embodiment, semiconductor device 1A includes chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be called a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0020] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0021] The semiconductor device 1A may be referred to as a "SiC-MISFET." Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0022] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of a SiC single crystal.

[0023] In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be more than 0° and not more than 10°. The off angle is preferably not more than 5°.

[0024] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0025] Hereinafter, the third side surface 5C side in the first direction X may be referred to as one side of the first direction X, and the fourth side surface 5D side in the first direction X may be referred to as the other side of the first direction X. The first side surface 5A side in the second direction Y may be referred to as one side of the second direction Y, and the second side surface 5B side in the second direction Y may be referred to as the other side of the second direction Y.

[0026] The chip 2 may have a thickness of 5 μm or more and 200 μm or less. The thickness of the chip 2 may be set to a value belonging to any one of the following ranges: 5 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 125 μm or less, 125 μm or more and 150 μm or less, 150 μm or more and 175 μm or less, and 175 μm or more and 200 μm or less. The thickness of the chip 2 is preferably 100 μm or less.

[0027] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may be set to a value belonging to any one of the ranges of 0.5 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D are preferably 5 mm or more.

[0028] The semiconductor device 1A includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2. A drain potential as a high potential (first potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "drain region," a "drift region," or the like. The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0029] In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer). The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less. The thickness of the first semiconductor region 6 is preferably 3 μm or more and 30 μm or less. The thickness of the first semiconductor region 6 is particularly preferably 5 μm or more and 25 μm or less.

[0030] The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as a "drain region." The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 within the chip 2. The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0031] In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC semiconductor substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 may have a thickness of 1 μm or more and 200 μm or less. The thickness of the second semiconductor region 7 may be 150 μm or less, 100 μm or less, 50 μm or less, or 40 μm or less. The thickness of the second semiconductor region 7 may be 5 μm or more. The thickness of the second semiconductor region 7 is preferably 10 μm or more. In this embodiment, the thickness of the second semiconductor region 7 is greater than the thickness of the first semiconductor region 6.

[0032] The semiconductor device 1A includes an active surface 8, an outer surface 9, and first to fourth connecting surfaces 10A to 10D formed on the first main surface 3. The active surface 8, the outer surface 9, and the first to fourth connecting surfaces 10A to 10D define an active plateau 11 on the first main surface 3.

[0033] The active surface 8 may be referred to as the “first surface portion,” the outer peripheral surface 9 may be referred to as the “second surface portion,” the first to fourth connecting surfaces 10A to 10D may be referred to as “connecting surface portions,” and the active plateau 11 may be referred to as the “mesa portion.” The active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D (i.e., the active plateau 11) may be considered to be components of the chip 2 (first main surface 3).

[0034] The active surface 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 8 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 8 is formed by the c-plane (Si-plane). In this embodiment, the active surface 8 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0035] The outer peripheral surface 9 is located outside the active surface 8 and is recessed in the thickness direction of the chip 2 (toward the second main surface 4) relative to the active surface 8. Specifically, the outer peripheral surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 so as to expose the first semiconductor region 6. The outer peripheral surface 9 extends in a band shape along the active surface 8 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8.

[0036] The outer peripheral surface 9 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 8. In this embodiment, the outer peripheral surface 9 is formed by the c-plane (Si-plane). The outer peripheral surface 9 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 9 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 5 μm or less. The circumferential depth DO is preferably 2.5 μm or less.

[0037] The first to fourth connection surfaces 10A to 10D extend in the normal direction Z and connect the active surface 8 and the outer peripheral surface 9. The first connection surface 10A is located on the first side surface 5A side, the second connection surface 10B is located on the second side surface 5B side, the third connection surface 10C is located on the third side surface 5C side, and the fourth connection surface 10D is located on the fourth side surface 5D side. The first connection surface 10A and the second connection surface 10B extend in the first direction X and face the second direction Y. The third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face the first direction X.

[0038] The first to fourth connection surfaces 10A to 10D may extend substantially perpendicularly between the active surface 8 and the outer peripheral surface 9 so as to define a quadrangular pillar-shaped active plateau 11. The first to fourth connection surfaces 10A to 10D may be inclined obliquely downward from the active surface 8 toward the outer peripheral surface 9 so as to define a quadrangular pyramid-shaped active plateau 11. In this way, the active plateau 11 is defined in a protruding shape in the first semiconductor region 6 on the first main surface 3. The active plateau 11 is formed only in the first semiconductor region 6, and is not formed in the second semiconductor region 7.

[0039] Referring to Figure 3, the semiconductor device 1A includes, on the first main surface 3, an active region 12, a first side end region 13, a second side end region 14, a first termination region 15, a second termination region 16, a resistance region 17, a first dummy region 18, a second dummy region 19 and a peripheral region 20.

[0040] The active region 12 is a region where the output current (drain current) of the transistor is generated. The active region 12 is provided in the inner part of the active surface 8 and spaced apart from the periphery (first to fourth connecting surfaces 10A to 10D) of the active surface 8. In this embodiment, the active region 12 is provided in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0041] The proportion of the active region 12 in the active surface 8 is preferably 50% or more and 95% or less. The proportion of the active region 12 may be a value belonging to any one of the ranges of 50% or more and 60% or more, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and 95% or less. The proportion of the active region 12 is preferably 70% or more.

[0042] The first side end region 13 is provided as a non-active region on one side (the third connection surface 10C side) in the first direction X with respect to the active region 12 on the active surface 8. The first side end region 13 is provided in a strip shape extending in the second direction Y in a plan view.

[0043] The second side end region 14 is provided as a non-active region on the active surface 8 on the other side in the first direction X (toward the fourth connection surface 10D) of the active region 12, and faces the first side end region 13 across the active region 12 in the first direction X. The second side end region 14 is provided in a strip shape extending in the second direction Y in a plan view.

[0044] The first termination region 15 is provided as an inactive region on one side in the second direction Y (the first connection surface 10A side) of the active region 12. In this embodiment, the first termination region 15 is provided in a strip shape extending in the first direction X in a plan view. The first termination region 15 faces the active region 12, the first side end region 13, and the second side end region 14 in the second direction Y.

[0045] The second termination region 16 is provided as an inactive region on the other side in the second direction Y (the second connection surface 10B side) of the active region 12. In this embodiment, the second termination region 16 is provided in a strip shape extending in the first direction X in a plan view. The second termination region 16 faces the active region 12, the first side end region 13, and the second side end region 14 in the second direction Y.

[0046] Resistance region 17 is provided as an inactive region on one side in the second direction Y (the first connection surface 10A side) of active region 12. Specifically, resistance region 17 is provided in a region between active region 12 and first termination region 15, and faces active region 12 and first termination region 15 in the second direction Y.

[0047] Resistance region 17 is provided in a region on one side in the second direction Y of an imaginary line that crosses the center of active surface 8 in the first direction X in a plan view. Resistance region 17 is located on the imaginary line that crosses the center of active surface 8 in the second direction Y in a plan view. In other words, resistance region 17 faces the center of first side surface 5A (first connecting surface 10A) in the second direction Y in a plan view.

[0048] The resistance region 17 is provided in an inner portion of the active surface 8 at a distance from the periphery of the active surface 8 (the third connecting surface 10C and the fourth connecting surface 10D) in the first direction X. Specifically, the resistance region 17 is provided in an inner portion of the active surface 8 at a distance from both ends of the active region 12 in the first direction X (the first side end region 13 and the second side end region 14), and does not face the first side end region 13 and the second side end region 14 in the second direction Y.

[0049] The resistance region 17 is provided in a strip shape extending in the first direction X in a plan view. The resistance region 17 has a plan area smaller than the plan area of ​​the active region 12. The plan area of ​​the resistance region 17 may be 1 / 10,000 to 1 / 10 of the plan area of ​​the active region 12. The plan area of ​​the resistance region 17 may be 1 / 50 or less of the plan area of ​​the active region 12. The plan area of ​​the resistance region 17 may be 1 / 100 or less of the plan area of ​​the active region 12.

[0050] The proportion of the resistive region 17 in the active surface 8 is preferably more than 0% and not more than 10%. The proportion of the resistive region 17 may be a value belonging to any one of the following ranges: more than 0% and not more than 1%, 1% to 2.5%, 2.5% to 5%, 5% to 7.5%, and 7.5% to 10%. The proportion of the resistive region 17 is preferably 5% or less.

[0051] The first dummy region 18 is provided as an inactive region on one side in the first direction X (the third connection surface 10C side) of the resistance region 17 on the active surface 8. The first dummy region 18 is provided in a strip shape extending in the first direction X in a plan view, and faces the active region 12, the first side end region 13, and the first termination region 15 in the second direction Y.

[0052] The second dummy region 19 is provided as an inactive region on the active surface 8 on the other side in the first direction X (toward the fourth connection surface 10D) of the resistance region 17, and faces the first dummy region 18 across the resistance region 17 in the first direction X. The second dummy region 19 is provided in a strip shape extending in the first direction X in a plan view, and faces the active region 12, the second side end region 14, and the second termination region 16 in the second direction Y.

[0053] The peripheral region 20 is provided on the peripheral surface 9 as an inactive region. In this embodiment, the peripheral region 20 is provided in a ring shape (specifically, a rectangular ring shape) surrounding the active surface 8 (active plateau 11) in a plan view. That is, the peripheral region 20 surrounds the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the resistor region 17, the first dummy region 18, and the second dummy region 19 in a plan view.

[0054] 4 is an enlarged plan view showing an example layout of the active region 12. FIG. 5 is an enlarged plan view showing an example layout of the first side end region 13. FIG. 6 is an enlarged plan view showing an example layout of the first termination region 15.

[0055] Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 4. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 5. Fig. 10 is a cross-sectional view taken along line XX in Fig. 5. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 5. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 5. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 6.

[0056] 4 to 13 mainly show the layout of the third connecting surface 10C (third side surface 5C). The layout of the fourth connecting surface 10D (fourth side surface 5D) is substantially the same as the layout of the third side surface 5C, so the third connecting surface 10C will be mainly described below. The layout of the fourth connecting surface 10D can be obtained by replacing "first side end region 13" with "second side end region 14" and "third connecting surface 10C" with "fourth connecting surface 10D" in the following description.

[0057] 4 to 13, the semiconductor device 1A includes a p-type body region 21 (first impurity region) formed in a surface layer portion of the first main surface 3 (active surface 8). The body region 21 may also be referred to as a "channel region," a "base region," or the like. The body region 21 is formed at an interval from the bottom of the first semiconductor region 6 toward the active surface 8. The body region 21 is formed in a layer shape extending along the active surface 8. The body region 21 is preferably formed over the entire active surface 8 and exposed from the first to fourth connecting surfaces 10A to 10D.

[0058] The semiconductor device 1A includes an n-type source region 22 (second impurity region) formed in a surface layer portion of the body region 21 in the active region 12. The source region 22 is formed at a distance from the bottom of the body region 21 toward the active surface 8. In other words, the source region 22 is formed in a region on the active surface 8 side of the body region 21. The source region 22 has a higher n-type impurity concentration than the first semiconductor region 6. The source region 22 forms a transistor channel together with the first semiconductor region 6 in the body region 21.

[0059] In this embodiment, the source region 22 is not formed in any region other than the active region 12. Of course, the source region 22 may be formed in at least one of the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the resistance region 17, the first dummy region 18, and the second dummy region 19, as long as it does not affect the electrical characteristics of the channel. The source region 22 may be formed over the entire active surface 8.

[0060] The semiconductor device 1A includes a plurality of trench electrode type gate structures 25 formed on the first main surface 3 (active surface 8) in the active region 12. The gate structures 25 may also be referred to as "trench gate structures." A gate potential is applied to the plurality of gate structures 25 as a control potential. The plurality of gate structures 25 controls inversion and non-inversion of the channel in the body region 21 in response to the gate potential.

[0061] The plurality of gate structures 25 are arranged in the active region 12 at intervals inward from the periphery (first to fourth connection surfaces 10A to 10D) of the active surface 8, and define the active region 12 in the inner part of the active surface 8. The plurality of gate structures 25 are each formed in a strip shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y.

[0062] That is, the plurality of gate structures 25 are arranged in a stripe pattern extending in the first direction X in a plan view. The plurality of gate structures 25 penetrate the body region 21 and the source region 22 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0063] Each gate structure 25 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z. The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 2 μm or less. The first depth D1 is less than the aforementioned peripheral depth DO. The first depth D1 may be 0.1 μm or more and 3 μm or less. The first depth D1 is preferably 0.5 μm or more and 1.5 μm or less.

[0064] Each gate structure 25 includes a first trench 26, a first insulating film 27, and a first buried electrode 28. The first trench 26 is formed in the active surface 8 and defines a wall surface of the gate structure 25. The first insulating film 27 covers the wall surface of the first trench 26. The first insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0065] In this embodiment, the first insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 27 includes a silicon oxide film made of an oxide of the chip 2. The first buried electrode 28 is embedded in the first trench 26 across the first insulating film 27 and faces the channel across the first insulating film 27. The first buried electrode 28 may include p-type or n-type conductive polysilicon.

[0066] The semiconductor device 1A includes a plurality of trench electrode type source structures 30 formed on the first main surface 3 (active surface 8) in the active region 12. A source potential as a low potential (a second potential lower than the drain potential) is applied to the plurality of source structures 30. The source structures 30 may also be referred to as "trench source structures," "first source structures," "first trench source structures," or the like.

[0067] The source structures 30 are formed on the active surface 8 in the active region 12 so as to be adjacent to the gate structures 25 in the second direction Y. Specifically, the source structures 30 are respectively disposed in regions between pairs of adjacent gate structures 25 and face the gate structures 25 in the second direction Y. In other words, the source structures 30 and the gate structures 25 are arranged alternately in the second direction Y.

[0068] The multiple source structures 30 are each formed in a strip shape extending in the first direction X in a plan view. In this embodiment, the multiple source structures 30 are drawn out from the active region 12 to either or both of the first side end region 13 and the second side end region 14 (in this embodiment, both). The multiple source structures 30 face the gate structure 25 in the second direction Y in the active region 12, but do not face the gate structure 25 in the second direction Y in the first side end region 13 (second side end region 14).

[0069] The source structures 30 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the source structures 30 penetrate both the third connection surface 10C and the fourth connection surface 10D and are exposed from both the third connection surface 10C and the fourth connection surface 10D.

[0070] The plurality of source structures 30 penetrate the body region 21 and the source region 22 to reach the first semiconductor region 6 in the active region 12, and penetrate the body region 21 to reach the first semiconductor region 6 in the first side end region 13. The plurality of source structures 30 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0071] Each source structure 30 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. The second width W2 may be approximately equal to the first width W1. The second width W2 may be greater than the first width W1. The second width W2 may be 0.1 μm or more and 3 μm or less. The second width W2 is preferably 0.5 μm or more and 2 μm or less.

[0072] The second depth D2 is equal to or greater than the first depth D1 described above. In this embodiment, the second depth D2 is greater than the first depth D1. The second depth D2 is preferably 1.5 to 3 times the first depth D1. In this embodiment, the second depth D2 is approximately equal to the outer circumferential depth DO described above. The second depth D2 may be 0.1 μm to 5 μm. It is particularly preferable that the second depth D2 be 2.5 μm or less.

[0073] Each source structure 30 is disposed at a first interval I1 in the second direction Y from the gate structure 25. The first interval I1 is preferably 0.5 to 2 times the first width W1 (second width W2). It is particularly preferable that the first interval I1 be less than the first width W1 (second width W2). The first interval I1 may be 0.1 μm to 2.5 μm. The first interval I1 is preferably 0.5 μm to 1.5 μm.

[0074] Each source structure 30 includes a second trench 31, a second insulating film 32, and a second buried electrode 33. The second trench 31 is formed in the active surface 8 and defines a wall surface of the source structure 30. In this embodiment, the sidewall of the second trench 31 communicates with the third connection surface 10C and the fourth connection surface 10D. The bottom wall of the second trench 31 communicates with the outer peripheral surface 9.

[0075] The second insulating film 32 covers the wall surface of the second trench 31. The second insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 32 includes a silicon oxide film made of an oxide of the chip 2. The second buried electrode 33 is buried in the second trench 31 with the second insulating film 32 sandwiched therebetween. The second buried electrode 33 may include p-type or n-type conductive polysilicon.

[0076] The semiconductor device 1A includes a plurality of trench electrode-type side edge structures 35 formed on the first main surface 3 (active surface 8) in the first side edge region 13. A source potential is applied to the plurality of side edge structures 35. The side edge structures 35 may also be referred to as "trench side edge structures," "second source structures," "second trench source structures," or the like. The plurality of side edge structures 35 are also formed in the second side edge region 14. The configuration on the second side edge region 14 side is similar to the configuration on the first side edge region 13 side. The description of the first side edge region 13 side applies to the description of the second side edge region 14 side.

[0077] The side edge structures 35 are respectively arranged in the first side edge region 13 on the periphery of the active surface 8 (the third connection surface 10C) and in regions between the gate structures 25. The side edge structures 35 face the gate structures 25 in a one-to-one correspondence in the first direction X. The side edge structures 35 are respectively arranged in regions between pairs of source structures 30 adjacent to each other in the second direction Y, and face the source structures 30 in the second direction Y. In other words, the side edge structures 35 and the source structures 30 are alternately arranged in the second direction Y.

[0078] As a result, the side edge structures 35, together with the gate structures 25, define a plurality of side edge mesa portions ME. The side edge mesa portions ME are arranged in a line in the second direction Y. Of course, the side edge mesa portions ME may be arranged offset from one another in the first direction X so as not to face at least one side edge mesa portion ME in the second direction Y.

[0079] The multiple side edge structures 35 are each formed in a strip shape extending in the first direction X in a plan view. In this embodiment, the multiple side edge structures 35 on the first side edge region 13 side penetrate the third connecting surface 10C and are exposed from the third connecting surface 10C. The multiple side edge structures 35 on the second side edge region 14 side penetrate the fourth connecting surface 10D and are exposed from the fourth connecting surface 10D. The multiple side edge structures 35 penetrate the body region 21 to reach the first semiconductor region 6 and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0080] Each side edge structure 35, like the source structure 30, has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. Each side edge structure 35 is spaced a second distance I2 from the gate structure 25 in the first direction X and a third distance I3 from the source structure 30 in the second direction Y.

[0081] The second interval I2 is preferably 0.5 to 2 times the first width W1 (second width W2). The second interval I2 is preferably 0.5 to 2 times the first interval I1. It is particularly preferable that the second interval I2 be 1.5 times or less the first interval I1. The second interval I2 may be approximately equal to the first interval I1. The second interval I2 may be 0.1 μm to 2.5 μm. The second interval I2 is preferably 0.5 μm to 1.5 μm.

[0082] The third interval I3 is preferably 0.5 to 2 times the first width W1 (second width W2). The third interval I3 may be less than the second width W2. The third interval I3 is preferably approximately equal to the first interval I1. The third interval I3 may be 0.1 μm to 2.5 μm. The third interval I3 is preferably 0.5 μm to 1.5 μm.

[0083] Each side edge structure 35 includes a third trench 36, a third insulating film 37, and a third buried electrode 38. The third trench 36 is formed in the active surface 8 and defines the wall surface of the side edge structure 35. The side wall of the third trench 36 communicates with the third connection surface 10C. The bottom wall of the third trench 36 communicates with the outer peripheral surface 9.

[0084] The third insulating film 37 covers the wall surface of the third trench 36. The third insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the third insulating film 37 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 37 includes a silicon oxide film made of an oxide of the chip 2. The third buried electrode 38 is buried in the third trench 36 with the third insulating film 37 sandwiched therebetween. The third buried electrode 38 may include p-type or n-type conductive polysilicon.

[0085] The semiconductor device 1A includes a plurality of trench electrode type termination structures 40 formed on the first main surface 3 (active surface 8) in the first termination region 15. A source potential is applied to the plurality of termination structures 40. The termination structures 40 may also be referred to as "trench termination structures," "third source structures," "third trench source structures," or the like. The plurality of termination structures 40 are also formed in the second termination region 16. The configuration on the second termination region 16 side is similar to the configuration on the first termination region 15 side. The description on the first termination region 15 side applies to the description on the second termination region 16 side.

[0086] The multiple termination structures 40 are each formed in a strip shape extending in the first direction X and are arranged at intervals in the second direction Y. The multiple termination structures 40 are arranged continuously at equal intervals in the second direction Y so as to face each other with a part of the chip 2 in between. In other words, the multiple termination structures 40 face each other without a gate structure 25 in between.

[0087] The plurality of termination structures 40 face the plurality of gate structures 25 and the plurality of source structures 30 in the second direction Y. The plurality of termination structures 40 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the plurality of termination structures 40 penetrate both the third connection surface 10C and the fourth connection surface 10D and are exposed from both the third connection surface 10C and the fourth connection surface 10D.

[0088] That is, the plurality of termination structures 40 have portions facing the plurality of side edge structures 35 in the second direction Y on the side of the first side edge region 13. The plurality of termination structures 40 penetrate the body region 21 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0089] Like the source structures 30, each termination structure 40 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. The termination structures 40 are arranged with a fourth interval I4 between them. The fourth interval I4 is preferably 0.5 to 2 times the first width W1 (second width W2).

[0090] The fourth interval I4 may be less than the first width W1 (the second width W2). The fourth interval I4 is preferably approximately equal to the first interval I1 (the third interval I3). The fourth interval I4 may be 0.1 μm or more and 2.5 μm or less. The fourth interval I4 is preferably 0.5 μm or more and 1.5 μm or less.

[0091] Each termination structure 40 includes a fourth trench 41, a fourth insulating film 42, and a fourth buried electrode 43. The fourth trench 41 is formed in the active surface 8 and defines a wall surface of the termination structure 40. The sidewall of the fourth trench 41 communicates with the third connecting surface 10C. The bottom wall of the fourth trench 41 communicates with the outer peripheral surface 9.

[0092] The fourth insulating film 42 covers the wall surface of the fourth trench 41. The fourth insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the fourth insulating film 42 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fourth insulating film 42 includes a silicon oxide film made of an oxide of the chip 2. The fourth buried electrode 43 is buried in the fourth trench 41 with the fourth insulating film 42 sandwiched therebetween. The fourth buried electrode 43 may include p-type or n-type conductive polysilicon.

[0093] FIG. 14 is a plan view showing an example layout of the gate electrode 100 and the source electrode 120. FIG. 15 is an enlarged plan view showing a main part of FIG. 14. FIG. 16 is a further enlarged plan view of a main part of FIG. 15. FIG. 17 is an enlarged plan view showing the resistance region 17 according to a first layout example. FIG. 18 is an enlarged plan view showing an example layout of the inner part of the resistance region 17. FIG. 19 is an enlarged plan view showing an example layout of the peripheral part of the resistance region 17. FIG. 20 is an enlarged plan view showing an example layout of the first dummy region 18.

[0094] Fig. 21 is a cross-sectional view taken along line XXI-XXI in Fig. 18. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 18. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 18. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 19. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 19. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI in Fig. 20. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 20. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII in Fig. 20.

[0095] 14 to 28, the semiconductor device 1A includes at least one (in this embodiment, multiple) trench electrode type resistance structure 50 formed on the first main surface 3 (active surface 8) in the resistance region 17. The resistance structure 50 may be referred to as a "trench resistance structure." The resistance structure 50 constitutes a part of a resistance (specifically, a gate resistance RG). A gate potential is applied to the multiple resistance structures 50, but the multiple resistance structures 50 do not contribute to channel control.

[0096] The plurality of resistor structures 50 are arranged in the resistor region 17 at intervals inward from the periphery of the active surface 8 (the third connecting surface 10C and the fourth connecting surface 10D), and define the resistor region 17 in the inner part of the active surface 8.

[0097] The multiple resistance structures 50 are arranged in a region on one side in the second direction Y of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view. The multiple resistance structures 50 are located on the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. In other words, the multiple resistance structures 50 face the center of the first side surface 5A (first connecting surface 10A) in the second direction Y in a plan view.

[0098] The multiple resistance structures 50 are each formed in a strip shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y. That is, the multiple resistance structures 50 are arranged in a stripe shape extending in the first direction X in a plan view. Each of the multiple resistance structures 50 has one end on one side in the first direction X and the other end on the other side in the first direction X. Each resistance structure 50 has a length in the first direction X that is shorter than the length of each gate structure 25.

[0099] The multiple resistance structures 50 are formed at intervals inward of the active surface 8 relative to the positions of the ends of the multiple gate structures 25 in the first direction X. In other words, the multiple resistance structures 50 face inner portions of the multiple gate structures 25 in the second direction Y, but do not face both ends of the multiple gate structures 25 in the second direction Y. The multiple resistance structures 50 penetrate the body region 21 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0100] Each resistor structure 50 has a third width W3 in the second direction Y and a third depth D3 in the normal direction Z. The third width W3 is preferably approximately equal to the first width W1. The third width W3 may be 0.1 μm or more and 3 μm or less. The third width W3 is preferably 0.5 μm or more and 2 μm or less.

[0101] The third depth D3 is less than the aforementioned outer peripheral depth DO (second depth D2). The third depth D3 is preferably approximately equal to the aforementioned first depth D1. The third depth D3 may be 0.1 μm or more and 3 μm or less. The third depth D3 is preferably 0.5 μm or more and 1.5 μm or less.

[0102] The multiple resistor structures 50 are arranged in the second direction Y at a trench pitch that is approximately equal to the trench pitch of the multiple gate structures 25. The trench pitch between adjacent gate structures 25 and resistor structures 50 is approximately equal to the trench pitch of the multiple gate structures 25 (multiple resistor structures 50).

[0103] Each resistor structure 50 includes a fifth trench 51, a fifth insulating film 52, and a fifth buried electrode 53. The fifth trench 51 is formed in the active surface 8 and defines a wall surface of the resistor structure 50. The fifth insulating film 52 covers the wall surface of the fifth trench 51. The fifth insulating film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0104] In this embodiment, the fifth insulating film 52 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fifth insulating film 52 includes a silicon oxide film made of an oxide of the chip 2. The fifth buried electrode 53 is embedded in the fifth trench 51 across the fifth insulating film 52 and faces the channel across the fifth insulating film 52. The fifth buried electrode 53 may include p-type or n-type conductive polysilicon.

[0105] The semiconductor device 1A includes at least one (in this embodiment, multiple) first dummy structures 55 of a trench electrode type formed on the first main surface 3 (active surface 8) in the resistance region 17. A source potential is applied to the multiple first dummy structures 55. The first dummy structure 55 may also be referred to as a "first dummy trench structure," a "fourth source structure," a "fourth trench source structure," or the like.

[0106] The plurality of first dummy structures 55 are formed on the active surface 8 in the resistance region 17 so as to be adjacent to the plurality of resistance structures 50 in the second direction Y. Specifically, the plurality of first dummy structures 55 are respectively arranged in regions between pairs of adjacent resistance structures 50 and face the plurality of resistance structures 50 in the second direction Y.

[0107] That is, the multiple first dummy structures 55 are arranged alternately with the multiple resistance structures 50 in the second direction Y. The multiple first dummy structures 55 face the multiple resistance structures 50, the multiple gate structures 25, the multiple source structures 30, and the multiple termination structures 40 in the second direction Y. The multiple first dummy structures 55 are each formed in a strip shape extending in the first direction X in a plan view.

[0108] The plurality of first dummy structures 55 are drawn out from the resistance region 17 to either or both of the first dummy region 18 and the second dummy region 19 (both in this embodiment). That is, the plurality of first dummy structures 55 have a length in the first direction X that is greater than the length of the resistance structure 50, and face the active region 12 in the second direction Y in the first dummy region 18 (second dummy region 19).

[0109] The plurality of first dummy structures 55 are drawn out toward the peripheral edge of the active surface 8 relative to the positions of the ends of the plurality of gate structures 25 in the first direction X, and have portions facing the first side end regions 13 (second side end regions 14) in the second direction Y. In other words, the plurality of first dummy structures 55 have portions facing the plurality of side end structures 35 in the second direction Y.

[0110] The plurality of first dummy structures 55 are exposed from at least one of the third connecting surface 10C and the fourth connecting surface 10D. In this embodiment, the plurality of first dummy structures 55 penetrate both the third connecting surface 10C and the fourth connecting surface 10D and are exposed from both the third connecting surface 10C and the fourth connecting surface 10D. The plurality of first dummy structures 55 penetrate the body region 21 to reach the first semiconductor region 6 and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0111] Each first dummy structure 55 has a fourth width W4 in the second direction Y and a fourth depth D4 in the normal direction Z. The fourth width W4 may be approximately equal to the third width W3 described above. The fourth width W4 may be larger than the third width W3. The fourth width W4 is preferably approximately equal to the second width W2 described above. The fourth width W4 may be 0.1 μm or more and 3 μm or less. The fourth width W4 is preferably 0.5 μm or more and 2 μm or less.

[0112] The fourth depth D4 is equal to or greater than the third depth D3. In this embodiment, the fourth depth D4 is greater than the third depth D3. The fourth depth D4 is preferably 1.5 to 3 times the third depth D3. In this embodiment, the fourth depth D4 is approximately equal to the outer periphery depth DO (second depth D2). The fourth depth D4 may be 0.1 μm to 5 μm. It is particularly preferable that the fourth depth D4 be 2.5 μm or less.

[0113] Each first dummy structure 55 is arranged at a fifth interval I5 in the second direction Y from the resistor structure 50. The fifth interval I5 is preferably 0.5 to 2 times the third width W3 (fourth width W4). It is particularly preferable that the fifth interval I5 be less than the third width W3 (fourth width W4). The fifth interval I5 is preferably approximately equal to the first interval I1 (third interval I3) described above. The fifth interval I5 may be 0.1 μm to 2.5 μm. The fifth interval I5 is preferably 0.5 μm to 1.5 μm.

[0114] When the outermost portion of the active region 12 is formed by the gate structure 25, the first dummy structure 55 is arranged in a region between the gate structure 25 and the resistance structure 50 at a fifth interval I5 (first interval I1) in the second direction Y from the gate structure 25 and the resistance structure 50. When the outermost portion of the active region 12 is formed by the source structure 30, the first dummy structure 55 is arranged to face the source structure 30 with the resistance structure 50 sandwiched between them in the second direction Y.

[0115] In this case, the first dummy structure 55 is arranged at a fifth interval I5 (first interval I1) from the resistor structure 50 in the second direction Y. The first dummy structure 55 constitutes the outermost portion of the resistor region 17 on the first termination region 15 side. The outermost first termination region 15 is arranged at a fifth interval I5 (first interval I1) from the termination structure 40 in the second direction Y.

[0116] Each first dummy structure 55 includes a sixth trench 56, a sixth insulating film 57, and a sixth buried electrode 58. The sixth trench 56 is formed in the active surface 8 and defines the wall surface of the first dummy structure 55. In this embodiment, the sidewall of the sixth trench 56 communicates with the third connecting surface 10C and the fourth connecting surface 10D. The bottom wall of the sixth trench 56 communicates with the outer peripheral surface 9.

[0117] The sixth insulating film 57 covers the wall surface of the sixth trench 56. The sixth insulating film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the sixth insulating film 57 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the sixth insulating film 57 includes a silicon oxide film made of an oxide of the chip 2. The sixth buried electrode 58 is buried in the sixth trench 56 with the sixth insulating film 57 sandwiched therebetween. The sixth buried electrode 58 may include p-type or n-type conductive polysilicon.

[0118] The semiconductor device 1A includes at least one (in this embodiment, a plurality) of second dummy structures 60 of a trench electrode type formed on the first main surface 3 (active surface 8) in the first dummy region 18. A source potential is applied to the plurality of second dummy structures 60. The second dummy structure 60 may also be referred to as a "second dummy trench structure," a "fifth source structure," a "fifth trench source structure," or the like. The plurality of second dummy structures 60 are also formed in the second dummy region 19. The configuration of the second dummy region 19 side is the same as the configuration of the first dummy region 18 side. The description of the first side end region 13 side applies to the description of the second dummy region 19 side.

[0119] The second dummy structures 60 are respectively arranged in the first dummy region 18 on the periphery of the active surface 8 (third connection surface 10C) and in regions between the resistor structures 50. The second dummy structures 60 face the resistor structures 50 in a one-to-one correspondence in the first direction X. The second dummy structures 60 are respectively arranged in regions between pairs of first dummy structures 55 adjacent in the second direction Y, and face the first dummy structures 55 in the second direction Y.

[0120] That is, the second dummy structures 60 and the first dummy structures 55 are alternately arranged in the second direction Y. The second dummy structures 60, together with the resistor structures 50, define dummy mesa portions MD. The dummy mesa portions MD are located closer to the inner side of the active surface 8 than the side end mesa portions ME in the first direction X.

[0121] The multiple dummy mesa portions MD are arranged in a line in the second direction Y. Of course, the multiple dummy mesa portions MD may be arranged shifted from one another in the first direction X so as not to face at least one dummy mesa portion MD in the second direction Y. The multiple dummy mesa portions MD face the multiple gate structures 25, the multiple source structures 30, the multiple termination structures 40, and the multiple first dummy structures 55 in the second direction Y.

[0122] The second dummy structures 60 are each formed in a strip shape extending in the first direction X in a plan view. The second dummy structures 60 are arranged in a region on the side of the resistance structures 50 relative to the end positions of the gate structures 25 in the first direction X, and face the active region 12 in the second direction Y. In other words, the second dummy structures 60 face the gate structures 25, the source structures 30, the termination structures 40, and the first dummy structures 55 in the second direction Y on the active region 12 side.

[0123] The second dummy structures 60 are extended toward the periphery of the active surface 8 relative to the positions of the ends of the gate structures 25 in the first direction X, and have portions facing the first side end regions 13 (second side end regions 14) in the second direction Y. In other words, the second dummy structures 60 have portions facing the side end structures 35 in the second direction Y.

[0124] In this embodiment, the plurality of second dummy structures 60 on the first dummy region 18 side penetrate the third connection surface 10C and are exposed from the third connection surface 10C. The plurality of second dummy structures 60 on the second dummy region 19 side penetrate the fourth connection surface 10D and are exposed from the fourth connection surface 10D. The plurality of second dummy structures 60 penetrate the body region 21 to reach the first semiconductor region 6 and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8.

[0125] Like the first dummy structures 55, each second dummy structure 60 has a fourth width W4 in the second direction Y and a fourth depth D4 in the normal direction Z. Each second dummy structure 60 is arranged at a sixth distance I6 from the resistor structure 50 in the first direction X, and at a seventh distance I7 from the first dummy structure 55 in the second direction Y.

[0126] The sixth interval I6 is preferably 0.5 to 2 times the third width W3 (fourth width W4). The sixth interval I6 is preferably 0.5 to 2 times the fifth interval I5 (first interval I1). The sixth interval I6 is particularly preferably 1.5 times or less the fifth interval I5 (first interval I1). The sixth interval I6 may be approximately equal to the fifth interval I5 (first interval I1). The sixth interval I6 may be 0.1 μm to 2.5 μm. The sixth interval I6 is preferably 0.5 μm to 1.5 μm.

[0127] The seventh interval I7 is preferably 0.5 to 2 times the third width W3 (fourth width W4). The seventh interval I7 may be less than the third width W3 (fourth width W4). The seventh interval I7 is preferably approximately equal to the fifth interval I5 (first interval I1) described above. The seventh interval I7 may be 0.1 μm to 2.5 μm. The seventh interval I7 is preferably 0.5 μm to 1.5 μm.

[0128] Each second dummy structure 60 includes a seventh trench 61, a seventh insulating film 62, and a seventh buried electrode 63. The seventh trench 61 is formed in the active surface 8 and defines a wall surface of the second dummy structure 60. A sidewall of the seventh trench 61 communicates with the third connecting surface 10C. A bottom wall of the seventh trench 61 communicates with the outer peripheral surface 9.

[0129] The seventh insulating film 62 covers the wall surface of the seventh trench 61. The seventh insulating film 62 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the seventh insulating film 62 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the seventh insulating film 62 include a silicon oxide film made of an oxide of the chip 2. The seventh buried electrode 63 is buried in the seventh trench 61, sandwiching the seventh insulating film 62 therebetween. The seventh buried electrode 63 may include p-type or n-type conductive polysilicon.

[0130] The semiconductor device 1A includes a plurality of p-type first well regions 65 formed in regions along the plurality of gate structures 25 in a surface layer portion of the active surface 8 of the active region 12. The first well regions 65 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 21. Of course, the p-type impurity concentration of the first well regions 65 may be lower than the p-type impurity concentration of the body region 21.

[0131] The multiple first well regions 65 cover the wall surfaces of the corresponding gate structures 25 at intervals from the adjacent source structures 30, and are electrically connected to the body region 21 in the surface layer portion of the active surface 8. The multiple first well regions 65 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between. The multiple first well regions 65 form pn junctions with the first semiconductor region 6.

[0132] The semiconductor device 1A includes a plurality of p-type second well regions 66 formed in regions along the plurality of source structures 30 in the surface layer portion of the active surface 8 of the active region 12. The second well regions 66 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 21. Of course, the p-type impurity concentration of the second well regions 66 may be lower than the p-type impurity concentration of the body region 21. It is preferable that the p-type impurity concentration of the second well regions 66 is approximately equal to the p-type impurity concentration of the first well region 65.

[0133] The second well regions 66 cover the wall surfaces of the corresponding source structures 30 at intervals from the adjacent gate structures 25, and are electrically connected to the body region 21 in the surface portion of the active surface 8. The second well regions 66 cover the wall surfaces of the corresponding source structures 30 in the active region 12, the first side end region 13, and the second side end region 14, and are exposed from the third connection surface 10C and the fourth connection surface 10D.

[0134] The second well regions 66 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the second well regions 66 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the first well regions 65. The second well regions 66 form pn junctions with the first semiconductor region 6.

[0135] The semiconductor device 1A includes a plurality of p-type third well regions 67 formed in a region along the plurality of side edge structures 35 in a surface layer portion of the active surface 8 of the first side edge region 13 (second side edge region 14). The third well regions 67 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 21. Of course, the p-type impurity concentration of the third well regions 67 may be lower than the p-type impurity concentration of the body region 21. It is preferable that the p-type impurity concentration of the third well regions 67 be approximately equal to the p-type impurity concentration of the first well region 65 (second well region 66).

[0136] The plurality of third well regions 67 cover the wall surfaces of the corresponding side edge structures 35 at intervals from the adjacent gate structures 25 and source structures 30, and are electrically connected to the body region 21 in the surface portion of the active surface 8. Of course, the third well regions 67 may be integrated with the first well region 65 in the region between the gate structures 25 and the side edge structures 35. The plurality of third well regions 67 are exposed from the third connection surface 10C.

[0137] The plurality of third well regions 67 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the plurality of third well regions 67 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the plurality of first well regions 65. The bottoms of the plurality of third well regions 67 are formed at approximately the same depth as the bottoms of the plurality of second well regions 66. The plurality of third well regions 67 form pn junctions with the first semiconductor region 6.

[0138] Semiconductor device 1A includes at least one (in this embodiment, multiple) p-type fourth well region 68 formed in a region along multiple termination structures 40 in first termination region 15 (second termination region 16). In this embodiment, fourth well region 68 has a higher p-type impurity concentration than body region 21. Of course, the p-type impurity concentration of fourth well region 68 may be lower than that of body region 21. It is preferable that the p-type impurity concentration of fourth well region 68 is approximately equal to the p-type impurity concentration of first well region 65 (second well region 66).

[0139] The plurality of fourth well regions 68 cover the wall surfaces of the corresponding termination structures 40 at intervals from the adjacent termination structures 40, and are electrically connected to the body region 21 in the surface layer portion of the active surface 8. The plurality of fourth well regions 68 extend in a strip shape along the corresponding termination structures 40 in a plan view, and are exposed from the third connection surface 10C and the fourth connection surface 10D.

[0140] The multiple fourth well regions 68 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the multiple fourth well regions 68 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the multiple first well regions 65. The bottoms of the multiple fourth well regions 68 are preferably formed at approximately the same depth as the bottoms of the multiple second well regions 66. The multiple fourth well regions 68 form pn junctions with the first semiconductor region 6.

[0141] The semiconductor device 1A includes a plurality of p-type fifth well regions 69 formed in a region along the plurality of resistor structures 50 in a surface layer portion of the active surface 8 of the resistor region 17. The fifth well regions 69 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 21. Of course, the p-type impurity concentration of the fifth well regions 69 may be lower than the p-type impurity concentration of the body region 21. It is preferable that the p-type impurity concentration of the fifth well regions 69 is approximately equal to the p-type impurity concentration of the first well region 65.

[0142] The plurality of fifth well regions 69 cover the wall surfaces of the corresponding resistor structures 50 at intervals from the adjacent first dummy structures 55, and are electrically connected to the body region 21 in the surface layer portion of the active surface 8. The plurality of fifth well regions 69 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 with a part of the first semiconductor region 6 in between.

[0143] The bottoms of the plurality of fifth well regions 69 are located closer to the active surface 8 than the depth positions of the bottoms of the plurality of second well regions 66. The bottoms of the plurality of fifth well regions 69 are preferably formed at approximately the same depth as the bottoms of the plurality of first well regions 65. The plurality of fifth well regions 69 form pn junctions with the first semiconductor region 6.

[0144] The semiconductor device 1A includes a plurality of p-type sixth well regions 70 formed in a region along the plurality of first dummy structures 55 in a surface layer portion of the active surface 8 of the resistor region 17. The sixth well regions 70 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 21. Of course, the p-type impurity concentration of the sixth well regions 70 may be lower than the p-type impurity concentration of the body region 21. It is preferable that the p-type impurity concentration of the sixth well regions 70 be approximately equal to the p-type impurity concentration of the fifth well region 69 (first well region 65).

[0145] The plurality of sixth well regions 70 cover the wall surfaces of the corresponding first dummy structures 55 at intervals from the adjacent resistor structures 50, and are electrically connected to the body region 21 in the surface portion of the active surface 8. The plurality of sixth well regions 70 cover the wall surfaces of the corresponding first dummy structures 55 in the resistor region 17, the first dummy region 18, and the second dummy region 19, and are exposed from the third connecting surface 10C and the fourth connecting surface 10D.

[0146] The plurality of sixth well regions 70 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The bottoms of the plurality of sixth well regions 70 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the plurality of fifth well regions 69 (first well regions 65). The plurality of sixth well regions 70 form pn junctions with the first semiconductor region 6.

[0147] The semiconductor device 1A includes a plurality of p-type seventh well regions 71 formed in a region along the plurality of second dummy structures 60 in a surface layer portion of the active surface 8 of the first dummy region 18 (second dummy region 19). The seventh well regions 71 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 21. Of course, the p-type impurity concentration of the seventh well regions 71 may be lower than the p-type impurity concentration of the body region 21. It is preferable that the p-type impurity concentration of the seventh well regions 71 be approximately equal to the p-type impurity concentration of the fifth well region 69 (sixth well region 70).

[0148] The seventh well regions 71 cover the wall surfaces of the corresponding second dummy structures 60 at intervals from the adjacent resistance structures 50 and first dummy structures 55, and are electrically connected to the body region 21 in the surface layer portion of the active surface 8. Of course, the seventh well regions 71 may be integrated with the fifth well region 69 in the region between the resistance structures 50 and the second dummy structures 60. The seventh well regions 71 are exposed from the third connection surface 10C.

[0149] The multiple seventh well regions 71 are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The bottoms of the multiple seventh well regions 71 are located closer to the bottom of the first semiconductor region 6 than the depth positions of the bottoms of the multiple fifth well regions 69 (first well regions 65). The bottoms of the multiple seventh well regions 71 are formed at approximately the same depth as the bottoms of the multiple sixth well regions 70 (second well regions 66). The multiple seventh well regions 71 form pn junctions with the first semiconductor region 6.

[0150] The semiconductor device 1A includes a plurality of p-type contact regions 72 formed in regions along the plurality of source structures 30 in a surface layer portion of the active surface 8 of the active region 12. The contact regions 72 may also be referred to as "back gate regions." The contact regions 72 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 21. The p-type impurity concentration of the contact regions 72 is higher than the p-type impurity concentration of the first well region 65 (second well region 66).

[0151] The plurality of contact regions 72 are formed only in the plurality of second well regions 66, and are not formed in the first well region 65, the third well region 67, the fourth well region 68, the fifth well region 69, the sixth well region 70, or the seventh well region 71. The plurality of contact regions 72 cover the wall surfaces of the corresponding source structures 30 in the corresponding second well regions 66.

[0152] The plurality of contact regions 72 are formed in a one-to-many correspondence with each source structure 30. The plurality of contact regions 72 are formed at intervals along the corresponding source structures 30. The plurality of contact regions 72 are extended from within the corresponding second well region 66 to the surface portion of the body region 21 along the wall surface of the corresponding source structure 30, and are exposed from the active surface 8.

[0153] In this embodiment, the multiple contact regions 72 are each formed in a strip shape extending in the first direction X in a plan view. The multiple contact regions 72 face the gate structures 25 in the second direction Y, but do not face the side end structures 35 in the second direction Y. The length of the multiple contact regions 72 in the first direction X is preferably equal to or greater than the second width W2 described above. The length of the multiple contact regions 72 is preferably greater than the distance between two adjacent contact regions 72 in the first direction X.

[0154] The plurality of contact regions 72 along one source structure 30 face the plurality of contact regions 72 along another source structure 30 in the second direction Y. That is, in this embodiment, the plurality of contact regions 72 are arranged in a matrix form at intervals in the first direction X and the second direction Y as a whole in a plan view.

[0155] The plurality of contact regions 72 along one source structure 30 may be arranged offset in the first direction X so as to face the regions between the plurality of contact regions 72 along another source structure 30 in the second direction Y. In other words, the plurality of contact regions 72 may be arranged in a staggered pattern as a whole in a plan view with intervals in the first direction X and the second direction Y.

[0156] 29 is a cross-sectional view showing the structure of peripheral region 20. Referring to Fig. 29, semiconductor device 1A includes a p-type outer well region 73 formed in a surface layer portion of peripheral surface 9. Outer well region 73 has a p-type impurity concentration that is lower than the p-type impurity concentration of contact region 72.

[0157] The p-type impurity concentration of the outer well region 73 is higher than the p-type impurity concentration of the body region 21. Of course, the p-type impurity concentration of the outer well region 73 may be lower than the body region 21. It is preferable that the outer well region 73 has a p-type impurity concentration approximately equal to that of the first well region 65 (second well region 66).

[0158] The outer well region 73 is formed in a plan view at a distance from the periphery of the outer peripheral surface 9 (first to fourth side surfaces 5A to 5D) toward the active surface 8, and extends in a band shape along the active surface 8. In this embodiment, the outer well region 73 is formed in a ring shape (specifically, a quadrangular ring) that surrounds the active surface 8 in a plan view. The outer well region 73 extends from the surface layer portion of the outer peripheral surface 9 toward the surface layer portions of the first to fourth connecting surfaces 10A to 10D, and covers the first to fourth connecting surfaces 10A to 10D.

[0159] The outer well region 73 is electrically connected to the body region 21 in a surface layer portion of the active surface 8. The outer well region 73 is connected to the second well region 66, the third well region 67, the fourth well region 68, the sixth well region 70, and the seventh well region 71 at the third connection surface 10C (fourth connection surface 10D).

[0160] The outer well region 73 is formed at a distance from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The bottom of the outer well region 73 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the resistance structure 50 (gate structure 25). Specifically, the bottom of the outer well region 73 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first dummy structure 55 (source structure 30).

[0161] The bottom of the outer well region 73 is located closer to the bottom of the first semiconductor region 6 than the bottom of the contact region 72. The bottom of the outer well region 73 is preferably formed at a depth substantially equal to the bottom of the sixth well region 70 (second well region 66). The outer well region 73 forms a pn junction with the first semiconductor region 6.

[0162] The semiconductor device 1A includes a p-type outer contact region 74 formed in a surface layer portion of the outer peripheral surface 9. The outer contact region 74 has a higher p-type impurity concentration than the body region 21. The p-type impurity concentration of the outer contact region 74 is higher than the outer well region 73. It is preferable that the p-type impurity concentration of the outer contact region 74 be approximately equal to the p-type impurity concentration of the contact region 72.

[0163] The outer contact region 74 is formed in the surface layer of the outer well region 73 at a distance from the periphery of the active surface 8 (first to fourth connection surfaces 10A to 10D) and the periphery of the outer surface 9 (first to fourth side surfaces 5A to 5D) in a planar view, and is formed in a strip shape extending along the active surface 8.

[0164] In this embodiment, the outer contact region 74 is formed in a ring shape (specifically, a square ring shape) in a plan view that surrounds the active surface 8. The outer contact region 74 is formed at a distance from the bottom of the outer well region 73 toward the outer peripheral surface 9, and faces the first semiconductor region 6 with a part of the outer well region 73 in between.

[0165] The outer contact region 74 is located closer to the bottom of the first semiconductor region 6 than the bottom of the resistor structure 50 (gate structure 25). The outer contact region 74 is located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first dummy structure 55 (source structure 30). The bottom of the outer contact region 74 is preferably formed at a depth position substantially equal to the bottom of the contact region 72.

[0166] Semiconductor device 1A includes at least one (preferably two to twenty) p-type field region 75 formed in the surface layer of outer peripheral surface 9. In this embodiment, semiconductor device 1A includes four field regions 75. The multiple field regions 75 are formed in an electrically floating state and relieve the electric field within chip 2 at outer peripheral surface 9.

[0167] The number, width, depth, p-type impurity concentration, etc. of the field regions 75 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The field regions 75 may have a lower p-type impurity concentration than the outer contact regions 74. The field regions 75 may have a higher p-type impurity concentration than the outer well region 73. The field regions 75 may have a lower p-type impurity concentration than the outer well region 73.

[0168] The plurality of field regions 75 are formed in a region between the periphery of the outer peripheral surface 9 and the outer well region 73. The plurality of field regions 75 are arranged at intervals from the outer well region 73 side toward the periphery of the outer peripheral surface 9. The plurality of field regions 75 are formed in a band shape extending along the active surface 8 in a plan view. In this embodiment, the plurality of field regions 75 are formed in a ring shape (specifically, a square ring) surrounding the active surface 8 in a plan view.

[0169] The plurality of field regions 75 are formed at intervals from the bottom of the first semiconductor region 6 toward the outer circumferential surface 9, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The plurality of field regions 75 are located closer to the bottom of the first semiconductor region 6 than the bottom of the resistor structure 50 (gate structure 25). The plurality of field regions 75 are located closer to the bottom of the first semiconductor region 6 than the bottom wall of the first dummy structure 55 (source structure 30). The bottoms of the plurality of field regions 75 may be formed at a depth position substantially equal to the bottom of the sixth well region 70 (second well region 66).

[0170] The semiconductor device 1A includes a main surface insulating film 80 covering the first main surface 3. The main surface insulating film 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 80 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 80 include a silicon oxide film made of an oxide of the chip 2.

[0171] The main surface insulating film 80 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connecting surfaces 10A to 10D. The main surface insulating film 80 is connected to the first insulating film 27, the second insulating film 32, the third insulating film 37, the fourth insulating film 42, the fifth insulating film 52, the sixth insulating film 57, and the seventh insulating film 62 on the active surface 8, and exposes the first buried electrode 28, the second buried electrode 33, the third buried electrode 38, the fourth buried electrode 43, the fifth buried electrode 53, the sixth buried electrode 58, and the seventh buried electrode 63.

[0172] The main surface insulating film 80 covers the outer well region 73, the outer contact region 74, and the plurality of field regions 75 on the outer peripheral surface 9. In this embodiment, the main surface insulating film 80 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the main surface insulating film 80 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.

[0173] The main surface insulating film 80 is connected to the second insulating film 32, the third insulating film 37, the fourth insulating film 42, the sixth insulating film 57, and the seventh insulating film 62 at the first to fourth connecting surfaces 10A to 10D, and exposes the second buried electrode 33, the third buried electrode 38, the fourth buried electrode 43, the sixth buried electrode 58, and the seventh buried electrode 63.

[0174] 11 to 13 and 26 to 29 , semiconductor device 1A includes sidewall wiring 81 formed on outer peripheral surface 9 so as to cover at least one of first to fourth connecting surfaces 10A to 10D. Specifically, sidewall wiring 81 is arranged on main surface insulating film 80. Sidewall wiring 81 also functions as a "sidewall structure" that reduces a step formed between active surface 8 and outer peripheral surface 9.

[0175] The sidewall wiring 81 is preferably formed in a strip shape extending along at least one of the third connecting surface 10C and the fourth connecting surface 10D. In this embodiment, the sidewall wiring 81 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting surfaces 10A to 10D so as to surround the active surface 8 in a plan view. The portions of the sidewall wiring 81 that cover the four corners of the active surface 8 are formed in a curved shape toward the outer peripheral surface 9.

[0176] The sidewall wiring 81 includes a portion extending in a film-like manner along the outer peripheral surface 9 and a portion extending in a film-like manner along the first to fourth connecting surfaces 10A to 10D. The portion of the sidewall wiring 81 located on the outer peripheral surface 9 may cover the outer peripheral surface 9 in a film-like manner in a region on the outer peripheral surface 9 side of the active surface 8. In other words, the portion of the sidewall wiring 81 located on the outer peripheral surface 9 may have a thickness less than the thickness of the active plateau 11 (peripheral depth DO).

[0177] The sidewall wiring 81 faces the outer well region 73 at the outer peripheral surface 9, with the main surface insulating film 80 therebetween. The sidewall wiring 81 may also face the outer contact region 74, with the main surface insulating film 80 therebetween. In this embodiment, the sidewall wiring 81 is formed at a distance from the field region 75 toward the active surface 8 in plan view.

[0178] The sidewall wiring 81 covers the first to fourth connecting surfaces 10A to 10D with the main surface insulating film 80 interposed therebetween. The sidewall wiring 81 faces the second well region 66, the third well region 67, the fourth well region 68, and the outer well region 73 at the first to fourth connecting surfaces 10A to 10D with the main surface insulating film 80 interposed therebetween. In this embodiment, the sidewall wiring 81 also faces the body region 21 with the main surface insulating film 80 interposed therebetween.

[0179] The sidewall wiring 81 covers the exposed portions of the plurality of source structures 30 (second buried electrodes 33), the exposed portions of the plurality of side end structures 35 (third buried electrodes 38), the exposed portions of the plurality of termination structures 40 (fourth buried electrodes 43), the exposed portions of the plurality of first dummy structures 55 (sixth buried electrodes 58), and the plurality of second dummy structures 60 (seventh buried electrodes 63) on the first to fourth connection surfaces 10A to 10D.

[0180] As a result, the sidewall wiring 81 is electrically connected to the plurality of source structures 30, the plurality of side end structures 35, the plurality of termination structures 40, the plurality of first dummy structures 55, and the plurality of second dummy structures 60. In other words, the sidewall wiring 81 applies a source potential to the connection target from the outer circumferential surface 9 side.

[0181] The sidewall wiring 81 has an overlapping portion 82 that extends from at least one of the first to fourth connecting surfaces 10A to 10D onto the edge of the active surface 8. The overlapping portion 82 covers the active surface 8 in a film-like manner in plan view and is formed in a band shape that extends along the edge of the active surface 8. In this embodiment, the overlapping portion 82 is formed in a ring shape (specifically, a quadrangular ring) that surrounds the inner portion of the active surface 8 in plan view.

[0182] The overlapping portion 82 covers the peripheral portion of the active surface 8, spaced apart from the plurality of gate structures 25 and the plurality of resistor structures 50. At the peripheral portion of the active surface 8, the overlapping portion 82 covers exposed portions of the plurality of source structures 30 (second buried electrodes 33), exposed portions of the plurality of side edge structures 35 (third buried electrodes 38), exposed portions of the plurality of termination structures 40 (fourth buried electrodes 43), exposed portions of the plurality of first dummy structures 55 (sixth buried electrodes 58), and exposed portions of the plurality of second dummy structures 60 (seventh buried electrodes 63).

[0183] As a result, the sidewall wiring 81 is electrically connected to the multiple source structures 30, the multiple side end structures 35, the multiple termination structures 40, the multiple first dummy structures 55 and the multiple second dummy structures 60 on the active surface 8.

[0184] In this embodiment, the sidewall wiring 81 includes p-type or n-type conductive polysilicon and is formed integrally with the second buried electrode 33, the third buried electrode 38, the fourth buried electrode 43, the sixth buried electrode 58, and the seventh buried electrode 63. Of course, the sidewall wiring 81 may be formed separately from the second buried electrode 33, the third buried electrode 38, and the fourth buried electrode 43.

[0185] 5 and 9 again, the semiconductor device 1A includes a plurality of gate connection electrodes 83 that cover the plurality of gate structures 25 in the active region 12 in a film-like manner. The gate connection electrodes 83 may be referred to as "connection electrodes," "connection electrode films," "gate connection electrode films," etc. The gate connection electrodes 83 may be considered to be one component of the gate structures 25.

[0186] In this embodiment, a plurality of gate connection electrodes 83 are provided at intervals in a one-to-many correspondence with each gate structure 25. In this embodiment, the plurality of gate connection electrodes 83 selectively cover the inner portions and both end portions of the corresponding gate structures 25. In this embodiment, the plurality of gate connection electrodes 83 are each formed in a strip shape extending in the first direction X.

[0187] The plurality of gate connection electrodes 83 are formed at intervals in the first direction X from the plurality of side edge structures 35 in a plan view, and are formed at intervals in the second direction Y from the plurality of source structures 30. The plurality of gate connection electrodes 83 expose the plurality of source structures 30 and the plurality of side edge structures 35. The plurality of gate connection electrodes 83 are arranged alternately with the plurality of source structures 30 in the second direction Y in a plan view, and do not face the plurality of side edge structures 35 in the second direction Y.

[0188] Each gate connection electrode 83 is connected to the first buried electrode 28 in a portion covering the corresponding gate structure 25, and has a portion that is extended from above the first buried electrode 28 onto the main surface insulating film 80. In this embodiment, each gate connection electrode 83 is formed integrally with the corresponding first buried electrode 28. That is, each gate connection electrode 83 includes a portion where part of the first buried electrode 28 is extended in the form of a film to an area outside the gate structure 25 (above the main surface insulating film 80). Of course, the gate connection electrode 83 may be formed separately from the first buried electrode 28.

[0189] Each gate connection electrode 83 has an electrode surface extending along the active surface 8. In this embodiment, each gate connection electrode 83 is formed in a tapered shape (a truncated quadrangular pyramid shape) from the active surface 8 toward the electrode surface in a cross-sectional view. The electrode surface is preferably formed to be wider than the gate structure 25 in the second direction Y. In other words, the electrode surface preferably has a portion facing the gate structure 25 in the normal direction Z and a portion facing a region outside the gate structure 25 (i.e., the main surface insulating film 80) in the normal direction Z.

[0190] In this embodiment, each gate connection electrode 83 includes p-type or n-type conductive polysilicon. Each gate connection electrode 83 has an electrode thickness TE. The electrode thickness TE is preferably at least 0.5 times the first width W1 (second width W2) described above. The electrode thickness TE is preferably not more than the peripheral depth DO described above. The electrode thickness TE is preferably not more than the second depth D2 described above. It is particularly preferable that the electrode thickness TE be less than the second depth D2 (periphery depth DO).

[0191] The electrode thickness TE is preferably equal to or less than the first depth D1. Of course, the electrode thickness TE may be greater than the first depth D1. It is particularly preferable that the electrode thickness TE is less than the first depth D1. The electrode thickness TE may be equal to or greater than 0.05 μm and equal to or less than 2.5 μm. The electrode thickness TE is preferably equal to or greater than 0.5 μm and equal to or less than 1.5 μm.

[0192] 14 to 28 , etc., the semiconductor device 1A includes at least one resistive film 85 (in this embodiment, multiple resistive films 85) arranged in the resistive region 17. The resistive film 85 may also be referred to as a "resistor," a "gate resistive film," etc. The multiple resistive films 85, together with the multiple resistive structures 50, form part of a resistor (specifically, a gate resistor RG). Each resistive film 85 may be considered to be one component of each resistive structure 50.

[0193] The resistive film 85 includes at least one of a conductive polysilicon film and an alloy crystal film. The alloy crystal film includes alloy crystals composed of a metal element and a non-metal element. The alloy crystal film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the resistive film 85 includes p-type or n-type conductive polysilicon.

[0194] Each of the plurality of resistive films 85 covers a corresponding one of the resistive structures 50 as a single covering target in a film-like manner, and is electrically connected to the corresponding one of the resistive structures 50. In other words, each of the resistive films 85 is provided in a one-to-one correspondence with each of the resistive structures 50. In this embodiment, the plurality of resistive films 85 are each formed in a strip shape extending in the first direction X in a plan view, and face each other in the second direction Y. In other words, the plurality of resistive films 85 are arranged in a strip shape extending along the plurality of resistive structures 50 in a plan view.

[0195] The multiple resistive films 85 are arranged at intervals in the second direction Y from the resistive structures 50 that are not to be covered, thereby exposing the resistive structures 50 that are not to be covered. The multiple resistive films 85 are arranged at intervals in the second direction Y from the multiple first dummy structures 55, thereby exposing the multiple first dummy structures 55. In other words, the multiple resistive films 85 are arranged alternately with the multiple first dummy structures 55 in the second direction Y in a plan view.

[0196] The multiple resistance films 85 are arranged at intervals in the first direction X from the multiple second dummy structures 60, exposing the multiple second dummy structures 60. In other words, the multiple resistance films 85 face the multiple second dummy structures 60 in the first direction X in plan view, but do not face the multiple second dummy structures 60 in the second direction Y.

[0197] Each resistive film 85 selectively covers a portion of the resistive structure 50 to partially expose the resistive structure 50. In this embodiment, each resistive film 85 covers an inner portion of the corresponding resistive structure 50 at a distance inward from both ends of the corresponding resistive structure 50 in the first direction X, thereby exposing both ends of the corresponding resistive structure 50. Of course, the resistive film 85 may cover the entire area of ​​the corresponding resistive structure 50.

[0198] Each resistive film 85 covers the fifth buried electrode 53 so as to partially expose the fifth buried electrode 53 of the corresponding resistive structure 50. Each resistive film 85 is connected to the corresponding fifth buried electrode 53, and has a portion that is extended from above the fifth buried electrode 53 onto the main surface insulating film 80.

[0199] That is, each resistive film 85 is formed wider in the second direction Y than the corresponding resistive structure 50. Each resistive film 85 faces the body region 21 and the fifth well region 69 in the stacking direction in an area outside the resistive structure 50. In this embodiment, each resistive film 85 does not face the source region 22 in the stacking direction.

[0200] In this embodiment, each resistive film 85 is made of the same conductive material as the corresponding fifth buried electrode 53 and is formed integrally with the fifth buried electrode 53. In other words, each resistive film 85 includes a portion of the fifth buried electrode 53 that is extended in the form of a film to an area outside the resistive structure 50 (above the main surface insulating film 80). Of course, each resistive film 85 may be formed separately from the fifth buried electrode 53.

[0201] Each resistive film 85 has a resistive surface extending along the active surface 8. In this embodiment, each resistive film 85 is formed in a tapered shape (a truncated quadrangular pyramid shape) from the active surface 8 toward the resistive surface in a cross-sectional view. The resistive surface is preferably formed to be wider than the resistive structure 50 in the second direction Y. In other words, the resistive surface preferably has a portion facing the resistive structure 50 in the normal direction Z and a portion facing a region outside the resistive structure 50 (i.e., the main surface insulating film 80) in the normal direction Z.

[0202] The resistive film 85 has a resistor thickness TR. The resistor thickness TR is adjusted as appropriate depending on the resistance value to be achieved. The resistor thickness TR is preferably 0.5 times or more the aforementioned fourth width W4. The resistor thickness TR is preferably equal to or less than the aforementioned outer circumferential depth DO. The resistor thickness TR is preferably equal to or less than the aforementioned fourth depth D4 (second depth D2). It is particularly preferable that the resistor thickness TR be less than the outer circumferential depth DO (fourth depth D4).

[0203] The resistor thickness TR is preferably equal to or less than the third depth D3 (first depth D1) described above. It is particularly preferable that the resistor thickness TR be less than the third depth D3 (first depth D1). The resistor thickness TR may be approximately equal to the electrode thickness TE described above. The resistor thickness TR may be equal to or greater than 0.05 μm and equal to or less than 2.5 μm. The resistor thickness TR is preferably equal to or greater than 0.5 μm and equal to or less than 1.5 μm.

[0204] Of course, the resistor thickness TR may be greater than the third depth D3 (first depth D1). The resistor thickness TR may be greater than the outer circumferential depth DO (fourth depth D4). When the resistor film 85 is made of an alloy crystal film, the resistor thickness TR may be less than the fourth depth D4. In this case, the resistor thickness TR may be 0.1 nm or more and 100 nm or less.

[0205] The semiconductor device 1A includes an insulating interlayer film 86 that covers the main surface insulating film 80. The interlayer film 86 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 86 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 86 preferably includes a silicon oxide film.

[0206] The interlayer film 86 selectively covers the active surface 8, the outer peripheral surface 9, and the first to fourth connection surfaces 10A to 10D, sandwiching the main surface insulating film 80. The interlayer film 86 covers the plurality of gate structures 25 (first buried electrodes 28), the plurality of source structures 30 (second buried electrodes 33), the plurality of side end structures 35 (third buried electrodes 38), the plurality of termination structures 40 (fourth buried electrodes 43), the plurality of resistance structures 50 (fifth buried electrodes 53), the plurality of first dummy structures 55 (sixth buried electrodes 58), and the plurality of second dummy structures 60 (seventh buried electrodes 63) on the active surface 8. The interlayer film 86 covers the plurality of gate connection electrodes 83 and the plurality of resistance films 85 on the active surface 8.

[0207] The interlayer film 86 covers the outer well region 73, the outer contact region 74, and the plurality of field regions 75 on the outer peripheral surface 9, sandwiching the main surface insulating film 80 therebetween. The interlayer film 86 covers the sidewall wiring 81 on the first to fourth connecting surfaces 10A to 10D. In this embodiment, the interlayer film 86 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the interlayer film 86 may be formed at a distance inward from the periphery of the outer peripheral surface 9, exposing the first semiconductor region 6 from the periphery of the outer peripheral surface 9.

[0208] 4 to 13 , etc., the semiconductor device 1A includes a plurality of gate openings 87 formed in an interlayer film 86. The plurality of gate openings 87 penetrate the interlayer film 86 so as to selectively expose the plurality of gate structures 25. Specifically, the plurality of gate openings 87 are formed in portions of the interlayer film 86 that cover the plurality of gate connection electrodes 83, respectively, and expose the plurality of gate connection electrodes 83, respectively.

[0209] That is, the plurality of gate openings 87 expose parts of the plurality of gate structures 25 via the plurality of gate connection electrodes 83. The plurality of gate openings 87 are provided in a one-to-one correspondence with the plurality of gate connection electrodes 83.

[0210] The semiconductor device 1A includes a plurality of source openings 88 formed in an interlayer film 86. The plurality of source openings 88 penetrate the interlayer film 86 to selectively expose a plurality of source structures 30. Specifically, the plurality of source openings 88 exposes a corresponding source structure 30 and the source region 22 and contact region 72 located on both sides of the corresponding source structure 30.

[0211] The plurality of source openings 88 may be formed in a strip shape extending along the corresponding source structures 30. Of course, the plurality of source openings 88 may be formed in a one-to-many correspondence with the corresponding source structures 30. In this case, the plurality of source openings 88 may be formed at intervals along the corresponding source structures 30.

[0212] The semiconductor device 1A includes an outer opening 89 formed in an interlayer film 86. The outer opening 89 penetrates the main surface insulating film 80 and the interlayer film 86 so as to selectively expose the outer contact region 74 and the sidewall wiring 81. The outer opening 89 is formed in a strip or ring shape extending along the outer contact region 74 and the sidewall wiring 81 so as to surround the active surface 8 (active plateau 11) in plan view.

[0213] 14 to 28 , etc., the semiconductor device 1A includes a plurality of resistor openings 90 formed in an interlayer film 86. The plurality of resistor openings 90 penetrate the interlayer film 86 so as to selectively expose the plurality of resistor structures 50. Specifically, the plurality of resistor openings 90 are formed in portions of the interlayer film 86 that cover the plurality of resistor films 85, respectively, and expose the plurality of resistor films 85, respectively.

[0214] The plurality of resistor openings 90 are provided in a one-to-many correspondence with each resistor structure 50, and each resistor structure 50 (each resistor film 85 in this embodiment) is exposed from a plurality of locations. In other words, a plurality of resistor openings 90 are provided corresponding to one resistor structure 50. Specifically, the plurality of resistor openings 90 include a plurality of first resistor openings 91, a plurality of second resistor openings 92, and a plurality of third resistor openings 93.

[0215] In this embodiment, the multiple first resistor openings 91 are provided in a one-to-one correspondence with each resistor structure 50. That is, one first resistor opening 91 is provided corresponding to one resistor structure 50. The multiple first resistor openings 91 expose inner portions of the multiple resistor structures 50 at intervals from both ends of the multiple resistor structures 50. Specifically, the multiple first resistor openings 91 expose inner portions of the multiple resistor films 85 at intervals from both ends of the multiple resistor films 85.

[0216] In this embodiment, the multiple first resistor openings 91 are arranged in a row at intervals in the second direction Y and face each other in the second direction Y. Of course, the multiple first resistor openings 91 may be arranged offset in the first direction X from at least one first resistor opening 91 so as not to face at least one first resistor opening 91 in the second direction Y. In this embodiment, the multiple first resistor openings 91 are formed in a band shape extending in the first direction X in a plan view.

[0217] Of course, the multiple first resistor openings 91 may be formed in a rectangular shape, a polygonal shape, a circle shape, etc. The multiple first resistor openings 91 may be provided in a one-to-many correspondence with each resistor structure 50. In other words, multiple first resistor openings 91 may be provided corresponding to one resistor structure 50. In this case, the multiple first resistor openings 91 are formed at intervals in the first direction X so as to expose the inner portion of the corresponding resistor structure 50 (resistive film 85) from multiple locations.

[0218] In this embodiment, the multiple second resistor openings 92 are provided in a one-to-one correspondence with the resistor structures 50. That is, one second resistor opening 92 is provided corresponding to one resistor structure 50. The multiple second resistor openings 92 are formed at intervals on one side in the first direction X from the multiple first resistor openings 91, and expose regions on one end sides of the multiple resistor structures 50, respectively. Specifically, the multiple second resistor openings 92 expose regions on one end sides of the multiple resistor films 85, respectively.

[0219] In this embodiment, the multiple second resistor openings 92 are arranged in a row at intervals in the second direction Y and face each other in the second direction Y. Of course, the multiple second resistor openings 92 may be arranged offset in the first direction X from at least one second resistor opening 92 so as not to face at least one second resistor opening 92 in the second direction Y. In this embodiment, the multiple second resistor openings 92 are each formed in a strip shape extending in the first direction X in a plan view and each face one first resistor opening 91 corresponding to the first direction X.

[0220] Of course, the multiple second resistor openings 92 may be formed in a rectangular shape, a polygonal shape, a circle shape, etc. The multiple second resistor openings 92 may be provided in a one-to-many correspondence with each resistor structure 50. In other words, multiple second resistor openings 92 may be provided corresponding to one resistor structure 50. In this case, the multiple second resistor openings 92 are formed at intervals in the first direction X so as to expose a region on one end side of the corresponding one resistor structure 50 (resistive film 85) from multiple locations.

[0221] In this embodiment, the multiple third resistor openings 93 are provided in a one-to-one correspondence with each resistor structure 50. That is, one third resistor opening 93 is provided corresponding to one resistor structure 50. The multiple third resistor openings 93 are formed at intervals on the other side in the first direction X from the multiple first resistor openings 91, and expose regions on the other end sides of the multiple resistor structures 50, respectively. Specifically, the multiple third resistor openings 93 expose regions on the other end sides of the multiple resistor films 85, respectively.

[0222] In this embodiment, the multiple third resistor openings 93 are arranged in a row at intervals in the second direction Y and face each other in the second direction Y. Of course, the multiple third resistor openings 93 may be arranged shifted in the first direction X from at least one third resistor opening 93 so as not to face at least one third resistor opening 93 in the second direction Y. In this embodiment, the multiple third resistor openings 93 are each formed in a strip shape extending in the first direction X in a plan view and face each corresponding second resistor opening 92 across one first resistor opening 91 corresponding to the first direction X.

[0223] Of course, the multiple third resistor openings 93 may be formed in a rectangular shape, a polygonal shape, a circle shape, etc. The multiple third resistor openings 93 may be provided in a one-to-many correspondence with each resistor structure 50. In other words, multiple third resistor openings 93 may be provided corresponding to one resistor structure 50. In this case, the multiple third resistor openings 93 are formed at intervals in the first direction X so as to expose the region on the other end side of the corresponding one resistor structure 50 (resistive film 85) from multiple locations.

[0224] The semiconductor device 1A includes a gate electrode 100 disposed on an interlayer film 86. The gate electrode 100 has a resistance value lower than the resistance values ​​of the plurality of resistor structures 50 and the plurality of resistor films 85. The gate electrode 100 includes a gate pad 101 and a gate wiring 102. The gate pad 101 may be referred to as a "pad electrode," a "gate pad electrode," a "control pad electrode," etc. The gate wiring 102 may be referred to as a "wiring electrode," a "gate wiring electrode," a "control wiring electrode," etc.

[0225] The gate pad 101 is an external terminal electrode to which a gate potential is applied from the outside. The gate pad 101 is disposed on the interlayer film 86 and is electrically connected to the plurality of resistive films 85 through the interlayer film 86. That is, the gate pad 101 is electrically connected to the plurality of resistive structures 50 via the plurality of resistive films 85. The gate pad 101 is electrically connected to the plurality of gate structures 25, but does not have any mechanical connection to the plurality of gate structures 25. The gate pad 101 does not have any electrical or mechanical connection to the plurality of source structures 30.

[0226] The gate pad 101 is arranged in a region on one side in the second direction Y of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view. The gate pad 101 is located on the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. In other words, the gate pad 101 faces the center of the first side surface 5A (first connection surface 10A) in the second direction Y in a plan view.

[0227] In this embodiment, the gate pad 101 is arranged on the other side in the second direction Y (inner side of the active region 12) of the resistance region 17 (plurality of resistance structures 50) in plan view. In this embodiment, the gate pad 101 is arranged on the active region 12 at a distance from the first side end region 13, the second side end region 14, the first termination region 15, and the second termination region 16 in plan view.

[0228] The gate pad 101 partially faces the plurality of gate structures 25 and the plurality of source structures 30 with the interlayer film 86 interposed therebetween. The gate pad 101 is disposed inward of the active surface 8 at a distance from the positions of the ends of the plurality of side edge structures 35 in the first direction X in plan view, and faces the plurality of side edge structures 35 in the first direction X. In this embodiment, the gate pad 101 does not face the plurality of side edge structures 35 in the stacking direction.

[0229] The gate pad 101 is disposed inward of the active surface 8 at a distance from both end portions of the plurality of gate structures 25 in the first direction X in a plan view. The gate pad 101 covers the inner portions of the plurality of gate structures 25 with the interlayer film 86 interposed therebetween, and exposes both end portions of the plurality of gate structures 25. The gate pad 101 covers the inner portions of the plurality of source structures 30 with the interlayer film 86 interposed therebetween, and exposes both end portions of the plurality of source structures 30.

[0230] The gate pad 101 is spaced apart from the plurality of termination structures 40 in the second direction Y in plan view, and faces the plurality of termination structures 40 in the second direction Y. In this embodiment, the gate pad 101 does not face the plurality of termination structures 40 in the stacking direction.

[0231] The gate pad 101 faces the body region 21, the source region 22, the plurality of first well regions 65, the plurality of second well regions 66, and the plurality of contact regions 72, with the interlayer film 86 sandwiched therebetween. In this embodiment, the gate pad 101 is disposed on the interlayer film 86 at a distance from the gate connection electrode 83 in the horizontal direction, and does not face the gate connection electrode 83 in the stacking direction. In other words, the gate pad 101 faces a portion of the gate structure 25 that is exposed from the gate connection electrode 83.

[0232] In this embodiment, the gate pad 101 faces in the first direction X a region between at least two gate connection electrodes 83 arranged on both sides of the gate structure 25 in the first direction X in a plan view. The gate pad 101 faces in the second direction Y at least one gate connection electrode 83 arranged in an inner portion of the gate structure 25 in a plan view. Of course, the gate pad 101 may be arranged shifted to one side or the other in the first direction X with respect to an imaginary line that crosses in the second direction Y the gate connection electrode 83 arranged in an inner portion of the gate structure 25 in a plan view.

[0233] The gate pad 101 is disposed on the interlayer film 86 at a horizontal distance from the overlapping portion 82 of the sidewall wiring 81, and does not face the overlapping portion 82 in the stacking direction. In other words, the gate pad 101 is disposed on a region surrounded by the sidewall wiring 81 in a plan view.

[0234] The planar area of ​​the gate pad 101 is smaller than the planar area of ​​the active region 12 and larger than the planar area of ​​the resistor region 17. The proportion of the gate pad 101 in the active surface 8 is preferably 1% or more and 25% or less. The proportion of the gate pad 101 may be a value belonging to any one of the ranges of 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less. The proportion of the gate pad 101 is preferably 10% or less.

[0235] The gate pad 101 has a pad main body 103 (first portion) and a lead portion 104 (second portion). The pad main body 103 forms the main body of the gate pad 101 and is arranged in a region outside the resistor region 17 in a plan view. In this embodiment, the pad main body 103 is arranged in the active region 12 in a plan view and faces the plurality of gate structures 25 and the plurality of source structures 30 with the interlayer film 86 interposed therebetween.

[0236] In this embodiment, the pad body 103 has a pad width WP in the first direction X that is larger than the length of the plurality of resistor structures 50. Of course, the pad width WP may be smaller than the length of the plurality of resistor structures 50. In this embodiment, the pad body 103 is formed in a quadrangular shape in a plan view. Of course, the pad body 103 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, or the like.

[0237] The lead-out portion 104 is provided at the end of the pad body portion 103 on the resistor region 17 side, and is led out from the pad body portion 103 toward the region above the resistor region 17. As a result, the lead-out portion 104 covers the plurality of resistor structures 50 and the plurality of first dummy structures 55 with the interlayer film 86 sandwiched therebetween.

[0238] The lead-out portion 104 has a lead-out width WD in the first direction X that is less than the pad width WP of the pad body portion 103, and is formed in a strip shape extending in the second direction Y. The lead-out portion 104 only needs to have a lead-out width WD that is greater than the opening width of the first resistor opening 91, and the value of the lead-out width WD is arbitrary.

[0239] In this embodiment, the lead-out portions 104 are formed inwardly from both ends of the plurality of resistor structures 50 at intervals in plan view, and cover central portions of the plurality of resistor structures 50. The lead-out portions 104 cover the plurality of first resistor openings 91 at intervals from the plurality of second resistor openings 92 and the plurality of third resistor openings 93 in plan view.

[0240] The lead-out portion 104 extends from above the interlayer film 86 into the plurality of first resistor openings 91, and is mechanically and electrically connected to the plurality of resistor films 85 within the plurality of first resistor openings 91. In other words, the gate pad 101 penetrates the interlayer film 86 and is mechanically and electrically connected to the inner portions of the plurality of resistor films 85.

[0241] The lead-out portion 104 may partially cover the active region 12 and face at least one gate structure 25 and / or at least one source structure 30 across the interlayer film 86. The lead-out portion 104 may partially cover the first termination region 15 and face at least one termination structure 40 across the interlayer film 86.

[0242] The gate wiring 102 is disposed on the interlayer film 86 at a distance from the gate pad 101. In this embodiment, the gate wiring 102 is disposed on the inner part of the active surface 8 at a distance from the periphery of the active surface 8, and is not disposed on the outer circumferential surface 9.

[0243] The gate wiring 102 is disposed on a portion of the interlayer film 86 that covers the active surface 8, and is selectively routed to a region between the active region 12 and the resistance region 17. The gate wiring 102 is electrically connected to the plurality of gate structures 25 in the active region 12, and is electrically connected to the plurality of resistance structures 50 (the plurality of resistance films 85) in the resistance region 17.

[0244] The gate wiring 102 extends in a line shape so as to intersect (specifically, orthogonally intersect) with the plurality of gate structures 25 in the active region 12, and penetrates the interlayer film 86 to be electrically connected to the plurality of gate structures 25. The gate wiring 102 is also electrically connected to the plurality of gate structures 25 located directly below the gate pad 101.

[0245] The gate wiring 102 penetrates the interlayer film 86 in the resistance region 17 and is electrically connected to the plurality of resistance structures 50 (the plurality of resistance films 85). The gate wiring 102 is electrically connected to the gate pad 101 via the plurality of resistance structures 50 (the plurality of resistance films 85), and transmits the gate potential applied to the gate pad 101 to the plurality of gate structures 25.

[0246] In this embodiment, the gate wiring 102 includes a first resistance wiring 105 , a second resistance wiring 106 , a first line wiring 107 , a second line wiring 108 , a third line wiring 109 and a fourth line wiring 110 .

[0247] The first resistance wiring 105 is provided as an electrical connection portion for the multiple resistance structures 50 (multiple resistance films 85). The first resistance wiring 105 is arranged on the interlayer film 86 at a distance from the gate pad 101 on one side in the first direction X. Specifically, the first resistance wiring 105 is arranged at a distance from the lead-out portion 104 on one side in the first direction X, and faces the lead-out portion 104 in the first direction X.

[0248] The first resistance wiring 105 is disposed on a portion of the interlayer film 86 that covers one end of the resistance region 17 (one end of the plurality of resistance structures 50), and covers the plurality of resistance structures 50 and the plurality of first dummy structures 55 with the interlayer film 86 in between. The first resistance wiring 105 may have a portion that covers the plurality of second dummy structures 60 with the interlayer film 86 in between.

[0249] In this embodiment, the first resistance wiring 105 is disposed on the interlayer film 86 at a horizontal distance from the gate connection electrode 83 and does not face the gate connection electrode 83 in the stacking direction. The first resistance wiring 105 is disposed on the interlayer film 86 at a horizontal distance from the overlapping portion 82 of the sidewall wiring 81 and does not face the overlapping portion 82 in the stacking direction.

[0250] The first resistance wiring 105 may partially cover the active region 12 and face at least one gate structure 25 and / or at least one source structure 30 across the interlayer film 86. The first resistance wiring 105 may partially cover the first termination region 15 and face at least one termination structure 40 across the interlayer film 86.

[0251] The first resistance wiring 105 may have any planar shape. In this embodiment, the first resistance wiring 105 is formed in a rectangular shape in a planar view. The first resistance wiring 105 enters the plurality of second resistance openings 92 from above the interlayer film 86 and is mechanically and electrically connected to one end of the plurality of resistance films 85 within the plurality of second resistance openings 92.

[0252] That is, the first resistance wiring 105 is electrically connected to one end of the plurality of resistance structures 50 via one end of the plurality of resistance films 85. The first resistance wiring 105 is electrically connected to the gate pad 101 (the lead-out portion 104) via the plurality of resistance films 85 (the plurality of resistance structures 50).

[0253] The second resistance wiring 106 is provided as an electrical connection portion for the multiple resistance structures 50 (multiple resistance films 85). The second resistance wiring 106 is arranged on the interlayer film 86 at a distance from the gate pad 101 on the other side in the first direction X. Specifically, the second resistance wiring 106 is arranged at a distance from the drawn-out portion 104 on the other side in the first direction X, and faces the first resistance wiring 105 across the drawn-out portion 104 in the first direction X.

[0254] The second resistance wiring 106 is disposed on a portion of the interlayer film 86 that covers the other end of the resistance region 17 (the other ends of the plurality of resistance structures 50), and covers the plurality of resistance structures 50 and the plurality of first dummy structures 55 with the interlayer film 86 in between. The second resistance wiring 106 may have a portion that covers the plurality of second dummy structures 60 with the interlayer film 86 in between.

[0255] In this embodiment, the second resistance wiring 106 is disposed on the interlayer film 86 at a horizontal distance from the gate connection electrode 83 and does not face the gate connection electrode 83 in the stacking direction. The second resistance wiring 106 is disposed on the interlayer film 86 at a horizontal distance from the overlapping portion 82 of the sidewall wiring 81 and does not face the overlapping portion 82 in the stacking direction.

[0256] The second resistance wiring 106 may partially cover the active region 12 and face at least one gate structure 25 and / or at least one source structure 30 across the interlayer film 86. The second resistance wiring 106 may partially cover the first termination region 15 and face at least one termination structure 40 across the interlayer film 86.

[0257] The second resistance wiring 106 may have any planar shape. In this embodiment, the second resistance wiring 106 is formed in a rectangular shape in plan view. The second resistance wiring 106 enters the third resistance openings 93 from above the interlayer film 86 and is mechanically and electrically connected to the other ends of the resistance films 85 within the third resistance openings 93.

[0258] That is, the second resistance wiring 106 is electrically connected to the other ends of the plurality of resistance structures 50 via the other ends of the plurality of resistance films 85. The second resistance wiring 106 is electrically connected to the gate pad 101 via the plurality of resistance films 85 (the plurality of resistance structures 50).

[0259] The first line wiring 107 is drawn out from the first resistance wiring 105 to one side in the first direction X, and is electrically connected to one end of the plurality of resistance structures 50 (plurality of resistance films 85) via the first resistance wiring 105. In plan view, the first line wiring 107 is drawn out from the resistance region 17 into the active region 12 via the first dummy region 18, and extends in a line along the periphery of the active region 12.

[0260] The first line wiring 107 has a first extension portion 107 a and a second extension portion 107 b. The first extension portion 107 a is drawn out in a line shape in the first direction X from the first resistance wiring 105 toward a region above the first dummy region 18, and faces the plurality of first dummy structures 55 and the plurality of second dummy structures 60 with the interlayer film 86 interposed therebetween.

[0261] The tip end of the first extension portion 107a is formed at a distance from the third connecting surface 10C inward of the active surface 8 in plan view. The tip end of the first extension portion 107a may be formed at a distance from the end positions of the multiple side edge structures 35 in the first direction X inward of the active surface 8.

[0262] The second extension portion 107b is drawn out from the tip of the first extension portion 107a in the second direction Y and extends linearly along the third side surface 5C (third connection surface 10C). The second extension portion 107b intersects (specifically, is perpendicular to) one ends of the plurality of gate structures 25 and one ends of the plurality of source structures 30 in the second direction Y in plan view.

[0263] The second extension portion 107b is formed at a distance inward from the positions of the ends of the plurality of side edge structures 35 in the first direction X toward the active surface 8 in plan view, and does not face the plurality of side edge structures 35 in the stacking direction. Of course, a portion of the second extension portion 107b may be drawn out from the active region 12 to the first side edge region 13 and face the plurality of side edge structures 35. The tip portion of the second extension portion 107b may be located above the active region 12 or above the second termination region 16.

[0264] The second extension portion 107b enters the plurality of gate openings 87 from above the interlayer film 86, and is electrically connected to one end of the plurality of gate structures 25 in the plurality of gate openings 87. Specifically, the second extension portion 107b is connected to the plurality of gate connection electrodes 83 in the plurality of gate openings 87.

[0265] As a result, the first line wiring 107 is electrically connected to one ends of the plurality of gate structures 25 via the plurality of gate connection electrodes 83. In this embodiment, the first line wiring 107 (second extension portion 107b) is also electrically connected to one ends of the plurality of gate structures 25 located directly below the gate pad 101.

[0266] The second line wiring 108 is drawn out from the second resistance wiring 106 to the other side in the first direction X, and is electrically connected to the other ends of the plurality of resistance structures 50 (the plurality of resistance films 85) via the second resistance wiring 106. In plan view, the second line wiring 108 is drawn out from the resistance region 17 into the active region 12 via the second dummy region 19, and extends in a line along the periphery of the active region 12.

[0267] The second line wiring 108 has a third extension portion 108 a and a fourth extension portion 108 b. The third extension portion 108 a is drawn out in a line shape in the first direction X from the second resistance wiring 106 toward a region above the second dummy region 19, and faces the plurality of first dummy structures 55 and the plurality of second dummy structures 60 with the interlayer film 86 interposed therebetween.

[0268] The tip end of the third extension portion 108a is formed at a distance from the fourth connection surface 10D inward of the active surface 8 in plan view. The tip end of the third extension portion 108a may be formed at a distance from the end positions of the multiple side edge structures 35 in the first direction X inward of the active surface 8.

[0269] The fourth extension portion 108b is drawn out from the tip of the third extension portion 108a in the second direction Y and extends linearly along the fourth side surface 5D (fourth connection surface 10D). The fourth extension portion 108b intersects (specifically, is perpendicular to) the other ends of the plurality of gate structures 25 and the other ends of the plurality of source structures 30 in the second direction Y in plan view.

[0270] The fourth extension portion 108b is formed inward of the active surface 8 at a distance from the positions of the ends of the plurality of side edge structures 35 in the first direction X in plan view, and does not face the plurality of side edge structures 35 in the stacking direction. Of course, a portion of the fourth extension portion 108b may be drawn out from the active region 12 to the second side edge region 14 and face the plurality of side edge structures 35. The tip portion of the fourth extension portion 108b may be located above the active region 12 or above the second termination region 16.

[0271] The fourth extension portion 108b enters the plurality of gate openings 87 from above the interlayer film 86, and is electrically connected to the other ends of the plurality of gate structures 25 in the plurality of gate openings 87. Specifically, the fourth extension portion 108b is connected to the plurality of gate connection electrodes 83 in the plurality of gate openings 87.

[0272] As a result, the second line wiring 108 is electrically connected to the other ends of the plurality of gate structures 25 via the plurality of gate connection electrodes 83. In this embodiment, the second line wiring 108 (fourth extension portion 108b) is also electrically connected to one ends of the plurality of gate structures 25 located directly below the gate pad 101.

[0273] The third line wiring 109 is routed in a line shape around the gate pad 101 and is connected to the first resistance wiring 105 and the second resistance wiring 106. The third line wiring 109 is electrically connected to the plurality of resistance structures 50 (the plurality of resistance films 85) via the first resistance wiring 105 and the second resistance wiring 106.

[0274] Specifically, the third line wiring 109 includes a first line portion 109 a, a second line portion 109 b, and a third line portion 109 c. The first line portion 109 a is drawn out in a line shape extending in the second direction Y from the first resistance wiring 105 on one side (the third side surface 5C side) in the first direction X with respect to the gate pad 101.

[0275] In plan view, the first line portion 109a intersects (specifically, orthogonally) with inner portions of the plurality of gate structures 25 and inner portions of the plurality of source structures 30. The first line portion 109a extends from above the interlayer film 86 into the plurality of gate openings 87 and is electrically connected to the inner portions of the plurality of gate structures 25 within the plurality of gate openings 87.

[0276] Specifically, the first line portion 109a is connected to the plurality of gate connection electrodes 83 within the plurality of gate openings 87, and is electrically connected to inner portions of the plurality of gate structures 25 via the plurality of gate connection electrodes 83. In this embodiment, the first line portion 109a is also electrically connected to portions of the plurality of gate structures 25 located directly below the gate pad 101 that are exposed from the gate pad 101.

[0277] The second line portion 109b is drawn out in a line shape extending in the second direction Y from the second resistance wiring 106 on the other side in the first direction X (the fourth side surface 5D side) with respect to the gate pad 101. The second line portion 109b intersects (specifically, is perpendicular to) the inner portions of the plurality of gate structures 25 and the inner portions of the plurality of source structures 30 in a plan view. The second line portion 109b enters the plurality of gate openings 87 from above the interlayer film 86 and is electrically connected to the inner portions of the plurality of gate structures 25 within the plurality of gate openings 87.

[0278] Specifically, the second line portion 109b is connected to the plurality of gate connection electrodes 83 within the plurality of gate openings 87, and is electrically connected to inner portions of the plurality of gate structures 25 via the plurality of gate connection electrodes 83. In this embodiment, the second line portion 109b is also electrically connected to portions of the plurality of gate structures 25 located directly below the gate pad 101 that are exposed from the gate pad 101.

[0279] The third line portion 109c is formed in a line shape extending in the first direction X on the other side (the second side surface 5B side) of the gate pad 101 in the second direction Y, and is connected to the first line portion 109a and the second line portion 109b. That is, the third line portion 109c (third line wiring 109) electrically connects the first resistance wiring 105 and the second resistance wiring 106. The third line portion 109c faces the plurality of gate structures 25 and the plurality of source structures 30 in the stacking direction.

[0280] The fourth line wiring 110 is disposed in a region on the other side in the second direction Y (toward the second side surface 5B) of the gate pad 101, and extends in a line shape in the second direction Y through the region between the gate pad 101 and the second connection surface 10B. Specifically, the fourth line wiring 110 is drawn out from the third line wiring 109 (third line portion 109c) toward the inner portion of the active region 12, and is electrically connected to the plurality of resistance structures 50 (the plurality of resistance films 85) via the first resistance wiring 105, the second resistance wiring 106, and the third line wiring 109.

[0281] The fourth line wiring 110 intersects (specifically, orthogonally) with inner portions of the plurality of gate structures 25 and inner portions of the plurality of source structures 30 in a plan view. The fourth line wiring 110 enters the plurality of gate openings 87 from above the interlayer film 86 and is electrically connected to inner portions of the plurality of gate structures 25 within the plurality of gate openings 87. Specifically, the fourth line wiring 110 is connected to the plurality of gate connection electrodes 83 within the plurality of gate openings 87 and is electrically connected to the inner portions of the plurality of gate structures 25 via the plurality of gate connection electrodes 83.

[0282] 14 and 15 , in this embodiment, the gate electrode 100 includes a gate subpad 111 arranged on the interlayer film 86 at a distance from the gate pad 101. The gate subpad 111 may be referred to as a "subpad electrode" or the like. The presence or absence of the gate subpad 111 is optional, and it may be omitted as necessary.

[0283] The gate subpad 111 is a pad (dummy pad) for electrical testing to measure the gate resistance RG during the manufacturing process, and is electrically connected to the gate pad 101 via a plurality of resistive structures 50 (a plurality of resistive films 85). In the electrical test, a test signal is applied between the gate pad 101 and the gate subpad 111.

[0284] For example, a gate potential may be applied to either the gate pad 101 or the gate subpad 111, and a ground potential may be applied to the other. In other words, the gate subpad 111 is a terminal to which a potential different from that of the gate pad 101 is applied. The gate subpad 111 is an open terminal after the manufacturing process, and is excluded from the targets for connection of conductive bonding members such as bonding wires.

[0285] For example, when the semiconductor device 1A is mounted in a semiconductor package, the entire area of ​​the gate subpad 111 is directly or indirectly covered with an insulator (e.g., a sealing resin containing a plurality of fillers and a matrix resin) to electrically insulate it from other structures. Of course, the gate subpad 111 may be electrically connected to a lead terminal of the semiconductor package via a bonding wire or the like so that a test signal can be input even after the semiconductor device 1A is mounted in the semiconductor package.

[0286] The location of the gate subpad 111 is arbitrary. The gate subpad 111 is disposed in a region on one side in the second direction Y (the first side surface 5A side) of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view. In this embodiment, the gate subpad 111 is disposed shifted to one side or the other in the first direction X with respect to the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.

[0287] The gate subpad 111 may be arranged on at least one of the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the first dummy region 18, the second dummy region 19, and the peripheral region 20. In this embodiment, the gate subpad 111 is arranged on the active region 12 at a distance from the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the resistor region 17, the first dummy region 18, and the second dummy region 19 in a plan view.

[0288] In this embodiment, the gate subpad 111 is disposed at a distance from the gate pad 101 on one side in the first direction X (the third connection surface 10C side), and faces the gate pad 101 in the first direction X. The gate subpad 111 has a planar area smaller than the planar area of ​​the gate pad 101. The gate subpad 111 is formed narrower than the gate pad 101 and wider than the gate wiring 102 (first resistance wiring 105) in the second direction Y.

[0289] The gate subpad 111 partially faces the plurality of gate structures 25 and the plurality of source structures 30 with the interlayer film 86 interposed therebetween. The gate subpad 111 is disposed inward of the active surface 8 at a distance from the positions of the ends of the plurality of side edge structures 35 in the first direction X in plan view, and faces the plurality of side edge structures 35 in the first direction X. The gate subpad 111 does not face the plurality of side edge structures 35 in the stacking direction.

[0290] The gate subpad 111 is arranged inward of the active surface 8 at a distance from both ends of the plurality of gate structures 25 in the first direction X in a plan view. The gate subpad 111 covers the inner parts of the plurality of gate structures 25 with the interlayer film 86 therebetween, and exposes both ends of the plurality of gate structures 25. The gate subpad 111 covers the inner parts of the plurality of source structures 30 with the interlayer film 86 therebetween, and exposes both ends of the plurality of source structures 30.

[0291] The gate subpad 111 faces the body region 21, the source region 22, the plurality of first well regions 65, the plurality of second well regions 66, and the plurality of contact regions 72, with the interlayer film 86 sandwiched therebetween. In this embodiment, the gate subpad 111 is disposed on the interlayer film 86 at a distance from the gate connection electrode 83 in the horizontal direction, and does not face the gate connection electrode 83 in the stacking direction. In other words, the gate subpad 111 faces a portion of the gate structure 25 that is exposed from the gate connection electrode 83.

[0292] The gate subpad 111 is disposed on the interlayer film 86 at a horizontal distance from the overlapping portion 82 of the sidewall wiring 81, and does not face the overlapping portion 82 in the stacking direction. In other words, the gate subpad 111 is disposed on a region surrounded by the sidewall wiring 81 in a plan view.

[0293] In this embodiment, the gate subpad 111 is connected to the gate wiring 102. That is, the gate subpad 111 is fixed to the same potential as the gate wiring 102, and is electrically connected to the plurality of resistance structures 50 (the plurality of resistance films 85) via the gate wiring 102. In consideration of the wiring resistance of the gate wiring 102, it is preferable that the gate subpad 111 be connected to a portion of the gate wiring 102 that is located in the vicinity of the resistance region 17.

[0294] For example, the gate subpad 111 is preferably connected to the first resistance wiring 105, the second resistance wiring 106, the first extension portion 107a of the first line wiring 107, the third extension portion 108a of the second line wiring 108, the first line portion 109a of the third line wiring 109, the second line portion 109b of the third line wiring 109, etc. In this embodiment, the gate subpad 111 is connected to the third line wiring 109 (first line portion 109a).

[0295] The gate electrode 100 preferably has a thickness greater than that of the resistive film 85. The gate electrode 100 preferably has a thickness greater than that of the interlayer film 86. The thickness of the gate electrode 100 may be 0.5 μm or more and 10 μm or less. The thickness of the gate electrode 100 is preferably 1 μm or more and 5 μm or less.

[0296] In this embodiment, the gate electrode 100 has a laminated structure including a first electrode film 112 and a second electrode film 113 laminated in this order from the interlayer film 86 side. The first electrode film 112 is formed as a barrier electrode. The first electrode film 112 includes at least one of a Ti film, a TiN film, and a W film. In this embodiment, the first electrode film 112 includes a Ti film.

[0297] The second electrode film 113 has a thickness greater than that of the first electrode film 112 and forms the main body of the gate electrode 100. The second electrode film 113 includes at least one of an Al film, a Cu film, an Al alloy film, and a Cu alloy film. The second electrode film 113 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 113 includes an Al alloy film (an AlSiCu alloy film in this embodiment).

[0298] The first electrode film 112 of the gate pad 101 covers the interlayer film 86 in the pad body 103 in a film-like manner, and extends into the first resistor openings 91 from above the interlayer film 86 in the lead-out portion 104. The first electrode film 112 of the gate pad 101 covers the opening wall surfaces of the first resistor openings 91 in a film-like manner, and covers the resistor films 85 in a film-like manner.

[0299] The second electrode film 113 of the gate pad 101 covers the first electrode film 112 in the pad body portion 103 in a film-like manner, and faces the interlayer film 86 with the first electrode film 112 sandwiched therebetween. The second electrode film 113 of the gate pad 101 covers the first electrode film 112 in the extension portion 104 in a film-like manner, and backfills the multiple first resistor openings 91. The second electrode film 113 of the gate pad 101 is electrically connected to the resistor film 85 via the first electrode film 112 in the multiple first resistor openings 91.

[0300] The first electrode film 112 of the gate wiring 102 covers the interlayer film 86 in a film form, and extends from above the interlayer film 86 into the plurality of gate openings 87, the plurality of second resistor openings 92, and the plurality of third resistor openings 93. The first electrode film 112 of the gate wiring 102 covers the opening wall surfaces of the plurality of gate openings 87 in a film form, and also covers the plurality of gate connection electrodes 83 in a film form. The first electrode film 112 of the gate wiring 102 covers the opening wall surfaces of the plurality of second resistor openings 92 and the opening wall surfaces of the plurality of third resistor openings 93 in a film form, and also covers the plurality of resistor films 85 in a film form.

[0301] The second electrode film 113 of the gate wiring 102 backfills the plurality of gate openings 87, the plurality of second resistor openings 92, and the plurality of third resistor openings 93 with the first electrode film 112 of the gate wiring 102 sandwiched therebetween, and covers the first electrode film 112 in a film form on the interlayer film 86. The second electrode film 113 of the gate wiring 102 is electrically connected to the plurality of gate connection electrodes 83 and the plurality of resistor films 85 via the first electrode film 112.

[0302] The semiconductor device 1A includes a source electrode 120 disposed on the interlayer film 86 at a distance from the gate electrode 100. The source electrode 120 has a resistance value lower than that of the resistive film 85. In this embodiment, the source electrode 120 includes at least one (in this embodiment, multiple) source pad 121 and source wiring 122. The source pad 121 may be referred to as a "low-potential pad electrode," a "source pad electrode," or the like. The source wiring 122 may be referred to as a "low-potential wiring electrode," a "source wiring electrode," or the like.

[0303] The source pad 121 includes a first source pad 121A and a second source pad 121B. The first source pad 121A is disposed in a region on one side in the first direction X on a portion of the interlayer film 86 that covers the active region 12. Specifically, the first source pad 121A is disposed in a region defined by the first line wiring 107, the third line wiring 109, and the fourth line wiring 110.

[0304] The first source pad 121A has a planar area that is larger than the planar area of ​​the resistor region 17 and smaller than the planar area of ​​the active region 12. The planar area of ​​the first source pad 121A is larger than the planar area of ​​the gate pad 101. The proportion of the active surface 8 (first main surface 3) occupied by the first source pad 121A is preferably 25% or more and 50% or less.

[0305] The first source pad 121A is disposed on the active region 12 at a distance from the first side edge region 13 in a plan view. That is, the first source pad 121A is disposed at a distance inward from the ends of the side edge structures 35 in the first direction X toward the active surface 8 in a plan view, and faces the side edge structures 35 in the first direction X. The first source pad 121A does not face the side edge structures 35 in the stacking direction.

[0306] The first source pad 121A partially faces the plurality of gate structures 25 and the plurality of source structures 30 across the interlayer film 86. The first source pad 121A is disposed inward of the active surface 8 at a distance from both end positions of the plurality of gate structures 25 in the first direction X in plan view.

[0307] The first source pad 121A covers the inner portions of the plurality of gate structures 25 with the interlayer film 86 interposed therebetween, and exposes both ends of the plurality of gate structures 25. The first source pad 121A covers the inner portions of the plurality of source structures 30 with the interlayer film 86 interposed therebetween, and exposes both ends of the plurality of source structures 30.

[0308] The first source pad 121A extends from above the interlayer film 86 into the source openings 88 and is electrically connected to the source structures 30, the source regions 22, and the contact regions 72 within the source openings 88.

[0309] In this embodiment, the first source pad 121A includes a first pad portion 121a and a second pad portion 121b. A source potential for the main source may be applied to the first pad portion 121a from an external source. A source potential for source sensing may be applied to the second pad portion 121b from an external source. Of course, a source potential for the main source may also be applied to the second pad portion 121b.

[0310] The first pad portion 121a is located in an area on the other side (second side surface 5B side) of the gate pad 101 in the second direction Y, and faces the gate pad 101 in the second direction Y. The second pad portion 121b is located in an area on one side (third side surface 5C side) of the gate pad 101 in the first direction X, and faces the gate pad 101 in the first direction X.

[0311] Specifically, the second pad portion 121b faces the gate pad 101 in the first direction X, with a part of the gate wiring 102 (the third line wiring 109) sandwiched therebetween. The second pad portion 121b may face at least one resistor structure 50 (at least one resistor film 85) in the first direction X in a plan view.

[0312] In this embodiment, the second pad portion 121b faces the gate pad 101 across the gate subpad 111 in plan view. The portion of the second pad portion 121b that is along the gate subpad 111 is recessed in a rectangular shape along the gate subpad 111 in plan view.

[0313] The second pad portion 121b may be extended from the active region 12 to the first dummy region 18 and cover at least one first dummy structure 55. Of course, the second pad portion 121b may also cover at least one second dummy structure 60.

[0314] In this embodiment, the second pad portion 121b is connected to a portion of at least one (a plurality of in this embodiment) source structure 30 arranged directly below the gate pad 101 that is exposed from the gate pad 101, via at least one (a plurality of in this embodiment) source opening 88. The second pad portion 121b is also connected to the source region 22 and the contact region 72 that are located along the plurality of source structures 30 arranged directly below the gate pad 101.

[0315] The second source pad 121B is disposed in a region on the other side in the first direction X on a portion of the interlayer film 86 that covers the active region 12. Specifically, the second source pad 121B is disposed in a region defined by the second line wiring 108, the third line wiring 109, and the fourth line wiring 110, and faces the first source pad 121A in the first direction X.

[0316] The second source pad 121B has a planar area that is larger than the planar area of ​​the resistor region 17 and smaller than the planar area of ​​the active region 12. The planar area of ​​the second source pad 121B is larger than the planar area of ​​the gate pad 101. The proportion of the active surface 8 (first main surface 3) occupied by the second source pad 121B is preferably 25% or more and 50% or less.

[0317] The second source pad 121B is disposed on the active region 12 at a distance from the second side edge region 14 in a plan view. That is, the second source pad 121B is disposed at a distance inward from the ends of the plurality of side edge structures 35 in the first direction X on the active surface 8 in a plan view, and faces the plurality of side edge structures 35 in the first direction X. The second source pad 121B does not face the plurality of side edge structures 35 in the stacking direction.

[0318] The second source pad 121B partially faces the plurality of gate structures 25 and the plurality of source structures 30 across the interlayer film 86. The second source pad 121B is disposed inward of the active surface 8 at a distance from both end positions of the plurality of gate structures 25 in the first direction X in plan view.

[0319] The second source pad 121B covers the inner portions of the plurality of gate structures 25 with the interlayer film 86 interposed therebetween, and exposes both ends of the plurality of gate structures 25. The second source pad 121B covers the inner portions of the plurality of source structures 30 with the interlayer film 86 interposed therebetween, and exposes both ends of the plurality of source structures 30.

[0320] The second source pad 121B extends from above the interlayer film 86 into the source openings 88 and is electrically connected to the source structures 30, the source regions 22 and the contact regions 72 within the source openings 88.

[0321] In this embodiment, the second source pad 121B includes a third pad portion 121c and a fourth pad portion 121d. A source potential for the main source may be applied to the third pad portion 121c from the outside. A source potential for source sensing may be applied to the fourth pad portion 121d from the outside. Of course, a source potential for the main source may also be applied to the fourth pad portion 121d.

[0322] The third pad portion 121c is located in an area on the other side in the second direction Y (toward the second side surface 5B) of the gate pad 101, faces the first pad portion 121a in the first direction X, and faces the gate pad 101 in the second direction Y. The fourth pad portion 121d is located in an area on the other side in the first direction X (toward the fourth side surface 5D) of the gate pad 101, and faces the second pad portion 121b in the first direction X across the gate pad 101.

[0323] Specifically, the fourth pad portion 121d faces the gate pad 101 in the first direction X, with a part of the gate wiring 102 (the third line wiring 109) sandwiched therebetween. The fourth pad portion 121d may face at least one resistor structure 50 (at least one resistor film 85) in the first direction X in a plan view.

[0324] The fourth pad portion 121d may be extended from the active region 12 to the second dummy region 19 and cover at least one first dummy structure 55. Of course, the fourth pad portion 121d may also cover at least one second dummy structure 60.

[0325] In this embodiment, the fourth pad portion 121d is connected to a portion of at least one (a plurality of) source structures 30 arranged directly below the gate pad 101 that is exposed from the gate pad 101, via at least one (a plurality of) source openings 88. The second source pad 121B is also connected to the source region 22 and the contact region 72 that are located along the plurality of source structures 30 arranged directly below the gate pad 101.

[0326] The source wiring 122 transmits the source potential applied to the source pad 121 to other regions. In this embodiment, the source wiring 122 is drawn out from the source pad 121 onto the interlayer film 86 so as to be located closer to the outer periphery region 20 than the gate wiring 102. The source wiring 122 is drawn out from the active surface 8 side to the outer periphery surface 9 side, passing through the first to fourth connecting surfaces 10A to 10D.

[0327] The source wiring 122 is formed in a strip shape extending along the first to fourth connecting faces 10A to 10D, and faces the sidewall wiring 81 across the interlayer film 86. In this embodiment, the source wiring 122 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connecting faces 10A to 10D.

[0328] The source wiring 122 covers the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the first dummy region 18, and the second dummy region 19 on the active surface 8, and surrounds the active region 12. In other words, the source wiring 122 surrounds the resistive film 85, the gate pad 101, the gate wiring 102, and the plurality of source pads 121. The source wiring 122 is disposed closer to the outer circumferential surface 9 than the resistive film 85, and has a portion facing the resistive film 85 in the second direction Y.

[0329] The source wiring 122 enters the outer opening 89 from above the interlayer film 86 in the peripheral region 20, and is electrically connected to the outer contact region 74 and the sidewall wiring 81 within the outer opening 89. The source potential applied to the source pad 121 is transmitted to the sidewall wiring 81 via the source wiring 122. The source potential applied to the sidewall wiring 81 is transmitted from the peripheral region 20 to the plurality of source structures 30, the plurality of side end structures 35, the plurality of termination structures 40, the plurality of first dummy structures 55, and the plurality of second dummy structures 60.

[0330] The source electrode 120 preferably has a thickness greater than that of the resistive film 85. The thickness of the source electrode 120 is preferably greater than that of the interlayer film 86. The thickness of the source electrode 120 is preferably approximately equal to that of the gate electrode 100. The thickness of the source electrode 120 may be 0.5 μm or more and 10 μm or less. The thickness of the source electrode 120 is preferably 1 μm or more and 5 μm or less.

[0331] In this embodiment, the source electrode 120 has a laminated structure including a first electrode film 123 and a second electrode film 124 laminated in this order from the interlayer film 86 side. The first electrode film 123 is formed as a barrier electrode. The first electrode film 123 includes at least one of a Ti film, a TiN film, and a W film. In this embodiment, the first electrode film 123 includes a Ti film. It is preferable that the first electrode film 123 has a thickness approximately equal to that of the first electrode film 112 of the gate electrode 100.

[0332] The second electrode film 124 has a thickness greater than that of the first electrode film 123 and forms the main body of the source electrode 120. The second electrode film 124 preferably has a thickness approximately equal to that of the second electrode film 113 of the gate electrode 100. The second electrode film 124 includes at least one of an Al film, a Cu film, an Al alloy film, and a Cu alloy film.

[0333] The second electrode film 124 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 124 includes an Al alloy film (an AlSiCu alloy film in this embodiment).

[0334] The semiconductor device 1A includes a pad insulating film 130 that selectively covers the gate electrode 100, the source electrode 120, and the interlayer film 86. With respect to the gate electrode 100, the pad insulating film 130 covers the periphery of the gate pad 101, the periphery of the gate subpad 111, and the entire area of ​​the gate wiring 102.

[0335] In this embodiment, the pad insulating film 130 covers the lead-out portion 104 of the gate pad 101. That is, the pad insulating film 130 covers the connection portion (i.e., the lead-out portion 104) of the gate pad 101 to the plurality of resistance structures 50 (plurality of resistance films 85). The pad insulating film 130 covers the first resistance wiring 105 and the second resistance wiring 106. That is, the pad insulating film 130 covers the connection portion (i.e., the first resistance wiring 105 and the second resistance wiring 106) of the gate wiring 102 to the plurality of resistance structures 50 (plurality of resistance films 85).

[0336] The pad insulating film 130 covers a gap portion of the interlayer film 86 that is exposed from a region between the gate pad 101 (the lead portion 104) and the gate wiring 102 (the first resistance wiring 105 and the second resistance wiring 106), and covers the plurality of resistance structures 50 (the plurality of resistance films 85) across the gap portion. The pad insulating film 130 preferably covers the entire area of ​​the plurality of resistance structures 50 (the plurality of resistance films 85) in a plan view.

[0337] The pad insulating film 130 has a gate pad opening 131 that exposes the inner part of the gate pad 101 and a gate subpad opening 132 that exposes the inner part of the gate subpad 111 .

[0338] The gate pad opening 131 is formed in a quadrangular shape in a plan view, and exposes the pad body portion 103 of the gate pad 101. The gate pad opening 131 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, etc. in a plan view. The gate subpad opening 132 is formed in a quadrangular shape in a plan view, and has a planar area smaller than the planar area of ​​the gate pad opening 131. The gate subpad opening 132 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, etc. in a plan view.

[0339] With respect to the source electrode 120, the pad insulating film 130 covers the peripheral portion of the first source pad 121A, the peripheral portion of the second source pad 121B, and the entire area of ​​the source wiring 122. The pad insulating film 130 includes a first source pad opening 133 exposing the first pad portion 121a, a second source pad opening 134 exposing the second pad portion 121b, a third source pad opening 135 exposing the third pad portion 121c, and a fourth source pad opening 136 exposing the fourth pad portion 121d.

[0340] The second source pad opening 134 is spaced apart from the first source pad opening 133 and exposes the second pad portion 121b, and the fourth source pad opening 136 is spaced apart from the third source pad opening 135 and exposes the fourth pad portion 121d.

[0341] The first to fourth source pad openings 133 to 136 preferably have a planar area larger than the planar area of ​​the gate subpad opening 132. The planar areas of the first to fourth source pad openings 133 to 136 are preferably larger than the planar area of ​​the gate pad opening 131. Of course, the planar areas of the second source pad opening 134 and the fourth source pad opening 136 may be smaller than the planar area of ​​the gate pad opening 131.

[0342] The planar area of ​​the second source pad opening 134 is preferably less than the planar area of ​​the first source pad opening 133. The planar area of ​​the third source pad opening 135 is preferably greater than the planar area of ​​the second source pad opening 134. The planar area of ​​the third source pad opening 135 is preferably approximately equal to the planar area of ​​the first source pad opening 133.

[0343] The planar area of ​​the fourth source pad opening 136 is preferably less than the planar area of ​​the third source pad opening 135. The planar area of ​​the fourth source pad opening 136 is preferably approximately equal to the planar area of ​​the second source pad opening 134. The first to fourth source pad openings 133 to 136 are formed in a quadrangular shape in a planar view. The first to fourth source pad openings 133 to 136 may be formed in a polygonal shape other than a quadrangular shape, a circular shape, or the like in a planar view.

[0344] In this embodiment, the second source pad opening 134 is formed spaced apart from the first source pad opening 133. However, the second source pad opening 134 may be connected to the first source pad opening 133 and form one pad opening together with the first source pad opening 133. Similarly, the fourth source pad opening 136 may be connected to the third source pad opening 135 and form one pad opening together with the third source pad opening 135.

[0345] The pad insulating film 130 covers the outer well region 73, the outer contact region 74, and the plurality of field regions 75 with the interlayer film 86 sandwiched therebetween in the peripheral region 20. The pad insulating film 130 covers the sidewall wiring 81 with the interlayer film 86 and the source wiring 122 sandwiched therebetween at the first to fourth connecting surfaces 10A to 10D.

[0346] The pad insulating film 130 is formed in the outer peripheral region 20 at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2, and defines a dicing street 137 between the pad insulating film 130 and the periphery of the chip 2. The dicing street 137 is formed in a band shape extending along the periphery of the chip 2 in a plan view. In this embodiment, the dicing street 137 is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 8 in a plan view. In this embodiment, the dicing street 137 exposes the interlayer film 86.

[0347] Of course, when the main surface insulating film 80 and the interlayer film 86 expose the outer peripheral surface 9, the dicing street 137 may also expose the outer peripheral surface 9. The dicing street 137 may have a width of 1 μm or more and 200 μm or less. The width of the dicing street 137 is the width in a direction perpendicular to the extension direction of the dicing street 137. The width of the dicing street 137 is preferably 5 μm or more and 50 μm or less.

[0348] The pad insulating film 130 preferably has a thickness greater than the thickness of the gate electrode 100 and the thickness of the source electrode 120. The thickness of the pad insulating film 130 is preferably greater than the total thickness of the gate electrode 100 and the source electrode 120. The thickness of the pad insulating film 130 is preferably less than the thickness of the chip 2. The thickness of the pad insulating film 130 may be 3 μm or more and 35 μm or less. The thickness of the pad insulating film 130 is preferably 25 μm or less.

[0349] In this embodiment, the pad insulating film 130 has a laminated structure including an inorganic insulating film 141 and an organic insulating film 142 laminated in this order from the chip 2 side (interlayer film 86 side). The pad insulating film 130 only needs to include at least one of the inorganic insulating film 141 and the organic insulating film 142, and does not necessarily need to include both the inorganic insulating film 141 and the organic insulating film 142 at the same time.

[0350] The inorganic insulating film 141 selectively covers the gate electrode 100, the source electrode 120, and the interlayer film 86, and defines a part of the gate pad opening 131, a part of the gate subpad opening 132, a part of the first source pad opening 133, a part of the second source pad opening 134, a part of the third source pad opening 135, a part of the fourth source pad opening 136, and a part of the dicing street 137.

[0351] The inorganic insulating film 141 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 141 preferably includes an insulating material different from that of the interlayer film 86. The inorganic insulating film 141 preferably includes a silicon nitride film. The inorganic insulating film 141 preferably has a thickness less than that of the interlayer film 86. The thickness of the inorganic insulating film 141 may be 0.1 μm or more and 5 μm or less.

[0352] The organic insulating film 142 selectively covers the inorganic insulating film 141 and defines a portion of the gate pad opening 131, a portion of the gate subpad opening 132, a portion of the first source pad opening 133, a portion of the second source pad opening 134, a portion of the third source pad opening 135, a portion of the fourth source pad opening 136, and a portion of the dicing street 137.

[0353] The organic insulating film 142 may expose the inorganic insulating film 141 at the wall surface of the gate pad opening 131. The organic insulating film 142 may expose the inorganic insulating film 141 at the wall surface of the gate subpad opening 132. The organic insulating film 142 may expose the inorganic insulating film 141 at the wall surface of the first source pad opening 133. The organic insulating film 142 may expose the inorganic insulating film 141 at the wall surface of the second source pad opening 134.

[0354] The organic insulating film 142 may expose the inorganic insulating film 141 at the wall surface of the third source pad opening 135. The organic insulating film 142 may expose the inorganic insulating film 141 at the wall surface of the fourth source pad opening 136. The organic insulating film 142 may expose the inorganic insulating film 141 at the wall surface of the dicing street 137. Of course, the organic insulating film 142 may cover the entire area of ​​the inorganic insulating film 141 so that the inorganic insulating film 141 is not exposed.

[0355] The organic insulating film 142 is preferably made of a resin film other than a thermosetting resin. The organic insulating film 142 may be made of a light-transmitting resin or a transparent resin. The organic insulating film 142 may be made of a negative-type or positive-type photosensitive resin film. The organic insulating film 142 is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film.

[0356] The organic insulating film 142 preferably has a thickness greater than that of the inorganic insulating film 141. The organic insulating film 142 preferably has a thickness greater than that of the interlayer film 86. The organic insulating film 142 particularly preferably has a thickness greater than that of the gate electrode 100 and that of the source electrode 120. The thickness of the organic insulating film 142 may be 3 μm or more and 30 μm or less. The thickness of the organic insulating film 142 is preferably 20 μm or less.

[0357] The semiconductor device 1A includes a drain electrode 145 covering the second main surface 4. The drain electrode 145 may also be referred to as a "drain pad," "drain pad electrode," "high-potential pad electrode," or the like. The drain electrode 145 forms ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 145 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain electrode 145 may cover the second main surface 4 so as to partially expose the periphery of the chip 2.

[0358] The breakdown voltage that can be applied between the source electrode 120 and the drain electrode 145 (between the first main surface 3 and the second main surface 4) may be 500 V or more. The breakdown voltage may be 600 V or more. The breakdown voltage may be 1000 V or more. The breakdown voltage may be 3000 V or more. The breakdown voltage may be 5000 V or less. Of course, the breakdown voltage may be 3000 V or less.

[0359] 30 is a circuit diagram showing the electrical configuration of the gate resistor RG. As shown in Fig. 30, the gate wiring 102 is electrically connected to the gate pad 101 via the gate resistor RG. The gate resistor RG is formed by a parallel circuit of a first parallel resistor circuit RC1 and a second parallel resistor circuit RC2.

[0360] The first parallel resistance circuit RC1 is electrically interposed between the gate pad 101 and the first resistance wiring 105 and is composed of a plurality of first resistance elements R1 connected in parallel. The plurality of first resistance elements R1 are formed by portions of the plurality of resistance structures 50 (each resistance film 85) located between the first resistance opening 91 and the second resistance opening 92 in the region between the gate pad 101 and the first resistance wiring 105. In other words, the plurality of first resistance elements R1 each have a stacked structure including portions of the plurality of resistance structures 50 and portions of the plurality of resistance films 85.

[0361] The first resistor elements R1 may have the same resistance value or different resistance values. The resistance value of each first resistor element R1 can also be adjusted by adjusting the distance between the first resistor opening 91 and the second resistor opening 92.

[0362] The second parallel resistance circuit RC2 is electrically interposed between the gate pad 101 and the first resistance wiring 105 and is composed of a plurality of second resistance elements R2 connected in parallel. The plurality of second resistance elements R2 are formed by portions of the plurality of resistance structures 50 (each resistance film 85) located between the first resistance opening 91 and the third resistance opening 93 in the region between the gate pad 101 and the first resistance wiring 105. In other words, the plurality of second resistance elements R2 each have a stacked structure including a portion of the plurality of resistance structures 50 and a portion of the plurality of resistance films 85.

[0363] The second resistance elements R2 may have the same resistance value as each other or different resistance values ​​from each other. The second resistance elements R2 may have the same resistance value as each of the first resistance elements R1 or different resistance values ​​from each of the first resistance elements R1. The resistance value of each second resistance element R2 can also be adjusted by adjusting the distance between the first resistance opening 91 and the third resistance opening 93.

[0364] The resistance value of the gate resistor RG is determined by the combined resistance of the first parallel resistor circuit RC1 and the second parallel resistor circuit RC2. The resistance value of the first parallel resistor circuit RC1 is determined by the combined resistance of the multiple first resistor elements R1. The resistance value of the second parallel resistor circuit RC2 is determined by the combined resistance of the multiple second resistor elements R2.

[0365] The gate resistor RG does not necessarily have to have both the first parallel resistor circuit RC1 and the second parallel resistor circuit RC2 at the same time, and may be configured with only one of the first parallel resistor circuit RC1 and the second parallel resistor circuit RC2. Such a configuration can be realized by adjusting the presence or absence of the second resistor opening 92 and the third resistor opening 93 and the presence or absence of the first resistor wiring 105 and the second resistor wiring 106 at the layout level.

[0366] For example, if the gate resistor RG is composed of only the second parallel resistor circuit RC2, then it is sufficient to remove either or both of the second resistor opening 92 and the first resistor wiring 105 and electrically disconnect the gate wiring 102 from one end of the plurality of resistor structures 50 (the plurality of resistor films 85). When only the second resistor opening 92 is removed, the first resistor wiring 105 becomes a dummy wiring.

[0367] Similarly, when the gate resistance RG is composed of only the first parallel resistance circuit RC1, it is only necessary to remove either or both of the third resistance opening 93 and the second resistance wiring 106, and electrically disconnect the gate wiring 102 from the other ends of the plurality of resistance structures 50 (the plurality of resistance films 85). When only the third resistance opening 93 is removed, the second resistance wiring 106 becomes a dummy wiring.

[0368] The gate resistor RG slows down the switching speed during switching operations to suppress surge currents. In other words, the gate resistor RG suppresses noise caused by surge currents. Because the gate resistor RG is formed on the first main surface 3 (active surface 8), it is not externally connected to the semiconductor device 1A. This reduces the number of components mounted on a circuit board.

[0369] Since the gate resistor RG includes a plurality of resistor structures 50 embedded in the thickness direction of the chip 2, the area occupied by the gate resistor RG with respect to the first main surface 3 is limited. Therefore, a reduction in the area of ​​the active region 12 due to the introduction of the gate resistor RG is suppressed. In particular, since the gate resistor RG is disposed in the region between the active region 12 and the first termination region 15, a reduction in the area of ​​the active region 12 is appropriately suppressed.

[0370] The plurality of resistance structures 50 arranged in the resistance region 17 have a configuration similar to the plurality of gate structures 25 arranged in the active region 12, and are controlled by a gate potential. The plurality of first dummy structures 55 arranged in the resistance region 17 have a configuration similar to the plurality of source structures 30 arranged in the active region 12, and are controlled by a source potential. Therefore, the electric field distribution in the resistance region 17 is similar to the electric field distribution in the active region 12. This suppresses a decrease in breakdown voltage caused by the layout of the resistance region 17.

[0371] The plurality of first dummy structures 55 and the plurality of second dummy structures 60 arranged in the first dummy region 18 (second dummy region 19) have a configuration similar to the plurality of source structures 30 and the plurality of side end structures 35 arranged in the active region 12 and the first side end region 13 (second side end region 14), and are controlled by the source potential.

[0372] Therefore, the electric field distribution in the first dummy region 18 becomes similar to the electric field distribution in the active region 12 and the first side end region 13. This suppresses a decrease in breakdown voltage caused by the layout of the first dummy region 18 (second dummy region 19). The first dummy region 18 (second dummy region 19) also suppresses bias in the electric field distribution in the region between the active region 12 and the first termination region 15.

[0373] The plurality of gate structures 25 located directly below the gate pad 101 (gate subpad 111) have the same configuration as the plurality of gate structures 25 located directly below the gate pad 101 and are controlled by a gate potential. The plurality of source structures 30 located directly below the gate pad 101 have the same configuration as the plurality of source structures 30 located directly below the gate pad 101 and are controlled by a source potential.

[0374] Therefore, the electric field distribution immediately below the gate pad 101 (gate subpad 111) inside the chip 2 becomes the same as the electric field distribution in the region outside the region immediately below the gate pad 101 inside the chip 2. Therefore, a decrease in breakdown voltage caused by the layout of the gate pad 101 is suppressed.

[0375] As described above, the semiconductor device 1A includes the chip 2, the trench electrode type resistance structure 50, and the resistance film 85. The chip 2 has a first main surface 3. The resistance structure 50 is formed on the first main surface 3. The resistance film 85 covers the resistance structure 50 as a single object to be covered, and is electrically connected to the resistance structure 50.

[0376] This configuration makes it possible to provide a semiconductor device 1A having a novel layout associated with resistors. In particular, this configuration allows the resistive film 85 to be provided in a one-to-one correspondence with the resistive structure 50, so that the resistive film 85 can be electrically isolated from structures other than the resistive structure 50. This allows other structures to be designed while being electrically isolated from the resistive film 85. This prevents the electrical characteristics of the resistive film 85 from fluctuating due to other structures, and prevents the electrical characteristics of other structures from fluctuating due to the resistive film 85.

[0377] From another perspective, the semiconductor device 1A includes a chip 2, a trench electrode type resistance structure 50, and a trench electrode type first dummy structure 55 (electrode structure). The chip 2 has a first main surface 3. The resistance structure 50 is formed on the first main surface 3. The first dummy structure 55 is a structure to which a potential different from that of the resistance structure 50 is applied, and is formed on the first main surface 3 so as to be adjacent to the resistance structure 50.

[0378] This configuration makes it possible to provide a semiconductor device 1A having a novel layout associated with a resistor. For example, it is conceivable to form a first dummy structure 55 deeper than the resistor structure 50 and use the first dummy structure 55 as another resistor structure 50. In this case, since the first dummy structure 55 functions as the resistor structure 50, the first dummy structure 55 is required to have the same level of reliability as the resistor structure 50.

[0379] Generally, the process difficulty of a relatively deep trench structure is higher than that of a relatively shallow trench structure. Therefore, the process error that may occur in the relatively deep first dummy structure 55 is larger than the process error that may occur in the relatively shallow resistor structure 50. Examples of the process error that may occur in the resistor structure 50 include process errors that may occur in the depth of the fifth trench 51 and the film thickness of the fifth insulating film 52. Examples of the process error that may occur in the first dummy structure 55 include process errors that may occur in the depth of the sixth trench 56 and the film thickness of the sixth insulating film 57.

[0380] Therefore, when the first dummy structure 55 is used as another resistor structure 50, the electrical characteristics of the first dummy structure 55 may be inferior to the electrical characteristics of the resistor structure 50 due to process errors. This problem may be solved by imposing strict process conditions on the first dummy structure 55. However, such a design change further increases the process difficulty, leading to increased costs.

[0381] In this regard, according to a configuration from another perspective, the first dummy structure 55 is electrically isolated from the resistance structure 50. This allows the resistance structure 50 to be designed separately from the first dummy structure 55, and the first dummy structure 55 to be designed separately from the resistance structure 50. This makes it possible to suppress a decrease in the reliability of the resistance structure 50 caused by the first dummy structure 55, and makes it possible to suppress a decrease in the reliability of the first dummy structure 55 caused by the resistance structure 50.

[0382] From another perspective, the semiconductor device 1A includes a chip 2, a trench electrode type resistor structure 50, a trench electrode type first dummy structure 55 (first electrode structure), and a trench electrode type second dummy structure 60 (second electrode structure). The chip 2 has a first main surface 3. The resistor structure 50 is formed on the first main surface 3.

[0383] The first dummy structure 55 is a structure to which a potential different from that of the resistance structure 50 is applied, and is formed on the first main surface 3 at a distance in one direction (second direction Y) from the resistance structure 50. The second dummy structure 60 is a structure to which a potential different from that of the resistance structure 50 is applied, and is formed on the first main surface 3 at a distance in an orthogonal direction (first direction X) that is orthogonal to the one direction (second direction Y) from the resistance structure 50.

[0384] This configuration makes it possible to provide a semiconductor device 1A having a novel layout associated with resistors. In particular, this configuration makes it possible to electrically separate the first dummy structure 55 and the second dummy structure 60 from the resistor structure 50. This allows the resistor structure 50 to be designed separately from the first dummy structure 55 and the second dummy structure 60, and allows the first dummy structure 55 and the second dummy structure 60 to be designed separately from the resistor structure 50. This makes it possible to suppress a decrease in reliability of the resistor structure 50 due to the first dummy structure 55 and the second dummy structure 60, and to suppress a decrease in reliability of the first dummy structure 55 and the second dummy structure 60 due to the resistor structure 50.

[0385] From another perspective, the semiconductor device 1A includes a chip 2, an active plateau 11 (mesa portion), and a resistive film 85. The chip 2 has a first main surface 3. The active plateau 11 is defined on the first main surface 3 by an active surface 8 (first surface portion), an outer peripheral surface 9 (second surface portion), and first to fourth connecting surfaces 10A to 10D (connecting surface portions). The active surface 8 is located inside the first main surface 3. The outer peripheral surface 9 is recessed in the thickness direction outside the active surface 8. The first to fourth connecting surfaces 10A to 10D connect the active surface 8 and the outer peripheral surface 9. The resistive film 85 is disposed on the active surface 8.

[0386] This configuration provides a semiconductor device 1A having a novel layout associated with the resistor. In particular, this configuration prevents the electrical characteristics and layout on the outer peripheral surface 9 from being limited by the resistive film 85, since the resistive film 85 is disposed on the active surface 8.

[0387] From another perspective, the semiconductor device 1A includes a chip 2, an active plateau 11 (mesa portion), and a trench electrode type resistor structure 50. The chip 2 has a first main surface 3. The active plateau 11 is defined on the first main surface 3 by an active surface 8 (first surface portion), an outer peripheral surface 9 (second surface portion), and first to fourth connection surfaces 10A to 10D (connection surface portions). The active surface 8 is located inside the first main surface 3. The outer peripheral surface 9 is recessed in the thickness direction outside the active surface 8. The first to fourth connection surfaces 10A to 10D connect the active surface 8 and the outer peripheral surface 9. The resistor structure 50 is formed on the active surface 8.

[0388] This configuration provides a semiconductor device 1A having a novel layout associated with a resistor. In particular, this configuration prevents the electrical characteristics and layout on the outer peripheral surface 9 side from being limited by the resistor structure 50, since the resistor structure 50 is formed on the active surface 8.

[0389] The layout of the semiconductor device 1A is particularly effective when a chip 2 including a SiC single crystal is employed. The layout of the semiconductor device 1A provides various ideas that contribute to improving electrical characteristics from various perspectives regarding designs associated with resistors in SiC semiconductor devices (wide bandgap semiconductor devices). Other layout examples of the resistor region 17, etc. are shown below.

[0390] Fig. 31 is an enlarged plan view showing a resistor region 17 according to a second layout example. Fig. 32 is an enlarged plan view showing a layout example of an inner part of the resistor region 17. Fig. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in Fig. 32. Fig. 34 is a cross-sectional view taken along line XXXIV-XXXIV shown in Fig. 32. Fig. 35 is a cross-sectional view taken along line XXXV-XXXV shown in Fig. 32.

[0391] In the resistor region 17 according to the first layout example described above, one resistor film 85 is provided in a one-to-one correspondence with one resistor structure 50. In contrast, in the resistor region 17 according to the second layout example, a plurality of resistor films 85 are provided in a one-to-many correspondence with one resistor structure 50.

[0392] Specifically, the multiple resistive films 85 include multiple first resistive films 151, multiple second resistive films 152, and multiple third resistive films 153. The multiple first resistive films 151 form a film covering an inner region of a corresponding one of the resistive structures 50 as a single covering target. In other words, each first resistive film 151 is provided in a one-to-one correspondence with the inner portion of each of the resistive structures 50, and is electrically connected to the corresponding one of the resistive structures 50.

[0393] The multiple first resistance films 151 cover the inner portions of the corresponding resistance structures 50 at intervals inward from both ends of the corresponding resistance structures 50. In this embodiment, the multiple first resistance films 151 are each formed in a strip shape extending in the first direction X in a plan view and face each other in the second direction Y. In other words, the multiple first resistance films 151 are arranged in a stripe shape extending along the multiple resistance structures 50 in a plan view.

[0394] The multiple first resistance films 151 are arranged at intervals in the second direction Y from the resistance structures 50 that are not to be covered, thereby exposing the resistance structures 50 that are not to be covered. The multiple first resistance films 151 are arranged at intervals in the second direction Y from the multiple first dummy structures 55, thereby exposing the multiple first dummy structures 55. In other words, the multiple first resistance films 151 and the multiple first dummy structures 55 are arranged alternately in the second direction Y in a plan view.

[0395] The multiple first resistance films 151 are arranged at intervals in the first direction X from the multiple second dummy structures 60, exposing the multiple second dummy structures 60. In other words, the multiple first resistance films 151 face the multiple second dummy structures 60 in the first direction X in a plan view, but do not face the multiple second dummy structures 60 in the second direction Y in a plan view.

[0396] The second resistive films 152 each cover a region on one end side of a corresponding one of the resistive structures 50 at a distance from the first resistive films 151 on one side in the first direction X. In other words, each of the second resistive films 152 is provided in a one-to-one correspondence with one end of each of the resistive structures 50, and is electrically connected to the corresponding one of the resistive structures 50.

[0397] The plurality of second resistive films 152 expose portions of the corresponding fifth buried electrodes 53 from regions between the plurality of first resistive films 151. In this embodiment, the plurality of second resistive films 152 are formed at intervals from one end of the plurality of resistive structures 50 toward the plurality of first resistive films 151, and expose portions of the corresponding fifth buried electrodes 53 from regions between the one end of the plurality of resistive structures 50. Of course, the plurality of second resistive films 152 may cover one end of the corresponding resistive structure 50.

[0398] In this embodiment, the second resistive films 152 are each formed in a strip shape extending in the first direction X in a plan view, and are opposed to each other in the second direction Y. In other words, the second resistive films 152 are arranged in stripes extending along the resistive structures 50 in a plan view.

[0399] The second resistive films 152 are arranged at intervals in the second direction Y from the resistive structures 50 that are not to be covered, thereby exposing the resistive structures 50 that are not to be covered. The second resistive films 152 are arranged at intervals in the second direction Y from the second dummy structures 60, thereby exposing the second dummy structures 60. In other words, the second resistive films 152 and the first dummy structures 55 are arranged alternately in the second direction Y in a plan view.

[0400] The second resistance films 152 are arranged at intervals in the first direction X from the second dummy structures 60, exposing the second dummy structures 60. In other words, the second resistance films 152 face the second dummy structures 60 in the first direction X in a plan view, but do not face the second dummy structures 60 in the second direction Y in a plan view.

[0401] The plurality of third resistive films 153 are arranged in a film-like manner to cover a region on the other end side of one corresponding resistive structure 50 at intervals on the other side in the first direction X from the plurality of first resistive films 151. In other words, each third resistive film 153 is provided in a one-to-one correspondence with the other end of each resistive structure 50, and is electrically connected to the corresponding one resistive structure 50.

[0402] The plurality of third resistive films 153 expose portions of the corresponding fifth buried electrodes 53 from regions between the plurality of first resistive films 151. In this embodiment, the plurality of third resistive films 153 are formed at intervals from the other ends of the plurality of resistive structures 50 toward the plurality of first resistive films 151, and expose portions of the corresponding fifth buried electrodes 53 from regions between the other ends of the plurality of resistive structures 50. Of course, the plurality of third resistive films 153 may cover the other ends of the corresponding resistive structures 50.

[0403] In this embodiment, the multiple third resistive films 153 are each formed in a strip shape extending in the first direction X in a plan view, and face each other in the second direction Y. That is, the multiple third resistive films 153 are arranged in a stripe shape extending along the multiple resistive structures 50 in a plan view. The multiple third resistive films 153 face the multiple second resistive films 152 in the first direction X, with the multiple first resistive films 151 sandwiched between them.

[0404] The plurality of third resistive films 153 are arranged at intervals in the second direction Y from the resistive structures 50 that are not to be covered, thereby exposing the resistive structures 50 that are not to be covered. The plurality of third resistive films 153 are arranged at intervals in the second direction Y from the plurality of second dummy structures 60, thereby exposing the plurality of second dummy structures 60. In other words, the plurality of third resistive films 153 are arranged alternately with the plurality of first dummy structures 55 in the second direction Y in a plan view.

[0405] The third resistance films 153 are arranged at intervals in the first direction X from the second dummy structures 60, exposing the second dummy structures 60. In other words, the third resistance films 153 face the second dummy structures 60 in the first direction X in a plan view, but do not face the second dummy structures 60 in the second direction Y in a plan view.

[0406] As in the first layout example, the plurality of resistive films 85 (first to third resistive films 151 to 153) are connected to the fifth buried electrodes 53 in the portions covering the corresponding resistive structures 50, and have portions that extend from above the fifth buried electrodes 53 onto the main surface insulating film 80. In other words, the plurality of resistive films 85 are formed wider in the second direction Y than the corresponding resistive structures 50.

[0407] The plurality of resistive films 85 (first to third resistive films 151 to 153) are made of the same conductive material as the corresponding fifth buried electrodes 53 and are formed integrally with the fifth buried electrodes 53. In other words, the plurality of resistive films 85 include a portion of the fifth buried electrodes 53 that is extended in the form of a film to an area outside the resistive structure 50 (above the main surface insulating film 80). Of course, the plurality of resistive films 85 may be formed separately from the fifth buried electrodes 53. For other descriptions of the plurality of resistive films 85 (first to third resistive films 151 to 153), the description of the resistive film 85 according to the first layout example applies.

[0408] In this embodiment, the plurality of first resistor openings 91 expose the plurality of first resistor films 151 in a one-to-one correspondence. In this embodiment, the plurality of second resistor openings 92 expose the plurality of second resistor films 152 in a one-to-one correspondence. In this embodiment, the plurality of third resistor openings 93 expose the plurality of third resistor films 153 in a one-to-one correspondence. The other configurations are the same as in the first layout example.

[0409] The gate resistor RG according to the second layout example is configured by a parallel circuit of a first parallel resistance circuit RC1 and a second parallel resistance circuit RC2, similar to the first layout example (see also FIG. 30).

[0410] In the second layout example, each first resistance element R1 is formed by a portion of the fifth buried electrode 53 located in the region between the first resistance film 151 and the second resistance film 152. With this configuration, the resistance value of each first resistance element R1 is less susceptible to process errors that occur in the film thicknesses of the multiple resistance films 85. This improves the reliability of each first resistance element R1.

[0411] Similarly, each second resistive element R2 is formed by a portion of the fifth buried electrode 53 located in a region between the first resistive film 151 and the third resistive film 153. With this configuration, the resistance value of each second resistive element R2 is less susceptible to process errors that occur in the film thickness of the multiple resistive films 85. This improves the reliability of each second resistive element R2.

[0412] 36 is an enlarged plan view showing the resistor region 17 according to the third layout example. In the resistor region 17 according to the first layout example described above, the gate resistor RG includes a first parallel resistor circuit RC1 and a second parallel resistor circuit RC2. In contrast, in the resistor region 17 according to the third layout example, the gate resistor RG includes three or more parallel resistor circuits.

[0413] The layout of the multiple resistor structures 50 and the multiple resistor films 85 is the same as in the first layout example. In this embodiment, the multiple resistor openings 90 described above include multiple first resistor openings 155 and multiple second resistor openings 156. The multiple first resistor openings 155 are provided in a one-to-many correspondence with each resistor structure 50. In other words, multiple first resistor openings 155 are provided corresponding to one resistor structure 50.

[0414] For one resistor structure 50, the multiple first resistor openings 155 are arranged at intervals in the first direction X, exposing one resistor film 85 at multiple locations. For multiple resistor structures 50 (resistance films 85), the multiple first resistor openings 155 are arranged in a row at intervals in the second direction Y.

[0415] That is, the multiple first resistor openings 155 are generally formed in a matrix at intervals in the first direction X and the second direction Y in plan view, and each exposes a portion of the corresponding resistor film 85. The planar shape of each first resistor opening 155 is arbitrary. Each first resistor opening 155 may be formed in a strip shape extending in the first direction X in plan view. Of course, each first resistor opening 155 may be formed in a rectangular, polygonal, circular, or other shape in plan view.

[0416] The second resistor openings 156 are spaced apart from the first resistor openings 155 and are provided in a one-to-many correspondence with the resistor structures 50. In other words, the second resistor openings 156 are provided in correspondence with one resistor structure 50.

[0417] For one resistor structure 50, the second resistor openings 156 are arranged alternately with the first resistor openings 155 in the first direction X, exposing one resistor film 85 at multiple locations. For multiple resistor structures 50 (resistance films 85), the second resistor openings 156 are arranged in a row at intervals in the second direction Y.

[0418] That is, the second resistor openings 156 are generally formed in a matrix at intervals in the first direction X and the second direction Y in plan view, and each exposes a portion of the corresponding resistor film 85. The planar shape of each second resistor opening 156 is arbitrary. Each second resistor opening 156 may be formed in a strip shape extending in the first direction X in plan view. Of course, each second resistor opening 156 may be formed in a rectangular, polygonal, circular, or other shape in plan view.

[0419] In this embodiment, the gate pad 101 has a pad body 103 and a plurality of lead-out portions 104. The lead-out portions 104 are arranged at intervals in the first direction X at the end of the pad body 103 on the resistor region 17 side, are drawn out in strip shapes from the pad body 103 toward the region above the resistor region 17, and cover the plurality of resistor structures 50 with the interlayer film 86 sandwiched therebetween.

[0420] In this embodiment, the gate pad 101 includes two outermost lead-out portions 104 led out from both end portions of the pad body portion 103, and a plurality of lead-out portions 104 led out at intervals in the first direction X from the outermost lead-out portion 104 in the inner portion of the pad body portion 103. Of course, either or both of the two outermost lead-out portions 104 may be formed at intervals in the first direction X from the end portion of the pad body portion 103.

[0421] The plurality of lead-out portions 104 each have a lead-out width WD that is less than the pad width WP of the pad body portion 103, and are formed in a strip shape extending in the second direction Y. The plurality of lead-out portions 104 only need to have a lead-out width WD that is greater than the opening width of the first resistor opening 155, and the value of the lead-out width WD is arbitrary.

[0422] The plurality of lead portions 104 cover the plurality of first resistor openings 155 at intervals from the plurality of second resistor openings 156 in a plan view. The plurality of lead portions 104 enter the plurality of first resistor openings 155 from above the interlayer film 86, and are mechanically and electrically connected to the plurality of resistor films 85 within the plurality of first resistor openings 155.

[0423] In this embodiment, the gate wiring 102 has a connection wiring portion 160 instead of the first resistance wiring 105 and the second resistance wiring 106. The connection wiring portion 160 is arranged in a region on one side (the first side surface 5A side) in the second direction Y with respect to the gate pad 101 (plurality of lead portions 104) in a plan view, and faces the gate pad 101 in the second direction Y.

[0424] That is, connection wiring portion 160 is arranged in a region on one side (first side surface 5A side) in second direction Y with respect to resistance region 17 in plan view, and has a portion facing resistance region 17 in second direction Y. In this embodiment, connection wiring portion 160 is arranged on a portion of interlayer film 86 that covers first termination region 15, and faces multiple termination structures 40 with interlayer film 86 in between.

[0425] Connection wiring portion 160 has a wiring main body 161 and multiple lead-out wiring portions 162. Wire main body 161 is arranged in a region outside resistance region 17 (multiple resistance structures 50) in a plan view. In this embodiment, wire main body 161 is arranged above first termination region 15 and faces multiple termination structures 40 in the stacking direction.

[0426] The plurality of lead-out wiring portions 162 are arranged at intervals in the first direction X at the end of the wire main body 161 on the resistance region 17 side, and are led out in the first direction X from the wire main body 161 toward the region above the resistance region 17. As a result, the plurality of lead-out wiring portions 162 cover the plurality of resistance structures 50 with the interlayer film 86 sandwiched therebetween. The plurality of lead-out wiring portions 162 are led out so as to be arranged alternately with the plurality of lead-out portions 104 of the gate pad 101 in the first direction X in the region above the resistance region 17.

[0427] The plurality of lead-out wiring portions 162 each have a lead-out width WD2 that is less than the pad width WP of the pad body portion 103, and are formed in a strip shape extending in the second direction Y. The plurality of lead-out wiring portions 162 only need to have a lead-out width WD2 that is greater than the opening width of the second resistor opening 156 and smaller than the distance between two adjacent lead-out portions 104, and the value of the lead-out width WD2 is arbitrary.

[0428] The plurality of lead wiring portions 162 enter the plurality of second resistor openings 156 from above the interlayer film 86, and are mechanically and electrically connected to the plurality of resistor films 85 within the plurality of second resistor openings 156. In the region of the interlayer film 86 between the gate pad 101 and the gate wiring 102, a zigzag gap is defined by the plurality of lead wiring portions 104 and the plurality of lead wiring portions 162.

[0429] In this embodiment, the pad insulating film 130 covers the plurality of lead portions 104 of the gate pad 101 and has a gate pad opening 131 that exposes the pad body portion 103 of the gate pad 101. In other words, the pad insulating film 130 covers the plurality of resistor structures 50 (the plurality of resistor films 85) with the plurality of lead portions 104 and the interlayer film 86 sandwiched therebetween.

[0430] The pad insulating film 130 covers the plurality of lead-out wiring portions 162 of the gate wiring 102, and also covers the plurality of resistance structures 50 (the plurality of resistance films 85) with the plurality of lead-out wiring portions 162 and the interlayer film 86 sandwiched therebetween. The pad insulating film 130 covers zigzag gaps exposed from regions of the interlayer film 86 between the plurality of lead-out portions 104 and the plurality of lead-out wiring portions 162, and also covers the plurality of resistance structures 50 (the plurality of resistance films 85) with the zigzag gaps sandwiched therebetween. The pad insulating film 130 preferably covers the entire areas of the plurality of resistance structures 50 (the plurality of resistance films 85) in a plan view.

[0431] 37 is a circuit diagram showing the electrical configuration of the gate resistor RG. Referring to Fig. 37, the gate resistor RG is configured by a parallel circuit of a plurality (eight in this embodiment) of parallel resistance circuits RC. Each of the parallel resistance circuits RC is electrically interposed in a region between adjacent lead-out portions 104 and lead-out wiring portions 162, and is configured by a plurality (four in this embodiment) of resistance elements R connected in parallel.

[0432] The multiple resistance elements R are formed by portions of the multiple resistance structures 50 (each resistance film 85) located between the first resistor opening 155 and the second resistor opening 156 in the region between the adjacent lead-out portions 104 and lead-out wiring portions 162. The multiple resistance elements R may have the same resistance value or different resistance values. The resistance value of each resistance element R can also be adjusted by adjusting the distance between the adjacent first resistor opening 155 and second resistor opening 156.

[0433] The resistance value of the gate resistor RG is determined by the combined resistance of a plurality of parallel resistor circuits RC. The resistance value of each parallel resistor circuit RC is determined by the combined resistance of a plurality of (four in this embodiment) resistor elements R.

[0434] The resistance value (combined resistance) of the gate resistor RG can be adjusted by changing the combined resistance of the parallel resistor circuit RC or the number of parallel resistor circuits RC. The resistance value (combined resistance) of the parallel resistor circuit RC can be adjusted by changing the resistance value of the resistive element R or the number of resistive elements R. Such a gate resistor RG is effective when realizing a relatively small resistance value or when precisely adjusting the resistance value within a relatively small range of values.

[0435] The number of parallel resistance circuits RC may be one or more. That is, the gate resistor RG may be configured with a single parallel resistance circuit RC. In this case, the single parallel resistance circuit RC is configured with one lead-out portion 104 and one lead-out wiring portion 162. Of course, the parallel resistance circuit RC may also be configured with a single resistance element R.

[0436] 38 is an enlarged plan view showing the resistor region 17 according to the fourth layout example. The resistor region 17 according to the fourth layout example has a layout obtained by modifying the resistor region 17 according to the third layout example. In the resistor region 17 according to the third layout example, all of the lead-out portions 104 are electrically connected to a plurality of resistor structures 50 (resistive films 85), and all of the lead-out wiring portions 162 are electrically connected to a plurality of resistor structures 50 (resistive films 85).

[0437] In contrast, in the resistor region 17 according to the fourth layout example, either a portion of the plurality of first resistor openings 155 or a portion of the plurality of second resistor openings 156 or both (in this embodiment, both) are selectively thinned out.

[0438] That is, some of the plurality of lead portions 104 cover the interlayer film 86 at intervals from some or all (all in this embodiment) of the plurality of first resistor openings 155, and are electrically isolated from some or all (all in this embodiment) of the plurality of resistor structures 50 (resistance films 85). In other words, the plurality of lead portions 104 include dummy lead portions 104D that are electrically isolated from some or all of the plurality of resistor structures 50.

[0439] Similarly, some of the plurality of lead-out wiring portions 162 cover the interlayer film 86 at intervals from some or all (all in this embodiment) of the plurality of second resistor openings 156, and are electrically isolated from some or all (all in this embodiment) of the plurality of resistor structures 50 (resistance films 85). In other words, the plurality of lead-out wiring portions 162 include dummy lead-out wiring portions 162D that are electrically isolated from some or all of the plurality of resistor structures 50.

[0440] Such a configuration is formed by changing the layout of the resist mask used in the process of forming the plurality of resistor openings 90. On the other hand, it is not necessary to change the layout of the resist mask used in the process of forming the gate electrode 100, etc. Therefore, with the resistor region 17 according to the fourth layout example, the number of parallel resistor circuits RC can be easily adjusted.

[0441] Of course, the number of resistor elements R constituting the parallel resistor circuit RC may be adjusted by adjusting the number of first resistor openings 155. Also, the number of resistor elements R constituting the parallel resistor circuit RC may be adjusted by adjusting the number of second resistor openings 156.

[0442] 39 is an enlarged plan view showing the resistor region 17 according to the fifth layout example. The resistor region 17 according to the fifth layout example has a layout that combines the technical concept of the resistor region 17 according to the third layout example with the resistor region 17 according to the second layout example. That is, in the resistor region 17 according to the fifth layout example, a plurality of resistor films 85 are formed in a one-to-many correspondence with one resistor structure 50.

[0443] In this embodiment, the plurality of resistive films 85 includes a plurality of first resistive films 165 and a plurality of second resistive films 166. The plurality of first resistive films 165 are provided in a one-to-many correspondence with the respective resistive structures 50, and each first resistive film 165 covers one corresponding resistive structure 50 as a single covering target.

[0444] For one resistor structure 50, the multiple first resistor films 165 are arranged at intervals in the first direction X so as to partially expose the fifth buried electrode 53, and cover one fifth buried electrode 53 at multiple locations. For multiple resistor structures 50, the multiple first resistor films 165 are arranged in a row at intervals in the second direction Y. In other words, the multiple first resistor films 165 are formed as a whole in a matrix shape at intervals in the first direction X and the second direction Y in a plan view, and each covers a portion of the corresponding fifth buried electrode 53.

[0445] In this embodiment, the multiple first resistance films 165 are each formed in a strip shape extending in the first direction X in a plan view, and face each other in the second direction Y. In other words, the multiple first resistance films 165 are arranged in a stripe shape extending along the multiple resistance structures 50 in a plan view.

[0446] The multiple first resistance films 165 are arranged at intervals in the second direction Y from the resistance structures 50 that are not to be covered, thereby exposing the resistance structures 50 that are not to be covered. The multiple first resistance films 165 are arranged at intervals in the second direction Y from the multiple first dummy structures 55, thereby exposing the multiple first dummy structures 55. In other words, the multiple first resistance films 165 are arranged alternately with the multiple first dummy structures 55 in the second direction Y in a plan view.

[0447] The multiple first resistance films 165 are arranged at intervals in the first direction X from the multiple second dummy structures 60, exposing the multiple second dummy structures 60. In other words, the multiple first resistance films 165 face the multiple second dummy structures 60 in the first direction X in a plan view, but do not face the multiple second dummy structures 60 in the second direction Y in a plan view.

[0448] The second resistive films 166 are provided at intervals from the first resistive films 165 in a one-to-many correspondence with the respective resistive structures 50, and each second resistive film 166 covers one corresponding resistive structure 50 as a single covering target. In other words, the second resistive films 166 are provided corresponding to one resistive structure 50.

[0449] For one resistor structure 50, the multiple second resistor films 166 are arranged alternately with the multiple first resistor films 165 in the first direction X so as to partially expose the fifth buried electrode 53, and cover one fifth buried electrode 53 at multiple locations. For multiple resistor structures 50, the multiple second resistor films 166 are arranged in a row at intervals in the second direction Y. That is, the multiple second resistor films 166 are formed as a whole in a matrix shape at intervals in the first direction X and the second direction Y in a plan view, and each covers a portion of the corresponding fifth buried electrode 53.

[0450] In this embodiment, the second resistive films 166 are each formed in a strip shape extending in the first direction X in a plan view, and are opposed to each other in the second direction Y. In other words, the second resistive films 166 are arranged in stripes extending along the resistive structures 50 in a plan view.

[0451] The multiple second resistive films 166 are arranged at intervals in the second direction Y from the resistive structures 50 that are not to be covered, thereby exposing the resistive structures 50 that are not to be covered. The multiple second resistive films 166 are arranged at intervals in the second direction Y from the multiple first dummy structures 55, thereby exposing the multiple first dummy structures 55. In other words, the multiple second resistive films 166 are arranged alternately with the multiple first dummy structures 55 in the second direction Y in a plan view.

[0452] The second resistance films 166 are arranged at intervals in the first direction X from the second dummy structures 60, exposing the second dummy structures 60. In other words, the second resistance films 166 face the second dummy structures 60 in the first direction X in a plan view, but do not face the second dummy structures 60 in the second direction Y in a plan view.

[0453] In this embodiment, the plurality of first resistor openings 155 expose the plurality of first resistor films 165 in a one-to-one correspondence, respectively. In this embodiment, the plurality of second resistor openings 156 expose the plurality of second resistor films 166 in a one-to-one correspondence, respectively.

[0454] The gate resistor RG according to the fifth layout example is configured with multiple parallel resistance circuits RC, as in the third layout example (see also FIG. 37 ). In the fifth layout example, each resistance element R is formed by a portion of the fifth buried electrode 53 located in a region between adjacent first resistance films 165 and second resistance films 166. With this configuration, the resistance value of each resistance element R is less susceptible to process errors that occur in the film thicknesses of the multiple resistance films 85. This improves the reliability of each resistance element R.

[0455] Fig. 40 is a plan view showing a layout example of the first main surface 3 of the semiconductor device 1B according to the second embodiment. Fig. 41 is an enlarged plan view showing the sub-resistor region 170 according to the first layout example together with the resistor region 17 according to the first layout example. Fig. 42 is an enlarged plan view showing a layout example of the periphery of the resistor region 17. Fig. 43 is an enlarged plan view showing a layout example of the first side end region 13. Fig. 44 is a cross-sectional view taken along line XLIV-XLIV shown in Fig. 42.

[0456] Similar to the semiconductor device 1A according to the first embodiment, the semiconductor device 1B includes an active region 12, a first side end region 13, a second side end region 14, a first termination region 15, a second termination region 16, a resistor region 17, a first dummy region 18, and a second dummy region 19 on the first main surface 3. The configurations within these regions are similar to those in the first embodiment, and therefore descriptions thereof will be omitted.

[0457] The semiconductor device 1B further includes a sub-resistance region 170, a first sub-active region 171, and a second sub-active region 172 on the first main surface 3. The sub-resistance region 170 is provided in a region between the active region 12 and the resistance region 17, and faces the active region 12 and the resistance region 17 in the second direction Y.

[0458] The sub-resistance region 170 is provided inwardly from both ends of the active region 12 in the first direction X with a gap therebetween. Therefore, the sub-resistance region 170 does not face the first side end region 13 or the second side end region 14 in the second direction Y. In this embodiment, the sub-resistance region 170 is set in a band shape extending in the first direction X in a plan view. In this embodiment, the sub-resistance region 170 has a planar area smaller than the planar area of ​​the resistance region 17. Of course, the planar area of ​​the active region 12 may be equal to or larger than the planar area of ​​the resistance region 17.

[0459] The first sub-active region 171 is provided on one side of the sub-resistor region 170 in the first direction X. The first sub-active region 171 is set in a strip shape extending in the first direction X in a plan view. The first sub-active region 171 faces the first side end region 13 and the sub-resistor region 170 in the first direction X, and faces the active region 12 and the first dummy region 18 in the second direction Y. In other words, the first sub-active region 171 is provided within a region defined by the active region 12, the first side end region 13, the first dummy region 18, and the sub-resistor region 170.

[0460] The second sub-active region 172 is provided on the other side in the first direction X of the sub-resistor region 170, and faces the first sub-active region 171 in the first direction X, with the sub-resistor region 170 sandwiched between them. In this embodiment, the second sub-active region 172 is set in a strip shape extending in the first direction X in a plan view. The second sub-active region 172 faces the first side end region 13 and the sub-resistor region 170 in the first direction X, and faces the active region 12 and the first dummy region 18 in the second direction Y. In other words, the second sub-active region 172 is provided within a region defined by the active region 12, the second side end region 14, the second dummy region 19, and the sub-resistor region 170.

[0461] The semiconductor device 1B includes at least one (in this embodiment, multiple) trench electrode type resistor structures 50 formed on the first main surface 3 (active surface 8) in the sub-resistor region 170. Hereinafter, the resistor structure 50 on the sub-resistor region 170 side will be referred to as a "sub-resistor structure 175" to distinguish it from the resistor structure 50 on the resistor region 17 side. Like the resistor structure 50, each sub-resistor structure 175 has a third width W3 in the second direction Y and a third depth D3 in the normal direction Z. Like the resistor structure 50, each sub-resistor structure 175 includes a fifth trench 51, a fifth insulating film 52, and a fifth buried electrode 53.

[0462] The multiple sub-resistor structures 175 are arranged in the sub-resistor region 170 at intervals inward from the periphery of the active surface 8 (the third connection surface 10C and the fourth connection surface 10D), and define the sub-resistor region 170 in the inner part of the active surface 8.

[0463] The multiple sub-resistance structures 175 are arranged in a region on one side in the second direction Y of an imaginary line that crosses the center of the active surface 8 in the first direction X in a plan view. The multiple sub-resistance structures 175 are located on the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. In other words, the multiple sub-resistance structures 175 face the center of the first side surface 5A (first connecting surface 10A) in the second direction Y in a plan view.

[0464] The multiple sub-resistance structures 175 are each formed in a strip shape extending in the first direction X in a plan view, and are arranged at intervals in the second direction Y. That is, the multiple sub-resistance structures 175 are arranged in a stripe shape extending in the first direction X in a plan view. Each of the multiple sub-resistance structures 175 has one end on one side in the first direction X and the other end on the other side in the first direction X.

[0465] The multiple sub-resistance structures 175 are formed with a length in the first direction X that is shorter than the length of the multiple gate structures 25, and spaced apart inward of the active surface 8 relative to the positions of the ends of the multiple gate structures 25 in the first direction X. In other words, the multiple sub-resistance structures 175 face inner portions of the multiple gate structures 25 in the second direction Y, but do not face both ends of the multiple gate structures 25 in the second direction Y. The length of the multiple sub-resistance structures 175 may be approximately equal to the length of the multiple resistance structures 50.

[0466] The plurality of sub-resistance structures 175 penetrate the body region 21 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8. The source region 22 described above may be formed in a surface layer portion of the body region 21 in the sub-resistance region 170. In this case, the plurality of sub-resistance structures 175 may penetrate both the body region 21 and the source region 22.

[0467] The multiple sub-resistor structures 175 are arranged in the second direction Y at a trench pitch approximately equal to the trench pitch of the multiple resistor structures 50 (gate structures 25). It is preferable that the trench pitch between the gate structure 25 and the sub-resistor structures 175 is approximately equal to the trench pitch of the multiple gate structures 25. It is also preferable that the trench pitch between the resistor structure 50 and the sub-resistor structures 175 is approximately equal to the trench pitch of the multiple gate structures 25.

[0468] The semiconductor device 1B includes at least one (in this embodiment, multiple) trench electrode type source structure 30 formed on the first main surface 3 (active surface 8) in the sub-resistance region 170. Hereinafter, the source structure 30 on the sub-resistance region 170 side will be referred to as a "sub-source structure 180" to distinguish it from the source structure 30 on the active region 12 side.

[0469] Similar to the source structure 30, each sub-source structure 180 has a second width W2 in the second direction Y and a second depth D2 in the normal direction Z. Each sub-source structure 180 is disposed at a first distance I1 from the sub-resistor structure 175 in the second direction Y. Each sub-source structure 180 includes a second trench 31, a second insulating film 32, and a second buried electrode 33.

[0470] The plurality of sub-source structures 180 are formed on the active surface 8 in the sub-resistor region 170 so as to be adjacent to the plurality of sub-resistor structures 175 in the second direction Y. Specifically, the plurality of sub-source structures 180 are respectively disposed in regions between pairs of adjacent sub-resistor structures 175 and face the plurality of sub-resistor structures 175 in the second direction Y. In other words, the plurality of sub-source structures 180 are arranged alternately with the plurality of sub-resistor structures 175 in the second direction Y.

[0471] The multiple sub-source structures 180 are each formed in a strip shape extending in the first direction X in a plan view. In this embodiment, the multiple sub-source structures 180 are drawn from the sub-resistance region 170 to either or both (in this embodiment, both) of the first sub-active region 171 and the second sub-active region 172. The multiple sub-source structures 180 face the multiple gate structures 25, the multiple source structures 30, the multiple first dummy structures 55, and the multiple second dummy structures 60 in the second direction Y in the first sub-active region 171 (second sub-active region 172).

[0472] The plurality of sub-source structures 180 extend from the first sub-active region 171 to the first side edge region 13 and extend from the second sub-active region 172 to the second side edge region 14. The plurality of sub-source structures 180 have portions that face the plurality of source structures 30 and the plurality of side edge structures 35 in the first side edge region 13 and the second side edge region 14.

[0473] That is, the sub-source structures 180 are respectively arranged in regions between pairs of side edge structures 35 adjacent to each other in the second direction Y in the first side edge region 13 (second side edge region 14), and face the side edge structures 35 in the second direction Y. The sub-source structures 180 are arranged alternately with the side edge structures 35 in the second direction Y in the first side edge region 13 (second side edge region 14).

[0474] The sub-source structures 180 are exposed from at least one of the third connection surface 10C and the fourth connection surface 10D. In this embodiment, the sub-source structures 180 penetrate both the third connection surface 10C and the fourth connection surface 10D and are exposed from both the third connection surface 10C and the fourth connection surface 10D. The sidewall wiring 81 described above is electrically connected to the sub-source structures 180 at the third connection surface 10C and the fourth connection surface 10D.

[0475] The plurality of sub-source structures 180 penetrate the body region 21 to reach the first semiconductor region 6 in the sub-resistor region 170, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8. The plurality of sub-source structures 180 penetrate the body region 21 and the source region 22 to reach the first semiconductor region 6 in the active region 12.

[0476] The plurality of sub-source structures 180 penetrate the body region 21 to reach the first semiconductor region 6 in the first side end region 13 (second side end region 14). When the aforementioned source region 22 is formed in the sub-resistor region 170, the plurality of sub-resistor structures 175 may penetrate both the body region 21 and the source region 22.

[0477] The semiconductor device 1B includes at least one gate structure 25 (in this embodiment, multiple gate structures 25) formed on the active surface 8 in the first sub-active region 171. Several gate structures 25 are also formed in the second sub-active region 172. The configuration on the second sub-active region 172 side is similar to the configuration on the first sub-active region 171 side. The description of the first sub-active region 171 side applies to the description of the second sub-active region 172 side. Hereinafter, the gate structure 25 on the first sub-active region 171 side will be referred to as a "sub-gate structure 185" to distinguish it from the gate structure 25 on the active region 12 side.

[0478] Similar to the gate structure 25, each sub-gate structure 185 has a first width W1 in the second direction Y and a first depth D1 in the normal direction Z. Each sub-gate structure 185 is disposed at a first distance I1 from the sub-source structure 180 in the second direction Y. Each sub-gate structure 185 includes a first trench 26, a first insulating film 27, and a first buried electrode 28.

[0479] The plurality of sub-gate structures 185 are respectively arranged in the first sub-active region 171 on the periphery of the active surface 8 (third connection surface 10C) and in regions between the plurality of sub-resistance structures 175, and face the plurality of sub-resistance structures 175 in a one-to-one correspondence in the first direction X. The plurality of sub-gate structures 185 are each formed in a strip shape extending in the first direction X in a plan view, and are formed at intervals in the first direction X from the first side end region 13.

[0480] That is, the plurality of sub-gate structures 185 are arranged in a region on the side of the plurality of sub-resistor structures 175 relative to the positions of the ends of the plurality of gate structures 25 in the first direction X, and face the plurality of gate structures 25, the plurality of source structures 30, the plurality of termination structures 40, the plurality of first dummy structures 55, and the plurality of second dummy structures 60 in the second direction Y.

[0481] The plurality of sub-gate structures 185 are formed in the first direction X at the aforementioned second intervals I2 (sixth intervals I6) from the plurality of sub-resistor structures 175, and are formed in the first direction X at the aforementioned second intervals I2 (sixth intervals I6) from the plurality of first side end regions 13.

[0482] The plurality of sub-gate structures 185 are respectively disposed in regions between pairs of sub-source structures 180 adjacent to each other in the second direction Y, and face the plurality of sub-source structures 180 in the second direction Y. That is, the plurality of sub-gate structures 185 are alternately arranged with the plurality of sub-source structures 180 in the second direction Y.

[0483] The sub-gate structures 185, together with the sub-resistor structures 175, define a plurality of sub-mesa portions MS. The sub-mesa portions MS are located closer to the inner side of the active surface 8 than the side end mesa portions ME in the first direction X. The sub-mesa portions MS are arranged in a line in the second direction Y.

[0484] In this embodiment, the multiple sub-mesa portions MS face the multiple dummy mesa portions MD in the second direction Y. Of course, the multiple sub-mesa portions MS may be arranged shifted to one side and / or the other side in the first direction X from at least one or all of the dummy mesa portions MD so as not to face at least one or all of the dummy mesa portions MD in the second direction Y.

[0485] Of course, the multiple submesa portions MS may be arranged offset from one another in the first direction X so as not to face at least one submesa portion MS in the second direction Y. The multiple submesa portions MS face the multiple gate structures 25, the multiple source structures 30, the multiple termination structures 40, and the multiple first dummy structures 55 in the second direction Y.

[0486] The plurality of sub-gate structures 185 penetrate the body region 21 and the source region 22 to reach the first semiconductor region 6, and are formed at intervals from the bottom of the first semiconductor region 6 toward the active surface 8. The plurality of sub-gate structures 185 control inversion and non-inversion of the channel in the body region 21 in response to a gate potential.

[0487] The above-mentioned plurality of gate connection electrodes 83 selectively cover the plurality of gate structures 25 and the plurality of sub-gate structures 185. In this embodiment, the plurality of gate connection electrodes 83 cover the ends of the plurality of sub-gate structures 185 on the peripheral edge side of the active surface 8. Of course, the plurality of gate connection electrodes 83 may also cover the ends of the plurality of sub-gate structures 185 on the inner side of the active surface 8.

[0488] In this embodiment, the semiconductor device 1B includes at least one resistive film 85 (in this embodiment, multiple resistive films 85) that cover a corresponding sub-resistive structure 175 as a single covering target in a film-like manner. Hereinafter, the resistive film 85 on the sub-resistive region 170 side will be referred to as a "sub-resistive film 190" to distinguish it from the resistive film 85 on the resistive region 17 side. Each sub-resistive film 190 is provided in one-to-one correspondence with each sub-resistive structure 175 and is electrically connected to the corresponding sub-resistive structure 175. Each sub-resistive film 190 may be considered to be one component of the corresponding sub-resistive structure 175.

[0489] In this embodiment, the multiple sub-resistive films 190 are each formed in a strip shape extending in the first direction X in a plan view and face each other in the second direction Y. That is, the multiple sub-resistive films 190 are arranged in a stripe shape extending along the multiple sub-resistive structures 175 in a plan view. The multiple sub-resistive films 190 face the multiple resistive films 85 in the second direction Y and extend parallel to the multiple resistive films 85.

[0490] The multiple sub-resistance films 190 are arranged at intervals in the second direction Y from the sub-resistance structures 175 that are not to be covered, exposing the sub-resistance structures 175 that are not to be covered. The multiple sub-resistance films 190 are arranged at intervals in the second direction Y from the multiple sub-source structures 180, exposing the multiple sub-source structures 180. In other words, the multiple sub-resistance films 190 are arranged alternately with the multiple sub-source structures 180 in the second direction Y in a plan view.

[0491] The sub-resistance films 190 are arranged at intervals in the first direction X from the sub-gate structures 185, exposing the sub-gate structures 185. In other words, the sub-resistance films 190 face the sub-gate structures 185 in the first direction X in a plan view, but do not face the sub-gate structures 185 in the second direction Y in a plan view.

[0492] Each sub-resistance film 190 selectively covers a portion of the sub-resistance structure 175 to partially expose the sub-resistance structure 175. In this embodiment, each sub-resistance film 190 covers an inner portion of the corresponding sub-resistance structure 175 at a distance inward from both ends of the corresponding sub-resistance structure 175 in the first direction X, exposing both ends of the corresponding sub-resistance structure 175. Of course, the sub-resistance film 190 may cover the entire area of ​​the corresponding sub-resistance structure 175.

[0493] In this embodiment, each sub-resistance film 190 selectively covers the fifth buried electrode 53 of the sub-resistance structure 175 so as to partially expose the fifth buried electrode 53. Each sub-resistance film 190 is connected to the fifth buried electrode 53 in the portion covering the corresponding sub-resistance structure 175, and has a portion that is extended from above the fifth buried electrode 53 onto the main surface insulating film 80.

[0494] That is, each sub-resistance film 190 is formed wider in the second direction Y than the corresponding sub-resistance structure 175. Each sub-resistance film 190 faces the body region 21 and the fifth well region 69 in the stacking direction in an area outside the sub-resistance structure 175. When the above-mentioned source region 22 is formed in the sub-resistance region 170, each sub-resistance film 190 may penetrate both of the source regions 22 in the stacking direction.

[0495] In this embodiment, each sub-resistance film 190 is made of the same conductive material as the corresponding fifth buried electrode 53 and is formed integrally with the fifth buried electrode 53. In other words, each sub-resistance film 190 includes a portion of the fifth buried electrode 53 that is extended in the form of a film to an area outside the sub-resistance structure 175 (above the main surface insulating film 80). Of course, each sub-resistance film 190 may be formed separately from the fifth buried electrode 53.

[0496] The resistor openings 90 include a plurality of first resistor openings 91, a plurality of second resistor openings 92, and a plurality of third resistor openings 93. The first resistor openings 91 expose inner portions of the resistor structures 50 as well as inner portions of the sub-resistor structures 175. The second resistor openings 92 expose one ends of the resistor structures 50 as well as one ends of the sub-resistor structures 175. The third resistor openings 93 expose the other ends of the resistor structures 50 as well as the other ends of the sub-resistor structures 175.

[0497] The aforementioned gate pad 101 is disposed on the active region 12 at a distance from the first sub-active region 171 and the second sub-active region 172. That is, the gate pad 101 is disposed at a distance from the plurality of sub-gate structures 185. The gate pad 101 is electrically connected to the plurality of sub-gate structures 185, but does not have a mechanical connection to the plurality of sub-gate structures 185.

[0498] In this embodiment, the pad body 103 of the gate pad 101 is arranged in a region outside the resistance region 17 and the sub-resistance region 170 in plan view. In this embodiment, the pad body 103 is arranged in the active region 12 in plan view, and faces the resistance region 17 across the sub-resistance region 170 in the second direction Y.

[0499] The pad body 103 partially faces the plurality of gate structures 25 and the plurality of source structures 30 across the interlayer film 86. The pad body 103 is disposed on the active region 12 at a distance from the first sub-active region 171 and the second sub-active region 172, and does not face the plurality of sub-gate structures 185 in the stacking direction.

[0500] In this embodiment, the lead-out portion 104 of the gate pad 101 is provided at the end of the pad body portion 103 on the sub-resistor region 170 side, and is led out from the pad body portion 103 across the region on the sub-resistor region 170 to the region on the resistor region 17. As a result, the lead-out portion 104 covers the plurality of resistor structures 50, the plurality of first dummy structures 55, the plurality of sub-resistor structures 175, and the plurality of sub-source structures 180 with the interlayer film 86 sandwiched therebetween.

[0501] The lead-out portion 104 is formed at a distance from the first sub-active region 171 and the second sub-active region 172, and does not face the plurality of sub-gate structures 185 in the stacking direction. In this embodiment, the lead-out portion 104 is formed at a distance inward from both ends of the plurality of resistor structures 50 in plan view, and covers central portions of the plurality of resistor structures 50. The lead-out portion 104 covers the plurality of first resistor openings 91 at a distance from the plurality of second resistor openings 92 and the plurality of third resistor openings 93 in plan view.

[0502] The lead portion 104 extends from above the interlayer film 86 into the plurality of first resistor openings 91, and is mechanically and electrically connected to the plurality of resistor films 85 and the plurality of sub-resistance films 190 within the plurality of first resistor openings 91. In other words, the gate pad 101 penetrates the interlayer film 86 and is mechanically and electrically connected to the inner parts of the plurality of resistor films 85 and the inner parts of the plurality of sub-resistance films 190.

[0503] The gate wiring 102 includes a first resistance wiring 105 , a second resistance wiring 106 , a first line wiring 107 , a second line wiring 108 , a third line wiring 109 and a fourth line wiring 110 .

[0504] In this embodiment, the first resistance wiring 105 is disposed on a portion of the interlayer film 86 that covers one end of the resistance region 17 (one end of the plurality of resistance structures 50) and one end of the sub-resistance region 170 (one end of the plurality of sub-resistance structures 175). The first resistance wiring 105 covers the plurality of resistance structures 50, the plurality of first dummy structures 55, the plurality of sub-resistance structures 175, and the plurality of sub-source structures 180 with the interlayer film 86 sandwiched therebetween.

[0505] The first resistance wiring 105 may have a portion that covers the plurality of second dummy structures 60 and the plurality of sub-gate structures 185 with the interlayer film 86 sandwiched therebetween. The first resistance wiring 105 enters the plurality of second resistance openings 92 from above the interlayer film 86, and is mechanically and electrically connected to one end of the plurality of resistance films 85 and one end of the plurality of sub-resistance films 190 within the plurality of second resistance openings 92.

[0506] That is, the first resistance wiring 105 is electrically connected to one end of the plurality of resistance structures 50 via one end of the plurality of resistance films 85, and is electrically connected to one end of the plurality of sub-resistance structures 175 via one end of the plurality of sub-resistance films 190. The first resistance wiring 105 is electrically connected to the gate pad 101 via the plurality of resistance films 85 (the plurality of resistance structures 50) and the plurality of sub-resistance films 190 (the plurality of sub-resistance structures 175).

[0507] In this embodiment, the second resistance wiring 106 is disposed on a portion of the interlayer film 86 that covers the other end of the resistance region 17 (the other end of the plurality of resistance structures 50) and the other end of the sub-resistance region 170 (the other end of the plurality of sub-resistance structures 175). The second resistance wiring 106 covers the plurality of resistance structures 50, the plurality of first dummy structures 55, the plurality of sub-resistance structures 175, and the plurality of sub-source structures 180 with the interlayer film 86 sandwiched therebetween.

[0508] The second resistance wiring 106 may have a portion that covers the plurality of second dummy structures 60 and the plurality of sub-gate structures 185 with the interlayer film 86 sandwiched therebetween. The second resistance wiring 106 enters the plurality of third resistance openings 93 from above the interlayer film 86, and is mechanically and electrically connected to the other ends of the plurality of resistance films 85 and the other ends of the plurality of sub-resistance films 190 within the plurality of third resistance openings 93.

[0509] That is, the second resistance wiring 106 is electrically connected to the other ends of the plurality of resistance structures 50 via the other ends of the plurality of resistance films 85, and is electrically connected to the other ends of the plurality of sub-resistance structures 175 via the other ends of the plurality of sub-resistance films 190. The second resistance wiring 106 is electrically connected to the gate pad 101 via the plurality of resistance films 85 (the plurality of resistance structures 50) and the plurality of sub-resistance films 190 (the plurality of sub-resistance structures 175).

[0510] In this embodiment, the second extension portion 107b of the first line wiring 107 intersects (specifically, perpendicular to) one end of the multiple gate structures 25, one end of the multiple source structures 30, one end of the multiple sub-source structures 180, and one end of the multiple sub-gate structures 185 in the second direction Y when viewed in a plane.

[0511] The second extension portion 107b enters the plurality of gate openings 87 from above the interlayer film 86, and is electrically connected to one end of the plurality of gate structures 25 and one end of the plurality of sub-gate structures 185 within the plurality of gate openings 87. Specifically, the second extension portion 107b is connected to the plurality of gate connection electrodes 83 within the plurality of gate openings 87. As a result, the first line wiring 107 is electrically connected to one end of the plurality of gate structures 25 and one end of the plurality of sub-gate structures 185 via the plurality of gate connection electrodes 83.

[0512] In this embodiment, the fourth extension portion 108b of the second line wiring 108 intersects (specifically, perpendicular to) the other ends of the multiple gate structures 25, the other ends of the multiple source structures 30, the other ends of the multiple sub-source structures 180, and the other ends of the multiple sub-gate structures 185 in the second direction Y when viewed in a plane.

[0513] The fourth extension portion 108b enters the plurality of gate openings 87 from above the interlayer film 86, and is electrically connected to the other ends of the plurality of gate structures 25 and the other ends of the plurality of sub-gate structures 185 within the plurality of gate openings 87. Specifically, the fourth extension portion 108b is connected to the plurality of gate connection electrodes 83 within the plurality of gate openings 87. As a result, the second line wiring 108 is electrically connected to the other ends of the plurality of gate structures 25 and the other ends of the plurality of sub-gate structures 185 via the plurality of gate connection electrodes 83.

[0514] In this embodiment, the above-described first source pad 121A (second pad portion 121b) covers the plurality of sub-source structures 180 and the plurality of sub-gate structures 185. The first source pad 121A extends into the plurality of source openings 88 from above the interlayer film 86, and is electrically connected to the plurality of sub-source structures 180, the source region 22, and the plurality of contact regions 72 in the plurality of source openings 88.

[0515] In this embodiment, the second source pad 121B (fourth pad portion 121d) described above covers the plurality of sub-source structures 180 and the plurality of sub-gate structures 185. The second source pad 121B extends from above the interlayer film 86 into the plurality of source openings 88, and is electrically connected to the plurality of sub-source structures 180, the source region 22, and the plurality of contact regions 72 in the plurality of source openings 88.

[0516] As described above, the semiconductor device 1B includes a chip 2, a trench electrode type resistor structure 50, and a trench electrode type sub-gate structure 185 (gate structure 25). The chip 2 has a first main surface 3. The resistor structure 50 is formed on the first main surface 3. The sub-gate structure 185 (gate structure 25) is formed on the first main surface 3 so as to be adjacent to the resistor structure 50. This configuration makes it possible to provide the semiconductor device 1B having a novel layout associated with the resistor. In particular, this configuration is effective in expanding the active region 12 because it allows channels to be formed in regions to the sides of the resistor structure 50.

[0517] From another perspective, the semiconductor device 1B includes a chip 2, a trench electrode-type sub-gate structure 185 (gate structure 25), and a sub-resistance film 190 (resistance film 85). The chip 2 has a first main surface 3. The sub-gate structure 185 is formed on the first main surface 3. The sub-resistance film 190 is disposed on the first main surface 3 adjacent to the sub-gate structure 185 and spaced apart from the sub-gate structure 185. This configuration makes it possible to provide the semiconductor device 1B with a novel layout associated with a resistor. In particular, this configuration is effective in expanding the active region 12 because it allows channels to be formed in regions to the sides of the sub-resistance film 190.

[0518] 45 is an enlarged plan view showing the sub-resistor region 170 according to the second layout example together with the resistor region 17 according to the second layout example. The sub-resistor region 170 according to the second layout example has a similar configuration to the resistor region 17 according to the second layout example.

[0519] That is, the plurality of resistive films 85 (sub resistive films 190) associated with the sub resistive region 170 include a plurality of first resistive films 151, a plurality of second resistive films 152, and a plurality of third resistive films 153, similar to the plurality of resistive films 85 associated with the resistive region 17. The description of the plurality of first resistive films 151, a plurality of second resistive films 152, and a plurality of third resistive films 153 on the resistive region 17 side also applies to the description of the plurality of first resistive films 151, a plurality of second resistive films 152, and a plurality of third resistive films 153 on the sub resistive region 170 side.

[0520] 46 is an enlarged plan view showing the sub-resistor region 170 according to the third layout example together with the resistor region 17 according to the third layout example. The sub-resistor region 170 according to the third layout example has a similar configuration to the resistor region 17 according to the third layout example.

[0521] That is, the plurality of resistor openings 90 related to the sub-resistor region 170 includes a plurality of first resistor openings 155 and a plurality of second resistor openings 156, similar to the plurality of resistor openings 90 related to the resistor region 17. The description of the plurality of first resistor openings 155 and the plurality of second resistor openings 156 on the resistor region 17 side also applies to the description of the plurality of first resistor openings 155 and the plurality of second resistor openings 156 on the sub-resistor region 170 side.

[0522] In this embodiment, the plurality of lead-out portions 104 are mechanically and electrically connected to the plurality of resistive films 85 and the plurality of sub-resistive films 190 within the plurality of first resistor openings 155. In this embodiment, the plurality of lead-out wiring portions 162 are mechanically and electrically connected to the plurality of resistive films 85 and the plurality of sub-resistive films 190 within the plurality of second resistor openings 156.

[0523] 47 is an enlarged plan view showing the sub-resistor region 170 according to the fourth layout example together with the resistor region 17 according to the fourth layout example. The sub-resistor region 170 according to the fourth layout example has the same layout and configuration as the resistor region 17 according to the fourth layout example.

[0524] That is, in the sub-resistor region 170 according to the fourth layout example, one or both of a portion of the plurality of first resistor openings 155 and a portion of the plurality of second resistor openings 156 are selectively thinned out.

[0525] Some of the plurality of lead-out portions 104 (dummy lead-out portions 104D) cover the interlayer film 86 at intervals from the plurality of first resistor openings 155, and are electrically isolated from the plurality of sub-resistor structures 175 (resistance film 85). Similarly, some of the plurality of lead-out wiring portions 162 (dummy lead-out wiring portions 162D) cover the interlayer film 86 at intervals from the plurality of second resistor openings 156, and are electrically isolated from the plurality of sub-resistor structures 175 (resistance film 85).

[0526] 48 is an enlarged plan view showing the sub-resistor region 170 according to the fifth layout example together with the resistor region 17 according to the fifth layout example. The sub-resistor region 170 according to the fifth layout example has the same layout and the same configuration as the resistor region 17 according to the fifth layout example.

[0527] That is, the plurality of resistive films 85 associated with the sub-resistive region 170 includes a plurality of first resistive films 165 and a plurality of second resistive films 166. The description of the plurality of first resistive films 165 and the plurality of second resistive films 166 on the resistive region 17 side applies to the description of the plurality of first resistive films 165 and the plurality of second resistive films 166 on the sub-resistive region 170 side.

[0528] Other embodiments of the chip 2 are shown below. Fig. 49 is a cross-sectional view showing another embodiment of the chip 2. Referring to Fig. 49, semiconductor devices 1A and 1B may include a second semiconductor region 7 thinner than the first semiconductor region 6 inside the chip 2. In other words, the chip 2 may include an epitaxial layer thicker than the semiconductor substrate.

[0529] The first semiconductor region 6 may have a thickness of 1 μm or more and 50 μm or less (preferably 5 μm or more and 25 μm or less). The second semiconductor region 7 may have a thickness of 0.1 μm or more and less than 50 μm. The thickness of the second semiconductor region 7 may be 5 μm or more (preferably 10 μm or more).

[0530] 50 is a cross-sectional view showing another example of the chip 2. Referring to Fig. 50, semiconductor devices 1A and 1B may not have the second semiconductor region 7 inside the chip 2 and may include only the first semiconductor region 6.

[0531] In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4, and the first to fourth side surfaces 5A to 5D of the chip 2. That is, in this embodiment, the chip 2 does not have a semiconductor substrate, but has a single-layer structure made of an epitaxial layer. The first semiconductor region 6 may have a thickness of 1 μm to 50 μm (preferably 5 μm to 25 μm).

[0532] The above-described embodiment can be implemented in other embodiments. For example, the above-described embodiment shows a layout including the resistive film 85. However, a layout without the resistive film 85 may be adopted. In this case, the gate pad 101 is directly connected to the resistive structure 50, and the gate wiring 102 is directly connected to the resistive structure 50.

[0533] In the above-described embodiment, the resistance region 17 is located on an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. However, the resistance region 17 may be positioned to one side or the other in the first direction X with respect to the imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.

[0534] That is, the plurality of resistive structures 50 (the plurality of resistive films 85) may be arranged so as to be shifted to one side or the other in the first direction X with respect to an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view. The gate pad 101 may be arranged so as to be shifted to one side or the other in the first direction X with respect to an imaginary line that crosses the center of the active surface 8 in the second direction Y in a plan view.

[0535] In this case, the resistance region 17 (the plurality of resistance structures 50) may be disposed at any corner of the active surface 8 in a plan view. The gate pad 101 may be disposed at any corner of the active surface 8 in a plan view.

[0536] In the above embodiment, an example has been shown in which the gate wiring 102 includes the first to fourth line wirings 107 to 110. However, the gate wiring 102 does not need to include all of the first to fourth line wirings 107 to 110 at the same time, and it is sufficient if the gate wiring 102 includes at least one of the first to fourth line wirings 107 to 110.

[0537] For example, the gate wiring 102 may be employed without the fourth line wiring 110. In this case, the first source pad 121A and the second source pad 121B may be integrally formed. In these cases, the gate wiring 102 may be employed without the third line wiring 109.

[0538] In the above-described embodiment, an example has been shown in which the gate pad 101 is connected to the resistive film 85 (through the resistive opening 90) by penetrating the interlayer film 86. For example, as another example of such a connection form, the gate pad 101 may be connected to the resistive film 85 through a via electrode embedded in the interlayer film 86 (resistive opening 90).

[0539] In the above-described embodiment, an example has been shown in which the gate wiring 102 penetrates the interlayer film 86 (through the resistor opening 90) and is connected to the resistive film 85. For example, as another example of such a connection form, the gate wiring 102 may be connected to the resistive film 85 through a via electrode embedded in the interlayer film 86 (resistor opening 90). Similarly, the gate wiring 102 may be connected to the gate structure 25 (gate connection electrode 83) through a via electrode embedded in the interlayer film 86 (gate opening 87).

[0540] In the above-described embodiment, the source pad 121 is connected to the source structure 30 through the interlayer film 86 (via the source opening 88). As another example of such a connection form, for example, the source pad 121 may be connected to the source structure 30 via a via electrode embedded in the interlayer film 86 (source opening 88).

[0541] For example, in these connection examples, the via electrode may include a via body electrode (e.g., W-based metal) embedded in the interlayer film 86 (resistor opening 90) via a barrier electrode film (e.g., Ti-based metal film).

[0542] In the above-described embodiments, a structure may be adopted in which the conductivity type of an "n-type" semiconductor region is inverted to "p-type" and the conductivity type of a "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0543] In the above-described embodiment, the n-type second semiconductor region 7 is shown. However, a p-type second semiconductor region 7 may be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0544] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in each of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "wide bandgap semiconductor device," "SiC semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0545] [A1] A semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a trench electrode type resistor structure (50) formed on the main surface (3); and a resistor film (85) that covers the resistor structure (50) as a single object to be covered and is electrically connected to the resistor structure (50).

[0546] [A2] The semiconductor device (1A, 1B) according to A1, wherein the resistive film (85) covers a part of the resistive structure (50) and exposes a part of the resistive structure (50).

[0547] [A3] A semiconductor device (1A, 1B) according to A1 or A2, wherein the resistive structure (50) extends in a band shape in one direction in a planar view, and the resistive film (85) extends in a band shape in the one direction in a planar view.

[0548] [A4] The semiconductor device (1A, 1B) according to A3, wherein the resistive film (85) covers the inner part of the resistive structure (50) and exposes the end of the resistive structure (50) in the one direction.

[0549] [A5] A semiconductor device (1A, 1B) according to any one of A1 to A4, wherein a plurality of the resistance structures (50) are formed at intervals on the main surface (3), and a plurality of the resistance films (85) each cover a corresponding one of the resistance structures (50) as a single covering object, and are each electrically connected to the corresponding one of the resistance structures (50).

[0550] [A6] The semiconductor device (1A, 1B) according to any one of A1 to A5, wherein one of the resistive films (85) covers one of the resistive structures (50) in a one-to-one correspondence.

[0551] [A7] The semiconductor device (1A, 1B) according to any one of A1 to A5, wherein a plurality of the resistive films (85) cover one of the resistive structures (50) in a one-to-many correspondence.

[0552] [A8] A semiconductor device (1A, 1B) according to any one of A1 to A7, wherein the resistance structure (50) includes a trench (51) formed in the main surface (3), an insulating film (52) covering the wall surface of the trench (51), and a buried electrode (53) buried in the trench (51) via the insulating film (52), and the resistance film (85) is connected to the buried electrode (53).

[0553] [A9] The semiconductor device (1A, 1B) according to A8, wherein the resistive film (85) is formed integrally with the buried electrode (53).

[0554] [A10] The semiconductor device (1A, 1B) according to A8 or A9, further comprising a main surface insulating film (80) covering the main surface (3) and connected to the insulating film (52), wherein the resistive film (85) has a portion extending from above the buried electrode (53) onto the main surface insulating film (80).

[0555] [A11] The semiconductor device (1A, 1B) according to any one of A1 to A10, further including: a pad electrode (101) disposed on the main surface (3) and electrically connected to the resistive film (85); and a wiring electrode (102) disposed on the main surface (3) at a distance from the pad electrode (101) and electrically connected to the resistive film (85).

[0556] [A12] A semiconductor device (1A, 1B) according to A11, further comprising a pad insulating film (130) covering the connection portion of the pad electrode (101) and the resistive film (85) and having a pad opening (131) exposing the inner portion of the pad electrode (101).

[0557] [A13] A semiconductor device (1A, 1B) according to any one of A1 to A12, further including a trench electrode type electrode structure (55) formed on the main surface (3) adjacent to the resistance structure (50) and to which a potential different from that of the resistance structure (50) is applied, and the resistance film (85) covers the resistance structure (50) at a distance from the electrode structure (55).

[0558] [A14] A semiconductor device (1A, 1B) according to A13, wherein the resistance structure (50) extends in a strip-like manner in a first direction (X) in a planar view, and the electrode structure (55) is formed on the main surface (3) at a distance from the resistance structure (50) in a second direction (Y) perpendicular to the first direction (X) in a planar view, and extends in a strip-like manner in the first direction (X).

[0559] [A15] A semiconductor device (1A, 1B) according to A14, wherein the resistance structure (50) has a first length in the first direction (X), and the electrode structure (55) has a second length in the first direction (X) that is greater than the first length.

[0560] [A16] A semiconductor device (1A, 1B) described in any one of A13 to A15, wherein the resistor structure (50) has a first depth (D3), and the electrode structure (55) has a second depth (D4) greater than the first depth (D3).

[0561] [A17] The semiconductor device (1A, 1B) according to any one of A1 to A16, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); and an impurity region (21) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), wherein the resistance structure (50) penetrates the impurity region (21) so as to reach the semiconductor region (6).

[0562] [A18] A semiconductor device (1A, 1B) according to any one of A1 to A17, further comprising a mesa portion (11) defined on the main surface (3) by a first surface portion (8) located inside the main surface (3), a second surface portion (9) recessed in the thickness direction outside the first surface portion (8), and a connection surface portion (10A to 10D) connecting the first surface portion (8) and the second surface portion (9), and the resistor structure (50) is formed on the first surface portion (8).

[0563] [A19] The semiconductor device (1A, 1B) according to any one of A1 to A18, wherein the chip (2) is a wide bandgap semiconductor chip.

[0564] [A20] The semiconductor device (1A, 1B) according to A19, wherein the chip (2) is a SiC chip.

[0565] [B1] A semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a trench electrode type resistance structure (50) formed on the main surface (3); and a trench electrode type electrode structure (55, 60) formed on the main surface (3) adjacent to the resistance structure (50) and to which a potential different from that of the resistance structure (50) is applied.

[0566] [B2] The semiconductor device (1A, 1B) according to B1, wherein a source potential is applied to the electrode structure (55, 60).

[0567] [B3] A semiconductor device (1A, 1B) according to B1 or B2, wherein the resistor structure (50) has a first depth (D3), and the electrode structure (55, 60) has a second depth (D4) greater than or equal to the first depth (D3).

[0568] [B4] A semiconductor device (1A, 1B) according to any one of B1 to B3, wherein the resistance structure (50) extends in a strip shape in a first direction (X) in a planar view, and the electrode structure (55) is formed on the main surface (3) at a distance from the resistance structure (50) in a second direction (Y) perpendicular to the first direction (X) in a planar view, and extends in a strip shape in the first direction (X).

[0569] [B5] The semiconductor device (1A, 1B) described in B4, wherein the resistor structure (50) has a first length in the first direction (X), and the electrode structure (55) has a second length in the first direction (X) that is greater than the first length.

[0570] [B6] The semiconductor device (1A, 1B) according to B4 or B5 further includes a mesa portion (11) defined on the main surface (3) by a first surface portion (8) located inside the main surface (3), a second surface portion (9) recessed in the thickness direction outside the first surface portion (8), and connection surface portions (10A-10D) connecting the first surface portion (8) and the second surface portion (9), wherein the resistor structure (50) is formed on the first surface portion (8), and the electrode structure (55) is formed on the first surface portion (8).

[0571] [B7] A semiconductor device (1A, 1B) described in B6, wherein the resistor structure (50) is formed on the first surface portion (8) at a distance from the connection surface portion (10A to 10D), and the electrode structure (55) is formed on the first surface portion (8) so as to penetrate the connection surface portion (10A to 10D).

[0572] [B8] The semiconductor device (1A, 1B) according to B6 or B7, further comprising a sidewall structure (81) arranged on the second surface portion (9) so as to cover the connection surface portion (10A to 10D).

[0573] [B9] The semiconductor device (1A, 1B) according to B8, wherein the sidewall structure (81) is made of wiring electrically connected to the electrode structure (55, 60).

[0574] [B10] A semiconductor device (1A, 1B) according to any one of B1 to B3, wherein the resistance structure (50) extends in a strip shape in a first direction (X) in a planar view, and the electrode structure (60) is formed on the main surface (3) at a distance from the resistance structure (50) in the first direction (X) in a planar view, and extends in a strip shape in the first direction (X).

[0575] [B11] The semiconductor device (1A, 1B) according to B10 further includes a mesa portion (11) defined on the main surface (3) by a first surface portion (8) located inside the main surface (3), a second surface portion (9) recessed in the thickness direction outside the first surface portion (8), and connection surface portions (10A-10D) connecting the first surface portion (8) and the second surface portion (9), wherein the resistor structure (50) is formed on the first surface portion (8) at a distance from the connection surface portions (10A-10D), and the electrode structure (60) is formed in a region on the first surface portion (8) between the resistor structure (50) and the connection surface portions (10A-10D).

[0576] [B12] The semiconductor device (1A, 1B) according to B11, wherein the electrode structure (60) penetrates the connection surface portion (10A to 10D).

[0577] [B13] The semiconductor device (1A, 1B) according to B11 or B12, further comprising a sidewall structure (81) arranged on the second surface portion (9) so as to cover the connection surface portion (10A to 10D).

[0578] [B14] The semiconductor device (1A, 1B) according to B13, wherein the sidewall structure (81) is made of wiring electrically connected to the electrode structure (60).

[0579] [B15] The semiconductor device (1A, 1B) according to any one of B1 to B14, further comprising a resistive film (85) covering the resistive structure (50) at a distance from the electrode structure (55, 60).

[0580] [B16] A semiconductor device (1A, 1B) according to any one of B1 to B15, further including a pad electrode (101) arranged on the main surface (3) and electrically connected to the resistor structure (50), and a wiring electrode (102) arranged on the main surface (3) and electrically connected to the resistor structure (50).

[0581] [B17] The semiconductor device (1A, 1B) according to B16, wherein the wiring electrode (102) faces both the resistor structure (50) and the electrode structure (55, 60) in a plan view.

[0582] [B18] The semiconductor device (1A, 1B) according to B16 or B17 further includes an active region (12) set on the main surface (3), a resistance region (17) set on the main surface (3), and a trench electrode type gate structure (25) formed on the main surface (3) of the active region (12), wherein the resistance structure (50) is formed on the main surface (3) of the resistance region (17), and the wiring electrode (102) is electrically connected to the gate structure (25) in the active region (12) and electrically connected to the resistance structure (50) in the resistance region (17).

[0583] [B19] The semiconductor device (1A, 1B) according to B18, further comprising a trench electrode type source structure (30) formed on the main surface (3) of the active region (12) adjacent to the gate structure (25).

[0584] [B20] The semiconductor device (1A, 1B) according to any one of B1 to B19, wherein the chip (2) is a wide bandgap semiconductor chip.

[0585] [C1] A semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a trench electrode type resistance structure (50) formed on the main surface (3); a trench electrode type first electrode structure (55) formed on the main surface (3) at a distance from the resistance structure (50) in one direction (Y) and to which a potential different from that of the resistance structure (50) is applied; and a trench electrode type second electrode structure (60) formed on the main surface (3) at a distance from the resistance structure (50) in an orthogonal direction (X) perpendicular to the one direction (Y) and to which a potential different from that of the resistance structure (50) is applied.

[0586] [C2] The semiconductor device (1A, 1B) described in C1, wherein the second electrode structure (60) faces the resistor structure (50) in the orthogonal direction (X) and faces the first electrode structure (55) in the one direction (Y).

[0587] [C3] The semiconductor device (1A, 1B) according to C1 or C2, wherein a source potential is applied to the first electrode structure (55), and the source potential is applied to the second electrode structure (60).

[0588] [C4] A semiconductor device (1A, 1B) described in any one of C1 to C3, wherein the resistance structure (50) has a first depth (D3), the first electrode structure (55) has a second depth (D4) greater than or equal to the first depth (D3), and the second electrode structure (60) has a third depth (D4) greater than or equal to the first depth (D3).

[0589] [C5] A semiconductor device (1A, 1B) according to any one of C1 to C4, wherein the resistance structure (50) extends in a strip shape in the orthogonal direction (X), the first electrode structure (55) extends in a strip shape in the orthogonal direction (X), and the second electrode structure (60) extends in a strip shape in the orthogonal direction (X).

[0590] [C6] A semiconductor device (1A, 1B) according to C5, wherein the resistor structure (50) has a first length in the orthogonal direction (X), and the first electrode structure (55) has a second length in the orthogonal direction (X) that is greater than the first length.

[0591] [C7] A semiconductor device (1A, 1B) according to any one of C1 to C6, further comprising a mesa portion (11) defined on the main surface (3) by a first surface portion (8) located inside the main surface (3), a second surface portion (9) recessed in the thickness direction outside the first surface portion (8), and connection surface portions (10A to 10D) connecting the first surface portion (8) and the second surface portion (9), wherein the resistor structure (50) is formed on the first surface portion (8), the first electrode structure (55) is formed on the first surface portion (8), and the second electrode structure (60) is formed on the first surface portion (8).

[0592] [C8] A semiconductor device (1A, 1B) described in C7, wherein the resistor structure (50) is formed on the first surface portion (8) at a distance from the connection surface portion (10A to 10D), and the second electrode structure (60) is formed in a region on the first surface portion (8) between the resistor structure (50) and the connection surface portion (10A to 10D).

[0593] [C9] A semiconductor device (1A, 1B) according to C7 or C8, wherein the first electrode structure (55) is formed on the first surface portion (8) so as to penetrate the connection surface portion (10A to 10D).

[0594] [C10] A semiconductor device (1A, 1B) described in any one of C7 to C9, wherein the second electrode structure (60) is formed on the first surface portion (8) so as to penetrate the connection surface portion (10A to 10D).

[0595] [C11] A semiconductor device (1A, 1B) according to any one of C7 to C10, further comprising a sidewall structure (81) arranged on the second surface portion (9) so as to cover the connection surface portion (10A to 10D).

[0596] [C12] The semiconductor device (1A, 1B) according to C11, wherein the sidewall structure (81) is made of wiring electrically connected to the second electrode structure (60).

[0597] [C13] The semiconductor device (1A, 1B) according to any one of C1 to C12, further comprising a resistive film (85) covering the resistive structure (50).

[0598] [C14] A semiconductor device (1A, 1B) according to C13, wherein the resistive film (85) covers the resistive structure (50) at a distance from either or both of the first electrode structure (55) and the second electrode structure (60).

[0599] [C15] A semiconductor device (1A, 1B) according to any one of C1 to C14, further including a pad electrode (101) arranged on the main surface (3) and electrically connected to the resistor structure (50), and a wiring electrode (102) arranged on the main surface (3) and electrically connected to the resistor structure (50).

[0600] [C16] A semiconductor device (1A, 1B) according to C15, wherein the pad electrode (101) faces the resistance structure (50) and the first electrode structure (55) in a planar view, and the wiring electrode (102) faces the resistance structure (50) and the first electrode structure (55) in a planar view.

[0601] [C17] A semiconductor device (1A, 1B) described in C15 or C16, wherein the pad electrode (101) is arranged at a distance from the second electrode structure (60) in a planar view, and the wiring electrode (102) faces the second electrode structure (60) in a planar view.

[0602] [C18] A semiconductor device (1A, 1B) according to any one of C1 to C17, further comprising an active region (12) set on the main surface (3), a resistance region (17) set on the main surface (3), and a trench electrode type gate structure (25) formed on the main surface (3) of the active region (12), wherein the resistance structure (50) is formed on the main surface (3) of the resistance region (17), and the first electrode structure (55) is formed on the main surface (3) of the resistance region (17).

[0603] [C19] The semiconductor device (1A, 1B) according to C18, further comprising a trench electrode type source structure (30) formed on the main surface (3) adjacent to the gate structure (25) in the active region (12).

[0604] [C20] A semiconductor device (1A, 1B) according to any one of C1 to C19, wherein the chip (2) is a wide bandgap semiconductor chip.

[0605] [D1] A semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a first surface portion (8) located inside the main surface (3); a second surface portion (9) recessed in the thickness direction outside the first surface portion (8); and a mesa portion (11) defined on the main surface (3) by connection surface portions (10A-10D) connecting the first surface portion (8) and the second surface portion (9); and a resistive film (85) arranged on the first surface portion (8).

[0606] [D2] The semiconductor device (1A, 1B) according to D1, wherein the resistive film (85) is arranged on the first surface portion (8) at a distance from the connection surface portion (10A to 10D).

[0607] [D3] A semiconductor device (1A, 1B) according to D1 or D2, further comprising a trench electrode type resistance structure (50) formed on the first surface portion (8), wherein the resistance film (85) covers the resistance structure (50).

[0608] [D4] The semiconductor device (1A, 1B) described in D3 further includes a trench electrode type electrode structure (55) formed on the first surface portion (8) adjacent to the resistance structure (50) and to which a potential different from that of the resistance structure (50) is applied.

[0609] [D5] A semiconductor device (1A, 1B) according to any one of D1 to D4, further including a pad electrode (101) arranged on the main surface (3) and electrically connected to the resistive film (85), and a wiring electrode (102) arranged on the main surface (3) and electrically connected to the resistive film (85).

[0610] [D6] A semiconductor device (1A, 1B) according to D5, further comprising an interlayer film (86) covering the resistive film (85), the pad electrode (101) being arranged on the interlayer film (86), and the wiring electrode (102) being arranged on the interlayer film (86).

[0611] [D7] A semiconductor device (1A, 1B) according to D5 or D6, further comprising a pad insulating film (130) that selectively covers the pad electrode (101) and has a pad opening (131) that partially exposes the pad electrode (101).

[0612] [D8] A semiconductor device (1A, 1B) according to any one of D1 to D7, further comprising a sidewall structure (81) arranged on the second surface portion (9) so as to cover the connection surface portion (10A to 10D).

[0613] [D9] A semiconductor device (1A, 1B) according to any one of D1 to D8, wherein the chip (2) is a wide bandgap semiconductor chip.

[0614] [D10] The semiconductor device (1A, 1B) according to D9, wherein the chip (2) is a SiC chip.

[0615] [D11] A semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a first surface portion (8) located inside the main surface (3); a second surface portion (9) recessed in the thickness direction outside the first surface portion (8); a mesa portion (11) defined on the main surface (3) by connection surface portions (10A-10D) connecting the first surface portion (8) and the second surface portion (9); and a trench electrode type resistor structure (50) formed on the first surface portion (8).

[0616] [D12] The semiconductor device (1A, 1B) according to D11, wherein the resistor structure (50) is formed on the first surface portion (8) at a distance from the connection surface portion (10A to 10D).

[0617] [D13] The semiconductor device (1A, 1B) according to D11 or D12, further comprising a resistive film (85) covering the resistive structure (50).

[0618] [D14] A semiconductor device (1A, 1B) according to any one of D11 to D13, further including an electrode structure (55, 60) formed on the first surface portion (8) adjacent to the resistance structure (50) and to which a potential different from that of the resistance structure (50) is applied.

[0619] [D15] A semiconductor device (1A, 1B) according to any one of D11 to D14, further including a pad electrode (101) arranged on the main surface (3) and electrically connected to the resistor structure (50), and a wiring electrode (102) arranged on the main surface (3) and electrically connected to the resistor structure (50).

[0620] [D16] A semiconductor device (1A, 1B) according to D15, further comprising an interlayer film (86) covering the resistor structure (50), the pad electrode (101) being arranged on the interlayer film (86), and the wiring electrode (102) being arranged on the interlayer film (86).

[0621] [D17] A semiconductor device (1A, 1B) according to D15 or D16, further comprising a pad insulating film (130) that selectively covers the pad electrode (101) and has a pad opening (131) that partially exposes the pad electrode (101).

[0622] [D18] A semiconductor device (1A, 1B) according to any one of D11 to D17, further comprising a sidewall structure (81) arranged on the second surface portion (9) so as to cover the connection surface portion (10A to 10D).

[0623] [D19] A semiconductor device (1A, 1B) according to any one of D11 to D18, wherein the chip (2) is a wide bandgap semiconductor chip.

[0624] [D20] The semiconductor device (1A, 1B) according to D19, wherein the chip (2) is a SiC chip.

[0625] [E1] A semiconductor device (1B) including: a chip (2) having a main surface (3); a trench electrode type resistor structure (50, 175) formed on the main surface (3); and a trench electrode type gate structure (25, 185) formed on the main surface (3) adjacent to the resistor structure (50, 175).

[0626] [E2] The semiconductor device (1B) according to E1, wherein the gate structure (25, 185) has a depth (D1) substantially equal to a depth (D3) of the resistor structure (50, 175).

[0627] [E3] The semiconductor device (1B) according to E1 or E2, wherein the gate structure (25, 185) has a width (W1) that is approximately equal to the width (W3) of the resistor structure (50, 175).

[0628] [E4] A semiconductor device (1B) according to any one of E1 to E3, wherein the resistance structure (50, 175) is formed in a strip shape extending in one direction (X) in a planar view, and the gate structure (25, 185) is formed in a strip shape extending in the one direction (X) in a planar view....

Claims

1. A chip having a main surface, A trench electrode type resistance structure formed on the main surface, A semiconductor device including a resistance film that covers the resistance structure as a single object to be coated and is electrically connected to the resistance structure.

2. The semiconductor device according to claim 1, wherein the resistance film covers a part of the resistance structure and exposes a part of the resistance structure.

3. The resistance structure extends in a strip shape in one direction in a plan view, The semiconductor device according to claim 1, wherein the resistance film extends in a strip shape in the one direction in a plan view.

4. The semiconductor device according to claim 3, wherein the resistance film covers an inner part of the resistance structure and exposes an end part of the resistance structure in the one direction.

5. A plurality of the resistance structures are formed on the main surface at intervals, The semiconductor device according to claim 1, wherein a plurality of the resistance films respectively cover one corresponding resistance structure as a single object to be coated and are electrically connected to one corresponding resistance structure respectively.

6. The semiconductor device according to claim 1, wherein one resistance film covers one resistance structure in a one-to-one correspondence.

7. The semiconductor device according to claim 1, wherein a plurality of the resistance films cover one resistance structure in a one-to-many correspondence.

8. The resistance structure includes a trench formed on the main surface, an insulating film covering a wall surface of the trench, and a buried electrode buried in the trench through the insulating film, The semiconductor device according to claim 1, wherein the resistance film is connected to the buried electrode.

9. The semiconductor device according to claim 8, wherein the resistance film is formed integrally with the buried electrode.

10. Further including a main surface insulating film that covers the main surface and is connected to the insulating film, The semiconductor device according to claim 8, wherein the resistance film has a portion drawn from above the buried electrode to above the main surface insulating film.

11. The semiconductor device according to claim 1, wherein the chip is a wide bandgap semiconductor chip.

12. An interlayer film covering the resistance film, A pad electrode disposed on the interlayer film and electrically connected to the resistance film, The semiconductor device according to any one of claims 1 to 11, further including a wiring electrode disposed on the interlayer film and electrically connected to the resistance film.

13. Further comprising a trench electrode type electrode structure formed on the main surface so as to be adjacent to the resistance structure and having a potential different from that of the resistance structure, The semiconductor device according to any one of claims 1 to 11, wherein the resistance film covers the resistance structure with a space from the electrode structure.

14. The resistance structure extends in a strip shape in a first direction in a plan view, The semiconductor device according to claim 13, wherein the electrode structure is formed on the main surface at a distance from the resistance structure in a second direction orthogonal to the first direction in a plan view and extends in a strip shape in the first direction.

15. The resistance structure has a first length in the first direction, The semiconductor device according to claim 14, wherein the electrode structure has a second length greater than the first length in the first direction.

16. The resistance structure has a first depth, The semiconductor device according to claim 13, wherein the electrode structure has a second depth greater than the first depth.

17. A chip having a main surface, A trench electrode type resistance structure formed on the main surface, A semiconductor device including a trench electrode type electrode structure formed on the main surface so as to be adjacent to the resistance structure and having a potential different from that of the resistance structure.

18. The semiconductor device according to claim 17, further comprising a resistance film covering the resistance structure with a space from the electrode structure.

19. A chip having a main surface, A mesa portion partitioned on the main surface by a first surface portion located inside the main surface, a second surface portion recessed in the thickness direction outside the first surface portion, and a connection surface portion connecting the first surface portion and the second surface portion, A semiconductor device including a trench electrode type resistance structure formed on the first surface portion.

20. The semiconductor device according to claim 19, further comprising a resistance film covering the resistance structure on the first surface portion.