Method for manufacturing semiconductor devices

Abstract

Provided is a semiconductor device that can be easily miniaturized. Provided is a semiconductor device in which parasitic capacitance is reduced. This semiconductor device comprises a transistor, a first insulation layer, and a second insulation layer. The transistor has a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulation layer. The first insulation layer is positioned above the first conductive layer and has a first opening that reaches the first conductive layer. The second conductive layer is positioned above the first insulation layer. The semiconductor layer makes contact with the second conductive layer, a side surface of the first insulation layer in the first opening, and an upper surface of the first conductive layer. The third insulation layer makes contact with the upper surface of the first insulation layer and the semiconductor layer in the first opening. The second insulation layer is positioned above the third insulation layer and has a second opening that reaches the third insulation layer, at a position overlapping with the first opening. The third conductive layer is provided so as to fill the second opening and the first opening.

Description

Semiconductor device and manufacturing method thereof

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 also discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0008] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0009] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be easily miniaturized. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device with reduced parasitic capacitance. Another object is to provide a semiconductor device with reduced wiring load. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that exhibits favorable electrical characteristics. Another object is to provide a semiconductor device with high operating speed.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, a display device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is located above the first conductive layer and has a first opening reaching the first conductive layer. The second conductive layer is located above the first insulating layer. The semiconductor layer is in contact with the second conductive layer, as well as a side surface of the first insulating layer in the first opening and an upper surface of the first conductive layer. The third insulating layer is in contact with the semiconductor layer in the first opening. The second insulating layer is located above the third insulating layer and has a second opening reaching the third insulating layer at a position overlapping the first opening. The third conductive layer is provided to fill the second opening and the first opening.

[0014] In the above, the second insulating layer preferably has a portion that is thicker than the third insulating layer.

[0015] In the above, it is preferable to have a wiring that is in contact with the top surface of the third conductive layer and has a portion that overlaps with the semiconductor layer or the second conductive layer with the second insulating layer interposed therebetween.

[0016] In the above, the second opening preferably has a portion extending in one direction, and in this case, the portion of the third conductive layer located within the second opening preferably functions as a wiring.

[0017] In the above, it is preferable that the first opening has a larger opening diameter at its upper end than at its lower end.

[0018] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including forming a first insulating layer having a first opening, forming a semiconductor layer in contact with a side surface of the first insulating layer in the first opening, forming a third insulating layer to cover the first insulating layer and the semiconductor layer, forming a dummy layer on the third insulating layer so as to overlap with the first opening, forming a second insulating layer to cover the third insulating layer and the dummy layer, etching an upper portion of the second insulating layer to expose a top surface of the dummy layer, removing the dummy layer to form a second opening in the second insulating layer that overlaps with the first opening and reaches the third insulating layer, and forming a conductive layer in the second opening.

[0019] In the above, the dummy layer is preferably removed by wet etching.

[0020] In any of the above, it is preferable to further form wiring on the second insulating layer so as to be in contact with the conductive layer.

[0021] According to one embodiment of the present invention, a semiconductor device that can be easily miniaturized can be provided. Alternatively, a semiconductor device that enables high integration can be provided. Alternatively, a semiconductor device with reduced parasitic capacitance can be provided. Alternatively, a semiconductor device with reduced wiring load can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device that exhibits favorable electrical characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided.

[0022] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, a display device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0024] FIGS. 1A and 1B are structural examples of a semiconductor device. FIGS. 2A to 2C are structural examples of a semiconductor device. FIGS. 3A and 3B are structural examples of a semiconductor device. FIGS. 4A to 4D are structural examples of a semiconductor device. FIGS. 5A to 5D are structural examples of a semiconductor device. FIGS. 6A to 6D are structural examples of a semiconductor device. FIGS. 7A to 7C are structural examples of a semiconductor device. FIGS. 8A to 8D are structural examples of a semiconductor device. FIGS. 9A to 9D are structural examples of a semiconductor device. FIGS. 10A and 10D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11A and 11C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12A and 12B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13A and 13B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14A to 14C are structural examples of a memory device. FIGS. 15A and 15B are structural examples of a memory device. FIGS. 16A and 16B are configuration examples of a storage device. FIGS. 17A and 17B are configuration examples of a storage device. FIG. 18 is a configuration example of a storage device. FIG. 19 is a configuration example of a storage device. FIGS. 20A and 20B are configuration examples of a storage device. FIGS. 21A to 21D are configuration examples of a storage device. FIG. 22 is a configuration example of a storage device. FIGS. 23A and 23B are configuration examples of a display device. FIG. 24 is a configuration example of a display device. FIG. 25 is a configuration example of a display device. FIG. 26 is a configuration example of a display device. FIGS. 27A to 27C are configuration examples of a display device. FIGS. 28A and 28B are configuration examples of a display device. FIGS. 29A to 29D are configuration examples of electronic devices. FIGS. 30A to 30F are configuration examples of electronic devices. FIGS. 31A to 31G are configuration examples of electronic devices. FIGS. 32A and 32B are configuration examples of electronic components. 33A to 33C are configuration examples of a mainframe computer, Fig. 34A is a configuration example of space equipment, and Fig. 34B is a configuration example of a storage system.

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0028] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0029] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0030] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0031] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0032] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0033] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0034] In the following description, expressions indicating directions such as "up" and "down" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided in the drawing (such as the surface to be formed, the supporting surface, the adhesive surface, or the flat surface) is located above the laminate, the direction toward the surface may be expressed as "down" and the opposite direction as "up."

[0035] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0036] Embodiment 1 In this embodiment, a structure example of a semiconductor device and a manufacturing method example of the semiconductor device according to one embodiment of the present invention will be described. Hereinafter, a transistor will be described as an example of a semiconductor device.

[0037] In a transistor according to one embodiment of the present invention, the source electrode and the drain electrode are located at different heights (for example, heights in a direction perpendicular to a substrate surface or an insulating plane on which the transistor is provided), and current flows in the semiconductor layer in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can also be called a vertical transistor or a vertical channel transistor.

[0038] More specifically, an insulating layer functioning as a first spacer is provided between a lower electrode, which is one of a source electrode and a drain electrode of a transistor, and an upper electrode, which is the other of the source electrode and the drain electrode of the transistor, and a semiconductor layer, in which a channel is formed, is provided inside a first opening provided in the insulating layer so as to connect the lower electrode and the upper electrode. A gate insulating layer and a gate electrode are provided inside the first opening so as to overlap with the semiconductor layer. Because the source electrode, the semiconductor layer, and the drain electrode can be provided overlapping with each other, the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged on a plane.

[0039] Furthermore, it is preferable to provide a gate wiring electrically connected to the gate electrode. In this case, an insulating layer functioning as a second spacer is provided between the gate wiring and the upper electrode. For example, it is preferable that the second spacer is thicker than the gate insulating layer. It is also preferable that the second spacer is made of a low-dielectric-constant material such as silicon oxide or silicon oxynitride. This effectively reduces the parasitic capacitance between the gate wiring and the upper electrode.

[0040] The gate electrode is provided in each of the second opening provided in the second spacer and the first opening provided in the first spacer, and the upper surface of the gate electrode can be configured to contact a gate wiring provided on the second spacer.

[0041] Alternatively, the gate electrode itself may be used as the gate wiring. For example, the second opening in the second spacer may be formed to have the same shape as the wiring, and the gate electrode may be formed so as to be embedded in the second opening. This simplifies the process because there is no need to provide a separate gate wiring.

[0042] A method for fabricating a semiconductor device includes first forming a semiconductor layer and a gate insulating layer along the side surface of the first spacer at the first opening, forming a second spacer thereon, and then forming a second opening for embedding a gate electrode. Note that, in this method, when forming the second opening, a portion of the second spacer must be etched down to the gate insulating layer. If the gate insulating layer is damaged by etching, the reliability of the transistor may be reduced. Therefore, before forming the second spacer, a dummy pattern (also called a dummy gate) is formed in the position where the gate electrode will be formed later, and the second spacer is formed to cover the dummy gate. Next, the upper portion of the second spacer is etched to expose the top surface of the dummy gate, and the dummy gate is then removed. A gate electrode is formed to fill the recess left by removing the dummy gate. This method allows for the realization of a highly reliable transistor.

[0043] Here, the channel length of the transistor can be precisely controlled by the thickness of the insulating layer that functions as the first spacer, thereby significantly reducing the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer, transistors with extremely short channel lengths can be manufactured. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be manufactured. Therefore, transistors with extremely short channel lengths that could not be realized using exposure equipment for mass production can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be manufactured without using extremely expensive exposure equipment used in cutting-edge LSI technology.

[0044] The transistor of one embodiment of the present invention can have an extremely short channel length, a reduced occupation area, a large current, a small parasitic capacitance, and can operate at high speed. The transistor of one embodiment of the present invention can be applied to various semiconductor devices, such as memory devices, computing devices, display devices, and imaging devices.

[0045] A more specific example will be described below with reference to the drawings.

[0046] 1A and 1B each show a schematic perspective view of a transistor 10. Fig. 1B is a perspective view with a portion cut away from Fig. 1A. In Figs. 1A and 1B, only the outlines of some components (such as interlayer insulating layers) are shown by dashed lines.

[0047] 1A and 1B, the X direction, the Y direction, and the Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both Fig. 1A and Fig. 1B, the directions do not necessarily have to match.

[0048] 2A shows a plan view of the transistor 10, and FIGS. 2B and 2C show schematic cross-sectional views taken along the cutting lines A1-A2 and B1-B2 in FIG. 2A, respectively. Note that some components (such as insulating layers) are omitted in FIG. 2A.

[0049] The transistor 10 is provided on an insulating layer 11 provided on a substrate (not shown). The transistor 10 includes a conductive layer 31 functioning as one of a source electrode and a drain electrode, a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, and a conductive layer 32 functioning as the other of the source electrode and the drain electrode. The conductive layer 31 and the conductive layer 32 also function as wirings.

[0050] A conductive layer 31 is provided over the insulating layer 11, and an insulating layer 41 is provided over the conductive layer 31. A conductive layer 32 is provided over the insulating layer 41. The insulating layer 41 has an opening 20a that reaches the conductive layer 31. The semiconductor layer 21 is provided in contact with an inner wall (also referred to as a side surface or a sidewall) of the opening 20a in the insulating layer 41, and is in contact with the top surface of the conductive layer 31 and the top surface and side surface of the conductive layer 32. The insulating layer 22 is provided to cover the insulating layer 45, the conductive layer 32, and the semiconductor layer 21. A portion of the insulating layer 22 located inside the opening 20a is provided along the top surface of the semiconductor layer 21.

[0051] An insulating layer 42 is provided on the insulating layer 22. The insulating layer 42 overlaps the opening 20a and has an opening 20b that reaches the insulating layer 22. The conductive layer 23 is provided in contact with the surface of the insulating layer 22 so as to be embedded in the openings 20a and 20b.

[0052] The insulating layer 42 and the conductive layer 23 each have a flattened upper surface, and their upper surfaces are at approximately the same height. A conductive layer 33 that functions as wiring is provided on the insulating layer 42. The conductive layer 33 is provided in contact with the upper surface of the conductive layer 23. The conductive layer 33 functions as, for example, gate wiring.

[0053] Here, conductive layer 31 is embedded in insulating layer 44, conductive layer 32 is embedded in insulating layer 45, and conductive layer 33 is embedded in insulating layer 46. Furthermore, the upper surfaces of these layers are planarized, and the heights of the upper surfaces of the conductive layer and insulating layer are approximately the same. This configuration is preferable because it can eliminate the influence of steps. Insulating layer 44, insulating layer 45, and insulating layer 46 function as interlayer insulating layers. It is preferable to use an inorganic insulating material with a low dielectric constant, such as silicon oxide or silicon oxynitride.

[0054] In the transistor 10 having the above-described configuration, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the height direction through the semiconductor. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a vertical field effect transistor (VFET), a vertical transistor, a vertical channel transistor, or the like. Because the source electrode, the semiconductor, and the drain electrode of the transistor 10 can be provided overlapping with each other, the area occupied by the transistor 10 can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (lateral FET), or the like) in which semiconductors are arranged on a plane.

[0055] Furthermore, the channel length of the transistor 10 can be precisely controlled by the thickness of the insulating layer 41, which functions as a spacer, and therefore the variation in channel length can be significantly reduced compared to planar transistors. Furthermore, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more can be fabricated. Therefore, even with conventional mass-production exposure equipment, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0056] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a high on-state current and an extremely low off-state current can be realized at low cost. Unless otherwise specified, the following describes a preferred configuration example in which an oxide semiconductor is used for the semiconductor layer 21.

[0057] The conductive layer 31 and the conductive layer 32 are configured so that the semiconductor layer 21 contacts the upper surface thereof. Therefore, if an oxide semiconductor is used for the semiconductor layer 21, the exposed surfaces of the conductive layer 31 and the conductive layer 32 may be oxidized due to the influence of heat applied during or after the film formation process of the semiconductor film that becomes the semiconductor layer 21, forming an insulating oxide film between the conductive layer 31 and the semiconductor layer 21 and increasing the contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for at least the uppermost portions of the conductive layer 31 and the conductive layer 32. This makes it possible to prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layer 31 and the conductive layer 32. The conductive layer 31 and the conductive layer 32 may also be called an oxide layer, a metal oxide layer, an oxide conductor layer, or the like.

[0058] The conductive layer 31 can be used as one of a source wiring and a drain wiring. The conductive layer 32 can be used as the other of the source wiring and the drain wiring. When one or both of the conductive layer 31 and the conductive layer 32 are used as wirings in this way, it is preferable that the conductive layer 31 and the conductive layer 32 have low electrical resistance. Therefore, it is preferable to use a material having higher conductivity than an oxide conductor, such as a metal, an alloy, or a nitride thereof. In particular, it is preferable that one or both of the conductive layer 31 and the conductive layer 32 have a stacked structure including a layer of the highly conductive material, and that the above-described oxide conductor is used at least in the uppermost portion.

[0059] Here, the transistor 10 is provided at an intersection of a conductive layer 33 functioning as a gate wiring and a conductive layer 32 functioning as a source wiring or a drain wiring. Therefore, parasitic capacitance occurs at an overlapping portion of the conductive layer 33 and the conductive layer 32 at the intersection. However, in one embodiment of the present invention, the insulating layer 42 is provided between the conductive layer 33 and the conductive layer 32, and therefore the parasitic capacitance is significantly reduced compared to a case where the insulating layer 42 is not provided (for example, a case where the conductive layer 33 and the conductive layer 32 overlap with the insulating layer 22 interposed therebetween).

[0060] Furthermore, by increasing the thickness of the insulating layer 42, the parasitic capacitance between the conductive layer 33 and the conductive layer 32 can be reduced. For example, the insulating layer 42 can be made thicker than the insulating layer 22. It is also more preferable to make the insulating layer 42 thicker than at least one of the insulating layers 44, 45, and 46. A thicker insulating layer 42 is preferable because it can reduce the parasitic capacitance between the conductive layer 33 and the conductive layer 32, but the thickness may be determined taking productivity into consideration. For example, the thickness can be set to be no more than two or three times the thickness of the insulating layer 41.

[0061] 2B and 2C show a case where a laminated film of insulating layers 41a, 41b, and 41c is used as the insulating layer 41 in FIGS. 1A and 1B. Also, FIG. 3A shows an enlarged view of FIG. 2B.

[0062] The semiconductor layer 21 is provided in contact with the inner wall of the opening 20a of the insulating layer 41b. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c that have a barrier property against oxygen. This allows oxygen contained in the insulating layer 41b to be confined in a region surrounded by the insulating layer 41a, the insulating layer 41c, and the semiconductor layer 21, and prevents oxygen from being released and reduced during the process, thereby enabling more efficient supply of oxygen to the semiconductor layer 21.

[0063] The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b is a region in which oxygen vacancies are reduced and can be said to be an i-type region. On the other hand, the portion that is not in contact with the insulating layer 41b is preferably an n-type region containing many carriers. That is, the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b can be called a channel formation region, and the region outside of that can be called a low-resistance region (also called a source region or a drain region). In Figure 3A, the channel formation region 21i and the low-resistance region 21n of the semiconductor layer 21 are shown with different hatching patterns.

[0064] 3A, the channel length L of the transistor 10 can be defined as the length of the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b on the shortest path connecting the portion of the semiconductor layer 21 that is in contact with the conductive layer 31 and the portion of the semiconductor layer 21 that is in contact with the conductive layer 32. When the angle (θ) of the sidewall of the opening 20a in the insulating layer 41b is 90 degrees, the channel length L is equal to the thickness of the insulating layer 41b. By making θ smaller (or larger) than 90 degrees, the channel length L can be made larger than the thickness of the insulating layer 41b.

[0065] On the other hand, the channel width W of the transistor 10 depends on the shape of the opening 20a. Figure 3B is a plan view of a cross section taken along the cutting line C1-C2 in Figure 3A at the height where the insulating layer 41b is provided, viewed from the Z direction. Here, the opening 20a is shown as having a cylindrical shape. When the contour of the opening 20a is a circle with a diameter R, the channel width W can be considered to be the circumference of the opening 20a (i.e., = π × R). Here, if the angle θ of the sidewall of the opening 20a in the insulating layer 41b deviates from 90 degrees, the circumference of the opening 20a varies depending on the height. In that case, the circumference at the height where the diameter of the opening 20a is smallest may be considered to be the channel width W, or the circumference at the height of the upper end of the opening 20a may be considered to be the channel width W.

[0066] Because the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a in the insulating layer 41b, the thickness of this portion may be thin depending on the film formation method. For example, with film formation methods such as sputtering or plasma CVD, films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface. On the other hand, with film formation methods such as atomic layer deposition (ALD) or thermal CVD, films of uniform thickness can be formed regardless of the angle of the surface on which they are formed. For example, when the angle θ of the sidewall of the opening 20a in the insulating layer 41b is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0067] The diameter of the opening 20b provided in the insulating layer 42 is preferably the same as or larger than the diameter of the opening 20a provided in the insulating layer 41b. By making the opening 20b larger than the opening 20a, it is possible to prevent the openings 20a and 20b from overlapping due to misalignment when forming the opening 20b, and thus to prevent the opening 20a from being blocked.

[0068] Here, the thickness of the insulating layer 42 may be equal to or greater than the channel length L. For example, by making the thickness of the insulating layer 42 equal to or greater than the thickness of the insulating layer 41b, the parasitic capacitance can be reduced more effectively.

[0069] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0070] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0071] Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element having a high bond energy with oxygen, such as a metal element or semimetal element having a bond energy with oxygen higher than that of In. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0072] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0073] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0074] The semiconductor layer 21 may be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, etc. Ga—Zn oxide may also be used.

[0075] Note that the metal oxide may contain one or more metal elements with a larger periodic number instead of or in addition to In. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a larger periodic number may improve the field-effect mobility of a transistor. Examples of metal elements with a larger periodic number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0076] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0077] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.

[0078] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0079] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0080] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0081] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0082] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0083] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. Note that a stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is also possible to form a metal oxide layer whose composition continuously varies in the thickness direction. This not only broadens the range of design options compared to when a film with a fixed composition is used, but also makes it possible to prevent the generation of interface states and the like between two layers with different compositions, thereby improving electrical characteristics and reliability.

[0084] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a transistor that is normally off and has a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0085] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0086] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is contained, or the content of such an element, also affects the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn=4:3:2 [atomic ratio] and materials in the vicinity thereof, In:Zn=1:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=4:1 [atomic ratio] and materials in the vicinity thereof, and In:Sn:Zn=40:X:10 [atomic ratio] (X is 0.1 or more and 5 or less, typically X=1) and materials in the vicinity thereof. On the other hand, examples of materials having lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn=1:3:2 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:3:4 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=2:2:1 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:1:1 [atomic ratio] and materials in the vicinity thereof, and In:Ga:Zn=1:1:2 [atomic ratio] and materials in the vicinity thereof.

[0087] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0088] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0089] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0090] A semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because an OS transistor has a higher source-drain breakdown voltage than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0091] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger gradation in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0092] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0093] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0094] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0095] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0096] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0097] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0098] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor and also as a dielectric layer of a capacitor element. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0099] In this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen, and a nitride oxide refers to a material containing more nitrogen than oxygen.

[0100] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials, and preferably by using a laminate structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating film (also referred to as ZAZA) can be formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0101] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0).

[0102] <Conductive Layer> The upper surfaces of the conductive layers 31 and 32 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the upper part of the conductive layer 31 or the conductive layer 32, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 31 or the conductive layer 32 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the uppermost parts of the conductive layer 31 and the conductive layer 32.

[0103] For example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are preferably used for the conductive layers 31 and 32. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferred.

[0104] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0105] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element, may be used as the conductive layer 23. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0106] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layer 31 and the conductive layer 32 .

[0107] Since the conductive layers 31 and 32 also function as wirings, a stack of low-resistance conductive materials can be used. The lower the resistance of the conductive layer 33, the more preferable it is. The conductive layers 31, 32, and 33 can be made of the same conductive material as the conductive layer 23.

[0108] <Insulating Layer> The insulating layer 41 (or insulating layer 41b) has a portion in contact with the semiconductor layer 21. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide for at least the portion of the insulating layer 41 in contact with the semiconductor layer 21 in order to improve the interface characteristics between the semiconductor layer 21 and the insulating layer 41. For example, silicon oxide or silicon oxynitride can be suitably used.

[0109] It is more preferable to use a film that releases oxygen when heated for the insulating layer 41. In this case, oxygen is supplied to the semiconductor layer 21 by heat applied during the manufacturing process of the transistor 10, and oxygen vacancies in the semiconductor layer 21 can be reduced, thereby improving reliability. Methods for supplying oxygen to the insulating layer 41 include heat treatment in an oxygen atmosphere and plasma treatment in an oxygen atmosphere. Alternatively, oxygen may be supplied by forming an oxide film on the top surface of the insulating layer 41 in an oxygen atmosphere by sputtering. The oxide film may then be removed.

[0110] The insulating layer 41 is preferably formed by a deposition method such as a sputtering method or a plasma CVD method. In particular, by using a sputtering method without using hydrogen gas as a deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0111] It is preferable that the insulating layers 41a and 41c are made of films through which oxygen does not easily diffuse. This prevents oxygen contained in the insulating layer 41b from permeating through the insulating layer 41a to the insulating layer 11 side and through the insulating layer 41c to the insulating layer 22 side due to heating. In other words, by sandwiching the insulating layer 41b between the insulating layers 41a and 41c, through which oxygen does not easily diffuse, the oxygen contained in the insulating layer 41b can be trapped. This allows oxygen to be effectively supplied to the semiconductor layer 21.

[0112] The insulating layer 41 a and the insulating layer 41 c can be made of, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. In particular, silicon nitride and silicon nitride oxide are suitable for use as the insulating layer 41 a and the insulating layer 41 c because they emit little impurities (for example, water and hydrogen) and are less permeable to oxygen and hydrogen.

[0113] [Modification] The following describes an example in which the configuration is partially different from the above configuration example, and explanations of parts that overlap with the above may be omitted.

[0114] 4A and 4B are schematic cross-sectional views of a transistor 10a. Similar to FIG. 2B, FIG. 4A is a cross-sectional view taken along a plane parallel to the extension direction of the conductive layer 32, and similar to FIG. 2C, FIG. 4B is a cross-sectional view taken along a plane parallel to the extension direction of the conductive layer 33. The transistor 10a differs from the transistor 10 described above mainly in the shape of the opening 20b.

[0115] In the transistor 10a, the end of the semiconductor layer 21 is located inside the opening 20b. Also, as shown in FIG. 4A, the diameter of the opening 20b is larger than the width of the conductive layer 33.

[0116] In this way, by increasing the diameter of the opening 20b, the contact area between the conductive layer 23 and the conductive layer 33 can be increased, and therefore the contact resistance therebetween can be reduced.

[0117] 4C and 4D show an example of a transistor 10b in which the sidewalls of the opening 20a are tapered. In the transistor 10b, the diameter of the opening 20a at its upper end (opening diameter) is larger than the diameter of the opening 20a at its lower end (opening diameter).

[0118] By tapering the sidewalls of the opening 20a, the coverage of the semiconductor layer 21, the insulating layer 22, etc. is improved, and even when a film formation method such as a sputtering method is used, the generation of defects such as low-density regions in the film can be suppressed. For example, the angle θ can be 45 degrees or more and 90 degrees or less, or 60 degrees or more and less than 90 degrees, or 70 degrees or more and less than 90 degrees. Note that when a film formation method with extremely high coverage, such as an ALD method, is used, the angle θ may be greater than 90 degrees.

[0119] When the sidewall of the opening 20a is tapered, the diameter of the opening 20a, which corresponds to the channel width of the transistor 10c, increases from the conductive layer 31 side toward the conductive layer 32 side. In this case, the magnitude of the current flowing through the transistor 10c is limited to the portion with the smallest diameter. Therefore, the channel width of the transistor 10c can be regarded as the perimeter of the portion with the smallest diameter. Therefore, by tapering the sidewall of the opening 20a, a transistor with a channel width smaller than the diameter at the top of the opening 20a can be fabricated.

[0120] 5A and 5B and transistor 10d shown in Figures 5C and 5D are examples in which the angle of the sidewall of not only opening 20a but also opening 20b is deviated from 90 degrees. In particular, as shown in Figures 5C and 5D, the diameter of opening 20b at the upper end is larger than the diameter at the lower end, which is preferable because it allows for a larger contact area between conductive layer 23 and conductive layer 33.

[0121] <Modification 3> A transistor 10e shown in FIGS. 6A and 6B differs from the transistor 10 described above mainly in that it has a conductive layer 26 and an insulating layer 27.

[0122] The conductive layer 26 functions as a second gate electrode (or back gate electrode). The insulating layer 27 is located between the conductive layer 26 and the semiconductor layer 21 and functions as a second gate insulating layer (or back gate insulating layer). A fixed potential or an arbitrary signal can be applied to the conductive layer 26. By providing the conductive layer 26 and applying an appropriate potential to the conductive layer 26, the potential on the back channel side of the semiconductor layer 21 can be fixed, thereby reducing variations in electrical characteristics. The conductive layer 26 may also be electrically connected to any one of the conductive layers 31, 32, and 23 and applied with the same potential.

[0123] The conductive layer 26 is embedded in the insulating layer 41b. Therefore, the conductive layer 26 is provided between the insulating layer 41a and the insulating layer 41c. The insulating layer 27 is provided along the side surfaces of the conductive layer 32, the insulating layer 41c, the conductive layer 26, and the insulating layer 41a. For example, the insulating layer 27 can be formed by forming openings in the conductive layer 32, the insulating layer 41c, the conductive layer 26, and the insulating layer 41a, depositing an insulating film that covers the openings by a film deposition method with high coverage, and then performing anisotropic etching.

[0124] <Modification 4> A transistor 10f shown in FIGS. 6C and 6D differs from the transistors 10, 10a, etc. mainly in that the shape of the conductive layer 31 is different.

[0125] A recess is provided in the conductive layer 31, and the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are provided along the recess. In this case, it is preferable that the height of the lower end of the conductive layer 23 is lower than the height of the upper surface of the conductive layer 31.

[0126] In the transistor 10f, the portion of the semiconductor layer 21 in contact with the conductive layer 31 becomes a region with lower resistance than the channel formation region. Therefore, by positioning the lower end of the conductive layer 23 lower than the upper surface of the conductive layer 31, a gate electric field can be uniformly applied to the entire channel formation region of the semiconductor layer 21, and it is possible to prevent the formation of a high-resistance region (offset region) in the semiconductor layer 21 due to the difficulty of the gate electric field reaching therein. This makes it possible to realize a transistor with an increased on-current. To achieve such a configuration, for example, it is preferable that the thickness of the conductive layer 31 be at least greater than the sum of the thicknesses of the semiconductor layer 21 and the insulating layer 22.

[0127] Although the above describes a configuration capable of reducing the parasitic capacitance between the conductive layer 33 and the conductive layer 32, when the requirements for wiring capacitance are not strict, such as in a circuit that does not require high-speed operation, the conductive layer 23 may serve as both the gate electrode and the gate wiring, and the conductive layer 33 may not be provided. This can significantly reduce the number of manufacturing steps.

[0128] A transistor 10g shown in FIGS. 7A, 7B, and 7C differs from the transistor 10 mainly in that it does not include the conductive layer 33 and that the shape of the conductive layer 23 is partially different.

[0129] In the transistor 10g, the shape of the opening 20b provided in the insulating layer 42 (i.e., the shape of the conductive layer 23) is not cylindrical but is elongated in one direction. The transistor 10g shows an example in which the opening 20b and the conductive layer 23 are elongated in the Y direction.

[0130] In this case, the smaller the diameter of opening 20b in the direction perpendicular to the extension direction (the diameter of opening 20b in FIG. 7B ), i.e., the narrower the width of conductive layer 23, the smaller the area where conductive layer 23 intersects with conductive layer 32, and the less parasitic capacitance therebetween, which is preferable. For example, it is preferable to set this diameter to be equal to or smaller than the width of semiconductor layer 21, or equal to or smaller than the diameter of opening 20a.

[0131] 8A and 8B shows an example in which the diameter of the opening 20b in the direction perpendicular to the extension direction is larger than the width of the semiconductor layer 21. In this way, by increasing the width of the conductive layer 23, the wiring resistance of the conductive layer 23 can be reduced.

[0132] 8C and 8D is a modified example of the transistor 10b, in which the conductive layer 23 also serves as wiring. Similarly, the transistor 10j shown in Figures 9A and 9B is a modified example of the transistor 10e, and the transistor 10k shown in Figures 9C and 9D is a modified example of the transistor 10f.

[0133] The above is a description of the modified example.

[0134] [Manufacturing Method Example] Next, a manufacturing method of the semiconductor device of one embodiment of the present invention will be described. Here, an example of a manufacturing method of the transistor 10 will be described.

[0135] 10A to 13B are schematic cross-sectional views illustrating steps in a method for manufacturing a semiconductor device, which will be described below. In each figure, a cross section corresponding to FIG. 2B is shown on the left side, and a cross section corresponding to FIG. 2C is shown on the right side.

[0136] In the following, an insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor layer can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0137] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0138] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0139] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0140] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0141] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0142] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0143] In addition, the ALD method allows for the deposition of a film of any desired composition by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, the number of cycles of each precursor can be controlled to deposit a film of any desired composition. Similarly to the CVD method, a film with a continuously changing composition can be deposited.

[0144] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate. The insulating layer 11 can be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, it is preferable to perform a planarization process after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0145] Next, a conductive film that will become the conductive layer 31 is formed on the insulating layer 11. Next, a resist mask is formed on the conductive film by photolithography or the like, and the portions of the conductive film that are not covered by the resist mask are removed by etching, and then the resist mask is removed. This allows the conductive layer 31 to be formed. Next, an insulating film that will become the insulating layer 44 is formed, and the portions that overlap with the conductive layer 31 are removed, thereby forming the insulating layer 44 and the conductive layer 31 embedded in the insulating layer 44 ( FIG. 10A ). The insulating film that will become the insulating layer 44 is preferably processed by CMP (Chemical Mechanical Polishing). For example, the insulating film is processed until the top surface of the conductive layer 31 is exposed, thereby forming the insulating layer 44 shown in FIG. 10A .

[0146] Alternatively, the insulating layer 44 and the conductive layer 31 may be formed by first forming an insulating film that will become the insulating layer 44, then forming an opening in the insulating film, forming a conductive film to fill the opening, and then performing a polishing process (planarization process) using the CMP method until the top surface of the insulating film is exposed.

[0147] By performing a planarization process so that the heights of the upper surfaces of the insulating layer 44 and the conductive layer 31 are the same, it is possible to flatten the upper surface of the subsequently formed insulating layer 41. Note that the insulating layer 41 may be provided to cover the conductive layer 31 without providing the insulating layer 44, and in that case, it is preferable to flatten the upper surface of the insulating layer 41 by performing a planarization process by a CMP method.

[0148] Subsequently, insulating layers 41a, 41b, and 41c (hereinafter, these may be collectively referred to as insulating layers 41) are formed on the conductive layer 31 and the insulating layer 44 (FIG. 10B). The insulating layers 41a, 41b, and 41c may be formed by appropriate methods such as sputtering, CVD, MBE, PLD, and ALD.

[0149] Here, since the thickness of the insulating layer 41 affects the channel length of the transistor, it is important to prevent variations in the thickness of the insulating layer 41 .

[0150] Furthermore, by forming the insulating layer 41b by sputtering in an oxygen-containing atmosphere, the insulating layer 41b can be formed to contain a large amount of oxygen. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 41b can be reduced. By forming the insulating layer 41b in this manner, oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0151] Next, the conductive layer 32 and the insulating layer 45 are formed on the insulating layer 41 (FIG. 10C). The conductive layer 32 and the insulating layer 45 can be formed in the same manner as the conductive layer 31 and the insulating layer 44.

[0152] Subsequently, an opening 20a is formed in the conductive layer 32 and the insulating layer 41, reaching the conductive layer 31 (FIG. 10D).

[0153] The sidewall of the opening 20 a is preferably perpendicular to the top surface of the conductive layer 31. With this structure, a transistor with a small occupation area can be manufactured. Alternatively, the sidewall of the opening 20 a may be tapered. The tapered shape can improve the coverage of a film formed inside the opening 20 a.

[0154] The maximum width of the opening 20a (maximum diameter when the opening 20a is circular in plan view) is preferably as small as possible. For example, the maximum width of the opening 20a is 1 μm or less, 500 nm or less, 300 nm or less, 150 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 5 nm or more. In particular, to process the opening 20a finely, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0155] Because the opening 20a has a large aspect ratio, it is preferable to form it using anisotropic etching. Processing by dry etching is particularly preferable because it is suitable for fine processing. Furthermore, the etching conditions for this processing may be different for each of the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a. The angle of the sidewall of the opening 20a may be different for each of the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a.

[0156] Furthermore, when etching the insulating layer 41, a part of the upper part of the conductive layer 31 may be etched, and the conductive layer 31 at the bottom of the opening 20 a may become thin. Alternatively, after the opening 20 a is formed, a part of the upper part of the conductive layer 31 may be etched to thin the conductive layer 31.

[0157] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., more preferably 320° C. to 450° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0158] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 41 and the like as much as possible.

[0159] Next, a semiconductor film that will become the semiconductor layer 21 is formed to cover the insulating layer 41, the conductive layer 31, the conductive layer 32, the opening 20a, the insulating layer 45, etc., and unnecessary portions are removed by etching to form the semiconductor layer 21 (Figure 11A).

[0160] An oxide semiconductor film can be used as the semiconductor film. The oxide semiconductor film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate. The oxide semiconductor film is preferably formed in contact with the bottom and sidewall of the opening 20 a having a large aspect ratio. Therefore, the oxide semiconductor film is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like. For example, an In—Ga—Zn oxide film can be formed by an ALD method. When the opening 20 a has a tapered shape, the oxide semiconductor film can be formed by a sputtering method.

[0161] Furthermore, during or after the formation of an oxide semiconductor film, microwave treatment is preferably performed in an atmosphere containing oxygen to reduce the impurity concentration in the oxide semiconductor film. Examples of impurities include hydrogen and carbon. The microwave treatment can improve the crystallinity of the oxide semiconductor film in some cases. Here, the microwave treatment refers to treatment using, for example, an apparatus having a power supply that generates high-density plasma using microwaves.

[0162] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be used. Oxygen acting on an oxide semiconductor can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). The oxygen acting on an oxide semiconductor may take one or more of the above forms, and oxygen radicals are particularly preferred.

[0163] Furthermore, when the microwave treatment is performed in the oxygen-containing atmosphere, the substrate is preferably heated to a temperature of 100° C. to 650° C., preferably 200° C. to 600° C., more preferably 300° C. to 450° C., because the impurity concentration in the oxide semiconductor film can be further reduced by heating the substrate.

[0164] By heating the substrate during the microwave treatment in the oxygen-containing atmosphere, the carbon concentration in the oxide semiconductor film obtained by SIMS was increased to 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 1×10 １８ atoms / cm ３ It can be less than.

[0165] Although the above example illustrates a configuration in which microwave treatment is performed on an oxide semiconductor film in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the oxide semiconductor film in an atmosphere containing oxygen. This converts hydrogen contained in the silicon oxide film into H ２ The hydrogen can be released to the outside as O. By releasing hydrogen from the silicon oxide film located in the vicinity of the oxide semiconductor film, a highly reliable semiconductor device can be provided.

[0166] Furthermore, when the semiconductor layer 21 has a stacked structure, the deposition methods for each layer may be the same or different. For example, when the semiconductor layer 21 has a two-layer stacked structure, the lower layer of the oxide semiconductor film may be deposited by sputtering, and the upper layer of the oxide semiconductor film may be deposited by ALD. Oxide semiconductor films deposited by sputtering tend to have crystallinity. Therefore, by providing a crystalline oxide semiconductor film as the lower layer of the oxide semiconductor film, the crystallinity of the upper layer of the oxide semiconductor film can be improved. Even if pinholes or discontinuities are formed in the lower layer of the oxide semiconductor film deposited by sputtering, the overlapping portions can be blocked by the upper layer of the oxide semiconductor film deposited by ALD, which has good coverage.

[0167] Here, the oxide semiconductor film is preferably formed in contact with the upper surface of the conductive layer 31 in the opening 20 a , the side surface of the insulating layer 41 in the opening 20 a , and the side surface and upper surface of the conductive layer 32 on the insulating layer 41 .

[0168] After the oxide semiconductor film is formed, heat treatment is preferably performed. The heat treatment may be performed at a temperature range in which the oxide semiconductor film does not become polycrystallized, such as 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for desorbed oxygen.

[0169] The gas used in the heat treatment is preferably highly purified. For example, the gas used in the heat treatment may contain moisture of 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film and the like as much as possible.

[0170] Here, it is preferable to perform the heat treatment while the semiconductor film is in contact with the insulating layer 41b containing a large amount of oxygen, so that oxygen can be supplied from the insulating layer 41b to a portion of the semiconductor film that will become a channel formation region, thereby reducing oxygen vacancies.

[0171] Although the heat treatment is performed after the oxide semiconductor film is formed in the above example, the present invention is not limited to this. The heat treatment may be performed in a later step.

[0172] Subsequently, the insulating layer 22 is formed to cover the insulating layer 45, the conductive layer 32, and the semiconductor layer 21 (FIG. 11B). The insulating layer 22 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0173] It is preferable that the insulating layer 22 be provided on the side surface of the semiconductor layer 21 in the opening 20a with as uniform a thickness as possible. Therefore, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. Note that if the side wall of the opening 20a has a tapered shape, the insulating layer 22 can be formed using a film formation method such as a sputtering method.

[0174] Subsequently, a dummy layer 35 is formed on the insulating layer 22 at a position overlapping the opening 20a (FIG. 11C).

[0175] The dummy layer 35 is formed at a position where the conductive layer 23 will be formed later. Therefore, a portion of the dummy layer 35 is provided so as to be embedded in the opening 20a. The dummy layer 35 is also formed so that its upper portion protrudes above the upper surface of the portion of the insulating layer 22 that overlaps with the conductive layer 32 and the semiconductor layer 21. A higher height of the protruding portion is preferable because it allows the thickness of the insulating layer 42 to be formed later to be thicker.

[0176] Because the dummy layer 35 is a layer that will be removed in a later process, it is preferable to use a material that can achieve a large etching selectivity with respect to the films (insulating layer 22, insulating layer 42, etc.) that the dummy layer 35 contacts. For example, the dummy layer 35 can be a film having a different composition from the insulating layer 22 and insulating layer 42. More specifically, the dummy layer 35 can be a film containing different constituent elements from the insulating layer 22 and insulating layer 42, a film containing the same constituent elements as the insulating layer 22 and insulating layer 42 but with a different composition, or a film having a different density from the insulating layer 22 and insulating layer 42. Furthermore, either or both of the insulating layer 22 and insulating layer 42 may be a film containing a different constituent element from the dummy layer 35.

[0177] In particular, it is preferable to form the dummy layer 35 using a film formation method or under conditions that minimize film formation damage to the insulating layer 22. When forming the film by sputtering or CVD, it is preferable to form the film under conditions that minimize damage to the surface to be formed, such as by lowering the power supply voltage. Furthermore, film formation methods such as vacuum deposition, ALD, and wet methods are suitable for forming the dummy layer 35 because they cause very little damage to the surface to be formed. Examples of wet methods that can be used to form the dummy layer 35 include spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0178] Furthermore, it is preferable to use a material that can be removed by wet etching for the dummy layer 35. This significantly reduces damage to the insulating layer 22 when etching the dummy layer 35 compared to when dry etching is used.

[0179] The dummy layer 35 can be made of various materials as long as it is a film having a composition different from that of the insulating layer 22 and the insulating layer 47. Examples of the material include semiconductor films such as silicon and germanium, inorganic insulating films such as silicon nitride, silicon nitride oxide, aluminum oxide, and aluminum nitride, metal films such as aluminum, copper, molybdenum, and tungsten, and oxide conductor films such as indium oxide and zinc oxide.

[0180] Alternatively, an organic film such as an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimideamide resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins may be used as the dummy layer 35. Such an organic insulating film is preferable because it can be formed by a film formation method (e.g., a wet method or a vacuum deposition method) that causes little damage to the surface on which it is formed, and because there is a high degree of freedom in selecting a chemical solution (etchant) that can be used for wet etching.

[0181] After the dummy layer 35 is formed, the dummy layer 35 may be reduced in size (also referred to as shrinkage) by performing isotropic etching. This makes it possible to miniaturize the dummy layer 35 even when a material that is difficult to form a fine pattern into by photolithography is used.

[0182] Next, an insulating layer 42 is formed to cover the insulating layer 22 and the dummy layer 35 (FIG. 12A). The insulating layer 42 can be formed in the same manner as the insulating layer 41b. At this time, an unevenness reflecting the shape of the dummy layer 35 is formed on the upper surface of the insulating layer 42.

[0183] Subsequently, the insulating layer 42 is polished (planarized) using CMP to expose the upper surface of the dummy layer 35 (FIG. 12B). At the same time, the upper surface of the insulating layer 42 can be planarized.

[0184] Next, the dummy layer 35 is removed by etching ( FIG. 13A ). As described above, it is preferable to etch the dummy layer 35 by a method that has a high etching selectivity with respect to the insulating layer 22 and the insulating layer 42. In particular, it is preferable to remove the dummy layer 35 by wet etching. At this time, it is important to use an etchant and etching conditions that have a high etching selectivity with respect to the insulating layer 22 and the insulating layer 42.

[0185] For example, when an organic film is used for the dummy layer 35, etching damage to the insulating layer 22 can be minimized by using a wet etching method that uses an organic solvent as an etchant.

[0186] Alternatively, when the dummy layer 35 is made of an organic material, the dummy layer 35 may be etched by plasma treatment (also called ashing) in an atmosphere containing oxygen.

[0187] By removing the dummy layer 35, an opening 20b can be formed in the insulating layer 42.

[0188] After removing the dummy layer 35, a heat treatment may be performed. In particular, when wet etching is used to etch the dummy layer 35, this is preferable because the heat treatment can remove water adsorbed on the surfaces of the insulating layer 42 and the insulating layer 22. The above description can be referred to for the method of the heat treatment.

[0189] Next, a conductive film that will later become the conductive layer 23 is formed on the insulating layer 42. The conductive film is provided so that a portion of the conductive film is embedded in the openings 20a and 20b. The conductive film is preferably formed by a film formation method that has high coverage or embedding properties, and more preferably, a CVD method or an ALD method, for example. Note that if the sidewalls of the openings 20a and 20b are tapered, the conductive film can be formed by a sputtering method.

[0190] Next, the upper part of the conductive film is etched by CMP, dry etching, or the like until the upper surface of the insulating layer 42 is exposed, thereby forming a conductive layer 23 buried in the openings 20a and 20b (FIG. 13B).

[0191] Finally, the conductive layer 33 and the insulating layer 46 are formed on the insulating layer 42 and the conductive layer 23. The conductive layer 33 and the insulating layer 46 can be formed in the same manner as the conductive layer 31 and the insulating layer 44.

[0192] Through the above steps, the transistor 10 can be manufactured.

[0193] According to the manufacturing method of one embodiment of the present invention, damage to a gate insulating layer can be reduced, and therefore a highly reliable semiconductor device can be realized. In addition, a thick interlayer insulating layer can be formed between the gate wiring and one of the source wiring and the drain wiring, which reduces parasitic capacitance and enables a transistor applicable to a circuit that requires high-speed operation.

[0194] The above is an explanation of an example of the manufacturing method.

[0195] [Application Example] A configuration of a memory device using a transistor and a capacitor will be described below.

[0196] 14A shows a circuit diagram of a memory cell 30. The memory cell 30 is configured with one transistor Tr1 and one capacitor C, and can also be represented as 1Tr1C. The transistor Tr1 has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor C. The other electrode of the capacitor C is connected to a wiring PL.

[0197] The memory cell 30 can store data by holding, in the capacitor C, a data potential input from the wiring BL via the transistor Tr1. Furthermore, data can be held by turning the transistor Tr1 off. Furthermore, by turning the transistor Tr1 on, a potential corresponding to the held data is output to the wiring BL, allowing the data to be read. A signal that controls the conduction and non-conduction of the transistor Tr1 is applied to the wiring WL. Furthermore, a predetermined potential (e.g., a fixed potential) is applied to the wiring PL.

[0198] 14B and 14C show cross-sectional views of the memory cell 30. Fig. 14B is a cross-sectional view taken along the extension direction of the conductive layer 32, and Fig. 14C is a cross-sectional view taken along the extension direction of the conductive layers 31 and 33. The memory cell 30 has a configuration in which a transistor 10 is stacked on a capacitance element 50. The transistor 10 corresponds to the transistor Tr1, and the capacitance element 50 corresponds to the capacitance element C.

[0199] The above description can be referred to for the configuration of the transistor 10, and therefore the description thereof will be omitted. Note that although an example in which the transistor 10 is used is shown here, the transistor is not limited to the transistor 10 and can be replaced with any of the various transistors described above.

[0200] The capacitance element 50 includes a conductive layer 51, a conductive layer 52, and an insulating layer 53 sandwiched therebetween. The capacitance element 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0201] The capacitor element 50 is provided on the insulating layer 11. A conductive layer 34 is provided on the insulating layer 11, and an insulating layer 47 is provided on the conductive layer 34. An opening 20c is provided in the insulating layer 47, reaching the conductive layer 34. A conductive layer 51 is provided inside the opening 20c, in contact with the side surface of the insulating layer 47 and the upper surface of the conductive layer 34. An insulating layer 53 is provided to cover the insulating layer 47 and the conductive layer 51. An insulating layer 48 is provided on the insulating layer 53, and an opening 20d is provided in the insulating layer 48, which overlaps with the opening 20c. A conductive layer 52 is provided so as to be embedded in the opening 20d and the opening 20c.

[0202] The conductive layer 52 and the insulating layer 48 have flattened upper surfaces and are at approximately the same height. The insulating layer 44 and the conductive layer 31 are provided on the conductive layer 52 and the insulating layer 48. The conductive layer 31 is provided in contact with the upper surface of the conductive layer 52.

[0203] 14B and 14C, the conductive layer 32 corresponds to the wiring BL, the conductive layer 33 corresponds to the wiring WL, and the conductive layer 34 corresponds to the wiring PL.

[0204] A low-resistance conductive material can be used for the conductive layer 34, the conductive layer 51, and the conductive layer 52. For example, the material that can be used for the conductive layer 23 can be applied.

[0205] The insulating layer 53 functions as a dielectric layer of the capacitance element 50. The thinner the insulating layer 53 is and the higher the relative dielectric constant thereof is, the larger the capacitance of the capacitance element 50. For example, it is preferable to use a high-k material that can be used for the insulating layer 22.

[0206] 15A and 15B show an example of a memory device in which two memory cells 30 are connected to a common wiring. Fig. 15A is a schematic top view of the memory device, and Fig. 15B is a schematic cross-sectional view taken along line A3-A4 in Fig. 15A.

[0207] The conductive layer 33 functioning as the wiring WL is provided for each of the two memory cells 30. The conductive layer 32 functioning as the wiring BL is provided in common to the two memory cells 30.

[0208] The conductive layer 32 functioning as the wiring BL is embedded in each interlayer insulating layer and is electrically connected to the conductive layer 61 and the conductive layer 62 functioning as plugs (also referred to as connection electrodes). The conductive layer 61 may be electrically connected to a sense amplifier (not shown) provided below the insulating layer 11. The conductive layer 61 may also be electrically connected to the conductive layer 32 of a memory cell stacked above the insulating layer 65.

[0209] The insulating layer 65 functions as a barrier layer and has a function of preventing impurities such as water and hydrogen from diffusing into the memory device from the outside.

[0210] Furthermore, a memory cell array can be configured by arranging the memory cells 30 in a three-dimensional matrix. As an example of a memory cell array, Figures 16A and 16B show an example of a memory device in which 4 x 2 x 4 memory cells 30 are arranged in the X, Y, and Z directions. Figure 16A is a plan view of the memory device, and Figure 16B is a cross-sectional view taken along the cutting line A3-A4 in Figure 16A.

[0211] A group of four memory cells 30 can be called a memory unit 60. 16A and 16B show eight memory units (memory unit 60[1,1] to memory unit 60[2,4]). In memory unit 60[a,b] (a and b are positive integers), a indicates an address in the Y direction, and b indicates an address in the Z direction.

[0212] In the memory unit 60, two memory cells 30 are arranged symmetrically around the conductive layer 61 or the conductive layer 62. The conductive layers 32 of the memory units 60 stacked in the Z direction are electrically connected to each other by the conductive layer 62. By stacking a plurality of memory units 60 in this way, it is possible to increase the storage capacity per unit area, and to provide a memory device that can be miniaturized or highly integrated.

[0213] 17A and 17B show an example in which the connection portion is arranged at the end of the memory unit. FIG. 17A is a plan view of the memory device, and FIG. 17B is a cross-sectional view. Here, as an example of a memory cell array, an example of a memory device in which 3 x 3 x m (m is an integer of 2 or more) memory cells 30 are arranged is shown. Of the layers having memory cells 30, the first layer is denoted as layer 70[1], and the mth layer (top) is denoted as layer 70[m].

[0214] The conductive layer 63 is provided outside the memory unit. The conductive layer 63 may be connected to wiring in a layer above the layer 70 including the conductive layer 63. For example, the conductive layer 63 provided in the layer 70[1] is electrically connected to wiring in the layer 70[2]. However, this is not limiting, and the conductive layer 63 may be configured to be electrically connected to wiring in the layer 70 located below the layer 70 including the conductive layer 63.

[0215] FIG. 18 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells 30 is stacked on a layer in which a driver circuit including a sense amplifier is provided.

[0216] 18 shows an example in which a capacitor 50 is stacked above a transistor 90, and the transistor 10 is stacked thereon. The transistor 90 is one of the transistors included in the sense amplifier.

[0217] By configuring the sense amplifier so that it overlaps with the memory cell 30, the bit line can be shortened. This reduces the load on the bit line, improving the read sensitivity of the sense amplifier. As a result, the storage capacitance of the memory cell can be reduced.

[0218] The transistor 90 is provided over a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95 a and 95 b functioning as source and drain regions. The transistor 90 may be either a p-channel type or an n-channel type.

[0219] 18, a semiconductor region 92 (part of a substrate 91) where a channel is formed has a convex shape. A conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 with an insulating layer 93 interposed therebetween. Such a transistor 90 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate.

[0220] It is preferable that a structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) be provided between a layer in which the transistor 90 is provided and a layer in which the memory cell 30 is provided. In the example shown in Figure 18, the low-resistance region 95b of the transistor 90 is electrically connected to the conductive layer 32 functioning as a bit line of the memory cell 30 via a wiring and a plug.

[0221] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0222] 19 to 22. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided will be described.

[0223] 19 is a block diagram illustrating a configuration example of a memory device 480 according to one embodiment of the present invention. The memory device 480 illustrated in FIG. 19 includes a layer 420 and a stacked layer 470.

[0224] The layer 420 is a layer including a Si transistor. The layer 470 includes stacked element layers 430[1] to 430[m] (m is an integer of 2 or more). The element layers 430[1] to 430[m] include OS transistors. The layer 470 including stacked layers including OS transistors can be provided over the layer 420.

[0225] 19 illustrates an example in which the element layers 430[1] to 430[m] each include a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n ​​is an integer of 2 or greater).

[0226] In FIG. 19 , the memory cell 432 in the first row and first column is indicated as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is indicated as memory cell 432[m,n]. In this embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In this embodiment and the like, the memory cell 432 in the ith row and jth column is indicated as memory cell 432[i,j]. In this embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is used, "j+α" is not less than 1 or more than n.

[0227] 19 illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n]. Note that the number of element layers 430[1] to 430[m] does not have to be the same as the number of wirings WL (and wirings PL).

[0228] The memory cells 432 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 432 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0229] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring for transmitting a back gate potential can be provided separately.

[0230] The memory cells 432 included in each of the element layers 430[1] to 430[m] are connected to a sense amplifier 446 (sense amplifier) ​​via a wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the surface of the substrate on which the layer 420 is provided. The wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] can be configured as wirings arranged vertically in addition to wirings arranged horizontally on the surface of the substrate, thereby shortening the length of the wiring between the element layer 430 and the sense amplifier 446. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. This can reduce the power consumption and signal delay of the memory device 480. Furthermore, the memory cell 432 can operate even if the capacitance of the capacitor included in the memory cell 432 is reduced. This can reduce the size of the memory device 480.

[0231] The layer 420 includes a PSW 471 (power switch), a PSW 472, and a peripheral circuit 422. The peripheral circuit 422 includes a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit included in the layer 420 includes a Si transistor.

[0232] In the memory device 480, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0233] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 473.

[0234] The control circuit 473 is a logic circuit having the function of controlling the overall operation of the memory device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 480. Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operation mode is executed.

[0235] The voltage generation circuit 474 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0236] The driver circuit 440 is a circuit for writing and reading data to and from the memory cells 432. The driver circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the sense amplifier 446 described above.

[0237] The row decoder 442 and the column decoder 444 have a function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying a row to be accessed, and the column decoder 444 is a circuit for specifying a column to be accessed. The row driver 443 has a function of selecting a wiring WL specified by the row decoder 442. The column driver 445 has a function of writing data to the memory cell 432, a function of reading data from the memory cell 432, a function of holding the read data, and the like.

[0238] The input circuit 447 has a function of holding a signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is data (Din) to be written to the memory cell 432. The data (Dout) read from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has a function of holding Dout. In addition, the output circuit 448 has a function of outputting Dout to the outside of the memory device 480. The data output from the output circuit 448 is a signal RDA.

[0239] The PSW 471 has a function of controlling the supply of VDD to the peripheral circuit 422. The PSW 472 has a function of controlling the supply of VHM to the row driver 443. In this example, the high power supply voltage of the memory device 480 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 471 is controlled by a signal PON1, and the on / off of the PSW 472 is controlled by a signal PON2. In FIG. 19, the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0240] The element layers 430[1] to 430[m] can be stacked on the layer 420. Figure 20A is a perspective view of a memory device 480 showing five (m = 5) element layers 430[1] to 430[5] stacked on the layer 420.

[0241] 20A, the element layer 430 provided in the first layer is shown as element layer 430[1], the element layer 430 provided in the second layer is shown as element layer 430[2], and the element layer 430 provided in the fifth layer is shown as element layer 430[5]. Also shown in FIG. 20A are wirings WL and PL extending in the X direction, and wirings BL and BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the driver circuit is provided). The wiring BLB is an inverted bit line. Note that, to make the drawing easier to understand, the wirings WL and PL included in each element layer 430 are partially omitted.

[0242] 20B is a schematic diagram illustrating a configuration example of the sense amplifier 446 connected to the wiring BL and the wiring BLB shown in FIG. 20A and the memory cells 432 included in the element layers 430[1] to 430[5] connected to the wiring BL and the wiring BLB. Note that a configuration in which a plurality of memory cells (memory cells 432) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string."

[0243] 20B illustrates an example of a circuit configuration of the memory cell 432 connected to the wiring BLB. The memory cell 432 includes a transistor 437 and a capacitor 438. Regarding the transistor 437, the capacitor 438, and the wirings (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] may also be referred to as wiring BL and wiring WL. The memory cell 30 exemplified in the above embodiment can be applied to the memory cell 432. That is, the transistor 10 can be used as the transistor 437, and the capacitor 50 can be used as the capacitor 438. The transistor 90 (see FIG. 18 ) can be used as the transistor included in the sense amplifier 446.

[0244] In the memory cell 432, one of the source and the drain of the transistor 437 is connected to a wiring BL. The other of the source and the drain of the transistor 437 is connected to one electrode of a capacitor 438. The other electrode of the capacitor 438 is connected to a wiring PL. The gate of the transistor 437 is connected to a wiring WL.

[0245] The wiring PL is a wiring that applies a constant potential for maintaining the potential of the capacitor 438. The number of wirings can be reduced by connecting a plurality of wirings PL to each other and using them as one wiring.

[0246] In one embodiment of the present invention, OS transistors are stacked, and a wiring functioning as a bit line is arranged perpendicular to the surface of the substrate on which the layer 420 is provided. Additionally, the transistor 437 and the capacitor 438 included in the memory cell 432 are arranged side by side in the perpendicular direction to the surface of the substrate on which the layer 420 is provided. By providing each element and each wiring perpendicular to the surface of the substrate, the length of the wiring between element layers can be shortened and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent storage capacity and reduced power consumption can be obtained.

[0247] 21A and 21B show circuit diagrams corresponding to the memory cell 432 described above and circuit block diagrams corresponding to the circuit diagrams. As shown in FIGS. 21A and 21B, the memory cell 432 may be represented as a block in the drawings. Note that the wiring BL shown in FIGS. 21A and 21B can be represented in the same manner even when replaced with wiring BLB.

[0248] 21C and 21D show a circuit diagram corresponding to the sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485. In addition to the wiring BL and the wiring BLB, the wirings SA_OUT and SA_OUTB for outputting read signals are also shown.

[0249] 21C, the switch circuit 482 includes, for example, n-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.

[0250] 21C, the precharge circuit 483 is formed of n-channel transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQ.

[0251] 21C, the precharge circuit 484 is formed of p-channel transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQB.

[0252] 21C , the amplifier circuit 485 includes p-channel transistors 485_1 and 485_2 and n-channel transistors 485_3 and 485_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN has a function of supplying VDD or VSS. The transistors 485_1 to 485_4 are transistors that form an inverter loop.

[0253] Moreover, Fig. 21D shows a circuit block diagram corresponding to the sense amplifier 446 described in Fig. 21C etc. As shown in Fig. 21D, the sense amplifier 446 may be represented as a block in the drawings etc.

[0254] Fig. 22 is a circuit diagram of the memory device 480 of Fig. 19. Fig. 22 illustrates the circuit blocks described in Fig. 21A to Fig. 21D.

[0255] 22, the layer 470 including the element layer 430[m] includes a memory cell 432. The memory cell 432 illustrated in FIG. 22 is connected to a pair of wirings BL[1] and BLB[1] or a pair of wirings BL[2] and BLB[2], for example. The memory cell 432 connected to the wiring BL is a memory cell to which data is written or read.

[0256] The wiring BL[1] and the wiring BLB[1] are connected to a sense amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to a sense amplifier 446[2]. The sense amplifier 446[1] and the sense amplifier 446[2] can read data in response to various signals described with reference to FIG.

[0257] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0258] Embodiment 3 In this embodiment, a structural example of a display device to which a transistor of one embodiment of the present invention can be applied will be described.

[0259] Since the transistor of one embodiment of the present invention can be made extremely small, a display device using the transistor of one embodiment of the present invention can have extremely high resolution. For example, the display device of one embodiment of the present invention can be used in a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, and a head-mounted display (HMD), such as a glasses-type AR device.

[0260] 23A shows a perspective view of display module 280. Display module 280 has a display device 200A and an FPC 290. Note that the display panel of display module 280 is not limited to display device 200A, and may be a display device 200B or a display device 200C, which will be described later.

[0261] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is an area for displaying an image.

[0262] 23B is a perspective view schematically illustrating the configuration on the substrate 291 side. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. A terminal portion 285 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are electrically connected by a wiring portion 286 composed of a plurality of wirings.

[0263] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of Fig. 23B. The pixel 284a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0264] The pixel circuit portion 283 has a plurality of pixel circuits 283a arranged periodically. Each pixel circuit 283a is a circuit that controls the light emission of three light-emitting devices included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0265] The circuit portion 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it is preferable that the circuit portion 282 includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be composed of a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.

[0266] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 282. An IC may be mounted on the FPC 290.

[0267] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are provided overlapping below the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 281 to be extremely high. For example, the aperture ratio of the display unit 281 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the resolution of the display unit 281 to be extremely high. For example, it is preferable that the pixels 284a be arranged in the display unit 281 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0268] Because such a display module 280 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 281, so even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0269] Display Device 200A The display device 200A shown in FIG. 24 includes a substrate 331, a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 240, and a transistor 320.

[0270] Substrate 331 corresponds to substrate 291 in FIG. 23A.

[0271] The transistor 320 is a vertical channel transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed, and includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a conductive layer 325, and a conductive layer 326.

[0272] Any of the various transistors exemplified in Embodiment 1 can be used as the transistor 320 .

[0273] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0274] A conductive layer 327 is provided over the insulating layer 332, and a conductive layer 325 is provided over the conductive layer 327. An insulating layer 334 is provided over the conductive layer 325, and a conductive layer 326 is provided over the insulating layer 334. Openings are provided in the insulating layer 334 and the conductive layer 326, and a semiconductor layer 321 is provided in the openings. An insulating layer 323 is provided to cover the semiconductor layer 321 and the conductive layer 326, and an insulating layer 264 is provided over the insulating layer 323, and the conductive layer 324 is provided in the opening in the insulating layer 264. An insulating layer 265 and a conductive layer 328 are provided over the insulating layer 264 and the conductive layer 324. An insulating layer 266 is provided over the insulating layer 265 and the conductive layer 328.

[0275] The insulating layers 264, 265, and 266 function as interlayer insulating layers. A barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 266 or the like to the transistor 320 may be provided between the insulating layer 266 and the insulating layer 265. An insulating film similar to the insulating layer 332 can be used as the barrier layer.

[0276] A plug 274 electrically connected to one side of the conductive layer 326 is provided to be embedded in the insulating layer 266, the insulating layer 265, and the insulating layer 264. Here, the plug 274 preferably has a conductive layer 274a covering the side surfaces of the openings of the insulating layer 266, the insulating layer 265, and the insulating layer 264 and part of the top surface of the conductive layer 326, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, the conductive layer 274a is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0277] Furthermore, a capacitor 240 is provided on the insulating layer 266. The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0278] The conductive layer 241 is provided over the insulating layer 266 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to the conductive layer 326 of the transistor 320 by a plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0279] An insulating layer 255a is provided to cover the capacitor 240, an insulating layer 255b is provided over the insulating layer 255a, and an insulating layer 255c is provided over the insulating layer 255b.

[0280] An inorganic insulating film can be preferably used for each of the insulating layers 255a, 255b, and 255c. For example, it is preferable to use a silicon oxide film for the insulating layer 255a and the insulating layer 255c, and a silicon nitride film for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 255c is etched to form a recess, but the insulating layer 255c does not necessarily have to have a recess.

[0281] The light-emitting elements 110R, 110G, and 110B are provided over the insulating layer 255c. Details of the light-emitting elements 110R, 110G, and 110B will be described in Embodiment 4.

[0282] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0283] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0284] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, resulting in minimal change in chromaticity between low-luminance and high-luminance emission. Furthermore, because the organic layers 112R, 112G, and 112B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This allows for the realization of a high-resolution, high-quality display panel.

[0285] In the region between adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0286] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 326 of the transistor 320 via a plug 256 embedded in the insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in the insulating layer 254, and a plug 274. The height of the top surface of the insulating layer 255c and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0287] A protective layer 121 is provided on the light emitting elements 110R, 110G, and 110B. A substrate 170 is attached to the protective layer 121 with an adhesive layer 171.

[0288] There is no insulating layer covering the upper end of each pixel electrode 111 between two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0289] [Display Device 200B] The following describes a display device that has a configuration that is partially different from that described above. Note that parts that are common to the above will be referred to, and descriptions thereof may be omitted.

[0290] 25 shows an example in which a transistor 320A, which is a planar transistor having a semiconductor layer formed on a plane, and a transistor 320B, which is a vertical channel transistor, are stacked. The transistor 320B has a similar configuration to the transistor 320 in the display device 200A.

[0291] The transistor 320A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0292] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352. The insulating layer 352 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0293] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as a first gate electrode of the transistor 320A, and part of the insulating layer 356 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that is in contact with the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0294] The semiconductor layer 351 is provided over the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided over and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0295] An insulating layer 358 and an insulating layer 350 are provided to cover top surfaces and side surfaces of the pair of conductive layers 355 and side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be formed using an insulating film similar to the insulating layer 352.

[0296] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with a top surface of the semiconductor layer 351 and a conductive layer 354 are buried in the opening. The conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.

[0297] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can be formed using an insulating film similar to the insulating layer 352.

[0298] The transistor 320 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0299] [Display Device 200C] A display device 200C shown in FIG. 26 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a vertical channel transistor 320.

[0300] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0301] An element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0302] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0303] In this embodiment, a structural example of a display device that can be used for a display device manufactured using a transistor of one embodiment of the present invention will be described. The display device exemplified below can be used for the pixel portion 284 in Embodiment 3, for example.

[0304] One embodiment of the present invention is a display device having a light-emitting element (also referred to as a light-emitting device). The display device has two or more pixels that emit light of different colors. Each pixel has a light-emitting element. Each light-emitting element has a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescent element). Two or more light-emitting elements that emit light of different colors each have an EL layer containing a different light-emitting material. For example, a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light, respectively.

[0305] When fabricating a display device having multiple light-emitting elements that emit different colors of light, it is necessary to form at least one layer containing a light-emitting material (light-emitting layer) in an island shape. When fabricating a partial or entire EL layer, a method of forming island-shaped organic films by vapor deposition using a shadow mask such as a metal mask is known. However, this method can cause deviations in the shape and position of the island-shaped organic films from the design due to various factors such as the accuracy of the metal mask, misalignment between the metal mask and the substrate, deflection of the metal mask, and spreading of the contours of the deposited film due to vapor scattering, making it difficult to achieve high-definition and high-aperture display devices. Furthermore, during vapor deposition, the contours of the layer can become blurred, resulting in thinning of the edges. In other words, the thickness of the island-shaped light-emitting layer can vary depending on the location. Furthermore, when fabricating large, high-resolution, or high-definition display devices, there is a concern that low dimensional accuracy of the metal mask and deformation due to heat, etc., can reduce manufacturing yield. Therefore, measures have been taken to artificially increase the resolution (also known as pixel density) by adopting special pixel arrangements such as a pentile array.

[0306] In this specification, the term "island-like" refers to a state in which two or more layers formed using the same material in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0307] In one embodiment of the present invention, an EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM). This makes it possible to realize a display device with high definition and a large aperture ratio, which have been difficult to achieve until now. Furthermore, since the EL layer can be individually fabricated, a display device with extremely vivid images, high contrast, and high display quality can be realized. For example, the EL layer may be processed into a fine pattern by using both a metal mask and photolithography.

[0308] Furthermore, the EL layer can be partially or entirely separated physically. This can suppress leakage current between adjacent light-emitting elements through a layer shared between the light-emitting elements (also referred to as a common layer). This can prevent unintended light emission due to crosstalk, thereby realizing a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.

[0309] One embodiment of the present invention can also be a display device that combines a white-emitting light-emitting element and a color filter. In this case, light-emitting elements provided in pixels (subpixels) that emit light of different colors can have the same configuration, and all layers can be common layers. Furthermore, part or all of each EL layer can be separated by photolithography. This suppresses leakage current through the common layer, thereby achieving a display device with high contrast. In particular, in an element having a tandem structure in which multiple light-emitting layers are stacked via a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, thereby achieving a display device that combines high brightness, high definition, and high contrast.

[0310] When the EL layer is processed by photolithography, a portion of the light-emitting layer may be exposed, which may cause deterioration. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. The insulating layer may also be configured to cover a portion of the top surface of the island-shaped EL layer. The insulating layer is preferably made of a material that has barrier properties against water and oxygen. For example, an inorganic insulating film that is less likely to diffuse water or oxygen can be used. This suppresses deterioration of the EL layer, thereby achieving a highly reliable display device.

[0311] Furthermore, there is a region (recess) between two adjacent light-emitting elements where the EL layer of either light-emitting element is not provided. When a common electrode, or a common electrode and a common layer, is formed to cover the recess, a phenomenon in which the common electrode is separated by a step at the edge of the EL layer (also called a step discontinuity) may occur, resulting in insulation of the common electrode on the EL layer. Therefore, it is preferable to use a configuration in which the local step located between two adjacent light-emitting elements is filled with a resin layer functioning as a planarization film (also called LFP: Local Filling Planarization). The resin layer functions as a planarization film. This suppresses step discontinuity of the common layer or common electrode, thereby achieving a highly reliable display device.

[0312] A more specific example of the structure of the display device of one embodiment of the present invention will be described below with reference to the drawings.

[0313] 27A shows a schematic top view of a display device 100 of one embodiment of the present invention. The display device 100 includes a plurality of light-emitting elements 110R that exhibit red light, a plurality of light-emitting elements 110G that exhibit green light, and a plurality of light-emitting elements 110B that exhibit blue light, over a substrate 101. In FIG. 27A , the symbols R, G, and B are assigned within the light-emitting regions of the light-emitting elements to easily distinguish them from one another.

[0314] The light emitting elements 110R, 110G, and 110B are arranged in a matrix. Fig. 27A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be used, or a pentile arrangement, a diamond arrangement, or the like may also be used.

[0315] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) is preferably used. Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material). As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0316] 27A also shows a connection electrode 111C that is electrically connected to the common electrode 113. The connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 113. The connection electrode 111C is provided outside the display area where the light-emitting elements 110R and the like are arranged.

[0317] The connection electrode 111C can be provided along the periphery of the display area. For example, it may be provided along one side of the periphery of the display area, or it may be provided over two or more sides of the periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be a strip shape (rectangle), an L-shape, a U-shape (square bracket shape), a square shape, or the like.

[0318] 27B and 27C are schematic cross-sectional views corresponding to dashed dotted lines A1-A2 and A3-A4 in Fig. 27A, respectively. Fig. 27B shows a schematic cross-sectional view of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, and Fig. 27C shows a schematic cross-sectional view of connection portion 140 where connection electrode 111C and common electrode 113 are connected.

[0319] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0320] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0321] Hereinafter, when describing matters common to light emitting element 110R, light emitting element 110G, and light emitting element 110B, they may be referred to as light emitting element 110. Similarly, when describing matters common to components distinguished by alphabets, such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the alphabets.

[0322] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 may have a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 may have an electron injection layer.

[0323] The pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are provided for each light-emitting element. The common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element. A conductive film transmissive to visible light is used for either the pixel electrode or the common electrode 113, and a conductive film reflective to visible light is used for the other. By making each pixel electrode transmissive and the common electrode 113 reflective, a bottom-emission display device can be obtained. Conversely, by making each pixel electrode reflective and the common electrode 113 transmissive, a top-emission display device can be obtained. Note that by making both the pixel electrodes and the common electrode 113 transmissive, a dual-emission display device can be obtained.

[0324] A protective layer 121 is provided on the common electrode 113 to cover the light emitting elements 110R, 110G, and 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above into each light emitting element.

[0325] The edge of the pixel electrode 111 preferably has a tapered shape. When the edge of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the edge of the pixel electrode 111 can also have a tapered shape. By tapering the edge of the pixel electrode 111, the coverage of the organic layer 112 provided over the edge of the pixel electrode 111 can be improved. Furthermore, by tapering the side surface of the pixel electrode 111, foreign matter (for example, also referred to as dust or particles) during the manufacturing process can be easily removed by a process such as cleaning, which is preferable.

[0326] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0327] The organic layer 112 is processed into an island shape by photolithography. As a result, the angle between the top surface and the side surface of the organic layer 112 at its edge is close to 90 degrees. On the other hand, an organic film formed using a fine metal mask (FMM) or the like tends to become gradually thinner as it approaches the edge. For example, the top surface is formed in a sloped shape over a range of 1 μm to 10 μm up to the edge, making it difficult to distinguish between the top surface and the side surface.

[0328] Between two adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0329] Between two adjacent light-emitting elements, the side surfaces of the organic layers 112 face each other with the resin layer 126 sandwiched therebetween. The resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the region between the two organic layers 112. The resin layer 126 has a smooth, convex upper surface, and a common layer 114 and a common electrode 113 are provided to cover the upper surface of the resin layer 126.

[0330] The resin layer 126 functions as a planarization film that fills in a step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent a phenomenon (also called step disconnection) in which the common electrode 113 is divided by a step at the end of the organic layer 112, resulting in insulation of the common electrode on the organic layer 112. The resin layer 126 can also be called an LFP (Local Filling Planarization) layer.

[0331] An insulating layer containing an organic material can be suitably used as the resin layer 126. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, precursors of these resins, etc. can be used as the resin layer 126. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the resin layer 126.

[0332] Furthermore, a photosensitive resin can be used as the resin layer 126. A photoresist can be used as the photosensitive resin. The photosensitive resin can be a positive-type material or a negative-type material.

[0333] The resin layer 126 may contain a material that absorbs visible light. For example, the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light. For example, the resin layer 126 may be a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.

[0334] The insulating layer 125 is provided in contact with the side surface of the organic layer 112. The insulating layer 125 is also provided to cover the upper end portion of the organic layer 112. A portion of the insulating layer 125 is provided in contact with the upper surface of the substrate 101.

[0335] The insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from contacting the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact with each other, the organic layer 112 may be dissolved by an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surfaces of the organic layer 112.

[0336] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, by using an inorganic insulating film such as a metal oxide film, an aluminum oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 125, an insulating layer 125 with few pinholes and excellent protection of the EL layer can be formed.

[0337] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0338] The insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. The insulating layer 125 is preferably formed by an ALD method because it has good coverage.

[0339] Furthermore, a reflective film (e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.) may be provided between the insulating layer 125 and the resin layer 126, so that the light emitted from the light-emitting layer is reflected by the reflective film, thereby improving the light extraction efficiency.

[0340] The layer 128 is a remaining portion of a protective layer (also referred to as a mask layer or a sacrificial layer) for protecting the organic layer 112 during etching of the organic layer 112. The layer 128 can be made of a material that can be used for the insulating layer 125. In particular, it is preferable to use the same material for the layer 128 and the insulating layer 125 because a common processing device or the like can be used for both.

[0341] In particular, inorganic insulating films such as metal oxide films such as aluminum oxide films and hafnium oxide films, or silicon oxide films formed by the ALD method have few pinholes and therefore have an excellent function of protecting the EL layer, and can be suitably used for the insulating layer 125 and the layer 128.

[0342] The protective layer 121 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 121 may be made of a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide.

[0343] The protective layer 121 may also be a laminated film of an inorganic insulating film and an organic insulating film. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 121 is flat, when a structure (e.g., a color filter, a touch sensor electrode, a lens array, etc.) is provided above the protective layer 121, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0344] 27C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C. The connection electrode 111C and the common electrode 113 are electrically connected in the opening.

[0345] 27C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected, but the common electrode 113 may be provided on the connection electrode 111C via the common layer 114. In particular, when a carrier injection layer is used for the common layer 114, the electrical resistivity of the material used for the common layer 114 is sufficiently low and the common layer 114 can be formed thin, so that there is often no problem even if the common layer 114 is located at the connection portion 140. This allows the common electrode 113 and the common layer 114 to be formed using the same masking mask, thereby reducing manufacturing costs.

[0346] [Configuration Example 2] The following describes a display device that has a configuration that is partially different from that of the above-described configuration example 1. Note that parts that are common to the above-described configuration example 1 will be referred to, and descriptions thereof may be omitted.

[0347] 28A shows a schematic cross-sectional view of a display device 100a. The display device 100a differs from the display device 100 in that the light-emitting element has a different configuration and that a colored layer is provided.

[0348] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may be configured to include two or more light-emitting materials whose emitted light colors are complementary to each other. For example, the organic layer 112W may be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. Alternatively, the organic layer 112W may be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0349] The organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, thereby suppressing crosstalk caused by the leakage current. As a result, a display device with high contrast and color reproducibility can be realized.

[0350] An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0351] An organic resin film or an inorganic insulating film with a planarized upper surface can be used as the insulating layer 122. The insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed, and therefore, by having a planar upper surface of the insulating layer 122, the thickness of the colored layers 116R and the like can be made uniform, thereby improving color purity. Note that if the thickness of the colored layers 116R and the like is uneven, the amount of light absorption varies depending on the location of the colored layer 116R, which may result in a decrease in color purity.

[0352] Configuration Example 3 FIG. 28B shows a schematic cross-sectional view of a display device 100b.

[0353] The light-emitting element 110R has a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layer 115R, the conductive layer 115G, and the conductive layer 115B each have light-transmitting properties and function as an optical adjustment layer.

[0354] A microresonator (microcavity) structure can be realized by using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113. In this case, by adjusting the thicknesses of the conductive layers 115R, 115G, and 115B so as to provide optimal optical path lengths, even when the organic layer 112 that emits white light is used, light of different wavelengths that are intensified can be obtained from the light-emitting elements 110R, 110G, and 110B.

[0355] Furthermore, colored layers 116R, 116G, and 116B are provided on the optical paths of the light emitting elements 110R, 110G, and 110B, respectively, so that light with high color purity can be obtained.

[0356] An insulating layer 123 is provided to cover the edges of the pixel electrode 111 and the conductive layer 115. The edges of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, coverage by the organic layer 112W, the common electrode 113, the protective layer 121, and the like formed thereon can be improved.

[0357] The organic layer 112W and the common electrode 113 are each provided as a continuous film in common to each light-emitting element, which is preferable because it can greatly simplify the manufacturing process of the display device.

[0358] Here, it is preferable that the edge of the pixel electrode 111 has a shape that is nearly vertical. This allows a steeply inclined portion to be formed on the surface of the insulating layer 123, and it is possible to form a thin portion in a part of the organic layer 112W that covers this portion, or to divide a part of the organic layer 112W. Therefore, it is possible to suppress leakage current that occurs through the organic layer 112W between adjacent light-emitting elements without processing the organic layer 112W by a photolithography method or the like.

[0359] The above is a description of an example of the configuration of the display device.

[0360] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0361] Embodiment 5 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0362] The electronic devices of this embodiment include a display panel (display device) in which the transistor of one embodiment of the present invention is used in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution and can also achieve high display quality. Therefore, the display device of one embodiment of the present invention can be used in the display portion of various electronic devices.

[0363] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0364] In particular, the display panel of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0365] The display panel of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display panel having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0366] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0367] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0368] 29A to 29D , examples of wearable devices that can be worn on the head are described. These wearable devices have one or both of a function for displaying AR content and a function for displaying VR content. Note that these wearable devices may also have a function for displaying SR or MR content in addition to AR and VR. By having an electronic device have a function for displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0369] The electronic device 700A shown in FIG. 29A and the electronic device 700B shown in FIG. 29B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0370] A display panel of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided.

[0371] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0372] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0373] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0374] Furthermore, the electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0375] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation or a slide operation by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can expand the range of operations.

[0376] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0377] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element). The active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0378] The electronic device 800A shown in Figure 29C and the electronic device 800B shown in Figure 29D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0379] A display panel of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided, which allows a user to feel a high sense of immersion.

[0380] The display unit 820 is provided inside the housing 821 at a position that can be viewed through the lens 832. In addition, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0381] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0382] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0383] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 29C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0384] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0385] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0386] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0387] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0388] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 29A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 29C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0389] The electronic device may also have an earphone unit. Electronic device 700B shown in Fig. 29B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0390] 29D includes an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the attachment unit 823. The earphone unit 827 and the attachment unit 823 may also have magnets. This allows the earphone unit 827 to be fixed to the attachment unit 823 by magnetic force, which is preferable as it makes storage easier.

[0391] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0392] As described above, as electronic devices of one embodiment of the present invention, both glasses-type devices (such as the electronic devices 700A and 700B) and goggle-type devices (such as the electronic devices 800A and 800B) are suitable.

[0393] The electronic device 6500 shown in FIG. 30A is a portable information terminal that can be used as a smartphone.

[0394] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. The display portion 6502 has a touch panel function. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0395] The display panel of one embodiment of the present invention can be applied to the display portion 6502 .

[0396] FIG. 30B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0397] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0398] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0399] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0400] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0401] 30C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0402] 30C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0403] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0404] 30D shows an example of a laptop personal computer. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like. A display portion 7000 is incorporated in the housing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.

[0405] 30E and 30F show an example of digital signage.

[0406] 30E includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0407] 30F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0408] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0409] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0410] 30E and 30F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0411] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0412] 30C to 30F, a display panel of one embodiment of the present invention can be applied to the display portion 7000.

[0413] The electronic device shown in Figures 31A to 31G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including the function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0414] The electronic devices shown in Figures 31A to 31G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0415] The electronic devices shown in Figures 31A to 31G will be described in detail below.

[0416] FIG. 31A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 31A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0417] 31B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while storing the mobile information terminal 9102 in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0418] 31C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0419] FIG. 31D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0420] 31E to 31G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 31E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 31G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 31F is a perspective view of a state in the process of changing from one of FIG. 31E and FIG. 31G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0421] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0422] Embodiment 6 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0423] An electronic component or the like to which the semiconductor device of one embodiment of the present invention is applied can be applied to the electronic devices exemplified in Embodiment 5.

[0424] [Electronic Component] FIG. 32A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 32A has a semiconductor device 710 inside a mold 711. FIG. 32A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0425] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0426] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0427] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0428] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0429] 32B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0430] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0431] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0432] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0433] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0434] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0435] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0436] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0437] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 32B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0438] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0439] 33A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0440] 33B shows a perspective view of an example of a computer 5620. The computer 5620 includes a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0441] Fig. 33C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 33C illustrates components other than electronic components 5626, 5627, and 5628.

[0442] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0443] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0444] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0445] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0446] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0447] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0448] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0449] Fig. 34A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 34A shows a planet 6804 in space as an example.

[0450] 34A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0451] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0452] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0453] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0454] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0455] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0456] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0457] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0458] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0459] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0460] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0461] Fig. 34B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 34B has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0462] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0463] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0464] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0465] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced.

[0466] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0467] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0468] 10a: transistor, 10b: transistor, 10c: transistor, 10d: transistor, 10e: transistor, 10f: transistor, 10g: transistor, 10h: transistor, 10i: transistor, 10j: transistor, 10k: transistor, 10: transistor, 11: insulating layer, 20a: opening, 20b: opening, 20c: opening, 20d: opening, 21i: channel formation region, 21n: low resistance region, 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 26: conductive layer, 27: insulating layer, 30: memory cell, 31: conductive layer, 32: conductive layer, 33: conductive layer, 34: conductive layer, 35: dummy layer, 41a : insulating layer, 41b: insulating layer, 41c: insulating layer, 41: insulating layer, 42: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 47: insulating layer, 48: insulating layer, 50: capacitor, 51: conductive layer, 52: conductive layer, 53: insulating layer, 60[1,1]: memory unit, 60[2,4]: memory unit, 60[a,b]: memory unit, 60: memory unit, 61: conductive layer, 62: conductive layer, 63: conductive layer, 65: insulating layer, 70[1]: layer, 70[2]: layer, 70[m]: layer, 70: layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region

Claims

1. A first insulating layer having a first opening is formed, A semiconductor layer is formed in contact with the side surface of the first insulating layer at the first opening. A third insulating layer is formed by covering the first insulating layer and the semiconductor layer. A dummy layer is formed on the third insulating layer at a position overlapping with the first opening. A second insulating layer is formed to cover the third insulating layer and the dummy layer. The upper part of the second insulating layer is etched to expose the upper surface of the dummy layer. The dummy layer is removed to form a second opening in the second insulating layer that overlaps with the first opening and reaches the third insulating layer. A conductive layer is formed in the second opening. Method for manufacturing semiconductor devices.

2. In claim 1, The removal of the dummy layer is performed using a wet etching method. Method for manufacturing semiconductor devices.

3. In claim 1 or claim 2, Furthermore, wiring in contact with the conductive layer is formed on the second insulating layer. Method for manufacturing semiconductor devices.