Nitride semiconductor light-emitting element

Abstract

The present invention improves the damage resistance of a nitride semiconductor light-emitting element when being externally connected. The nitride semiconductor light-emitting element comprises: a nitride semiconductor layered part having a light-emitting mesa structure section arranged on a first conductivity type semiconductor layer formed on a substrate, and a non-light-emitting protective mesa structure section that is arranged on a first conductivity type semiconductor layer, that is spatially separated from the light-emitting mesa structure section, and that surrounds the light-emitting mesa structure section; a first electrode that is arranged on another portion of the first conductivity type semiconductor layer, and has at least two electrode regions including a first electrode region disposed apart from the protective mesa structure section by a first distance, and a second electrode region disposed apart from the first electrode region by a second distance; a passivation layer that directly covers the edge of the protective mesa structure section, the outer edges of the plurality of electrode regions, and the surface of the first conductivity type semiconductor layer; and a first pad electrode that is arranged covering the surface of a portion of the passivation layer and the surface of at least a portion of each of the plurality of electrode regions not covered by the passivation layer.

Description

Nitride semiconductor light emitting device

[0001] The present disclosure relates to nitride semiconductor light emitting devices.

[0002] Conventionally, a nitride semiconductor device has, for example, an n-type nitride semiconductor layer, a nitride semiconductor light-emitting layer, and a p-type nitride semiconductor light-emitting layer stacked on a substrate, and is provided with an n-type electrode disposed on the n-type nitride semiconductor layer, a p-type electrode disposed on the p-type nitride semiconductor layer, and pad electrodes for external connection electrically connected to the n-type electrode and the p-type electrode, respectively (e.g., Patent Documents 1 and 2).

[0003] JP 2016-096193 A

[0004] In such nitride semiconductor devices, physical loads are applied to the device when the nitride semiconductor device is externally connected to a package substrate, wiring board, or the like, which may result in damage to the nitride semiconductor device. Even in the conventional nitride semiconductor devices described above, attempts have been made to suppress damage to the nitride semiconductor device by, for example, separately forming the external connection electrode, the contact electrode, and the lead-out wiring electrically connecting the external connection electrode and the contact electrode to increase the overall thickness of the electrodes in the external connection portion (Patent Document 1), or by spatially separating the n-type electrode directly below the external connection electrode to prevent corrosion of the n-type electrode from spreading (Patent Document 2). However, from the perspective of damage resistance, further improvements in suppressing damage to nitride semiconductor devices have been needed. An object of the present disclosure is to provide a nitride semiconductor device with improved damage resistance during external connection.

[0005] In order to solve the above-mentioned problems, a nitride semiconductor light-emitting element according to one aspect of the present disclosure includes: a substrate; a first conductivity type semiconductor layer disposed on the substrate; a light-emitting mesa structure disposed on a portion of the first conductivity type semiconductor layer; and a non-emitting protective mesa structure disposed on the first conductivity type semiconductor layer and spatially separated from the light-emitting mesa structure, surrounding the light-emitting mesa structure; a first electrode disposed on another portion of the first conductivity type semiconductor layer, the first electrode having at least two electrode regions: a first electrode region disposed a first distance apart from the protective mesa structure in a plan view; and a second electrode region disposed a second distance apart from the first electrode region; a passivation layer directly covering an edge of the protective mesa structure, an outer edge of each of the plurality of electrode regions, and a surface of the first conductivity type semiconductor layer; and a first pad electrode disposed so as to cover a portion of the surface of the passivation layer and at least a portion of the surface of each of the plurality of electrode regions that is not covered by the passivation layer, and electrically connecting the plurality of electrode regions to each other. It should be noted that the above summary of the invention does not list all of the features of the invention according to the present disclosure.

[0006] According to the present disclosure, it is possible to provide a nitride semiconductor device with improved resistance to damage that occurs when an external connection is made.

[0007] FIG. 1 is a schematic plan view showing a configuration example of a nitride semiconductor light-emitting device according to the first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view showing a configuration example of a nitride semiconductor light-emitting device according to the first embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view showing a configuration example of a nitride semiconductor light-emitting device according to the first embodiment of the present disclosure. FIG. 4 is a schematic plan view showing a configuration example of a nitride semiconductor light-emitting device according to the first embodiment of the present disclosure. FIG. 5 is an enlarged view showing an enlarged view of a portion of the configuration example of the nitride semiconductor light-emitting device according to the first embodiment of the present disclosure. FIG. 6 is a schematic plan view showing a configuration example of a nitride semiconductor light-emitting device according to a comparative example of the present disclosure. FIG. 7 is a schematic cross-sectional view showing a configuration example of a nitride semiconductor light-emitting device according to a comparative example of the present disclosure.

[0008] The nitride semiconductor light-emitting device according to the present disclosure will be described below through embodiments, but the following embodiments do not limit the scope of the claimed invention. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. Furthermore, the figures described below are schematic diagrams, and the ratios of size and thickness do not necessarily reflect the actual dimensional ratios. Furthermore, "up" and "down" in the following description do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationships of surfaces, layers, substrates, etc., and do not limit the technical concept of the present disclosure. For example, if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0009] A nitride semiconductor light emitting device according to an embodiment of the present disclosure will be described.

[0010] [Structure of Nitride Semiconductor Light-Emitting Device] A specific configuration example of the nitride semiconductor light-emitting device 1 will now be described with reference to Fig. 1 to Fig. 4. Figs. 1 to 4 are schematic diagrams for explaining the nitride semiconductor light-emitting device 1 according to this embodiment. Fig. 1 is a schematic plan view showing the planar structure of the nitride semiconductor light-emitting device 1. Fig. 2A is a schematic cross-sectional view showing the cross-sectional structure of the nitride semiconductor light-emitting device 1 shown in Fig. 1 taken along the line A-A, and Fig. 2B is a schematic cross-sectional view showing the cross-sectional structure of the nitride semiconductor light-emitting device 1 shown in Fig. 1 taken along the line B-B.

[0011] 1 and 2A to 2B , a nitride semiconductor light-emitting element 1 according to an embodiment of the present disclosure (hereinafter, this embodiment) includes a substrate 10, a nitride semiconductor stack 20 arranged on the substrate 10, a first electrode 30, a second electrode 40, a passivation layer 50, and a pad electrode 70. In Fig. 1 , an opening provided in the passivation layer 50 is indicated by a dashed line, and a region where the pad electrode 70 is formed is indicated by a dotted line. In Fig. 2B , an example of a position where a conductive bump is provided when the nitride semiconductor light-emitting element 1 is connected to an external device is indicated by a dotted line.

[0012] 1 and 2A , the nitride semiconductor stack 20 includes a first n-type semiconductor layer (an example of a first conductivity type semiconductor layer) 21, a light emitting mesa structure 22 disposed in a portion of the first n-type semiconductor layer 21, and a protective mesa structure 23 disposed on the first n-type semiconductor layer 21 and spatially separated from the light emitting mesa structure 22. The light emitting mesa structure 22 includes a light emitting layer. The protective mesa structure 23 has the function of protecting the region inside the protective mesa structure 23, including the light emitting mesa structure 22. The protective mesa structure 23 is preferably disposed on the outer edge of the substrate.

[0013] The first electrode 30 is disposed on another portion of the first n-type semiconductor layer 21 (a region where the light emitting mesa structure 22 is not provided). As shown in FIGS. 2A and 2B , the first electrode 30 has a first electrode region 31 that serves as a base for an external connection portion and a second electrode region 32 that is spatially separated from the first electrode region 31. The first electrode region 31 is disposed between the protective mesa structure 23 and the first narrow space 61. The second electrode region 32 is disposed between the first electrode region 31 and the protective mesa structure 23 and the second narrow space 62. That is, the first narrow space 61 is formed by the spatial arrangement of the protective mesa structure 23 and the first electrode region 31, and the second narrow space 62 is formed by the spatial arrangement of the first electrode region 31 and the second electrode region 32. Hereinafter, when there is no need to distinguish between the first narrow space 61 and the second narrow space 62, they may be referred to as narrow space 60. The first electrode 30 also has a third electrode region 33 disposed between the light emitting mesa structures 22. A portion of the third electrode region 33 is disposed in a position facing the second electrode region 32 across the light emitting mesa structure 22. The second electrode 40 is disposed on the light emitting mesa structure 22.

[0014] The pad electrode 70 has a first pad electrode portion 71 and a second pad electrode portion 72. The first pad electrode portion 71 is arranged to cover a portion of the surface of the passivation layer 50 and the surface of the first electrode 30 (the first electrode region 31, the second electrode region 32, and the third electrode region 33) that is not covered by the passivation layer 50. Specifically, the first pad electrode portion 71 is provided to cover a portion of the second passivation covered region 52 and a portion of the third passivation covered region 53 (details will be described later). The first pad electrode portion 71 also electrically connects the first electrode region 31, the second electrode region 32, and the third electrode region 33. The second pad electrode portion 72 is arranged on a portion of the passivation layer 50 and on the surface of the second electrode 40 that is not covered by the passivation layer 50. More preferably, the pad electrode 70 includes a third pad electrode portion 73 covering a portion of the surface of the passivation layer 50 and a portion of the protective mesa structure 23 that is not covered by the passivation layer 50. Specifically, the third pad electrode portion 73 is provided so as to cover at least a portion of the first passivation covered region 51.

[0015] The narrow space 60 has a first narrow space 61 formed by the spatial arrangement of the protective mesa structure 23 and the first electrode region 31, and a second narrow space 62 formed by the spatial arrangement of the first electrode region 31 and the second electrode region 32. The passivation layer 50 is disposed on the entire surface except for the outer periphery of the protective mesa structure 23 (the outer periphery of the nitride semiconductor light-emitting element 1) and the central portion of the first electrode 30 (the first electrode region 31, the second electrode region 32, and the third electrode region 33) and the second electrode 40, and is formed across the first narrow space 61 and the second narrow space 62. The passivation layer 50 has a first passivation coating region 51 that covers the outer edge of the protective mesa structure 23 on the first electrode region 31 side, a second passivation coating region 52 that covers the outer edge of the first electrode region 31, and a third passivation coating region 53 that covers the outer edge of the second electrode region 32. That is, the first passivation coating region 51 covers the edge and side of the upper surface of the protective mesa structure 23, the second passivation coating region 52 covers the edge and side of the upper surface of the first electrode region 31, and the third passivation coating region 53 covers the edge and side of the upper surface of the second electrode region 32.

[0016] The nitride semiconductor light-emitting element 1 according to this embodiment, having the above-described configuration, achieves improved resistance to damage during external connection. Damage during external connection refers to, for example, peeling or cracking of the pad electrode 70 or the first electrode 30 from the underlying layer in the region where the conductive bump is provided, or peeling or cracking (including microcracks) of the passivation layer 50. Damage to the nitride semiconductor light-emitting element 1 can cause deterioration of the nitride semiconductor light-emitting element 1 during power-on, particularly in high-humidity environments. Deterioration of the nitride semiconductor light-emitting element 1 during power-on mainly refers to an increase in drive voltage or disconnection due to corrosion of the electrodes or the semiconductor layer. In the case of AlGaN-based nitride semiconductor light-emitting elements, the higher the Al content, the more likely corrosion of the semiconductor layer occurs. Furthermore, peeling of the pad electrode 70 or the first electrode 30 increases the risk of the nitride semiconductor light-emitting element 1 becoming detached from an externally connected package substrate, wiring board, or the like (not shown).

[0017] In the nitride semiconductor light-emitting element 1, the passivation layer 50 formed across the narrow space portion 60 improves the adhesion of the passivation layer 50 due to the anchor effect, thereby strengthening the effect of suppressing the first electrode region 31 and improving the adhesion to the layer below the first electrode region 31 (first n-type semiconductor layer 21). Therefore, the nitride semiconductor light-emitting element 1 including the passivation covering region and the narrow space portion 60 does not experience peeling of the pad electrode 70 or the first electrode 30 when connected to an external device, and has significantly superior damage resistance.

[0018] The first pad electrode 71 of this embodiment also functions as an extraction electrode that electrically connects the first electrode region 31 and the second electrode region 32. The first pad electrode 71 also functions as an extraction electrode that electrically connects the first electrode region 31 and the second electrode region 32 to the third electrode region 33. This eliminates the need for a process for separately forming the external connection portion and the extraction electrode, which is preferable in terms of simplifying the manufacturing process. Furthermore, the narrow space 60 can be formed by the spatial arrangement of the protective mesa structure 23 and the first electrode region 31, and the spatial arrangement of the first electrode region 31 and the second electrode region 32. This is also preferable in terms of obtaining a nitride semiconductor light-emitting element 1 with high damage resistance without changing the manufacturing process.

[0019] Furthermore, because the present embodiment can improve damage resistance, it is not necessary to design the nitride semiconductor light-emitting element 1 with a large margin for the size and positional misalignment of external connectors. This allows the area within the nitride semiconductor light-emitting element 1 that does not contribute to light emission to be reduced, which is preferable in that it increases the light output per unit area of ​​the chip. Furthermore, the second narrow space 62 has the effect of preventing corrosion from spreading to the second electrode region 32, even if the first electrode region 31 corrodes during current application in a high-humidity environment. In this case, corrosion does not spread to the second electrode region 32, and carrier supply to the light-emitting mesa structure 22 is not impeded, preventing degradation of device performance, such as an increase in drive voltage, disconnection, or degradation of light-emitting performance, during current application. Therefore, a nitride semiconductor light-emitting element 1 having the second narrow space 62 may be preferable in that it further suppresses degradation of device performance during current application in a high-humidity environment. Next, each component of the nitride semiconductor light-emitting element 1 according to this embodiment will be described in detail.

[0020] <Substrate> The substrate 10 is not particularly limited as long as it allows the first n-type semiconductor layer 21 to be formed thereon. Specific examples of the substrate 10 include sapphire, Si, SiC, MgO, Ga2O3, ZnO, GaN, InN, AlN, and alloy substrates thereof. From the viewpoints of reducing threading dislocations by growing the substrate 10 in a lattice-matched system, which has a small difference in lattice constant with the first n-type semiconductor layer 21 formed thereon, and increasing the lattice strain required for hole gas generation, the substrate 10 is preferably a single-crystal substrate made of a bulk nitride semiconductor such as GaN, AlN, or AlGaN, or a nitride semiconductor layer (also referred to as a template) of GaN, AlN, AlGaN, or the like grown on a certain material. Impurities may be incorporated into the substrate 10. To improve light extraction, the surface of the substrate 10 opposite the surface on which the first n-type semiconductor layer 21 is formed may be processed.

[0021] <Nitride Semiconductor Stack> The nitride semiconductor stack 20 includes a first n-type semiconductor layer 21, a light emitting mesa structure 22 disposed on the first n-type semiconductor layer 21, and a protective mesa structure 23. The light emitting mesa structure 22 and the protective mesa structure 23 have mesa structures that protrude from a portion of the first n-type semiconductor layer 21. There are no particular limitations on the method for forming the mesa structure, but it can be formed by stacking each layer on the substrate 10 using a known film formation apparatus that employs a technique such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD), forming a mask pattern by photolithography, and etching desired regions by dry etching or wet etching.

[0022] The light emitting mesa structure 22 and the protective mesa structure 23 are spatially separated. Here, "spatially separated" means that the side surfaces of the light emitting mesa structure 22 and the protective mesa structure 23 exist but do not contact each other. In order to achieve a nitride semiconductor light emitting device 1 with a longer lifetime, it is preferable that the protective mesa structure 23 is disposed so as to surround the light emitting mesa structure 22 in a planar view. Here, "disposed so as to surround" means that 50% or more of the sides of the smallest convex polygon that surrounds the entire light emitting mesa structure 22 face the side surfaces of the protective mesa structure 23 in a planar view.

[0023] The light emitting mesa structure 22 has a second n-type semiconductor layer (an example of a first conductivity type semiconductor layer) 221, a first quantum well layer 222 disposed on the second n-type semiconductor layer, and a first p-type semiconductor layer 223 disposed on the first quantum well layer 222. The protection mesa structure 23 has a third n-type semiconductor layer 231, a second quantum well layer 232 disposed on the third n-type semiconductor layer, and a second p-type semiconductor layer 233 disposed on the second quantum well layer 232.

[0024] In a plan view, it is preferable that a portion of the edge of the protective mesa structure 23 overlaps a portion of the edge of the substrate 10, i.e., that the side surface of the protective mesa structure 23 is disposed substantially flush with the side surface of the substrate 10. This allows the protective mesa structure 23 to cover the first n-type semiconductor layer 21 up to the chip periphery, thereby protecting a wide area on the first n-type semiconductor layer 21. For example, when the first n-type semiconductor layer 21 has a high Al composition ratio, the first n-type semiconductor layer 21 tends to deteriorate easily. However, by providing the protective mesa structure 23 on the first n-type semiconductor layer 21, the exposed area of ​​the first n-type semiconductor layer 21 can be reduced. This suppresses deterioration of the first n-type semiconductor layer 21 and realizes a nitride semiconductor light-emitting element 1 with a longer life. Note that "overlap" means that a deviation between a portion of the edge of the protective mesa structure 23 and the edge of the substrate 10 is 2 μm or less in a plan view.

[0025] <n-Type Semiconductor Layer> The n-type semiconductor layer (an example of a first conductivity type semiconductor layer) includes a first n-type semiconductor layer 21, a second n-type semiconductor layer 221 that is part of the light emitting mesa structure 22, and a third n-type semiconductor layer 231 that is part of the protective mesa structure 23. As shown in FIG. 2A and other figures, the first n-type semiconductor layer 21 is formed directly on the substrate 10. Alternatively, a layer other than the first n-type semiconductor layer 21 may be provided on the substrate 10, and the first n-type semiconductor layer 21 may be provided on the layer other than the first n-type semiconductor layer 21. Specifically, for example, a buffer layer (not shown) may be provided on the substrate 10, and the first n-type semiconductor layer 21 may be provided on the buffer layer.

[0026] The first n-type semiconductor layer 21, the second n-type semiconductor layer 221, and the third n-type semiconductor layer 231 are made of Al ｘ Ga １－ｘ It is preferably made of N (x>0.3), and n-type Al ｘ Ga １－ｘIt is more preferable that the nitride semiconductor light emitting element 1 is formed of N (x>0.3), which improves the light emitting efficiency of the nitride semiconductor light emitting element 1. In addition to the n-type dopant, the first n-type semiconductor layer 21, the second n-type semiconductor layer 221, and the third n-type semiconductor layer 231 may contain other Group V elements such as P, As, and Sb, or impurities such as C, H, F, O, Mg, and Si.

[0027] <Quantum Well Layer> The quantum well layer includes a first quantum well layer 222 that is part of the light-emitting mesa structure 22 and a second quantum well layer 232 that is part of the protective mesa structure 23. As shown in FIG. 2A , the first quantum well layer 222 is provided directly on the second n-type semiconductor layer 221, and the second quantum well layer 232 is provided directly on the third n-type semiconductor layer 231. Alternatively, the first quantum well layer 222 may be provided on a layer other than the quantum well layer provided on the second n-type semiconductor layer 221. Specifically, an undoped AlGaN layer (not shown) may be provided on the second n-type semiconductor layer 221, and the first quantum well layer 222 may be provided on the AlGaN layer. Similarly, the second quantum well layer 232 may be provided on an undoped AlGaN layer or the like that is formed on the third n-type semiconductor layer 231.

[0028] The first quantum well layer 222 and the second quantum well layer 232 are not particularly limited as long as they are nitride semiconductor layers, but are preferably mixed crystals of AlN, GaN, or InN from the viewpoint of achieving high light emission efficiency. The first quantum well layer 222 and the second quantum well layer 232 may contain, in addition to N, other Group V elements such as P, As, and Sb, or impurities such as C, H, F, O, Mg, and Si. The first quantum well layer 222 and the second quantum well layer 232 may have either a multiple quantum well structure or a single quantum well structure, but are preferably formed of at least two wells from the viewpoint of achieving high light emission efficiency.

[0029] <P-Type Semiconductor Layer> The p-type semiconductor layer includes a first p-type semiconductor layer 223 that is part of the light-emitting mesa structure 22 and a second p-type semiconductor layer 233 that is part of the protective mesa structure 23. The p-type semiconductor layer corresponds to a second conductivity type semiconductor layer. As shown in FIG. 2A , the first p-type semiconductor layer 223 is formed directly on the first quantum well layer 222, and the second p-type semiconductor layer 233 is formed directly on the second quantum well layer 232. The first p-type semiconductor layer 223 may also be formed on a layer other than the p-type semiconductor layer provided on the third n-type semiconductor layer 231. Specifically, a graded composition layer (not shown) in which the ratio of constituent elements changes continuously or discretely may be provided on the first quantum well layer 222, and the first p-type semiconductor layer 223 may be provided on the graded composition layer. Similarly, the second p-type semiconductor layer 233 may be provided on a compositionally graded layer or the like provided on the second quantum well layer 232. A barrier layer with a relatively large band gap may be further provided between the graded composition layer and the first p-type semiconductor layer 223 or the second p-type semiconductor layer 233.

[0030] It is preferable that the uppermost surface of the first p-type semiconductor layer 223 and the second p-type semiconductor layer 233 contain a large amount of Al element, because this allows light with wavelengths in the deep ultraviolet region to be easily transmitted and achieves high light emission efficiency. However, if the amount is too large, chemical reactions with oxygen and water vapor in the air are likely to be promoted, which makes deterioration more likely to occur. Therefore, in order to realize the nitride semiconductor light-emitting element 1, the first p-type semiconductor layer 223 and the second p-type semiconductor layer 233 should contain a large amount of Al element. ｙ Ga １－ｙIt is preferable that the p-type semiconductor layer is formed of N (0≦y≦0.6). From the viewpoint of efficiently generating two-dimensional hole gas in the compositionally graded layer and the p-type semiconductor layer, it is preferable to strain the p-type semiconductor layer, i.e., to reduce the relaxation rate. To reduce the relaxation rate of the p-type semiconductor layer, the thickness of the p-type semiconductor layer is preferably 1 nm to 10 nm, more preferably 4 nm to 8 nm. An electrode may be in direct contact with the upper layer of the p-type semiconductor layer, or an electrode may be in contact with the top surface of a multi-layered p-type semiconductor layer. The p-type semiconductor layer may contain a p-type dopant from the viewpoint of generating holes within the thin film, or may not contain a dopant in order to inject holes directly from the electrode into the two-dimensional hole gas at the interface. Mg is commonly used as the p-type dopant, but impurities that generate holes, such as Be and Zn, can also be used. The composition difference between the p-type semiconductor layer and the outermost surface of the gradient composition layer can be confirmed by various analytical techniques such as XRD (X-ray diffraction), EDX (energy dispersive X-ray spectroscopy), XRF (X-ray fluorescence analysis), AES (Auger electron spectroscopy), SIMS (secondary ion mass spectroscopy), and EELS (electron energy loss spectroscopy).

[0031] <First Electrode> The first electrode 30 has a first electrode region 31 formed on the upper surface of the first n-type semiconductor layer 21 and serving as a base for the external connection portion, and a second electrode region 32 formed on the upper surface of the first n-type semiconductor layer 21 and spatially separated from the first electrode region 31. The first electrode 30 also has a third electrode region 33 disposed on the first n-type semiconductor layer 21 and facing the second electrode region 32 across the light emitting mesa structure 22. Here, "spatially separated" means that side surfaces of the first electrode region 31 and the second electrode region 32 exist but are not in contact with each other. The first electrode region 31 is provided to improve the adhesion of the base for the external connection portion, and the second electrode region 32 and third electrode region 33 are provided to supply electrons to the light emitting mesa structure 22. Furthermore, from the viewpoint of reliability, for example, preventing detachment of the external connection portion, it is preferable to have a large number of first electrode regions 31, but if there are too many, the area ratio of the light emitting mesa structure 22 decreases, which is undesirable because it reduces the relative light emission output per unit area. Therefore, by forming the first electrode regions 31 preferably in two or more corners of the substrate 10, and more preferably in four corners of the substrate 10, the reliability of the external connection portion can be improved and adhesion can be efficiently improved without reducing the area ratio of the light emitting mesa structure 22.

[0032] The first electrode 30 is formed using a material that has effects such as improving electrode adhesion and preventing oxidation of the electrode material, and that reduces contact resistance with the first n-type semiconductor layer 21. Examples of such materials include metals such as Ti, Al, Ni, Mo, V, Au, W, Pt, Pd, Si, Zr, Cr, Hf, Nb, Ta, Co, Rh, Ir, Cu, and Ag, alloys containing these metals, and conductive oxides such as ITO and Ga2O3. Materials containing titanium, aluminum, nickel, and gold are more preferred, but are not limited to these materials. When the first electrode 30 is made of titanium, aluminum, nickel, or gold, it is preferable to have both an alloy layer containing aluminum and nickel and an aluminum-containing layer other than the alloy layer formed on or near the contact surface with the first n-type semiconductor layer 21. Here, the vicinity of the contact surface refers to a portion of the first electrode 30 that is close to the first n-type semiconductor layer 21 but that is not in contact with the first n-type semiconductor layer 21, and refers to, for example, a region between the contact surface and a position 3 nm away from the contact surface within the layer of the first electrode 30. In order to reduce the resistance at the interface with the first n-type semiconductor layer 21, at least a portion of the above-mentioned contact surface of the first electrode 30 may contain, for example, Ti, Mo, V, Au, W, Pt, Pd, Si, Zr, or the like. More preferably, Ti or Au is contained, and even more preferably Ti is contained.

[0033] The first electrode 30 may also have the above-described aluminum-nickel alloy layer and aluminum-containing layer separated into multiple regions. In this case, the total abundance ratio of the aluminum-nickel alloy layer and the aluminum-containing layer in the first electrode 30 is preferably 60% or more, more preferably 70% or more. However, this configuration is not limited to these. Such a first electrode 30 can be obtained by forming a metal laminate on the first n-type semiconductor layer 21 by, for example, sputtering or vapor deposition, and then subjecting the metal laminate to a heat treatment such as RTA (Rapid Thermal Annealing). The first electrode region 31, second electrode region 32, and third electrode region 33 of the first electrode 30 can be simultaneously formed by a single lithography, film formation, and heat treatment process, which is preferable from the viewpoint of simplifying the manufacturing process.

[0034] <Second Electrode> The second electrode 40 is provided to supply holes to the nitride semiconductor light-emitting element 1. The second electrode 40 is formed on the upper surface of the first p-type semiconductor layer 223 of the light-emitting mesa structure 22. The second electrode 40 may be formed of any conductive material. Examples of such materials include Ni, Al, Ti, Au, Pt, Ag, Rh, Pd, Pt, Cu, and alloys thereof, or ITO. Ni, Au, or an alloy layer thereof, which has low contact resistance with the nitride semiconductor layer, is more preferably used. Such an electrode can be obtained by forming a metal stack by, for example, sputtering or vapor deposition, and then performing a heat treatment using, for example, rapid thermal annealing (RTA).

[0035] Each electrode may also include a UV (ultraviolet) reflector, which is a structure designed to redirect emitted photons toward the electrode, preventing them from escaping the semiconductor layer structure, and is designed to improve the extraction efficiency of photons generated in the active region of the device by redirecting them toward a desired light-emitting surface, such as the bottom surface.

[0036] <Arrangement of Protective Mesa Structure and First and Second Electrode Regions> The narrow spaces 60 formed between the protective mesa structure 23 and the first electrode region 31, and between the first electrode region 31 and the second electrode region 32, will be described with reference to Figures 3 and 4. Figure 3 is a plan view schematically illustrating an example of the overall configuration of the nitride semiconductor light-emitting element 1, and illustrates the light-emitting mesa structure 22 and the protective mesa structure 23, the first electrode 30 (the first electrode region 31, the second electrode region 32, and the third electrode region 33), and the first n-type semiconductor layer 21. Figure 4 is an enlarged view of the region indicated by the dashed line in Figure 3.

[0037] Before the passivation layer 50 is formed, a narrow space 60 having a predetermined distance is formed between the protective mesa structure 23 and the first electrode region 31. The narrow space 60 has a first narrow space 61 formed by the spatial arrangement of the protective mesa structure 23 and the first electrode region 31 with a first distance W1 between them before the passivation layer 50 is formed. The narrow space 60 also has a second narrow space 62 formed by the spatial arrangement of the first electrode region 31 and the second electrode region 32 with a second distance W2 between them. The protective mesa structure 23 is preferably disposed on the outer edge of the substrate 10. Therefore, the first electrode region 31 is preferably provided at two or more corners, more preferably four corners, of the substrate 10 in a plan view, and is preferably disposed with the first distance W1 between it and the protective mesa structure 23. 4, the light emitting mesa structure 22 and the protective mesa structure 23 are disposed in an area other than the first narrow space 61 and the second narrow space 62. The passivation layer 50 is formed across the first narrow space 61 and the second narrow space 62 (details will be described later), and this improves the adhesion of the passivation layer 50 around the first electrode region 31 due to the anchor effect.

[0038] The first narrow space 61 is formed by a region surrounded by the side surfaces of the protective mesa structure 23 and the side surfaces of the first electrode region 31. As shown in Fig. 4, the first narrow space 61 is preferably formed so as to surround at least two sides of each first electrode region 31, and it is preferable that there are the same number of first narrow spaces 61 as the number of first electrode regions 31. Furthermore, it is preferable that the first narrow spaces 61 are formed in two or more corners of the nitride semiconductor light-emitting device 1, more preferably in four corners. However, the present invention is not limited to these configurations.

[0039] The first interval W1 (see FIG. 4 ), which is the width of the first narrow space 61, is determined by the distance between the protective mesa structure 23 and the first electrode region 31. If the first interval W1 is too narrow, the passivation layer 50 may not be sufficiently covered, or the first narrow space 61 may not be formed due to misalignment during the manufacturing process. Furthermore, if the first interval W1 is too wide, the ratio of the chip area to the area of ​​the light-emitting portion increases, increasing the area that does not contribute to light emission. Therefore, the first interval W1 is preferably 0.5 μm or more and 25 μm or less, more preferably 1 μm or more and 20 μm or less.

[0040] The second narrow space 62 is formed by a region surrounded by the side surfaces of the first electrode region 31 and the second electrode region 32. As shown in Fig. 4, the second narrow space 62 is preferably formed between each first electrode region 31 and the second electrode region 32 that is closest to it, and it is preferable that the number of second narrow spaces 62 is the same as the number of first electrode regions 31. However, the present invention is not limited to this configuration.

[0041] The second interval W2 (see FIG. 4 ), which is the width of the second narrow space 62, is determined by the distance between the first electrode region 31 and the second electrode region 32. If the second interval W2 is too narrow, the passivation layer 50 cannot sufficiently cover the second narrow space 62. If the second interval W2 is too wide, the light emission distribution of the light emitting mesa structure 22 becomes unbalanced. Therefore, the second interval W2 is preferably 0.5 μm or more and 140 μm or less, and more preferably 1 μm or more and 120 μm or less.

[0042] The first electrode region 31 is more susceptible to damage and corrosion in a high-humidity environment than the second electrode region 32 because it is subjected to a direct physical load when connected to an external device. However, by forming the first electrode region 31 and the second electrode region 32 with the second distance W2 therebetween, it is possible to prevent corrosion from spreading from the first electrode region 31 to the second electrode region 32 during current application in a high-humidity environment. Because it is the second electrode region 32 and the third electrode region 33 that supply electrons (carriers) to the light-emitting mesa structure 22, preventing corrosion from spreading to the second electrode region 32 can prevent an increase in drive voltage and disconnection in the nitride semiconductor light-emitting device 1 during current application in a high-humidity environment.

[0043] <Passivation Layer> The passivation layer 50 has a first passivation coating region 51 that covers an edge portion (the outer edge portion of the protective mesa structure 23 on the first electrode region 31 side) that is a part of the upper surface of the protective mesa structure 23, a second passivation coating region 52 that covers the outer edge portion of the first electrode region 31, and a third passivation coating region 53 that covers the outer edge portion of the second electrode region 32. In other words, the passivation layer 50 is disposed on the entire surface except for the outer periphery of the protective mesa structure 23 (the outer periphery of the nitride semiconductor light-emitting element 1) and the central portion of the first electrode 30 (the first electrode region 31, the second electrode region 32, and the third electrode region 33) and the second electrode 40, and is formed across the first narrow space portion 61 and the second narrow space portion 62. Covering the protective mesa structure 23 with the first passivation coating region 51 improves the adhesion of the passivation layer 50 to the protective mesa structure 23, thereby reducing the area of ​​the first n-type semiconductor layer 21 that comes into contact with air and water vapor. Furthermore, the larger the area that the first passivation coating region 51 covers the protective mesa structure 23, the more the adhesion of the passivation layer 50 to the protective mesa structure 23 improves. Therefore, covering the protective mesa structure 23 with the first passivation coating region 51 can achieve a nitride semiconductor light-emitting element 1 with a longer lifetime. On the other hand, if the first passivation coating region 51 covers the entire protective mesa structure 23, cracks may occur in the passivation layer 50 when the nitride semiconductor light-emitting elements 1 on the wafer are separated into individual pieces. Therefore, as described above, it is preferable that the passivation layer 50 be disposed so as to cover the outer edge of the protective mesa structure 23 on the first electrode region side.

[0044] The passivation layer 50 has a second passivation coating region 52 that covers the outer edge of the first electrode region 31. In other words, the edge of the first electrode region 31 is held down by the second passivation coating region 52, which allows the first electrode region 31 to achieve high adhesion to the first n-type semiconductor layer 21. If the area covered by the second passivation coating region 52 over the first electrode region 31 is wider, the force with which the second passivation coating region 52 holds down the first electrode region 31 becomes stronger. However, if the area over which the first electrode region 31 is covered is too wide, the opening over the first electrode region 31 becomes too small, which is not preferable. It is possible to widen the second passivation coating region 52 while maintaining the size of the opening by changing the size of the first electrode region 31. However, if the second passivation coating region 52 is too wide, the overall area of ​​the chip increases, which is not preferable as it reduces the light output per unit area of ​​the chip. Furthermore, if the area where the second passivation coating region 52 covers the first electrode region 31 is too narrow, it is not preferable because alignment during manufacturing will prevent the edge of the first electrode region 31 from being covered. For this reason, the width where the passivation layer 50 covers the edge of the upper surface of the first electrode region 31, i.e., the width of the area where the upper surface of the first electrode region 31 is covered by the second passivation coating region 52 (hereinafter, may be referred to as the width of the second passivation coating region 52), is preferably 0.5 μm or more and 15 μm or less, and more preferably 1 μm or more and 10 μm or less.

[0045] The passivation layer 50 has a third passivation coating region 53 that covers the outer edge of the second electrode region 32. In other words, the edge of the second electrode region 32 is held down by the third passivation coating region 53, which allows the second electrode region 32 to achieve high adhesion to the first n-type semiconductor layer 21. As the area covered by the third passivation coating region 53 of the second electrode region 32 becomes wider, the force with which the third passivation coating region 53 holds down the second electrode region 32 becomes stronger. However, if the area covered by the second electrode region 32 is too wide, the opening on the second electrode region 32 becomes too small, which is not preferable. By changing the size of the second electrode region, the third passivation coating region can be widened while maintaining the size of the opening. However, if the third passivation coating region is too wide, the overall area of ​​the chip increases, which is not preferable as it reduces the light-emitting output per unit area of ​​the chip. Furthermore, if the area where the third passivation coating region 53 covers the second electrode region 32 is too narrow, it is not preferable because alignment during manufacturing will make it impossible to cover the edge of the second electrode region 32. For this reason, the width where the passivation layer 50 covers the edge of the upper surface of the second electrode region 32, i.e., the width of the area where the upper surface of the second electrode region 32 is covered by the third passivation coating region 53 (hereinafter, sometimes referred to as the width of the third passivation coating region 53), is preferably 0.5 μm or more and 15 μm or less, and more preferably 1 μm or more and 10 μm or less.

[0046] The passivation layer 50 is formed, in a plan view, so as to overlap a first narrow space 61 of the first n-type semiconductor layer 21, which is located between the protective mesa structure 23 and the first electrode region 31. This allows the anchor effect to improve the adhesion of the passivation layer 50. In this case, the effect of the first passivation coating region 51 adhering to the protective mesa structure 23 and the effect of the second passivation coating region 52 suppressing the first electrode region 31 are particularly enhanced. Furthermore, the passivation layer 50 is formed, in a plan view, so as to overlap a second narrow space 62 of the first n-type semiconductor layer 21, which is located between the first electrode region 31 and the second electrode region 32. This allows the anchor effect to improve the adhesion of the passivation layer 50. In this case, the effect of the second passivation coating region 52 suppressing the first electrode region 31 and the effect of the third passivation coating region 53 suppressing the second electrode region 32 are particularly enhanced. Therefore, by forming the passivation layer 50 so as to straddle the first narrow space portion 61 and the second narrow space portion 62, it is possible to suppress peeling and cracks (including microcracks) in the passivation layer 50 even if a physical load is applied when connecting the nitride semiconductor light-emitting element 1 to an external device. Furthermore, the adhesion of the passivation layer 50 to the protective mesa structure 23 is improved, making it difficult for the first n-type semiconductor layer 21 to come into contact with air and water vapor, thereby extending the life of the nitride semiconductor light-emitting element 1.

[0047] In such a nitride semiconductor light-emitting element 1, the first electrode region 31 and the passivation layer 50 are more resistant to damage when the nitride semiconductor light-emitting element 1 is connected to an external device. Therefore, it is no longer necessary to set the area of ​​the first electrode region 31 and the opening provided on the first electrode region 31 with a large margin relative to the size of the conductive wire or conductive bump used for external connection. This eliminates the need to unnecessarily increase the area of ​​the first electrode region 31 in the nitride semiconductor light-emitting element 1, allowing for a greater number of nitride semiconductor light-emitting elements 1 to be produced on a wafer. Furthermore, the area of ​​the light-emitting mesa structure 22 in the nitride semiconductor light-emitting element 1 (its occupation rate relative to the chip area) can be increased. This can also be expected to improve the light output per unit area in the nitride semiconductor light-emitting element 1.

[0048] The passivation layer 50 is made of, for example, SiN or SiO ２ , SiON, Al ２ O ３ The passivation layer 50 can be formed using oxides or nitrides such as a ZrO layer. From the viewpoint of waterproofing and stress on the device, it is preferable that silicon oxide or silicon nitride, or both, be used for the passivation layer 50. There are no particular restrictions on the method for forming the passivation layer 50, but it can be formed, for example, by a plasma CVD (Chemical Vapor Deposition) device, a sputtering device, a vacuum deposition device, or the like. When a silicon nitride film is formed as the passivation layer 50 using a plasma CVD device, monosilane (SiH) is used as a supply gas for silicon, which is a constituent element. ４ ) as a nitrogen feed gas and ammonia (NH ３ In addition, when a silicon oxide film is formed as the passivation layer 50 using a plasma CVD apparatus, monosilane (SiH) is used as a supply gas for silicon, which is a constituent element. ４ ) as the oxygen supply gas, and nitrous oxide (N ２ O) is widely known.

[0049] From the viewpoints of productivity and stress on the device, the thickness of the passivation layer 50 is preferably 10 nm to 1000 nm, and more preferably 50 nm to 500 nm. From the viewpoints of further improving waterproofing and suppressing peeling of the passivation layer 50, other passivation layers, metal layers, etc. may be disposed on the passivation layer 50.

[0050] <Pad Electrode> The pad electrode 70 is disposed on a portion of the passivation layer 50, on the first electrode region 31, the second electrode region 32, and the third electrode region 33 that are not covered by the passivation layer 50, and on the second electrode 40 that is not covered by the passivation layer 50. The pad electrode 70 has a first pad electrode portion 71 that electrically connects the first electrode region 31, the second electrode region 32, and the third electrode region 33, a second pad electrode portion 72 that is disposed on a portion of the passivation layer 50 and on the second electrode 40 that is not covered by the passivation layer 50, and a third pad electrode portion 73 that is formed on a portion of the passivation layer 50 and on a portion of the protective mesa structure 23.

[0051] The first pad electrode portion 71 covers a part of the second passivation coating region 52 and a part of the third passivation coating region 53. Therefore, the first pad electrode portion 71 has the effect of improving the adhesion of the second passivation coating region 52 to the first electrode region 31 and the adhesion of the third passivation coating region 53 to the second electrode region 32. Furthermore, by forming the first pad electrode portion 71, an external connection region based on the first electrode region 31 and an extraction electrode region that electrically connects the first electrode region 31, the second electrode region 32, and the third electrode region 33 can be formed at the same time, which is preferable from the viewpoint of simplifying the manufacturing process.

[0052] The second pad electrode 72 covers a portion of the passivation covered region (not shown) where the passivation layer 50 covers the outer edge of the light emitting mesa structure 22 (see FIG. 2A ). Therefore, the second pad electrode 72 has the effect of improving adhesion of the passivation layer 50 to the light emitting mesa structure 22. The third pad electrode 73 covers a portion of the first passivation covered region 51 that covers the protective mesa structure 23. More specifically, as shown in FIG. 3 , the third pad electrode 73 is disposed so as to cover the first passivation covered region 51, which is the region of the passivation layer 50 that covers the outer edge of the protective mesa structure 23, and at least a portion of the region of the protective mesa structure 23 that is not covered by the passivation layer 50. Therefore, the third pad electrode 73 has the effect of improving adhesion of the first passivation covered region 51 to the protective mesa structure 23. In addition, by using a structure in which the pad electrode 70 covers the outer edge of the passivation layer 50, moisture is prevented from penetrating into the semiconductor layer or electrode portion from the end of the passivation layer 50, and reaction with oxygen and water vapor in the air is suppressed, which is also preferable from the standpoint of reliability.

[0053] The present disclosure will be described in more detail below with reference to examples and comparative examples. Note that the nitride semiconductor light-emitting device according to the present disclosure is not limited to the examples shown below.

[0054] [Example 1] <Example 1-1> The nitride semiconductor light emitting device of Example 1-1 is a nitride semiconductor light emitting device having the structure shown in FIGS. 1 and 2 described in the embodiment. Each layer of the nitride semiconductor light emitting device has the following configuration. The substrate is an AlN substrate. The first n-type semiconductor layer contains 2.0×10 Si as an impurity. ２０ cm －３ containing n-type Al ０．７ Ga ０．３ N(n-Al ０．７ Ga ０．３ The first n-type semiconductor layer is a 400 nm thick n-type semiconductor layer.

[0055] The light-emitting mesa structure is composed of a second n-type semiconductor layer having a thickness of 150 nm, a first quantum well layer having a thickness of 70 nm, and a first p-type semiconductor layer having a thickness of 10 nm, while the protective mesa structure is composed of a third n-type semiconductor layer having a thickness of 150 nm, a second quantum well layer having a thickness of 70 nm, and a second p-type semiconductor layer having a thickness of 10 nm.

[0056] The second n-type semiconductor layer and the third n-type semiconductor layer contain 2.0×10 Si as an impurity. ２０ cm －３ Contains n-Al ０．７ Ga ０．３ The first quantum well layer and the second quantum well layer are made of AlN layers with a thickness of 3 nm. ０．５１ Ga ０．４９ N layer (well layer) and Al containing Si as an impurity with a thickness of 11 nm. ０．７８ Ga ０．２２ The first p-type semiconductor layer of the light emitting mesa structure and the second p-type semiconductor layer of the protective mesa structure contain 2.0×10 Mg as an impurity. ２０ cm －３ The semiconductor layer is formed of a p-type GaN (p-GaN) layer containing ZnO.

[0057] The first electrode formed on the first n-type semiconductor layer is made of Ti, Al, Ni, and Au. The second electrode formed on the first p-type semiconductor layer of the light emitting mesa structure is made of Ni and Au. The passivation layer is a silicon nitride layer with a film thickness of 240 nm.

[0058] The nitride semiconductor light-emitting device of Example 1-1 was fabricated by the following method. First, 2.0×10 Si was added as an impurity to an AlN substrate formed of an AlN single crystal. ２０ cm －３ Contains n-Al ０．７ Ga ０．３ The N layer was formed to a thickness of 550 nm. ０．７ Ga ０．３ On the N layer, a 3 nm thick Al ０．５１ Ga ０．４９ N layer and Al containing Si as an impurity with a thickness of 11 nm ０．７８ Ga ０．２２N layers were alternately stacked in layers of 5 each, for a total thickness of 70 nm. ２０ cm －３ A p-GaN layer containing nitride semiconductor layers was formed to a thickness of 10 nm. These layers were formed by metal organic chemical vapor deposition (MOCVD). As a result, a stacked structure made of nitride semiconductor layers was formed on the AlN substrate.

[0059] Next, the stacked body on the AlN substrate is subjected to dry etching to remove the regions other than the regions that will become the light emitting mesa structure and the protective mesa structure of the stacked body to a predetermined depth. ０．７ Ga ０ ．３ The N layer was partially exposed. As a result, the stack was formed into a shape in which the light-emitting mesa structure and the protective mesa structure protruded from the 400 nm-thick first n-type semiconductor layer. This dry etching was performed using a chlorine-based gas after a resist pattern was formed on the stack by photolithography. The chip in Example 1 was square, with each side measuring 860 μm, and the protective mesa structure was formed in a region extending 20 μm from the outer periphery of the chip.

[0060] Next, a Ti layer, an Al layer, a Ni layer, and an Au layer were sequentially formed on a portion of the exposed first n-type semiconductor layer using electron beam evaporation to form a metal stacked film, and the metal stacked film was then heat-treated using RTA to form a first electrode. The first electrode (first electrode region, second electrode region, and third electrode region) was formed so that the first gap, which was the distance between the protective mesa structure and the first electrode region, was 2 μm and the second gap, which was the distance between the first electrode region and the second electrode region, was 9 μm. Furthermore, a Ni layer and an Au layer were sequentially formed on a portion of the first p-type semiconductor layer of the light-emitting mesa structure using electron beam evaporation to form a metal stacked film, and the second electrode was then heat-treated using RTA to form a second electrode. Next, a 240 nm-thick silicon nitride film was formed using plasma CVD to cover the entire AlN substrate (the entire top and side surfaces) on which the light-emitting mesa structure, protective mesa structure, first electrode, and second electrode were formed.

[0061] Next, a resist pattern formed by photolithography is used to４ Openings were formed at predetermined positions in the silicon nitride film by etching using a fluorine-containing ... Finally, the wafer was divided into individual pieces by laser dicing and breaking, and the submounts were flip-chip mounted by the GGI (Gold to Gold Interconnection) method to form a package.

[0062] [Evaluation] To confirm the effect of damage resistance during external connection on the nitride semiconductor light-emitting device obtained in Example 1-1, the state of delamination of the first pad electrode and the first electrode (first electrode region) was observed. It was confirmed that no delamination occurred in the nitride semiconductor light-emitting device of Example 1-1. Because the nitride semiconductor light-emitting device after grinding and polishing has sufficient transparency, the state of delamination of the pad electrode and the first electrode in the external connection region can be visually observed from the backside. Furthermore, to evaluate the delamination, cracks, and microcracks of the first pad electrode and the first electrode, which are not visible to the naked eye, a 1000-hour continuous current test (250 mA) was performed on the nitride semiconductor light-emitting device in an environment of 55°C and 85% RH. Generally, when an Al-containing nitride semiconductor or a first electrode (an electrode for an n-type semiconductor) reacts with oxygen or water vapor in the air and deteriorates during a current test, it turns black. Further deterioration leads to increased resistance of the semiconductor and an increase in the device's driving voltage. Therefore, the appearance around the external connection region after the continuous current test was evaluated, and it was confirmed that no blackening occurred around the external connection region. That is, it was confirmed that in the nitride semiconductor light-emitting element of Example 1-1, peeling and cracking of the pad electrode and the first electrode, and peeling and cracking (including microcracks) of the passivation layer due to physical loads during external connection were suppressed. That is, it was confirmed that a nitride semiconductor light-emitting element with improved resistance to damage during external connection was obtained in Example 1-1.

[0063] <Comparative Example 1-1> The nitride semiconductor light-emitting device of Comparative Example 1-1 is a nitride semiconductor light-emitting device having the structure shown in Figures 5 and 6. Here, Figure 5 is a plan view schematically showing the configuration of the nitride semiconductor light-emitting device of Comparative Example 1-1, and Figure 6 is a cross-sectional view schematically showing the configuration of the nitride semiconductor light-emitting device, showing the CC cross section in Figure 5. Note that in Figures 5 and 6, for ease of explanation, the same reference numerals are used to denote parts corresponding to the parts constituting the nitride semiconductor light-emitting device shown in Figures 1 and 2.

[0064] In Comparative Example 1, when forming the metal laminated film that becomes the first electrode of the nitride semiconductor light emitting device, only the second electrode region and the third electrode region are formed, and the first electrode region is not formed. ４The opening was formed in the same manner as in Example 1-1, except that when openings were formed by etching, openings were not formed in the regions where the first electrode regions were not formed.

[0065] [Evaluation] When the state of peeling of the first pad electrode in the same region as in Example 1-1 (the region where the first electrode region was not formed) was confirmed for the obtained nitride semiconductor light-emitting device of Comparative Example 1-1 by the same method as in Example 1-1, peeling was clearly confirmed in the first pad electrode portion. Since the first electrode region was not formed in Comparative Example 1-1, it was not possible to form a first narrow space between the protective mesa structure and the first electrode region, and a second narrow space between the first electrode region and the second electrode region. In other words, the region where the first electrode region was not formed had to withstand physical damage solely through the adhesion between the first pad electrode and the passivation layer, and it is thought that the adhesion between the first pad electrode and the passivation layer was insufficient.

[0066] <Comparative Example 1-2> The nitride semiconductor light-emitting device of Comparative Example 1-2 is a nitride semiconductor light-emitting device having the structure shown in Figures 7 and 8. Here, Figure 7 is a plan view schematically showing the configuration of the nitride semiconductor light-emitting device of Comparative Example 1-2, and Figure 8 is a cross-sectional view schematically showing the configuration of the nitride semiconductor light-emitting device, showing the D-D cross section in Figure 7. Note that in Figures 7 and 8, for ease of explanation, the same reference numerals are used to denote parts corresponding to the parts constituting the nitride semiconductor light-emitting device shown in Figures 1 and 2.

[0067] In Comparative Example 2, when forming the metal laminated film of the first electrode, only the second electrode region and the third electrode region were formed, and the first electrode region was not formed. ４ The opening was formed in the same manner as in Example 1-1, except that the opening was formed in the region where the first electrode region was not formed when the opening was formed by etching.

[0068] [Evaluation] For the obtained nitride semiconductor light-emitting device of Comparative Example 1-2, the state of peeling of the first pad electrode was confirmed in the same region as in Example 1-1 (the region where the first electrode region was not formed) using the same method as in Example 1-1. Although there was an improvement over Comparative Example 1-1, peeling was clearly observed in the first pad electrode portion. Similarly to Comparative Example 1-1, Comparative Example 1-2 also lacks the first electrode region, making it impossible to form the first narrow space portion and the second narrow space portion. In other words, in the region where the first electrode region was not formed in Comparative Example 1-2, the adhesion between the first pad electrode and the first n-type semiconductor layer was improved compared to the adhesion between the first pad electrode and the passivation layer in the region where the first electrode region was not formed in Comparative Example 1-1, but it is believed that the adhesion was not sufficient.

[0069] The evaluation results for Example 1 are shown in Table 1 below.

[0070]

[0071] From the above, it was found that by adopting the structure of Example 1-1, a nitride semiconductor light emitting device with improved resistance to damage during external connection can be obtained.

[0072] [Example 2] In Example 2, nitride semiconductor light-emitting devices of Examples 2-1 to 2-9, which were fabricated by varying the width of the second passivation coating region, were evaluated. Specifically, the size of the first electrode region in the photomask used to form the first electrode was varied so as to vary the length of the second passivation coating portion. Here, the opening size of the passivation layer was maintained, so the alignment margin with the conductive bumps for external connection (see FIG. 2B) was maintained and a structure in which the same physical load was applied was evaluated. Furthermore, since the chip size needed to be increased to accommodate the increased size of the first electrode region, other photomasks were also modified and fabricated to fit the first electrode, including the pitch of one chip. When the size of the first electrode region was reduced, the chip size was not changed. The nitride semiconductor light-emitting devices of each Example and Comparative Example were obtained in the same manner as in Example 1-1, except for changing the photomask used.

[0073] Example 2-1 A nitride semiconductor light-emitting device of Example 2-1 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 0.1 μm.

[0074] Example 2-2 A nitride semiconductor light-emitting device of Example 2-2 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 0.5 μm.

[0075] Example 2-3 A nitride semiconductor light-emitting device of Example 2-3 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 1.0 μm.

[0076] Example 2-4 A nitride semiconductor light-emitting device of Example 2-4 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 2.0 μm.

[0077] Example 2-5 A nitride semiconductor light-emitting device of Example 2-5 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 8.0 μm.

[0078] Example 2-6 A nitride semiconductor light-emitting device of Example 2-6 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 10 μm.

[0079] Example 2-7 A nitride semiconductor light-emitting device of Example 2-7 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 15 μm.

[0080] Example 2-8 A nitride semiconductor light-emitting device of Example 2-8 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 17 μm.

[0081] Example 2-9 A nitride semiconductor light-emitting device of Example 2-9 was formed in the same manner as in Example 1-1, except that the width of the second passivation coating region was set to 20 μm.

[0082] [Evaluation] For the nitride semiconductor light-emitting devices of each Example, the state of peeling of the first pad electrode and the first electrode (particularly the first electrode region) and discoloration after a continuous current test were confirmed using the same method as in Example 1-1. Furthermore, for the nitride semiconductor light-emitting devices of each Example, the output when 500 mA was applied was measured, and the relative output per unit area of ​​the chip was calculated and evaluated, with the nitride semiconductor light-emitting device of Example 1-1 as the reference (1.00). The evaluation results for Example 2 are shown in Table 2 below.

[0083]

[0084] As shown in Table 2, in the nitride semiconductor light-emitting devices of each example, peeling of the first pad electrode or the first electrode region did not occur regardless of the width of the second passivation coating region. Furthermore, in the nitride semiconductor light-emitting devices of Examples 2-2 to 2-9, in which the width of the second passivation coating region was 0.5 μm or more, not only did peeling of the first pad electrode or the first electrode region not occur, but blackening of the nitride semiconductor and the first electrode was suppressed, i.e., an additional effect was confirmed in which invisible peeling, cracks, and microcracks of the first pad electrode or the first electrode were suppressed. This is thought to be because when the width of the second passivation coating region was 0.5 μm or more, the passivation layer sufficiently covered the first electrode region, suppressing invisible peeling, cracks, and microcracks of the first pad electrode or the first electrode. Taking into account the margin due to photomask alignment, the width of the second passivation coating region is more preferably 1 μm or more.

[0085] Furthermore, as shown in Table 2, the relative output per unit area of ​​the chip tended to gradually improve as the width of the second passivation coating region became narrower. This is thought to be because the chip size becomes smaller as the width of the second passivation coating region becomes narrower, thereby improving the output per unit area of ​​the chip. Therefore, the width of the second passivation coating region is preferably 15 μm or less, and more preferably 10 μm or less. From the above, it was confirmed that the width of the second passivation coating region is preferably 0.5 μm or more and 15 μm or less, and more preferably 1 μm or more and 10 μm or less.

[0086] [Example 3] In Example 3, nitride semiconductor light-emitting devices of Examples 3-1 to 3-8 were evaluated, which were fabricated by changing the first gap, which is the distance between the protective mesa structure and the first electrode region. Specifically, in the photomask for forming the mesa structure, the position of the protective mesa structure was changed so that the distance between the protective mesa structure and the first electrode region was changed. Since changing the photomask design changes the chip size, other photomasks were also modified and fabricated to fit the protective mesa structure, including the pitch of one chip. Except for changing the photomask used, nitride semiconductor light-emitting devices of each Example and Comparative Example were obtained in the same manner as in Example 1-1.

[0087] Example 3-1 A nitride semiconductor light-emitting device of Example 3-1 was formed in the same manner as in Example 1-1, except that the first gap was set to 0.1 μm.

[0088] Example 3-2 A nitride semiconductor light-emitting device of Example 3-2 was formed in the same manner as in Example 1-1, except that the first gap was set to 0.5 μm.

[0089] Example 3-3 A nitride semiconductor light-emitting device of Example 3-3 was formed in the same manner as in Example 1-1, except that the first gap was set to 1 μm.

[0090] Example 3-4 A nitride semiconductor light-emitting device of Example 3-4 was formed in the same manner as in Example 1-1, except that the first gap was set to 10 μm.

[0091] Example 3-5 A nitride semiconductor light-emitting device of Example 3-5 was formed in the same manner as in Example 1-1, except that the first gap was set to 15 μm.

[0092] Example 3-6 A nitride semiconductor light-emitting device of Comparative Example 3-2 was formed in the same manner as in Example 1-1, except that the first gap was set to 20 μm.

[0093] Example 3-7 A nitride semiconductor light-emitting device of Example 3-7 was formed in the same manner as in Example 1-1, except that the first gap was set to 25 μm.

[0094] Example 3-8 A nitride semiconductor light-emitting device of Example 3-8 was formed in the same manner as in Example 1-1, except that the first gap was set to 30 μm.

[0095] [Evaluation] For the nitride semiconductor light-emitting devices of each Example, the state of peeling of the first pad electrode and the first electrode (particularly the first electrode region) and discoloration after a continuous current test were confirmed using the same method as in Example 1-1. Furthermore, for the nitride semiconductor light-emitting devices of each Example, the output when 500 mA was applied was measured, and the relative output per unit area of ​​the chip was calculated and evaluated, with the nitride semiconductor light-emitting device of Example 1-1 as the reference (1.00). The evaluation results for Example 3 are shown in Table 3 below.

[0096]

[0097] As shown in Table 3, in the nitride semiconductor light-emitting devices of each example, peeling of the first pad electrode or the first electrode region did not occur regardless of the first gap between the protective mesa structure and the first electrode region. Furthermore, in the nitride semiconductor light-emitting devices of Examples 3-2 to 3-6, in which the first gap was 0.5 μm or greater, not only did peeling of the first pad electrode or the first electrode region not occur, but blackening of the nitride semiconductor or the first electrode was also suppressed, i.e., peeling, cracks, and microcracks of the first pad electrode or the first electrode that are not visible to the naked eye were further confirmed. When the first gap was 0.5 μm or greater, no interference color was observed in the first space, and good coverage of the passivation layer was confirmed. Therefore, the first gap is preferably 0.5 μm or greater, and more preferably 1 μm or greater.

[0098] Furthermore, as shown in Table 3, the shorter the first spacing, the gradually improved the relative output per unit area of ​​the chip. This is thought to be because the narrower the first spacing, the smaller the overall chip size becomes, i.e., the larger the area ratio of the light-emitting mesa structure, resulting in improved output per unit area of ​​the chip. Therefore, the first spacing is preferably 25 μm or less, and more preferably 20 μm or less. From the above, it was confirmed that the distance of the first narrow space portion is preferably 0.5 μm or more and 25 μm or less, and more preferably 1 μm or more and 20 μm or less.

[0099] [Example 4] In Example 4, nitride semiconductor light-emitting devices of Examples 4-1 to 4-7, which were fabricated by changing the second gap, which is the distance between the first electrode region and the second electrode region, were evaluated. Specifically, in the photomask for forming the first electrode region, the length of the second electrode region was changed so that the distance between the first electrode region and the second electrode region was changed. Nitride semiconductor light-emitting devices of each Example and Comparative Example were obtained in the same manner as in Example 1-1, except that the photomask for the second electrode region and the associated mask for passivation openings were changed.

[0100] Example 4-1 A nitride semiconductor light-emitting device of Example 4-1 was formed in the same manner as in Example 1-1, except that the second gap was set to 0.1 μm.

[0101] Example 4-2 A nitride semiconductor light-emitting device of Example 4-2 was formed in the same manner as in Example 1-1, except that the second gap was set to 0.5 μm.

[0102] Example 4-3 A nitride semiconductor light-emitting device of Example 4-3 was formed in the same manner as in Example 1-1, except that the second gap was set to 1 μm.

[0103] Example 4-4 A nitride semiconductor light-emitting device of Example 4-4 was formed in the same manner as in Example 1-1, except that the second gap was set to 100 μm.

[0104] Example 4-5 A nitride semiconductor light-emitting device of Example 4-5 was formed in the same manner as in Example 1-1, except that the second gap was set to 120 μm.

[0105] Comparative Example 4-6 A nitride semiconductor light-emitting device of Comparative Example 4-6 was formed in the same manner as in Example 1-1, except that the second gap was set to 140 μm.

[0106] Example 4-7 A nitride semiconductor light-emitting device of Example 4-7 was formed in the same manner as in Example 1-1, except that the second gap was set to 160 μm.

[0107] [Evaluation] For the nitride semiconductor light-emitting devices of each Example, the state of peeling of the first pad electrode and the first electrode (particularly the first electrode region) and discoloration after a continuous current test were confirmed using the same method as in Example 1-1. Furthermore, for the nitride semiconductor light-emitting devices of each Example, the area of ​​the light-emitting region within the chip surface (the region that emitted 85% or more of the maximum light-emitting intensity) when 500 mA was applied was measured, and the area of ​​the light-emitting region was calculated as the relative output per unit area of ​​the chip, with the area of ​​the light-emitting region in the nitride semiconductor light-emitting device of Example 1-1 set as the reference (1.00), and evaluated. The evaluation results for Example 4 are shown in Table 4 below.

[0108]

[0109] As shown in Table 4, in the nitride semiconductor light-emitting devices of each example, peeling of the first pad electrode or the first electrode region did not occur regardless of the second gap between the first electrode region and the second electrode region. Furthermore, in the nitride semiconductor light-emitting devices of Examples 4-2 to 4-6, in which the second gap was 0.5 μm or greater, not only did peeling of the first pad electrode or the first electrode region not occur, but blackening of the nitride semiconductor or the first electrode was also suppressed, i.e., peeling, cracks, and microcracks of the first pad electrode or the first electrode that are not visible to the naked eye were further confirmed. When the second gap was 0.5 μm or greater, no interference color was observed in the second space, and it was confirmed that the coverage of the passivation layer was good. Therefore, the second gap is preferably 0.5 μm or greater, and more preferably 1 μm or greater.

[0110] Furthermore, as shown in Table 4, the relative output per unit area of ​​the chip tended to improve as the second spacing became shorter. As the second spacing became shorter, the electrode length increased, making it easier to supply electrons to the tip of the light-emitting mesa structure, reducing the likelihood of unevenness in the light-emitting region. Therefore, as the second spacing became shorter, the length of the second electrode portion could be maintained at a long length, further reducing the likelihood of unevenness in the light-emitting region. The reduced likelihood of unevenness in the light-emitting region means that partial reductions in light output are less likely to occur, improving the light-emitting output per unit area of ​​the chip. Therefore, the second spacing is preferably 140 μm or less, and more preferably 120 μm or less. From the above, it was confirmed that the second spacing is preferably 0.5 μm or more and 140 μm or less, and more preferably 1 μm or more and 120 μm or less.

[0111] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the technical scope described in the above-described embodiments. Various modifications and improvements can be made to the above-described embodiments, and it is clear from the claims that such modifications and improvements can also be included in the technical scope of the present disclosure.

[0112] REFERENCE SIGNS LIST 1 Nitride semiconductor light emitting element 10 Substrate 20 Nitride semiconductor stack 21 First n-type semiconductor layer 22 Light emitting mesa structure 221 Second n-type semiconductor layer 222 First quantum well layer 223 First p-type semiconductor layer 23 Protective mesa structure 231 Third n-type semiconductor layer 232 Second quantum well layer 233 Second p-type semiconductor layer 30 First electrode 31 First electrode region 32 Second electrode region 33 Third electrode region 40 Second electrode 50 Passivation layer 51 First passivation coating region 52 Second passivation coating region 53 Third passivation coating region 60 Narrow space portion 61 First narrow space portion 62 Second narrow space portion 70 Pad electrode 71 First pad electrode portion 72 Second pad electrode portion 73 Third pad electrode portion

Claims

a nitride semiconductor laminate including: a substrate; a first conductivity type semiconductor layer disposed on the substrate; a light emitting mesa structure disposed on a portion of the first conductivity type semiconductor layer; and a non-emitting protective mesa structure disposed on the first conductivity type semiconductor layer and spatially separated from the light emitting mesa structure, surrounding the light emitting mesa structure; a first electrode disposed on another portion of the first conductivity type semiconductor layer, the first electrode having at least two electrode regions: a first electrode region disposed a first distance apart from the protective mesa structure in a plan view, and a second electrode region disposed a second distance apart from the first electrode region; a passivation layer directly covering an edge of the protective mesa structure, outer edges of each of the plurality of electrode regions, and a surface of the first conductivity type semiconductor layer; and a first pad electrode disposed so as to cover a portion of the surface of the passivation layer and at least a portion of the surface of each of the plurality of electrode regions that is not covered by the passivation layer, and electrically connecting the plurality of electrode regions together.

2. The nitride semiconductor light-emitting device according to claim 1, wherein the protective mesa structure is disposed on the outer edge of the substrate.

3. The nitride semiconductor light-emitting element according to claim 2, wherein the first electrode regions are arranged at two or more corners of the substrate in a plan view, with the first gap between them and the protective mesa structure.

4. The nitride semiconductor light-emitting device according to claim 2, wherein the first electrode regions are arranged at the four corners of the substrate in a plan view with the first gap between them and the protective mesa structure.

5. The nitride semiconductor light-emitting element according to claim 1, wherein the light-emitting mesa structure and the protective mesa structure are arranged in a region other than a first narrow space formed at the first interval between the protective mesa structure and the first electrode region, and a second narrow space formed at the second interval between the first electrode region and the second electrode region.

6. The nitride semiconductor light-emitting element according to claim 1, wherein the passivation layer has a first passivation covering region that covers the edge of the protective mesa structure on the first electrode region side.

7. The nitride semiconductor light-emitting element according to claim 6, wherein the passivation layer is formed so as to overlap, in plan view, at least a portion of a region of the first conductivity type semiconductor layer that is located between the protective mesa structure and the first electrode region, and at least a portion of a region of the first conductivity type semiconductor layer that is located between the first electrode region and the second electrode region.

8. The nitride semiconductor light-emitting element according to claim 1, wherein the passivation layer has a second passivation covering region that covers the edge of the first electrode region, and the width of the region where the upper surface of the first electrode region is covered by the second passivation covering region is 0.5 μm or more and 15 μm or less.

9. The nitride semiconductor light-emitting element according to claim 8, wherein the first pad electrode is provided so as to cover a portion of the second passivation-covered region.

10. The nitride semiconductor light-emitting element according to any one of claims 1 to 9, further comprising a third pad electrode portion arranged to cover a region of the passivation layer covering the edge of the protective mesa structure and at least a portion of a region of the protective mesa structure not covered by the passivation layer.

11. The nitride semiconductor light-emitting device according to claim 1, wherein the first distance is not less than 0.5 μm and not more than 25 μm.

12. The nitride semiconductor light-emitting device according to claim 1, wherein the second distance between the first electrode region and the second electrode region is 0.5 μm or more and 140 μm or less.

13. The nitride semiconductor light-emitting device according to claim 1, wherein the protective mesa structure is disposed to surround the light-emitting mesa structure in plan view.

14. The nitride semiconductor light-emitting element according to claim 1, wherein the substrate is rectangular in plan view, the protective mesa structure is provided along the outer periphery of the substrate, a plurality of the light-emitting mesa structures are provided along the same direction as the extension direction of one side of the protective mesa structure, the first electrode region is provided on the inner periphery of a corner of the protective mesa structure, and the second electrode region is adjacent to the first electrode region and is provided to extend in one direction along the protective mesa structure and the light-emitting mesa structure.

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