Semiconductor device

Abstract

This semiconductor device comprises: a diode connection electrode that is disposed on a first main surface of a chip, that is spaced apart from a diode connection straight portion in a second direction parallel to the first main surface and orthogonal to a first direction, and that is electrically connected to a collector electrode; and a diode forming body including a Zener diode electrically connected at one end to the diode connection straight portion through a first contact and electrically connected at the other end to the diode connection electrode through a second contact. When a diode arrangement length L represents the length from one end to the other end of the Zener diode in the second direction, and a diode arrangement width W represents the length of the Zener diode in the first direction, the ratio W / L of the diode arrangement width to the diode arrangement length is 1.3 or more.

Description

Semiconductor Devices Related Applications

[0001] This application claims priority based on Patent Application No. 2022-209478 filed with the Japan Patent Office on December 27, 2022, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] FIG. 12 is a block diagram showing the configuration of an internal combustion engine ignition system disclosed in Patent Document 1.

[0004] The ECU 202 is an electronic control unit for controlling the operation of the engine. The ECU 202 generates an ignition instruction signal IGT, which indicates the ignition timing of the spark plug 203, as a periodic signal synchronized with the rotation of the engine. The ECU 202 outputs the ignition instruction signal IGT to the igniter 201.

[0005] The ignition coil 204 generates a high voltage for discharging the spark plug 203. The ignition coil 204 includes a primary coil 241 and a secondary coil 242. One terminal of the primary coil 241 is connected to the battery 205, and the other terminal is connected to the output terminal OUT of the igniter 201. One terminal of the secondary coil 242 is connected to the battery 205, and the other terminal is connected to the spark plug 203.

[0006] The spark plugs 203 are provided for each cylinder of the engine (not shown), and cause the air-fuel mixture in the engine to explode by discharging electricity.

[0007] The igniter 201 controls the discharge of the spark plug 203 based on an ignition command signal IGT input from the ECU 202. Specifically, the igniter 201 controls the current Ic flowing through the primary coil 241 of the ignition coil 204 based on the ignition command signal IGT. The igniter 201 passes the current Ic through the primary coil 241 while the ignition command signal IGT is at a high level. The igniter 201 then cuts off the current Ic flowing through the primary coil 241 when the ignition command signal IGT switches from a high level to a low level. This generates a counter electromotive force of several hundred volts in the primary coil 241. At this time, a high voltage of, for example, several tens of kV, calculated by multiplying the primary side voltage by the turns ratio, is generated in the secondary coil 242. The spark plug 203 discharges due to the high voltage applied from the secondary coil 242.

[0008] The igniter 201 has a power supply terminal VDD, a ground terminal GND, an input terminal IN, an output terminal OUT, and a feedback terminal FB. The power supply terminal VDD is connected to a battery 205 and is supplied with a power supply voltage. The ground terminal GND is grounded. The input terminal IN is connected to the ECU 202 via a harness (not shown). An ignition command signal IGT is input from the ECU 202 to the input terminal IN. The output terminal OUT is connected to a primary coil 241 of the ignition coil 204. The feedback terminal FB is connected to the ECU 202 via a harness and outputs an ignition confirmation signal IGF to the ECU 202. The igniter 201 also has an IGBT 211, a current detection resistor 212, and a control circuit 213.

[0009] The IGBT 211 is switched on and off by the control circuit 213, thereby switching between conduction and non-conduction between the output terminal OUT and the ground terminal GND. The collector terminal of the IGBT 211 is connected to the primary coil 241 of the ignition coil 204 via the output terminal OUT. The emitter terminal of the IGBT 211 is grounded via the ground terminal GND. The gate terminal of the IGBT 211 is connected to the control circuit 213. The IGBT 211 is switched on and off in response to a gate drive signal input from the control circuit 213 to the gate terminal.

[0010] The current detection resistor 212 is connected between the emitter terminal of the IGBT 211 and the ground terminal GND. When the IGBT 211 is in the on state, the current Ic that flows through the primary coil 241 of the ignition coil 204 flows through the current detection resistor 212. Therefore, a detection voltage Vcs that is proportional to the current Ic is generated between the terminals of the current detection resistor 212.

[0011] The control circuit 213 controls the igniter 201. The control circuit 213 controls the IGBT 211 based on an ignition command signal IGT input from the ECU 202. The control circuit 213 also monitors the current Ic flowing through the primary coil 241, generates an ignition confirmation signal IGF, and outputs it to the ECU 202.

[0012] The control circuit 213 includes a drive unit 333 and an ignition confirmation unit 334. The drive unit 333 controls the IGBT 211. The drive unit 333 controls the on / off of the IGBT 211 by controlling the voltage of the gate terminal of the IGBT 211 in response to an ignition instruction signal IGT input from the ECU 202. The drive unit 333 turns the IGBT 211 on while the ignition instruction signal IGT is at a high level, and turns the IGBT 211 off while the ignition instruction signal IGT is at a low level. When the ignition instruction signal IGT switches from a high level to a low level, the IGBT 211 switches from on to off. This generates a high voltage in the secondary coil 242 of the ignition coil 204, and the high voltage is applied to the spark plug 203.

[0013] The ignition confirmation unit 334 generates an ignition confirmation signal IGF based on the current Ic flowing through the primary coil 241 and outputs the signal to the ECU 202. The ignition confirmation unit 334 generates the ignition confirmation signal IGF by comparing the current Ic with reference currents Iref1 and Iref2 (>Iref1). The ignition confirmation unit 334 generates a signal that is at a first level (e.g., low level) when the detected voltage Vcs is a voltage between the reference voltages Vref1 and Vref2 (Vref1<Vc<Vref2) and at a second level (e.g., high level) otherwise (Vc<Vref1, Vref2<Vc), and outputs the signal as the ignition confirmation signal IGF to the ECU 202.

[0014] Japanese Patent Application Laid-Open No. 2006-261562

[0015] Although not disclosed in Patent Document 1, it is known that a Zener diode 301 is connected between the collector terminal and gate terminal of the IGBT 211 as a surge protection measure, as shown by the dashed line in Figure 12. This Zener diode 301 is provided to clamp the primary voltage generated when the primary current is interrupted so that it does not exceed the withstand voltage of the IGBT 211. When a primary voltage exceeding the Zener voltage is generated, the Zener diode 301 breaks down, turning on the IGBT 211. This prevents a voltage exceeding the withstand voltage from being applied to the IGBT 211.

[0016] However, the surge generated at the collector electrode of the IGBT 211 due to abnormal operation in which voltage noise generated during secondary ignition flows into the collector electrode of the primary IGBT through parasitic capacitance formed between windings in the boost coil is a high-frequency surge with a pulse width of several tens of nanoseconds. As a result, the operation of the IGBT 211 cannot keep up with the Zener current, and there is a risk that the IGBT 211 will suffer bulk breakdown.

[0017] An object of one embodiment of the present disclosure is to provide a semiconductor device capable of suppressing bulk breakdown due to a high-frequency surge.

[0018] One embodiment of the present disclosure relates to a chip having a first main surface and a second main surface opposite to the first main surface, an emitter electrode disposed on the first main surface, a gate pad disposed on the first main surface and on an outer periphery side of the emitter electrode, a gate finger disposed on the first main surface and on an outer periphery side of the emitter electrode, electrically connected to the gate pad, and having a linear portion for diode connection extending in a predetermined first direction along the first main surface, a collector electrode disposed on the second main surface, and a gate electrode disposed on the first main surface and extending from the linear portion for diode connection in a direction along the first main surface and perpendicular to the first direction. Provided is a semiconductor device including: a diode forming body including a diode connection electrode arranged at intervals in two directions and electrically connected to the collector electrode; and a Zener diode having one end electrically connected to the diode connection straight portion via a first contact and the other end electrically connected to the diode connection electrode via a second contact, wherein the length in the second direction from the one end to the other end of the Zener diode is defined as a diode arrangement length, and the length of the Zener diode in the first direction is defined as a diode arrangement width, and the ratio of the diode arrangement length to the diode arrangement width is 1.3 or more.

[0019] This configuration can prevent bulk breakdown due to high frequency surges.

[0020] One embodiment of the present disclosure relates to a chip having a first main surface and a second main surface opposite thereto, an emitter electrode disposed on the first main surface, a gate pad disposed on the first main surface and on an outer periphery side of the emitter electrode, a gate finger disposed on the first main surface and on an outer periphery side of the emitter electrode, electrically connected to the gate pad, and having a linear portion for diode connection extending in a predetermined first direction along the first main surface, a collector electrode disposed on the second main surface, and a gate finger disposed on the first main surface and spaced apart from the linear portion for diode connection in a second direction that is a direction along the first main surface and perpendicular to the first direction. a diode forming body including a diode connection electrode arranged with a gap therebetween and electrically connected to the collector electrode; and a Zener diode having one end electrically connected to the diode connection straight portion via a first contact and the other end electrically connected to the diode connection electrode via a second contact, wherein the length in the second direction from the one end to the other end of the Zener diode is defined as a diode arrangement length, and the length in the first direction of the Zener diode is defined as a diode arrangement width, wherein the diode arrangement length is 550 μm or more and 610 μm or less, and the diode arrangement width is 750 μm or more.

[0021] This configuration can prevent bulk breakdown due to high frequency surges.

[0022] FIG. 1 is an electrical circuit diagram for explaining the electrical configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a schematic plan view of the semiconductor device according to the first embodiment of the present disclosure. FIG. 3 is a schematic plan view of the semiconductor device according to the first embodiment of the present disclosure, with a passivation film omitted. FIG. 4 is an enlarged view of a region surrounded by a two-dot chain line IV in FIG. 3. FIG. 5 is an enlarged view of a region surrounded by a two-dot chain line V in FIG. 3. FIG. 6 is a schematic cross-sectional view taken along line VI-VII in FIG. 3. FIG. 7A is a schematic cross-sectional view showing a portion of a cross-section taken along line VII-VII in FIG. 4. FIG. 7B is a schematic cross-sectional view showing a portion of a cross-section taken along line VII-VII in FIG. 4, which is a cross-sectional view connected to the +X side of the cross-sectional view of FIG. 7A. FIG. 7C is a schematic cross-sectional view showing a portion of a cross-section taken along line VII-VII in FIG. 4, which is a cross-sectional view connected to the +X side of the cross-sectional view of FIG. 7B. FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9A is a schematic cross-sectional view showing a portion of a cross-section taken along line IX-IX in FIG. 5. FIG. 9B is a schematic cross-sectional view showing a portion of a cross-section taken along line IX-IX in FIG. 5, which is a cross-sectional view connected to the +X side of the cross-sectional view in FIG. 9A. FIG. 10 is a table showing the diode arrangement length L, diode arrangement width W, and ratio W / L of diode arrangement width W to diode arrangement length L for each sample S1, S2, and S3. FIG. 11 is a table showing evaluation results of a special operation test. FIG. 10 is a block diagram showing an example of the configuration of an internal combustion engine ignition system.

[0023] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] [Electrical Configuration of Semiconductor Device] FIG. 1 is an electric circuit diagram for explaining the electrical configuration of a semiconductor device according to an embodiment of the present disclosure.

[0025] The semiconductor device 1 is suitable for use as an IGBT for an internal combustion engine ignition system, but can also be used as a switching element other than an IGBT for an internal combustion engine ignition system.

[0026] The semiconductor device 1 includes an IGBT 101, a first Zener diode 102, a second Zener diode 103, a gate resistor circuit 104, and a gate terminal electrode 105. The IGBT 101 includes a collector electrode (C), an emitter electrode (E), and a gate electrode (G).

[0027] The gate resistance circuit 104 is connected between the gate terminal electrode 105 and the gate electrode (G) of the IGBT 101. The gate resistance circuit 104 is composed of a parallel circuit of a first gate resistance R1 and a second gate resistance R2.

[0028] The first Zener diode 102 is connected between the gate terminal electrode 105 and the emitter electrode (E). The second Zener diode 103 is connected between the collector electrode (C) and the gate electrode (G).

[0029] [Structure of Semiconductor Device] Fig. 2 is a schematic plan view of the semiconductor device according to the first embodiment of the present disclosure. Fig. 3 is a schematic plan view of the semiconductor device according to the first embodiment of the present disclosure, with a passivation film omitted. Fig. 4 is an enlarged view of the region surrounded by the two-dot chain line IV in Fig. 3. Fig. 5 is an enlarged view of the region surrounded by the two-dot chain line V in Fig. 3.

[0030] For ease of explanation, the +X direction, −X direction, +Y direction, and −Y direction shown in FIGS. 2 and 3 may be used below. The +X direction is a predetermined direction along the first main surface 30a of the chip 40 (see FIG. 6) in a plan view, and the +Y direction is a direction along the first main surface 40a of the chip 40 in a plan view, and is a direction perpendicular to the +X direction. The −X direction is the direction opposite to the +X direction. The −Y direction is the direction opposite to the +Y direction. The +X direction and −X direction are referred to collectively simply as the "X direction." The +Y direction and −Y direction are referred to collectively simply as the "Y direction."

[0031] 2, the semiconductor device 1 has a rectangular parallelepiped shape that is elongated in the X direction in a plan view. The semiconductor device 1 has first to fourth side surfaces 40c to 40f. Specifically, the first to fourth side surfaces 40c to 40f are four side surfaces of a chip 40 (see FIGS. 6, 7A, 9B, etc.) described below. In a plan view, the first side surface 40c and the third side surface 40e extend parallel to the X direction, and the second side surface 40d and the first side surface 40f extend parallel to the Y direction.

[0032] The semiconductor device 1 includes an emitter electrode 4, a gate pad 5, gate fingers 6, and an EQR electrode 7 formed on its front surface side (the surface side facing the first main surface 40a of the chip 40). In this embodiment, the emitter electrode 4, the gate pad 5, the gate fingers 6, and the EQR electrode 7 have a layered structure including a Ti film and an Al alloy film (e.g., an AlSiCu alloy film) formed in this order from the chip 40 side. The gate pad 5 corresponds to the gate terminal electrode 105 in FIG. 1 . The EQR electrode 7 is an example of a "diode-connecting electrode" in the present disclosure.

[0033] The emitter electrode 4 is formed so as to cover the active region 2 of the semiconductor device 1. The active region 2 is provided in the inner portion of the first main surface 40a of the chip 40. The active region 2 is a region where an IGBT element structure 44, which will be described later, is formed.

[0034] The emitter electrode 4 is formed over almost the entire active region 2. In plan view, the emitter electrode 4 has a rectangular shape with two sides parallel to the X direction and two sides parallel to the Y direction. A first recess 8 and a second recess 9 are selectively formed in the emitter electrode 4 in plan view.

[0035] In this embodiment, in plan view, a first recess 8 recessed in the +X direction is formed in the center of the length of the side on the second side surface 40d side of the emitter electrode 4, of the two sides parallel to the X direction. In plan view, the first recess 8 is open in the −X direction.

[0036] In this embodiment, a second recess 9 recessed in the −X direction is formed in the center of the length of the side of the emitter electrode 4 that is on the fourth side surface 40f side, of the two sides that are parallel to the X direction in a plan view. In a plan view, the second recess 9 opens in the +X direction. In this embodiment, the length of the second recess 9 in the Y direction is longer than the length of the first recess 8 in the Y direction.

[0037] The outer peripheral edge of the emitter electrode 4 includes a first curved portion 11 that convex in the +X direction on the +Y side of the second recess 9. In addition, the outer peripheral edge of the emitter electrode 4 includes a second curved portion 12 that convex in the +X direction on the -Y side of the second recess 9.

[0038] A peripheral region 3 surrounding the active region 2 is provided outside the active region 2 on the first main surface 40 of the chip 40. The gate pad 5 and the gate fingers 6 are formed in the peripheral region 3. In a plan view, the gate pad 5 includes a rectangular main portion 5A that is long in the Y direction, and a protruding portion 5B that protrudes in the −X direction from the center of the length of the side on the −X side of the main portion 5A.

[0039] The gate finger 6 has an annular shape with ends in a plan view. In this specification, the term "annular" includes a circular annular shape, a square annular shape, a polygonal annular shape, etc. One end 6A of the gate finger 6 is spaced apart in the +Y direction from the protruding portion 5B of the gate pad 5, and is spaced apart in the −X direction from the main portion 5A of the gate pad 5. The other end 6B of the gate finger 6 is spaced apart in the −Y direction from the protruding portion 5B of the gate pad 5, and is spaced apart in the −X direction from the main portion 5A of the gate pad 5.

[0040] An intermediate portion between one end 6A and the other end 6B of the gate finger 6 extends along the outer periphery of the emitter electrode 4 in a plan view. The gate finger 6 includes a first curved portion 6C that follows the first curved portion 11, a second curved portion 6D that follows the second curved portion 12, and a straight portion 6E that connects the first curved portion 6C and the second curved portion 6D. The first curved portion 6C and the second curved portion 6D face the side surface of the second recess 9, and the straight portion 6E faces the bottom surface of the second recess 9. The straight portion 6E is an example of a "diode-connecting straight portion" in the present disclosure.

[0041] The EQR electrode 7 is formed outside the gate fingers 6 in the outer circumferential region 3. The EQR electrode 7 is formed along the outer periphery of the first main surface 40a of the chip 40. The EQR electrode 7 is formed in a quadrangular ring shape in a plan view. The EQR electrode 7 includes a first linear portion 7A, a second linear portion 7B, a third linear portion 7C, and a fourth linear portion 7D that are respectively along the first side surface 40c, the second side surface 40d, the third side surface 40e, and the fourth side surface 40f in a plan view. The connection portions of these linear portions 7A to 7D are formed in an outwardly convex curved shape in a plan view.

[0042] The semiconductor device 1 includes a passivation film 13 that covers the emitter electrode 4, the gate pad 5, the gate fingers 6, and the EQR electrode 7. The passivation film 13 collectively covers the emitter electrode 4, the gate pad 5, the gate fingers 6, and the EQR electrode 7, and has a plurality of openings 14, 15 that expose a portion of the emitter electrode 4 and the gate pad 5, respectively. The passivation film 13 includes, for example, polyimide.

[0043] A portion of the emitter electrode 4 is exposed as a pad portion 16 from the first pad opening 14, and a portion of the main portion 5A of the gate pad 5 is exposed as a pad portion 17 from the second pad opening 15. A bonding material such as a bonding wire may be bonded to each of the pad portions 16, 17 when packaging the semiconductor device 1.

[0044] 3 to 5, the semiconductor device 1 includes an EQR wiring 21 arranged below the EQR electrode 7. The EQR wiring 21 is arranged along the EQR electrode 7 and has a ring shape (a quadrangular ring shape in this embodiment) in plan view. The EQR wiring 21 is electrically connected to the EQR electrode 7. In this embodiment, the EQR wiring 21 includes conductive polysilicon.

[0045] The semiconductor device 1 includes a gate wiring 22 that is arranged to pass under the protruding portion 5B of the gate pad 5 and the gate fingers 6. The gate wiring 22 has a quadrangular ring shape in a plan view. In this embodiment, the gate wiring 22 includes conductive polysilicon.

[0046] 4, the protruding portion 5B of the gate pad 5 is electrically connected to the gate wiring 22 via the contact 23. The contact 23 has a rectangular shape that is long in the Y direction in a plan view. In this embodiment, the contact 23 is formed by a part of the gate pad 5. The contact 23 may be formed by a member different from the gate pad 5. The contact 23 is an example of a "third contact" in the present disclosure.

[0047] The gate finger 6 is electrically connected to the gate wiring 22 via a contact 24. The contact 24 is arranged along the gate finger 6 except for both end portions 6A and 6B of the gate finger 6. The contact 24 has an annular shape with ends (an annular shape with ends in this embodiment) in a plan view. In this embodiment, the contact 24 is formed by a part of the gate finger 6. The contact 24 may be formed by a material different from the gate finger 6. The contact 24 is an example of a "first contact" in the present disclosure. The contact 24 is an example of a "first contact" and a "fourth contact" in the present disclosure.

[0048] One end 24A of the contact 24 is spaced apart in the +Y direction from the tip of one end 6A of the gate finger 6. The other end 24B of the contact 24 is spaced apart in the −Y direction from the tip of the other end 6B of the gate finger 6.

[0049] A first gate resistor R1 is formed by the portion of the gate wiring 22 between the portion where the contact 23 is connected and the portion where one end 24A of the contact 24 is connected. A second gate resistor R2 is formed by the portion of the gate wiring 22 between the portion where the contact 23 is connected and the portion where the other end 24B of the contact 24 is connected.

[0050] As a result, the protrusion 5B of the gate pad 5 is electrically connected to the gate finger 6 via the contact 23, the first gate resistor R1, and the contact 24, and is also electrically connected to the gate finger 6 via the contact 23, the second gate resistor R2, and the contact 24. In other words, the gate pad 5 is connected to the gate finger 6 via a parallel circuit (gate resistor circuit 104 in FIG. 1) with the first gate resistor R1 and the second resistor R2.

[0051] 3 and 4 , semiconductor device 1 includes a first diode 102 having one end electrically connected to gate pad 5 and the other end electrically connected to emitter electrode 4. Semiconductor device 1 includes a first diode-forming body 26 for forming first diode 102.

[0052] The first diode forming body 26 extends from below the main portion 5A of the gate pad 5 to below the periphery of the first recess 8 in the emitter electrode 4. In this embodiment, the first diode forming body 26 is made of conductive polysilicon.

[0053] The first diode forming body 26 has a rectangular shape elongated in the Y direction in plan view. In plan view, the first diode forming body 26 is larger than the main portion 5A. The side edge on the −X direction side of the first diode forming body 26 is spaced apart in the +X direction from the side edge on the −X direction side of the main portion 5A. The side edge on the +X direction side of the first diode forming body 26 is spaced apart from the side edge on the +X direction side of the main portion 5A and is located below the emitter electrode 4. Both end edges on the Y direction side of the first diode forming body 26 are each spaced apart from the corresponding end edges on the Y direction side of the main portion 5A and are located below the emitter electrode 4.

[0054] The main portion 5A of the gate pad 5 is electrically connected to the first diode-forming body 26 via a contact 25. In plan view, the contact 25 has a strip shape extending along three sides of the main portion 5A excluding the side on the −X side. In this embodiment, the contact 25 is formed by a part of the gate pad 5. The contact 25 may be formed by a member different from that of the gate pad 5.

[0055] The peripheral edge of the first recess 8 in the emitter electrode 4 is electrically connected to the first diode-forming body 26 via a contact 27. In a plan view, the contact 27 has a strip shape extending along the inner edge of the first recess 8 in the emitter electrode 4. In this embodiment, the contact 27 is formed by a part of the emitter electrode. The contact 27 may be formed by a material different from that of the emitter electrode 4.

[0056] A first Zener diode 102 is formed in the region between the location where the contact 25 is connected and the location where the contact 27 is connected in the first diode-forming body 26. As will be described later, the first Zener diode 102 is formed by forming a plurality of n-type regions 26n (see FIG. 7C ) and p-type regions 26p alternately in the X direction in the first diode-forming body 26.

[0057] In plan view, the semiconductor device 1 includes a plurality of annular (square annular in this embodiment) field plates 29 arranged between the EQR wiring 21 and the gate wiring 22. In this embodiment, four field plates 29 are provided. Each field plate 29 extends along the gate wiring 22. Adjacent two field plates 29 are arranged with a gap between them. In this embodiment, each field plate 29 includes n-type conductive polysilicon.

[0058] 3 and 5 , the semiconductor device 1 includes a second diode 103 having one end electrically connected to the straight portion 6E of the gate finger 6 and the other end electrically connected to the fourth straight portion 7D of the EQR electrode 7. The semiconductor device 1 includes a second diode-forming body 30 for forming the second diode 103.

[0059] In this embodiment, the second diode forming body 30 extends from below the peripheral edge of the emitter electrode 4 inside the straight portion 6E of the gate finger 6, passing below the straight portion 6E, to below the fourth straight portion 7D of the EQR electrode 7. In this embodiment, the second diode forming body 30 includes conductive polysilicon.

[0060] In plan view, the second diode forming body 30 is disposed between the straight portion 6E of the gate finger 6 and the fourth straight portion 7D of the EQR electrode 7, and includes a rectangular main portion 30A that is elongated in the Y direction. The second diode forming body 30 further includes a first extension portion (first connection portion) 30B that extends in the −X direction (inward) from the −X side edge of the main portion 30A, and a second extension portion (second connection portion) 30C that extends in the +X direction (outward) from the +X side edge of the main portion 30A. The main portion 30A is an example of a “diode forming body main portion” in this disclosure.

[0061] In this embodiment, a portion of the first extension 30B is formed by a portion of the gate wiring 22. That is, the first extension 30B includes a portion of the gate wiring 22. Furthermore, a portion of the second extension 30C is formed by a portion of the EQR wiring 21. That is, the second extension 30C includes a portion of the EQR wiring 21.

[0062] In plan view, the main portion 30A of the second diode forming body 30 is spaced apart in the -Y direction from the first curved portion 6C of the gate finger 6, and is spaced apart in the +Y direction from the second curved portion 6D of the gate finger 6.

[0063] The straight portion 6E of the gate finger 6 is electrically connected to the first extension 30B (gate wiring 22) of the second diode forming body 30 via a contact 24. The fourth straight portion 7D of the EQR electrode 7 is electrically connected to the second extension 30C (EQR wiring 21) of the second diode forming body 30 via a contact 56.

[0064] The region in the second diode forming body 30 between the location where the contact 24 is connected and the location where the contact 56 is connected is the second diode region 31. The second diode region 31 in the second diode forming body 30 constitutes the second Zener diode 103. In FIG. 5 , for clarity, the second diode forming body 30 is indicated by dot hatching, and the second diode region 31 is indicated by gray. The second diode region 31 is an example of a "diode region" in the present disclosure.

[0065] As will be described later, the second Zener diode 103 is formed by forming a plurality of n-type regions 30n (see FIG. 9B) and p-type regions 30p alternately in the X direction in the second diode forming body 30.

[0066] Each field plate 29 includes a straight portion 29A that passes through the main portion 30A of the second diode forming body 30. In other words, the main portion 30A of the second diode forming body 30 includes the straight portion 29A of each field plate 29. The straight portion 29A of each field plate 29 forms part of the n-type region 30n. In other words, the straight portion 29A of each field plate 29 forms part of the component of the second Zener diode 103.

[0067] Fig. 6 is a schematic cross-sectional view taken along line VI-VI in Fig. 3. Fig. 7A is a schematic cross-sectional view showing a portion of a cross-section taken along line VII-VII in Fig. 4. Fig. 7B is a schematic cross-sectional view showing a portion of a cross-section taken along line VII-VII in Fig. 4, which is a cross-sectional view connected to the +X side of the cross-sectional view of Fig. 7A. Fig. 7C is a schematic cross-sectional view showing a portion of a cross-section taken along line VII-VII in Fig. 4, which is a cross-sectional view connected to the +X side of the cross-sectional view of Fig. 7B.

[0068] Fig. 8 is a schematic cross-sectional view taken along line VIII-VIII in Fig. 4. Fig. 9A is a schematic cross-sectional view showing a part of a cross section taken along line IX-IX in Fig. 5. Fig. 9B is a schematic cross-sectional view showing a part of a cross section taken along line IX-IX in Fig. 5, which is a cross-sectional view connected to the +X side of the cross-sectional view in Fig. 9A.

[0069] 6, 7A, and 9B, semiconductor device 1 includes chip 40. Chip 40 has a first main surface (top surface) 40a, a second main surface (bottom surface) 40b on the opposite side, and four side surfaces 40c to 40f connecting the first and second main surfaces 40a and 40b. In plan view, first main surface 40a and second main surface 40b have two sides parallel to the X direction and two sides parallel to the Y direction, and are formed into a rectangular shape that is long in the X direction.

[0070] The chip 40 is ＋ a type semiconductor substrate 41 and an n-type semiconductor layer formed on the semiconductor substrate 41; ＋The semiconductor device includes a n-type buffer layer 42 and an n-type epitaxial layer 43 formed on the buffer layer 42 .

[0071] In this embodiment, the semiconductor substrate 41 is ＋ The substrate may be a semiconductor substrate (e.g., a silicon substrate) of the same type. Alternatively, a substrate that is generally used for transistors, such as a SiC substrate or a GaN substrate, may be used.

[0072] Examples of p-type impurities that can be used include B (boron), Al (aluminum), and Ga (gallium). Examples of n-type impurities that can be used include P (phosphorus), As (arsenic), Sb (antimony), and H (hydrogen).

[0073] p ＋ The impurity concentration of the semiconductor substrate 41 is, for example, 1×10 １８ cm －３ ~1 x 10 ２０ cm －３ Examples of p-type impurities are as described above.

[0074] The buffer layer 42 is, for example, p ＋ On the semiconductor substrate 41, an n-type impurity is implanted and epitaxially grown. － Examples of n-type impurities are as described above.

[0075] The epitaxial layer 43 is, for example, ＋ Alternatively, the n-type epitaxial layer 43 may be an n-type layer epitaxially grown on the n-type buffer layer 42 while implanting n-type impurities. Examples of n-type impurities are as described above. The impurity concentration of the n-type epitaxial layer 43 is lower than that of the buffer layer 42. The n-type region in the epitaxial layer 43 may be referred to as an n-type drift region 43A.

[0076] The semiconductor device 1 includes a collector electrode 18 that covers the second main surface 40b of the chip 40. The collector electrode 18 forms an ohmic contact with the semiconductor substrate 41.

[0077] The cross-sectional structure of the semiconductor device 1 in the active region 2 will be described with reference to FIG.

[0078] In the active region 2, a plurality of IGBT element structures 44 are formed in the surface layer portion (surface layer portion of the epitaxial layer 43) on the first main surface 40a side of the chip 40. The IGBT element structures 44 are p ＋ a body region 45 of the n-type; ＋＋ a p-type emitter region 46; ＋＋ and a body contact region 47 of the same.

[0079] A plurality of body regions 45 are formed in the surface layer portion of the epitaxial layer 43. In this embodiment, the body regions 45 are strip-shaped and long in the Y direction in plan view. In this embodiment, the body regions 45 are arranged in stripes spaced apart in the X direction in plan view.

[0080] The body region 45 may be a p-type semiconductor layer formed by ion-implanting p-type impurities into the n-type epitaxial layer 43. Examples of p-type impurities are as described above. The impurity concentration of the body region 45 is, for example, 1×10 １６ cm －３ ~1 x 10 １８ cm －３ It may be to some extent.

[0081] The emitter region 46 is formed in an inner region of the body region 45. The emitter region 46 is selectively formed in the surface portion of the body region 45 in this inner region. The emitter region 46 may be formed by selectively ion-implanting n-type impurities into the body region 45. Examples of n-type impurities are as described above. The impurity concentration of the emitter region 46 is higher than that of the drift region 43A, for example, 1×10 １８ cm －３ ~1 x 10 ２０ cm －３ It may be to some extent.

[0082] The emitter region 46 extends in the Y direction in plan view and is spaced a predetermined distance inward from the periphery of the body region 45 (the boundary between the body region 45 and the drift region 43A). As a result, in the surface portion of the epitaxial layer 43 including the drift region 43A and the body region 45, the surface portion of the body region 45 is interposed between the emitter region 46 and the drift region 43A. The surface portion of the body region 45 interposed between the emitter region 46 and the drift region 43A is a channel region 48 in which a channel is formed when an appropriate voltage is applied to the gate electrode 28, which will be described later.

[0083] The body contact region 47 extends in the Y direction in plan view, and is selectively formed in the surface layer portion of the body region 45. The body contact region 47 extends toward the buffer layer 42 so as to pass through the emitter region 46 and reach the body region 45. The body contact region 47 may be formed by selectively ion-implanting p-type impurities into the body region 45. Examples of p-type impurities are as described above. The impurity concentration of the body contact region 47 is higher than that of the body region 45, for example, 1×10 １８ cm －３ ~1 x 10 ２０ cm －３ It may be to some extent.

[0084] The body region 45 , the emitter region 46 and the body contact region 47 form an IGBT element structure 44 .

[0085] A main surface insulating film 49 is selectively formed on the first main surface 40a of the chip 40. The main surface insulating film 49 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, or a tantalum oxide film.

[0086] Hereinafter, of the main surface insulating film 49 formed on the first main surface 40 a of the chip 40 , the main surface insulating film 49 on which the gate electrode 50 described later is formed will be referred to as the gate insulating film 49 .

[0087] The gate insulating film 49 covers at least the surface of the body region 45. In this embodiment, the gate insulating film 49 covers part of the surface of the emitter region 46, the surfaces of the channel region 48, and the drift region 43A.

[0088] In this embodiment, the gate insulating film 49 has a belt shape extending in the Y direction in a plan view, and is formed in stripes spaced apart in the X direction.

[0089] A gate electrode 50 is formed on the gate insulating film 49. The gate electrode 50 faces the channel region 48 via the gate insulating film 49. The gate electrode 50 is formed in substantially the same pattern as the gate insulating film 49. In this embodiment, the gate electrodes 50 are formed in stripes spaced apart in the X direction, thereby forming a planar gate structure.

[0090] Both ends of the gate electrode 50 in the Y direction are connected to the gate wiring 22. In this embodiment, the gate electrode 50 includes conductive polysilicon. In this embodiment, the gate electrode 50 is formed integrally with the gate wiring 22.

[0091] An interlayer insulating film 51 is formed on the epitaxial layer 43. The interlayer insulating film 51 covers the gate electrode 50. The interlayer insulating film 51 may be made of an insulating material such as a silicon oxide film, a silicon nitride film, or TEOS (tetraethoxysilane).

[0092] A first contact hole 52 exposing the body contact region 47 and the emitter region 46 is formed in the interlayer insulating film 51. The first contact hole 52 penetrates the interlayer insulating film 51 and the gate insulating film 49.

[0093] An emitter electrode 4 is formed on the interlayer insulating film 51. The emitter electrode 4 may be made of aluminum or another metal. The emitter electrode 4 is connected to the body contact region 47 and the emitter region 46 within the first contact hole 52.

[0094] The cross-sectional structure of semiconductor device 1 in peripheral region 3 will be described with reference to FIGS. 7A to 7C, 8, 9A and 9B.

[0095] 4, 5, 7A, and 9B, in the peripheral portion of the outer peripheral region 3, the surface layer portion on the first main surface 40a side of the chip 40 (the surface layer portion of the epitaxial layer 43) has n ＋＋ A channel stopper region 61 having an n-type impurity concentration higher than that of the drift region 43A is formed in the first major surface 40a. The channel stopper region 61 is formed along the periphery of the first major surface 40a and has a ring shape (a square ring shape in this embodiment) in a plan view. The channel stopper region 61 has a higher n-type impurity concentration than that of the drift region 43A. The channel stopper region 61 may have the same n-type impurity concentration as that of the emitter region 46.

[0096] In the peripheral region 3, a main surface insulating film (hereinafter referred to as the "first main surface insulating film 49") is formed on the first main surface 40a of the chip 40 at a distance from the outer peripheral edge of the first main surface 40a of the chip 40. The first main surface insulating film 49 is formed along the outer peripheral edge of the first main surface 40a of the chip 40. The first main surface insulating film 49 is formed in a ring shape (a quadrangular ring shape in this embodiment) in a planar view. The outer peripheral edge of the first main surface insulating film 49 is located at a distance outward from the inner peripheral edge of the channel stopper region 61 in a planar view. The inner peripheral edge of the first main surface insulating film 49 is located at a distance inward from the inner peripheral edge of the channel stopper region 61 in a planar view.

[0097] A field insulating film 53 is formed on the first main surface 40a of the chip 40 in a region inward of the first main surface insulating film 49 in the peripheral region 3. The field insulating film 53 is formed along the inner peripheral edge of the first main surface insulating film 49. The outer peripheral edge of the field insulating film 53 is connected to the inner peripheral edge of the first main surface insulating film 49. The field insulating film 53 is made of, for example, a local oxidation of silicon (LOCOS) oxide film. The film thickness of the field insulating film 53 is thicker than that of the first main surface insulating film 49.

[0098] EQR wiring 21 is formed on first main surface insulating film 49 and field insulating film 53 so as to cover the entire surface of first main surface insulating film 49 and a portion of the surface of field insulating film 53 closer to first main surface insulating film 49. A plurality of field plates 29 are arranged at intervals on field insulating film 53 in a region inward of EQR wiring 21.

[0099] In the peripheral region 3, an interlayer insulating film 51 is formed on the first main surface 40a of the chip 40, covering the exposed surface of the first main surface 40a, the EQR wiring 21, the exposed surface of the field insulating film 53, the field plate 29, etc. An opening 55 is formed in the interlayer insulating film 51, exposing a portion of the surface of the channel stopper region 61 and exposing the peripheral edge of the surface of the EQR wiring 21. The opening 55 has a ring shape (a quadrangular ring shape in this embodiment) in a plan view, and is formed along the peripheral edge of the first main surface 40a.

[0100] The EQR electrode 7 is formed on the first main surface 40a of the chip 40 so as to cover the opening 55 and the EQR wiring 21. A part of the EQR electrode 7 enters the opening 55 and is electrically connected to the channel stopper region 61 and the EQR wiring 21 within the opening 55. The EQR wiring 21 functions as a part of the EQR electrode 7.

[0101] The portion of the EQR electrode 7 that extends into the opening 55 is referred to as a contact 56. The contact 56 is an example of a “second contact” in this disclosure. The EQR electrode 7 is electrically connected to the collector electrode 18 via the channel stopper region 61, the drift region 43A, the buffer layer 42, and the semiconductor substrate 41.

[0102] The exposed surfaces of the EQR electrode 7 , the plurality of field plates 29 and the interlayer insulating film 51 are covered with a passivation film 13 .

[0103] 4, 7A, 7B, 7C, 8, and 9A, in the outer periphery region 3, the field insulating film 53 extends from below the inner periphery of the EQR wiring 21 to below the center of the width of the gate finger 6 (below the center of the width of the protrusion 5B).

[0104] A p-type well region 62 is formed in the surface portion (surface portion of the epitaxial layer 43) on the first main surface 40a side of the chip 40 at the boundary between the peripheral region 3 and the active region 2. The p-type well region 62 includes a portion formed in almost the entire region below the gate pad 5, a portion formed in almost the entire region below the gate fingers 6, a portion formed in the region below the peripheral edge of the emitter electrode 4, a portion formed in the region between the gate pad 5 and the emitter electrode 4, and a portion formed in the region between the gate fingers 6 and the emitter electrode 4.

[0105] A main surface insulating film 49 (hereinafter referred to as the "second main surface insulating film 49") having a quadrangular ring shape in plan view is formed on the first main surface 40a of the chip 40 at the boundary between the outer periphery region 3 and the active region 2. The outer peripheral edge of the second main surface insulating film 49 is connected to the inner peripheral edge of the field insulating film 53. The inner peripheral edge of the second main surface insulating film 49 extends beyond the boundary between the outer periphery region 3 and the active region 2 into the active region 2. Both ends of the gate insulating film 49 in the Y direction are connected to the inner edges of the second main surface insulating film 49. In this embodiment, the second main surface insulating film 49 and the gate insulating film 49 are formed integrally.

[0106] The gate wiring 22 is formed on the field insulating film 53 and the second main surface insulating film 49, straddling the field insulating film 53 and the second main surface insulating film 49 (see FIGS. 7B, 8, and 9A). The gate wiring 22 is covered with an interlayer insulating film 51. The protrusion 5B and the gate finger 6 of the gate pad 5 are formed on the interlayer insulating film 51.

[0107] A second contact hole 63 (see FIG. 7B ) penetrating the interlayer insulating film 51 is formed in the interlayer insulating film 51 between the protruding portion 5B of the gate pad 5 and the gate wiring 22. In this embodiment, a part of the gate pad 5 enters the second contact hole 63 and is electrically connected to the gate wiring 22 within the second contact hole 63. The part of the gate pad 5 that enters the second contact hole 63 forms the contact 23.

[0108] A third contact hole 64 (see FIGS. 8 and 9A ) penetrating the interlayer insulating film 51 is formed between the gate finger 6 and the gate wiring 22 in the interlayer insulating film 51. The third contact hole 64 has a ring shape (a square ring shape in this embodiment) in a plan view. In this embodiment, a part of the gate finger 6 enters the third contact hole 64 and is electrically connected to the gate wiring 22 inside the third contact hole 64. The part of the gate finger 6 that enters the third contact hole 64 forms the contact 24.

[0109] 4 and 7C , the first diode forming body 26 is formed on the second main surface insulating film 49. The first diode forming body 26 extends from below the main portion 5A of the gate pad 5 to the peripheral edge of the first recess 8 in the emitter electrode 4. The first diode forming body 26 faces the p-type well region 62. The first diode forming body 26 is covered with the interlayer insulating film 51. The main portion 5A of the gate pad 5 and the peripheral edge of the first recess 8 in the emitter electrode 4 are formed on the interlayer insulating film 51.

[0110] A fourth contact hole 65 is formed in the interlayer insulating film 51 between the main portion 5A of the gate pad 5 and the first diode forming body 26. In this embodiment, a part of the gate pad 5 enters the fourth contact hole 65 and is electrically connected to the first diode forming body 26 within the fourth contact hole 65. The part of the gate pad 5 that enters the fourth contact hole 65 forms the contact 25.

[0111] A fifth contact hole 66 is formed in the interlayer insulating film 51 between the periphery of the first recess 8 in the emitter electrode 4 and the first diode forming body 26. In this embodiment, a part of the emitter electrode 4 extends into the fifth contact hole 66 and is electrically connected to the first diode forming body 26 within the fifth contact hole 66. The part of the emitter electrode 4 that extends into the fifth contact hole 66 forms a contact 27.

[0112] A first Zener diode 102 is formed in the first diode-forming body 26 in a region between a location where the contact 25 is connected and a location where the contact 27 is connected. The first Zener diode 102 is formed by forming a plurality of n-type regions 26n and p-type regions 26p alternately in the X direction in the first diode-forming body 26. Specifically, the first Zener diode 102 is formed by connecting a plurality of series-connected structures (pn-connected structures) of the n-type regions 26n and the p-type regions 26p in series. One end of the first Zener diode 102 is electrically connected to the main portion 5A of the gate pad 5 via the contact 25, and the other end of the first Zener diode 102 is electrically connected to the emitter electrode 4 via the contact 27.

[0113] Note that the widths (lengths in the X direction) of n-type regions 26n and p-type regions 26p shown in Fig. 7C do not represent actual widths. Furthermore, the number of n-type regions 26n and p-type regions 26p is not limited to the number shown in Fig. 7C and can be set arbitrarily.

[0114] The protruding portion 5 B of the gate pad 5 , the peripheral edge of the main portion 5 A of the gate pad 5 , and the area of ​​the emitter electrode 4 excluding the central portion are covered with a passivation film 13 .

[0115] 5 , 9A and 9B , the second diode forming body 30 is formed on the field insulating film 53 and on the second main surface insulating film 49 to which the inner edge of the field insulating film 53 is connected. The second diode forming body 30 extends from below the peripheral edge of the emitter electrode 4 facing the straight line portion 6E of the gate finger 6, passing below the straight line portion 6E, to below the fourth straight line portion 7D of the EQR electrode 7.

[0116] As described above, the second diode forming body 30 is composed of a main portion 30A, a first extension portion 30B, and a second extension portion 30C. A portion of the first extension portion 30B is formed by a portion of the gate wiring 22. A portion of the second extension portion 30C is formed by a portion of the EQR wiring 21.

[0117] The second diode forming body 30 is covered with an interlayer insulating film 51. The interlayer insulating film 51 has formed therein a third contact hole 64 that exposes a portion of the first extension 30B (gate wiring 22) and an opening 55 that exposes a portion of the second extension 30C (EQR wiring 21).

[0118] The first extension 30B is electrically connected to the straight portion 6E of the gate finger 6 via a contact 24 in a third contact hole 64. The second extension 30C is electrically connected to the EQR electrode 7 via a contact 56 in an opening 55.

[0119] The region in the second diode-forming body 30 between the location where the contact 24 is connected and the location where the contact 56 is connected is a second diode region 31 that constitutes the second diode 103. Therefore, one end of the second diode 103 is electrically connected to the gate finger 6 via the contact 24, and the other end of the second diode 103 is electrically connected to the collector electrode 18 via the contact 56 and the EQR electrode 7.

[0120] The second Zener diode 103 is formed by forming a plurality of n-type regions 30n and p-type regions 30p alternately in the X direction in the second diode-forming body 30. Specifically, the second Zener diode 103 is configured by connecting a plurality of series-connected structures (pn junction structures) of n-type regions 30n and p-type regions 30p in series. It is preferable that 10 or more pn junction structures each consisting of an n-type region 30n and a p-type region 30p are connected in series.

[0121] 9A and 9B do not represent the actual widths (lengths in the X direction). The number of n-type regions 30n and p-type regions 30p is not limited to the number shown in FIGS. 9A and 9B, and can be set arbitrarily.

[0122] Hereinafter, the length of the second diode region 31 in the X direction will be referred to as the diode arrangement length L. The diode arrangement length L may also be referred to as the diode length L. The diode arrangement length L is equal to the distance between the contact 24 and the contact 56 in the X direction.

[0123] The length of the second diode region 31 in the Y direction is referred to as the diode arrangement width W. The diode arrangement width W may also be referred to as the diode width W. The diode arrangement width W is equal to the length of the main portion 30A of the second diode forming body 30 in the Y direction.

[0124] In this embodiment, the diode arrangement length L is 581 μm and the diode width W is 910 μm. Therefore, the ratio W / L of the diode arrangement width W to the diode arrangement length L is 1.57.

[0125] [Special Operation Test] Three samples S1, S2, and S3 were prepared, each with a constant diode arrangement length L and different diode arrangement widths W, and a special operation test was conducted. The special operation test involved connecting the collector of the sample's IGBT to the primary winding of the ignition coil, grounding the IGBT's emitter, and simulating the high-frequency, high-voltage noise of several tens of kV generated during secondary ignition flowing into the IGBT's collector via parasitic capacitance formed between the primary and secondary windings wound around the iron core in the ignition coil. More specifically, the special operation test involved adding a capacitor between the primary and secondary sides of the ignition coil, causing the secondary voltage to leak into the primary side and apply a load to the IGBT.

[0126] FIG. 10 is a table showing the diode arrangement length L, the diode arrangement width W, and the ratio W / L of the diode arrangement width W to the diode arrangement length L for each of the samples S1, S2, and S3.

[0127] FIG. 11 is a table showing the evaluation results of the special operation test.

[0128] 11, it can be seen that the absolute values ​​of the secondary breakdown voltages for samples S2 and S3 are larger than the absolute value of the secondary breakdown voltage for sample S1. It can also be seen that the absolute value of the secondary breakdown voltage for sample S3 is equal to or larger than the absolute value of the secondary breakdown voltage for sample S2.

[0129] That is, it can be seen that the absolute value of the secondary breakdown voltage increases when the diode arrangement width W is increased. The reason for this is thought to be that when the diode arrangement width W is increased, the parasitic resistance of the second diode 103 decreases, and the second Zener diode 103 is able to transiently respond even to a high-frequency surge with a pulse width of several tens of nanoseconds.

[0130] For these reasons, in order to suppress bulk breakdown due to high-frequency surges, it is preferable that the ratio W / L of the diode arrangement width W to the diode arrangement length L be 1.3 or greater, that is, greater than 0.96, and more preferably 1.57 or greater.

[0131] Furthermore, in order to suppress bulk breakdown due to high-frequency surges, when the diode arrangement length L is approximately 550 μm or more and 610 μm or less, it is preferable that the diode arrangement length L be 750 μm or more, and more preferably 910 μm or more.

[0132] Although the embodiments of the present disclosure have been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0133] The following characteristics can be extracted from the description of this specification and the drawings.

[0134] [Supplementary Note 1-1] A chip (40) having a first main surface (40a) and a second main surface (40b) opposite thereto; an emitter electrode (4) disposed on the first main surface (40a); a gate pad (5) disposed on the first main surface (40a) on the outer periphery of the emitter electrode (4); a gate finger (6) disposed on the first main surface (40a) on the outer periphery of the emitter electrode (4), electrically connected to the gate pad (5), and having a diode-connecting linear portion (6E) extending in a predetermined first direction (Y direction) along the first main surface (40a); and a collector electrode (18) disposed on the second main surface (40b). a diode-connecting electrode (7) disposed on the first main surface (40a), spaced apart from the diode-connecting straight line segment (6E) in a second direction (X direction) that is a direction along the first main surface (40a) and perpendicular to the first direction (Y direction), and electrically connected to the collector electrode (18); and a diode-forming body (30) including a Zener diode (103) having one end electrically connected to the diode-connecting straight line segment (6E) via a first contact (24) and the other end electrically connected to the diode-connecting electrode (7) via a second contact (56), a diode arrangement length (L) representing the length of the Zener diode (103) in the second direction (X direction) from one end to the other end, and a diode arrangement width (W) representing the length of the Zener diode (103) in the first direction (Y direction), wherein a ratio (W / L) of the diode arrangement width (W) to the diode arrangement length (L) is 1.3 or more.

[0135] [Appendix 1-2] The semiconductor device according to [Appendix 1-1], wherein a ratio (W / L) of the diode arrangement width (W) to the diode arrangement length (L) is 1.57 or more.

[0136] [Supplementary Note 1-3] A chip (40) having a first main surface (40a) and a second main surface (40b) opposite thereto; an emitter electrode (4) disposed on the first main surface (40a); a gate pad (5) disposed on the first main surface (40a) on the outer periphery of the emitter electrode (4); a gate finger (6) disposed on the first main surface (40a) on the outer periphery of the emitter electrode (4), electrically connected to the gate pad (5), and having a diode-connecting linear portion (6E) extending in a predetermined first direction (Y direction) along the first main surface (40a); and a collector electrode (18) disposed on the second main surface (40b). a diode-connecting electrode (7) disposed on the first main surface (40a), spaced apart from the diode-connecting straight line segment (6E) in a second direction (X direction) that is a direction along the first main surface (40a) and perpendicular to the first direction (Y direction), and electrically connected to the collector electrode (18); and a diode-forming body (30) including a Zener diode (103) having one end electrically connected to the diode-connecting straight line segment (6E) via a first contact (24) and the other end electrically connected to the diode-connecting electrode (7) via a second contact (56), The length of the Zener diode (103) in the second direction (X direction) from one end to the other end is defined as a diode arrangement length (L), and the length of the Zener diode (103) in the first direction (Y direction) is defined as a diode arrangement width (W), wherein the diode arrangement length (L) is 550 μm or more and 610 μm or less, and the diode arrangement width (W) is 750 μm or more.

[0137] [Appendix 1-4] The semiconductor device according to [Appendix 1-3], wherein the diode arrangement length (L) is 550 μm or more and 610 μm or less, and the diode arrangement width (W) is 910 μm or more.

[0138] [Appendix 1-5] The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-4], wherein the diode arrangement length (L) is the length in the second direction (X direction) between a point where the first contact (24) in the diode forming body (30) is connected and a point where the second contact (56) in the diode forming body (30) is connected.

[0139] [Appendix 1-6] The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-5], wherein the diode forming body (30) is made of conductive polysilicon, the diode forming body (30) includes a diode region (31) in which a plurality of n-type regions (30n) and p-type regions (30p) are formed alternately in the second direction (X direction) between a location in the diode forming body (30) where the first contact (24) is connected and a location in the diode forming body (30) where the second contact (56) is connected, and the Zener diode (103) is constituted by the diode region (31) in the diode forming body (30).

[0140] [Appendix 1-7] The semiconductor device according to [Appendix 1-6], wherein the diode region (31) has 10 or more series-connected structures of the n-type region (30n) and the p-type region (30p) connected in series.

[0141] [Appendix 1-8] The semiconductor device according to any one of [Appendix 1-1] to [Appendix 1-7], including: an active region (2) provided in an inner portion of the first main surface (40a) and having an IGBT element structure (44) formed therein; and a peripheral region (3) provided outside the active region (2) of the first main surface (40a), wherein the emitter electrode (4) is arranged in the active region (2), and the gate pad (5), the gate finger (6), and the diode connection electrode (7) are arranged in the peripheral region (3).

[0142] [Supplementary Note 1-9] The first main surface (40a) has a quadrangular shape in plan view having two sides parallel to the first direction (Y direction) and two sides parallel to the second direction (X direction), the emitter electrode (4) has a quadrangular shape in plan view having two sides parallel to the first direction (Y direction) and two sides parallel to the second direction (X direction), the emitter electrode (4) has a first recess (8) on one of the two sides parallel to the first direction (Y direction) that is recessed toward the other side, and a second recess (9) on the other side that is recessed toward the one side, The gate pad (5) is arranged in the first recess (8) and has a rectangular main portion (5A) having two sides parallel to the first direction (Y direction) and two sides parallel to the second direction (X direction), and a protrusion (5B) protruding outward from the center of the length of the outer side of the two sides of the main portion parallel to the first direction (Y direction). This is the conductor device described in [Appendix 1-8].

[0143] [Appendix 1-10] The conductor device according to [Appendix 1-9], wherein the gate finger (6) has one end (6A) spaced apart in the first direction (Y direction) from one side edge of the protrusion (5B), the other end (6B) spaced apart in the first direction (Y direction) from the other side edge of the protrusion (5B), and an intermediate portion that is between the one end (6A) and the other end (6B) in a plan view and extends along the outer circumferential edge of the emitter electrode (4), and the diode-connecting straight portion (6E) is constituted by a straight portion that faces a bottom surface of the second recess (9) in the intermediate portion.

[0144] [Appendix 1-11] The semiconductor device according to [Appendix 1-10], wherein an EQR electrode (7) having a ring shape in a planar view and arranged along an outer periphery of the first main surface (40 a) is formed on the first main surface (40 a) in a region outside the gate finger (6) in the outer periphery region (3), and the diode connection electrode (7) is the EQR electrode.

[0145] [Supplementary Note 1-12] The EQR electrode (7) includes a first linear portion (7A) and a third linear portion (7C) that are two linear portions parallel to the second direction (X direction), and a second linear portion (7B) and a fourth linear portion (7D) that are two linear portions parallel to the first direction (Y direction), and if the linear portion of the second linear portion (7B) and the fourth linear portion (7D) that is on the second recess (9) side is defined as the fourth linear portion (7D), The semiconductor device described in [Appendix 1-11], wherein the diode forming body (30) includes a diode forming body main portion (30A) that is arranged between the diode connection straight portion (6E) and the fourth straight portion (7D) in a planar view, a first extension portion (30B) that extends inward from an edge of the diode forming body main portion (30A) on the diode connection straight portion (6E) side, and a second extension portion (30C) that extends outward from an edge of the diode forming body main portion (30A) on the fourth straight portion (7D) side.

[0146] [Appendix 1-13] The semiconductor device according to [Appendix 1-12], wherein the first extension portion (30B) is electrically connected to the diode connection straight portion (6E) via the first contact (24), and the second extension portion (30C) is electrically connected to the fourth straight portion (7D) via the second contact (56).

[0147] [Appendix 1-14] The semiconductor device according to [Appendix 1-13], further comprising: a gate wiring (22) that is annular in plan view and is disposed on the first main surface (40a) so as to pass below the protrusion of the gate pad (5) and below the gate finger (6); and an EQR wiring (21) that is annular in plan view and is disposed on the first main surface (40a) so as to pass below the EQR electrode (21), wherein the first extension (30B) includes a portion of the gate wiring (22), and the second extension (30C) includes a portion of the EQR wiring (21).

[0148] [Supplementary Note 1-15] The gate wiring (22) is disposed on the first main surface (40a) so as to pass below the protruding portion (5B) of the gate pad (5) and below the gate finger (6), and is annular in plan view, the protruding portion (5B) is electrically connected to the gate wiring (22) via a third contact (23), an intermediate portion of the length between both ends of the gate finger (6) is electrically connected to the gate wiring (22) via a fourth contact (24) which has an annular shape with ends in plan view, a first gate resistor (R1) is formed by a region between a portion of the gate wiring (22) to which the third contact (23) is connected and a portion of the gate wiring (22) to which one end of the fourth contact (24) is connected, The semiconductor device according to [Appendix 1-10], wherein a second gate resistor (R2) is formed by a region between a portion of the gate wiring (22) to which the third contact (23) is connected and a portion of the gate wiring (22) to which the other end of the fourth contact (24) is connected.

[0149] [Appendix 1-16] The semiconductor device according to [Appendix 1-15], wherein the gate pad (5) is electrically connected to the gate finger (6) via a parallel circuit of the first gate resistor (R1) and the second gate resistor (R2).

[0150] [Appendix 1-17] The semiconductor device according to [Appendix 1-15], wherein the chip (40) includes an n-type semiconductor layer (43) on the first main surface (40a) side, and the IGBT element structure (44) includes: a plurality of p-type body regions (45) formed in a surface layer portion of the n-type semiconductor layer (43) at intervals in the second direction (X direction); and an n-type emitter region (46) formed in an inner region of the p-type body region (45).

[0151] [Appendix 1-18] The semiconductor device according to [Appendix 1-17], including: a gate insulating film (49) formed on the first main surface (40a) and arranged so as to straddle two of the body regions (45) adjacent in one direction; and a gate electrode (50) formed on the gate insulating film (49), the gate electrode (50) being electrically connected to the gate wiring (22).

[0152] [Appendix 1-19] The semiconductor device according to [Appendix 1-18], wherein the gate wiring (22) and the gate electrode (50) are integrally formed.

[0153] REFERENCE SIGNS LIST 1 semiconductor device 2 active region 3 peripheral region 4 emitter electrode 5 gate pad 5A main portion 5B protruding portion 6 gate finger 6A one end portion 6B other end portion 6C first curved portion 6D second curved portion 6E straight portion 7 EQR electrode 7A first straight portion 7B second straight portion 7C third straight portion 7D fourth straight portion 8 first recess 9 second recess 11 first curved portion 12 second curved portion 13 passivation film 14 first pad opening 15 second pad opening 16 pad portion 17 pad portion 18 collector electrode 21 EQR wiring 22 gate wiring 23 contact (third contact) (gate pad) 24 contact (first contact) (gate finger) 24A one end portion 24B other end portion 25 contact (gate pad) 26 First diode forming body 26n n-type region 26p p-type region 27 Contact (emitter electrode) 29 Field plate 30 Second diode forming body 30A Main portion 30B First extension portion 30C Second extension portion 30n n-type region 30p p-type region 31 Second diode region 40 Chip 40a First main surface 40b Second main surface 40c to 40f Side surface 41 Semiconductor substrate 42 Buffer layer 43 Epitaxial layer 43A Drift region 44 IGBT element structure 45 Body region 46 Emitter region 47 Body contact region 48 Channel region 49 Main surface insulating film (gate insulating film) 50 Gate electrode 51 Interlayer insulating film 52 First contact hole 53 Field insulating film 55 Opening 56 Contact (second contact) (EQR electrode) 61 Channel stopper region 62 p-type well region 63 second contact hole (gate pad) 64 third contact hole (gate finger) 65 fourth contact hole (gate pad) 66 fifth contact hole (emitter electrode) 101 IGBT 102 first Zener diode 103 second Zener diode 104 gate resistor circuit 105 gate terminal electrode R1 first gate resistor R2 second gate resistor

Claims

1. a chip having a first major surface and an opposite second major surface; an emitter electrode disposed on the first major surface; a gate pad disposed on the first main surface and on an outer periphery side of the emitter electrode; a gate finger disposed on the first main surface and on an outer circumferential side of the emitter electrode, electrically connected to the gate pad, and having a linear portion for diode connection extending in a predetermined first direction along the first main surface; a collector electrode disposed on the second major surface; a diode-connecting electrode disposed on the first main surface, spaced apart from the diode-connecting straight portion in a second direction that is a direction along the first main surface and perpendicular to the first direction, and electrically connected to the collector electrode; a diode forming body including a Zener diode, one end of which is electrically connected to the diode connecting linear portion via a first contact and the other end of which is electrically connected to the diode connecting electrode via a second contact; a diode arrangement length, a length of the Zener diode in the second direction from one end to the other end of the Zener diode, and a diode arrangement width, a ratio of the diode arrangement length to the diode arrangement width is 1.3 or more.

2. 2. The semiconductor device according to claim 1, wherein a ratio of said diode arrangement width to said diode arrangement length is 1.57 or greater.

3. a chip having a first major surface and an opposite second major surface; an emitter electrode disposed on the first major surface; a gate pad disposed on the first main surface and on an outer periphery side of the emitter electrode; a gate finger disposed on the first main surface and on an outer circumferential side of the emitter electrode, electrically connected to the gate pad, and having a linear portion for diode connection extending in a predetermined first direction along the first main surface; a collector electrode disposed on the second major surface; a diode-connecting electrode disposed on the first main surface, spaced apart from the diode-connecting straight portion in a second direction that is a direction along the first main surface and perpendicular to the first direction, and electrically connected to the collector electrode; a diode forming body including a Zener diode, one end of which is electrically connected to the diode connecting linear portion via a first contact and the other end of which is electrically connected to the diode connecting electrode via a second contact; a diode arrangement length, the length of the Zener diode in the second direction from one end to the other end of the Zener diode, and a diode arrangement width, the diode arrangement length being 550 μm or more and 610 μm or less, and the diode arrangement width being 750 μm or more.

4. 4. The semiconductor device according to claim 3, wherein the diode arrangement length is 550 [mu]m or more and 610 [mu]m or less, and the diode arrangement width is 910 [mu]m or more.

5. 4. The semiconductor device according to claim 1, wherein the diode arrangement length is a length in the second direction between a point on the diode forming body where the first contact is connected and a point on the diode forming body where the second contact is connected.

6. the diode formation is made of conductive polysilicon; the diode formation includes a diode region in which a plurality of n-type regions and p-type regions are alternately formed in the second direction between a portion of the diode formation to which the first contact is connected and a portion of the diode formation to which the second contact is connected, 4. The semiconductor device according to claim 1, wherein the Zener diode is formed by the diode region in the diode forming body.

7. 7. The semiconductor device according to claim 6, wherein the diode region has 10 or more series-connected structures of the n-type region and the p-type region connected in series.

8. an active region provided in an inner portion of the first main surface and having an IGBT element structure formed therein; a peripheral region provided outside the active region of the first main surface, 4. The semiconductor device according to claim 1, wherein said emitter electrode is disposed in said active region, and said gate pad, said gate finger and said diode-connecting electrode are disposed in said outer periphery region.

9. the first main surface has a quadrilateral shape in a plan view having two sides parallel to the first direction and two sides parallel to the second direction, the emitter electrode has a quadrangular shape in a plan view having two sides parallel to the first direction and two sides parallel to the second direction, the emitter electrode has, on one of two sides parallel to the first direction, a first recess recessed toward the other side, and, on the other side, a second recess recessed toward the one side, 9. The conductor device of claim 8, wherein the gate pad is disposed within the first recess and has a rectangular main portion having two sides parallel to the first direction and two sides parallel to the second direction, and a protrusion protruding outward from the center of the length of the outer side of the two sides of the main portion parallel to the first direction.

10. the gate finger has one end portion spaced apart from one side edge of the protruding portion in the first direction, the other end portion spaced apart from the other side edge of the protruding portion in the first direction, and an intermediate portion that is between the one end portion and the other end portion in a plan view and extends along an outer circumferential edge of the emitter electrode, 10. The conductor device according to claim 9, wherein the diode-connecting straight portion is configured by a straight portion in the intermediate portion that faces a bottom surface of the second recess.

11. an EQR electrode having a ring shape in a plan view and arranged along an outer periphery of the first main surface is formed on the first main surface in a region outside the gate fingers in the outer periphery region, The semiconductor device according to claim 10 , wherein the diode connection electrode is the EQR electrode.

12. the EQR electrode includes two straight line portions, a first straight line portion and a third straight line portion, which are parallel to the second direction, and two straight line portions, a second straight line portion and a fourth straight line portion, which are parallel to the first direction; Of the second linear portion and the fourth linear portion, the linear portion on the second recess side is defined as a fourth linear portion, 12. The semiconductor device according to claim 11, wherein the diode forming body includes: a diode forming body main portion arranged between the diode connection straight portion and the fourth straight portion in a planar view; a first extension portion extending inward from an edge of the diode forming body main portion on the diode connection straight portion side; and a second extension portion extending outward from an edge of the diode forming body main portion on the fourth straight portion side.

13. the first extension portion is electrically connected to the diode-connecting straight portion via the first contact; The semiconductor device according to claim 12 , wherein the second extension portion is electrically connected to the fourth linear portion via the second contact.

14. a gate wiring that is arranged on the first main surface and has a ring shape in a plan view so as to pass below the protruding portion of the gate pad and below the gate fingers; an EQR wiring that is disposed on the first main surface so as to pass under the EQR electrode and has a ring shape in a plan view; the first extension portion includes a part of the gate line, The semiconductor device according to claim 13 , wherein the second extension portion includes a part of the EQR wiring.

15. a gate wiring that is disposed on the first main surface so as to pass under the protruding portion of the gate pad and under the gate finger, and that is annular in plan view; the protrusion is electrically connected to the gate wiring via a third contact, an intermediate portion of the gate finger between both end portions thereof is electrically connected to the gate wiring via a fourth contact having an annular shape with ends in a plan view; a first gate resistor is formed by a region between a portion of the gate wiring to which the third contact is connected and a portion of the gate wiring to which one end of the fourth contact is connected; 11. The semiconductor device according to claim 10, wherein a second gate resistor is formed by a region between a portion of the gate wiring to which the third contact is connected and a portion of the gate wiring to which the other end of the fourth contact is connected.

16. 16. The semiconductor device according to claim 15, wherein the gate pad is electrically connected to the gate finger via a parallel circuit of the first gate resistor and the second gate resistor.

17. the chip includes an n-type semiconductor layer on the first main surface side, The IGBT element structure is a plurality of p-type body regions formed at intervals in the second direction in a surface layer portion of the n-type semiconductor layer; 16. The semiconductor device according to claim 15, further comprising an n-type emitter region formed in an inner region of said p-type body region.

18. a gate insulating film formed on the first main surface and arranged to straddle two of the p-type body regions adjacent in the second direction; a gate electrode formed on the gate insulating film, 18. The semiconductor device according to claim 17, wherein the gate electrode is electrically connected to the gate wiring.

19. 19. The semiconductor device according to claim 18, wherein the gate wiring and the gate electrode are integrally formed.