SiC SEMICONDUCTOR DEVICE

Abstract

This SiC semiconductor device comprises: an SiC chip having a main surface; a channel region formed in a surface layer section of the main surface; a drift region adjacent to the channel region in the surface layer section of the main surface; a gate insulation film having a channel covering section that is formed above the main surface and covers the channel region, and a drift covering section that covers the drift region; a planar gate electrode that is disposed above the channel covering section and faces the channel region via the channel covering section in the vertical direction; and a planar source electrode that is disposed above the drift covering section at an interval from the planar gate electrode so as to face the planar gate electrode in the horizontal direction, and that faces the drift region via the drift covering section in the vertical direction.

Description

SiC semiconductor device

[0001] This application claims priority to Patent Application No. 2022-212614 filed with the Japan Patent Office on December 28, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a SiC semiconductor device.

[0002] Patent Document 1 (US2003 / 0235942A1) discloses a semiconductor device with a lateral MOSFET structure including a gate electrode divided into two parts. In FIG. 6 of Patent Document 1, p-type polysilicon is disposed in the region between the divided gate electrodes. The p-type polysilicon is disposed on the surface of a semiconductor layer as a diffusion source for p-type impurities, and forms a p-type electric field relaxation region on the surface of the semiconductor layer. In FIG. 7 of Patent Document 1, a metal layer is disposed in the region between the divided gate electrodes. The metal layer is disposed on the surface of the semiconductor layer and forms a Schottky junction with the surface of the semiconductor layer.

[0003] US Patent Application Publication No. 2003 / 0235942

[0004] SUMMARY The present disclosure provides a novel SiC semiconductor device.

[0005] The present disclosure provides a SiC semiconductor device including: a SiC chip having a main surface; a channel region formed in a surface layer portion of the main surface; a drift region adjacent to the channel region in the surface layer portion of the main surface; a gate insulating film formed on the main surface and having a channel covering portion covering the channel region and the drift covering portion covering the drift region; a planar gate electrode disposed on the channel covering portion and facing the channel region in a vertical direction via the channel covering portion; and a planar source electrode disposed on the drift covering portion at a distance from the planar gate electrode so as to face the planar gate electrode in a horizontal direction, and facing the drift region in the vertical direction via the drift covering portion.

[0006] The present disclosure provides a SiC semiconductor device including: a SiC chip having a main surface; a first channel region formed in a surface layer portion of the main surface; a second channel region formed in the surface layer portion of the main surface at a distance from the first channel region; a drift region partitioned in a region between the first channel region and the second channel region in the surface layer portion of the main surface; a gate insulating film formed on the main surface and having a first portion covering the first channel region and a second portion covering the second channel region; a planar gate electrode disposed on the first portion and facing the first channel region in a vertical direction via the first portion; and a planar source electrode disposed on the second portion so as to face the planar gate electrode in a horizontal direction and facing the second channel region in the vertical direction via the second portion.

[0007] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of the chip shown in FIG. 1. FIG. 4 is an enlarged plan view showing an example layout of an active region together with a first planar structure according to the first embodiment. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is an enlarged cross-sectional view showing the first planar structure according to the first embodiment. FIG. 7A is an enlarged cross-sectional view showing the first planar structure according to a second embodiment. FIG. 7B is an enlarged cross-sectional view showing the first planar structure according to a third embodiment. FIG. 7C is an enlarged cross-sectional view showing the first planar structure according to a fourth embodiment. FIG. 7D is an enlarged cross-sectional view showing the first planar structure according to a fifth embodiment. FIG. 7E is an enlarged cross-sectional view showing the first planar structure according to a sixth embodiment. FIG. 7F is an enlarged cross-sectional view showing the first planar structure according to a seventh embodiment. FIG. 7G is an enlarged plan view showing the first planar structure according to an eighth embodiment. FIG. 7H is an enlarged plan view showing a first planar structure according to a ninth embodiment. FIG. 7I is an enlarged plan view showing a first planar structure according to a tenth embodiment. FIG. 7J is an enlarged cross-sectional view showing a first planar structure according to an eleventh embodiment. FIG. 8 is a plan view showing a semiconductor device according to a second embodiment. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 8. FIG. 10 is a plan view showing an example layout of the chip shown in FIG. 8. FIG. 11 is an enlarged plan view showing an example layout of active regions together with a second planar structure according to the first embodiment. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 11. FIG. 13 is an enlarged cross-sectional view showing the second planar structure. FIG. 14A is an enlarged cross-sectional view showing the second planar structure according to the second embodiment. FIG. 14B is an enlarged cross-sectional view showing the second planar structure according to the third embodiment. FIG. 14C is an enlarged cross-sectional view showing the second planar structure according to the fourth embodiment. FIG. 14D is an enlarged cross-sectional view showing the second planar structure according to the fifth embodiment. Fig. 14E is an enlarged cross-sectional view showing a second planar structure according to a sixth embodiment. Fig. 15 is an enlarged cross-sectional view showing a main part of a semiconductor device according to a third embodiment. Fig. 16 is an enlarged plan view showing an example of the layout of an active region of a semiconductor device according to a fourth embodiment. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 16.Fig. 18 is an enlarged plan view showing an example of the layout of an active region of a semiconductor device according to a fifth embodiment. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 18. Fig. 20 is an enlarged plan view showing an example of the layout of an active region of a semiconductor device according to a sixth embodiment. Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in Fig. 20. Fig. 22 is a cross-sectional view showing a modified example of a planar insulating film.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a SiC semiconductor device 1A according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of the chip 2 shown in FIG. 1. FIG. 4 is an enlarged plan view showing an example layout of the active region 8 together with a first planar structure 20A according to the first embodiment. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 4. FIG. 6 is an enlarged cross-sectional view showing the first planar structure 20A according to the first embodiment.

[0013] 1 to 6, SiC semiconductor device 1A includes chip 2 including SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0015] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0016] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0017] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0018] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0019] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off-axis direction by the off-axis angle. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off-axis angle.

[0020] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0021] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0022] The SiC semiconductor device 1A includes an n-type drift region 6 formed in a region (surface layer) on the first main surface 3 side of the chip 2. The drift region 6 may also be referred to as a "first semiconductor region," a "drain drift region," a "drain region," or the like. A drain potential as a high potential (first potential) is applied to the drift region 6.

[0023] Drift region 6 is formed in a layer shape extending along first main surface 3, and is exposed from first main surface 3 and first to fourth side surfaces 5A to 5D. In this embodiment, drift region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).

[0024] The SiC semiconductor device 1A includes an n-type drain region 7 formed in a region (surface layer) on the second main surface 4 side in the chip 2. A drain potential is applied to the drain region 7. The drain region 7 may also be referred to as a "second semiconductor region," etc. The drain region 7 has a higher n-type impurity concentration than the drift region 6 and is electrically connected to the drift region 6 in the chip 2.

[0025] The drain region 7 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the drain region 7 is made of a semiconductor substrate (specifically, a SiC substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The drain region 7 has a thickness greater than that of the drift region 6.

[0026] The SiC semiconductor device 1A includes an active region 8 set in the chip 2. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0027] The SiC semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a plan view. The peripheral region 9 extends in a band shape along the active region 8 in a plan view and is set in a polygonal ring shape (a square ring in this embodiment) surrounding the active region 8.

[0028] The SiC semiconductor device 1A includes a plurality of p-type body regions 10 formed in a surface layer portion of the first main surface 3 in the active region 8. A source potential as a low potential (second potential) is applied to the plurality of body regions 10. The plurality of body regions 10 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 10 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. The plurality of body regions 10 are also formed in a strip shape extending in the second direction Y (a-axis direction).

[0029] The SiC semiconductor device 1A includes a plurality of n-type source regions 11A, 11B formed in the surface layer portions of a plurality of body regions 10 in the active region 8. A source potential is applied to the plurality of body regions 10. The plurality of source regions 11A, 11B have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 6.

[0030] In this embodiment, a plurality of source regions 11A, 11B are formed in a surface layer portion of each body region 10. Specifically, the plurality of source regions 11A, 11B include a first source region 11A and a second source region 11B formed in a surface layer portion of each body region 10. In this embodiment, one first source region 11A is formed on one end side of the body region 10, and one second source region 11B is formed on the other end side of the body region 10, in the first direction X.

[0031] The first source regions 11A are formed at intervals from one end to the other end of the body region 10, and extend in a strip shape along the extension direction of the body region 10. When a plurality of first source regions 11A are formed in the body region 10, the plurality of first source regions 11A may be formed at intervals in the extension direction of the body region 10. The first source regions 11A are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the drift region 6 with a part of the body region 10 sandwiched therebetween.

[0032] The second source region 11B is formed at a distance from the first source region 11A toward the other end of the body region 10. The second source region 11B is formed at a distance from the other end of the body region 10 toward one end, and extends in a strip shape along the extension direction of the body region 10. When multiple second source regions 11B are formed in the body region 10, the multiple second source regions 11B may be formed at a distance from each other in the extension direction of the body region 10. The second source region 11B is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the drift region 6 with a part of the body region 10 sandwiched therebetween.

[0033] The SiC semiconductor device 1A includes a plurality of p-type contact regions 12 formed in the surface layer portions of a plurality of body regions 10 in the active region 8. The contact regions 12 may also be referred to as "back gate regions." A source potential is applied to the plurality of contact regions 12. The contact regions 12 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10.

[0034] In this embodiment, one contact region 12 is interposed in a region between adjacent source regions 11A and 11B in the surface layer portion of the corresponding body region 10. That is, each contact region 12 is interposed in a region between the first source region 11A and the second source region 11B in the surface layer portion of each body region 10.

[0035] The contact region 12 extends in a strip shape along the extension direction of the body region 10. When a plurality of contact regions 12 are formed in the body region 10, the plurality of contact regions 12 may be formed at intervals in the extension direction of the body region 10. In this case, each contact region 12 may be formed in a strip shape extending in the second direction Y.

[0036] In the second direction Y, the contact region 12 may be formed at a distance inward from the periphery of the body region 10, or may have a portion that crosses the periphery of the body region 10 and is positioned within the drift region 6. The contact region 12 is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the drift region 6 with a portion of the body region 10 sandwiched therebetween.

[0037] SiC semiconductor device 1A includes a plurality of p-type channel regions 13A, 13B formed in a surface layer portion of first main surface 3. The plurality of channel regions 13A, 13B are defined in the surface layer portions of the plurality of body regions 10 in regions between the peripheries of the plurality of body regions 10 and the peripheries of the plurality of source regions 11A, 11B, respectively.

[0038] In this embodiment, the multiple channel regions 13A, 13B are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple channel regions 13A, 13B are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. The multiple channel regions 13A, 13B are also formed in stripes extending in the second direction Y (a-axis direction).

[0039] Specifically, the plurality of channel regions 13A, 13B include a plurality of first channel regions 13A and a plurality of second channel regions 13B. The plurality of first channel regions 13A are each defined as a region between one end of the plurality of body regions 10 and a region between the plurality of first source regions 11A, and form a current path extending in the horizontal direction. The plurality of second channel regions 13B are each defined as a region between the other end of the plurality of body regions 10 and a region between the plurality of second source regions 11B, and form a current path extending in the horizontal direction.

[0040] The SiC semiconductor device 1A includes a plurality of n-type surface drift regions 14 formed in a surface portion of the first main surface 3. In this embodiment, the plurality of surface drift regions 14 each comprises a portion of the drift region 6. Of course, the plurality of surface drift regions 14 may have a higher n-type impurity concentration than the drift region 6.

[0041] The plurality of surface drift regions 14 are partitioned into regions between adjacent body regions 10, and are interposed between first channel region 13A and second channel region 13B. In the surface portion of first main surface 3, the plurality of surface drift regions 14 form a current path that reaches first source region 11A via first channel region 13A, and a current path that reaches second source region 11B via second channel region 13B.

[0042] In this embodiment, the multiple surface drift regions 14 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple surface drift regions 14 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. The multiple surface drift regions 14 are also formed in stripes extending in the second direction Y (a-axis direction).

[0043] The SiC semiconductor device 1A includes a plurality of first planar structures 20A arranged on the first main surface 3 in the active region 8. Each of the plurality of first planar structures 20A includes a gate insulating film 21 covering the first main surface 3. The gate insulating film 21 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 21 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 21 include a silicon oxide film made of an oxide of the chip 2.

[0044] In this embodiment, the multiple gate insulating films 21 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple gate insulating films 21 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. Furthermore, the extending direction of the multiple gate insulating films 21 coincides with the off-direction of the SiC single crystal.

[0045] Each gate insulating film 21 is arranged to straddle two adjacent body regions 10, and covers the plurality of channel regions 13A, 13B and the surface drift region 14. Specifically, each gate insulating film 21 is arranged to straddle the first source region 11A on one body region 10 side and the second source region 11B on the other body region 10 side, and covers the first source region 11A, the second source region 11B, the first channel region 13A, the second channel region 13B, and the surface drift region 14.

[0046] Each gate insulating film 21 has a first channel covering portion 21A (first portion) that covers the first channel region 13A in a film-like manner, a second channel covering portion 21B (second portion) that covers the second channel region 13B in a film-like manner, and a drift covering portion 21C (third portion) that covers the surface drift region 14 in a film-like manner.

[0047] The first channel covering portion 21A partially covers the first source region 11A at a distance from the contact region 12, and exposes a part of the first source region 11A and the contact region 12 from the first main surface 3. The second channel covering portion 21B partially covers the second source region 11B at a distance from the contact region 12, and exposes a part of the second source region 11B and the contact region 12 from the first main surface 3. The drift covering portion 21C is continuous with the first channel covering portion 21A and the second channel covering portion 21B.

[0048] Each of the plurality of first planar structures 20A includes a planar gate electrode 22 disposed on a gate insulating film 21. A gate potential is applied to the planar gate electrode 22 as a control potential. The planar gate electrode 22 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the planar gate electrode 22 is adjusted according to the gate threshold voltage to be achieved.

[0049] The planar gate electrode 22 is formed in a strip shape on the gate insulating film 21 and extends in the second direction Y. That is, the planar gate electrode 22 extends in the a-axis direction of the SiC single crystal. The extending direction of the planar gate electrode 22 also coincides with the off-direction of the SiC single crystal.

[0050] The planar gate electrode 22 faces the plurality of channel regions 13A, 13B in the vertical direction Z via the gate insulating film 21, and controls inversion and non-inversion of the plurality of channel regions 13A, 13B in response to an external gate potential. Specifically, the planar gate electrode 22 covers the first channel covering portion 21A and the second channel covering portion 21B, and faces the first channel region 13A via the first channel covering portion 21A and the second channel region 13B via the second channel covering portion 21B.

[0051] Planar gate electrode 22 extends from above first channel covering portion 21A onto drift covering portion 21C, and has a portion facing surface drift region 14 via drift covering portion 21C. Planar gate electrode 22 extends from above second channel covering portion 21B onto drift covering portion 21C, and has a portion facing surface drift region 14 via drift covering portion 21C.

[0052] It is preferable that planar gate electrode 22 is formed at a distance from the widthwise intermediate portion of drift covering 21C toward first channel covering 21A, and at a distance from the widthwise intermediate portion of drift covering 21C toward second channel covering 21B. In other words, it is preferable that the area hidden by planar gate electrode 22 relative to drift covering 21C be less than the exposed area of ​​drift covering 21C.

[0053] The area of ​​the planar gate electrode 22 facing the surface drift region 14 may be smaller than the area of ​​the planar gate electrode 22 facing the first channel region 13A. The area of ​​the planar gate electrode 22 facing the surface drift region 14 may be smaller than the area of ​​the planar gate electrode 22 facing the second channel region 13B.

[0054] The planar gate electrode 22 has a through hole 23 that exposes the drift covering 21C. The through hole 23 is formed at a distance inward from the first channel covering 21A and the second channel covering 21B in cross-sectional and plan views. That is, the through hole 23 exposes only the drift covering 21C.

[0055] In this embodiment, the through holes 23 are formed in a band shape extending in the second direction Y in plan view. That is, the through holes 23 extend in the a-axis direction of the SiC single crystal. The extending direction of the through holes 23 coincides with the off-direction of the SiC single crystal. In this embodiment, the through holes 23 are formed spaced apart inward from both end portions of the planar gate electrode 22 in the second direction Y. The through holes 23 divide the planar gate electrode 22 into polygonal ring shapes (quadrilateral rings, specifically rectangular rings, in this embodiment) in plan view.

[0056] The planar area of ​​the through-hole 23 is preferably larger than either or both of the planar area of ​​the first channel region 13A and the planar area of ​​the second channel region 13B. It is particularly preferable that the planar area of ​​the through-hole 23 is larger than the total planar area of ​​the first channel region 13A and the planar area of ​​the second channel region 13B.

[0057] 4 to 6 , the planar gate electrode 22 includes a first electrode portion 22A and a second electrode portion 22B separated by a through hole 23 in a cross-sectional view. The first electrode portion 22A is defined above the first channel covering portion 21A and faces the first channel region 13A in the vertical direction Z via the first channel covering portion 21A. The first electrode portion 22A is formed in a strip shape extending in the second direction Y (a-axis direction) in a plan view.

[0058] The first electrode 22A is extended to the first source region 11A side on the first channel covering 21A, and has a portion facing the first source region 11A via the first channel covering 21A. The first electrode 22A is extended from above the first channel covering 21A onto the drift covering 21C, and has a portion facing the surface drift region 14 via the drift covering 21C.

[0059] First electrode 22A is preferably formed at a distance from the widthwise middle of drift covering 21C toward first channel covering 21A. That is, the area of ​​first electrode 22A hidden by drift covering 21C is preferably less than the exposed area of ​​drift covering 21C. The width of first electrode 22A in first direction X may be less than the width of through hole 23. Of course, the width of first electrode 22A may be greater than the width of through hole 23.

[0060] The first electrode portion 22A is capacitively coupled to the first source region 11A (first channel region 13A) via the first channel covering portion 21A, and is capacitively coupled to the surface drift region 14 via the drift covering portion 21C. The first electrode portion 22A forms a gate-source capacitance Cgs together with the first source region 11A (first channel region 13A), and forms a gate-drain capacitance Cdg together with the surface drift region 14. The gate-drain capacitance Cdg of the first electrode portion 22A is preferably less than the gate-source capacitance Cgs of the first electrode portion 22A.

[0061] The second electrode portion 22B is defined above the second channel covering portion 21B at a distance from the first electrode portion 22A in the horizontal direction (first direction X) and faces the second channel region 13B in the vertical direction Z via the second channel covering portion 21B. The second electrode portion 22B is formed in a strip shape extending in the second direction Y (a-axis direction) in a plan view. The second electrode portion 22B extends approximately parallel to the first electrode portion 22A in a plan view.

[0062] The second electrode 22B is extended to the second source region 11B side on the second channel covering 21B, and has a portion facing the second source region 11B via the second channel covering 21B. The second electrode 22B is extended from above the second channel covering 21B onto the drift covering 21C, and has a portion facing the surface drift region 14 via the drift covering 21C.

[0063] Second electrode 22B is preferably formed at a distance from the widthwise middle of drift covering 21C toward second channel covering 21B. In other words, the area hidden by second electrode 22B relative to drift covering 21C is preferably less than the exposed area of ​​drift covering 21C.

[0064] The second electrode portion 22B is capacitively coupled to the second source region 11B (second channel region 13B) via the second channel covering portion 21B, and is capacitively coupled to the surface drift region 14 via the drift covering portion 21C. The second electrode portion 22B forms a gate-source capacitance Cgs together with the second source region 11B (second channel region 13B), and forms a gate-drain capacitance Cdg together with the surface drift region 14. The gate-drain capacitance Cdg of the second electrode portion 22B is preferably less than the gate-source capacitance Cgs of the second electrode portion 22B.

[0065] In the first direction X, the width of the second electrode portion 22B may be approximately equal to the width of the first electrode portion 22A. The width of the second electrode portion 22B may be less than the width of the first electrode portion 22A. The width of the second electrode portion 22B may be greater than the width of the first electrode portion 22A. The width of the second electrode portion 22B may be less than the width of the through-hole 23. The width of the second electrode portion 22B may be greater than the width of the through-hole 23.

[0066] The second electrode portion 22B does not necessarily have to have the same conductivity type as the first electrode portion 22A. The conductivity type of the second electrode portion 22B may be the same as or different from the conductivity type of the first electrode portion 22A. For example, the first electrode portion 22A may include n-type conductive polysilicon, while the second electrode portion 22B may include p-type conductive polysilicon. For example, the first electrode portion 22A may include p-type conductive polysilicon, while the second electrode portion 22B may include n-type conductive polysilicon.

[0067] Of course, if the first electrode portion 22A includes n-type and p-type regions formed in conductive polysilicon in a first layout, the second electrode portion 22B may include n-type and p-type regions formed in conductive polysilicon in a second layout similar to the first layout. Of course, the second layout may be different from the first layout.

[0068] Each of the first planar structures 20A includes an intermediate insulating film 24 that covers the drift covering portion 21C in the through-hole 23. The intermediate insulating film 24 may include the same insulating material as the gate insulating film 21, or may include an insulating material different from that of the gate insulating film 21. The intermediate insulating film 24 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the intermediate insulating film 24 has a single-layer structure made of a silicon oxide film.

[0069] Intermediate insulating film 24 extends horizontally along drift covering portion 21C to cover drift covering portion 21C in a film-like manner, and has a portion that contacts the wall surface of planar gate electrode 22. Specifically, intermediate insulating film 24 contacts the wall surface of first electrode portion 22A and the wall surface of second electrode portion 22B within through hole 23.

[0070] Intermediate insulating film 24 is formed at a distance from first channel region 13A and second channel region 13B in the horizontal direction. Therefore, intermediate insulating film 24 faces surface drift region 14 in vertical direction Z via drift covering portion 21C, but does not face first channel region 13A or second channel region 13B in vertical direction Z.

[0071] The intermediate insulating film 24 has a thickness less than that of the planar gate electrode 22, and is formed at a distance from the electrode surface of the planar gate electrode 22 toward the gate insulating film 21. The intermediate insulating film 24 may have a thickness greater than that of the gate insulating film 21. The intermediate insulating film 24 may have a thickness less than that of the gate insulating film 21.

[0072] Each of the first planar structures 20A includes an isolation insulating film 25 that covers the wall surface of the planar gate electrode 22 in the through hole 23. The isolation insulating film 25 may include the same insulating material as the gate insulating film 21, or may include an insulating material different from that of the gate insulating film 21.

[0073] The isolation insulating film 25 may contain the same insulating material as the intermediate insulating film 24, or may contain an insulating material different from that of the intermediate insulating film 24. The isolation insulating film 25 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the isolation insulating film 25 has a single-layer structure made of a silicon oxide film.

[0074] The isolation insulating film 25 extends in the vertical direction Z along the wall surface of the planar gate electrode 22, and coats the wall surface of the planar gate electrode 22 in a film-like manner. The isolation insulating film 25 is disposed on the drift covering portion 21C, and has a portion facing the surface drift region 14 in the vertical direction Z via the drift covering portion 21C. The isolation insulating film 25 is connected to the gate insulating film 21 (drift covering portion 21C) and the intermediate insulating film 24 on the lower end side of the planar gate electrode 22.

[0075] Specifically, the isolation insulating film 25 extends in the vertical direction Z along the wall surface of the first electrode portion 22A in a cross-sectional view, and coats the wall surface of the first electrode portion 22A in a film-like manner. The isolation insulating film 25 is connected to the gate insulating film 21 (drift covering portion 21C) and the intermediate insulating film 24 on the lower end side of the first electrode portion 22A. In other words, the isolation insulating film 25 is formed at a distance from the first channel region 13A in the horizontal direction, and does not face the first channel region 13A in the vertical direction Z.

[0076] The isolation insulating film 25 extends in the vertical direction Z along the wall surface of the second electrode portion 22B in a cross-sectional view, and coats the wall surface of the second electrode portion 22B in a film-like manner. The isolation insulating film 25 is connected to the gate insulating film 21 (drift covering portion 21C) and the intermediate insulating film 24 on the lower end side of the second electrode portion 22B. In other words, the isolation insulating film 25 is formed at a distance from the second channel region 13B in the horizontal direction, and does not face the second channel region 13B in the vertical direction Z.

[0077] The isolation insulating film 25, together with the intermediate insulating film 24, defines an insulating recess 26 within the through hole 23. The insulating recess 26 is formed in a strip shape extending along the through hole 23 in a plan view. The insulating recess 26 is formed to be narrower than the surface drift region 14 in a cross-sectional view.

[0078] The isolation insulating film 25 may have a thickness greater than that of the gate insulating film 21. The thickness of the isolation insulating film 25 is defined by the horizontal thickness with reference to the wall surface of the planar gate electrode 22. The thickness of the isolation insulating film 25 may be less than that of the gate insulating film 21. The thickness of the isolation insulating film 25 may be greater than that of the intermediate insulating film 24. The thickness of the isolation insulating film 25 may be less than that of the intermediate insulating film 24. The thickness of the isolation insulating film 25 may be less than that of the planar gate electrode 22. The thickness of the isolation insulating film 25 may be greater than that of the planar gate electrode 22.

[0079] Each of the first planar structures 20A includes a planar insulating film 27 covering the planar gate electrode 22. The planar insulating film 27 may contain the same insulating material as the gate insulating film 21, or may contain a different insulating material from the gate insulating film 21. The planar insulating film 27 may contain the same insulating material as the intermediate insulating film 24, or may contain a different insulating material from the intermediate insulating film 24.

[0080] The planar insulating film 27 may contain the same insulating material as the isolation insulating film 25, or may contain an insulating material different from that of the isolation insulating film 25. The planar insulating film 27 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the planar insulating film 27 has a single-layer structure made of a silicon oxide film.

[0081] The planar insulating film 27 covers the electrode surface of the planar gate electrode 22 from above the gate insulating film 21 via the wall surface of the planar gate electrode 22. Specifically, the planar insulating film 27 covers the electrode surface of the first electrode portion 22A from above the first channel covering portion 21A via the wall surface of the first electrode portion 22A, and covers the electrode surface of the second electrode portion 22B from above the second channel covering portion 21B via the wall surface of the second electrode portion 22B.

[0082] The planar insulating film 27 has a portion extending horizontally in a film shape along the first channel covering portion 21A, a portion extending horizontally in a film shape along the second channel covering portion 21B, a portion extending horizontally in a film shape along the first electrode portion 22A, and a portion extending horizontally in a film shape along the second electrode portion 22B. The portions of the planar insulating film 27 covering the first electrode portion 22A and the second electrode portion 22B are positioned higher than the portions of the planar insulating film 27 covering the first channel covering portion 21A and the second channel covering portion 21B.

[0083] The planar insulating film 27 is connected to the isolation insulating film 25 at an inner portion of the planar gate electrode 22, and defines a recess through-hole 28 that communicates with the insulating recess 26. The recess through-hole 28 is formed in a strip shape extending along the insulating recess 26 in a plan view. In this embodiment, the recess through-hole 28 is formed to be narrower than the surface drift region 14 in a cross-sectional view.

[0084] In this embodiment, the intermediate insulating film 24 and the isolation insulating film 25 are made of a part of the planar insulating film 27, and the insulating recess 26 and the recess through-hole 28 are formed by etching the planar insulating film 27 (the part covering the through-hole 23). Therefore, the recess through-hole 28 has a wall surface formed flush with the wall surface of the recess through-hole 28. The width of the recess through-hole 28 is approximately equal to the width of the insulating recess 26.

[0085] Each of the first planar structures 20A includes a planar source electrode 29 disposed on the gate insulating film 21. The planar source electrode 29 is disposed on the drift covering 21C at a distance from the planar gate electrode 22 so as to face the planar gate electrode 22 in the horizontal direction, and faces the surface drift region 14 in the vertical direction Z via the drift covering 21C.

[0086] Specifically, the planar source electrode 29 is disposed within the insulating recess 26. The planar source electrode 29 is formed in a strip shape extending in the second direction Y along the insulating recess 26 in a plan view. That is, the planar source electrode 29 extends in the a-axis direction of the SiC single crystal. The extending direction of the planar source electrode 29 also coincides with the off-direction of the SiC single crystal.

[0087] The planar source electrode 29 faces the planar gate electrode 22 in the horizontal direction within the insulating recess 26 via the isolation insulating film 25, and is electrically insulated from the planar gate electrode 22 by the isolation insulating film 25. Specifically, the planar source electrode 29 faces both the first electrode portion 22A and the second electrode portion 22B in the horizontal direction via the isolation insulating film 25 in a cross-sectional view, and is electrically insulated from both the first electrode portion 22A and the second electrode portion 22B by the isolation insulating film 25.

[0088] In this embodiment, the planar source electrode 29 has a portion that protrudes from the insulating recess 26 toward the recess through-hole 28 and is located within the recess through-hole 28. That is, the planar source electrode 29 has a portion that is located below (on the gate insulating film 21 side) the electrode surface (upper end) of the planar gate electrode 22, and a portion that is located above (on the opposite side to the gate insulating film 21) the electrode surface (upper end) of the planar gate electrode 22.

[0089] The planar source electrode 29 has a portion in contact with the intermediate insulating film 24 and the isolation insulating film 25 within the insulating recess 26, and a portion in contact with the planar insulating film 27 within the recess through-hole 28. That is, the planar source electrode 29 faces the surface drift region 14 in the vertical direction Z within the insulating recess 26 via the intermediate insulating film 24 and the gate insulating film 21. The height position of the lower end of the planar source electrode 29 is located higher than the height position of the lower end of the planar gate electrode 22.

[0090] The planar source electrode 29 is capacitively coupled to the surface drift region 14 via the gate insulating film 21. Specifically, the planar source electrode 29 is capacitively coupled to the surface drift region 14 via the intermediate insulating film 24 and the gate insulating film 21. The planar source electrode 29 forms a drain-source capacitance Cds together with the surface drift region 14, and reduces the feedback capacitance Crss (=gate-drain capacitance Cdg) between the surface drift region 14 and the planar gate electrode 22. This improves the switching speed.

[0091] In the first planar structure 20A, the planar gate electrode 22 and the planar source electrode 29 are arranged adjacent to each other in the horizontal direction on the same gate insulating film 21, and the planar source electrode 29 faces the surface drift region 14 via the gate insulating film 21. Therefore, the source potential occurs near the side of the planar gate electrode 22, reducing the electrical influence of the gate potential on the surface drift region 14. This suppresses capacitive coupling of the planar gate electrode 22 to the surface drift region 14 via the gate insulating film 21.

[0092] The planar source electrode 29 includes a conductive material different from that of the planar gate electrode 22. Specifically, the planar source electrode 29 includes a metal. More specifically, the planar source electrode 29 includes a metallic underlying electrode film 30 and a metallic electrode body 31.

[0093] The underlying electrode film 30 is made of a metal barrier film. The underlying electrode film 30 includes at least one of a Ti film, a TiN film, and a W film. In this embodiment, the underlying electrode film 30 includes a Ti film. The underlying electrode film 30 is formed in a film shape along the wall surfaces of the insulating recess 26 and the wall surfaces of the recess through-hole 28.

[0094] The underlying electrode film 30 covers the intermediate insulating film 24 and the isolation insulating film 25 within the insulating recess 26. The underlying electrode film 30 covers the planar insulating film 27 within the recess through-hole 28. The underlying electrode film 30 has a thickness less than half the width of the insulating recess 26, and defines an electrode recess within the insulating recess 26 and the recess through-hole 28.

[0095] The electrode body 31 forms the body of the planar source electrode 29. The electrode body 31 includes at least one of a pure W film (a W film with a purity of 99% or more), a W alloy film, an Al film, a Cu film, an Al alloy film, and a Cu alloy film. The electrode body 31 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the electrode body 31 includes an Al alloy film (an AlSiCu alloy film).

[0096] The electrode body 31 has a thickness greater than that of the underlying electrode film 30, and is embedded in the insulating recess 26 and the recess through-hole 28 via the underlying electrode film 30. The electrode body 31 has a portion facing the insulating recess 26 via the underlying electrode film 30, and a portion facing the recess through-hole 28 via the underlying electrode film 30.

[0097] The electrode body 31 has a portion that covers the intermediate insulating film 24 and the isolation insulating film 25 via the underlying electrode film 30 within the insulating recess 26. The electrode body 31 has a portion that covers the planar insulating film 27 via the underlying electrode film 30 within the recess through-hole 28.

[0098] The SiC semiconductor device 1A includes a plurality of contact recesses 32 formed in regions between adjacent first planar structures 20A (a plurality of planar insulating films 27) on the first main surface 3. In this embodiment, the plurality of contact recesses 32 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0099] That is, the contact recesses 32 are alternately formed with the first planar structures 20A in the first direction X. The contact recesses 32 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. The contact recesses 32 are also formed in a stripe pattern extending in the second direction Y (a-axis direction).

[0100] The plurality of contact recesses 32 are formed in the surface layer portions of the plurality of body regions 10 so as to expose the plurality of contact regions 12 in one-to-one correspondence. Each contact recess 32 has a bottom wall located closer to the bottom of the body region 10 than the height position of the gate insulating film 21. Each contact recess 32 is formed inward from the periphery of the body region 10 at intervals, and has a horizontally elongated recess shape extending horizontally from the bottom of the contact region 12 toward the first main surface 3 at an interval.

[0101] Each contact recess 32 extends from the contact region 12 toward the periphery of the body region 10, partially exposing both the first source region 11A and the second source region 11B from both sides. The bottom wall of each contact recess 32 is formed at a distance from the bottom of the first source region 11A and the bottom of the second source region 11B toward the first main surface 3. The contact recess 32 does not necessarily have to be formed, and a configuration without the contact recess 32 may be employed.

[0102] 2 , SiC semiconductor device 1A includes an interlayer insulating film 40 that selectively covers first main surface 3. In this embodiment, interlayer insulating film 40 has a stacked structure including a first insulating film 41 and a second insulating film 42. First insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that first insulating film 41 includes a silicon oxide film made of an oxide of chip 2.

[0103] The first insulating film 41 selectively covers the first main surface 3 in the active region 8 and the peripheral region 9. Specifically, the first insulating film 41 covers the region outside the plurality of gate insulating films 21 in the active region 8, and is connected to the plurality of gate insulating films 21. In this embodiment, the first insulating film 41 is formed integrally with the plurality of gate insulating films 21, and forms a single insulating film together with the plurality of gate insulating films 21.

[0104] The first insulating film 41 covers the first main surface 3 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 in the outer peripheral region 9. Of course, the first insulating film 41 may be formed at a distance inward from the periphery of the first main surface 3, exposing the drift region 6 from the periphery of the first main surface 3.

[0105] The second insulating film 42 is stacked on the first insulating film 41. The second insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 40 preferably includes a silicon oxide film.

[0106] The second insulating film 42 selectively covers the first main surface 3 in the active region 8 and the peripheral region 9, sandwiching the first insulating film 41 therebetween. Specifically, the second insulating film 42 covers the region outside the plurality of planar insulating films 27 in the active region 8, and is connected to the plurality of planar insulating films 27. In this embodiment, the second insulating film 42 is formed integrally with the plurality of planar insulating films 27, and forms a single insulating film together with the plurality of planar insulating films 27.

[0107] The second insulating film 42 covers the first insulating film 41 in the outer peripheral region 9 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, exposing the drift region 6 from the periphery of the first main surface 3.

[0108] 4 , although a specific cross-sectional view is omitted, the SiC semiconductor device 1A includes a plurality of gate openings 43 exposing a plurality of planar gate electrodes 22. The plurality of gate openings 43 penetrate a plurality of planar insulating films 27 and expose one end and / or the other end of the plurality of planar gate electrodes 22 (both ends in this embodiment). The plurality of gate openings 43 may expose one end and / or the other end of the plurality of first electrode portions 22A. The plurality of gate openings 43 may expose one end and / or the other end of the plurality of second electrode portions 22B.

[0109] The SiC semiconductor device 1A includes a plurality of source openings 44 formed in a region between a plurality of first planar structures 20A (a plurality of planar insulating films 27). The plurality of source openings 44 penetrate the gate insulating film 21 and the planar insulating film 27, and expose the plurality of contact recesses 32 in a one-to-one correspondence, respectively.

[0110] That is, each source opening 44 exposes the first source region 11A, the second source region 11B, and the contact region 12 through the corresponding contact recess 32. In this embodiment, each source opening 44 also exposes the corresponding planar insulating film 27 and gate insulating film 21.

[0111] In this embodiment, the source opening 44 is formed in a strip shape extending in the second direction Y along the contact recess 32 in a plan view. That is, the source opening 44 extends in the a-axis direction of the SiC single crystal. The extending direction of the source opening 44 also coincides with the off-direction of the SiC single crystal. Of course, multiple source openings 44 may be formed at intervals in the second direction Y.

[0112] 1 to 6 , the SiC semiconductor device 1A includes a first main surface electrode 45 disposed on an interlayer insulating film 40. The first main surface electrode 45 has a layered structure including an underlying electrode film 46 and an electrode body film 47, which are layered in this order from the interlayer insulating film 40 side. The underlying electrode film 46 is made of a metal barrier film and is layered on the interlayer insulating film 40. The underlying electrode film 46 includes at least one of a Ti film, a TiN film, and a W film. In this embodiment, the underlying electrode film 46 includes a Ti film. The underlying electrode film 46 is formed in a film shape along the wall surface of the interlayer insulating film 40.

[0113] The electrode body film 47 has a thickness greater than that of the underlying electrode film 46 and is laminated on the underlying electrode film 30. The electrode body film 47 includes at least one of a pure W film (a W film with a purity of 99% or more), a W alloy film, an Al film, a Cu film, an Al alloy film, and a Cu alloy film. The electrode body film 47 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the electrode body film 47 includes an Al alloy film (an AlSiCu alloy film in this embodiment).

[0114] 1 and 2 , the first main surface electrode 45 includes a gate pad 48 disposed on the interlayer insulating film 40. The gate pad 48 is an electrode to which a gate potential is applied from the outside. The gate pad 48 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. In this embodiment, the gate pad 48 is disposed on a portion of the interlayer insulating film 40 that covers the active region 8. In this embodiment, the gate pad 48 is formed in a polygonal shape (specifically, a quadrangular shape) in a plan view.

[0115] The gate pad 48 may be arranged in the active region 8 at a distance from the outer periphery region 9 in a plan view. Of course, the gate pad 48 may have a portion that is drawn out from the active region 8 to the outer periphery region 9 and is located in the outer periphery region 9. In this embodiment, the gate pad 48 is arranged on the periphery of the active region 8 in a plan view.

[0116] 1 shows an example in which the gate pad 48 is arranged in a region along the center of the second side surface 5B on the periphery of the active region 8. Of course, the gate pad 48 may also be arranged in a region along the center of any of the first to fourth side surfaces 5A to 5D. The gate pad 48 may also be arranged at any corner of the active region 8 in a plan view. The gate pad 48 may also be arranged in the center of the active region 8 in a plan view.

[0117] 1 and 4, the first principal surface electrode 45 includes at least one (in this embodiment, a plurality) gate wirings 49A, 49B that are drawn out from the gate pad 48 onto the interlayer insulating film 40 (the plurality of planar insulating films 27). The gate wirings 49A, 49B may also be referred to as "wiring", "wiring electrode", etc.

[0118] The plurality of gate wirings 49A, 49B include a first gate wiring 49A and a second gate wiring 49B. The first gate wiring 49A is drawn out from the gate pad 48 toward the first side surface 5A and extends in a line along the periphery of the active region 8 so as to intersect (specifically, perpendicular to) a portion (specifically, one end) of the plurality of first planar structures 20A. In other words, the first gate wiring 49A covers the plurality of planar insulating films 27.

[0119] The first gate wiring 49A penetrates the planar insulating films 27 via the gate openings 43 and is electrically connected to one ends of the planar gate electrodes 22 (first electrode portions 22A and second electrode portions 22B). In a plan view, the first gate wiring 49A is formed at a distance from one end of the planar source electrode 29 toward the peripheral edge of the chip 2, and faces the planar source electrode 29 in the second direction Y.

[0120] In other words, the first gate wiring 49A does not face the planar source electrode 29 via the planar insulating film 27. Of course, the first gate wiring 49A may face one end of the planar source electrode 29 across the planar insulating film 27 and be electrically insulated from the planar source electrode 29 by the planar insulating film 27.

[0121] On the other hand, the second gate wiring 49B is drawn out from the gate pad 48 toward the third side surface 5C and extends in a line along the periphery of the active region 8 so as to intersect (specifically, perpendicular to) parts (specifically, other ends) of the plurality of first planar structures 20A. In other words, the second gate wiring 49B covers the plurality of planar insulating films 27.

[0122] The second gate wiring 49B penetrates the planar insulating films 27 via the gate openings 43 and is electrically connected to the other ends of the planar gate electrodes 22 (the first electrode portions 22A and the second electrode portions 22B). In plan view, the second gate wiring 49B is formed at a distance from the other end of the planar source electrode 29 toward the periphery of the chip 2, and faces the planar source electrode 29 in the second direction Y.

[0123] In other words, the second gate wiring 49B does not face the planar source electrode 29 via the planar insulating film 27. Of course, the second gate wiring 49B may face the other end of the planar source electrode 29 with the planar insulating film 27 in between, and be electrically insulated from the planar source electrode 29 by the planar insulating film 27.

[0124] 1, 2, 5, and 6, the first main surface electrode 45 includes a source pad 50 disposed on the interlayer insulating film 40 (plurality of planar insulating films 27) at a distance from the gate pad 48 and the gate wirings 49A and 49B. The source pad 50 is an electrode to which a source potential is applied from the outside. The source pad 50 may also be referred to as a "source pad electrode," a "second pad electrode," or the like.

[0125] The source pad 50 covers the plurality of planar insulating films 27 in the active region 8. The source pad 50 may be disposed within the active region 8 at a distance from the peripheral region 9. Of course, the source pad 50 may have a portion that is drawn out from the active region 8 to the peripheral region 9 and positioned in the peripheral region 9. In this embodiment, the source pad 50 is formed in a polygonal shape having a recess that is recessed along the gate pad 48 in a plan view. Of course, the source pad 50 may also be formed in a quadrangular shape in a plan view.

[0126] The source pad 50 penetrates the planar insulating films 27 and the gate insulating films 21 via the source openings 44, and is electrically connected to the first source regions 11A, the second source regions 11B, and the contact regions 12. The source pad 50 is electrically connected to the body regions 10 via the first source regions 11A, the second source regions 11B, and the contact regions 12.

[0127] The underlying electrode film 46 of the source pad 50 extends from above the planar insulating film 27 through the source opening 44 into the contact recess 32, and is electrically connected to a plurality of first source regions 11A, a plurality of second source regions 11B, and a plurality of contact regions 12 within the contact recess 32.

[0128] The electrode body film 47 of the source pad 50 extends from above the underlying electrode film 46 through the source opening 44 into the contact recess 32, and is electrically connected to a plurality of first source regions 11A, a plurality of second source regions 11B, and a plurality of contact regions 12 via the underlying electrode film 46.

[0129] When the thickness of the underlying electrode film 46 is less than the depth of the contact recess 32, the electrode body film 47 of the source pad 50 is connected to the underlying electrode film 46 in the contact recess 32. When the thickness of the underlying electrode film 46 is greater than the depth of the contact recess 32, the electrode body film 47 of the source pad 50 is connected to the underlying electrode film 46 in the source opening 44.

[0130] In this embodiment, the source pad 50 is electrically connected to the plurality of planar source electrodes 29 on the plurality of planar insulating films 27. In this embodiment, the source pad 50 includes the plurality of planar source electrodes 29. That is, the plurality of planar source electrodes 29 extend from above the plurality of planar insulating films 27 into the plurality of insulating recesses 26 via the plurality of recess through-holes 28, and form the plurality of planar source electrodes 29 within the plurality of insulating recesses 26 (the plurality of recess through-holes 28).

[0131] Specifically, the base electrode film 46 of the source pad 50 extends from above the planar insulating film 27 into the insulating recess 26 through the recess through-hole 28, and forms the base electrode film 30 of the planar source electrode 29 in the insulating recess 26 and the recess through-hole 28. The electrode body film 47 of the source pad 50 extends from above the base electrode film 46 into the insulating recess 26 through the recess through-hole 28, and forms the electrode body 31 of the planar source electrode 29 in the insulating recess 26 and the recess through-hole 28.

[0132] The SiC semiconductor device 1A includes a drain pad 51 as a second-main-surface electrode covering the second main surface 4. The drain pad 51 is an electrode to which a drain potential is applied from the outside. The drain pad 51 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 51 forms ohmic contact with the drain region 7 exposed from the second main surface 4.

[0133] That is, the drain pad 51 is electrically connected to the drift region 6 and the surface drift region 14 via the drain region 7. The drain pad 51 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 51 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0134] The breakdown voltage that can be applied between source pad 50 and drain pad 51 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0135] Second to eleventh embodiments of the first planar structure 20A will be described below. The first planar structure 20A may have one or more of the features of the second to eleventh embodiments instead of or in addition to the features of the first embodiment. That is, the first planar structure 20A may have at least one feature of the first to eleventh embodiments.

[0136] The first planar structure 20A may have a feature that combines features of a plurality of the first to eleventh embodiments. The first planar structure 20A may partially have one or a plurality of features of the first to eleventh embodiments in different regions. The SiC semiconductor device 1A may simultaneously include at least two of the first planar structures 20A according to the first to eleventh embodiments in the active region 8.

[0137] 7A is an enlarged cross-sectional view showing a first planar structure 20A according to the second embodiment. In the first embodiment described above, the intermediate insulating film 24, the isolation insulating film 25, and the planar insulating film 27 are formed from the same insulating film. In contrast, the first planar structure 20A according to the second embodiment includes an insulating film 55 that integrally includes the intermediate insulating film 24 and the isolation insulating film 25 and is separate from the planar insulating film 27.

[0138] The insulating film 55 is formed as an etching stopper film from an insulating material different from the insulating material of the planar insulating film 27. For example, the insulating film 55 may be formed from a silicon nitride film, and the planar insulating film 27 may be formed from a silicon oxide film. Of course, the insulating film 55 may be formed from a silicon oxide film, and the planar insulating film 27 may be formed from a silicon nitride film.

[0139] In this example, the insulating film 55 (isolation insulating film 25) is extended from the through hole 23 onto the electrode surface of the planar gate electrode 22, and is extended onto the first channel covering portion 21A and the second channel covering portion 21B via the wall surface of the planar gate electrode 22. In other words, the insulating film 55 (isolation insulating film 25) covers the gate insulating film 21 and the planar gate electrode 22 (the first electrode portion 22A and the second electrode portion 22B) in a film-like manner, and defines an insulating recess 26 within the through hole 23.

[0140] The insulating film 55 (isolation insulating film 25) alleviates restrictions on the layout (width and planar shape) of the recess through-hole 28 resulting from the layout (width and planar shape) of the insulating recess 26. For example, the planar insulating film 27 may cover the gate insulating film 21 and the planar gate electrode 22 (first electrode portion 22A and second electrode portion 22B) with the insulating film 55 (isolation insulating film 25) sandwiched therebetween so as to expose the entire area of ​​the insulating recess 26.

[0141] The planar insulating film 27 may have a recess through-hole 28 that covers the insulating film 55 (isolation insulating film 25) at a distance outward from the wall surface of the insulating recess 26 and exposes the entire insulating recess 26. In this case, the width of the recess through-hole 28 may be larger than the width of the insulating recess 26.

[0142] 7B is an enlarged cross-sectional view showing a first planar structure 20A according to a third embodiment. The first planar structure 20A according to the third embodiment has a modified form of the first planar structure 20A according to the second embodiment. In the third embodiment, the planar insulating film 27 covers the gate insulating film 21 and the planar gate electrode 22 (the first electrode portion 22A and the second electrode portion 22B) with the insulating film 55 (the isolation insulating film 25) sandwiched therebetween so as to partially expose the insulating recess 26.

[0143] The planar insulating film 27 extends from above the insulating film 55 into the insulating recess 26, and has a portion that covers the intermediate insulating film 24 and a portion that covers the isolation insulating film 25 within the insulating recess 26. The planar insulating film 27 defines a recess through-hole 28 that partially exposes the intermediate insulating film 24 within the insulating recess 26. In this case, the width of the recess through-hole 28 may be smaller than the width of the insulating recess 26.

[0144] 7C is an enlarged cross-sectional view showing a first planar structure 20A according to the fourth embodiment. The features of the fourth embodiment can be applied to any one or more of the first to third embodiments. In the first embodiment, the intermediate insulating film 24 is formed to cover the drift covering portion 21C in the through hole 23. In contrast, the first planar structure 20A according to the fourth embodiment has an isolation insulating film 25 but does not have the intermediate insulating film 24.

[0145] Such a structure is formed by completely removing the intermediate insulating film 24 by etching. The intermediate insulating film 24 may be made of the same insulating material as the gate insulating film 21, or may be made of an insulating material different from the insulating material of the gate insulating film 21.

[0146] When the insulating material of the intermediate insulating film 24 is the same as that of the gate insulating film 21, strict etching conditions are imposed to prevent the gate insulating film 21 from being lost during etching of the intermediate insulating film 24. When the insulating material of the intermediate insulating film 24 is different from that of the gate insulating film 21, the gate insulating film 21 functions as an etching stopper film against the etching of the intermediate insulating film 24. In these cases, the planar insulating film 27 may be made of the same insulating material as the intermediate insulating film 24 (the same insulating film), or may be made of a different insulating material (a different insulating film) from that of the intermediate insulating film 24.

[0147] The first planar structure 20A may have a recess 56 recessed toward the surface drift region 14 in a portion (insulating recess 26) of the drift covering portion 21C exposed from the isolation insulating film 25. The recess 56 is formed by a thinned portion of the drift covering portion 21C. That is, the recess 56 has a bottom located closer to the first main surface 3 than the portion of the drift covering portion 21C that is hidden by the isolation insulating film 25.

[0148] The bottom of the recess 56 is located closer to the first main surface 3 than the upper ends of the first channel covering portion 21A and the second channel covering portion 21B. The recess 56 does not necessarily have to be formed, and a configuration without the recess 56 may be employed. In this case, the height position of the portion of the drift covering portion 21C exposed from the insulating recess 26 is approximately equal to the height position of the other portions.

[0149] The planar source electrode 29 is disposed on the recess portion 56 in the insulating recess 26, and faces the surface drift region 14 in the vertical direction Z via the thinned portion of the drift covering portion 21C. The height position of the lower end of the planar source electrode 29 is located lower than the height position of the lower end of the planar gate electrode 22.

[0150] The base electrode film 30 of the planar source electrode 29 is formed in a film shape along the wall surfaces of the recess portion 56, the wall surfaces of the insulating recess 26, and the wall surfaces of the recess through-hole 28, and covers the thinned portion of the drift covering portion 21C, the isolation insulating film 25, and the planar insulating film 27. The base electrode film 30 preferably has a thickness greater than the depth of the recess portion 56 and has an electrode surface positioned above the recess portion 56.

[0151] That is, the electrode surface of the underlying electrode film 30 is preferably positioned higher than the upper ends of the first channel covering portion 21 A and the second channel covering portion 21 B. Of course, the underlying electrode film 30 may have a thickness less than the depth of the recessed portion 56 and an electrode surface positioned lower than the recessed portion 56.

[0152] The electrode body 31 of the planar source electrode 29 is embedded in the insulating recess 26 and the recess through-hole 28 via the underlying electrode film 30. The electrode body 31 has a portion facing the recess portion 56 via the underlying electrode film 30, a portion facing the insulating recess 26 via the underlying electrode film 30, and a portion facing the recess through-hole 28 via the underlying electrode film 30. In other words, the electrode body 31 has a portion covering the thinned portion of the drift covering portion 21C via the underlying electrode film 30.

[0153] When the thickness of the underlying electrode film 30 is greater than the depth of the recessed portion 56, the electrode body 31 is connected to the underlying electrode film 30 within the insulating recess 26. When the thickness of the underlying electrode film 30 is less than the depth of the recessed portion 56, the electrode body 31 is connected to the underlying electrode film 30 within the recessed portion 56.

[0154] The planar source electrode 29 is capacitively coupled to the surface drift region 14 via the thinned portion of the drift coating 21C. The planar source electrode 29 forms a drain-source capacitance Cds together with the surface drift region 14, thereby reducing the feedback capacitance Crss (=gate-drain capacitance Cdg) between the surface drift region 14 and the planar gate electrode 22.

[0155] 7D is an enlarged cross-sectional view showing a first planar structure 20A according to a fifth embodiment. The features of the fifth embodiment can also be applied to any one or more of the first to fourth embodiments. In the first embodiment, the electrode body 31 of the planar source electrode 29 is formed by a part of the electrode body film 47 of the source pad 50. In contrast, in the fifth embodiment, the electrode body 31 is formed separately from the electrode body film 47.

[0156] As in the first embodiment, the electrode body 31 may include at least one of a pure W film (a W film with a purity of 99% or more), a W alloy film, an Al film, a Cu film, an Al alloy film, and a Cu alloy film. Of these metal types, the electrode body 31 is preferably made of a pure W film or a W alloy film. In other words, the electrode body 31 of the planar source electrode 29 is preferably formed as a tungsten plug electrode.

[0157] The electrode surface of the planar source electrode 29 is located on the gate insulating film 21 (drift covering portion 21C) side with respect to the main surface of the planar insulating film 27, and is exposed from the insulating recess 26 (recess through-hole 28). The electrode surface of the planar source electrode 29 may be recessed toward the gate insulating film 21 (drift covering portion 21C) side. In this example, the electrode surface of the planar source electrode 29 is recessed in a curved shape toward the gate insulating film 21 (drift covering portion 21C) side.

[0158] As in the first embodiment, the base electrode film 46 of the source pad 50 is formed integrally with the base electrode film 30 of the planar source electrode 29. The electrode body film 47 of the source pad 50 directly covers the electrode body 31 and is physically and electrically connected to the electrode body 31. The electrode body film 47 is connected to the electrode surface of the planar source electrode 29 on the drift covering portion 21C side with respect to the main surface of the planar insulating film 27.

[0159] The configuration according to the fifth embodiment is effective in improving the embedding property of the planar source electrode 29 and the film formation property of the source pad 50. Of course, the technical idea of ​​the fourth embodiment may be adopted and the intermediate insulating film 24 may be removed (see FIG. 7C ). In this case, the planar source electrode 29 faces the surface drift region 14 in the vertical direction Z within the insulating recess 26 via the gate insulating film 21.

[0160] 7E is an enlarged cross-sectional view showing a first planar structure 20A according to the sixth embodiment. The features of the sixth embodiment can be applied to any one or more of the first to fifth embodiments. The first planar structure 20A according to the sixth embodiment has a modified form of the first planar structure 20A according to the fifth embodiment. In the fifth embodiment, the base electrode film 30 of the planar source electrode 29 is formed by a part of the base electrode film 46 of the source pad 50.

[0161] In contrast, in the sixth embodiment described above, the base electrode film 30 is formed separately from the base electrode film 46. As in the first embodiment, the base electrode film 30 may include at least one of a Ti film, a TiN film, and a W film. The base electrode film 30 does not have a portion that faces the planar gate electrode 22 in the vertical direction Z via the planar insulating film 27. The base electrode film 30 covers only the wall surfaces of the insulating recess 26 and the wall surfaces of the recess through-hole 28, and exposes almost the entire main surface of the planar insulating film 27.

[0162] In this example, the base electrode film 46 of the source pad 50 directly covers the planar insulating film 27, the base electrode film 30, and the electrode body 31, and is physically and electrically connected to the planar source electrode 29 (the base electrode film 30 and the electrode body 31). The base electrode film 46 of the source pad 50 is connected to the electrode surface of the planar source electrode 29 on the drift covering portion 21C side with respect to the main surface of the planar insulating film 27. The electrode body film 47 of the source pad 50 covers the planar insulating film 27, the base electrode film 30, and the electrode body 31 with the base electrode film 46 sandwiched therebetween.

[0163] The configuration according to the sixth embodiment is effective in improving the embedding property of the planar source electrode 29 and the film formation property of the source pad 50. Of course, the technical idea of ​​the fourth embodiment may be adopted and the intermediate insulating film 24 may be removed (see FIG. 7C ). In this case, the planar source electrode 29 faces the surface drift region 14 in the vertical direction Z within the insulating recess 26 via the gate insulating film 21.

[0164] 7F is an enlarged cross-sectional view showing a first planar structure 20A according to the seventh embodiment. The features of the seventh embodiment can be applied to any one or more of the first to sixth embodiments. In the first embodiment, the planar source electrode 29 has a laminated structure including an underlying electrode film 30 and an electrode body 31.

[0165] In contrast, the planar source electrode 29 according to the seventh embodiment is a single-layer buried electrode that is integrally buried in the insulating recess 26. In this embodiment, the planar source electrode 29 includes conductive polysilicon. That is, the planar source electrode 29 includes the same type of conductive material as the planar gate electrode 22. The planar source electrode 29 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0166] The planar source electrode 29 does not necessarily have to have the same conductivity type as the planar gate electrode 22. The conductivity type of the planar source electrode 29 may be the same as or different from the conductivity type of the planar gate electrode 22. For example, the planar gate electrode 22 may include n-type conductive polysilicon, while the planar source electrode 29 may include p-type conductive polysilicon. For example, the planar gate electrode 22 may include p-type conductive polysilicon, while the planar source electrode 29 may include n-type conductive polysilicon.

[0167] The electrode surface of the planar source electrode 29 is located on the gate insulating film 21 (drift covering portion 21C) side with respect to the main surface of the planar insulating film 27, and is exposed from the insulating recess 26 (recess through-hole 28). The electrode surface of the planar source electrode 29 may be recessed toward the gate insulating film 21 (drift covering portion 21C) side. The electrode surface of the planar source electrode 29 may be curved toward the gate insulating film 21 (drift covering portion 21C) side. In this example, the electrode surface of the planar source electrode 29 is recessed in a curved shape toward the gate insulating film 21 (drift covering portion 21C) side.

[0168] The base electrode film 46 of the source pad 50 covers the planar insulating film 27 and the electrode surfaces of the planar source electrode 29, and is physically and electrically connected to the planar source electrode 29. The base electrode film 46 is connected to the electrode surface of the planar source electrode 29 on the drift covering portion 21C side of the main surface of the planar insulating film 27. The electrode body film 47 of the source pad 50 covers the planar insulating film 27 and the planar source electrode 29 with the base electrode film 46 sandwiched therebetween.

[0169] The configuration according to the seventh embodiment is effective in improving the embedding property of the planar source electrode 29 and the film formation property of the source pad 50. Of course, the technical idea of ​​the fourth embodiment may be adopted, and the intermediate insulating film 24 may be removed (see FIG. 7C ). In this case, the planar source electrode 29 faces the surface drift region 14 in the vertical direction Z within the insulating recess 26 via the gate insulating film 21.

[0170] In the seventh embodiment, the planar source electrode 29 has a single-layer structure made of conductive polysilicon. However, the planar source electrode 29 may have a single-layer structure made of metal. For example, the planar source electrode 29 may have a single-layer structure made of pure Ti, a Ti alloy (e.g., TiN), pure W, a W alloy, pure Al, pure Cu, an Al alloy, or a Cu alloy. The planar source electrode 29 may have a single-layer structure made of an AlCu alloy, an AlSi alloy, or an AlSiCu alloy.

[0171] Fig. 7G is an enlarged plan view showing a first planar structure 20A according to an eighth embodiment. Fig. 7G is an enlarged plan view showing a first planar structure 20A according to an eighth embodiment. The features of the eighth embodiment can also be applied to any one or more of the first to seventh embodiments. In the first embodiment, the first electrode portion 22A and the second electrode portion 22B are separated by the through-hole 23.

[0172] In contrast to this, in the eighth embodiment, a through-hole 23 is formed that eliminates one of the first electrode portion 22A and the second electrode portion 22B (the second electrode portion 22B in FIG. 7G ). That is, the planar gate electrode 22 is made up of the other of the first electrode portion 22A and the second electrode portion 22B (the first electrode portion 22A in FIG. 7G ).

[0173] In this example, intermediate insulating film 24 covers drift covering portion 21C and second channel covering portion 21B, and vertically covers second source region 11B, second channel region 13B, and surface drift region 14 via gate insulating film 21. Isolation insulating film 25 covers the wall surface of first electrode portion 22A, and defines insulating recess 26 together with intermediate insulating film 24 within through hole 23. In this example, insulating recess 26 is defined to be wider than drift covering portion 21C and second channel covering portion 21B.

[0174] The planar insulating film 27 covers the electrode surface of the first electrode portion 22A via the wall surface of the first electrode portion 22A from above the first channel covering portion 21A. The planar insulating film 27 is connected to the isolation insulating film 25 above the first electrode portion 22A and defines a recess through-hole 28 that communicates with the insulating recess 26. In this example, the recess through-hole 28 is defined to be wider than the drift covering portion 21C and the second channel covering portion 21B.

[0175] The multiple source openings 44 communicate with the insulating recess 26 and the recess through-hole 28 on the second channel region 13B side. In this example, a part of the source pad 50 is disposed in the insulating recess 26 (recess through-hole 28) as a planar source electrode 29. Specifically, the source pad 50 extends from above the planar insulating film 27 into the insulating recess 26 via the recess through-hole 28 to form the planar source electrode 29.

[0176] The planar source electrode 29 faces the planar gate electrode 22 in the horizontal direction within the insulating recess 26 via the isolation insulating film 25, and is electrically insulated from the planar gate electrode 22 by the isolation insulating film 25. The planar source electrode 29 faces the second source region 11B, the second channel region 13B, and the surface drift region 14 in the vertical direction Z within the insulating recess 26 via the intermediate insulating film 24 and the gate insulating film 21.

[0177] The source pad 50 (planar source electrode 29 ) extends from the insulating recess 26 into the source opening 44 and is electrically connected to the first source region 11 A, the second source region 11 B, and the contact region 12 within the source opening 44 .

[0178] The planar source electrode 29 is fixed to the same potential as the second source region 11B and the second channel region 13B. Therefore, the planar source electrode 29 eliminates the function of the second channel region 13B and reduces the feedback capacitance Crss (=gate-drain capacitance Cdg) between the surface drift region 14 and the planar gate electrode 22.

[0179] Of course, the technical idea of ​​the fourth embodiment may be adopted, and the intermediate insulating film 24 may be removed (see FIG. 7C ). In this case, the planar source electrode 29 faces the second source region 11B, the second channel region 13B, and the surface drift region 14 in the vertical direction Z through the gate insulating film 21 within the insulating recess 26.

[0180] 7H is an enlarged plan view showing a first planar structure 20A according to the ninth embodiment. The features of the ninth embodiment can be applied to any one or more of the first to eighth embodiments. In the first embodiment described above, the through holes 23 are formed inwardly from both ends of the planar gate electrode 22 at intervals.

[0181] In contrast to this, in the ninth embodiment, the through-hole 23 penetrates one or both of the end portions of the planar gate electrode 22 in a planar view. In this example, the through-hole 23 penetrates both of the end portions of the planar gate electrode 22 in a planar view, and divides the planar gate electrode 22 (the first electrode portion 22A and the second electrode portion 22B) into stripes. Of course, the through-hole 23 may penetrate only one of the end portions of the planar gate electrode 22 in a planar view, and divide the planar gate electrode 22 into a U-shape.

[0182] 7I is an enlarged plan view showing a first planar structure 20A according to the tenth embodiment. The features of the tenth embodiment can be applied to any one or more of the first to ninth embodiments. In the first embodiment described above, one through-hole 23 is formed in one planar gate electrode 22.

[0183] In contrast to this, in the tenth embodiment, a plurality of through holes 23 are formed in one planar gate electrode 22. The plurality of through holes 23 are formed at intervals in the extension direction (second direction Y) of the planar gate electrode 22 in a planar view. The plurality of through holes 23 divide the planar gate electrode 22 into a lattice pattern in a planar view.

[0184] The planar shape of each through hole 23 is arbitrary. Each through hole 23 may be formed in a quadrangular, rectangular, hexagonal, octagonal, circular, elliptical, or other shape in a planar view. A plurality of planar source electrodes 29 are arranged in the plurality of through holes 23. In this example, the plurality of planar source electrodes 29 are arranged in the plurality of through holes 23 at intervals in the extension direction of the planar gate electrode 22 (second direction Y).

[0185] 7J is an enlarged cross-sectional view showing a first planar structure 20A according to the eleventh embodiment. The features of the eleventh embodiment can be applied to any one or more of the first to tenth embodiments. In the first embodiment described above, the first planar structure 20A includes a gate insulating film 21, a planar gate electrode 22, an intermediate insulating film 24, an isolation insulating film 25, a planar insulating film 27, and a planar source electrode 29.

[0186] In contrast, the first planar structure 20A according to the eleventh embodiment has the gate insulating film 21, the intermediate insulating film 24, and the planar source electrode 29, but does not have the planar gate electrode 22, the isolation insulating film 25, or the planar insulating film 27. The intermediate insulating film 24 covers almost the entire gate insulating film 21, and faces the first source region 11A, the second source region 11B, the first channel region 13A, the second channel region 13B, and the surface drift region 14 in the vertical direction Z via the gate insulating film 21.

[0187] A part of the source pad 50 described above is formed as a planar source electrode 29, and directly covers the intermediate insulating film 24. The planar source electrode 29 (source pad 50) faces the first source region 11A, the second source region 11B, the first channel region 13A, the second channel region 13B, and the surface drift region 14 in the vertical direction Z via the intermediate insulating film 24 and the gate insulating film 21.

[0188] The planar source electrode 29 is fixed to the same potential as the first source region 11A, the second source region 11B, the first channel region 13A, and the second channel region 13B. The planar source electrode 29 eliminates the functions of the first channel region 13A and the second channel region 13B, and reduces the feedback capacitance Crss (=gate-drain capacitance Cdg).

[0189] In the first planar structure 20A according to the eleventh embodiment, both the first channel region 13A and the second channel region 13B are eliminated, and therefore the first planar structure 20A according to the eleventh embodiment cannot be used alone. Therefore, it is desirable to use the first planar structure 20A according to the eleventh embodiment in combination with another planar structure. Of course, the first planar structure 20A according to the eleventh embodiment may be partially incorporated into a portion of the other planar structure.

[0190] Of course, the technical idea of ​​the fourth embodiment may be adopted, and the intermediate insulating film 24 may be removed (see FIG. 7C ). In this case, the planar source electrode 29 faces the first source region 11A, the second source region 11B, the first channel region 13A, the second channel region 13B, and the surface drift region 14 in the vertical direction Z via the gate insulating film 21.

[0191] Fig. 8 is a plan view showing a SiC semiconductor device 1B according to the second embodiment. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 8. Fig. 10 is a plan view showing an example layout of the chip 2 shown in Fig. 8. Fig. 11 is an enlarged plan view showing an example layout of the active region 8 together with a second planar structure 20B according to the first embodiment. Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 11. Fig. 13 is an enlarged cross-sectional view showing the second planar structure 20B.

[0192] Similar to the SiC semiconductor device 1A, the SiC semiconductor device 1B includes a chip 2, a drift region 6, a drain region 7, an active region 8, a peripheral region 9, a plurality of body regions 10, a plurality of source regions 11A, 11B, a plurality of contact regions 12, a plurality of channel regions 13A, 13B, a plurality of surface drift regions 14, a plurality of contact recesses 32, an interlayer insulating film 40, a plurality of gate openings 43, a plurality of source openings 44, a gate pad 48, gate wirings 49A, 49B, a source pad 50, and a drain pad 51.

[0193] SiC semiconductor device 1B differs from SiC semiconductor device 1A in that it includes a plurality of second planar structures 20B instead of the plurality of first planar structures 20A. Each of the plurality of second planar structures 20B includes a gate insulating film 21 covering first main surface 3. Gate insulating film 21 has the same form as in the first embodiment.

[0194] Each of the second planar structures 20B includes a planar gate electrode 60 disposed on the gate insulating film 21. The planar gate electrode 60 is disposed on the first channel covering portion 21A at a distance from the second channel covering portion 21B, and faces the first channel region 13A in the vertical direction Z via the first channel covering portion 21A. The planar gate electrode 60 does not face the second channel region 13B in the vertical direction Z.

[0195] The planar gate electrode 60 controls the inversion and non-inversion of the first channel region 13A in response to an external gate potential. The planar gate electrode 60 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the planar gate electrode 60 is adjusted according to the gate threshold voltage to be achieved.

[0196] The planar gate electrode 60 is formed in a strip shape on the first channel covering portion 21A and extends in the second direction Y. That is, the planar gate electrode 60 extends in the a-axis direction of the SiC single crystal. The extending direction of the planar gate electrode 60 also coincides with the off-direction of the SiC single crystal.

[0197] The planar gate electrode 60 extends from above the first channel covering portion 21A onto the drift covering portion 21C, and has a portion facing the surface drift region 14 via the drift covering portion 21C. In other words, the planar gate electrode 60 faces the second channel region 13B in the horizontal direction via a part of the drift covering portion 21C.

[0198] The planar gate electrode 60 is preferably formed at a distance from the widthwise middle of the drift covering portion 21C to the first channel covering portion 21A. That is, the area of ​​the planar gate electrode 60 hidden by the drift covering portion 21C is preferably less than the exposed area of ​​the drift covering portion 21C. The area of ​​the planar gate electrode 60 facing the surface drift region 14 may be less than the area of ​​the planar gate electrode 60 facing the first channel region 13A.

[0199] The planar gate electrode 60 is capacitively coupled to the first source region 11A (first channel region 13A) via the first channel covering portion 21A, and is capacitively coupled to the surface drift region 14 via the drift covering portion 21C. The planar gate electrode 60 forms a gate-source capacitance Cgs together with the first source region 11A (first channel region 13A), and forms a gate-drain capacitance Cdg together with the surface drift region 14. The gate-drain capacitance Cdg of the planar gate electrode 60 is preferably less than the gate-source capacitance Cgs of the planar gate electrode 60.

[0200] Each of the second planar structures 20B includes a planar source electrode 61 disposed on the gate insulating film 21. The planar source electrode 61 is disposed on the second channel covering portion 21B at a distance from the first channel covering portion 21A, and faces the planar gate electrode 60 in the horizontal direction via the drift covering portion 21C.

[0201] The planar source electrode 61 faces the second channel region 13B in the vertical direction Z via the second channel covering portion 21B. The planar source electrode 61 does not face the first channel region 13A in the vertical direction Z. The planar source electrode 61 is fixed to the same potential as the second source region 11B (second channel region 13B). The planar source electrode 61 eliminates the function of the second channel region 13B (see FIGS. 5 and 6 ) and reduces the feedback capacitance Crss (=gate-drain capacitance Cdg) between the surface drift region 14 and the planar gate electrode 60.

[0202] The planar source electrode 61 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the planar source electrode 61 may be the same as or different from the conductivity type of the planar gate electrode 60.

[0203] For example, the planar gate electrode 60 may comprise n-type conductive polysilicon, while the planar source electrode 61 may comprise p-type conductive polysilicon. For example, the planar gate electrode 60 may comprise p-type conductive polysilicon, while the planar source electrode 61 may comprise n-type conductive polysilicon.

[0204] Of course, when the planar gate electrode 60 includes n-type and p-type regions formed in conductive polysilicon in a first layout, the planar source electrode 61 may include n-type and p-type regions formed in conductive polysilicon in a second layout similar to the first layout. Of course, the planar source electrode 61 may include n-type and p-type regions formed in conductive polysilicon in a second layout different from the first layout.

[0205] The planar source electrode 61 is formed in a strip shape extending in the second direction Y on the second channel covering portion 21B. That is, the planar source electrode 61 extends in the a-axis direction of the SiC single crystal. The extending direction of the planar source electrode 61 also coincides with the off-direction of the SiC single crystal. The planar source electrode 61 extends approximately parallel to the planar gate electrode 60 on the same gate insulating film 21 in a plan view.

[0206] The planar source electrode 61 extends from above the second channel covering portion 21B onto the drift covering portion 21C, and has a portion facing the surface drift region 14 via the drift covering portion 21C. That is, the planar source electrode 61 faces the first channel region 13A in the horizontal direction via part of the drift covering portion 21C in a plan view. The facing area of ​​the planar source electrode 61 with respect to the surface drift region 14 may be smaller than the facing area of ​​the planar source electrode 61 with respect to the second channel region 13B.

[0207] The planar source electrode 61 may be formed at a distance from the middle of the drift covering portion 21C in the width direction to the second channel covering portion 21B. In other words, the area of ​​the planar source electrode 61 hidden by the drift covering portion 21C may be less than the area of ​​the drift covering portion 21C exposed to the planar source electrode 61.

[0208] In the first direction X, the width of the planar source electrode 61 may be approximately equal to the width of the planar gate electrode 60. Of course, the width of the planar source electrode 61 may be less than the width of the planar gate electrode 60. Alternatively, the width of the planar source electrode 61 may be greater than the width of the planar gate electrode 60.

[0209] The planar source electrode 61 may have one end positioned on the same straight line as one end of the planar gate electrode 60. Of course, one end of the planar source electrode 61 may be positioned closer to the active region 8 than one end of the planar gate electrode 60. Also, one end of the planar source electrode 61 may be positioned closer to the outer periphery region 9 than one end of the planar gate electrode 60.

[0210] The planar source electrode 61 may have another end positioned on the same straight line as the other end of the planar gate electrode 60. Of course, the other end of the planar source electrode 61 may be positioned closer to the active region 8 than the other end of the planar gate electrode 60. In addition, the other end of the planar source electrode 61 may be positioned closer to the outer periphery region 9 than the other end of the planar gate electrode 60.

[0211] The plurality of second planar structures 20B include an isolation insulating film 62 interposed in a region between the planar gate electrode 22 and the planar source electrode 61. The isolation insulating film 62 electrically insulates the planar gate electrode 22 and the planar source electrode 61 in the horizontal direction on the same gate insulating film 21 (drift covering portion 21C).

[0212] The isolation insulating film 62 may contain the same insulating material as the gate insulating film 21, or may contain an insulating material different from that of the gate insulating film 21. The isolation insulating film 62 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the isolation insulating film 62 has a single-layer structure made of a silicon oxide film.

[0213] The isolation insulating film 62 is disposed on the drift covering portion 21C, and has a portion facing the surface drift region 14 in the vertical direction Z via the drift covering portion 21C. The isolation insulating film 62 is connected to both the wall surfaces of the planar gate electrode 60 and the planar source electrode 61, and extends in the vertical direction Z along the wall surfaces of the planar gate electrode 60 and the planar source electrode 61.

[0214] The isolation insulating film 62 is formed at a distance from the first channel region 13A and the second channel region 13B in the horizontal direction, and faces the surface drift region 14 in the vertical direction Z. The isolation insulating film 62 does not face the first channel region 13A and the second channel region 13B in the vertical direction Z.

[0215] The isolation insulating film 62 has a thickness in the vertical direction Z that is greater than the thickness of the gate insulating film 21. The isolation insulating film 62 has a lower end located below (toward the drift covering 21C) the electrode surfaces of the planar gate electrode 60 and the planar source electrode 61, and an upper end protruding above (on the opposite side to the drift covering 21C) the electrode surfaces of the planar gate electrode 60 and the planar source electrode 61.

[0216] The lower end of the isolation insulating film 62 is connected to the drift covering portion 21C. The upper end of the isolation insulating film 62 has a recess 62A recessed toward the drift covering portion 21C. The recess 62A may be located above the electrode surfaces of the planar gate electrode 60 and the planar source electrode 61. Of course, the recess 62A may have a portion located below the electrode surfaces of the planar gate electrode 60 and the planar source electrode 61.

[0217] The horizontal thickness of the isolation insulating film 62 is less than the width of the drift covering portion 21C (surface drift region 14) and is defined by the distance (insulation distance) between the adjacent planar gate electrode 60 and planar source electrode 61.

[0218] The horizontal thickness of the isolation insulating film 62 may be greater than the thickness of the gate insulating film 21 in the vertical direction Z. The horizontal thickness of the isolation insulating film 62 may be greater than the thickness of the planar gate electrode 60 in the vertical direction Z. Of course, the horizontal thickness of the isolation insulating film 62 may be less than the thickness of the planar gate electrode 60 in the vertical direction Z. Furthermore, the horizontal thickness of the isolation insulating film 62 may be less than the thickness of the gate insulating film 21 in the vertical direction Z.

[0219] Each of the second planar structures 20B includes a planar insulating film 27 that covers the planar gate electrode 60 and the planar source electrode 61. The planar insulating film 27 may include the same insulating material as the gate insulating film 21, or may include an insulating material different from that of the gate insulating film 21.

[0220] The planar insulating film 27 may contain the same insulating material as the isolation insulating film 62, or may contain an insulating material different from that of the isolation insulating film 62. The planar insulating film 27 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the planar insulating film 27 has a single-layer structure made of a silicon oxide film.

[0221] The planar insulating film 27 covers the electrode surface of the planar gate electrode 60 via the wall surface of the planar gate electrode 60 from above the first channel covering portion 21A, and covers the electrode surface of the planar source electrode 61 via the wall surface of the planar source electrode 61 from above the second channel covering portion 21B.

[0222] In this embodiment, the planar insulating film 27 has a portion extending horizontally in the form of a film along the first channel covering portion 21A, a portion extending horizontally in the form of a film along the second channel covering portion 21B, a portion extending horizontally in the form of a film along the electrode surface of the planar gate electrode 60, and a portion extending horizontally in the form of a film along the electrode surface of the planar source electrode 61. The portions of the planar insulating film 27 covering the planar gate electrode 60 and the planar source electrode 61 are positioned higher than the portions of the planar insulating film 27 covering the first channel covering portion 21A and the second channel covering portion 21B.

[0223] The planar insulating film 27 is connected to the isolation insulating film 62 in the region between the planar gate electrode 60 and the planar source electrode 61. In this embodiment, the planar insulating film 27 contains the same insulating material as the isolation insulating film 62, and forms the isolation insulating film 62 in the region between the planar gate electrode 60 and the planar source electrode 61. In other words, the portion of the planar insulating film 27 located in the region between the planar gate electrode 60 and the planar source electrode 61 is formed as the isolation insulating film 62.

[0224] The SiC semiconductor device 1B includes, in addition to the plurality of gate openings 43 and the plurality of source openings 44, a plurality of planar source openings 63 exposing a plurality of planar source electrodes 61. The plurality of planar source openings 63 penetrate the plurality of planar insulating films 27 and expose the plurality of planar source electrodes 61 in a one-to-one correspondence, respectively.

[0225] The planar source opening 63 is formed on the inner side of the active region 8 relative to the multiple gate openings 43, and exposes the inner portion of the planar source electrode 61. In this embodiment, the planar source opening 63 is formed in a strip shape extending in the second direction Y along the planar source electrode 61 in a plan view.

[0226] That is, the planar source opening 63 extends in the a-axis direction of the SiC single crystal. The extending direction of the planar source opening 63 also coincides with the off-direction of the SiC single crystal. Of course, multiple planar source openings 63 may be formed at intervals in the second direction Y so as to expose a corresponding one planar source electrode 61 from multiple locations.

[0227] The second planar structure 20B may have a source recess 64 recessed toward the gate insulating film 21 in a portion of the electrode surface of the planar source electrode 61 exposed from the planar source opening 63. The source recess 64 is formed by a thinned portion of the planar source electrode 61. In other words, the source recess 64 has a bottom located closer to the gate insulating film 21 than the portion of the planar source electrode 61 that is hidden by the planar insulating film 27.

[0228] The bottom of the source recess 64 is located closer to the gate insulating film 21 than the electrode surface of the planar gate electrode 60. The bottom of the source recess 64 is preferably located closer to the electrode surface of the planar source electrode 61 than the middle part of the thickness range of the planar source electrode 61. The source recess 64 does not necessarily have to be formed, and a configuration without the source recess 64 may be employed.

[0229] In this embodiment, the above-described first gate wiring 49A is drawn out from the gate pad 48 toward the first side surface 5A and extends in a line along the periphery of the active region 8 so as to intersect (specifically, orthogonally intersect) with a part (specifically, one end) of the plurality of second planar structures 20B. In other words, the first gate wiring 49A covers the plurality of planar insulating films 27.

[0230] The first gate wiring 49A penetrates the planar insulating films 27 via the gate openings 43 and is electrically connected to one ends of the planar gate electrodes 60. The first gate wiring 49A faces one ends of the planar source electrodes 61 in the vertical direction Z via the planar insulating films 27, and is electrically insulated from the planar source electrodes 61 by the planar insulating films 27.

[0231] When one end of the planar source electrode 61 is positioned more inward of the active region 8 than one end of the planar gate electrode 60, the first gate wiring 49A may be arranged at a distance from one end of the multiple planar source electrodes 61 toward the outer periphery region 9 in a planar view.

[0232] In this embodiment, the second gate wiring 49B described above is drawn out from the gate pad 48 toward the third side surface 5C, and extends in a line along the periphery of the active region 8 so as to intersect (specifically, orthogonally) with parts (specifically, the other ends) of the plurality of second planar structures 20B. In other words, the second gate wiring 49B covers the plurality of planar insulating films 27.

[0233] The second gate wiring 49B penetrates the planar insulating films 27 via the gate openings 43 and is electrically connected to the other ends of the planar gate electrodes 60. The second gate wiring 49B faces the other ends of the planar source electrodes 61 in the vertical direction Z via the planar insulating films 27, and is electrically insulated from the planar source electrodes 61 by the planar insulating films 27.

[0234] When the other end of the planar source electrode 61 is positioned more inward of the active region 8 than the other end of the planar gate electrode 60, the second gate wiring 49B may be arranged at a distance from the other ends of the multiple planar source electrodes 61 toward the outer periphery region 9 in a planar view.

[0235] The aforementioned source pad 50 covers the plurality of second planar structures 20B (the plurality of planar insulating films 27) in the active region 8. As in the first embodiment, the source pad 50 penetrates the plurality of planar insulating films 27 and the plurality of gate insulating films 21 via the plurality of source openings 44, and is electrically connected to the plurality of first source regions 11A, the plurality of second source regions 11B, and the plurality of contact regions 12.

[0236] The source pad 50 penetrates the planar insulating films 27 via the planar source openings 63 and is electrically connected to the planar source electrodes 61. The base electrode film 46 of the source pad 50 extends from above the planar insulating film 27 into the planar source openings 63 and covers the planar source electrodes 61 in the planar source openings 63 in a film-like manner.

[0237] The base electrode film 46 of the source pad 50 is electrically connected to the planar source electrode 61 within the planar source opening 63. The electrode body film 47 of the source pad 50 extends into the planar source opening 63 from above the base electrode film 46 and is electrically connected to the planar source electrode 61 within the planar source opening 63 with the base electrode film 46 sandwiched therebetween.

[0238] Second to sixth embodiments of the second planar structure 20B will be described below. The second planar structure 20B may have one or more of the features of the second to sixth embodiments instead of or in addition to the feature of the first embodiment. That is, the second planar structure 20B may have at least one of the features of the first to sixth embodiments.

[0239] The second planar structure 20B may have a combination of features of the features of the first to sixth embodiments. The second planar structure 20B may partially have one or more features of the features of the first to sixth embodiments in different regions. The SiC semiconductor device 1B may simultaneously include at least two second planar structures 20B of the second planar structures 20B according to the first to sixth embodiments in the active region 8.

[0240] 14A is an enlarged cross-sectional view showing a second planar structure 20B according to the second embodiment. Referring to FIG. 14A, the planar source electrode 61 may be formed wider than the planar gate electrode 60. For example, the planar source electrode 61 may be formed wider than the surface drift region 14.

[0241] For example, the area of ​​the planar source electrode 61 facing the surface drift region 14 may be larger than the area of ​​the planar source electrode 61 facing the second channel region 13B. For example, the area of ​​the planar source electrode 61 facing the surface drift region 14 may be larger than the area of ​​the planar gate electrode 60 facing the surface drift region 14.

[0242] The planar source electrode 29 is capacitively coupled to the surface drift region 14 via the drift coating 21C, and forms a drain-source capacitance Cds together with the surface drift region 14. In this case, the drain-source capacitance Cds is preferably larger than the feedback capacitance Crss (=gate-drain capacitance Cdg) between the surface drift region 14 and the planar gate electrode 60.

[0243] The horizontal thickness of the isolation insulating film 62 is less than the width of the drift covering portion 21C (surface drift region 14). The horizontal thickness of the isolation insulating film 62 may be greater than the thickness of the gate insulating film 21 in the vertical direction Z. The horizontal thickness of the isolation insulating film 62 may be greater than the thickness of the planar gate electrode 60 (planar source electrode 61) in the vertical direction Z. Of course, the horizontal thickness of the isolation insulating film 62 may be less than the thickness of the planar gate electrode 60 (planar source electrode 61) in the vertical direction Z. Furthermore, the horizontal thickness of the isolation insulating film 62 may be less than the thickness of the gate insulating film 21 in the vertical direction Z.

[0244] When such a planar source electrode 61 is employed, restrictions on the layout of the planar source opening 63 are alleviated. For example, the planar source opening 63 may have at least one of a portion facing the second source region 11B, a portion facing the second channel region 13B, and a portion facing the surface drift region 14. For example, the planar source opening 63 may have both a portion facing the second channel region 13B and a portion facing the surface drift region 14.

[0245] For example, the planar source opening 63 may be formed wider than the second channel region 13B. For example, the planar source opening 63 may be formed wider than the planar gate electrode 60. For example, the planar source opening 63 may be formed wider than the surface drift region 14.

[0246] Of course, the planar source opening 63 may be formed narrower than the surface drift region 14. The planar source opening 63 may be formed narrower than the planar gate electrode 60. The planar source opening 63 may be formed narrower than the second channel region 13B.

[0247] 14B is an enlarged cross-sectional view showing a second planar structure 20B according to the third embodiment. The features according to the third embodiment are also applicable to the second embodiment. Referring to FIG. 14B, the planar source electrode 61 may be exposed from an end of the second channel covering portion 21B (gate insulating film 21).

[0248] The area of ​​the planar source electrode 61 facing the second source region 11B may be larger than the area of ​​the planar source electrode 61 facing the second channel region 13B. The area of ​​the planar source electrode 61 facing the second source region 11B may be larger than the area of ​​the planar gate electrode 60 facing the first source region 11A.

[0249] In this embodiment, the planar insulating film 27 covers the entire electrode surface of the planar source electrode 61 and does not have a planar source opening 63. The source opening 44 penetrates the planar insulating film 27, the planar source electrode 61, and the gate insulating film 21 on the second channel covering portion 21B side to expose the first source region 11A, the second source region 11B, the contact region 12, and the planar source electrode 61. The aforementioned source pad 50 is electrically connected to the first source region 11A, the second source region 11B, the contact region 12, and the planar source electrode 61 within the source opening 44.

[0250] 14C is an enlarged cross-sectional view showing a second planar structure 20B according to a fourth embodiment. The fourth embodiment is characterized by a modified version of the third embodiment. In the fourth embodiment, a planar source opening 63 is formed to expose the electrode surface of the planar source electrode 61. In this embodiment, the planar source opening 63 exposes the end of the electrode surface of the planar source electrode 61 on the side opposite to the planar gate electrode 60.

[0251] In this embodiment, the source opening 44 is connected to the planar source opening 63. Of course, as in the first embodiment, the planar source opening 63 may expose the inner part of the electrode surface of the planar source electrode 61, and the source opening 44 may be formed at a distance from the planar source opening 63.

[0252] 14D is an enlarged cross-sectional view showing a second planar structure 20B according to the fifth embodiment. Referring to FIG. 14D, the second planar structure 20B does not necessarily include both the planar gate electrode 60 and the planar source electrode 61. In the second planar structure 20B, the planar gate electrode 60 may be replaced with the planar source electrode 61.

[0253] That is, the second planar structure 20B may include one planar source electrode 61 facing the first channel region 13A in the vertical direction Z via the first channel covering portion 21A, and the other planar source electrode 61 facing the second channel region 13B in the vertical direction Z via the second channel covering portion 21B.

[0254] One planar source electrode 61 has a configuration similar to that of the other planar source electrode 61, except that it is disposed on the first channel covering portion 21A side. The description of the configuration of the planar source electrode 61 on the first channel region 13A side is omitted here, as the description of the configuration of the planar source electrode 61 on the second channel region 13B side applies. The source pad 50 is electrically connected to both the one planar source electrode 61 and the other planar source electrode 61 via a plurality of planar source openings 63.

[0255] In this example, one planar source electrode 61 faces the first source region 11A and the first channel region 13A in the vertical direction Z via the gate insulating film 21, and is fixed to the same potential as the first source region 11A and the first channel region 13A. The one planar source electrode 61 eliminates the function of the first channel region 13A and reduces the feedback capacitance Crss (=gate-drain capacitance Cdg).

[0256] The other planar source electrode 61 faces the second source region 11B and the second channel region 13B in the vertical direction Z via the gate insulating film 21, and is fixed to the same potential as the second source region 11B and the second channel region 13B. The other planar source electrode 61 eliminates the function of the second channel region 13B and reduces the feedback capacitance Crss (=gate-drain capacitance Cdg).

[0257] The second planar structure 20B according to the fifth embodiment cannot be used alone because both the first channel region 13A and the second channel region 13B are eliminated. Therefore, it is desirable to use the second planar structure 20B according to the fifth embodiment in combination with another planar structure. Of course, the second planar structure 20B according to the fifth embodiment may be partially incorporated into a portion of another planar structure.

[0258] 14E is an enlarged cross-sectional view showing a second planar structure 20B according to the sixth embodiment. The second planar structure 20B according to the sixth embodiment has a modified form of the second planar structure 20B according to the fifth embodiment. Specifically, in the second planar structure 20B, the planar source electrode 61 on the first channel covering portion 21A side and the planar source electrode 61 on the second channel covering portion 21B side are integrated.

[0259] That is, the second planar structure 20B according to the sixth embodiment includes a single planar source electrode 61. The single planar source electrode 61 is formed to be wider than the surface drift region 14, and faces the first source region 11A, the second source region 11B, the first channel region 13A, the second channel region 13B, and the surface drift region 14 in the vertical direction Z via the gate insulating film 21.

[0260] The single planar source electrode 61 is fixed to the same potential as the first source region 11A, the second source region 11B, the first channel region 13A, and the second channel region 13B. The single planar source electrode 61 eliminates the functions of the first channel region 13A and the second channel region 13B, and reduces the feedback capacitance Crss (=gate-drain capacitance Cdg).

[0261] The planar insulating film 27 has one or more planar source openings 63 that selectively expose the electrode surface of the planar source electrode 61. Fig. 14E shows an example in which one planar source opening 63 is formed. The planar source opening 63 may face the surface drift region 14 in the vertical direction Z across the planar source electrode 61.

[0262] The planar source opening 63 may be formed wider than the first channel region 13A. The planar source opening 63 may be formed wider than the second channel region 13B. The planar source opening 63 may be formed wider than the total width of the first channel region 13A and the second channel region 13B. The planar source opening 63 may be formed wider than the surface drift region 14. The planar source opening 63 may be formed wider than the total width of the first channel region 13A, the second channel region 13B, and the surface drift region 14.

[0263] Of course, the planar source opening 63 may be formed narrower than the total width of the first channel region 13A, the second channel region 13B, and the surface drift region 14. The planar source opening 63 may be formed narrower than the surface drift region 14. The planar source opening 63 may be formed narrower than the total width of the first channel region 13A and the second channel region 13B. The planar source opening 63 may be formed narrower than the first channel region 13A. The planar source opening 63 may be formed narrower than the second channel region 13B.

[0264] The second planar structure 20B according to the sixth embodiment cannot be used alone because both the first channel region 13A and the second channel region 13B are eliminated. Therefore, it is desirable to use the second planar structure 20B according to the sixth embodiment in combination with another planar structure. Of course, the second planar structure 20B according to the sixth embodiment may be partially incorporated into a portion of the other planar structure.

[0265] 15 is an enlarged cross-sectional view showing a main portion of a SiC semiconductor device 1C according to the third embodiment. The SiC semiconductor device 1C includes a third planar structure 20C. The third planar structure 20C has a structure in which the configuration (planar source electrode 29) of the first planar structure 20A according to the first embodiment (see FIG. 6) is combined with the second planar structure 20B according to the second embodiment (see FIG. 13).

[0266] 15 shows an example in which the first planar structure 20A according to the first embodiment (see FIG. 6) is applied to the second planar structure 20B according to the first embodiment (see FIG. 13). However, at least one feature of the first planar structures 20A according to the second to eleventh embodiments (see FIGS. 7A to 7J) may be incorporated into part or all of at least one feature of the second planar structures 20B according to the second to sixth embodiments (see FIGS. 14A to 14E).

[0267] The third planar structure 20C includes a through-hole 23 that separates the planar gate electrode 60 and the planar source electrode 61. The through-hole 23 is formed at a distance inward from the first channel covering portion 21A and the second channel covering portion 21B in cross-sectional and planar views. That is, the through-hole 23 exposes only the drift covering portion 21C.

[0268] In this embodiment, the through hole 23 is formed in a strip shape extending in the second direction Y in a plan view, and physically and electrically separates the planar gate electrode 60 and the planar source electrode 61. That is, the through hole 23 extends in the a-axis direction of the SiC single crystal. The extending direction of the through hole 23 also coincides with the off-direction of the SiC single crystal.

[0269] The third planar structure 20C includes an intermediate insulating film 24 that covers the drift covering portion 21C in the through hole 23. The intermediate insulating film 24 contacts the wall surfaces of the planar gate electrode 60 and the planar source electrode 61 in a cross-sectional view.

[0270] Intermediate insulating film 24 is formed at a distance from first channel region 13A and second channel region 13B in the horizontal direction. Intermediate insulating film 24 faces surface drift region 14 via drift covering portion 21C, but does not face first channel region 13A or second channel region 13B.

[0271] The intermediate insulating film 24 has a thickness less than the thickness of the planar gate electrode 60 and the thickness of the planar source electrode 61, and is formed at a distance from the electrode surfaces of the planar gate electrode 60 and the planar source electrode 61 toward the gate insulating film 21. The intermediate insulating film 24 may have a thickness greater than the thickness of the gate insulating film 21. The intermediate insulating film 24 may have a thickness less than the thickness of the gate insulating film 21. Of course, the technical idea of ​​the fourth embodiment may be adopted, and the intermediate insulating film 24 may be removed (see FIG. 7C ).

[0272] The third planar structure 20C includes an isolation insulating film 25 that covers the wall surfaces of the planar gate electrode 60 and the planar source electrode 61 in the through hole 23. The isolation insulating film 25 is disposed on the drift covering portion 21C and has a portion that faces the surface drift region 14 in the vertical direction Z with the drift covering portion 21C interposed therebetween.

[0273] The isolation insulating film 25 extends in the vertical direction Z along the wall surfaces of the planar gate electrode 60 and the planar source electrode 61, and coats the wall surfaces of the planar gate electrode 60 and the planar source electrode 61 in a film-like manner. The isolation insulating film 25 is connected to the gate insulating film 21 (drift covering portion 21C) and the intermediate insulating film 24 at the lower end sides of the planar gate electrode 60 and the planar source electrode 61.

[0274] The isolation insulating film 25 is formed at a distance from both the first channel region 13A and the second channel region 13B in the horizontal direction and does not face either the first channel region 13A or the second channel region 13B in the vertical direction Z. The isolation insulating film 25, together with the intermediate insulating film 24, defines an insulating recess 26 within the through hole 23. The insulating recess 26 is formed in a strip shape extending along the through hole 23 in a plan view. The insulating recess 26 is formed to be narrower than the surface drift region 14 in a cross-sectional view.

[0275] The third planar structure 20C includes a planar insulating film 27 that covers the planar gate electrode 60 and the planar source electrode 61. The planar insulating film 27 covers the electrode surface of the planar gate electrode 60 via the wall surface of the planar gate electrode 60 from above the first channel covering portion 21A, and covers the electrode surface of the planar source electrode 61 via the wall surface of the planar source electrode 61 from above the second channel covering portion 21B.

[0276] In this embodiment, the planar insulating film 27 has a portion extending horizontally in the form of a film along the first channel covering portion 21A, a portion extending horizontally in the form of a film along the second channel covering portion 21B, a portion extending horizontally in the form of a film along the planar gate electrode 60, and a portion extending horizontally in the form of a film along the planar source electrode 61. The portions of the planar insulating film 27 covering the planar gate electrode 60 and the planar source electrode 61 are positioned higher than the portions of the planar insulating film 27 covering the first channel covering portion 21A and the second channel covering portion 21B.

[0277] The planar insulating film 27 is connected to the isolation insulating film 25 at an inner portion of the planar gate electrode 60 and an inner portion of the planar source electrode 61, and defines a recess through-hole 28 that communicates with the insulating recess 26. The recess through-hole 28 is formed in a strip shape extending along the insulating recess 26 in a plan view. In this embodiment, the recess through-hole 28 is formed to be narrower than the surface drift region 14 in a cross-sectional view.

[0278] The third planar structure 20C includes a planar source electrode 29 disposed on the gate insulating film 21. The planar source electrode 29 is disposed on the drift covering 21C at a distance from both the planar gate electrode 60 and the planar source electrode 61 so as to face both the planar gate electrode 60 and the planar source electrode 61 in the horizontal direction, and faces the surface drift region 14 in the vertical direction Z via the drift covering 21C.

[0279] Specifically, the planar source electrode 29 is disposed in the insulating recess 26. The planar source electrode 29 is formed in a strip shape extending in the second direction Y (a-axis direction) along the insulating recess 26 in a planar view. In other words, the planar source electrode 29 extends substantially parallel to the planar gate electrode 60 and the planar source electrode 61.

[0280] The planar source electrode 29 faces both the planar gate electrode 60 and the planar source electrode 61 in the horizontal direction within the insulating recess 26 via the isolation insulating film 25 , and is electrically insulated from the planar gate electrode 22 by the isolation insulating film 25 .

[0281] In this embodiment, the planar source electrode 29 has a portion that protrudes from the insulating recess 26 toward the recess through-hole 28 and is located within the recess through-hole 28. That is, the planar source electrode 29 has a portion that is located below (on the gate insulating film 21 side) the electrode surfaces (upper ends) of the planar gate electrode 60 and the planar source electrode 61, and a portion that is located above (on the opposite side to the gate insulating film 21) the electrode surfaces (upper ends) of the planar gate electrode 60 and the planar source electrode 61.

[0282] The planar source electrode 29 has a portion in contact with the intermediate insulating film 24 and the isolation insulating film 25 within the insulating recess 26, and a portion in contact with the planar insulating film 27 within the recess through-hole 28. In other words, the planar source electrode 29 faces the surface drift region 14 in the vertical direction Z within the insulating recess 26 via the intermediate insulating film 24 and the gate insulating film 21.

[0283] In this embodiment, the planar source electrode 29 includes a conductive material different from that of the planar gate electrode 60 and the planar source electrode 61. Specifically, the planar source electrode 29 includes a metal. More specifically, the planar source electrode 29 includes a metallic underlying electrode film 30 and a metallic electrode body 31. Of course, the planar source electrode 29 may include the same type of conductive material as that of the planar gate electrode 60 and the planar source electrode 61 (see, for example, FIGS. 7D to 7F). In addition, the description of the first planar structure 20A applies to the planar source electrode 29.

[0284] Fig. 16 is an enlarged plan view showing an example layout of an active region 8 of a SiC semiconductor device 1D according to the fourth embodiment. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 16. The SiC semiconductor device 1D simultaneously includes one or more first planar structures 20A and one or more second planar structures 20B.

[0285] 16 and 17 show an example in which the SiC semiconductor device 1D includes the first planar structure 20A (see FIG. 6) according to the first embodiment and the second planar structure 20B (see FIG. 13) according to the first embodiment. However, the SiC semiconductor device 1D may include at least one of the first planar structures 20A (see FIGS. 7A to 7J) according to the second to eleventh embodiments instead of or in addition to the first planar structure 20A (see FIG. 6) according to the first embodiment.

[0286] The SiC semiconductor device 1D may include at least one of the second planar structures 20B (see Figures 14A to 14E) according to the second to sixth embodiments instead of or in addition to the second planar structure 20B (see Figure 13) according to the first embodiment.

[0287] The number of first planar structures 20A and the number of second planar structures 20B are appropriately adjusted depending on the feedback capacitance Crss to be achieved. For example, the SiC semiconductor device 1D may have a layout portion in which a plurality of first planar structures 20A and at least one second planar structure 20B are alternately arranged in the first direction X.

[0288] For example, SiC semiconductor device 1D may have a layout portion in which at least one first planar structure 20A and a plurality of second planar structures 20B are alternately arranged in first direction X. Of course, SiC semiconductor device 1D may include one or more third planar structures 20C instead of one or both of one or more first planar structures 20A and one or more second planar structures 20B.

[0289] 18 is an enlarged plan view showing an example of the layout of the active region 8 of a SiC semiconductor device 1E according to the fifth embodiment. The SiC semiconductor device 1E simultaneously includes one or more first planar structures 20A and one or more fourth planar structures 20D.

[0290] The fourth planar structure 20D is a normal planar structure that does not have the through-hole 23, the intermediate insulating film 24, the isolation insulating film 25, and the planar source electrode 29. In the fourth planar structure 20D, the planar gate electrode 22 faces the first source region 11A, the second source region 11B, the first channel region 13A, the second channel region 13B, and the surface drift region 14 in the vertical direction Z via the gate insulating film 21.

[0291] That is, the planar gate electrode 22 of the fourth planar structure 20D controls the inversion and non-inversion of both the first channel region 13A and the second channel region 13B. The planar gate electrode 22 of the fourth planar structure 20D is capacitively coupled to the source regions 11A and 11B (channel regions 13A and 13B) via the channel covering portions 21A and 21B, and is capacitively coupled to the surface drift region 14 via the drift covering portion 21C.

[0292] The planar gate electrode 22 of the fourth planar structure 20D forms a gate-source capacitance Cgs together with the source regions 11A, 11B (channel regions 13A, 13B) and a gate-drain capacitance Cdg together with the surface drift region 14. The gate-source capacitance Cgs of the fourth planar structure 20D is approximately equal to the gate-source capacitance Cgs of the first planar structure 20A. The gate-drain capacitance Cdg of the fourth planar structure 20D is larger than the gate-drain capacitance Cdg of the first planar structure 20A.

[0293] 18 and 19 show an example in which the SiC semiconductor device 1E includes the first planar structure 20A (see FIG. 6) according to the first embodiment. However, the SiC semiconductor device 1E may include at least one of the first planar structures 20A (see FIGS. 7A to 7J) according to the second to eleventh embodiments instead of or in addition to the first planar structure 20A (see FIG. 6) according to the first embodiment.

[0294] The number of first planar structures 20A and the number of fourth planar structures 20D are adjusted as appropriate depending on the feedback capacitance Crss to be achieved. For example, the SiC semiconductor device 1E may have a layout portion in which multiple first planar structures 20A and at least one fourth planar structure 20D are alternately arranged in the first direction X.

[0295] For example, SiC semiconductor device 1E may have a layout portion in which at least one first planar structure 20A and a plurality of fourth planar structures 20D are alternately arranged in first direction X. Of course, SiC semiconductor device 1E may include third planar structure 20C instead of or in addition to first planar structure 20A.

[0296] Fig. 20 is an enlarged plan view showing an example of the layout of the active region 8 of a SiC semiconductor device 1F according to the sixth embodiment. Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in Fig. 20. The SiC semiconductor device 1F simultaneously includes one or more second planar structures 20B and one or more fourth planar structures 20D.

[0297] The gate-source capacitance Cgs of the fourth planar structure 20D is larger than the gate-source capacitance Cgs of the second planar structure 20B. The gate-drain capacitance Cdg of the fourth planar structure 20D is larger than the gate-drain capacitance Cdg of the second planar structure 20B.

[0298] 20 and 21 show an example in which the SiC semiconductor device 1F includes the second planar structure 20B (see FIG. 13) according to the first embodiment. Of course, the SiC semiconductor device 1F may include at least one of the second planar structures 20B (see FIGS. 14A to 14E) according to the second to sixth embodiments instead of or in addition to the second planar structure 20B (see FIG. 13) according to the first embodiment.

[0299] The number of second planar structures 20B and the number of fourth planar structures 20D are adjusted as appropriate depending on the feedback capacitance Crss to be achieved. For example, SiC semiconductor device 1F may have a layout portion in which multiple second planar structures 20B and at least one fourth planar structure 20D are alternately arranged in the first direction X. For example, SiC semiconductor device 1F may have a layout portion in which at least one second planar structure 20B and multiple fourth planar structures 20D are alternately arranged in the first direction X.

[0300] The above-described embodiments can be implemented in other embodiments. For example, in each of the above-described embodiments, the planar insulating film 27 has a portion that extends horizontally along the first channel-covering portion 21A and the second channel-covering portion 21B. However, as shown in FIG. 22 , which shows a cross-sectional view of a modified example of the planar insulating film 27, the planar insulating film 27 may be formed such that either one or both of the first channel-covering portion 21A and the second channel-covering portion 21B does not have a portion that extends horizontally.

[0301] In each of the above-described embodiments, a configuration in which the relationship between the a-axis direction and the m-axis direction is interchanged may be adopted. A specific configuration in this case can be obtained by interchangeing the "a-axis direction (off direction)" and the "m-axis direction (direction perpendicular to the off direction)" in the above description and the accompanying drawings.

[0302] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0303] In the above-described embodiments, the chip 2 includes a single crystal SiC. However, the chip 2 may include a single crystal of a wide bandgap semiconductor other than a single crystal SiC. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of single crystal wide bandgap semiconductors include gallium nitride, diamond, and gallium oxide. Of course, the chip 2 may include a single crystal silicon.

[0304] In the above-described embodiments, an n-type drain region 7 is shown. However, a p-type semiconductor region may be adopted instead of the n-type drain region 7. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type semiconductor region may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 (drift region 6) by ion implantation.

[0305] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0306] [A1] A chip (2) having a main surface (3), channel regions (13A, 13B) formed in a surface layer portion of the main surface (3), drift regions (6, 14) adjacent to the channel regions (13A, 13B) in the surface layer portion of the main surface (3), a gate insulating film (21) formed on the main surface (3) and having channel covering portions (21A, 21B) covering the channel regions (13A, 13B) and a drift covering portion (21C) covering the drift regions (6, 14), and a gate insulating film (21) disposed on the channel covering portions (21A, 21B). a planar gate electrode (22, 60) facing the channel region (13A, 13B) in the vertical direction (Z) via the channel covering portion (21A, 21B); and a planar source electrode (29, 61) arranged on the drift covering portion (21C) at a distance from the planar gate electrode (22, 60) so as to face the planar gate electrode (22, 60) in the horizontal direction (X, Y), and facing the drift region (6, 14) in the vertical direction (Z) via the drift covering portion (21C).

[0307] [A2] The semiconductor device (1A to 1F) according to A1, wherein the planar source electrode (29, 61) includes a conductive material different from that of the planar gate electrode (22, 60).

[0308] [A3] The semiconductor device (1A to 1F) according to A1, wherein the planar source electrode (29, 61) includes the same type of conductive material as the planar gate electrode (22, 60).

[0309] [A4] The semiconductor device (1A to 1F) described in any one of A1 to A3, wherein the planar gate electrode (22, 60) is extended from above the channel covering portion (21A, 21B) onto above the drift covering portion (21C) and has a portion that faces the drift region (6, 14) in the vertical direction (Z) via the drift covering portion (21C).

[0310] [A5] A semiconductor device (1A-1F) according to any one of A1 to A4, further including a planar insulating film (27) covering the planar gate electrode (22, 60), and a source pad (50) arranged on the planar insulating film (27).

[0311] [A6] The semiconductor device (1A to 1F) according to A5, wherein the source pad (50) includes at least a part of the planar source electrode (29, 61).

[0312] [A7] A semiconductor device (1A to 1F) according to A5, wherein the source pad (50) is made of an electrode different from at least a portion of the planar source electrode (29, 61) and has a portion that is physically and electrically connected to at least a portion of the planar source electrode (29, 61).

[0313] [A8] The semiconductor device (1A-1F) according to any one of A1 to A7, further comprising an isolation insulating film (25, 62) disposed on the drift covering portion (21C) and having a portion facing the drift region (6, 14) in the vertical direction (Z) via the drift covering portion (21C), wherein the planar source electrode (29, 61) faces the planar gate electrode (22, 60) in the horizontal direction (X, Y) via the isolation insulating film (25, 62) and is electrically insulated from the planar gate electrode (22, 60) by the isolation insulating film (25, 62).

[0314] [A9] A semiconductor device (1A to 1F) according to A8, wherein the isolation insulating film (25, 62) extends in the vertical direction (Z) along the wall surface of the planar gate electrode (22, 60) and is connected to the gate insulating film (21).

[0315] [A10] The semiconductor device (1A-1F) according to any one of A1 to A9, further comprising an intermediate insulating film (24) having a thickness less than that of the planar gate electrode (22, 60) and covering the drift covering portion (21C) at a distance from the electrode surface of the planar gate electrode (22, 60) toward the gate insulating film (21), wherein the planar source electrode (29, 61) is disposed on the intermediate insulating film (24) and faces the drift region (6, 14) in the vertical direction (Z) via the intermediate insulating film (24) and the drift covering portion (21C).

[0316] [A11] A semiconductor device (1A to 1F) according to A10, wherein the intermediate insulating film (24) covers the drift covering portion (21C) in a film form and has a portion that contacts the wall surface of the planar gate electrode (22, 60).

[0317] [A12] A plurality of the channel regions (13A, 13B) are formed at intervals in a surface layer portion of the main surface (3), the drift region (6, 14) is partitioned into regions between the plurality of the channel regions (13A, 13B), the gate insulating film (21) has a plurality of the channel covering portions (21A, 21B) covering the plurality of the channel regions (13A, 13B), and the planar gate electrode (22, 60) has a through hole (23) exposing the drift covering portion (21C) and a plurality of front The semiconductor device (1A to 1F) according to any one of A1 to A11, further comprising a plurality of electrode portions (22A, 22B) partitioned on the plurality of channel covering portions (21A, 21B) by the through holes (23) so as to face the plurality of channel regions (13A, 13B) via the channel covering portions (21A, 21B), and the planar source electrode (29, 61) is disposed within the through holes (23) and faces the plurality of electrode portions (22A, 22B) in the horizontal direction (X, Y).

[0318] [A13] The semiconductor device (1A to 1F) according to A12, wherein the planar gate electrode (22, 60) is partitioned in a ring-like, striped or lattice shape by one or more of the through holes (23) in a planar view.

[0319] [A14] A semiconductor device (1A to 1F) according to any one of A1 to A13, wherein the chip (2) is a SiC chip (2) including a SiC single crystal.

[0320] [A15] A chip (2) having a main surface (3), a first channel region (13A) formed in a surface layer portion of the main surface (3), a second channel region (13B) formed in the surface layer portion of the main surface (3) at a distance from the first channel region (13A), a drift region (6, 14) partitioned in a region between the first channel region (13A) and the second channel region (13B) in the surface layer portion of the main surface (3), a first portion (21A) formed on the main surface (3) and covering the first channel region (13A), and a second channel region (13B) formed in the surface layer portion of the main surface (3). a gate insulating film (21) having a second portion (21B) covering a first channel region (13A) of the first insulating film (21); a planar gate electrode (22, 60) disposed on the first portion (21A) and facing the first channel region (13A) in a vertical direction (Z) via the first portion (21A); and a planar source electrode (29, 61) disposed on the second portion (21B) so as to face the planar gate electrode (22, 60) in a horizontal direction (X, Y), and facing the second channel region (13B) in the vertical direction (Z) via the second portion (21B).

[0321] [A16] The semiconductor device (1A to 1F) according to A15, wherein the gate insulating film (21) has a third portion (21C) covering the drift region (6, 14), the planar gate electrode (22, 60) is drawn from the first portion (21A) to the third portion (21C) and has a portion facing the drift region (6, 14) in the vertical direction (Z) via the third portion (21C), and the planar source electrode (29, 61) is drawn from the second portion (21B) to the third portion (21C) and has a portion facing the drift region (6, 14) in the vertical direction (Z) via the third portion (21C).

[0322] [A17] The semiconductor device (1A to 1F) according to A15 or A16, wherein the planar source electrode (29, 61) includes the same conductive material as the planar gate electrode (22, 60).

[0323] [A18] The semiconductor device (1A to 1F) according to A17, wherein the planar gate electrode (22, 60) includes polysilicon, and the planar source electrode (29, 61) includes polysilicon.

[0324] [A19] A semiconductor device (1A to 1F) according to any one of A15 to A18, further including an isolation insulating film (25, 62) interposed between the planar gate electrode (22, 60) and the planar source electrode (29, 61) and facing the drift region (6, 14) in the vertical direction (Z).

[0325] [A20] A semiconductor device (1A to 1F) according to A19, wherein the thickness of the isolation insulating film (25, 62) along the horizontal direction (X, Y) is greater than the thickness of the gate insulating film (21) along the vertical direction (Z).

[0326] [A21] A semiconductor device (1A to 1F) according to any one of A15 to A20, further including: a planar insulating film (27) covering the planar gate electrode (22, 60) and the planar source electrode (29, 61); and a source pad (50) arranged on the planar insulating film (27), electrically insulated from the planar gate electrode (22, 60) by the planar insulating film (27), and electrically connected to the planar source electrode (29, 61) through the planar insulating film (27).

[0327] [A22] A semiconductor device (1A to 1F) according to any one of A15 to A21, wherein the chip (2) is a SiC chip (2) including a SiC single crystal.

[0328] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0329] DESCRIPTION OF SYMBOLS 1A SiC semiconductor device 1B SiC semiconductor device 1C SiC semiconductor device 1D SiC semiconductor device 1E SiC semiconductor device 1F SiC semiconductor device 2 Chip 3 First main surface 13A First channel region 13B Second channel region 14 Drift region 21 Gate insulating film 21A First channel covering portion (first portion) 21B Second channel covering portion (second portion) 21C Drift covering portion (third portion) 22 Planar gate electrode 22A First electrode portion 22B Second electrode portion 23 Through hole 24 Intermediate insulating film 25 Isolation insulating film 27 Planar insulating film 29 Planar source electrode 50 Source pad 60 Planar gate electrode 61 Planar source electrode 62 Isolation insulating film X First direction (horizontal direction) Y Second direction (horizontal direction) Z Vertical direction

Claims

1. a SiC chip having a main surface; a channel region formed in a surface layer portion of the main surface; a drift region adjacent to the channel region in a surface layer portion of the main surface; a gate insulating film formed on the main surface, the gate insulating film having a channel covering portion that covers the channel region and a drift covering portion that covers the drift region; a planar gate electrode disposed on the channel covering portion and facing the channel region in a vertical direction with the channel covering portion interposed therebetween; a planar source electrode disposed on the drift covering portion at a distance from the planar gate electrode so as to face the planar gate electrode in the horizontal direction, and facing the drift region via the drift covering portion in the vertical direction.

2. The SiC semiconductor device of claim 1 , wherein the planar source electrode comprises a different conductive material than the planar gate electrode.

3. The SiC semiconductor device of claim 1 , wherein the planar source electrode comprises the same conductive material as the planar gate electrode.

4. 2. The SiC semiconductor device according to claim 1, wherein the planar gate electrode extends from above the channel covering portion onto above the drift covering portion and has a portion facing the drift region in the vertical direction via the drift covering portion.

5. A plurality of the channel regions are formed at intervals on a surface layer portion of the main surface, the drift region is partitioned into regions between the plurality of channel regions, the gate insulating film has a plurality of the channel covering portions that cover a plurality of the channel regions, the planar gate electrode has a through hole exposing the drift covering portion, and a plurality of electrode portions defined by the through hole on the plurality of channel covering portions so as to face the plurality of channel regions via the plurality of channel covering portions; The SiC semiconductor device according to claim 1 , wherein the planar source electrode is disposed in the through hole and faces a plurality of the electrode portions in the horizontal direction.

6. A SiC semiconductor device as described in Claim 5, wherein the planar gate electrode is partitioned into a ring-shaped, striped or lattice-shaped pattern by one or more of the through holes in a planar view.

7. a planar insulating film covering the planar gate electrode; 7. The SiC semiconductor device according to claim 1, further comprising: a source pad disposed on the planar insulating film.

8. The SiC semiconductor device according to claim 7 , wherein the source pad includes at least a portion of the planar source electrode.

9. 8. The SiC semiconductor device according to claim 7, wherein the source pad is made of an electrode different from at least a portion of the planar source electrode and has a portion physically and electrically connected to at least a portion of the planar source electrode.

10. an isolation insulating film disposed on the drift covering portion and having a portion facing the drift region with the drift covering portion interposed therebetween in the vertical direction; 7. The SiC semiconductor device according to claim 1, wherein the planar source electrode faces the planar gate electrode in the horizontal direction via the isolation insulating film and is electrically insulated from the planar gate electrode by the isolation insulating film.

11. The SiC semiconductor device according to claim 10 , wherein the isolation insulating film extends in the vertical direction along a wall surface of the planar gate electrode and is connected to the gate insulating film.

12. an intermediate insulating film having a thickness less than that of the planar gate electrode and covering the drift covering portion at a distance from an electrode surface of the planar gate electrode toward the gate insulating film; 7. The SiC semiconductor device according to claim 1, wherein the planar source electrode is disposed on the intermediate insulating film and faces the drift region in the vertical direction via the intermediate insulating film and the drift covering portion.

13. The SiC semiconductor device according to claim 12 , wherein the intermediate insulating film covers the drift covering portion in a film form and has a portion in contact with a wall surface of the planar gate electrode.

14. a SiC chip having a main surface; a first channel region formed in a surface layer portion of the main surface; a second channel region formed in a surface layer portion of the main surface at a distance from the first channel region; a drift region defined in a surface layer portion of the main surface between the first channel region and the second channel region; a gate insulating film formed on the main surface and having a first portion covering the first channel region and a second portion covering the second channel region; a planar gate electrode disposed on the first portion and facing the first channel region in a vertical direction with the first portion interposed therebetween; a planar source electrode disposed on the second portion so as to face the planar gate electrode in the horizontal direction, and facing the second channel region via the second portion in the vertical direction.

15. the gate insulating film has a third portion covering the drift region; the planar gate electrode has a portion that is drawn from the first portion to the third portion and faces the drift region in the vertical direction via the third portion; 15. The SiC semiconductor device according to claim 14, wherein the planar source electrode has a portion that is drawn from the second portion to the third portion and faces the drift region in the vertical direction with the third portion interposed therebetween.

16. The SiC semiconductor device of claim 14 , wherein the planar source electrode comprises the same conductive material as the planar gate electrode.

17. the planar gate electrode comprises polysilicon; The SiC semiconductor device of claim 16 , wherein the planar source electrode comprises polysilicon.

18. 18. The SiC semiconductor device according to claim 14, further comprising an isolation insulating film interposed between the planar gate electrode and the planar source electrode and facing the drift region in the vertical direction.

19. 19. The SiC semiconductor device according to claim 18, wherein the thickness of said isolation insulating film in said horizontal direction is larger than the thickness of said gate insulating film in said vertical direction.

20. a planar insulating film covering the planar gate electrode and the planar source electrode; The SiC semiconductor device according to any one of claims 14 to 17, further comprising: a source pad disposed on the planar insulating film, electrically insulated from the planar gate electrode by the planar insulating film, and electrically connected to the planar source electrode through the planar insulating film.