Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention suppresses a decline in the reliability of an insulated gate-type semiconductor device (100) which has a trench structure. A semiconductor device which is equipped with a source electrode (11) which is electrically connected to a source region adjacent to a trench (6) in a first region, and gate wiring (18) provided on the top surface of a gate electrode (8) provided inside a trench in a second region, wherein the radius of curvature (Re) of a gate insulated film provided in an upper corner section of the trench in the second region is greater than the radius of curvature (Rc) of a gate insulated film provided in an upper corner section of the trench in the first region.

Description

Semiconductor device and method for manufacturing the same

[0001] The technology disclosed in this specification relates to semiconductor technology.

[0002] BACKGROUND ART In power electronics devices, insulated gate semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) are widely used as switching elements for controlling power supply to loads such as motors.

[0003] Some of these insulated gate semiconductor devices have a trench structure in which the gate electrode is buried in the semiconductor layer. Insulated gate semiconductor devices with a trench structure can have a higher channel width density in the active region than insulated gate semiconductor devices (planar semiconductor devices) that do not have a trench structure in which the gate electrode is formed on the surface of the semiconductor layer. Therefore, the electrical resistance per unit area of ​​the semiconductor device can be reduced when it is in the on state.

[0004] Conventionally, insulated gate semiconductor devices having a trench structure have a termination region provided around an active region, in which a gate electrode and a gate insulating film are formed inside the trench and around the upper corners of the trench opening on the active region side. In this case, when a gate voltage is applied to turn the semiconductor device on, an electric field concentrates around the bottom surface of the trench and the upper corners, causing insulation degradation of the gate insulating film around the bottom surface of the trench and the upper corners. As a result, the reliability of the semiconductor device may be reduced.

[0005] To solve this problem, a method is known in which an electrically conductive electric field relaxation region is provided at the bottom of the trench to relax the electric field acting on the gate insulating film at the bottom of the trench (see, for example, Patent Document 1).

[0006] Also, a method is known in which a structure is formed having a narrow, deep trench in the active region and a wide, shallow trench in the termination region, and then a CMP (Chemical Mechanical Polishing) process or a combination of the CMP process and an etch-back process is used to planarize the gate electrodes formed in the trenches in the active region and the termination region, thereby preventing the upper corners of the trench from being covered by the gate electrode (see, for example, Patent Document 2).

[0007] Special table 2001-511315 publication Special table 2006-520091 publication

[0008] To set the potential of the gate electrode, a gate contact (contact hole) must be provided to the gate electrode formed in the gate trench within the cell array. Because the gate trench in the cell array is formed with minimum processing dimensions, there is a concern of misalignment with the contact mask. Therefore, instead of providing a gate contact within the cell, the gate contact is sometimes provided on the top surface of the polysilicon in a wide trench in the termination region.

[0009] Even in such a case, it is unavoidable that the upper corners of the trench are covered with polysilicon, which causes an electric field to concentrate on the gate insulating film at the upper corners of the trench that are covered with polysilicon, resulting in insulation degradation of the gate insulating film and reducing the reliability of the semiconductor device.

[0010] On the other hand, the method of providing an electric field relaxation region at the bottom of the trench may not be able to suppress insulation deterioration around the upper corners of the trench. Also, the method using the CMP process requires extremely small influences such as warpage of the semiconductor substrate, unevenness of the substrate surface, uniformity of the in-plane thickness of the film formed on the semiconductor substrate, and unevenness of the film due to the influence of particles, etc., making it difficult to adopt in practice.

[0011] Furthermore, when a wide trench is formed in the termination region and a gate insulating film and a gate electrode are successively deposited, the exposed area of ​​the gate electrode increases in the subsequent etch-back process, which may result in the gate electrode being etched away, resulting in a thinned gate electrode, or even disappearance of the gate electrode. This may result in unstable operation of the insulated gate semiconductor device (reduced reliability of the semiconductor device). Furthermore, it may be impossible to suppress insulation degradation around the upper corners of the trench.

[0012] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for suppressing a decrease in the reliability of an insulated gate semiconductor device having a trench structure.

[0013] A semiconductor device according to a first aspect of the technology disclosed in the present specification includes a first conductivity type drift layer, a second conductivity type base region provided in a surface layer of the drift layer, a plurality of first conductivity type source regions provided in a surface layer of the base region, at least one trench extending from an upper surface of the drift layer through the base region and into the drift layer, a second conductivity type protection layer provided in the drift layer below the trench, a gate insulating film provided along the inside of the trench including the upper corners of the trench, and a gate insulating film extending from the gate insulating film to the inside of the trench. a gate electrode provided within the trench, a source electrode electrically connected to the source region adjacent to the trench, and a gate wiring provided on an upper surface of the gate electrode provided within the trench, wherein, of the regions separated by the trench in a plan view, the region where the source electrode is provided is defined as a first region, and the region where the gate wiring is provided is defined as a second region, and the radius of curvature of the gate insulating film provided at the upper corner of the trench in the second region is larger than the radius of curvature of the gate insulating film provided at the upper corner of the trench in the first region.

[0014] According to at least the first aspect of the technique disclosed in the present specification, electric field concentration is suppressed even when a gate voltage is applied, and therefore breakdown of the gate insulating film is suppressed.

[0015] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below.

[0016] 3 is a plan view schematically showing an example of the configuration of a semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing a part of the configuration of a semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view showing a part of the configuration of a semiconductor device according to an embodiment. FIG. 6 is a cross-sectional view showing an example of the configuration of a cell portion in the figure. FIG. 7 is a cross-sectional view showing an example of the configuration of a gate contact portion in the active region 20 of FIG. 3. FIG. 8 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 9 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 10 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 11 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 12 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 13 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 14 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. FIG. 15 is a diagram showing an example of a manufacturing method of a semiconductor device according to an embodiment. Fig. 1 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to an embodiment; Fig. 2 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to an embodiment; Fig. 3 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to an embodiment; Fig. 4 is a cross-sectional view schematically showing an example of the configuration of a semiconductor device according to an embodiment.

[0017] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0018] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0019] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0020] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0021] Furthermore, in the description of this specification, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to make it easier to understand the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0022] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0023] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude the interposition of another component "C" between A and B.

[0024] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described below. Note that, for the sake of simplicity, details of semiconductor layers and electrodes may be omitted in the drawings.

[0025] 1 is a plan view schematically illustrating an example of the configuration of a semiconductor device 100 according to the present embodiment. As illustrated in the example of FIG. 1, the semiconductor device 100 includes an active region 20 and a termination region 30.

[0026] The active region 20 has a plurality of gate trenches 6 arranged in a plan view. The termination region 30 has a termination trench 16 and a gate wiring 18 formed so as to overlap the termination trench 16 in a plan view. A gate trench 26 is also formed in an inner portion of the termination region 30.

[0027] The active region 20 is provided in the center of the semiconductor device 100. The active region 20 is a region that allows a current to flow in the semiconductor device 100 when a voltage is applied to gate trenches 6 formed in a stripe shape within the active region 20.

[0028] When the semiconductor device 100 is in an on-state, a positive voltage is applied to the gate trench 6, whereby electrons are induced at the interface between the gate insulating film and the semiconductor layer, causing a current to flow.

[0029] The termination region 30 is formed around the active region 20 in a plan view. The termination region 30 has a termination trench 16, a gate insulating film 17, a gate electrode 8, a gate wiring 18, and a guard ring for alleviating the electric field. The termination trench 16 is a trench provided in the termination region 30.

[0030] In this embodiment, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the semiconductor device may also be one in which the first conductivity type is p-type and the second conductivity type is n-type.

[0031] Although the present embodiment describes a case where the semiconductor device is a MOSFET, the semiconductor device may be an IGBT. Although the present embodiment describes a case where the drift layer included in the semiconductor layer is formed of silicon carbide (SiC), the drift layer may be a wide bandgap semiconductor such as gallium nitride (GaN) or diamond, which has a bandgap larger than that of silicon.

[0032] 1 , in the semiconductor layer of semiconductor device 100, gate trench 6 is formed in active region 20, and gate trench 26 and termination trench 16 are formed in termination region 30. Termination trench 16 surrounds gate trench 6 and gate trench 26 in plan view, and is formed to be spaced apart from gate trench 6 and gate trench 26.

[0033] 1, the gate trenches 6 are formed in a stripe shape in plan view. A plurality of cells (cell portions) are formed in each region partitioned by the gate trenches 6 in the active region 20, and the cells function as MOSFETs.

[0034] 2 and 3 are cross-sectional views showing a part of the configuration of a semiconductor device according to this embodiment. FIG. 4 is a plan view showing a part of the configuration of a semiconductor device according to this embodiment. The configurations shown in FIGS. 2, 3, and 4 correspond to the area 1000 surrounded by the dashed line in FIG. 1. The cross section shown in FIG. 2 corresponds to the A-A' cross section shown in FIG. 4. Similarly, the cross section shown in FIG. 3 corresponds to the B-B' cross section shown in FIG. 4.

[0035] 2 and 3 , semiconductor device 100, which is a MOSFET, includes an n-type silicon carbide semiconductor substrate 1 and a semiconductor layer 2 formed by epitaxial growth on the upper surface of silicon carbide semiconductor substrate 1. Semiconductor device 100 also includes a drain electrode 12 on the lower surface of silicon carbide semiconductor substrate 1.

[0036] In the active region 20 of the semiconductor layer 2, a drift layer 3 made of an n-type silicon carbide semiconductor, a p-type base region 4 provided in the surface layer of the drift layer 3, an n-type source region 5 selectively provided in the surface layer of the base region 4, a gate trench 6 formed to penetrate the source region 5 and the base region 4 and have a bottom surface located within the drift layer 3, and a p-type diffusion protection layer 9 provided below the bottom surface of the gate trench 6 are formed.

[0037] On the other hand, in the termination region 30 of the semiconductor layer 2, there are formed a drift layer 3 made of an n-type silicon carbide semiconductor, a p-type base region 4 provided in the surface layer of the drift layer 3, a gate trench 26 and a termination trench 16 formed so that their bottom surfaces are located deeper than the base region 4 and within the n-type drift layer 3, a p-type diffusion protection layer 9 provided below the bottom surface of the gate trench 26, and a p-type termination protection layer 19 provided below the bottom surface of the termination trench 16.

[0038] When semiconductor device 100 is configured as an IGBT, silicon carbide semiconductor substrate 1 may have a p-type conductivity.

[0039] Here, the n-type impurity concentration of the drift layer 3 is, for example, 1×10 １４ cm －３ or more, and 1 x 10 １７ cm －３ The thickness of the drift layer 3 may be, for example, not less than 5 μm and not more than 200 μm.

[0040] The p-type impurity concentration of the base region 4 is, for example, 1×10 １７ cm －３ or more, and 1 x 10 ２０ cm －３ It may be the following:

[0041] The n-type impurity concentration of the source region 5 is equal to or higher than the p-type impurity concentration of the base region 4 and is 1×10 ２１ cm －３ It may be the following:

[0042] The p-type impurity concentration of the diffusion protection layer 9 and the p-type impurity concentration of the termination protection layer 19 are, for example, 1×10１７ cm －３ or more, and 1 x 10 １９ cm －３ The p-type impurity concentration of the diffusion protection layer 9 is preferably the same as or equal to or higher than the p-type impurity concentration of the termination protection layer 19.

[0043] 2 and 3, a gate insulating film 7 is formed on the side and bottom surfaces of the gate trench 6, and a gate electrode 8 made of polysilicon is embedded in the gate trench 6 via the gate insulating film 7. However, in Fig. 3, the gate insulating film 7 and gate electrode 8 in the gate trench 6 that overlap with the gate wiring 18 in a plan view are formed to extend to the upper surface of the semiconductor layer 2 (the upper surface of the semiconductor layer 2 on which the base region 4 or the source region 5 is formed).

[0044] Similarly, a gate insulating film 7 having the same thickness as the gate insulating film 7 in the gate trench 6 is formed on the side and bottom surfaces of the gate trench 26, and a gate electrode 8 made of polysilicon is buried in the gate trench 26 via the gate insulating film 7. The gate electrode 8 in the gate trench 26 is formed up to the upper surface of the semiconductor layer 2. Gate wiring 18 is provided across the upper surfaces of the gate electrodes 8 provided in the multiple gate trenches 6.

[0045] A gate electrode 8 is formed through a contact hole (gate contact 34) in the polysilicon formed to extend to the upper surface of the semiconductor layer 2. The gate electrode 8 extends to a bonding pad for wire bonding connection when the chip is assembled.

[0046] As shown in FIGS. 2, 3 and 4, an electrically non-functional gate trench 26 is formed at the boundary between the termination region 30 and the active region 20.

[0047] In the termination region 30, a termination trench 16 is formed which is wider than the gate trenches 6 and 26, and a gate insulating film 7 having the same thickness as the gate insulating film 7 in the gate trench 6 is formed on the bottom and side surfaces of the termination trench 16. An interlayer insulating film 13 (oxide film) is deposited in a portion of the termination trench 16. A gate electrode 8 is formed in another portion of the termination trench 16.

[0048] A gate electrode 8 is formed in the gate trench 6 in the cell portion. Polysilicon (gate electrode 8) is also deposited in the gate trench 26 at the boundary between the termination region 30 and the active region 20.

[0049] An interlayer insulating film 13 is formed to cover the upper surface of the semiconductor layer 2, including the gate electrode 8. A gate wiring 18 is formed to contact the gate electrode 8 exposed through a gate contact 34, which is an opening formed in the interlayer insulating film 13. The gate contact 34 is classified into two types: one that exposes the gate electrode 8 in the termination trench 16 in the termination region 30, and one that exposes the gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2 in the active region 20. A source electrode 11 is formed to contact, via an ohmic electrode 32, the upper surfaces of the base region 4 and the source region 5 exposed through a source contact 31, which is an opening formed in the interlayer insulating film 13.

[0050] An oxide film (interlayer insulating film 13) is formed in the termination trench 16 in the termination region 30, whereas polysilicon is formed in the gate trench 6 and the gate trench 26, meaning that different materials are formed in the two regions.

[0051] Furthermore, while the termination trench 16 in the termination region 30 is processed with wide dimensions, the gate trench 6 or gate trench 26 in the cell section is formed with a minimum processing line width. Because of the structural differences between the two, the thermal history during wafer processing results in different expansion coefficients depending on the material. This generates residual stress, which in turn causes differences in the electrical characteristics of the elements and also affects the reliability of the semiconductor device.

[0052] In each cell arranged in the active region 20, the stress increases toward the outermost periphery of the gate trench. As a result, the failure rate of the gate insulating film 7 increases toward the outermost periphery of the gate trench. For this reason, by electrically isolating the outermost cells from the other cells and floating the gate potential, it is possible to suppress element failure.

[0053] Fig. 5 is a cross-sectional view showing an example of the configuration of the cell portion in Fig. 2. As shown in the example in Fig. 5, the upper corners of the gate trench 6 have a rounded shape.

[0054] Fig. 6 is a cross-sectional view showing an example of the configuration of a gate contact portion in the active region 20 of Fig. 3. As shown in the example of Fig. 6, the upper corners of the gate trench 6 have a rounded shape.

[0055] 5 , the upper corners of the semiconductor layer 2 in the cell portion where the gate electrode 8 is buried in the gate trench 6 are rounded to a shape indicated by a radius of curvature Rc. Therefore, the shape of the gate insulating film 7 formed in that portion also has a rounded shape indicated by a radius of curvature Rc.

[0056] 6 , the upper corner of the semiconductor layer 2 of the gate contact portion including the gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2 has a rounded shape indicated by the radius of curvature Re. Therefore, the shape of the gate insulating film 7 formed in that portion also has a rounded shape indicated by the radius of curvature Re.

[0057] Comparing the radii of curvature of the gate trench 6 directly below the gate insulating film 7, Re>Rc, and the gate contact portion has a gentler shape. The small radius of curvature Rc of the cell portion is, for example, greater than 0 μm and equal to or less than 0.1 μm. The radius of curvature Re of the gate contact portion is, for example, equal to or greater than 0.1 μm and equal to or less than 2 μm. In particular, if the radius of curvature Re of the gate contact portion is equal to or greater than 0.5 μm and equal to or less than 2 μm, good characteristics can be obtained.

[0058] A gate insulating film 7 and a gate electrode 8 are formed at the upper corners of the gate trench 6 in the gate contact portion. Since the radius of curvature Re is larger than the radius of curvature Rc, it is possible to prevent a high electric field from being applied to the gate insulating film 7 formed at the upper corners of the gate trench 6 when the MOSFET is turned on.

[0059] For example, when a gate voltage of 20 V is applied, if the thickness of the gate insulating film 7 is 50 nm, an electric field of 4 MV / cm is applied to the sidewall portion of the gate trench 6. In this case, if the gate contact portion is formed with a gate insulating film 7 having a curvature radius Re, it is possible to prevent a high electric field from being applied to the gate insulating film 7 formed at the upper corner portion of the gate trench 6, and thereby prevent the insulating film from breaking down.

[0060] From the viewpoint of the reliability of the gate insulating film 7, it is desirable to design the radius of curvature Re so as to suppress the increase in the electric field applied to the gate insulating film 7 in the vicinity of the gate trench 6 to 5% or less.

[0061] It should be noted that the gate contact portion shown in FIG. 6 is assumed to be provided in the active region 20, but the upper corner of the termination trench 16 may be rounded (in a rounded shape) at the gate contact portion in the termination region 30 (the portion where the gate wiring 18 and the gate electrode 8 are connected via the gate contact 34).

[0062] In this embodiment, when an ohmic electrode is provided between a source electrode and a semiconductor layer, the source electrode and the ohmic electrode may be collectively referred to as the source electrode without distinction. Similarly, when an ohmic electrode is provided between a gate bonding pad, which is a metal electrode, and a gate electrode made of a semiconductor or the like, the gate bonding pad and the ohmic electrode may be collectively referred to as the gate bonding pad without distinction.

[0063] That is, in this embodiment, the source electrode and the gate bonding pad are not limited to being made of a single metal, but may have a structure in which a material suitable for bonding with the semiconductor layer is provided at the junction with the semiconductor layer. Furthermore, the ohmic electrode is not limited to a metal, but may be a compound of a metal and a semiconductor, or a silicide. Furthermore, the ohmic electrode may be made of a conductor such as a multilayer metal or semiconductor.

[0064] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 100 according to this embodiment will be described.

[0065] 7 to 18 are diagrams showing an example of a method for manufacturing a semiconductor device according to this embodiment.

[0066] 7 to 11 show examples of the process up to forming the diffusion protection layer 9 below the bottom surface of the gate trench 6 and the termination protection layer 19 below the bottom surface of the termination trench 16. Note that FIGS. 7 to 10 correspond to the AA' cross section in FIG.

[0067] 12 to 15 show examples of processes from forming the diffusion protection layer 9 and the termination protection layer 19 to forming the gate electrode 8. Note that Figures 12 and 13 correspond to the AA' cross section in Figure 15. Also, Figure 14 corresponds to the BB' cross section in Figure 15.

[0068] 16 to 18 show an example of the process from the formation of the gate electrode 8 to the completion of the semiconductor device 100.

[0069] First, as shown in FIG. 7, an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type semiconductor layer 2 is epitaxially grown on the upper surface thereof by chemical vapor deposition (CVD).

[0070] At this time, the n-type impurity concentration of the n-type semiconductor layer 2 is, for example, 1×10 １４ cm －３ or more, and 1 x 10 １７ cm －３ The thickness of the semiconductor layer 2 is, for example, not less than 5 μm and not more than 200 μm.

[0071] 7, aluminum (Al) ions, which are p-type impurities, are implanted into the surface layer of the epitaxially grown semiconductor layer 2 to form the base region 4. The depth of the Al ion implantation is set within a range not exceeding the thickness of the semiconductor layer 2, and is set to, for example, 0.3 μm or more and 3 μm or less. The impurity concentration of the implanted Al is set higher than the n-type impurity concentration of the epitaxially grown semiconductor layer 2, and the p-type impurity concentration of the base region 4 is set to, for example, 1×10 １７ cm －３ or more, and 1 x 10 ２０ cm －３ As a result, the region of the semiconductor layer 2 other than the base region 4 deeper than the Al ion implantation depth becomes the n-type drift layer 3.

[0072] The base region 4 may be formed by epitaxially growing a p-type semiconductor, and in this case, the p-type impurity concentration and thickness of the base region 4 may be the same as when the base region 4 is formed by ion implantation.

[0073] Next, as shown in FIG. 7, nitrogen (N), an n-type impurity, is selectively ion-implanted into the surface layer of the base region 4 to form the source region 5. The source region 5 is formed in a pattern corresponding to the layout of the gate electrode 8 to be formed in a later process. The depth of the N ion implantation is shallower than the thickness of the base region 4. The impurity concentration of the N ion implantation is equal to or greater than the p-type impurity concentration of the base region 4 and is 1×10 ２１ cm －３ The following applies.

[0074] The order of the step of ion implanting Al to form the base region 4 and the step of ion implanting N to form the source region 5 may be reversed. Alternatively, after N ions are implanted into the entire surface layer of the base region 4 to form an n-type semiconductor layer, a mask may be applied to the portion to be left as the source region 5, and Al ions may be implanted again into the unmasked region (region other than the source region 5) to return to the p-type base region 4. In this case, the impurity concentration of the Al ions implanted again may be made higher than the impurity concentration of Al in the portion of the base region 4 adjacent to the drift layer 3, thereby reducing the contact resistance with the source electrode.

[0075] 8 , a silicon oxide film 41 is formed on the upper surface of the semiconductor layer 2, and an etching mask 42 is further formed on the upper surface of the silicon oxide film 41. The silicon oxide film 41 is formed by deposition to a thickness of, for example, 1 μm or more and 2 μm or less, and then the etching mask 42 is formed on the upper surface of the silicon oxide film 41. A pattern having openings corresponding to regions where the gate trench 6, the gate trench 26, and the termination trench 16 will be formed is formed in the etching mask 42 using photolithography technology.

[0076] Next, reactive ion etching (RIE) is performed using the etching mask 42 as a mask to pattern the silicon oxide film 41. That is, the pattern of the etching mask 42 is transferred to the silicon oxide film 41, and the silicon oxide film 41 is used as an etching mask for the semiconductor layer 2.

[0077] Next, as shown in an example in FIG. 9 , using the patterned silicon oxide film 41 as a mask, gate trenches 6 and 26 that penetrate the source region 5 and the base region 4, and a termination trench 16 that penetrates the base region 4 are formed in the semiconductor layer 2 by RIE processing.

[0078] The depth of gate trench 6, gate trench 26 and termination trench 16 is equal to or greater than the depth of base region 4 formed in semiconductor layer 2 by ion implantation, and may be, for example, 1.0 μm or more and 6.0 μm or less.

[0079] Using the silicon oxide film 41 as a mask, the gate trench 6, the gate trench 26, and the termination trench 16 are formed. After the gate trench 6, the gate trench 26, and the termination trench 16 are formed, as shown in FIG. 10 , an implantation mask 43 having openings of the same pattern as the silicon oxide film 41 is formed, and a p-type diffusion protection layer 9 is formed at the bottom of the gate trench 6 and the bottom of the gate trench 26 by ion implantation of Al. Similarly, a p-type termination protection layer 19 is formed at the bottom of the termination trench 16 by ion implantation of Al. The impurity concentration of the implanted Al is, for example, 1×10 １７ cm －３ or more, and 1 x 10 １９ cm －３ The depth of the ion implantation is preferably, for example, 0.1 μm or more and 2.0 μm or less. The impurity concentration of Al ions to be implanted may be determined based on the electric field applied to the gate insulating film 7 when a voltage equal to the breakdown voltage of the semiconductor device 100 is applied between the drain electrode 12 and the source electrode 11 of the semiconductor device 100.

[0080] By adjusting the thickness of silicon oxide film 41 and etching conditions so that silicon oxide film 41 remains even after gate trench 6 and termination trench 16 are formed using silicon oxide film 41 as a mask, the remaining silicon oxide film 41 can be used as a mask instead of implantation mask 43 when forming diffusion protection layer 9 and termination protection layer 19. This makes it possible to simplify the manufacturing process and reduce manufacturing costs.

[0081] Furthermore, when forming the diffusion protection layer 9, Al ions are implanted obliquely into the opening of the gate trench 6, thereby forming a p-type semiconductor layer in the drift layer 3 in contact with the side surface of the gate trench 6, and the p-type diffusion protection layer 9 and the p-type base region 4 can be connected by the p-type semiconductor layer. This allows electrical connection between the diffusion protection layer 9 and the source electrode 11.

[0082] After forming the diffusion protection layer 9 and the termination protection layer 19, the implantation mask 43 used for the ion implantation is removed, and an annealing process is performed using a heat treatment device to activate the implanted impurities. The annealing process is performed in an inert gas atmosphere such as argon (Ar) or in a vacuum, for example, at a temperature of 1300° C. or higher and 1900° C. or lower for 30 seconds or longer and 1 hour or shorter.

[0083] Next, as shown in an example in FIG. 12 , the implantation mask 43 is removed and the upper surface of the semiconductor layer 2 is oxidized at the AA′ cross section and the BB′ cross section in FIG. 15 . The thickness of the oxide film formed on the upper surface of the semiconductor layer 2 is preferably, for example, approximately 5 nm or more and 100 nm or less. The oxide film is then removed by hydrofluoric acid-based wet etching. This process forms a rounded shape (with a radius of curvature Rc) at the upper corners of each trench.

[0084] Next, as shown in FIG. 13, an oxide film 41A is deposited, and then, as shown in FIG. 14, only the oxide film 41A in the portion corresponding to the region where the gate contact of the active region 20 is to be formed is opened.

[0085] 14, in the B-B' cross section of Fig. 15, the oxide film 41A is etched to expose a portion of the semiconductor layer 2, and a rounded shape (with a radius of curvature Re) is formed at the upper corner of the gate trench 6 in the exposed semiconductor layer 2. The B-B' cross section of Fig. 15 shows a state in which an area spanning a plurality of gate trenches 6 is exposed from the oxide film 41A.

[0086] The rounded shape may be formed by CDE (chemical dry etching: isotropic etching) or other etching treatment (such as heat treatment in a hydrogen atmosphere). Thereafter, the oxide film 41A is removed.

[0087] In the process shown in FIG. 12, a rounded shape (with a radius of curvature Rc) was formed at the upper corner of the trench, but by further performing heat treatment in a CDE or hydrogen atmosphere in the process shown in FIG. 14, a rounded shape with an even larger radius of curvature can be formed at the upper corner of the gate trench 6.

[0088] As described above, the radius of curvature Re of the gate insulating film 7 provided at the upper corners of the gate trench 6 (or the termination trench 16) in the region where the gate wiring 18 is provided on the upper surface is larger than the radius of curvature Rc of the gate insulating film 7 provided at the upper corners of the gate trench 6 in the region where the source electrode 11 is electrically connected to the adjacent source region 5. With this configuration, even if a gate voltage is applied to the gate insulating film 7 formed in a round shape with a larger radius of curvature (radius of curvature Re), the large radius of curvature effectively suppresses electric field concentration, thereby preventing the application of a high electric field. As a result, breakdown of the gate insulating film 7 is suppressed.

[0089] Next, the gate electrode 8 is formed. Note that Fig. 16 corresponds to the AA' cross section of Fig. 18. Fig. 17 corresponds to the BB' cross section of Fig. 18.

[0090] 16 , a gate insulating film 7 and a gate electrode 8 are formed in the gate trench 6, the gate trench 26, and the termination trench 16, respectively. Specifically, after depositing the gate insulating film 7, polysilicon that will become the gate electrode 8 is deposited. Thereafter, the deposited polysilicon is etched back using a resist as a mask. As a result, the polysilicon is etched back in areas where there is no resist, and polysilicon is formed in the gate trench 6, the gate trench 26, and the termination trench 16.

[0091] 17 , the region covered with the resist is a region in which the upper corners of the gate trench 6 have a rounded shape (with a radius of curvature Re), and the polysilicon is not etched back, so that polysilicon remains in the mesa region (the upper surface of the semiconductor layer 2). Because the upper corners of the gate trench 6 have a large rounded shape (with a radius of curvature Re), there is no need to locally thicken the gate insulating film 7 in order to suppress electric field concentration at the upper corners of the gate trench 6. Therefore, a structure capable of suppressing electric field concentration at the upper corners of the gate trench 6 can be manufactured in a single process of forming the gate insulating film 7, and an increase in manufacturing costs can be suppressed without increasing the number of manufacturing processes.

[0092] Next, an interlayer insulating film 13 is formed on the upper surface of the semiconductor layer 2 by low-pressure CVD so as to cover the gate electrode 8. The interlayer insulating film 13 is then patterned to form contact holes (gate contacts 34) in the active region 20 and the termination region 30, reaching the source region 5 and the base region 4. A contact hole (source contact 31) is also formed in the active region, reaching the gate electrode 8. An ohmic electrode 25 is then formed in the gate contact 34 (see FIG. 6 ). An ohmic electrode 32 is also formed in the source contact 31. Each ohmic electrode may be a silicide film formed by depositing a metal film containing nickel (Ni) as a main component on the upper surface of the semiconductor layer 2 and the upper surface of the gate electrode 8, and then reacting the Ni with the semiconductor by heat treatment at a temperature of 600° C. or higher and 1100° C. or lower.

[0093] Thereafter, an Al alloy or the like is deposited on the upper surface of the interlayer insulating film 13 and in the gate contact 34 and source contact 31, and then patterned to form the gate wiring 18 via the gate contact 34 and the source electrode 11 via the source contact 31.

[0094] Then, an Al alloy or the like is deposited on the surface of the silicon carbide semiconductor substrate 1 opposite to the surface on which the semiconductor layer 2 is formed, to form the drain electrode 12. Through the above steps, the semiconductor device 100 is formed.

[0095] <Operational Effects of Semiconductor Device> Next, operational effects of the semiconductor device 100 according to this embodiment will be described.

[0096] In the semiconductor device 100 according to this embodiment shown in FIGS. 2 to 5, by controlling the voltage applied between the gate electrode 8 and the source electrode 11, the channel formed in the base region 4 facing the gate electrode 8 via the gate insulating film 7 is controlled, and the on and off states of the semiconductor device 100 are controlled.

[0097] When a voltage large enough to turn on the semiconductor device 100 is applied between the gate electrode 8 and the source electrode 11, a voltage equal to or greater than the threshold value is applied to the gate electrode 8. As a result, a channel is formed in the base region 4 facing the gate electrode 8 via the gate insulating film 7, and a path through which electrons, which are carriers, flow is formed between the n-type source region 5 and the n-type drift layer 3.

[0098] Electrons flowing from source region 5 into drift layer 3 reach drain electrode 12 via drift layer 3 and silicon carbide semiconductor substrate 1 due to an electric field formed by a voltage applied between drain electrode 12 and source electrode 11. As a result, when a voltage equal to or higher than the threshold value is applied to gate electrode 8, a current flows from drain electrode 12 to source electrode 11. This state is the on state of semiconductor device 100.

[0099] On the other hand, when a voltage less than the threshold value is applied between the gate electrode 8 and the source electrode 11, no channel is formed in the base region 4 facing the gate electrode 8 via the gate insulating film 7. In this case, the p-type base region 4 exists between the n-type source region 5 and the n-type drift layer 3, and therefore no current flows from the drain electrode 12 to the source electrode 11. This state is the off state of the semiconductor device 100.

[0100] When the semiconductor device 100 is in the off state, a high voltage supplied from an external electric circuit is applied between the drain electrode 12 and the source electrode 11. When the semiconductor device 100 is in the off state, a depletion layer expands from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3, which prevents the electric field caused by the voltage applied between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 at the bottom of the gate trench 6, thereby preventing breakdown even when a high electric field is applied to the gate insulating film 7 at the bottom of the gate trench 6.

[0101] On the other hand, when the semiconductor device 100 is turned on, a voltage supplied from an external electric circuit is applied between the gate electrode 8 and the source electrode 11. The applied voltage applies an electric field to the gate insulating film 7. Because the upper corners of the semiconductor layer 2 in the gate trench 6 are formed in a rounded shape with a radius of curvature Re, the gate insulating film 7 also has a rounded shape with a radius of curvature Re. This prevents the electric field caused by the voltage applied between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 at the upper corners of the gate trench 6, thereby preventing breakdown of the gate insulating film 7 even when an electric field is applied to it.

[0102] Furthermore, when the semiconductor device 100 is in the on state, a current flows from the drain electrode 12 to the source electrode 11 due to a voltage supplied from an external electric circuit, and the voltage between the drain electrode 12 and the source electrode 11 becomes an on voltage, which is a voltage determined by the current flowing from the drain electrode 12 to the source electrode 11 and the on resistance of the semiconductor device 100. The on voltage is much lower than the voltage applied between the drain electrode 12 and the source electrode 11 in the off state. Therefore, the depletion layer that spreads from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 in the off state shrinks toward the diffusion protection layer 9 and the termination protection layer 19 when the semiconductor device is in the on state.

[0103] That is, when the semiconductor device 100 switches between the on state and the off state repeatedly, the depletion layer extending from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 expands and contracts in response to the switching.

[0104] The semiconductor device 100 functions by repeatedly switching between the off state and the on state, but even the repeated switching between the on state and the off state applies voltage stress to the gate insulating film 7, accelerating degradation. Because the upper corners of the semiconductor layer 2 in the gate trench 6 are formed in a rounded shape with a curvature radius Re, the gate insulating film 7 in that area also has a rounded shape with a curvature radius Re. This makes it possible to prevent the electric field between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 in the upper corners of the semiconductor layer 2. This makes it possible to suppress acceleration of degradation of the gate insulating film 7 and prevent its destruction.

[0105] In this embodiment, as shown in FIG. 4 , an electrically non-functional gate trench 26 is formed at the boundary between the termination region 30 and the active region 20. The termination region 30 and the active region 20 differ in their stacked structure and processing dimensions along the silicon carbide semiconductor substrate 1. Therefore, residual stress occurs at the boundary, affecting electrical characteristics and causing breakdown of the gate insulating film 7. Furthermore, the failure rate of the gate insulating film 7 increases the closer it is to the outermost periphery. Therefore, by electrically isolating the outermost cell (corresponding to the gate trench 26) from the other cells as the termination region 30 and electrically disconnecting its gate electrode 8 from the source electrode 11 and the gate wiring 18 to allow the gate potential to float, breakdown of the device can be suppressed.

[0106] 4, the yield rate increases as the number of gate trenches 26 increases. That is, by forming a plurality of gate trenches 26, the quality of the semiconductor device 100 increases.

[0107] Second Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0108] 19 is a plan view schematically illustrating an example of the configuration of a semiconductor device 101 according to this embodiment. As illustrated in the example of FIG. 19, the semiconductor device 101 includes an active region 20 and a termination region 30.

[0109] In the active region 20, a plurality of gate trenches 6 are formed, which are arranged in a plan view, a gate electrode 8 formed in the gate trench 6, and a gate wiring 18 connected to the gate electrode 8 via a gate contact 34. The gate contact 34 is formed directly below the gate wiring 18 and directly above the gate electrode 8.

[0110] The gate electrode 8 is connected to a gate bonding pad 58 disposed on the periphery of the chip. The gate bonding pad 58 and the gate electrode 8 are metal layers such as aluminum, and are formed in the same process.

[0111] A source electrode 11 is formed on the upper surface of a source region 5 formed in the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31). The source electrode 11 also extends to a source bonding pad 59.

[0112] In the termination region 30, a termination trench 16 and a gate wiring 18 are formed in a partial region within the termination trench 16. A metal wiring 120 is formed on the upper surface of the gate wiring 18 via a gate contact 34. The metal wiring 120 is formed in the same process as the gate electrode 8 and the source electrode 11. Since the metal wiring 120 and the gate wiring 18 are formed in parallel connection, electrical resistance can be reduced. The semiconductor device 101 is configured as described above.

[0113] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 101 according to this embodiment will be described.

[0114] 20 to 22 are diagrams showing an example of a method for manufacturing a semiconductor device according to this embodiment.

[0115] The structure shown in Fig. 20 corresponds to the plan view of the structure shown in Fig. 10. Gate trenches 6 are formed in active region 20, and outermost gate trenches 26 and termination trench 16 are formed in termination region 30.

[0116] The structure shown in Fig. 21 corresponds to the plan view of the structure shown in Fig. 16. Gate wiring 18 is formed in gate trench 6 in active region 20. Gate wiring 18 is also formed in gate trench 26 in termination region 30. Furthermore, gate wiring 18 is formed in a partial region of termination trench 16.

[0117] The gate wiring 18 is formed by depositing polysilicon in the gate trench 6, and then forming a mask of resist or the like in a partial region and etching back the polysilicon.

[0118] 21, regions 108 and 109 indicated by dashed lines are regions where the polysilicon is not etched back due to the placement of the mask, and polysilicon remains on the upper surface of the semiconductor layer 2. The polysilicon in these regions covers not only the inside of the gate trench 6 but also the upper corners of the gate trench 6 and is also formed in the mesa region (upper surface of the semiconductor layer 2). The radius of curvature Re of the upper corners of the gate trench 6 is large, which can suppress the concentration of the electric field. Therefore, breakdown of the gate insulating film 7 is suppressed.

[0119] 21, the gate electrodes 8 formed in the gate trenches 26 in the termination region 30 and the gate electrodes 8 formed in the gate trenches 6 arranged in a stripe pattern in the center of the active region 20 are separated in plan view. As shown in FIGS. 16 to 18, the gate wiring 18 is formed by etching back deposited polysilicon.

[0120] In the etch-back process, where there is a trench step (where the top surface height differs due to the formation of the trench), polysilicon remains on the sidewalls of the trench in the form of sidewalls. In a structure in which the remaining polysilicon is electrically connected in this manner, an electric field is also applied to the gate insulating film 7 below the polysilicon remaining in the form of sidewalls, causing breakdown of the gate insulating film 7. In contrast, in the structure shown in Figure 21, the potential of the polysilicon remaining in the form of sidewalls is floating and is not electrically connected to the gate electrode. Therefore, breakdown of the gate insulating film 7 can be suppressed.

[0121] FIG. 22 is a plan view showing an example of a structure in which an interlayer insulating film 13 is formed, and a source contact 31 and a gate contact 34 are formed after the step shown in FIG.

[0122] 22 , gate contacts 34 are formed on the upper surfaces of gate electrodes 8 in regions 108 and 109. In the structure shown in FIG. 22 , gate contacts 34 and gate wiring 18 can be formed in positions that overlap gate trenches 6 arranged in a stripe pattern in plan view, eliminating the need to provide a separate region for forming gate contacts 34. This allows the chip area to be reduced and increases the degree of freedom in design layout.

[0123] 19, aluminum is deposited and etched using a resist mask to pattern the aluminum. Gate wiring 18 is then formed in region 108 and connected to gate bonding pad 58. Aluminum is patterned in region 109 to form metal wiring 120, which extends to the top surface of gate electrode 8 formed in termination region 30. Metal wiring 120 is then electrically connected to gate electrode 8 via a contact hole (gate contact 34). Gate electrode 8 in termination region 30 extends to directly below gate bonding pad 58 and is electrically connected to gate electrode 8 via gate contact 34 in gate bonding pad 58.

[0124] The gate electrode 8 in the gate trench 6 in the cell array is electrically connected to the gate bonding pad 58 via the gate contact 34 in the center of the active region 20, and is also electrically connected to the gate electrode 8 formed in the termination region 30, the aluminum layer (metal wiring 120), and other gate electrodes 8 in the active region 20. This reduces the resistance of the gate electrode 8 in the gate trench 6 in the active region 20, resulting in good electrical characteristics (switching characteristics, on-characteristics).

[0125] The radius of curvature Re of the upper corners of the gate trench 6 in the region 108 in the center of the active region 20 where the gate contact 34 is formed is large. Therefore, even when a gate voltage is applied during device operation, concentration of an electric field at the upper corners of the gate trench 6 can be suppressed, and breakdown of the gate insulating film 7 can be suppressed.

[0126] Third Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0127] 23 is a plan view schematically illustrating an example of the configuration of a semiconductor device 102 according to this embodiment. As illustrated in the example of FIG. 23, the semiconductor device 102 includes an active region 20 and a termination region 30.

[0128] In the active region 20, a plurality of gate trenches 6 are formed, which are arranged in a plan view, a gate electrode 8 formed in the gate trench 6, and a gate wiring 18 connected to the gate electrode 8 via a gate contact 34. The gate contact 34 is formed immediately below the gate wiring 18 and in an upper layer of the gate electrode 8.

[0129] The gate electrode 8 is connected to a gate bonding pad 58 disposed on the periphery of the chip. The gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum, and are formed in the same process.

[0130] A source electrode 11 is formed on the upper surface of a source region 5 formed in the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31). The source electrode 11 also extends to a source bonding pad 59.

[0131] In the termination region 30, a termination trench 16 and a gate electrode 8 are formed in a partial region within the termination trench 16. A metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34. The metal wiring 122 is formed in the same process as the gate wiring 18 and the source electrode 11. Since the metal wiring 122 and the gate electrode 8 are formed in parallel connection, the gate resistance can be reduced. The semiconductor device 102 is configured as described above.

[0132] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 102 according to this embodiment will be described.

[0133] 24 and 25 are diagrams showing an example of a method for manufacturing a semiconductor device according to this embodiment.

[0134] The structure shown in Fig. 24 corresponds to the plan view of the structure shown in Fig. 16. A gate electrode 8 is formed in the gate trench 6 in the active region 20. A gate electrode 8 is also formed in the gate trench 26 in the termination region 30. Furthermore, a gate electrode 8 is formed in a partial region of the termination trench 16.

[0135] The gate electrode 8 is formed by depositing polysilicon in the gate trench 6, and then forming a mask of resist or the like in a partial region and etching back the polysilicon.

[0136] 24, regions 108 and 109 indicated by dashed lines are regions where the polysilicon is not etched back due to the placement of the mask, and polysilicon remains on the upper surface of the semiconductor layer 2. The polysilicon in these regions is not only formed within the gate trench 6, but also covers the upper corners of the gate trench 6 and is also formed in the mesa region (upper surface of the semiconductor layer 2). The radius of curvature Re of the upper corners of the gate trench 6 is large, which can suppress the concentration of the electric field. Therefore, breakdown of the gate insulating film 7 is suppressed.

[0137] The outermost end of the active region 20 shown in FIG. 24 (the portion corresponding to region 109) can electrically connect multiple gate electrodes 8 arranged in a stripe pattern via gate contacts 34, thereby reducing the gate resistance of the gate trench 6 formed to extend thinly.

[0138] FIG. 25 is a plan view showing an example of a structure in which an interlayer insulating film 13 is formed, and a source contact 31 and a gate contact 34 are formed after the step shown in FIG.

[0139] In FIG. 25, a gate contact 34 is formed on the upper surface of the gate electrode 8 in the regions 108 and 109 .

[0140] 23 , aluminum is deposited and etched using a resist mask to pattern the aluminum. A gate electrode 8 is then formed in region 108, and connected to gate bonding pad 58 via gate wiring 18. In region 109, aluminum is patterned to form metal wiring 122 (gate wiring 18), which extends to the top surface of gate electrode 8 formed in termination region 30. Metal wiring 122 is then electrically connected to gate electrode 8 via a contact hole (gate contact 34). Gate wiring 18 in termination region 30 extends to directly below gate bonding pad 58, and is electrically connected to gate electrode 8 via gate contact 34 in gate bonding pad 58.

[0141] The gate electrode 8 in the gate trench 6 in the cell array is electrically connected to the gate bonding pad 58 via the gate contact 34 in the center of the active region 20. The gate electrode 8 in the gate trench 6 in the cell array is also electrically connected to other gate wirings 18 in the active region 20 via the gate contact 34 and the aluminum layer (electrode portion 121) formed at the edge of the active region 20. This reduces the resistance of the gate wiring 18 in the gate trench 6 in the active region 20, thereby achieving good electrical characteristics (switching characteristics, on-characteristics).

[0142] The radius of curvature Re of the upper corner of the gate trench 6 in region 108 at the center of the active region 20 where the gate contact 34 is formed and the radius of curvature Re of the upper corner of the gate trench 6 in region 109 at the edge of the active region 20 are formed to be large. Therefore, even when a gate voltage is applied during device operation, concentration of an electric field at the upper corner of the gate trench 6 can be suppressed, and breakdown of the gate insulating film 7 can be suppressed.

[0143] Fourth Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0144] 26 to 30 are cross-sectional views schematically showing examples of the configuration of semiconductor device 103 according to this embodiment. As shown in the examples of FIGS. 26 to 30, semiconductor device 103 includes active region 20 and termination region 30.

[0145] In the active region 20, a plurality of gate trenches 6 are formed, which are arranged in a plan view, a gate electrode 8 formed in the gate trench 6, and a gate wiring 18 connected to the gate electrode 8 via a gate contact 34. The gate contact 34 is formed immediately below the gate wiring 18 and in an upper layer of the gate electrode 8.

[0146] The gate electrode 8 is connected to a gate bonding pad 58 disposed on the periphery of the chip. The gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum, and are formed in the same process.

[0147] A source electrode 11 is formed on the upper surface of a source region 5 formed in the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31). The source electrode 11 also extends to a source bonding pad 59.

[0148] In the termination region 30, a termination trench 16 and a gate electrode 8 are formed in a partial region within the termination trench 16. A metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34. The metal wiring 122 is formed in the same process as the gate electrode 8 and source electrode 11. Since the metal wiring 122 and the gate electrode 8 are formed in parallel connection, the gate resistance can be reduced. The semiconductor device 103 is configured as described above.

[0149] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 103 according to this embodiment will be described.

[0150] The structure shown in FIG. 26 corresponds to the structure at the stage when the steps from FIG. 7 to FIG. 9 are completed.

[0151] 26 , after the gate trench 6, the gate trench 26, and the termination trench 16 are formed, impurities are implanted into the bottom surface of each trench. Specifically, a p-type diffusion protection layer 39 is formed by implanting Al ions into the bottom of the gate trench 6 and the bottom of the gate trench 26. Similarly, a p-type termination protection layer 49 is formed by implanting Al ions into the bottom of the termination trench 16. The impurity concentration of the implanted Al ions is, for example, 1×10 １６ cm －３ or more, and 1 x 10 １８ cm －３ The depth of ion implantation is preferably, for example, 0.1 μm or more and 2.0 μm or less.

[0152] 27, a resist mask 51 is formed on the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30. Then, Al ions are additionally implanted into the exposed p-type diffusion protection layer 39 and termination protection layer 49. The impurity concentration of Al is, for example, 1×10 １６ cm －３ or more, and 1 x 10 １８ cm －３ The depth of ion implantation is preferably, for example, 0.1 μm or more and 2.0 μm or less.

[0153] As a result of the above-described two ion implantations, the impurity concentration of the diffusion protection layer 39 in the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30 becomes lower than the impurity concentration of the diffusion protection layer 9 in the gate trench 6 (the trench formed in a location other than the boundary) where two ion implantations have been performed. Similarly, the impurity concentration of the diffusion protection layer 39 becomes lower than the impurity concentration of the termination protection layer 19 in the termination trench 16 where two ion implantations have been performed.

[0154] Thereafter, the resist is removed, and an annealing process is performed using a heat treatment device to activate the implanted impurities. The annealing process is performed in an inert gas atmosphere such as argon (Ar) or in a vacuum, for example, at a temperature in the range of 1300° C. to 1900° C. for 30 seconds to 1 hour.

[0155] 28 , a gate insulating film 97 is deposited. Then, a resist mask 52 is formed on the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30, and the gate insulating film 97 in the region not covered by the resist mask 52 is removed by wet processing using hydrofluoric acid or the like. Here, the thickness of the gate insulating film 97 is, for example, not less than 20 nm and not more than 150 nm.

[0156] Thereafter, a gate insulating film is further deposited on the entire surface, as shown in the example of Fig. 29. The thickness of the gate insulating film further formed by the second deposition is, for example, 20 nm or more and 150 nm or less.

[0157] By the above two deposition steps, the gate insulating film 87 in some regions is formed thicker than the other gate insulating film 7 .

[0158] Thereafter, polysilicon that will become the gate electrode 8 is deposited. The deposited polysilicon is then etched back using a resist as a mask. Thereafter, the interlayer insulating film 13, source contact 31, gate contact 34, ohmic electrode 32, source electrode 11, gate wiring 18, etc. are formed in the same steps as those described in the first embodiment, thereby completing the MOSFET (see FIG. 30).

[0159] In the region where the gate contact 34 of the active region 20 is formed, polysilicon remains in the mesa region (the upper surface of the semiconductor layer 2), but this portion has a rounded shape with a large radius of curvature (radius of curvature Re). Therefore, as in the case shown in the first embodiment, electric field concentration at the upper corners of the gate trench 6 can be suppressed, and breakdown of the gate insulating film 7 can be suppressed.

[0160] 30, the termination trench 16 in the termination region 30 is processed with wide dimensions, while the gate trench 6 or gate trench 26 in the cell section is formed with the minimum processing line width. Because of the structural differences between the two, the thermal history during the wafer process causes the expansion coefficients of the materials to differ. This causes residual stress, which results in differences in the electrical characteristics of the elements and also affects the reliability of the semiconductor device.

[0161] In each cell arranged in the active region 20, the stress increases toward the outermost periphery of the gate trench. As a result, the failure rate of the gate insulating film 7 increases toward the outermost periphery of the gate trench.

[0162] For this reason, it would be effective to electrically isolate the outermost cells from the other cells and make the gate potential floating, but in this case, the region in question would not function as a MOSFET.

[0163] Therefore, in this embodiment, by increasing the thickness of the gate insulating film 87 of the cells in the peripheral portion (the boundary portion between the active region 20 and the termination region 30) or by designing the impurity concentration of the diffusion protection layer 39 to be lower than the impurity concentration of the diffusion protection layer 9 of other cells in other active regions 20, it is possible to reduce the concentrated electric field applied to the gate insulating film 87 when the gate voltage is applied and the semiconductor device is turned on. As a result, breakdown of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0164] <Regarding the Effects Produced by the Multiple Embodiments Described Above> Next, examples of the effects produced by the multiple embodiments described above will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the multiple embodiments described above, but these may be replaced with other specific configurations exemplified in the present specification to the extent that similar effects are produced. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0165] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0166] According to the embodiment described above, the semiconductor device includes a drift layer 3 of a first conductivity type (n-type), a base region 4 of a second conductivity type (p-type) provided in a surface layer of the drift layer 3, a plurality of n-type source regions 5 provided in a surface layer of the base region 4, at least one trench (e.g., gate trench 6, gate trench 26, termination trench 16) extending from the upper surface of the drift layer 3 through the base region 4 and into the drift layer 3, a p-type protective layer (e.g., diffusion protective layer 9, diffusion protective layer 39, termination protective layer 19) provided in the drift layer 3 below the trench, a gate insulating film 7 provided along the interior of the trench including the upper corners of the trench, and a gate electrode 8 surrounded by the gate insulating film 7 and provided at least in the trench. Here, the regions separated by the trench in a planar view are referred to as a first region and a second region. The semiconductor device further includes a source electrode 11 electrically connected to the source region 5 adjacent to the trench (gate trench 6) in the first region, and a gate wiring 18 provided on an upper surface of a gate electrode 8 provided in the trench (gate trench 6 or termination trench 16) in the second region. The radius of curvature Re of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6 or termination trench 16) in the second region is larger than the radius of curvature Rc of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6) in the first region.

[0167] With this configuration, even if a gate voltage is applied to the gate insulating film 7 formed in a round shape with a large radius of curvature (radius of curvature Re), the large radius of curvature effectively suppresses electric field concentration, thereby preventing the application of a high electric field, and therefore preventing breakdown of the gate insulating film 7.

[0168] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0169] Furthermore, according to the embodiment described above, the gate wiring 18 is provided on the upper surface of the gate electrode 8 extending over the upper surface of the source region 5. With such a configuration, breakdown of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0170] Furthermore, according to the embodiment described above, the gate wiring 18 is connected via a plurality of contact holes (gate contacts 34) to the upper surface of the gate electrode 8 extending over the upper surface of the source region 5. With this configuration, breakdown of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0171] Furthermore, according to the embodiment described above, the thickness of the gate insulating film 7 provided in the trench in the first region is equal to the thickness of the gate insulating film 7 provided in the trench in the second region. With this configuration, the gate insulating film 7 formed in multiple trenches can be formed in a single process.

[0172] Furthermore, according to the embodiment described above, a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20, and at least one gate trench 26 is provided in the termination region 30. Furthermore, the gate electrode 8 provided in the gate trench 26 provided in the termination region 30 is not electrically connected to the source electrode 11 and the gate wiring 18. With this configuration, the potential of the gate electrode 8 in the gate trench 26 is floated, thereby preventing breakdown of the device.

[0173] Furthermore, according to the embodiment described above, a plurality of trenches are provided. The plurality of gate trenches 6 are arranged in a striped pattern in plan view. The gate wiring 18 is provided across the upper surfaces of the gate electrodes 8 provided in the plurality of gate trenches 6. This configuration can suppress breakdown of the gate insulating film and improve the reliability of the semiconductor device.

[0174] Furthermore, according to the embodiment described above, a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20, and at least one termination trench 16 is provided in the termination region 30. The formation width of the termination trench 16 provided in the termination region 30 is wider than the formation width of the gate trench 6 (or gate trench 26) provided in the active region 20. With this configuration, a structure can be achieved in which no polysilicon remains on the sidewall of the termination trench 16, and therefore breakdown of the gate insulating film can be suppressed compared to a structure in which an electric field is applied to the underlying gate insulating film 7 via polysilicon remaining on the sidewall of the termination trench.

[0175] Furthermore, according to the embodiment described above, a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20 surrounded by the termination region 30 in a plan view. Furthermore, the thickness of the gate insulating film 87 provided in the trenches (gate trench 6 and gate trench 26) at the boundary between the active region 20 and the termination region 30 is thicker than the thickness of the gate insulating film 7 provided in the trenches (gate trench 6 and termination trench 16) in the active region 20 and termination region 30 other than the boundary. This configuration reduces the concentrated electric field applied to the gate insulating film 87 when a gate voltage is applied to turn the semiconductor device on. As a result, breakdown of the gate insulating film is suppressed, improving the reliability of the semiconductor device.

[0176] Furthermore, according to the embodiment described above, a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20, which is surrounded by the termination region 30 in a plan view. Furthermore, the impurity concentration of the protective layer (diffusion protective layer 39) provided below the gate trench 6 and gate trench 26 at the boundary between the active region 20 and the termination region 30 is lower than the impurity concentration of the protective layer (diffusion protective layer 9, termination protective layer 19) provided below the trenches (gate trench 6, termination trench 16) in the active region 20 and termination region 30 other than the boundary. This configuration reduces the concentrated electric field applied to the gate insulating film 87 when a gate voltage is applied to turn the semiconductor device on. As a result, breakdown of the gate insulating film is suppressed, improving the reliability of the semiconductor device.

[0177] According to the embodiment described above, in the method for manufacturing a semiconductor device, a p-type base region 4 is provided in the surface layer of an n-type drift layer 3. A plurality of n-type source regions 5 are provided in the surface layer of the base region 4. At least one trench (e.g., gate trench 6, gate trench 26, or termination trench 16) is provided extending from the upper surface of the drift layer 3 through the base region 4 and into the drift layer 3. A p-type protective layer (e.g., diffusion protective layer 9, diffusion protective layer 39, or termination protective layer 19) is provided in the drift layer 3 below the trench. Here, the regions separated by the trench in a planar view are referred to as a first region and a second region. In the first region and the second region, the upper corners of the trench (gate trench 6) are etched. In the second region, the upper corners of the trench (gate trench 6 or termination trench 16) are etched. A gate insulating film 7 is provided along the interior of the trench, including the upper corners of the trench. A gate electrode 8 is provided in the trench surrounded by the gate insulating film 7. A source electrode 11 is provided so as to be electrically connected to the source region 5 adjacent to the trench (gate trench 6) in the first region. A gate wiring 18 is provided on the upper surface of the gate electrode 8 provided in the trench (gate trench 6 or termination trench 16) in the second region. Here, the radius of curvature Re of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6 or termination trench 16) in the second region is larger than the radius of curvature Rc of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6) in the first region.

[0178] With this configuration, even if a gate voltage is applied to the gate insulating film 7 formed in a round shape with a large radius of curvature (radius of curvature Re), the large radius of curvature effectively suppresses electric field concentration, thereby preventing the application of a high electric field, and therefore preventing breakdown of the gate insulating film 7.

[0179] Unless otherwise specified, the order in which the processes are performed can be changed.

[0180] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0181] <Regarding Modifications of the Multiple Embodiments Described Above> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0182] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0183] Furthermore, in at least one embodiment described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0184] 3 Drift layer, 4 Base region, 5 Source region, 6 Gate trench, 7 Gate insulating film, 8 Gate electrode, 11 Source electrode, 16 Termination trench, 18 Gate wiring, 20 Active region, 26 Gate trench, 30 Termination region, 34 Gate contact, 87 Gate insulating film, 97 Gate insulating film, 100 Semiconductor device, 101 Semiconductor device, 102 Semiconductor device, 103 Semiconductor device, 108 Region, 109 Region, 1000 Region.

Claims

1. a drift layer of a first conductivity type; a second conductivity type base region provided on a surface layer of the drift layer; a first conductivity type source region provided in a surface layer of the base region; at least one trench extending from an upper surface of the drift layer through the base region into the drift layer; a protection layer of a second conductivity type disposed in the drift layer below the trench; a gate insulating film provided along an inside of the trench including an upper corner portion of the trench; a gate electrode provided at least in the trench and surrounded by the gate insulating film; a source electrode electrically connected to the source region adjacent to the trench; a gate wiring provided on an upper surface of the gate electrode provided in the trench, Among regions partitioned by the trench in a plan view, a region in which the source electrode is provided is defined as a first region, and a region in which the gate wiring is provided is defined as a second region; a radius of curvature of the gate insulating film provided at the upper corners of the trench in the second region is larger than a radius of curvature of the gate insulating film provided at the upper corners of the trench in the first region; Semiconductor device.

2. 2. The semiconductor device according to claim 1, The gate wiring is provided on the upper surface of the gate electrode extending to an upper surface of the source region. Semiconductor device.

3. 3. The semiconductor device according to claim 2, the gate wiring is connected to the upper surface of the gate electrode extending to the upper surface of the source region via a plurality of contact holes; Semiconductor device.

4. 3. The semiconductor device according to claim 1, a thickness of the gate insulating film provided in the trench in the first region is equal to a thickness of the gate insulating film provided in the trench in the second region; Semiconductor device.

5. 3. The semiconductor device according to claim 1, A plurality of the trenches are provided, At least one of the trenches is provided in each of an active region and a termination region surrounding the active region in a plan view; the gate electrode provided in the trench provided in the termination region is not electrically connected to the source electrode and the gate wiring; Semiconductor device.

6. 3. The semiconductor device according to claim 1, A plurality of the trenches are provided, The plurality of trenches are arranged in a stripe shape in a plan view, the gate wiring is provided across the upper surfaces of the gate electrodes provided in the plurality of trenches; Semiconductor device.

7. 3. The semiconductor device according to claim 1, A plurality of the trenches are provided, At least one of the trenches is provided in an active region and a termination region surrounding the active region in a plan view, the trenches being spaced apart from each other; a width of the trench provided in the termination region is wider than a width of the trench provided in the active region; Semiconductor device.

8. 3. The semiconductor device according to claim 1, A plurality of the trenches are provided, At least one of the trenches is provided in an active region surrounded by a termination region in a plan view; a thickness of the gate insulating film provided in the trench at a boundary between the active region and the termination region is greater than a thickness of the gate insulating film provided in the trench in the active region and the termination region other than the boundary; Semiconductor device.

9. 3. The semiconductor device according to claim 1, A plurality of the trenches are provided, At least one of the trenches is provided in an active region surrounded by a termination region in a plan view; an impurity concentration of the protection layer provided below the trench in a boundary portion between the active region and the termination region is lower than an impurity concentration of the protection layer provided below the trench in the active region and the termination region other than the boundary portion; Semiconductor device.

10. a base region of a second conductivity type is provided on a surface layer of a drift layer of a first conductivity type; a plurality of source regions of a first conductivity type are provided on a surface layer of the base region; providing at least one trench extending from an upper surface of the drift layer through the base region into the drift layer; providing a protection layer of a second conductivity type in the drift layer below the trench; A region partitioned by the trench in a plan view is defined as a first region and a second region, Etching upper corners of the trench in the first region and the second region; Etching the upper corners of the trench in the second region; providing a gate insulating film along an interior of the trench including the upper corners of the trench; a gate electrode is provided in the trench surrounded by the gate insulating film; providing a source electrode electrically connected to the source region adjacent the trench in the first region; providing a gate wiring on an upper surface of the gate electrode provided in the trench in the second region; a radius of curvature of the gate insulating film provided at the upper corners of the trench in the second region is larger than a radius of curvature of the gate insulating film provided at the upper corners of the trench in the first region; A method for manufacturing a semiconductor device.