Device and method for manufacturing device

Abstract

This device comprises: a substrate having a first surface, a second surface opposite to the first surface, and a through hole passing through between the first surface and the second surface; a through electrode provided in the through hole and having a side portion along an inner wall surface of the through hole and a bottom portion connected to the side portion; a protective film provided on the center side of the through hole with respect to the through electrode; and a first wire provided on the second surface of the substrate and connected to the bottom portion of the through electrode.　

Description

Device and method for manufacturing the same

[0001] The present invention relates to a device and a method for manufacturing the device.

[0002] Interposers are known as relay substrates that use through-hole electrodes to connect circuits on both sides of the substrate. For example, flip-chip mounting of quantum bit chips onto interposers is known (see, for example, Patent Documents 1 to 3). Another known configuration involves connecting quantum bit elements and passive elements on both sides of the substrate via through-hole electrodes (see, for example, Patent Document 4).

[0003] International Publication No. WO 2021 / 245949 International Publication No. WO 2018 / 212041 U.S. Patent Application Publication No. 2022 / 0199507 U.S. Patent Application Publication No. 2020 / 0343434

[0004] When a through electrode is provided so as to fill a through hole penetrating a substrate, the difference in the linear expansion coefficient between the substrate and the through electrode may damage the substrate and / or the through electrode. Therefore, in order to reduce the volume of the through electrode, the through electrode may be formed into a cylindrical shape that conforms to the inner wall surface of the through hole. However, in this case, the connection area between the wiring formed on the substrate and the through electrode becomes small, which may cause unstable contact between the wiring and the through electrode.

[0005] One aspect of the invention is to increase the connection area between the through electrode and the wiring.

[0006] In one aspect, the device comprises a substrate having a first surface, a second surface opposite the first surface, and a through hole penetrating between the first surface and the second surface; a through electrode provided in the through hole and having a side portion along the inner wall surface of the through hole and a bottom portion connected to the side portion; a protective film provided closer to the center of the through electrode in the through hole; and a first wiring provided on the second surface of the substrate and connected to the bottom portion of the through electrode.

[0007] In one aspect, a method for manufacturing a device includes the steps of forming a through electrode in a through hole that penetrates between a first surface of a substrate and a second surface opposite the first surface, the through electrode having a side portion along the inner wall surface of the through hole and a bottom portion connected to the side portion; forming a protective film on the through hole closer to the center than the through electrode; and forming a first wiring connected to the bottom portion of the through electrode on the second surface of the substrate.

[0008] As one aspect, the connection area between the through electrode and the wiring can be increased.

[0009] FIG. 1 is a cross-sectional view of a device according to Example 1. FIG. 2(a) is a plan view of a through electrode in Example 1 as viewed from the +Z direction, and FIG. 2(b) is a plan view as viewed from the −Z direction. FIGS. 3(a) to 3(c) are cross-sectional views (part 1) illustrating a method for manufacturing a device according to Example 1. FIGS. 4(a) to 4(c) are cross-sectional views (part 2) illustrating a method for manufacturing a device according to Example 1. FIGS. 5(a) to 5(c) are cross-sectional views (part 3) illustrating a method for manufacturing a device according to Example 1. FIGS. 6(a) to 6(c) are cross-sectional views (part 4) illustrating a method for manufacturing a device according to Example 1. FIGS. 7(a) to 7(c) are cross-sectional views (part 5) illustrating a method for manufacturing a device according to Example 1. FIGS. 8(a) to 8(c) are cross-sectional views (part 1) illustrating a method for manufacturing a device according to Comparative Example 1. FIGS. 9(a) to 9(c) are cross-sectional views (part 2) illustrating a method for manufacturing a device according to Comparative Example 1. FIGS. 10(a) and 10(b) are cross-sectional views showing an example in which no cavity is formed in the through-hole in Example 1. FIG. 11(a) is a cross-sectional view of a device in Example 2, and FIG. 11(b) is a cross-sectional view of a device in a modified example of Example 2. FIG. 12 is a cross-sectional view of a device in Example 3. FIG. 13(a) is a plan view of a quantum bit element in Example 3, and FIG. 13(b) is a cross-sectional view taken along line A-A of FIG. 13(a). FIGS. 14(a) to 14(c) are cross-sectional views (part 1) showing a method for manufacturing a device in Example 3. FIGS. 15(a) to 15(c) are cross-sectional views (part 2) showing a method for manufacturing a device in Example 3. FIGS. 16(a) to 16(c) are cross-sectional views (part 1) showing a method for manufacturing a quantum bit element and a third wiring pattern in Example 3. FIGS. 17(a) to 17(c) are cross-sectional views (part 2) showing a method for manufacturing a quantum bit element and a third wiring pattern in Example 3. Fig. 18 is a cross-sectional view of a device according to a modified example of Example 3. Figs. 19(a) to 19(c) are cross-sectional views showing a method for manufacturing a device according to a modified example of Example 3. Figs. 20(a) to 20(c) are cross-sectional views (part 1) showing a method for manufacturing a device according to Comparative Example 2. Figs. 21(a) to 21(c) are cross-sectional views (part 2) showing a method for manufacturing a device according to Comparative Example 2.FIG. 22( a ) is a cross-sectional view of a device according to Example 4, and FIG. 22( b ) is a cross-sectional view of a device according to a modification of Example 4.

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0011] FIG. 1 is a cross-sectional view of a device according to a first embodiment. In the first embodiment, an example is shown in which the device 100 is an interposer. The X-axis and Y-axis are parallel to a first surface 11 of a substrate 10 and are perpendicular to each other, and the Z-axis is the thickness direction of the substrate 10. As shown in FIG. 1, the device 100 according to the first embodiment includes a substrate 10 having a first surface 11 and a second surface 12 opposite to the first surface 11, and a through-hole 13 penetrating between the first surface 11 and the second surface 12. The substrate 10 is, for example, a silicon substrate, a glass substrate, or a quartz substrate. The through-hole 13 has a diameter of, for example, about 5 μm to 15 μm and a depth of, for example, about 100 μm to 300 μm.

[0012] A through electrode 20 is provided in the through hole 13. The through electrode 20 has a cylindrical side portion 21 extending along the inner wall surface of the through hole 13, and a bottom portion 22 which is a plate-like portion connected to the end of the side portion 21 and provided overlapping the cylindrical interior of the side portion 21 in a plan view. An insulating film 30 is provided between the inner wall surface of the through hole 13 and the through electrode 20. The through electrode 20 is made of, for example, titanium nitride, and has a thickness of, for example, about 50 nm to 150 nm. The insulating film 30 is made of, for example, silicon oxide, and has a thickness of, for example, 50 nm to 150 nm.

[0013] 2(a) is a plan view of the through electrode in Example 1 as viewed from the +Z direction, and FIG. 2(b) is a plan view as viewed from the −Z direction. In FIGS. 2(a) and 2(b), the through electrode 20 is hatched for clarity. As shown in FIGS. 2(a) and 2(b), the side portion 21 of the through electrode 20 is cylindrical and extends along the inner wall surface of the through hole 13. The bottom portion 22 is connected to the end of the side portion 21 and covers the cylindrical interior of the side portion 21. Therefore, the through electrode 20 has a concave shape.

[0014] As shown in FIG. 1 , one or more first wiring patterns 40 are provided on the second surface 12 of the substrate 10 via an insulating film 31. Of the one or more first wiring patterns 40, the first wiring patterns 40 that overlap the through holes 13 enter openings in the insulating film 31 and the insulating film 30 and connect to the bottoms 22 of the through electrodes 20. In FIGS. 2( a) and 2(b), the area in which the first wiring patterns 40 contact the bottoms 22 is indicated by dotted lines. The first wiring patterns 40 contact more than half of the surface of the bottoms 22 facing the first wiring patterns 40 (the shaded area in FIG. 2(b)). The first wiring patterns 40 are formed of, for example, titanium nitride and have a thickness of, for example, 50 nm to 150 nm. The insulating film 31 is formed of, for example, silicon oxide and have a thickness of, for example, approximately 50 nm to 150 nm.

[0015] An insulating film 32 is provided on the second surface 12 of the substrate 10, covering one or more first wiring patterns 40. Through-hole wiring 41 is provided in an opening provided in the insulating film 32 and connected to the first wiring pattern 40. A first terminal electrode 42 is provided on the insulating film 32, connected to the through-hole wiring 41 and serving as a terminal for external connection. A bump electrode 46 is provided on the surface of the first terminal electrode 42. The insulating film 32 is formed of, for example, silicon oxide and has a thickness of, for example, 100 nm to 300 nm. The first terminal electrode 42 is formed of a high-melting-point metal material such as vanadium, molybdenum, hafnium, or tantalum. The through-hole wiring 41 may be formed of the same material as the first terminal electrode 42, or may be formed of a different material. The bump electrode 46 is formed of, for example, indium, gallium, or solder.

[0016] One or more second wiring patterns 43 are provided on the first surface 11 of the substrate 10 via an insulating film 33. At least a portion of the one or more second wiring patterns 43 extends from the side 21 of the through electrode 20. An insulating film 34 covering the one or more second wiring patterns 43 is provided on the first surface 11 of the substrate 10. A portion of the insulating film 34 extends into the through hole 13 and covers the surface of the side 21 and bottom 22 of the through electrode 20. A cavity 35 is formed inside the through hole 13, further inside the insulating film 34. Covering the through electrode 20 with the insulating film 34 protects the through electrode 20 and prevents unintended conduction. A through wiring 44 is provided in an opening provided in the insulating film 34 and connected to the second wiring pattern 43. A second terminal electrode 45 is provided on the insulating film 34 and connected to the through wiring 44, serving as a terminal for external connection.

[0017] The second wiring pattern 43 is made of, for example, titanium nitride and has a thickness of, for example, 50 nm to 150 nm. The insulating film 33 is made of, for example, silicon oxide and has a thickness of, for example, 50 nm to 150 nm. The insulating film 34 is made of, for example, silicon oxide and has a thickness of, for example, 100 nm to 300 nm. The second terminal electrode 45 is made of a high-melting-point metal material, like the first terminal electrode 42. The through wiring 44 may be made of the same material as the second terminal electrode 45, or may be made of a different material.

[0018] As described above, the insulating film 34 provided closer to the center of the through-hole 13 than the through-electrode 20 is made of, for example, silicon oxide. The through-electrode 20 is made of, for example, titanium nitride. The substrate 10 is made of, for example, silicon. The linear expansion coefficient of silicon oxide is 0.5×10 －６ / K, and the linear expansion coefficient of titanium nitride is 9.35 × 10 －６ / K, the linear expansion coefficient of silicon is 3.9 × 10 －６ Therefore, the insulating film 34 provided closer to the center of the through hole 13 than the through electrode 20 has a linear expansion coefficient closer to that of the substrate 10 than that of the through electrode 20 .

[0019] When a quantum bit chip is implemented in device 100, the electrodes and wiring are preferably formed of a superconducting material that exhibits superconductivity at extremely low temperatures (e.g., 10 Kelvin or less). That is, the through electrode 20, the first wiring pattern 40, the second wiring pattern 43, the first terminal electrode 42, the second terminal electrode 45, the through wires 41 and 44, and the bump electrode 46 are preferably formed of a superconducting material. Examples of superconducting materials include aluminum, titanium, vanadium, zinc, gallium, zirconium, niobium, molybdenum, technetium, cadmium, indium, tin, hafnium, tantalum, niobium nitride, and titanium nitride. Furthermore, when a chip other than a quantum bit chip is implemented in device 100, the electrodes and wiring may be formed of copper, tungsten, or the like, in addition to the above materials.

[0020] 3( a ) to 7 ( c ) are cross-sectional views showing a method for manufacturing a device according to Example 1. As shown in FIG. 3( a ), after cleaning a silicon substrate 10, the substrate 10 is heated in an oxidizing atmosphere to form a thermal oxide film 80, which is a silicon oxide film, on the first surface 11 and the second surface 12 of the substrate 10. The thickness of the thermal oxide film 80 is, for example, 100 nm.

[0021] As shown in FIG. 3B, a resist is applied to a thermal oxide film 80 formed on the first surface 11 of the substrate 10 to form a resist film 81. The resist film 81 is exposed to light and developed to form an opening in the resist film 81. A hard mask layer may be formed between the resist film 81 and the thermal oxide film 80. Using the resist film 81 as a mask, a recess 82 is formed in the substrate 10. The recess 82 is formed using, for example, a Bosch process. The recess 82 corresponds to the through hole 13 in FIG. 1 and has, for example, a diameter of 10 μm and a depth of 200 μm.

[0022] 3C, after removing the resist film 81 and cleaning the substrate 10, the substrate 10 is heated in an oxidizing atmosphere to form a thermal oxide film 83, which is a silicon oxide film, on the inner surface of the recess 82. The thickness of the thermal oxide film 83 is, for example, 50 nm.

[0023] 4A, a conductive film 84 made of, for example, titanium nitride is formed on the first surface 11 of the substrate 10 by, for example, atomic layer deposition (ALD). ３ ) ２ ] ４ Gas and NH ３ The conductive film 84 made of titanium nitride is formed by the ALD method using NH 3 gas. The thickness of the conductive film 84 is, for example, 100 nm. ３ Instead of gas, N ２ H ４ A gas may be used. The conductive film 84 is formed along the surface of the thermal oxide film 80 and the surface of the thermal oxide film 83 formed on the inner surface of the recess 82. The recess 82 is not filled with the conductive film 84, and a void is formed inside the conductive film 84.

[0024] 4B, the conductive film 84 is patterned by reactive ion etching (RIE) using, for example, a chlorine-based gas. As a result, one or more second wiring patterns 43 made of the conductive film 84 are formed. The second wiring patterns 43 are formed on the first surface 11 of the substrate 10 via the insulating film 33 made of the thermal oxide film 80.

[0025] 4C , an insulating film 34 made of a silicon oxide film is formed on the first surface 11 of the substrate 10, for example, by using a chemical vapor deposition (CVD) method. The insulating film 34 has a thickness of 200 nm, for example. The insulating film 34 is formed on the insulating film 33 to cover the second wiring pattern 43, and also to cover the surface of the conductive film 84 formed along the side and bottom surfaces of the recess 82. The recess 82 is not filled with the insulating film 34, for example, and a cavity 35 is formed inside the insulating film 34.

[0026] 5A, the substrate 10 is turned upside down, and the insulating film 34 is bonded to a support substrate 86 with an adhesive 85. The support substrate 86 is, for example, a silicon substrate.

[0027] As shown in FIG. 5B , the substrate 10 is thinned from the second surface 12 side by grinding and polishing (for example, chemical mechanical polishing (CMP)) to expose the thermal oxide film 83 formed on the bottom surface of the recess 82. As an example, the substrate 10 is thinned by grinding and polishing so that a thickness of about several μm of the substrate 10 remains on the thermal oxide film 83 formed on the bottom surface of the recess 82, and then the substrate 10 is wet-etched with a KOH aqueous solution or the like to expose the thermal oxide film 83. As a result, a through hole 13 is formed in the substrate 10, penetrating between the first surface 11 and the second surface 12. The through hole 13 is provided with a through electrode 20 having a cylindrical side portion 21 made of a conductive film 84 formed on the inner wall surface of the through hole 13, and a bottom portion 22 made of the conductive film 84 connected to the side portion 21 and overlapping the cylindrical interior of the side portion 21. An insulating film 30 made of the thermal oxide film 83 is formed between the through electrode 20 and the inner wall surface of the through hole 13.

[0028] 5C, an insulating film 31 made of a silicon oxide film is formed by, for example, CVD on the second surface 12 of the substrate 10. The thickness of the insulating film 31 is, for example, 100 nm.

[0029] As shown in FIG. 6A, an opening 87 is formed in the insulating film 31 and the insulating film 30 by RIE using, for example, a fluorine-based gas, so that the bottom 22 of the through electrode 20 is exposed.

[0030] 6B, a conductive film 88 made of, for example, titanium nitride is formed on the second surface 12 of the substrate 10 by, for example, sputtering. The conductive film 88 is also formed in the opening 87 and contacts the bottom 22 of the through electrode 20. The thickness of the conductive film 88 is, for example, 100 nm. Note that the conductive film 88 may be formed by ALD or CVD instead of sputtering.

[0031] 6C, the conductive film 88 is patterned by, for example, RIE using a chlorine-based gas. As a result, one or more first wiring patterns 40 made of the conductive film 88 are formed. The first wiring patterns 40 are formed on the second surface 12 of the substrate 10 via an insulating film 31. Thereafter, an insulating film 32 made of a silicon oxide film is formed on the second surface 12 of the substrate 10 using, for example, a CVD method. The thickness of the insulating film 32 is, for example, 200 nm. The insulating film 32 is formed on the insulating film 31, covering the first wiring patterns 40.

[0032] 7A, the support substrate 86 is peeled off. For example, when an adhesive 85 whose adhesive strength is reduced by ultraviolet irradiation is used, the support substrate 86 is peeled off by irradiating the adhesive 85 with ultraviolet rays.

[0033] 7B, the substrate 10 is turned upside down, and openings that expose the second wiring patterns 43 are formed in the insulating film 34 by, for example, RIE using a fluorine-based gas. Thereafter, using, for example, a sputtering method, through-hole wirings 44 are formed that are embedded in the openings formed in the insulating film 34 and connect to the second wiring patterns 43. Using, for example, a sputtering method and an etching method, a second terminal electrode 45 that connects to the through-hole wiring 44 is formed on the insulating film 34. The through-hole wiring 44 and the second terminal electrode 45 do not necessarily have to be formed in separate steps, but may be formed simultaneously in the same step.

[0034] 7C, the substrate 10 is turned upside down, and openings are formed in the insulating film 32 by, for example, RIE using a fluorine-based gas, exposing the first wiring pattern 40. Then, using, for example, a sputtering method, through-hole wirings 41 are formed in the openings formed in the insulating film 32 and connected to the first wiring pattern 40. Using, for example, a sputtering method and an etching method, a first terminal electrode 42 is formed on the insulating film 32, connecting to the through-hole wiring 41. The through-hole wiring 41 and the first terminal electrode 42 do not necessarily have to be formed in separate processes, but may be formed simultaneously in the same process. Then, a bump electrode 46 is formed on the first terminal electrode 42. In this manner, the device 100 according to the first embodiment is formed.

[0035] 7(b) and 7(c) show an example in which the through wiring 44 and the second terminal electrode 45 are formed, and then the through wiring 41 and the first terminal electrode 42 are formed, but they may be formed in the opposite order. In the case in which the through wiring 41 and the first terminal electrode 42 are formed first, the through wiring 41 and the first terminal electrode 42 may be formed in a state in which the support substrate 86 is bonded to the insulating film 34 without being peeled off. Furthermore, the bump electrode 46 may be formed on the second terminal electrode 45 rather than the first terminal electrode 42, or may be formed on both the first terminal electrode 42 and the second terminal electrode 45, or may not be formed on both.

[0036] 8(a) to 9(c) are cross-sectional views showing a method for manufacturing a device according to Comparative Example 1. First, the same manufacturing steps as those shown in Fig. 3(a) to Fig. 4(c) of Example 1 are carried out to obtain Fig. 8(a).

[0037] 8( b), the substrate 10 is turned upside down, and the insulating film 34 is bonded to a support substrate 86 with an adhesive 85. Thereafter, the substrate 10 is thinned from the second surface 12 side by grinding, polishing, or the like, and the conductive film 84 is exposed from the second surface 12 of the substrate 10. As a result, a through hole 13 is formed in the substrate 10, penetrating between the first surface 11 and the second surface 12. A cylindrical through electrode 120 made of the conductive film 84 formed on the inner wall surface of the through hole 13 is formed in the through hole 13.

[0038] 8C , after the insulating film 31 is formed on the second surface 12 of the substrate 10, an opening that exposes the through electrode 120 is formed in the insulating film 31. Then, a conductive film 88 is formed on the second surface 12 of the substrate 10. The conductive film 88 is also formed in the opening of the insulating film 31 and comes into contact with the through electrode 120.

[0039] 9A, the conductive film 88 is patterned to form one or more first wiring patterns 40. Thereafter, the insulating film 32 is formed on the second surface 12 of the substrate 10.

[0040] 9B, after the support substrate 86 is peeled off, through-wires 44 connected to the second wiring patterns 43 are formed in the insulating film 34. Second terminal electrodes 45 connected to the through-wires 44 are formed on the insulating film 34.

[0041] 9C, through wirings 41 connected to the first wiring patterns 40 are formed in the insulating film 32. First terminal electrodes 42 connected to the through wirings 41 are formed on the insulating film 32. Then, bump electrodes 46 are formed on the first terminal electrodes 42. In this manner, the device according to Comparative Example 1 is formed.

[0042] In Comparative Example 1, the through electrode 120 formed in the through hole 13 of the substrate 10 has a cylindrical shape that conforms to the inner wall surface of the through hole 13. For example, if the through electrode is formed to fill the through hole, the substrate and / or the through electrode may be damaged due to the difference in linear expansion coefficient between the substrate and the through electrode. However, in Comparative Example 1, the through electrode 120 has a cylindrical shape that conforms to the inner wall surface of the through hole, so damage to the substrate 10 and the through electrode 120 due to the difference in linear expansion coefficient between the substrate 10 and the through electrode 120 is suppressed. However, in Comparative Example 1, the through electrode 120 has a cylindrical shape, so the connection area between the first wiring pattern 40 and the through electrode 120 is reduced. This may cause unstable contact between the first wiring pattern 40 and the through electrode 120, resulting in an increase and / or fluctuation in electrical resistance. For example, when forming the through electrode 120 in a through hole 13 with a large aspect ratio, the through electrode 120 is preferably formed by the ALD method, but in this case, the through electrode 120 is formed in a thin cylindrical shape along the inner wall surface of the through hole 13. This reduces the connection area between the first wiring pattern 40 and the through electrode 120. When the through electrode 120 is formed by the sputtering method or the CVD method, the conductive film 84 near the bottom surface of the recess 82 becomes thin, and therefore, even in this case, the connection area between the first wiring pattern 40 and the through electrode 120 is reduced.

[0043] On the other hand, according to Example 1, as shown in FIG. 1 , the through electrode 20 has a side portion 21 along the inner wall surface of the through hole 13 and a bottom portion 22 connected to the side portion 21. The first wiring pattern 40 is connected to the bottom portion 22 of the through electrode 20. By connecting the first wiring pattern 40 to the bottom portion 22 in this manner, the connection area between the first wiring pattern 40 and the through electrode 20 can be increased. This makes it possible to suppress increases and fluctuations in the electrical resistance between the first wiring pattern 40 and the through electrode 20. Also, as shown in FIG. 1 , an insulating film 34 (protective film) is provided on the through hole 13 closer to the center than the through electrode 20. This prevents the through electrode 20 from being exposed to the outside, thereby suppressing deterioration of the through electrode 20. Furthermore, it is possible to suppress unintended conduction of the through electrode 20.

[0044] 2B, in Example 1, the first wiring pattern 40 is connected to more than half of the surface of the bottom 22 on the first wiring pattern 40 side. This increases the connection area between the first wiring pattern 40 and the through electrode 20, thereby reducing the electrical resistance between the first wiring pattern 40 and the through electrode 20. In terms of increasing the connection area, the first wiring pattern 40 is preferably connected to more than 60% of the surface of the bottom 22 on the first wiring pattern 40 side, more preferably to more than 70%, and even more preferably to more than 80%.

[0045] Furthermore, in Example 1, the linear expansion coefficient of the insulating film 34 provided closer to the center of the through hole 13 than the through electrode 20 is closer to the linear expansion coefficient of the substrate 10 than the linear expansion coefficient of the through electrode 20. As a result, the insulating film 34 alleviates stress that occurs in the substrate 10 and / or the through electrode 20 due to the difference in the linear expansion coefficients between the substrate 10 and the through electrode 20, thereby suppressing damage to the substrate 10 and the through electrode 20. An example of a case where the linear expansion coefficient of the insulating film 34 is closer to that of the substrate 10 than that of the through electrode 20 is when the substrate 10 is a silicon substrate, a glass substrate, or a quartz substrate, and the insulating film 34 is a silicon oxide film or polysilicon. In this case, the ease of manufacturing the device 100 is also improved.

[0046] 1 , a second wiring pattern 43 formed from the same material as the through electrode 20 is provided on the first surface 11 of the substrate 10 and connected to the through electrode 20. A first terminal electrode 42 connected to the first wiring pattern 40 is provided on the second surface 12 of the substrate 10, and a second terminal electrode 45 connected to the second wiring pattern 43 is provided on the first surface 11. This allows the device 100 of Example 1 to be used as an interposer. Furthermore, since the second wiring pattern 43 is formed from the same material as the through electrode 20, the second wiring pattern 43 and the through electrode 20 can be formed in a single film formation process. This reduces the number of manufacturing steps and reduces the energy and resources used in manufacturing.

[0047] 1 , a cavity 35 is formed inside the insulating film 34 of the through hole 13. Even in this case, exposure of the through electrode 20 to the outside is suppressed, and therefore, deterioration of the through electrode 20 and unintended conduction of the through electrode 20 can be suppressed.

[0048] Although the first embodiment illustrates an example in which a cavity 35 is formed inside the insulating film 34 of the through hole 13, the cavity 35 may not be formed. FIGS. 10( a) and 10(b) are cross-sectional views showing an example in which a cavity is not formed in the through hole of the first embodiment. As shown in FIG. 10(a), the through hole 13 may be filled with the insulating film 34 inside the through electrode 20. As shown in FIG. 10(b), the through hole 13 may be filled with the insulating film 34 and another film 38 other than the insulating film 34 inside the through electrode 20. Even in these cases, deterioration of the through electrode 20 and unintended conduction of the through electrode 20 can be suppressed. It is preferable that the linear expansion coefficient of the other film 38 be closer to the linear expansion coefficient of the substrate 10 than that of the through electrode 20.

[0049] In Example 1, the through electrode 20, the first wiring pattern 40, and the second wiring pattern 43 are formed of titanium nitride. In this way, the through electrode 20, the first wiring pattern 40, and the second wiring pattern 43 are formed of a superconducting material, so that the device 100 can be used as an interposer on which a quantum bit chip is mounted.

[0050] Furthermore, according to Example 1, as shown in Fig. 5(b), a through electrode 20 having a side portion 21 along the inner wall surface of the through hole 13 and a bottom portion 22 connected to the side portion 21 is formed in the through hole 13 of the substrate 10. An insulating film 34 (protective film) is formed in the through hole 13 closer to the center than the through electrode 20. As shown in Fig. 6(c), a first wiring pattern 40 connected to the bottom portion 22 of the through electrode 20 is formed on the second surface 12 of the substrate 10. This makes it possible to increase the connection area between the first wiring pattern 40 and the through electrode 20, and to suppress an increase and variation in the electrical resistance between the first wiring pattern 40 and the through electrode 20.

[0051] In Example 1, as shown in FIG. 4A , a conductive film 84 is formed along the inner surface of a recess 82 formed in the first surface 11 of the substrate 10. As shown in FIG. 5B , the substrate 10 is thinned from the second surface 12 side of the substrate 10. This forms a through electrode 20 having a side portion 21 made of the conductive film 84 along the inner wall surface of the through hole 13 and a bottom portion 22 made of the conductive film 84 connected to the side portion 21. This manufacturing method makes it possible to easily form the through electrode 20 having the side portion 21 along the inner wall surface of the through hole 13 and the bottom portion 22 connected to the side portion 21.

[0052] In addition, in Example 1, the conductive film 84 is deposited by the ALD method along the inner surface of the recess 82. This allows the conductive film 84 to be formed with a uniform thickness on the inner surface of the recess 82 even when the aspect ratio of the recess 82 is large.

[0053] 4B, the conductive film 84 extending from the inner surface of the recess 82 onto the first surface 11 of the substrate 10 is patterned to form the second wiring pattern 43 connected to the through electrode 20 on the first surface 11. This allows the through electrode 20 and the second wiring pattern 43 to be formed in a single film formation process, thereby reducing the number of manufacturing steps. This allows for a reduction in the energy and resources used in manufacturing.

[0054] In the first embodiment, the first wiring pattern 40 is used as the first wiring connected to the bottom 22 of the through electrode 20, but the present invention is not limited to this and may be used, for example, as a through wiring buried in an opening in the insulating film 31. Also, a multilayer wiring structure having one or more wiring layers on the insulating film 34 on the first surface 11 of the substrate 10 and / or one or more wiring layers on the insulating film 32 on the second surface 12 of the substrate 10 may be used.

[0055] FIG. 11( a) is a cross-sectional view of a device according to a second embodiment, and FIG. 11( b) is a cross-sectional view of a device according to a modified example of the second embodiment. As shown in FIG. 11( a), in a device 200 according to the second embodiment, a quantum bit chip 50 is flip-chip mounted on a first surface 11 of a substrate 10 constituting the device 100. The quantum bit chip 50 is bonded to a second terminal electrode 45 by a bump electrode 52. Although not shown, a quantum bit element is formed on the quantum bit chip 50. A circuit chip 51 is flip-chip mounted on a second surface 12 of the substrate 10. The circuit chip 51 is bonded to a first terminal electrode 42 by a bump electrode 46. Although not shown, the circuit chip 51 has active elements such as CMOS elements and / or passive elements such as capacitors and inductors formed thereon.

[0056] 11( b), in a device 210 according to a modification of Example 2, a quantum bit chip 50 is flip-chip mounted on the second surface 12 of a substrate 10 constituting the device 100 by bump electrodes 46. A circuit chip 51 is flip-chip mounted on the first surface 11 of the substrate 10 by bump electrodes 52.

[0057] According to Example 2 and its modified example, quantum bit chip 50 is mounted on one of first surface 11 and second surface 12 of substrate 10, and circuit chip 51 is mounted on the other surface. Device 100 has a large connection area between first wiring pattern 40 and through electrode 20, and increases and variations in electrical resistance between first wiring pattern 40 and through electrode 20 are suppressed. Therefore, by mounting quantum bit chip 50 and circuit chip 51 on device 100, increases and variations in electrical resistance between quantum bit chip 50 and circuit chip 51 are suppressed.

[0058] Example 3 illustrates an example of a quantum bit device in which quantum bit elements are formed. FIG. 12 is a cross-sectional view of a device according to Example 3. As shown in FIG. 12, a device 300 according to Example 3 has a quantum bit element 60 and one or more third wiring patterns 61 provided on an insulating film 34. The quantum bit element 60 is connected to a through electrode 20 via the third wiring pattern 61 and a second wiring pattern 43. An insulating film 36 covering the quantum bit element 60 and the third wiring pattern 61 is provided on the insulating film 34. The insulating film 36 is, for example, a silicon oxide film, and has a thickness of, for example, 100 nm to 300 nm. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0059] FIG. 13( a) is a plan view of a quantum bit device according to a third embodiment, and FIG. 13( b) is a cross-sectional view taken along line A-A in FIG. 13( a). As shown in FIGS. 13( a) and 13(b), the quantum bit device 60 is a Josephson junction device having a lower superconducting film 64, an insulating film 65, and an upper superconducting film 66. The lower superconducting film 64 and the upper superconducting film 66 extend and intersect with each other. The insulating film 65 is provided between the lower superconducting film 64 and the upper superconducting film 66 at least at the intersection of the lower superconducting film 64 and the upper superconducting film 66. The lower superconducting film 64 and the upper superconducting film 66 are made of a superconducting material such as aluminum. The insulating film 65 is made of aluminum oxide, for example.

[0060] 14(a) to 15(c) are cross-sectional views showing a method for manufacturing a device according to Example 3. First, the same manufacturing steps as those shown in Fig. 3(a) to Fig. 7(a) of Example 1 are carried out to obtain Fig. 14(a).

[0061] As shown in FIG. 14B, the insulating film 32 is bonded to a support substrate 86 with an adhesive 85 .

[0062] As shown in FIG. 14C, using a mask layer (not shown) formed on the insulating film 34 as a mask, an opening 91 exposing the second wiring pattern 43 is formed in the insulating film 34 by RIE using, for example, a fluorine-based gas.

[0063] 15(a), a quantum bit element 60 and one or more third wiring patterns 61 are formed on an insulating film 34. The quantum bit element 60 is connected to the second wiring pattern 43 via the third wiring pattern 61. Here, the formation of the quantum bit element 60 and the third wiring pattern 61 will be described with reference to FIGS. 16(a) to 17(c).

[0064] 16( a) to 17(c) are cross-sectional views showing a method for manufacturing a quantum bit element and a third wiring pattern in Example 3. As shown in Fig. 16(a), a lower superconducting film 64 is formed on an insulating film 34, for example, by vapor deposition. An insulating film 65 is formed on the lower superconducting film 64, for example, by ALD. An upper superconducting film 66 is formed on the insulating film 65, for example, by vapor deposition.

[0065] 16B, a mask layer 92, which is, for example, a silicon oxide film, is formed by, for example, CVD on the upper superconducting film 66. Thereafter, the mask layer 92 is patterned.

[0066] As shown in FIG. 16C, the upper superconducting film 66 is etched by RIE using the mask layer 92 as a mask, for example, with a chlorine-based gas.

[0067] As shown in FIG. 17A, the insulating film 65 is etched using the mask layer 92 as a mask, for example, by milling.

[0068] As shown in FIG. 17B, the mask layer 92 is used as a mask to etch the lower superconducting film 64 by RIE using, for example, a chlorine-based gas.

[0069] 17( c), the mask layer 92 is removed. This forms the quantum bit element 60, which is made up of the lower superconducting film 64, the insulating film 65, and the upper superconducting film 66. The lower superconducting film 64, the insulating film 65, and the upper superconducting film 66 also form the third wiring pattern 61. The quantum bit element 60 is connected to the second wiring pattern 43 via the third wiring pattern 61.

[0070] 15B, an insulating film 36 made of a silicon oxide film is formed on the insulating film 34 by, for example, CVD. The thickness of the insulating film 36 is, for example, 200 nm. The insulating film 36 is formed on the insulating film 34, covering the quantum bit element 60 and the third wiring pattern 61.

[0071] 15C, after the support substrate 86 is peeled off, through wiring 41 is formed in the insulating film 32 and a first terminal electrode 42 is formed on the through wiring 41 by a method similar to that shown in FIG. 7C of Example 1. A bump electrode 46 is formed on the first terminal electrode 42. In this way, the device 300 according to Example 3 is formed.

[0072] [Modification] Fig. 18 is a cross-sectional view of a device according to a modification of Example 3. As shown in Fig. 18, in a device 310 according to a modification of Example 3, a quantum bit element 60 and one or more fourth wiring patterns 62 are provided on an insulating film 32. The quantum bit element 60 is connected to the through electrode 20 via the fourth wiring pattern 62 and the first wiring pattern 40. An insulating film 37 covering the quantum bit element 60 and the fourth wiring pattern 62 is provided on the insulating film 32. The insulating film 37 is, for example, a silicon oxide film, and has a thickness of, for example, 100 nm to 300 nm. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0073] 19(a) to 19(c) are cross-sectional views showing a method for manufacturing a device according to a modified example of Example 3. First, the same manufacturing steps as those shown in Fig. 3(a) to Fig. 6(c) of Example 1 are carried out to obtain Fig. 19(a).

[0074] As shown in FIG. 19( b), using a mask layer (not shown) formed on the insulating film 32 as a mask, openings exposing the first wiring patterns 40 are formed in the insulating film 32 by, for example, RIE using a fluorine-based gas. Then, a quantum bit element 60 and one or more fourth wiring patterns 62 are formed on the insulating film 32. The quantum bit element 60 is connected to the first wiring patterns 40 via the fourth wiring patterns 62. The quantum bit element 60 and the fourth wiring patterns 62 are formed by the same method as shown in FIGS. 16( a) to 17(c). Then, an insulating film 37 made of a silicon oxide film is formed on the insulating film 32 by, for example, CVD. The thickness of the insulating film 37 is, for example, 200 nm. The insulating film 37 is formed on the insulating film 32, covering the quantum bit element 60 and the fourth wiring patterns 62.

[0075] 19(c), after the support substrate 86 is peeled off, through wiring 44 is formed in the insulating film 34 by a method similar to that shown in FIG. 7(b) of Example 1, and second terminal electrodes 45 are formed on the through wiring 44. Bump electrodes 46 are formed on the surfaces of the second terminal electrodes 45. In this manner, a device 310 according to a modified example of Example 3 is formed.

[0076] 20( a) to 21(c) are cross-sectional views showing a method for manufacturing a device according to Comparative Example 2. As shown in Fig. 20(a), substrate 110 is heated in an oxidizing atmosphere to form thermal oxide films 180 on first surface 111 and second surface 112 of substrate 110. Next, quantum bit element 160 is formed on thermal oxide film 180 formed on first surface 111 of substrate 110.

[0077] 20B, the insulating film 130, which is a silicon oxide film, is formed by, for example, CVD on the first surface 111 of the substrate 110. The insulating film 130 is formed on the thermal oxide film 180, covering the quantum bit element 160.

[0078] As shown in FIG. 20C, an opening 150 exposing the quantum bit element 160 is formed in the insulating film 130 by RIE using, for example, a fluorine-based gas.

[0079] 21A, a conductive film 140 is formed on the first surface 111 of the substrate 110 by, for example, sputtering. The conductive film 140 is also formed so as to fill in the opening 150 formed in the insulating film 130. The conductive film 140 is formed of, for example, titanium nitride.

[0080] 21B, the conductive film 140 is patterned by RIE using, for example, a chlorine-based gas to form one or more wiring patterns 142. Some of the one or more wiring patterns 142 are connected to the quantum bit device 160.

[0081] 21C, an insulating film 132, which is a silicon oxide film, is formed by, for example, CVD on the first surface 111 of the substrate 110. The insulating film 132 is formed on the insulating film 130, covering the wiring pattern 142.

[0082] When forming a multilayer wiring structure in which a plurality of wiring patterns are stacked, the steps shown in FIGS. 20(b) to 21(c) are repeated.

[0083] According to Comparative Example 2, as shown in FIGS. 20( a ) to 21 ( c ), after forming the quantum bit element 160, the insulating film 130 is deposited and processed, the conductive film 140 is deposited and processed, and the insulating film 132 is deposited. The insulating films 130 and 132 are deposited, for example, by CVD. When deposited by CVD, the substrate 110 reaches a temperature of several hundred degrees Celsius, which may damage the quantum bit element 160. Furthermore, the conductive film 140 is deposited, for example, by sputtering, and the insulating film 130 and the conductive film 140 are processed, for example, by RIE. In sputtering and RIE, charged particles are irradiated onto the insulating films 130 and 132 or the conductive film 140, which may also damage the quantum bit element 160. These factors may degrade the characteristics of the quantum bit element 160.

[0084] On the other hand, in Example 3, as shown in FIG. 12 , a quantum bit element 60 connected to the second wiring pattern 43 is provided on the opposite side of the substrate 10 from the second wiring pattern 43. In a modification of Example 3, as shown in FIG. 18 , a quantum bit element 60 connected to the first wiring pattern 40 is provided on the opposite side of the substrate 10 from the first wiring pattern 40. In Example 3, as shown in FIGS. 14( a ) to 15 ( a ), the quantum bit element 60 is formed after the second wiring pattern 43 is formed. In a modification of Example 3, as shown in FIGS. 19 ( a ) and 19 ( b ), the quantum bit element 60 is formed after the first wiring pattern 40 is formed. In this way, by forming the quantum bit element 60 after the first wiring pattern 40 or the second wiring pattern 43, damage to the quantum bit element 60 can be reduced. Therefore, deterioration of the characteristics of the quantum bit element 60 can be suppressed, and the operation of the quantum bit element 60 can be stabilized. In order to prevent deterioration of the characteristics of the quantum bit device 60, it is preferable that the quantum bit device 60 be formed after both the first wiring pattern 40 and the second wiring pattern 43 have been formed.

[0085] In the third embodiment and its modifications, the wiring layer formed on the substrate 10 side of the quantum bit element 60 may have a multi-layer wiring structure. The quantum bit element 60 is preferably formed after all of the wiring patterns of the multiple wiring layers formed on the substrate 10. By forming the quantum bit element 60 after all of the wiring patterns, damage to the quantum bit element 60 can be reduced, and the annealing temperature in the wiring process can be increased.

[0086] Fig. 22(a) is a cross-sectional view of a device according to Example 4, and Fig. 22(b) is a cross-sectional view of a device according to a modified example of Example 4. As shown in Fig. 22(a), in a device 400 according to Example 4, a circuit chip 51 is flip-chip mounted by bump electrodes 46 onto a second surface 12 of a substrate 10 constituting a device 300. As shown in Fig. 22(b), in a device 410 according to a modified example of Example 4, a circuit chip 51 is flip-chip mounted by bump electrodes 46 onto a first surface 11 of a substrate 10 constituting a device 310.

[0087] According to the fourth embodiment and its modifications, the increase and fluctuation of the electrical resistance between the quantum bit device 60 and the circuit chip 51 are suppressed.

[0088] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0089] 10...substrate, 11...first surface, 12...second surface, 13...through hole, 20, 20a...through electrode, 21...side portion, 22...bottom portion, 30, 31, 32, 33, 34...insulating film, 35...cavity, 36...insulating film, 37...insulating film, 38...other film, 40...first wiring pattern, 41...through wiring, 42...first terminal electrode, 43...second wiring pattern, 44...through wiring, 45...second terminal electrode, 46...bump electrode, 50...quantum bit chip, 51...circuit chip, 52...bump electrode, 60...quantum bit element, 61...third wiring pattern, 62...fourth wiring pattern, 64...lower superconducting film, 65...insulating film, 66...upper superconducting film, 80...thermal oxide film, 81...resist film, 82...recess, 83...thermal oxide film, 84...conductive film, 85...adhesive, 86...support substrate, 87...opening, 88...conductive film, 91...opening, 92...mask layer, 100...device, 110...substrate, 111...first surface, 112...second surface, 120...through electrode, 130, 132...insulating film, 140...conductive film, 142...wiring pattern, 150...opening, 160...quantum bit element, 180...thermal oxide film, 200, 300, 310, 400, 410...device

Claims

1. a substrate having a first surface, a second surface opposite to the first surface, and a through hole penetrating between the first surface and the second surface; a through electrode provided in the through hole, the through electrode having a side portion along an inner wall surface of the through hole and a bottom portion connected to the side portion; a protective film provided on the through hole closer to the center than the through electrode; a first wiring provided on the second surface of the substrate and connected to the bottom of the through electrode.

2. The device according to claim 1 , wherein the first wiring is connected to at least half of the surface of the bottom portion on the first wiring side.

3. The device according to claim 1 , wherein the protective film has a linear expansion coefficient closer to that of the substrate than that of the through electrode.

4. a second wiring provided on the first surface and connected to the through electrode, the second wiring being made of the same material as the through electrode; a first terminal electrode for external connection provided on the second surface and connected to the first wiring; The device according to claim 1 , further comprising: a second terminal electrode for external connection provided on the first surface and connected to the second wiring.

5. a quantum bit chip mounted on one of the first surface and the second surface; The device of claim 4 , further comprising: a circuit chip mounted on the other of the first surface and the second surface.

6. a second wiring provided on the first surface and connected to the through electrode, the second wiring being made of the same material as the through electrode; 3. The device according to claim 1, further comprising: a quantum bit element provided on an opposite side of the substrate with respect to one of the first wiring and the second wiring, and connected to the one wiring.

7. The device according to claim 1 , wherein the through electrode and the first wiring are made of a superconducting material.

8. the substrate is a silicon substrate, a glass substrate, or a quartz substrate; The device according to claim 1 or 2, wherein the protective film is a silicon oxide film or polysilicon.

9. forming a through-hole penetrating between a first surface of a substrate and a second surface opposite to the first surface, the through-hole having a side portion along an inner wall surface of the through-hole and a bottom portion connected to the side portion; forming a protective film on the center side of the through hole relative to the through electrode; and forming a first wiring connected to the bottom of the through electrode on the second surface of the substrate.

10. 10. The method for manufacturing a device according to claim 9, wherein the step of forming the through electrode comprises forming a conductive film along the inner surface of a recess formed on the first surface of the substrate, and then thinning the substrate from the second surface side of the substrate to form the through electrode having a side portion made of the conductive film along the inner wall surface of the through hole and a bottom portion made of the conductive film connected to the side portion.

11. The method for manufacturing a device according to claim 10 , wherein the step of forming the through electrode comprises depositing the conductive film by atomic layer deposition to form the through electrode.

12. 12. The device manufacturing method according to claim 10, further comprising a step of forming second wiring on the first surface by patterning the conductive film extending from the inner surface of the recess onto the first surface of the substrate.

13. The method for manufacturing a device according to claim 9 , further comprising the step of forming, after the first wiring, a quantum bit element connected to the first wiring on the second surface of the substrate.

14. The method for manufacturing a device according to claim 12 , further comprising, after forming the second wiring, forming a quantum bit element connected to the second wiring on the first surface of the substrate.