Semiconductor device

Abstract

The present invention provides a semiconductor device that is provided with a transistor part and a diode part, which are arranged to be side by side in a first direction. This semiconductor device comprises a first mesa part and a second mesa part that is disposed to be more distant from the diode part than the first mesa part. The first mesa part has a first region which has a first conductivity type and is at least partially provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench part. The second mesa part has a second region which has the first conductivity type and a higher dose than the first region, and is at least partially provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench part.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] In a semiconductor device having a transistor portion and a diode portion, a structure is known in which a defect region is partially formed in the diode portion and the transistor portion to adjust the carrier lifetime (see, for example, Patent Document 1). Also, in a semiconductor device, a structure is known in which an electrode and a semiconductor substrate are connected by a trench-shaped contact (see, for example, Patent Document 2). Patent Document 1: WO2021 / 145079 Patent Document 2: Japanese Patent No. 7085975 Problem to be solved

[0003] In a semiconductor device including a transistor portion and a diode portion, it is preferable to improve the reverse recovery loss of the diode portion or the threshold voltage of the transistor portion. General disclosure

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device including a semiconductor substrate having an upper surface and a lower surface, a transistor portion provided in the semiconductor substrate, and a diode portion provided in the semiconductor substrate and arranged side by side with the transistor portion in a first direction. In the above semiconductor device, each of the transistor portion and the diode portion may include a plurality of trench portions provided from the upper surface to the interior of the semiconductor substrate and arranged side by side in the first direction, and a plurality of mesa portions that are portions of the semiconductor substrate sandwiched between two of the trench portions in the first direction. In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type and a base region of a second conductivity type arranged between the drift region and the upper surface. In any of the above semiconductor devices, the plurality of mesa portions may include a first mesa portion and a second mesa portion arranged farther from the diode portion than the first mesa portion. In any of the above semiconductor devices, the first mesa portion may include a first region of a first conductivity type provided at least partially between a depth position of a lower end of the base region and a depth position of a lower end of the trench portion. In any of the above semiconductor devices, the second mesa portion may include a second region of the first conductivity type provided at least partially between a depth position of a lower end of the base region and a depth position of a lower end of the trench portion, the second region having a larger dose than the first region.

[0005] In any of the above semiconductor devices, the first region may be the drift region.

[0006] In any of the above semiconductor devices, the first region may be a region having a doping concentration higher than that of the drift region.

[0007] In any of the above semiconductor devices, the diode section may have a lifetime adjusting region disposed on the upper surface side of the semiconductor substrate and including a lifetime killer that adjusts a lifetime of carriers.

[0008] In any of the above semiconductor devices, the lifetime adjusting region may extend to below the first mesa portion.

[0009] In any of the above semiconductor devices, the plurality of mesas may include one or more of the second mesas, and the lifetime adjusting region may extend to below at least one of the second mesas.

[0010] In any of the above semiconductor devices, the lifetime adjusting region may be disposed apart from the second mesa portion in the first direction.

[0011] In any of the above semiconductor devices, the second region may have a higher doping concentration than the first region.

[0012] In any of the above semiconductor devices, the number of peaks of doping concentration in the depth direction of the second region may be greater than the number of peaks of doping concentration in the depth direction of the first region.

[0013] In any of the above semiconductor devices, the second region may have a width in the depth direction greater than the width in the depth direction of the first region.

[0014] In any of the above semiconductor devices, the dose amount per unit area of ​​the second region may be greater than the dose amount per unit area of ​​the first region.

[0015] In any of the above semiconductor devices, the plurality of mesa portions may include a third mesa portion disposed in the diode portion.

[0016] In any of the above semiconductor devices, the third mesa portion may have an anode region of a second conductivity type disposed between the drift region and the upper surface. In any of the above semiconductor devices, the third mesa portion may have a third region of a first conductivity type provided in at least a portion between a depth position of a lower end of the anode region and a depth position of a lower end of the trench portion. In any of the above semiconductor devices, the second region may have a larger dose than the third region.

[0017] In any of the above semiconductor devices, the transistor portion and the diode portion may each have a metal electrode provided above the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first mesa portion may have a first contact portion with which the metal electrode comes into contact. In any of the above semiconductor devices, the second mesa portion may have a second contact portion with which the metal electrode comes into contact. In any of the above semiconductor devices, a lower end of the second contact portion may be located higher than a lower end of the first contact portion.

[0018] In any of the above semiconductor devices, the transistor portion and the diode portion may each have a metal electrode provided above the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the first mesa portion may have a first contact portion with which the metal electrode comes into contact. In any of the above semiconductor devices, the second mesa portion may have a second contact portion with which the metal electrode comes into contact. In any of the above semiconductor devices, a lower end of the first contact portion may be located higher than a lower end of the second contact portion.

[0019] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0020] 3A is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. It is an enlarged view of region D in FIG. 1. It is a diagram showing an example of an e-e cross section in FIG. 2. It is a diagram showing another ... an example of an f-f cross section in FIG. 2. It is a diagram showing an example of an f-f cross section in FIG. 2. It is a diagram showing an example of an f-f cross section. It is a diagram showing an example of an f-f cross section. It is a diagram showing an example of a doping concentration distribution along the r-r' line and the s-s' line in FIG. 3A. It is a diagram showing another example of a doping concentration distribution along the r-r' line and the s-s' line. It is a diagram showing another example of an e-e cross section. It is an enlarged view of the vicinity of a first mesa portion 61, a second mesa portion 62, and a third mesa portion 63. 10 is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. It is a diagram showing an example of the ff cross section in FIG. 2. It is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 shown in FIG. 9. It is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 shown in FIG. 9. It is a diagram showing an example of a doping concentration distribution along the a-a' line and the bb' line in FIG. 10. It is a diagram showing an example of a doping concentration distribution along the a-a' line and the bb' line in FIG. 10. It is an enlarged view of the periphery of the first contact portion 211 shown in FIG. 9. It is an enlarged view of the periphery of the second contact portion 212 shown in FIG. 9. It is a diagram showing another example of the ee cross section. It is a diagram showing an example of the arrangement of the adjustment region 201 and the non-adjustment region 202 in a top view. It is a diagram showing another example of the ee cross section. It is an enlarged view of the periphery of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. 17 is a diagram showing an example of the ff cross section in Figure 2. It is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 shown in Figure 17. It is a diagram showing an example of the doping concentration distribution along the a-a' line and the bb' line in Figure 18. It is a diagram showing an example of the doping concentration distribution along the a-a' line and the bb' line in Figure 18. It is an enlarged view of the periphery of the first contact portion 211 shown in Figure 16.24 is an enlarged view of the periphery of the second contact portion 212 shown in FIG. 16. FIG. 25 is a view showing another example of the ee cross section. FIG. 26 is a view showing another example of the ee cross section. FIG. 27 is a view showing another example of the ee cross section. FIG. 28 is a view showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. FIG. 29 is a view showing an example of the doping concentration distribution along the lines gg and hh of FIG. 22. FIG. 29 is a view showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. FIG. 30 is a view showing an example of the doping concentration distribution along the lines gg and hh of FIG. 26. FIG. 31 is a view showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. FIG. 32 is a view showing an example of the doping concentration distribution along the lines gg and hh of FIG. 28. FIG. 1 is a diagram showing another example of the e-e cross section. FIG. 2 is a diagram showing another example of the e-e cross section. FIG. 3 is a diagram showing another example of the e-e cross section. FIG. 4 is a diagram showing another example of the e-e cross section. FIG. 5 is a diagram showing another example of the e-e cross section. FIG. 6 is a diagram showing another example of the e-e cross section. FIG. 7 is a diagram showing another example of the e-e cross section. FIG. 8 is a diagram showing another example of the e-e cross section. FIG. 9 is a diagram showing another example of the e-e cross section. FIG. 10 is a diagram showing another example of the e-e cross section. FIG. 11 is a diagram showing another example of the e-e cross section.

[0021] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0022] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0023] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0024] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0025] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0026] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0027] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0028] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0029] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, in which a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as a donor that supplies electrons. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, an interstitial Si—H in a silicon semiconductor, in which interstitial silicon (Si-i) and hydrogen are bonded, also functions as a donor that supplies electrons. In this specification, a VOH defect or an interstitial Si—H may be referred to as a hydrogen donor.

[0030] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants contained substantially uniformly in the ingot that is the base of the semiconductor substrate when the ingot is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors include, but are not limited to, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donors are phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 １７ ~7 x 10 １７ / cm ３ The oxygen concentration in the substrate manufactured by the FZ method is 1×10 １５ ~5 x 10 １６ / cm ３ The higher the oxygen concentration, the more likely it is that hydrogen donors are generated. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or may be a value between 90% and 100% of the chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 １０ / cm ３ That's it, 5 x 10 １２ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 １１ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 １２ / cm ３ The concentrations in the present invention may be values ​​at room temperature, for example, values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0031] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0032] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0033] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0034] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0035] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0036] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0037] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0038] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region overlapped by the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0039] The active section 160 includes a transistor section 70 including a transistor element such as an insulated gate bipolar transistor (IGBT), and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined first direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT). A boundary region is arranged between the transistor section 70 and the diode section 80 in the X-axis direction, but is omitted in FIG. 1 .

[0040] In FIG. 1 , the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." In this specification, a direction different from the first direction in a top view may be referred to as the second direction (the Y-axis direction in FIG. 1 ). The second direction may be perpendicular to the first direction. The transistor section 70 and the diode section 80 may each have a longitudinal direction in the second direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The second direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section and the longitudinal direction of a mesa section, which will be described later.

[0041] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 that extends the diode section 80 in the Y-axis direction to the gate wiring described below may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0042] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0043] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0044] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0045] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0046] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like, or a wiring formed from a semiconductor such as polysilicon doped with impurities.

[0047] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0048] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be metal wiring containing aluminum or the like, or wiring formed from a semiconductor such as polysilicon doped with impurities.

[0049] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 extends in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y axis direction. When the active section 160 is divided by the active side gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X axis direction in each divided region.

[0050] The semiconductor device 100 may include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) which simulates the operation of a transistor section provided in the active section 160.

[0051] In the present example, the semiconductor device 100 includes an edge termination structure 90 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 90 in the present example is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0052] FIG. 2 is an enlarged view of region D in FIG. 1 . Region D includes a transistor section 70, a diode section 80, and an active-side gate wiring 131. Although omitted from FIG. 1 , a boundary region 200 is disposed between the transistor section 70 and the diode section 80 in the X-axis direction. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 is an example of a metal electrode. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0053] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0054] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0055] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0056] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug portion formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0057] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a doping concentration higher than that of the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+-type.

[0058] The transistor section 70, the diode section 80, and the boundary region 200 each have a plurality of trench sections arranged in a first direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the first direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the diode section 80 of this example, no gate trench section 40 is provided. In the boundary region 200 of this example, a plurality of dummy trench sections 30 are provided along the first direction. In the boundary region 200 of this example, no gate trench section 40 is provided.

[0059] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the second direction) extending along a second direction perpendicular to the first direction, and a tip portion 41 connecting the two straight line portions 39. The second direction in FIG. 2 is the Y-axis direction.

[0060] At least a portion of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0061] In the transistor section 70, the dummy trench section 30 is provided between each of the linear portions 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the linear portions 39. The dummy trench section 30 may have a linear shape extending in the second direction, and may have a linear section 29 and an end portion 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both linear dummy trench sections 30 without end portions 31 and dummy trench sections 30 with end portions 31.

[0062] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0063] A mesa portion 60 is provided between each trench portion in the first direction. The mesa portion 60 refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion 60 is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion 60 is provided on the upper surface of the semiconductor substrate 10, extending in the second direction (Y-axis direction) along the trench. The mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200 may have different structures. In this specification, the mesa portion 60 simply refers to the mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200.

[0064] A base region 14 is provided in each mesa portion 60. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e located at one end of each mesa portion in the second direction, a base region 14-e is also located at the other end of each mesa portion. Each mesa portion may be provided with at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0065] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0066] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the second direction (Y-axis direction) of the trench portion.

[0067] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe pattern along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region that contacts the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0068] The mesa portion 60 of the diode portion 80 and the boundary region 200 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surfaces of the mesa portion 60 of the diode portion 80 and the boundary region 200. A contact region 15 may be provided in the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 60, in contact with each of the base regions 14-e. A base region 14 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 60 of the diode portion 80. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15. The mesa portion 60 of the boundary region 200 may have the same structure as the mesa portion 60 of the diode portion 80, or may have a different structure. In the mesa portion 60 of the boundary region 200 of this example, a contact region 15 is provided in the entire region sandwiched between the base regions 14-e. That is, the area of ​​the contact region 15 of the mesa portion 60 in the boundary region 200 may be larger than the area of ​​the contact region 15 of the mesa portion 60 in the diode portion 80. In this case, holes in the semiconductor substrate 10 can be easily extracted to the emitter electrode 52 via the mesa portion 60 in the boundary region 200.

[0069] In another example, the mesa portion 60 of the boundary region 200 may be a P-type impurity region having a doping concentration similar to or lower than that of the base region 14 of the transistor portion 70. The P-type impurity region may occupy the entire mesa portion 60 of the boundary region 200, or another region may be provided in the mesa portion 60 of the boundary region 200. By providing the mesa portion 60 of the boundary region 200 with a P-type impurity region having a doping concentration lower than that of the base region 14, injection of holes from the mesa portion 60 of the boundary region 200 can be suppressed, and reverse recovery loss can be reduced.

[0070] Furthermore, an N-type impurity region having a doping concentration similar to or lower than that of the emitter region 12 may be provided in the mesa portion 60 of the boundary region 200. In this case, however, no gate trench portion 40 is provided in the boundary region 200. Furthermore, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. Because the N-type impurity region of the mesa portion 60 of the boundary region 200 does not contact the gate trench portion 40, no more current flows through the boundary region 200 than through the transistor portion 70. This suppresses the injection of holes from the mesa portion 60 of the boundary region 200, thereby reducing reverse recovery loss.

[0071] A contact hole 54 is provided above each mesa portion 60. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged at the center of the mesa portion 60 in the first direction (X-axis direction).

[0072] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2 , the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0073] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0074] 3A is a diagram showing an example of the ee cross section in FIG. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24.

[0075] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact holes 54 described with reference to FIG. 2 .

[0076] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction. The emitter electrode 52 may have a titanium-containing barrier metal in a portion that contacts the upper surface 21 of the semiconductor substrate 10. The barrier metal may have a titanium nitride layer or a stacked structure of a titanium nitride layer and a titanium layer. The emitter electrode 52 may have a plug portion, such as tungsten, filled inside the contact hole 54. The plug portion may also be provided in a trench contact portion, which will be described later.

[0077] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70, the diode section 80, and the boundary region 200.

[0078] In this example, the multiple mesa portions 60 include one or more first mesa portions 61, one or more second mesa portions 62, one or more third mesa portions 63, and one or more fourth mesa portions 64. The first mesa portion 61 and the second mesa portion 62 are provided in the transistor portion 70, the third mesa portion 63 is provided in the diode portion 80, and the fourth mesa portion 64 is provided in the boundary region 200. The second mesa portion 62 is disposed farther from the diode portion 80 than the first mesa portion 61.

[0079] In the first mesa portion 61 and the second mesa portion 62 of the transistor portion 70, an N+ type emitter region 12 and a P type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14.

[0080] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0081] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the first mesa portion 61 and the second mesa portion 62.

[0082] A P-type base region 14 is provided in the third mesa portion 63 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. In this specification, the base region 14 of the third mesa portion 63 may be referred to as an anode region. The doping concentration of the base region 14 of the third mesa portion 63 may be the same as or lower than the doping concentrations of the base regions 14 of the first mesa portion 61 and the second mesa portion 62. A drift region 18 is provided below the base region 14.

[0083] In this example, a P+ type contact region 15 is provided in the fourth mesa portion 64 of the boundary region 200 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the contact region 15. A base region 14 may be provided between the contact region 15 and the drift region 18.

[0084] In each of the transistor section 70, the diode section 80, and the boundary region 200, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0085] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0086] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0087] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as the donor and acceptor in each region are not limited to the examples described above.

[0088] In the boundary region 200, a P+ type collector region 22 is provided below the buffer region 20. The collector region 22 in the boundary region 200 may have the same doping concentration as the boundary region 200 of the transistor section 70. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 may be the boundary position in the X-axis direction between the diode section 80 and the boundary region 200. In another example, part or all of the collector region 22 in the boundary region 200 may be replaced with the cathode region 82. When the cathode region 82 is provided on the lower surface of the boundary region 200, the region sandwiched between the base regions 14-e, in which the contact regions 15 and the base regions 14 are alternately arranged, may be defined as the diode section 80, and the region sandwiched between the base regions 14-e, in which the contact region 15 is arranged throughout the region, may be defined as the boundary region 200. When the cathode region 82 is provided on the lower surface of the boundary region 200, the boundary region 200 may be considered as part of the diode section 80.

[0089] Of the gate trench portions 40 in contact with the emitter region 12, the gate trench portion 40 that is located closest to the diode portion 80 in the X-axis direction is defined as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80). The center position of the gate trench portion 40 in the X-axis direction may be defined as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80). Of the two trench portions that are in contact with the emitter region 12 that is located closest to the diode portion 80 in the X-axis direction, the trench portion on the diode portion 80 side may be the dummy trench portion 30. In this case, the dummy trench portion 30 may be defined as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80).

[0090] An emitter region 12 may be provided in the boundary region 200. However, in this case, a gate trench portion 40 is not provided in the boundary region 200. Furthermore, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. In other words, no transistor operation occurs in the boundary region 200. A gate trench portion 40 may be provided in the boundary region 200. However, in this case, an emitter region 12 is not provided in the boundary region 200. In other words, no transistor operation occurs in the boundary region 200.

[0091] The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0092] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12 and the contact region 15 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions.

[0093] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. In this example, the diode section 80 and the boundary region 200 are provided with the dummy trench section 30, but not with the gate trench section 40. However, the gate trench section 40 or the dummy trench section 30 may be arranged at the boundary between the boundary region 200 and the transistor section 70.

[0094] The boundary region 200 is a buffer structure for arranging the different structures of the transistor section 70 and the diode section 80 in parallel. Therefore, the width of the boundary region 200 in the X-axis direction may be short. For example, one or several fourth mesa sections 64 may be provided in the boundary region 200, and the boundary region 200 may not be provided at all.

[0095] Furthermore, the boundary region 200 may include a plurality of fourth mesa portions 64 in the X-axis direction. This makes it possible to suppress the influence of the transistor portion 70 on the characteristics of the diode portion 80, for example, the influence of the operation of the gate trench portion 40 and the injection or ejection of holes from or into the contact region 15 on the forward voltage and reverse recovery characteristics. Here, the number of mesa portions refers to the number of mesa portions arranged side by side in the X-axis direction.

[0096] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0097] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0098] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0099] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0100] The semiconductor device 100 of this example includes a lifetime adjustment region 206 including a lifetime killer that adjusts the lifetime of carriers. The lifetime adjustment region 206 of this example is a region where the lifetime of charge carriers is locally short. The charge carriers are electrons or holes. Charge carriers may be simply referred to as carriers. The lifetime adjustment region 206 of this example is formed by injecting charged particles such as helium ions from the top surface 21 side of the semiconductor substrate 10. In this example, the concentration distribution of helium, etc. in the depth direction of the semiconductor substrate 10 may have a shape that trails from the lifetime adjustment region 206 to the top surface 21 of the semiconductor substrate 10. In other words, the concentration ( / cm ) of helium, etc. from the lifetime adjustment region 206 to the top surface 21 ３) may decrease monotonically. The concentration of helium or the like in the upper surface 21 may be greater than 0. On the other hand, the concentration of helium or the like may also have a tail-like shape in the direction from the lifetime adjusting region 206 toward the lower surface 23. However, the concentration of helium or the like decreases more steeply toward the lower surface 23 than toward the upper surface 21. The concentration of helium or the like in the lower surface 23 is lower than the concentration of helium or the like in the upper surface 21. The concentration of helium or the like in the upper surface 21 may be equal to or less than the measurement limit, or may be 0. The lifetime adjusting region 206 may be formed by implanting charged particles such as helium ions from the lower surface 23 side of the semiconductor substrate 10.

[0101] By implanting charged particles such as helium ions into the semiconductor substrate 10, lattice defects 204 such as vacancies are formed near the implantation locations. The lattice defects 204 generate recombination centers. The lattice defects 204 may be primarily vacancies, such as monovacancies (V) and divacancies (VV), dislocations, interstitial atoms, transition metals, etc. For example, atoms adjacent to the vacancies have dangling bonds. In a broad sense, lattice defects 204 may also include donors and acceptors. However, in this specification, vacancy-based lattice defects 204 may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, the lattice defects 204, which serve as recombination centers contributing to carrier recombination, may be simply referred to as recombination centers or lifetime killers. The lifetime killers may be formed by implanting helium ions into the semiconductor substrate 10. The helium chemical concentration may be used as the density of the lattice defects 204. Note that the lifetime killer formed by implanting helium ions may be terminated by hydrogen present in the buffer region 20, and therefore the depth position of the lifetime killer density peak may not coincide with the depth position of the helium chemical concentration peak. Alternatively, when hydrogen ions are implanted into the semiconductor substrate 10, the lifetime killer may be formed in a region through which the hydrogen ions pass, on the implantation surface side relative to the range.

[0102] Lattice defects 204 are an example of a lifetime killer. In FIG. 3A, lattice defects 204 at the injection position of charged particles are schematically indicated by an x ​​mark. In regions where many lattice defects 204 remain, carriers are captured by the lattice defects 204, shortening the carrier lifetime. By adjusting the carrier lifetime, it is possible to adjust the characteristics of the diode section 80, such as the reverse recovery time and reverse recovery loss. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime shows a minimum value may be set as the depth position of the lifetime adjustment region 206.

[0103] The lifetime adjusting region 206 is disposed on the upper surface 21 side of the semiconductor substrate 10. The upper surface 21 side is the region from the central position in the depth direction of the semiconductor substrate 10 to the upper surface 21 of the semiconductor substrate 10. In this example, the lifetime adjusting region 206 is disposed below the lower end of the trench portion.

[0104] Furthermore, when the lifetime adjusting region 206 is formed by irradiation with a particle beam having high penetrating power, such as an electron beam, lattice defects are formed substantially uniformly from the upper surface 21 to the lower surface 23 of the semiconductor substrate 10. In this case as well, the depth position of the lifetime adjusting region 206 can be considered to be located on the upper surface 21 side of the semiconductor substrate 10.

[0105] The lifetime adjusting region 206 is provided in the diode section 80. When the semiconductor device 100 has a boundary region 200, the lifetime adjusting region 206 is also provided in the boundary region 200. The lifetime adjusting region 206 may be provided over the entire diode section 80 in the X-axis direction. The lifetime adjusting region 206 is also provided over the entire boundary region 200.

[0106] The lifetime adjustment region 206 of the diode section 80 is provided extending in the X-axis direction to a portion of the transistor section 70. The lifetime adjustment region 206 of the diode section 80 and the lifetime adjustment region 206 of the transistor section 70 are provided at the same depth position. In the transistor section 70, a region where the lifetime adjustment region 206 is provided is referred to as an adjustment region 201, and a region where the lifetime adjustment region 206 is not provided is referred to as a non-adjustment region 202. The adjustment region 201 is a region that overlaps with the lifetime adjustment region 206 in a top view. The non-adjustment region 202 is a region that does not overlap with the lifetime adjustment region 206 in a top view. The non-adjustment region 202 is a region in which the carrier lifetime at the same depth position as the lifetime adjustment region 206 is longer than the carrier lifetime of the lifetime adjustment region 206 of the diode section 80. The non-adjustment region 202 may be a region into which charged particles such as helium ions are not implanted to form lifetime killers such as lattice defects 204. Chemical concentration ( / cm) of helium, etc. in the unconditioned region 202 ３ ) may be the same as the chemical concentration of the charged particles at the center of the drift region 18 in the Z-axis direction.

[0107] The tuning region 201 has one or more first mesas 61. The lifetime tuning region 206 extends from below the diode region 80 to below the first mesa 61. All of the mesas 60 in the tuning region 201 may be the first mesas 61. The non-tuning region 202 has one or more second mesas 62. All of the mesas 60 in the non-tuning region 202 may be the second mesas 62. The diode region 80 has one or more third mesas 63. All of the mesas 60 in the diode region 80 may be the third mesas 63. The boundary region 200 has one or more fourth mesas 64. All of the mesas 60 in the boundary region 200 may be the fourth mesas 64.

[0108] The first mesa portion 61 has an N-type first region 301 provided in at least a portion between the depth position of the lower end of the base region 14 and the depth position of the lower end of a trench portion such as the gate trench portion 40. In this specification, the depth position of the lower end of the base region 14 may be referred to as Z14, and the depth position of the lower end of the trench portion may be referred to as Zt. The first region 301 may be provided over the entire area between depth position Z14 and depth position Zt.

[0109] The second mesa portion 62 has an N+ type second region 302 provided between depth position Z14 and depth position Zt. The second region 302 may be provided over the entire area between depth position Z14 and depth position Zt. The second region 302 has a higher doping concentration than the first region 301. The first region 301 and the second region 302 may be provided over the entire X-axis direction of each mesa portion. The first region 301 and the second region 302 may be provided so as to cover the entire lower surface of the base region 14 of each mesa portion.

[0110] The dose of the N-type dopant in the second region 302 ( / cm ２ ) is greater than the dose of N-type dopant in the first region 301. The dose of each region may be a value obtained by integrating the doping concentration of each region over a predetermined region in the depth direction. The predetermined region may be an N-type region between the base region 14 and the drift region 18, where the doping concentration is higher than that of the drift region 18. The predetermined region may be within the full width at half maximum of the peak of the N-type doping concentration between the base region 14 and the drift region 18. In this example, the second region 302 has a doping concentration higher than that of the drift region 18. By providing the high-concentration second region 302 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-state voltage can be reduced. The doping concentration of the second region 302 may be 10 times or more, 50 times or more, or 100 times or more than the doping concentration of the drift region 18.

[0111] In this example, the doping concentration of the first region 301 is equal to or greater than the doping concentration of the drift region 18 and less than the doping concentration of the second region 302. The peak value may be used as the value of the doping concentration of each region. The doping concentration of the first region 301 may be the same as the doping concentration of the drift region 18. In other words, the drift region 18 provided in the first mesa portion 61 may be treated as the first region 301. The doping concentration of the first region 301 may be higher than the doping concentration of the drift region 18. The doping concentration of the first region 301 may be half or less, 1 / 10 or less, or 1 / 100 or less of the doping concentration of the second region 302.

[0112] A lifetime adjusting region 206 (see FIG. 3A ) is formed in the adjusting region 201 by irradiating the adjusted region 201 with charged particles from the upper surface 21. On the other hand, a level is formed in the gate insulating film 42 of the adjusting region 201 by the irradiation of charged particles, and the threshold voltage (on voltage, off voltage) in the adjusting region 201 may become lower than the threshold voltage in the non-adjustment region 202. When the threshold voltage decreases, the timing of turn-off becomes slower, so that the turn-off of the adjusting region 201 becomes slower than the non-adjustment region 202, and current may concentrate in the adjusting region 201, reducing the withstand voltage.

[0113] In this example, the doping concentration of the first region 301 of the adjustment region 201 is set lower than the doping concentration of the second region 302. Therefore, the carrier concentration in the drift region 18 and the like of the adjustment region 201 is lowered, thereby suppressing the current flowing through the adjustment region 201. Therefore, even if the turn-off of the adjustment region 201 is delayed, the current flowing through the adjustment region 201 can be suppressed, thereby suppressing a decrease in the withstand voltage.

[0114] 3A , all of the mesas 60 in the adjustment region 201 are first mesas 61 provided with a low-concentration first region 301. In another example, some of the mesas 60 in the adjustment region 201 may be second mesas 62 provided with a high-concentration second region 302. As an example, of the mesas 60 in the adjustment region 201, one or more mesas 60 closest to the non-adjustment region 202 may be second mesas 62. Of the mesas 60 in the adjustment region 201, one or more mesas 60 closest to the diode portion 80 may be first mesas 61.

[0115] The doping concentration of the first region 301 may be the same or different in each first mesa portion 61. For example, the doping concentration of the first region 301 may be higher in the first mesa portion 61 closer to the non-adjusted region 202.

[0116] The doping concentration of the first region 301 may be adjusted according to the density of lattice defects 204 in the lifetime adjusting region 206 provided below. For example, the higher the density of lattice defects 204 below, the lower the doping concentration of the first region 301. As a result, the doping concentration of the first region 301 decreases in a region where a greater amount of charged particles is irradiated. Therefore, the lower the threshold voltage of the first mesa portion 61, the lower the doping concentration of the first region 301 and the lower the carrier concentration. Therefore, the slower the turn-off of the first mesa portion 61, the lower the carrier concentration below, thereby suppressing current concentration. As an example, the density of lattice defects 204 in the lifetime adjusting region 206 in the adjustment region 201 may decrease the farther it is from the diode portion 80. In this case, the doping concentration of the first region 301 may increase in a first mesa portion 61 that is farther from the diode portion 80.

[0117] The third mesa portion 63 and the fourth mesa portion 64 each have an N-type third region 303 provided between depth position Z14 and depth position Zt. The third region 303 may be provided over the entire area between depth position Z14 and depth position Zt. In this example, the second region 302 may have a higher dose than the third region 303. In this example, the third region 303 has a lower doping concentration than the second region 302. The third region 303 may have a higher doping concentration than the first region 301, the same doping concentration as the first region 301, or a lower doping concentration than the first region 301. In another example, the third region 303 may have the same doping concentration as the second region 302. The third region 303 may be provided over the entire X-axis direction of each mesa portion. The third region 303 may be provided so as to cover the entire lower surface of the base region 14 of each mesa portion.

[0118] 3B is a diagram showing an example of the e-e cross section in FIG. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24.

[0119] 3B differs from FIG. 3A in that a third plug region 223 is provided to cover the bottom of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200. Other structures are similar to those of the example shown in FIG. 3A. In this specification, the portion of each mesa portion that contacts the emitter electrode 52 may be referred to as a contact portion. The contact portion of the first mesa portion 61 is referred to as the first contact portion 211, the contact portion of the second mesa portion 62 is referred to as the second contact portion 212, and the contact portions of the third mesa portion 63 and the fourth mesa portion 64 are referred to as the third contact portion 213. The third plug region 223 is a P++-type region with a higher doping concentration than the contact region 15.

[0120] Even when a third plug region 223 is provided to cover the bottom of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200, as in this example, the same effect as that shown in Figure 3A can be obtained.

[0121] 3C is a diagram showing another example of the e-e cross section. This example differs from the example shown in FIG. 3A in that the lifetime adjusting region 206 extends to below at least one second mesa portion 62. The other structures are similar to those of the example shown in FIG. 3A.

[0122] In this example, among the mesa portions 60 in the adjustment region 201, one or more mesa portions 60 closest to the non-adjustment region 202 are second mesa portions 62, and the other mesa portions 60 are first mesa portions 61. In this example, the second region 302 and the lifetime adjustment region 206 partially overlap in a top view. By including the first mesa portion 61 in the adjustment region 201, the carrier density in the vicinity of the first mesa portion 61 can be reduced, thereby suppressing a decrease in the withstand voltage. The number of first mesa portions 61 in the adjustment region 201 may be equal to or greater than the number of second mesa portions 62 in the adjustment region 201. Furthermore, one first mesa portion 61 may be disposed between two second mesa portions 62 in the adjustment region 201. Furthermore, the second mesa portion 62 may be located on the boundary between the adjustment region 201 and the non-adjustment region 202.

[0123] 3D is a diagram showing an example of the e-e cross section in Fig. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24.

[0124] 3D differs from FIG. 3C in that a third plug region 223 is provided to cover the bottoms of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200. The other structures are similar to those of the example shown in FIG. 3C . Even when the third plug region 223 is provided to cover the bottoms of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200 as in this example, the same effect as that of FIG. 3C can be obtained.

[0125] 3E is a diagram showing another example of the e-e cross section. This example differs from the example shown in FIG. 3A in that the second mesa portion 62 and the second region 302 are disposed apart from the lifetime adjusting region 206 in the X-axis direction. The other structures are similar to those of the example shown in FIG. 3A.

[0126] One or more first mesa portions 61 may be provided between the end of the lifetime adjusting region 206 in the X-axis direction and the end of the second region 302 in the X-axis direction. In this example, among the mesa portions 60 in the non-adjustment region 202, one or more mesa portions 60 closest to the adjusting region 201 are first mesa portions 61, and the other mesa portions 60 are second mesa portions 62. By having one or more first mesa portions 61 in the non-adjustment region 202, the distance between the lifetime adjusting region 206 and the second region 302 can be secured, and a decrease in the withstand voltage can be further suppressed. The doping concentration of the first region 301 in the first mesa portion 61 in the non-adjustment region 202 may be the same as or higher than the doping concentration of the first region 301 in the first mesa portion 61 in the adjusting region 201. However, the doping concentration of the first region 301 in the first mesa portion 61 of the non-adjustment region 202 is lower than the doping concentration of the second region 302. Furthermore, the first mesa portion 61 may be located on the boundary between the adjustment region 201 and the non-adjustment region 202.

[0127] 3F is a diagram showing another example of the e-e cross section. This example differs from the example shown in FIG. 3E in that a third plug region 223 is provided so as to cover the bottoms of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200. The other structures are similar to those of the example shown in FIG. 3E. Even when the third plug region 223 is provided so as to cover the bottoms of the third contact portion 213 provided in the third mesa portion 63 of the diode portion 80 and the fourth mesa portion 64 of the boundary region 200 as in this example, the same effect as that of FIG. 3E can be obtained.

[0128] 4A is a diagram showing an example of the ff cross section in FIG. 2. The ff cross section is an XZ plane that passes through the contact region 15 and the cathode region 82. The cross section of this example has a structure in which the emitter region 12 in the example shown in FIG. 3A is replaced with the contact region 15. The structure other than the contact region 15 is the same as that of FIG. 3A.

[0129] 4B is a diagram showing an example of the ff cross section in FIG. 2. The ff cross section is an XZ plane passing through the contact region 15 and the cathode region 82. The cross section of this example has a structure in which the emitter region 12 in the example shown in FIG. 3B is replaced with a contact region 15. The structure other than the contact region 15 is the same as that of FIG. 3B. Also, as shown in FIG. 4B, the first mesa portion 61 may be provided with a first plug region 221 that covers the first contact portion 211. The second mesa portion 62 may be provided with a second plug region 222 that covers the second contact portion 212. The first plug region 221 and the second plug region 222 are P++-type regions with a higher doping concentration than the contact region 15.

[0130] 4C is a diagram showing an example of the ff cross section. The cross section of this example has a structure in which the emitter region 12 in the example shown in FIG. 3C is replaced with a contact region 15. The structure other than the contact region 15 is the same as that of FIG. 3C.

[0131] 4D is a diagram showing an example of an ff cross section. The cross section of this example has a structure in which the emitter region 12 in the example shown in FIG. 3D is replaced with a contact region 15. The structure other than the contact region 15 is the same as that of FIG. 3D. Also, as shown in FIG. 4D , a first plug region 221 covering the first contact portion 211 may be provided in the first mesa portion 61. A second plug region 222 covering the second contact portion 212 may be provided in the second mesa portion 62.

[0132] Fig. 4E is a diagram showing an example of the ff cross section. The cross section of this example has a structure in which the emitter region 12 in the example shown in Fig. 3E is replaced with a contact region 15. The structure other than the contact region 15 is the same as that of Fig. 3E.

[0133] 4F is a diagram showing an example of the ff cross section. The cross section of this example has a structure in which the emitter region 12 in the example shown in FIG. 3F is replaced with a contact region 15. The structure other than the contact region 15 is the same as that of FIG. 3F. Also, as shown in FIG. 4F, a first plug region 221 covering the first contact portion 211 may be provided in the first mesa portion 61. A second plug region 222 covering the second contact portion 212 may be provided in the second mesa portion 62.

[0134] 5 is a diagram showing an example of the doping concentration distribution along the r-r' line and the s-s' line in FIG. 3A. The r-r' line is a line that passes through the first region 301 and is parallel to the Z axis, and the s-s' line is a line that passes through the second region 302 and is parallel to the Z axis.

[0135] In this example, a PN junction is provided at the boundary between the second region 302 and the base region 14. The depth position of this boundary is designated Z14. The doping concentration distribution in the second region 302 has a peak. The doping concentration at the apex of this peak is designated P302. The doping concentration in the drift region 18 is designated D18. The peak concentration P302 is higher than the doping concentration D18. The position on the lower surface 23 side of the apex of the peak where the doping concentration first becomes D18 is designated as depth position Z302 of the lower end of the second region 302.

[0136] In this example, a PN junction is provided at the boundary between the first region 301 and the base region 14. The depth position of this boundary is designated Z14. The doping concentration distribution in the first region 301 in this example has a peak. The doping concentration at the apex of this peak is designated P301. The peak concentration P301 is higher than the doping concentration D18. The position on the lower surface 23 side of the apex of the peak where the doping concentration first becomes D18 is designated as depth position Z301 at the lower end of the first region 301. Depth position Z301 may be the same as or different from depth position Z302.

[0137] The peak concentration P301 is smaller than the peak concentration P302. As described above, the peak concentration P301 may be equal to or less than half, equal to or less than 1 / 10, or equal to or less than 1 / 100 of the peak concentration P302.

[0138] The dose per unit area of ​​the dopant ions in the first region 301 (ions / cm ２ The dose Do301 of the first region 301 may be a value obtained by integrating the doping concentration of the first region 301 from the depth position Z14 to Z301. The dose per unit area (ions / cm) of dopant ions in the second region 302 ２ ) is defined as Do302. The dose Do302 of the second region 302 may be a value obtained by integrating the doping concentration of the second region 302 from the depth position Z14 to Z302. The areas of the hatched portions in FIG. 5 correspond to the respective dose amounts.

[0139] The dose amount Do302 may be greater than the dose amount Do301. The dose amount Do302 may be two times or more, ten times or more, or even one hundred times or more, of the dose amount Do301.

[0140] 6 is a diagram showing another example of the doping concentration distribution along the r-r' line and the s-s' line. In this example, the doping concentration of the first region 301 is the same as the doping concentration of the drift region 18. In this case, the depth position Z302 of the lower end of the second region 302 may be used as the depth position of the lower end of the first region 301.

[0141] The doping concentration D18 of the first region 301 is smaller than the peak concentration P302. The dose Do301 of the first region 301 is smaller than the dose Do302 of the second region 302.

[0142] 7 is a diagram showing another example of the e-e cross section. This example differs from the examples described with reference to FIGS. 1 to 6 in that the first mesa 61 has a first contact portion 211, the second mesa 62 has a second contact portion 212, and the third mesa 63 and the fourth mesa 64 have a third contact portion 213. The other structures are similar to any of the examples described with reference to FIGS. 1 to 6.

[0143] The first contact portions 211 may be provided for some of the first mesas 61, or may be provided for all of the first mesas 61. The second contact portions 212 may be provided for some of the second mesas 62, or may be provided for all of the second mesas 62. The third contact portions 213 may be provided for some of the third mesas 63, or may be provided for all of the third mesas 63. The third contact portions 213 may be provided for some of the fourth mesas 64, or may be provided for all of the fourth mesas 64.

[0144] In this example, each contact portion refers to the interface where the emitter electrode 52 and the semiconductor substrate 10 are in contact. The contact portion may include the surface of the emitter electrode 52 and the surface of the semiconductor substrate 10. When a metal silicide layer is formed at the interface between the emitter electrode 52 and the semiconductor substrate 10, the metal silicide layer may be included in the emitter electrode 52 (metal electrode). In other words, the interface between the metal silicide layer and the semiconductor substrate 10 may be considered as the contact portion.

[0145] At least a portion of the mesa portion 60 may be provided with a trench contact portion 17. The trench contact portion 17 is a portion where a metal electrode such as the emitter electrode 52 is provided inside the semiconductor substrate 10. The trench contact portion 17 can be formed by forming a groove in the upper surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the inside of the groove with a metal electrode. In the mesa portion 60 provided with the trench contact portion 17, the region where the mesa portion 60 and the metal electrode such as the emitter electrode 52 contact each other in the trench contact portion 17 corresponds to the contact portion. In the example of FIG. 7 , the trench contact portion 17 is provided in the first mesa portion 61.

[0146] At least a part of the mesa portion 60 may have a plug region in contact with the lower end of the contact portion. The plug region is a P++-type region having a higher doping concentration than the contact region 15. In the example of FIG. 7 , a third plug region 223 is provided in contact with the third contact portion 213.

[0147] 7 may be provided at a depth shallower than the lower end of the emitter region 12. Note that the first plug region 221 is not provided at the lower end of the first contact portion 211. In another example, the lower end of the first contact portion 211 may be provided at a depth that reaches the base region 14, or the first plug region 221 may be provided so as to contact the lower end of the first contact portion 211.

[0148] 8A is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. In FIG. 8A, one each of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 is shown, and the regions between the mesa portions are omitted.

[0149] The depth position of the lower end of the first contact portion 211 is designated as Z1, the depth position of the lower end of the second contact portion 212 is designated as Z2, and the depth position of the lower end of the third contact portion 213 is designated as Z3. The lower end of each contact portion refers to the lowest portion at the interface between the metal electrode and the semiconductor substrate 10. Depth position Z2 is located higher than depth position Z1. That is, depth position Z1 is farther from the upper surface 21 of the semiconductor substrate 10 than depth position Z2. In the example of FIG. 8A , depth position Z1 is located below the upper surface 21 of the semiconductor substrate 10, and depth position Z2 is located at the same depth as the upper surface 21 of the semiconductor substrate 10. In another example, depth position Z2 may be located between depth position Z1 and the upper surface 21 of the semiconductor substrate 10. In this case, with respect to the upper surface 21 of the semiconductor substrate 10 as a reference, depth position Z2 may be less than half or less than one-quarter of depth position Z1.

[0150] A lifetime adjusting region 206 (see FIG. 7 ) is formed in the adjusting region 201 by irradiating the adjusted region 201 with charged particles from the upper surface 21. On the other hand, the irradiation of the charged particles may form a level in the gate insulating film 42 of the adjusting region 201, and the threshold voltage (on voltage, off voltage) in the adjusting region 201 may become lower than the threshold voltage in the non-adjustment region 202. When the threshold voltage decreases, the timing of turn-off becomes slower, so that the turn-off of the adjusting region 201 becomes slower than the non-adjustment region 202, and current may concentrate in the adjusting region 201, reducing the withstand voltage.

[0151] In the semiconductor device 100 of this embodiment, the depth position Z1 of the first contact portion 211 is set deeper than the depth position Z2 of the second contact portion 212. This makes it easier for holes to be extracted from the semiconductor substrate 10 to the emitter electrode 52 in the first mesa portion 61. Therefore, even if current concentrates in the first mesa portion 61, a decrease in the withstand capability can be suppressed. The depth position Z1 of the first contact portion 211 may be shallower or deeper than the emitter region 12.

[0152] In this example, the lower end of the third contact portion 213 is located higher than the first contact portion 211. The depth position Z3 of the third contact portion 213 may be the same as the depth position Z2 of the second contact portion 212, or may be located between the depth positions Z2 and Z1. The depth position Z3 of the third contact portion 213 may also be the same as the depth position Z1 of the first contact portion 211.

[0153] The third mesa portion 63 may be provided in contact with the lower end of the third contact portion 213 and may have a P++-type third plug region 223 having a higher doping concentration than the base region 14 (anode region). The third plug region 223 may have a higher doping concentration than the contact region 15. The base region 14 (anode region) of the third mesa portion 63 may have a lower doping concentration than the base region 14 of the transistor portion 70. In this case, injection of holes from the third mesa portion 63 into the drift region 18 can be suppressed.

[0154] 7 , at least one first mesa portion 61 is provided with both the trench contact portion 17 and the first region 301. All of the first mesas 61 may have both the trench contact portion 17 and the first region 301. In another example, some of the first mesas 61 may have the first region 301 without having the trench contact portion 17.

[0155] 8B is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. In FIG. 8B, one each of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 is shown, and the regions between the mesa portions are omitted.

[0156] The emitter electrode 52 (metal electrode) of this example includes a barrier metal portion 252 and an upper portion 251. The barrier metal portion 252 is provided above the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54 or the trench contact portion 17. The barrier metal portion 252 may be provided at the lower end of each contact portion. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side surface of the contact hole 54 and the trench contact portion 17. The barrier metal portion 252 may or may not be provided on the upper surface of the interlayer insulating film 38.

[0157] The barrier metal portion 252 is formed of a material that has a higher hydrogen absorbing property than the upper portion 251. This suppresses the penetration of hydrogen into the semiconductor substrate 10. The barrier metal portion 252 in this example contains titanium. The barrier metal portion 252 may include a titanium nitride layer. The barrier metal portion 252 may also be a laminated film of a titanium layer and a titanium nitride layer.

[0158] The upper portion 251 is provided above the barrier metal portion 252. The upper portion 251 is also provided above the interlayer insulating film 38. The upper portion 251 is formed of a material different from that of the barrier metal portion 252. In this example, the upper portion 251 does not contain titanium. As an example, the upper portion 251 contains aluminum. The upper portion 251 may be an alloy of aluminum and silicon. The upper portion 251 inside the contact hole 54 or the trench contact portion 17 may include a plug portion made of tungsten or the like, and the plug portion may be provided up to above the interlayer insulating film 38. Even when the first contact portion 211, the second contact portion 212, and the third contact portion 213 are provided with the barrier metal portion 252 as in this example, the same effect as that shown in FIG. 8A can be obtained.

[0159] 9 is a diagram showing an example of the ff cross section in FIG. 2. The ff cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the ff cross section, the contact region 15 is arranged in place of the emitter region 12 in the ee cross section shown in FIG. 7. The other structures are the same as in the ee cross section. In the ff cross section, the structures of the first contact portion 211, the second contact portion 212, and the third contact portion 213 are also the same as in the ee cross section.

[0160] The first mesa portion 61 in this example is provided in contact with the lower end of the first contact portion 211 and has a P++-type first plug region 221 having a doping concentration higher than that of the contact region 15. At least a portion of the first plug region 221 is provided to overlap the contact region 15 in a top view. That is, the first plug region 221 is provided in any XZ cross section passing through the contact region 15. The first plug region 221 may be provided in an XZ cross section passing through the center of the contact region 15 in the Z-axis direction. A portion of the first plug region 221 may overlap the emitter region 12 in a top view. The first plug region 221 may be provided in an end region of the emitter region 12 that is in contact with the contact region 15. The first plug region 221 may not be provided in any XZ cross section passing through the emitter region 12. For example, the first plug region 221 is not provided in an XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. The first plug region 221 may be provided so that the entirety of the first plug region 221 overlaps with the contact region 15. In this case, the first plug region 221 does not overlap with the emitter region 12 in top view.

[0161] The second mesa portion 62 in this example is provided in contact with the lower end of the second contact portion 212 and has a P++-type second plug region 222 having a doping concentration higher than that of the contact region 15. At least a portion of the second plug region 222 is provided to overlap the contact region 15 in a top view. That is, the second plug region 222 is provided in any XZ cross section passing through the contact region 15. The second plug region 222 may be provided in an XZ cross section passing through the center of the contact region 15 in the Z-axis direction. A portion of the second plug region 222 may overlap the emitter region 12 in a top view. The second plug region 222 may be provided in an end region of the emitter region 12 that is in contact with the contact region 15. The second plug region 222 may not be provided in any XZ cross section passing through the emitter region 12. For example, the second plug region 222 is not provided in an XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. The second plug region 222 may be provided so that the entire second plug region 222 overlaps with the contact region 15. In this case, the second plug region 222 does not overlap with the emitter region 12 in a top view. By providing each plug region, holes can be easily extracted in each mesa portion. This makes it possible to suppress a decrease in the withstand voltage.

[0162] Fig. 10A is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 shown in Fig. 9. Fig. 10A shows one each of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63, and omits the regions between the mesa portions. The structure of the third mesa portion 63 is similar to that of the third mesa portion 63 shown in Fig. 8A.

[0163] The first mesa portion 61 has a contact region 15 instead of the emitter region 12 in the structure shown in Figure 8A, and has a first plug region 221 in contact with the lower end of the first contact portion 211. The other structures are similar to those in the example of Figure 8A. The second mesa portion 62 has a contact region 15 instead of the emitter region 12 in the structure shown in Figure 8A, and has a second plug region 222 in contact with the lower end of the second contact portion 212. The other structures are similar to those in the example of Figure 8A.

[0164] The first plug region 221 may be provided below the second plug region 222. Each plug region is a high-concentration P++-type region. Therefore, if each plug region is located near the channel region (the contact portion between the base region 14 and the gate trench portion 40), acceptors implanted into the plug region are more likely to diffuse to the channel region, increasing the doping concentration of the channel region. As the doping concentration of the channel region increases, the threshold voltage increases.

[0165] In this example, the first plug region 221 is formed deeper than the second plug region 222. This makes it possible to relatively increase the threshold voltage of the first mesa portion 61. This makes it possible to offset the decrease in the threshold voltage of the first mesa portion 61 caused by the formation of the lifetime adjusting region 206.

[0166] The first plug region 221 and the second plug region 222 are doped with impurities at different doses ( / cm ２ ) to form the first plug region 221. This allows the threshold voltage of each mesa portion to be adjusted more accurately. For example, the difference in dose between the first plug region 221 and the second plug region 222 may be set according to the amount of fluctuation in the threshold voltage of the first mesa portion 61 caused by the formation of the lifetime adjusting region 206. This allows the fluctuation in threshold voltage to be offset with precision. The first plug region 221 and the second plug region 222 may be formed by implanting impurities with the same dose. In this case, the semiconductor device can be manufactured using a simple process.

[0167] 10B is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 shown in FIG. 10B shows one each of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63, and omits the regions between the mesa portions. The structure of the third mesa portion 63 is similar to that of the third mesa portion 63 shown in FIG. 8B.

[0168] The first mesa portion 61 has a contact region 15 instead of the emitter region 12 in the structure shown in FIG. 8B , and has a first plug region 221 in contact with the lower end of the first contact portion 211. The other structures are the same as those in the example of FIG. 8B . The second mesa portion 62 has a contact region 15 instead of the emitter region 12 in the structure shown in FIG. 8B , and has a second plug region 222 in contact with the lower end of the second contact portion 212. The other structures are the same as those in the example of FIG. 8B . Even when barrier metal portions 252 are provided in the first contact portion 211, the second contact portion 212, and the third contact portion 213 as in this example, the same effect as that in FIG. 10A can be obtained.

[0169] 11A is a diagram showing an example of doping concentration distributions along lines aa' and bb' in FIG. 10A. Line aa' is a line that passes through the second plug region 222 and is parallel to the Z axis. Line bb' is a line that passes through the first plug region 221 and is parallel to the Z axis. The first plug region 221 and the second plug region 222 have a first peak 231 and a second peak 232 of doping concentration. The second plug region 222 has a doping concentration junction 242 at the boundary with the contact region 15. The first plug region 221 in this example does not have a doping concentration valley at the boundary with the contact region 15, but may have a junction 242 that serves as a valley.

[0170] The dose of the second plug region 222 is defined as D2, and the dose of the first plug region 221 is defined as D1. The dose D2 may be a value obtained by integrating the doping concentration in the depth direction from the bottom position Z2 of the second contact portion 212 to the doping concentration junction 242. Similarly, the dose D1 may be a value obtained by integrating the doping concentration in the depth direction from the bottom position Z1 of the first contact portion 211 to the doping concentration junction 241. If no valley in the doping concentration exists at the boundary between the first plug region 221 and the contact region 15, the dose D1 may be a value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z1. The distance L2 is, for example, the depth distance from the depth position Z2 in the second plug region 222 to the junction 242. In other words, the values ​​obtained by integrating the doping concentration over the same distance L2 in the first plug region 221 and the second plug region 222 may be used as the respective doses. In another example, the value obtained by integrating the doping concentration from the lower end position (Z1 or Z2) of each contact portion to the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of the respective dose amounts. Also, the doping concentration at the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of the respective dose amounts.

[0171] As described above, the dose amount D1 and the dose amount D2 may be the same. The dose amounts being the same may allow an error of ±20%, an error of ±10%, or an error of ±5%.

[0172] 11B is a diagram showing an example of the doping concentration distribution along lines aa' and bb' in FIG. 10B. Line aa' is a line that passes through second plug region 222 and is parallel to the Z axis. Line bb' is a line that passes through first plug region 221 and is parallel to the Z axis. First plug region 221 and second plug region 222 have first and second peaks 231 and 232 of doping concentration.

[0173] The dose of the second plug region 222 is defined as D2, and the dose of the first plug region 221 is defined as D1. The dose D2 may be a value obtained by integrating the doping concentration in the depth direction from the bottom position Z2 of the second contact portion 212 to the junction 242 of the doping concentration. Similarly, the dose D1 may be a value obtained by integrating the doping concentration in the depth direction from the bottom position Z1 of the first contact portion 211 to the junction 241 of the doping concentration. The dose D1 may be a value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z1. The distance L2 is, for example, the depth distance from the depth position Z2 in the second plug region 222 to the junction 242. In other words, the values ​​obtained by integrating the doping concentration over the same distance L2 in the first plug region 221 and the second plug region 222 may be used as the respective doses. In another example, the value obtained by integrating the doping concentration from the lower end position (Z1 or Z2) of each contact portion to the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of the respective dose amounts. Also, the doping concentration at the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of the respective dose amounts.

[0174] The lower end of the first contact portion 211, which is the bottom of the trench contact portion 17, contacts a region of the contact region 15 having a lower doping concentration than the lower end of the second contact portion 212. This suppresses the injection of holes from the first mesa portion 61 and reduces reverse recovery loss compared to when the lower end position Z1 of the first contact portion 211 is at the same depth as the lower end position Z2 of the second contact portion 212. Therefore, by providing the trench contact portion 17 in the first mesa portion 61 of the transistor section 70, it is possible to reduce reverse recovery loss.

[0175] As described above, the dose amount D1 and the dose amount D2 may be the same. The dose amounts being the same may allow an error of ±20%, an error of ±10%, or an error of ±5%.

[0176] The first plug region 221 and the second plug region 222 are formed by exposing the bottoms of the first contact portion 211 and the second contact portion 212 and implanting ions into the exposed portions. The difference in doping concentration between the contact regions 15 of the first contact portion 211 and the second contact portion 212 is sufficiently smaller than the doping concentrations of the first peak 231 and the second peak 232.

[0177] 12A is an enlarged view of the periphery of the first contact portion 211. The barrier metal portion 252 of this example has a first layer 253 and a second layer 254. The first layer 253 is a titanium layer or a titanium nitride layer provided between the upper portion 251 and the semiconductor substrate 10. The second layer 254 is a titanium nitride layer provided between the first layer 253 and the semiconductor substrate 10.

[0178] The barrier metal portion 252 of the first mesa portion 61 is provided inside the contact hole 54 and the trench contact portion 17. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may further include a silicide layer 255. The silicide layer 255 is formed at a position in contact with the semiconductor substrate 10. The silicide layer 255 is a layer in which a portion of the second layer 254 is silicided. At the position of the barrier metal portion 252 in contact with the semiconductor substrate 10, the second layer 254 may not be present at all and may have been converted into the silicide layer 255.

[0179] 12B is an enlarged view of the periphery of the second contact portion 212. Similar to the example of FIG. 8A, the barrier metal portion 252 has a first layer 253 and a second layer 254. The barrier metal portion 252 may also have a silicide layer 255.

[0180] The barrier metal portion 252 of the second mesa portion 62 is provided inside the contact hole 54 and the trench contact portion 17. Therefore, its volume is larger than that of the barrier metal portion 252 of the first mesa portion 61. The thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the first mesa portion 61 may be the same as the thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the second mesa portion 62. The barrier metal portion 252 of the first mesa portion 61 and the barrier metal portion 252 of the second mesa portion 62 may be formed in the same process.

[0181] 13 is a diagram showing another example of the e-e cross section. In this example, the adjustment region 201 includes two or more first mesas 61 aligned in the X-axis direction. The semiconductor device 100 of this example differs from the other examples described in this specification in the structure of the trench contact portion 17 of the first mesa portion 61. The structure other than the trench contact portion 17 of the first mesa portion 61 is the same as any of the embodiments described in this specification.

[0182] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is provided deeper than the trench contact portion 17-1 of a first mesa portion 61 that is arranged closer to the diode portion 80 than the first mesa portion 61. The trench contact portion 17 of each first mesa portion 61 may be formed deeper the farther it is from the diode portion 80. However, the adjustment region 201 may include two or more trench contact portions 17 that are arranged adjacent to each other in the X-axis direction and have the same depth. With this structure, it is possible to gradually change the ease with which holes can be extracted in the adjustment region 201.

[0183] In another example, the depth of each trench contact portion 17 may be adjusted depending on the density of lattice defects 204 in the underlying lifetime adjusting region 206. As an example, the trench contact portion 17 may be formed shallower as the density of lattice defects 204 located below decreases. This makes it easier to offset the fluctuation in threshold voltage. As an example, if the density of lattice defects 204 decreases with increasing distance from the diode portion 80, the trench contact portion 17 may be formed shallower with increasing distance from the diode portion 80.

[0184] 14 is a diagram showing an example of the arrangement of the adjustment region 201 and the non-adjustment region 202 in a top view. The arrangement of this example may be applied to any of the semiconductor devices 100 described in this specification. In FIG. 14, two diode sections 80 and one transistor section 70 are shown, and other regions are omitted. In addition, in FIG. 14, the region where the lifetime adjustment region 206 is provided is hatched with diagonal lines.

[0185] The adjustment region 201 may be provided over the entire diode section 80 in the X-axis direction. The adjustment region 201 is also provided in a region of the transistor section 70 that contacts the diode section 80 (or the boundary region 200). The area of ​​the non-adjustment region 202 in the transistor section 70 may be larger than the area of ​​the adjustment region 201. In the non-adjustment region 202, the second contact portion 212 is disposed above the first contact portion 211. For this reason, the threshold voltage of the non-adjustment region 202 may be lower than the threshold voltage of the adjustment region 201. Even in this case, by increasing the area of ​​the non-adjustment region 202, it is possible to suppress local current concentration even if the turn-off of the non-adjustment region 202 is slower than that of the adjustment region 201.

[0186] In the transistor section 70, the number of second mesa sections 62 (see FIG. 7, etc.) may be greater than the number of first mesa sections 61 (see FIG. 7, etc.). This prevents localized current concentration even if the non-adjustment region 202 turns off slower than the adjustment region 201. In the transistor section 70, the threshold voltage of the second mesa section 62 may be lower than the threshold voltage of the first mesa section 61. The threshold voltage of each mesa section can be adjusted by adjusting the depth of the trench contact section 17 in the first mesa section 61 and the dose amount of each plug region. The threshold voltage of a mesa section is the voltage at which at least one channel region in the mesa section transitions from off to on.

[0187] 15 is a diagram showing another example of the e-e cross section. This example differs from the examples described with reference to FIGS. 1 to 6 in that the first mesa 61 has a first contact portion 211, the second mesa 62 has a second contact portion 212, and the third mesa 63 and the fourth mesa 64 have a third contact portion 213. The other structures are similar to those of the examples described with reference to FIGS. 1 to 6.

[0188] The first contact portions 211 may be provided for some of the first mesas 61, or may be provided for all of the first mesas 61. The second contact portions 212 may be provided for some of the second mesas 62, or may be provided for all of the second mesas 62. The third contact portions 213 may be provided for some of the third mesas 63, or may be provided for all of the third mesas 63. The third contact portions 213 may be provided for some of the fourth mesas 64, or may be provided for all of the fourth mesas 64.

[0189] In this example, each contact portion refers to the interface where the emitter electrode 52 and the semiconductor substrate 10 are in contact. The contact portion may include the surface of the emitter electrode 52 and the surface of the semiconductor substrate 10. When a metal silicide layer is formed at the interface between the emitter electrode 52 and the semiconductor substrate 10, the metal silicide layer may be included in the emitter electrode 52 (metal electrode). In other words, the interface between the metal silicide layer and the semiconductor substrate 10 may be considered as the contact portion.

[0190] At least some of the mesa portions 60 may be provided with trench contact portions 17. The trench contact portions 17 are portions where metal electrodes such as the emitter electrode 52 are provided inside the semiconductor substrate 10. The trench contact portions 17 can be formed by forming grooves in the upper surface 21 of the semiconductor substrate 10 exposed by the contact holes 54 and filling the interiors of the grooves with metal electrodes. In the mesa portion 60 provided with the trench contact portions 17, the regions where the mesa portion 60 and the metal electrodes such as the emitter electrode 52 contact each other correspond to contact portions. In the example of FIG. 15 , the trench contact portions 17 are provided in the second mesa portion 62, the third mesa portion 63, and the fourth mesa portion 64.

[0191] At least a part of the mesa portion 60 may have a plug region in contact with the lower end of the contact portion. The plug region is a P++-type region having a higher doping concentration than the contact region 15. In the example of FIG. 15 , a third plug region 223 is provided in contact with the third contact portion 213.

[0192] 16 is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. In FIG. 16, one each of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 is shown, and the regions between the mesa portions are omitted.

[0193] The emitter electrode 52 (metal electrode) of this example includes a barrier metal portion 252 and an upper portion 251. The barrier metal portion 252 is provided above the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54 or the trench contact portion 17. The barrier metal portion 252 may be provided at the lower end of each contact portion. The barrier metal portion 252 may be in contact with the semiconductor substrate 10. The barrier metal portion 252 may also be provided on the side surface of the contact hole 54 and the trench contact portion 17. The barrier metal portion 252 may or may not be provided on the upper surface of the interlayer insulating film 38.

[0194] The barrier metal portion 252 is formed of a material that has a higher hydrogen absorbing property than the upper portion 251. This suppresses the penetration of hydrogen ions into the semiconductor substrate 10. The barrier metal portion 252 in this example contains titanium. The barrier metal portion 252 may include a titanium nitride layer. The barrier metal portion 252 may also be a laminated film of a titanium layer and a titanium nitride layer.

[0195] The upper portion 251 is provided above the barrier metal portion 252. The upper portion 251 is also provided above the interlayer insulating film 38. The upper portion 251 is formed of a material different from that of the barrier metal portion 252. In this example, the upper portion 251 does not contain titanium. As an example, the upper portion 251 contains aluminum. The upper portion 251 may be an alloy of aluminum and silicon. The upper portion 251 inside the contact hole 54 or the trench contact portion 17 may include a plug portion made of tungsten or the like, and the plug portion may be provided up to above the interlayer insulating film 38.

[0196] The depth position of the lower end of the first contact portion 211 is designated as Z1, the depth position of the lower end of the second contact portion 212 is designated as Z2, and the depth position of the lower end of the third contact portion 213 is designated as Z3. The lower end of each contact portion refers to the lowest portion at the interface between the metal electrode and the semiconductor substrate 10. Depth position Z1 is located above depth position Z2. That is, depth position Z2 is farther from the upper surface 21 of the semiconductor substrate 10 than depth position Z1. In the example of FIG. 16 , depth position Z2 is located below the upper surface 21 of the semiconductor substrate 10, and depth position Z1 is located at the same depth as the upper surface 21 of the semiconductor substrate 10. In another example, depth position Z1 may be located between depth position Z2 and the upper surface 21 of the semiconductor substrate 10. In this case, with respect to the upper surface 21 of the semiconductor substrate 10 as a reference, depth position Z1 may be less than half or less than one-quarter of depth position Z2.

[0197] A lifetime adjusting region 206 (see FIG. 15 ) is formed in the adjusting region 201 by irradiating the adjusted region 201 with charged particles from the upper surface 21. On the other hand, a level is formed in the gate insulating film 42 of the adjusting region 201 by the irradiation of charged particles, and the threshold voltage (on voltage, off voltage) in the adjusting region 201 may become lower than the threshold voltage in the non-adjustment region 202. When the threshold voltage decreases, the timing of turn-off becomes slower, so that the turn-off of the adjusting region 201 becomes slower than the non-adjustment region 202, and current may concentrate in the adjusting region 201, reducing the withstand voltage.

[0198] In the semiconductor device 100 of this example, the depth position Z2 of the second contact portion 212 is set deeper than the depth position Z1 of the first contact portion 211. This makes it easier to make the volume of the barrier metal portion 252 in one second mesa portion 62 larger than the volume of the barrier metal portion 252 in one first mesa portion 61. Note that the volume of the barrier metal portion 252 in one mesa portion refers to the volume of the barrier metal portion 252 provided inside the trench contact portion 17 and the contact hole 54 above the mesa portion.

[0199] The manufacturing process of the semiconductor device 100 includes, for example, a process of annealing the semiconductor substrate 10 in a hydrogen atmosphere. This process allows oxygen to penetrate into the semiconductor substrate 10 and the insulating film, terminating defects. This prevents a decrease in the threshold voltage.

[0200] Because the barrier metal portion 252 absorbs hydrogen, the penetration of hydrogen into the first mesa portion 61, in which a large amount of the barrier metal portion 252 is formed, is suppressed compared to the second mesa portion 62. As a result, the threshold voltage of the first mesa portion 61 is lower than that of the second mesa portion 62, and the threshold voltage of the first mesa portion 61 can be relatively increased. This can offset the decrease in the threshold voltage of the first mesa portion 61 caused by the formation of the lifetime adjusting region 206. The volume of the barrier metal portion 252 in one second mesa portion 62 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more the volume of the barrier metal portion 252 in one first mesa portion 61.

[0201] In this example, the lower end of the first contact portion 211 is located higher than the third contact portion 213. The depth position Z3 of the third contact portion 213 may be the same as the depth position Z2 of the second contact portion 212, or may be located between the depth positions Z2 and Z1. The depth position Z3 of the third contact portion 213 may also be the same as the depth position Z1 of the first contact portion 211.

[0202] The third mesa portion 63 may be provided in contact with the lower end of the third contact portion 213 and may have a P++-type third plug region 223 having a higher doping concentration than the base region 14 (anode region). The third plug region 223 may have a higher doping concentration than the contact region 15. The base region 14 (anode region) of the third mesa portion 63 may have a lower doping concentration than the base region 14 of the transistor portion 70. In this case, injection of holes from the third mesa portion 63 into the drift region 18 can be suppressed.

[0203] 15 , at least one second mesa portion 62 is provided with both the trench contact portion 17 and the second region 302. All of the second mesas 62 may have both the trench contact portion 17 and the second region 302. In another example, some of the second mesas 62 may not have the trench contact portion 17 but may have the second region 302. Furthermore, some of the second mesas 62 may have the trench contact portion 17 but may not have the second region 302.

[0204] 17 is a diagram showing an example of the ff cross section in FIG. 2. The ff cross section is an XZ plane passing through the contact region 15 and the cathode region 82. In the ff cross section, the contact region 15 is arranged in place of the emitter region 12 in the ee cross section shown in FIG. 15. The other structures are the same as in the ee cross section. In the ff cross section, the structures of the first contact portion 211, the second contact portion 212, and the third contact portion 213 are also the same as in the ee cross section.

[0205] The first mesa portion 61 in this example is provided in contact with the lower end of the first contact portion 211 and has a P++-type first plug region 221 having a doping concentration higher than that of the contact region 15. At least a portion of the first plug region 221 is provided to overlap the contact region 15 in a top view. That is, the first plug region 221 is provided in any XZ cross section passing through the contact region 15. The first plug region 221 may be provided in an XZ cross section passing through the center of the contact region 15 in the Z-axis direction. A portion of the first plug region 221 may overlap the emitter region 12 in a top view. The first plug region 221 may be provided in an end region of the emitter region 12 that is in contact with the contact region 15. The first plug region 221 may not be provided in any XZ cross section passing through the emitter region 12. For example, the first plug region 221 is not provided in an XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. The first plug region 221 may be provided so that the entirety of the first plug region 221 overlaps with the contact region 15. In this case, the first plug region 221 does not overlap with the emitter region 12 in top view.

[0206] The second mesa portion 62 in this example is provided in contact with the lower end of the second contact portion 212 and has a P++-type second plug region 222 having a doping concentration higher than that of the contact region 15. At least a portion of the second plug region 222 is provided to overlap the contact region 15 in a top view. That is, the second plug region 222 is provided in any XZ cross section passing through the contact region 15. The second plug region 222 may be provided in an XZ cross section passing through the center of the contact region 15 in the Z-axis direction. A portion of the second plug region 222 may overlap the emitter region 12 in a top view. The second plug region 222 may be provided in an end region of the emitter region 12 that is in contact with the contact region 15. The second plug region 222 may not be provided in any XZ cross section passing through the emitter region 12. For example, the second plug region 222 is not provided in an XZ cross section passing through the center of the emitter region 12 in the Z-axis direction. The second plug region 222 may be provided so that the entire second plug region 222 overlaps with the contact region 15. In this case, the second plug region 222 does not overlap with the emitter region 12 in a top view. By providing each plug region, holes can be easily extracted in each mesa portion. This makes it possible to suppress a decrease in the withstand voltage.

[0207] Fig. 18 is an enlarged view of the vicinity of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63 shown in Fig. 17. Fig. 18 shows one each of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63, and omits the regions between the mesa portions. The structure of the third mesa portion 63 is similar to that of the third mesa portion 63 shown in Fig. 16.

[0208] 16, the first mesa portion 61 has a contact region 15 instead of the emitter region 12, and has a first plug region 221 in contact with the lower end of the first contact portion 211. The other structures are the same as those in the example of FIG. 16. The second mesa portion 62 has a contact region 15 instead of the emitter region 12, and has a second plug region 222 in contact with the lower end of the second contact portion 212. The other structures are the same as those in the example of FIG. 16.

[0209] The second plug region 222 may be provided below the first plug region 221. Each plug region is a high-concentration P++-type region. The first plug region 221 and the second plug region 222 are doped with impurities at different doses ( / cm ２ The first plug region 221 and the second plug region 222 may be formed by implanting impurities at the same dose. In this case, the semiconductor device can be manufactured by a simple process.

[0210] 19A is a diagram showing an example of the doping concentration distribution along lines aa' and bb' in FIG. 18. Line aa' is a line that passes through the second plug region 222 and is parallel to the Z axis. Line bb' is a line that passes through the first plug region 221 and is parallel to the Z axis. The first plug region 221 and the second plug region 222 have a first peak 231 and a second peak 232 of the doping concentration. The first plug region 221 has a doping concentration junction 241 at the boundary with the contact region 15. The second plug region 222 in this example does not have a doping concentration valley at the boundary with the contact region 15, but may have a junction 241 that serves as a valley.

[0211] The dose of the second plug region 222 is defined as D2, and the dose of the first plug region 221 is defined as D1. The dose D1 may be a value obtained by integrating the doping concentration in the depth direction from the bottom position Z1 of the first contact portion 211 to the doping concentration junction 241. Similarly, the dose D2 may be a value obtained by integrating the doping concentration in the depth direction from the bottom position Z2 of the second contact portion 212 to the doping concentration junction 242. If there is no valley in the doping concentration at the boundary between the second plug region 222 and the contact region 15, the dose D2 may be a value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z2. The distance L2 is, for example, the depth distance from the depth position Z1 in the first plug region 221 to the junction 241. In other words, the values ​​obtained by integrating the doping concentration over the same distance L2 in the first plug region 221 and the second plug region 222 may be used as the respective doses. In another example, the value obtained by integrating the doping concentration from the lower end position (Z1 or Z2) of each contact portion to the peak of the doping concentration (peak 231 or peak 232) may be used as an indicator of the respective dose. Also, the doping concentration at the peak of the doping concentration (peak 231 or peak 232) may be used as an indicator of the respective dose.

[0212] As described above, the dose amount D1 and the dose amount D2 may be the same. The "same dose amount" may mean that an error of ±20%, an error of ±10%, or an error of ±5% is acceptable. The first plug region 221 and the second plug region 222 are formed by exposing the first contact portion 211 and the second contact portion 212 and then performing ion implantation. However, the difference in doping concentration between the contact regions 15 of the first contact portion 211 and the second contact portion 212 is sufficiently smaller than the doping concentrations of the first peak 231 and the second peak 232 to be formed.

[0213] 19B is a diagram showing an example of the doping concentration distribution along lines aa' and bb' in FIG. 18. Line aa' is a line that passes through second plug region 222 and is parallel to the Z axis. Line bb' is a line that passes through first plug region 221 and is parallel to the Z axis. First plug region 221 and second plug region 222 have first and second peaks 231 and 232 of doping concentration.

[0214] The dose of the second plug region 222 is defined as D2, and the dose of the first plug region 221 is defined as D1. The dose D1 may be a value obtained by integrating the doping concentration in the depth direction from the lower end position Z1 of the first contact portion 211 to the junction 241 of the doping concentration. Similarly, the dose D2 may be a value obtained by integrating the doping concentration in the depth direction from the lower end position Z2 of the second contact portion 212 to the junction 242 of the doping concentration. The dose D2 may be a value obtained by integrating the doping concentration over a predetermined depth distance L2 from the depth position Z2. The distance L2 is, for example, the depth distance from the depth position Z1 in the first plug region 221 to the junction 241. In other words, the values ​​obtained by integrating the doping concentration over the same distance L2 in the first plug region 221 and the second plug region 222 may be used as the respective doses. In another example, the value obtained by integrating the doping concentration from the lower end position (Z1 or Z2) of each contact portion to the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of the respective dose amounts. Also, the doping concentration at the peak of the doping concentration (first peak 231 or second peak 232) may be used as an indicator of the respective dose amounts.

[0215] The lower end of the first contact portion 211 contacts a region of the contact region 15 having a higher doping concentration than the second contact portion 212, which is the bottom of the trench contact portion 17. Therefore, compared to when the lower end position Z1 of the first contact portion 211 is at the same depth as the lower end position Z2 of the second contact portion 212, more holes are injected from the first mesa portion 61, and the forward voltage is smaller. Therefore, by providing the trench contact portion 17 in the first mesa portion 61 of the transistor section 70, it is possible to adjust the trade-off between reverse recovery loss and forward voltage.

[0216] As described above, the dose amount D1 and the dose amount D2 may be the same. The "same dose amount" may mean that an error of ±20%, an error of ±10%, or an error of ±5% is acceptable. The first plug region 221 and the second plug region 222 are formed by exposing the first contact portion 211 and the second contact portion 212 and then performing ion implantation. However, the difference in doping concentration between the contact regions 15 of the first contact portion 211 and the second contact portion 212 is sufficiently smaller than the doping concentrations of the first peak 231 and the second peak 232 to be formed.

[0217] 20A is an enlarged view of the periphery of the first contact portion 211 shown in FIG. 16. The first contact portion 211 may have a structure similar to that of the example in FIG. 12A. The barrier metal portion 252 of this example has a first layer 253 and a second layer 254. The first layer 253 is a titanium layer or a titanium nitride layer provided between the upper portion 251 and the semiconductor substrate 10. The second layer 254 is a titanium nitride layer provided between the first layer 253 and the semiconductor substrate 10.

[0218] The barrier metal portion 252 of the first mesa portion 61 is provided inside the contact hole 54. The barrier metal portion 252 may be in contact with the upper surface 21 of the semiconductor substrate 10. The barrier metal portion 252 may further include a silicide layer 255. The silicide layer 255 is formed at a position in contact with the semiconductor substrate 10. The silicide layer 255 is a layer in which a portion of the second layer 254 is silicided. At the position of the barrier metal portion 252 in contact with the upper surface 21 of the semiconductor substrate 10, the second layer 254 may not be present at all, having been converted into the silicide layer 255.

[0219] 20B is an enlarged view of the periphery of the second contact portion 212 shown in FIG. 16. The second contact portion 212 may have a structure similar to that of the example of FIG. 12B. As in the example of FIG. 20A, the barrier metal portion 252 has a first layer 253 and a second layer 254. The barrier metal portion 252 may also have a silicide layer 255.

[0220] The barrier metal portion 252 of the second mesa portion 62 is provided inside the contact hole 54 and the trench contact portion 17. Therefore, its volume is larger than that of the barrier metal portion 252 of the first mesa portion 61. The thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the first mesa portion 61 may be the same as the thickness of the barrier metal portion 252 provided on the side wall of the contact hole 54 of the second mesa portion 62. The barrier metal portion 252 of the first mesa portion 61 and the barrier metal portion 252 of the second mesa portion 62 may be formed in the same process.

[0221] 21A is a diagram showing another example of the e-e cross section. In this example, the adjustment region 201 includes two or more first mesas 61 aligned in the X-axis direction. The semiconductor device 100 of this example differs from the other examples described in this specification in the structure of the trench contact portion 17 of the first mesa portion 61. The structure other than the trench contact portion 17 of the first mesa portion 61 is the same as any of the aspects described in this specification.

[0222] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is formed deeper than the trench contact portion 17-1 of a first mesa portion 61 that is arranged closer to the diode portion 80 than the first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed deeper the farther they are from the diode portion 80. However, the adjustment region 201 may include two or more trench contact portions 17 that are arranged adjacent to each other in the X-axis direction and have the same depth. With this structure, the volume of the barrier metal portion 252 in the first mesa portion 61 can be gradually changed.

[0223] In another example, the depth of each trench contact portion 17 may be adjusted according to the density of lattice defects 204 in the underlying lifetime adjusting region 206. As an example, the lower the density of the lattice defects 204 located below, the deeper the trench contact portion 17 may be formed. The deeper the trench contact portion 17 is formed, the larger the volume of the barrier metal portion 252 becomes. This makes it easier to offset fluctuations in the threshold voltage. As an example, if the density of lattice defects 204 decreases with increasing distance from the diode portion 80, the deeper the trench contact portion 17 may be formed with increasing distance from the diode portion 80.

[0224] 21B is a diagram showing another example of the e-e cross section. In this example, the non-adjusted region 202 includes two or more second mesas 62 aligned in the X-axis direction. The semiconductor device 100 of this example differs from the other examples described in this specification in the structure of the trench contact portion 17 of the second mesa portion 62. The structure other than the trench contact portion 17 of the second mesa portion 62 is the same as any of the aspects described in this specification.

[0225] In this example, the trench contact portion 17-2 of at least one second mesa portion 62 is formed deeper than the trench contact portion 17-1 of the second mesa portion 62 that is arranged closer to the diode portion 80 than the second mesa portion 62. The trench contact portions 17 of each second mesa portion 62 may be formed deeper as they are further away from the diode portion 80. However, the non-adjustment region 202 may include two or more trench contact portions 17 that are arranged adjacent to each other in the X-axis direction and have the same depth. With this structure, the volume of the barrier metal portion 252 in the second mesa portion 62 can be gradually changed.

[0226] 21C is a diagram showing another example of the e-e cross section. In this example, the adjustment region 201 includes two or more first mesas 61 aligned in the X-axis direction. The semiconductor device 100 of this example differs from the other examples described in this specification in the structure of the trench contact portion 17 of the first mesa portion 61. The structure other than the trench contact portion 17 of the first mesa portion 61 is the same as any of the aspects described in this specification.

[0227] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is formed deeper than the trench contact portion 17-1 of a first mesa portion 61 that is arranged closer to the diode portion 80 than the first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed deeper the farther they are from the diode portion 80. However, the adjustment region 201 may include two or more trench contact portions 17 that are arranged adjacent to each other in the X-axis direction and have the same depth. With this structure, the volume of the barrier metal portion 252 in the first mesa portion 61 can be gradually changed.

[0228] In another example, the depth of each trench contact portion 17 may be adjusted according to the density of lattice defects 204 in the underlying lifetime adjusting region 206. As an example, the lower the density of the lattice defects 204 located below, the deeper the trench contact portion 17 may be formed. The deeper the trench contact portion 17 is formed, the larger the volume of the barrier metal portion 252 becomes. This makes it easier to offset fluctuations in the threshold voltage. As an example, if the density of lattice defects 204 decreases with increasing distance from the diode portion 80, the deeper the trench contact portion 17 may be formed with increasing distance from the diode portion 80.

[0229] 22 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. The second mesa portion 62 of this example has a plurality of second regions 302 in the depth direction. Each of the second regions 302 has a peak doping concentration in the depth direction. The second mesa portion 62 of this example has second regions 302-1 and 302-2.

[0230] In this example, the first mesa 61 has a smaller number of first regions 301 than the number of second regions 302 in the second mesa 62. In Fig. 22, the first mesa 61 has one first region 301. The doping concentration of the first region 301 in this example is the same as that of the drift region 18. The doping concentration of the first region 301 in the depth direction in this example may be constant.

[0231] The third mesa 63 of this example has a smaller number of third regions 303 than the number of second regions 302 of the second mesa 62. The doping concentration of the third regions 303 of this example is the same as that of the first regions 301.

[0232] The structure is the same as any of the embodiments described herein except for the first region 301, the second region 302, and the third region 303. For example, in the example of Fig. 22, each mesa portion does not have a trench contact portion 17, but each mesa portion may have a trench contact portion 17 similar to any of the embodiments described herein.

[0233] 23 is a diagram showing an example of the doping concentration distribution along lines gg and hh in FIG. 22. Line gg is a line parallel to the Z axis that extends from the base region 14 to the drift region 18 in the second mesa 62. Line hh is a line parallel to the Z axis that extends from the base region 14 to the drift region 18 in the first mesa 61. In this specification, the doping concentration of the drift region 18 is designated D18. In this example, the number of doping concentration peaks in the depth direction of the second region 302 of the second mesa 62 is greater than the number of doping concentration peaks in the depth direction of the first region 301 of the first mesa 61. The number of peaks in the first region 301 may be zero.

[0234] In this example, the second mesa portion 62 has, in order from the upper surface 21 side, a second region 302-1 and a second region 302-2. The second region 302-1 and the second region 302-2 each have a doping concentration peak. In other words, the number of doping concentration peaks in the second region 302 in this example is two. The doping concentration P302-1 of the second region 302-1 and the doping concentration P302-2 of the second region 302-2 may be the same or different.

[0235] Between the second region 302-1 and the second region 302-2, there is a valley where the doping concentration exhibits a minimum value. The doping concentration of the valley may be the same as that of the drift region 18. In another example, the doping concentration of the valley may be higher than that of the drift region 18.

[0236] The first mesa portion 61 in this example has a first region 301 with the same doping concentration as the drift region 18. In this example, the number of peaks of the doping concentration in the first region 301 is 0. According to this example, it is possible to adjust the hole injection in the transistor portion 70 near the diode portion 80, suppress a decrease in the withstand capability, and adjust the trade-off between reverse recovery loss and forward voltage.

[0237] 24 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. The second mesa portion 62 of this example is similar to the example of FIG. 22. The first mesa portion 61 of this example has a plurality of first regions 301 in the depth direction. Each of the first regions 301 has a peak doping concentration in the depth direction. The first mesa portion 61 of this example has a first region 301-1 and a first region 301-2.

[0238] The third mesa 63 of this example has the same number of first regions 301 (or third regions 303) as the first mesa 61. The structure other than the first regions 301, the second regions 302, and the third regions 303 is the same as any of the embodiments described in this specification.

[0239] Fig. 25 is a diagram showing an example of the doping concentration distribution along the line gg and the line hh in Fig. 24. The doping concentration distribution in the second mesa portion 62 of this example is similar to the example in Fig. 23.

[0240] The first mesa 61 of this example has first regions 301-1 and first regions 301-2 in this order from the upper surface 21. The number of first regions 301 in the first mesa 61 may be the same as or different from the number of second regions 302 in the second mesa 62.

[0241] The first region 301-1 and the first region 301-2 each have a doping concentration peak. The doping concentration P301-1 of the first region 301-1 and the doping concentration P301-2 of the first region 301-2 may be the same or different. The doping concentration P301-1 of the first region 301-1 may be lower than both the doping concentration P302-1 of the second region 302-1 and the doping concentration P302-2 of the second region 302-2. The doping concentration P301-2 of the first region 301-2 may be lower than both the doping concentration P302-1 of the second region 302-1 and the doping concentration P302-2 of the second region 302-2. The doping concentration P301-1 may be half or less of the doping concentration P302-1, or even one-tenth or less. The doping concentration P301-2 may be half or less of the doping concentration P302-2, or may be one-tenth or less.

[0242] Between the first region 301-1 and the first region 301-2, there is a valley where the doping concentration exhibits a minimum value. The doping concentration of the valley may be the same as that of the drift region 18. In another example, the doping concentration of the valley may be higher than that of the drift region 18. According to this example, it is possible to adjust the hole injection in the transistor section 70 near the diode section 80, suppress a decrease in the withstand capability, and adjust the trade-off between reverse recovery loss and forward voltage.

[0243] 26 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. The second mesa portion 62 of this example is similar to the example of FIG. 22. The first mesa portion 61 of this example has one or more first regions 301 in the depth direction. Each of the first regions 301 has a peak doping concentration in the depth direction. The number of first regions 301 in the first mesa portion 61 is smaller than the number of second regions 302 in the second mesa portion 62. The second mesa portion 62 of this example has two second regions 302, and the first mesa portion 61 has one first region 301.

[0244] The third mesa 63 of this example has the same number of first regions 301 (or third regions 303) as the first mesa 61. The structure other than the first regions 301, the second regions 302, and the third regions 303 is the same as any of the embodiments described in this specification.

[0245] Fig. 27 is a diagram showing an example of the doping concentration distribution along the line gg and the line hh in Fig. 26. The doping concentration distribution in the second mesa portion 62 of this example is similar to the example in Fig. 23.

[0246] In this example, the first mesa portion 61 has one first region 301. The doping concentration P301 of the first region 301 may be smaller than that of either the second region 302-1 or the second region 302-2. In another example, the doping concentration P301 of the first region 301 may be the same as that of either the second region 302-1 or the second region 302-2. Because the number of first regions 301 is smaller than the number of second regions 302, even if the doping concentrations of the peaks are the same, the total dose amount of the first region 301 can be smaller than the total dose amount of the second region 302. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted to suppress a decrease in the withstand voltage and adjust the trade-off between reverse recovery loss and forward voltage.

[0247] 28 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. In this example, the number of first regions 301 in the first mesa portion 61 is the same as the number of second regions 302 in the second mesa portion 62. The number of first regions 301 (or third regions 303) in the third mesa portion 63 may also be the same as the number of first regions 301 in the first mesa portion 61. In the example of FIG. 28 , the first mesa portion 61 has one first region 301, the second mesa portion 62 has one second region 302, and the third mesa portion 63 has one third region 303.

[0248] In this example, the width of the second region 302 in the depth direction is greater than the width of the first region 301 in the depth direction. Each region has a peak doping concentration in the depth direction. The structure other than the first region 301, the second region 302, and the third region 303 is the same as any of the embodiments described in this specification.

[0249] 29 is a diagram showing an example of the doping concentration distribution along line gg and line hh in FIG. 28. The second region 302 has one or more doping concentration peaks. In this example, the second region 302 may be formed by implanting dopants at different depth positions. In this case, doping concentration peaks are provided at each depth position, but if the depth positions are close to each other, the doping concentration peaks may combine and be observed as a single peak.

[0250] In this example, the first region 301 has one peak of doping concentration. The first region 301 may be formed by implanting dopants at a single depth position. In this example, the width W2 of the second region 302 in the depth direction is greater than the width W1 of the first region 301 in the depth direction. The width W2 may be 1.5 times or more, or may be twice or more, of the width W1. The widths of the first region 301 and the second region 302 are the widths of the N-type region between the base region 14 and the drift region 18, where the doping concentration is higher than that of the drift region 18.

[0251] The doping concentration P301 of the first region 301 may be smaller than the doping concentration P302 of the second region 302. In another example, the doping concentration P301 of the first region 301 may be the same as the doping concentration P302 of the second region 302. This example also makes it possible to make the total dose amount of the first region 301 smaller than the total dose amount of the second region 302. This example makes it possible to adjust the hole injection in the transistor section 70 near the diode section 80, suppress a decrease in the withstand voltage, and adjust the trade-off between reverse recovery loss and forward voltage.

[0252] Figure 30 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 described in this specification in that it does not have the lifetime adjusting region 206, the adjusting region 201, and the non-adjusting region 202. The other structures are similar to the semiconductor device 100 of any of the aspects described in this specification. Figure 30 shows an example in which the lifetime adjusting region 206, the adjusting region 201, and the non-adjusting region 202 are deleted from the structure shown in Figure 3A, but the lifetime adjusting region 206, the adjusting region 201, and the non-adjusting region 202 may also be deleted from the structures shown in other figures.

[0253] Figure 31 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 described in this specification in that the lifetime adjusting region 206 is provided over the entire X-axis direction of the transistor section 70. The other structures are similar to those of the semiconductor device 100 of any aspect described in this specification. Figure 31 shows an example in which the lifetime adjusting region 206 is arranged over the entire transistor section 70 in the structure shown in Figure 3A, but the lifetime adjusting region 206 may also be arranged over the entire transistor section 70 in the structures shown in other figures.

[0254] 32 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the structure described in FIG. 13 in the depths of the trench contact portions 17-1 and 17-2. The other structures are similar to those of the semiconductor device 100 of any of the aspects described in this specification.

[0255] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is provided shallower than the trench contact portion 17-1 of a first mesa portion 61 that is arranged closer to the diode portion 80 than the first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed shallower as they are further away from the diode portion 80. According to this example, it is possible to adjust hole injection in the transistor portion 70 near the diode portion 80, suppress a decrease in the withstand capability, and adjust the trade-off between reverse recovery loss and forward voltage.

[0256] 33 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the structure described in FIG. 21A in the depths of the trench contact portions 17-1 and 17-2. The other structures are similar to those of the semiconductor device 100 of any of the aspects described in this specification.

[0257] In this example, the trench contact portion 17-2 of at least one first mesa portion 61 is provided shallower than the trench contact portion 17-1 of a first mesa portion 61 that is arranged closer to the diode portion 80 than the first mesa portion 61. The trench contact portions 17 of each first mesa portion 61 may be formed shallower as they are further away from the diode portion 80. According to this example, it is possible to adjust hole injection in the transistor portion 70 near the diode portion 80, suppress a decrease in the withstand capability, and adjust the trade-off between reverse recovery loss and forward voltage.

[0258] 34 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the structure described in FIG. 21B in the depths of the trench contact portions 17-1 and 17-2. The other structures are similar to those of the semiconductor device 100 of any of the aspects described in this specification.

[0259] In this example, the trench contact portion 17-2 of at least one second mesa portion 62 is provided shallower than the trench contact portion 17-1 of the second mesa portion 62 that is arranged closer to the diode portion 80 than the second mesa portion 62. The trench contact portions 17 of each second mesa portion 62 may be formed shallower as they are further away from the diode portion 80. According to this example, it is possible to adjust hole injection in the transistor portion 70 near the diode portion 80, suppress a decrease in the withstand capability, and adjust the trade-off between reverse recovery loss and forward voltage.

[0260] 35 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the structure described in FIG. 7 in that at least one first mesa portion 61 includes a second contact portion 212. The other structure is similar to that of the semiconductor device 100 of any aspect described in this specification. One or more first mesa portions 61 arranged closest to the second mesa portion 62 may include the second contact portion 212.

[0261] In this example, at least one first mesa portion 61 does not have a trench contact portion 17, similar to the second mesa portion 62. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, a decrease in the withstand voltage can be suppressed, and the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0262] 36 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the structure described in FIG. 7 in that at least one second mesa portion 62 includes a first contact portion 211. The other structure is similar to that of the semiconductor device 100 of any aspect described in this specification. One or more second mesas 61 arranged closest to the first mesa portion 61 may include the first contact portion 211.

[0263] In this example, at least one second mesa portion 62 includes a trench contact portion 17, similar to the first mesa portion 61. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, a decrease in the withstand voltage can be suppressed, and the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0264] 37 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example differs from the structure described in FIG. 15 in that at least one first mesa portion 61 includes a second contact portion 212. The other structure is similar to that of the semiconductor device 100 of any aspect described in this specification. One or more first mesas 61 arranged closest to the second mesa portion 62 may include the second contact portion 212.

[0265] In this example, at least one first mesa portion 61 has a trench contact portion 17, similar to the second mesa portion 62. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, a decrease in the withstand voltage can be suppressed, and the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0266] 38 is a diagram showing another example of the e-e cross section. This structure differs from the structure described in FIG. 15 in that at least one second mesa 62 includes a first contact portion 211. The remaining structure is similar to that of the semiconductor device 100 according to any aspect described in this specification. One or more second mesas 61 arranged closest to the first mesa 61 may include the first contact portion 211.

[0267] In this example, at least one second mesa portion 62 does not have a trench contact portion 17, similar to the first mesa portion 61. According to this example, hole injection in the transistor portion 70 near the diode portion 80 can be adjusted, a decrease in the withstand voltage can be suppressed, and the trade-off between reverse recovery loss and forward voltage can be adjusted.

[0268] FIG. 39 is a diagram showing another example of the e-e cross section. In the semiconductor device 100 of this example, at least one third mesa portion 63 of the diode portion 80 has the trench contact portion 17. All of the third mesa portions 63 of the diode portion 80 may have the trench contact portion 17. Furthermore, at least one fourth mesa portion 64 of the boundary region 200 may also have the trench contact portion 17. All of the fourth mesa portions 64 of the boundary region 200 may have the trench contact portion 17. The other structure is similar to that of the semiconductor device 100 of any of the aspects described herein. FIG. 39 shows an example in which the third mesa portion 63 and the fourth mesa portion 64 have the trench contact portion 17 in the structure shown in FIG. 3A . However, the third mesa portion 63 and the fourth mesa portion 64 may also have the trench contact portion 17 in the structures shown in other figures.

[0269] The trench contact portion 17 of the third mesa portion 63 may be formed shallower or deeper than the trench contact portion 17 of the transistor portion 70, or may be formed to the same depth. The trench contact portion 17 of the fourth mesa portion 64 may be formed shallower or deeper than the trench contact portion 17 of the transistor portion 70, or may be formed to the same depth.

[0270] 39 , the lower end of the third contact portion 213 may be located lower than the lower end of the second contact portion 212. The lower end of the third contact portion 213 may be located at the same depth as the lower end of the second contact portion 212.

[0271] 40 is a diagram showing another example of the e-e cross section. In the semiconductor device 100 of this example, the lower end of the third contact portion 213 of at least one third mesa portion 63 of the diode section 80 is disposed higher than the lower end of the second contact portion 212. The lower ends of the third contact portions 213 of all third mesas 63 of the diode section 80 may be disposed higher than the lower ends of the second contact portions 212. The lower ends of the third contact portions 213 may be disposed at the same height as the upper surface 21 of the semiconductor substrate 10. The fourth mesa portion 64 of the boundary region 200 may have a third contact portion 213 similar to the third mesa portion 63. The other structure is similar to that of the semiconductor device 100 of any aspect described herein.

[0272] The lower end of the third contact portion 213 may be located at the same depth as the lower end of the first contact portion 211. The lower end of the third contact portion 213 may be located above or below the lower end of the first contact portion 211. The lower ends of the third contact portions 213 provided in the fourth mesa portion 64 and the third mesa portion 63 in the boundary region 200 may have third plug regions 223.

[0273] In this example, the third contact portion 213 is shallowly formed, allowing a large portion of the base region 14 of the third mesa portion 63 to remain. This allows the amount of holes injected into the diode portion 80 to be increased, thereby reducing the forward voltage and adjusting the trade-off with reverse recovery loss. Furthermore, even if a barrier metal is provided in the semiconductor device 100, the amount of barrier metal in the third contact portion 213 can be reduced. This suppresses hydrogen absorption in the third contact portion 213, thereby maintaining the amount of hydrogen injected into the transistor portion 70 via the third contact portion 213. This suppresses a decrease in the threshold voltage of the transistor portion 70.

[0274] 41 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. In this example, the first mesa portion 61 is provided with a first contact portion 211, the second mesa portion 62 is provided with a second contact portion 212, and the third mesa portion 63 is provided with a third contact portion 213.

[0275] The emitter electrode 52 of this example does not have a barrier metal portion 252 in the portion that contacts the semiconductor substrate 10. In addition, it does not have the first plug region 221, the second plug region 222, or the third plug region 223. The other structures are similar to those of the semiconductor device 100 of any of the aspects described in this specification.

[0276] In this example as well, the dose in the first region 301 of the first mesa portion 61 is set to be smaller than the dose in the second region 302 of the second mesa portion 62. According to this example, it is possible to adjust the hole injection in the transistor portion 70 near the diode portion 80, suppress a decrease in the withstand capability, and adjust the trade-off between the reverse recovery loss and the forward voltage.

[0277] 42 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. This example differs from the example shown in FIG. 41 in that trench contact portions 17 are provided in the second mesa portion 62 and the third mesa portion 63.

[0278] In this example, the first mesa portion 61 is provided with a first contact portion 211. The second mesa portion 62 is provided with a trench contact portion 17 having a second contact portion 212, and the third mesa portion 62 is provided with a trench contact portion 17 having a third contact portion 213.

[0279] The emitter electrode 52 of this example does not have a barrier metal portion 252 in a portion that contacts the semiconductor substrate 10. It also does not have a first plug region 221, a second plug region 222, or a third plug region 223. The other structures are the same as those of the semiconductor device 100 of any of the aspects described herein. This eliminates the need to provide a trench contact portion 17 in the first mesa portion 61 of the transistor portion 70, thereby reducing the forward voltage. As described above, this example adjusts hole injection in the transistor portion 70 near the diode portion 80, suppresses a decrease in the withstand capability, and adjusts the trade-off between reverse recovery loss and forward voltage.

[0280] 43 is a diagram showing another example of the configuration of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. This example differs from the example shown in FIG. 41 in that a trench contact portion 17 is provided in the first mesa portion 61.

[0281] In this example, the second mesa portion 62 is provided with a second contact portion 212, and the third mesa portion 62 is provided with a third contact portion 213. Also, the first mesa portion is provided with a trench contact portion 17 having a first contact portion 211.

[0282] The emitter electrode 52 of this example does not have a barrier metal portion 252 in a portion that contacts the semiconductor substrate 10. It also does not have a first plug region 221, a second plug region 222, or a third plug region 223. The other structures are the same as those of the semiconductor device 100 of any of the aspects described herein. Thus, by providing the trench contact portion 17 in the first mesa portion 61 of the transistor portion 70, it is possible to reduce reverse recovery loss. As described above, this example makes it possible to adjust hole injection in the transistor portion 70 near the diode portion 80, suppress a decrease in the withstand capability, and adjust the trade-off between reverse recovery loss and forward voltage.

[0283] 41 , 42 , and 43 , the presence or absence of trench contact portions 17 corresponds to the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. For example, all of the first mesas 61 have trench contact portions 17, or none of the first mesas 61 have trench contact portions 17. Similarly, all of the second mesas 62 have trench contact portions 17, or none of the second mesas 62 have trench contact portions 17. Similarly, all of the third mesas 63 have trench contact portions 17, or none of the third mesas 63 have trench contact portions 17.

[0284] In another example, the presence or absence of the trench contact portion 17 does not have to be consistent among all of the first mesa portion 61, the second mesa portion 62, and the third mesa portion 63. For example, some of the first mesas 61 may have the trench contact portion 17, and the remaining first mesas 61 may not have the trench contact portion 17. Similarly, some of the second mesas 62 may have the trench contact portion 17, and the remaining second mesas 62 may not have the trench contact portion 17. Similarly, some of the third mesas 63 may have the trench contact portion 17, and the remaining third mesas 63 may not have the trench contact portion 17. Furthermore, a fourth mesa portion 64 (not shown) that does not have the third plug region 223 may be further included. The fourth mesa portion 64 that does not have the third plug region 223 may or may not have the trench contact portion 17.

[0285] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0286] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0287] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 17...Trench contact portion, 18...Drift region, 20...Buffer region, 21...Upper surface, 22...Collector region, 23...Lower surface, 24...Collector electrode, 29...Straight portion, 30...Dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 41...Tip portion, 42...Gate insulating film, 44...Gate conductive portion, 52...Emitter electrode, 54...Contact hole, 60...Mesa portion, 61...First mesa portion, 62...Second mesa portion, 63...Third mesa portion, 64...Fourth mesa portion, 70...Transistor portion, 80...Diode portion, 81...Extension Long region, 82... cathode region, 90... edge termination structure, 100... semiconductor device, 130... peripheral gate wiring, 131... active side gate wiring, 160... active portion, 162... edge, 164... gate pad, 200... boundary region, 201... adjustment region, 202... non-adjustment region, 204... lattice defects, 206... lifetime adjustment region, 211... first contact portion, 212... second contact portion, 213... third contact portion, 221... first plug region, 222... second plug region, 223... third plug region, 231... peak, 232... peak, 241, 242... junction portion, 251... upper portion, 252... barrier metal portion, 253... first layer, 254... second layer, 255... silicide layer, 301... first region, 302... second region, 303... third region

Claims

1. A semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface; a transistor portion provided on the semiconductor substrate; and a diode portion provided on the semiconductor substrate and arranged alongside the transistor portion in a first direction, Each of the transistor section and the diode section is A plurality of trench portions provided from the upper surface to the inside of the semiconductor substrate and arranged side by side in the first direction; a plurality of mesa portions that are portions of the semiconductor substrate sandwiched between two of the trench portions in the first direction; having the semiconductor substrate has a drift region of a first conductivity type and a base region of a second conductivity type disposed between the drift region and the upper surface; the plurality of mesa portions include a first mesa portion and a second mesa portion disposed farther from the diode portion than the first mesa portion, the first mesa portion has a first region of a first conductivity type provided in at least a portion between a depth position of a lower end of the base region and a depth position of a lower end of the trench portion; The second mesa portion is provided at least partially between a depth position of a lower end of the base region and a depth position of a lower end of the trench portion, and has a second region of a first conductivity type having a larger dose than the first region. Semiconductor device.

2. The first region is the drift region. The semiconductor device according to claim 1 .

3. The first region has a higher doping concentration than the drift region. The semiconductor device according to claim 1 .

4. The diode portion is disposed on the upper surface side of the semiconductor substrate and has a lifetime adjusting region including a lifetime killer that adjusts a lifetime of carriers. The semiconductor device according to claim 1 .

5. The lifetime adjusting region extends to below the first mesa portion. The semiconductor device according to claim 4.

6. the plurality of mesas include one or more of the second mesas, The lifetime adjusting region extends to below at least one of the second mesa portions, and does not extend to below other of the second mesa portions. The semiconductor device according to claim 5 .

7. The lifetime adjusting region is disposed apart from the second mesa portion in the first direction. The semiconductor device according to claim 5 .

8. The second region has a higher doping concentration than the first region. The semiconductor device according to claim 1 .

9. The number of peaks of the doping concentration in the depth direction of the second region is greater than the number of peaks of the doping concentration in the depth direction of the first region. The semiconductor device according to claim 1 .

10. The second region has a width in a depth direction larger than a width in a depth direction of the first region. The semiconductor device according to claim 1 .

11. The dose amount per unit area of ​​the second region is greater than the dose amount per unit area of ​​the first region. The semiconductor device according to claim 1 .

12. the plurality of mesa portions include a third mesa portion disposed in the diode portion, The third mesa portion is an anode region of a second conductivity type disposed between the drift region and the top surface; a third region of the first conductivity type provided at least partially between a depth position of a lower end of the anode region and a depth position of a lower end of the trench portion; The second region has a larger dose than the third region. The semiconductor device according to claim 1 .

13. each of the transistor portion and the diode portion has a metal electrode provided above the top surface of the semiconductor substrate; the first mesa portion has a first contact portion with which the metal electrode comes into contact; the second mesa portion has a second contact portion with which the metal electrode comes into contact; A lower end of the second contact portion is disposed above a lower end of the first contact portion. The semiconductor device according to claim 4 .

14. each of the transistor portion and the diode portion has a metal electrode provided above the top surface of the semiconductor substrate; the first mesa portion has a first contact portion with which the metal electrode comes into contact; the second mesa portion has a second contact portion with which the metal electrode comes into contact; A lower end of the first contact portion is disposed above a lower end of the second contact portion. The semiconductor device according to claim 4 .

15. The lifetime adjusting region is also provided in a part of the transistor portion, the transistor portion includes an adjustment region in which the lifetime adjusting region is provided and a non-adjustment region in which the lifetime adjusting region is not provided, all the mesa portions in the adjustment region are the first mesa portions, All the mesa portions in the non-adjustment region are the second mesa portions. The semiconductor device according to claim 4.

16. The lifetime adjusting region is also provided in a part of the transistor portion, the transistor portion includes an adjustment region in which the lifetime adjusting region is provided and a non-adjustment region in which the lifetime adjusting region is not provided, the adjustment region includes the first mesa portion and the second mesa portion, The number of the first mesa portions in the adjustment region is equal to or greater than the number of the second mesa portions in the adjustment region. The semiconductor device according to claim 4.

17. The lifetime adjusting region is also provided in a part of the transistor portion, the transistor portion includes an adjustment region in which the lifetime adjusting region is provided and a non-adjustment region in which the lifetime adjusting region is not provided, At least a part of the mesa portion in the adjustment region is the first mesa portion, the density of lattice defects in the lifetime adjusting region in the adjusting region decreases with increasing distance from the diode portion, In the adjustment region, the doping concentration of the first region is higher in the first mesa portion that is farther away from the diode portion. The semiconductor device according to claim 4.