Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device equipped with a transistor and a diode comprises: a plurality of trenches which include a gate trench and which are provided to the front surface of a semiconductor substrate; a first-conductivity type drift region provided to the semiconductor substrate; a second-conductivity type base region provided above the drift region; a first-conductivity type emitter region which is provided above the base region and which is higher in doping concentration as compared to the drift region; a first-conductivity type first storage region which is provided below the base region and which is higher in doping concentration as compared to the drift region; a second-conductivity type trench bottom region which is provided below the first storage region and which is higher in doping concentration as compared to the base region; and a first-conductivity type second storage region which is provided deeper than the trench bottom region in the depth direction of the semiconductor substrate and which is higher in doping concentration as compared to the drift region.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 states that "the semiconductor device may further have an electrically floating barrier region 105 of a second conductivity type (hereinafter also simply referred to as a 'barrier region')." [Prior art documents] [Patent documents] [Patent document 1] JP 2019-91892 A [Patent document 2] JP 6472714 A [Patent document 3] JP 5707681 A Problem to be solved

[0003] It is desirable to suppress gate oscillation and arm short-circuit oscillation while reducing on-loss of a semiconductor device. General disclosure

[0004] A first aspect of the present invention provides a semiconductor device having a transistor portion and a diode portion, the semiconductor device comprising: a plurality of trench portions including a gate trench portion provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a first accumulation region of the first conductivity type provided below the base region and having a doping concentration higher than that of the drift region; a trench bottom region of the second conductivity type provided below the first accumulation region and having a doping concentration higher than that of the base region; and a second accumulation region of the first conductivity type provided deeper than the trench bottom region in a depth direction of the semiconductor substrate and having a doping concentration higher than that of the drift region.

[0005] In the semiconductor device, an upper end of the trench bottom region may contact a lower end of the first accumulation region.

[0006] In any of the above semiconductor devices, the lower end of the trench bottom region may contact the upper end of the second accumulation region.

[0007] In any of the above semiconductor devices, the trench bottom region may extend from a lower end of one of the plurality of trench portions to a lower end of another opposing trench portion in a trench arrangement direction of the plurality of trench portions.

[0008] In any of the above semiconductor devices, the thickness of the trench bottom region in the depth direction of the semiconductor substrate may be 20% or more and 100% or less of the trench depth of the plurality of trench portions.

[0009] In any of the above semiconductor devices, the trench bottom region may have a thickness in the depth direction of the semiconductor substrate of not less than 1 μm and not more than 5 μm.

[0010] In any of the above semiconductor devices, the trench bottom region may include a first region provided below the plurality of trench portions and a second region provided below a mesa portion sandwiched between the plurality of trench portions, and the doping concentration of the first region may be higher than the doping concentration of the second region.

[0011] In any of the above semiconductor devices, the trench bottom region may include a first region provided below the plurality of trench portions and a second region provided below a mesa portion sandwiched between the plurality of trench portions, and the doping concentration of the first region may be the same as the doping concentration of the second region.

[0012] Any of the above semiconductor devices may further include a carrier passage region of the first conductivity type below the first accumulation region, in which the trench bottom region is not provided.

[0013] In any of the above semiconductor devices, the second accumulation region may have a protruding portion extending from below the trench bottom region, beyond an end of the trench bottom region, to the outside of the trench bottom region in the trench arrangement direction of the multiple trench portions.

[0014] In any of the above semiconductor devices, the doping concentration in the first accumulation region may have a profile in which a region having a doping concentration that is 50% or more of the maximum doping concentration in the first accumulation region occupies 60% or more and 100% or less of the thickness of the first accumulation region in the depth direction of the semiconductor substrate.

[0015] In any of the above semiconductor devices, the doping concentration in the first accumulation region may have one or more doping concentration peaks in the depth direction of the semiconductor substrate.

[0016] In any of the above semiconductor devices, the thickness of the region having a doping concentration that is 50% or more of the maximum doping concentration in the first accumulation region in the depth direction of the semiconductor substrate may be 1 μm or more and 4 μm or less.

[0017] a second aspect of the present invention provides a method for manufacturing a semiconductor device including a drift region of a first conductivity type, the method including the steps of: forming a plurality of trench portions in a front surface of a semiconductor substrate; forming a base region of a second conductivity type provided above the drift region; forming an emitter region of the first conductivity type above the base region, the emitter region having a doping concentration higher than that of the drift region; forming a first accumulation region of the first conductivity type having a doping concentration higher than that of the drift region by ion implanting dopant from the front surface side of the semiconductor substrate; forming a trench bottom region of the second conductivity type having a doping concentration higher than that of the base region below the first accumulation region by ion implanting dopant from the front surface side of the semiconductor substrate; and forming a second accumulation region of the first conductivity type having a doping concentration higher than that of the drift region at a position deeper in a depth direction of the semiconductor substrate than the trench bottom region by ion implanting dopant from the front surface side of the semiconductor substrate.

[0018] In the above-described method for manufacturing a semiconductor device, the step of forming the first accumulation region may include the step of injecting a dopant into sidewalls of the plurality of trench portions through openings of the plurality of trench portions from a direction having a predetermined inclination with respect to a depth direction of the semiconductor substrate.

[0019] In any of the above methods for manufacturing a semiconductor device, the step of forming the trench bottom region may include the step of implanting a dopant into the bottoms of the plurality of trench portions through openings of the plurality of trench portions in a depth direction of the semiconductor substrate.

[0020] In any of the above-described methods for manufacturing a semiconductor device, the step of forming the second accumulation region may include the step of injecting a dopant into bottoms of the plurality of trench portions through openings of the plurality of trench portions from a direction having a predetermined inclination with respect to a depth direction of the semiconductor substrate.

[0021] Any of the above-described methods for manufacturing a semiconductor device may include a step of forming the first accumulation region and a step of ion implantation to form the second accumulation region, wherein the ion implantation step may include a step of forming the first accumulation region by injecting dopants into sidewalls of the plurality of trench portions through openings of the plurality of trench portions, and a step of forming the second accumulation region by injecting dopants into bottoms of the plurality of trench portions through openings of the plurality of trench portions.

[0022] In any of the above-described methods for manufacturing a semiconductor device, the steps of forming the second accumulation region, forming the trench bottom region, and forming the first accumulation region may be performed before the step of forming the plurality of trench portions.

[0023] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0024] 1 is a diagram showing an example of a top view of the semiconductor device 100. FIG. 2 is a diagram showing an example of a cross section of the semiconductor device 100. FIG. 3 is a diagram showing an example of a doping concentration profile including a flat region. FIG. 4 is a diagram showing a modified example of the cross section of the semiconductor device 100. FIG. 5 is a diagram showing a modified example of the cross section of the semiconductor device 100. FIG. 6 is a diagram showing a modified example of the cross section of the semiconductor device 100. FIG. 7 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. FIG. 8 is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100. FIG. 9 is a diagram showing a modified example of the manufacturing process of the semiconductor device 100.

[0025] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0026] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0027] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0028] In this specification, a plane parallel to the top surface of the semiconductor substrate is referred to as the XY plane, and orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. An axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. The depth direction of the semiconductor substrate may be referred to as the Z-axis. In this specification, a view of the semiconductor substrate in the Z-axis direction is referred to as a planar view. In this specification, a direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as a horizontal direction.

[0029] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0030] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0031] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0032] In this specification, doping concentration means the concentration of donors or acceptors at thermal equilibrium.

[0033] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0034] 1 is a diagram illustrating an example of a top view of a semiconductor device 100 according to this embodiment. The semiconductor device 100 according to this embodiment is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor section 70 according to this embodiment includes a boundary section 90 in a portion adjacent to the diode section 80.

[0035] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. For example, the collector region 22 is a P+ type. The transistor section 70 includes a transistor such as an IGBT.

[0036] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is, for example, an N+ type. The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0037] The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.

[0038] FIG. 1 shows the region around the chip edge, which is the edge side of the semiconductor device 100, and omits other regions. An edge termination structure may be provided in the region on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a combination of these structures. For convenience, the edge on the negative side of the Y-axis direction will be described in this example, but the same applies to the other edges of the semiconductor device 100. The edge termination structure may be provided to surround an active region including the transistor portion 70 and the diode portion 80.

[0039] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0040] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a well region 17, and an anode region 19 on a front surface 21 of a semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0041] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, the well region 17, and the anode region 19. The gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0042] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal layer made of titanium or a titanium compound below the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0043] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0044] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55.

[0045] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. A plug layer made of tungsten or the like may be formed inside the contact hole 56.

[0046] The connection portion 25 is connected to a front surface side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 in this example may be provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0047] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0048] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0049] The dummy trench portion 30 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10. Like the gate trench portion 40, the dummy trench portion 30 may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions.

[0050] The transistor section 70 of this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.

[0051] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, or the ratio of the dummy trench portions 30 may be greater than the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trench portions as gate trench portions 40 and may not have dummy trench portions 30.

[0052] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 described below. The well region 17 is an example of a well region provided on the peripheral side of the active region. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0053] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0054] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0055] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0056] The base region 14 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends in the Y-axis direction of the mesa portion 71 and the mesa portion 81. Note that FIG. 1 shows only one end of the base region 14 in the Y-axis direction.

[0057] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0058] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0059] The contact region 15 is provided above the base region 14 and is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the contact region 15 is, for example, a P+ type. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one to the other of the two trench portions that sandwich the mesa portion 71.

[0060] The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0061] In the depth direction of the semiconductor substrate 10, the thickness of the contact region 15 may be greater than the thickness of the emitter region 12. The lower end of the contact region 15 may be located deeper than the lower end of the emitter region 12.

[0062] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has an anode region 19 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has the anode region 19 and the well region 17 on the negative side in the Y-axis direction.

[0063] The anode region 19 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The doping concentration of the anode region 19 may be lower than the doping concentration of the base region 14. In this example, the anode region 19 is, for example, P-type. In this example, the anode region 19 is provided on the front surface 21 of the mesa portion 81. The anode region 19 may be provided in the X-axis direction from one to the other of the two dummy trench portions 30 that sandwich the mesa portion 81. The anode region 19 may or may not be in contact with the dummy trench portion 30. In this example, the anode region 19 is in contact with the dummy trench portion 30.

[0064] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 may not have the emitter region 12. In one example, the trench portion in the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30. In the boundary portion 90, at least one of the dummy trench portions 30 may be set to a potential different from the gate potential.

[0065] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0066] FIG. 2 shows an example of the a-a' cross section in FIG. 1. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the a-a' cross section, the semiconductor device 100 of this example includes a semiconductor substrate 10 including the emitter region 12, the base region 14, the contact region 15, the first accumulation region 16, the drift region 18, the anode region 19, the trench bottom region 65, the second accumulation region 26, the collector region 22, and the cathode region 82, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0067] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0068] The first accumulation region 16 is a region of a first conductivity type provided below the base region 14 in the semiconductor substrate 10. The doping concentration of the first accumulation region 16 is higher than the doping concentration of the drift region 18. In this example, the first accumulation region 16 is, for example, an N+ type. The doping concentration of the first accumulation region 16 is 4.0E15 cm －３ or more, 1.0E17 cm －３ It may be the following:

[0069] The first accumulation region 16 may be provided in the transistor section 70, but may not be provided in the diode section 80 or the boundary section 90. The first accumulation region 16 may also be provided in the boundary section 90. The first accumulation region 16 may be provided in both the transistor section 70 and the diode section 80. By providing the first accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0070] The first accumulation region 16 may have one or more peaks of doping concentration. The first accumulation region 16 may have one or more peaks of doping concentration in the depth direction of the semiconductor substrate 10. The doping concentration of the first accumulation region 16 may have a profile that includes a flat region. A profile that includes a flat region will be described later.

[0071] The thickness of the first accumulation region 16 in the depth direction of the semiconductor substrate 10 may be greater than the thickness of a trench bottom region 65 (described later) and may be greater than the thickness of the second accumulation region 26. The thickness of the first accumulation region 16 may be 20% or more and 80% or less of the trench depth of the multiple trench portions. The thickness of the region having a doping concentration of 50% or more of the maximum doping concentration in the first accumulation region 16 may be 1 μm or more and 4 μm or less.

[0072] The trench bottom region 65 is a region of the second conductivity type provided below the first accumulation region 16. The doping concentration of the trench bottom region 65 in this example is higher than the doping concentration of the base region 14. The trench bottom region 65 in this example is, for example, P-type. The doping concentration of the trench bottom region 65 is 1.0E14 cm －３ or more, 1.0E16 cm －３ It may be the following:

[0073] The trench bottom region 65 in this example is provided so that its upper end is in contact with the lower end of the first accumulation region 16. The upper end of the trench bottom region 65 does not necessarily have to be in contact with the lower end of the first accumulation region 16.

[0074] The trench bottom region 65 in this example is provided so that its lower end is in contact with the upper end of the second accumulation region 26. The lower end of the trench bottom region 65 does not necessarily have to be in contact with the upper end of the second accumulation region 26.

[0075] In this example, the trench bottom region 65 extends from the lower end of one of the trench portions to the lower end of the other opposing trench portion in the trench arrangement direction of the multiple trench portions. The trench bottom region 65 may extend from the lower end of one of the multiple trench portions, beyond the lower end of the other opposing trench portion, to the lower end of the trench portion adjacent to the other opposing trench portion. In other words, the trench bottom region 65 may extend beyond the lower ends of two or more multiple trench portions.

[0076] The thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10 may be greater than the thickness of the second accumulation region 26 described below. The thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10 may be 20% or more and 100% or less of the trench depth of the multiple trench portions. The thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10 may be 1 μm or more and 5 μm or less.

[0077] The second accumulation region 26 is a region of the first conductivity type that is provided deeper than the trench bottom region 65 in the depth direction of the semiconductor substrate 10. The doping concentration of the second accumulation region 26 may be lower than the doping concentration of the first accumulation region 16. The doping concentration of the second accumulation region 26 is 5.0E14 cm －３ or more, 1.0E17 cm －３ It may be the following:

[0078] The doping concentration of the second accumulation region 26 in this example is higher than the doping concentration of the drift region 18. The second accumulation region 26 in this example is, for example, N-type. As will be described in detail later, by providing the second accumulation region 26, the thickness of the trench bottom region 65 can be controlled.

[0079] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. The collector electrode 24 may be formed of the same conductive material as the emitter electrode 52 and the gate metal layer 50, or may be formed of a different conductive material.

[0080] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0081] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0082] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0083] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more trench contact portions may be provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Similarly, the contact holes 55 and 56 may also have trench contact portions provided so as to penetrate the interlayer insulating film 38.

[0084] 3 is a diagram showing an example of a doping concentration profile including a flat region. In this specification, the doping concentration profile of the first accumulation region 16 including a flat region means that a region having a doping concentration of 50% or more of the maximum doping concentration in the first accumulation region 16 occupies 60% or more and 100% or less of the thickness of the first accumulation region 16 in the depth direction of the semiconductor substrate 10.

[0085] 3, the dotted line indicates the doping concentration of the first conductivity type dopant and is designated by the symbol Cn. The dashed-dotted line indicates the doping concentration of the second conductivity type dopant and is designated by the symbol Cp. The solid line indicates the actual doping concentration obtained by adding Cn and Cp and is designated by the symbol C.

[0086] In FIG. １ The position indicated by D is the upper end of the first accumulation region 16. ３ The position indicated by is the position of the lower end of the first accumulation region 16. In one example, the doping concentration of the first accumulation region 16 is １ The maximum value Pmax is reached at

[0087] In FIG. ２ The position indicated by is the position where the doping concentration is 50% of the maximum value of the doping concentration of the first accumulation region 16. In one example, when the doping concentration profile includes a flat region, the relational expression shown in the following Equation 1 holds. By having the doping concentration profile of the first accumulation region 16 include a flat region, it is possible to suppress a decrease in clamping tolerance.

[0088] Fig. 4A shows a modified example of the cross section taken along line aa' in Fig. 1. Fig. 4A differs from the embodiment shown in Fig. 2 in that a carrier passing region 66 and a protruding portion 67 are provided.

[0089] The carrier passage region 66 is a region of the first conductivity type below the first accumulation region 16 where the trench bottom region 65 is not provided. The carrier passage region 66 may be a region where no additional ions are implanted and where the drift region 18 remains. That is, the doping concentration of the carrier passage region 66 may be the same as the doping concentration of the drift region 18. By providing the carrier passage region 66, the electron barrier is lowered, and the on-loss Eon can be reduced.

[0090] A trench bottom region 65 may be provided in the mesa portion in the region where the carrier passage region 66 is provided. Furthermore, a first accumulation region 16 may be provided in the mesa portion in the region where the carrier passage region 66 is provided.

[0091] The protruding portion 67 is a portion of the second accumulation region 26 that protrudes from below the trench bottom region 65 beyond the end of the trench bottom region 65 in the trench arrangement direction of the multiple trench portions. By providing the protruding portion 67, the thickness of the trench bottom region 65 can be reliably controlled.

[0092] The distance between the outer edge of the trench bottom region 65 and the outer edge of the second accumulation region 26 in the trench arrangement direction of the multiple trench portions is defined as the width W67 of the protruding portion. The width W67 may be greater than 0 and less than or equal to the width between adjacent trenches. The width W67 may also be greater than or equal to the width between adjacent trenches.

[0093] Fig. 4B shows a modified example of the aa' cross section in Fig. 1. Fig. 4B differs from the embodiment shown in Fig. 2 in that a drift region 18 is provided between the base region 14 and the trench bottom region 65.

[0094] 4B, the doping concentration of the first accumulation region 16 has one doping concentration peak. The doping concentration of the first accumulation region 16 may have multiple doping concentration peaks. The doping concentration of the first accumulation region 16 may have a profile that includes flat regions.

[0095] 5 is a diagram showing an example of the vicinity of one mesa portion 71 in the transistor portion 70 of this example. In the example shown in Fig. 5, the trench bottom region 65 includes a first region 65a provided below a plurality of trench portions and a second region 65b provided below the mesa portion 71 sandwiched between the plurality of trench portions.

[0096] The trench bottom region 65 may have a doping concentration distribution in the trench arrangement direction of the multiple trench portions. The doping concentration of the first region 65 a may be higher than the doping concentration of the second region 65 b. In this specification, the doping concentration of the first region 65 a may be the average doping concentration of the trench bottom region 65 below the multiple trench portions. The doping concentrations of the first region 65 a and the second region 65 b may be the same.

[0097] 6A is a flowchart showing an example of a manufacturing process of the semiconductor device 100. This example shows an example of a flowchart of the manufacturing process of the semiconductor device 100, and is not limited to this. In step S100, a drift region 18 is formed in the semiconductor substrate 10. The step of forming the drift region 18 in the semiconductor substrate 10 can be formed by a common method used by those skilled in the art, and therefore will not be described in detail herein.

[0098] In step S110, a plurality of trenches are formed in the front surface 21 of the semiconductor substrate 10. This forms bottoms 61, sidewalls 62, and openings 63 of the trenches. The bottoms 61, sidewalls 62, and openings 63 will be described later.

[0099] In step S120, a mask 64 is formed on the front surface 21 of the semiconductor substrate 10. The mask 64 may be any mask such as a photoresist.

[0100] In step S130, the first accumulation region 16 and the second accumulation region 26 are formed by ion-implanting a dopant from the front surface 21 side of the semiconductor substrate 10. The implanted dopant may be phosphorus.

[0101] In step S130, dopants may be ion-implanted from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. The step of forming the first accumulation region 16 may include a step of implanting dopants into sidewalls 62 of the plurality of trench portions through openings 63 of the plurality of trench portions from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. The step of forming the second accumulation region 26 may include a step of implanting dopants into bottoms 61 of the plurality of trench portions through openings 63 of the plurality of trench portions from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. The predetermined inclination when implanting dopants is not particularly limited as long as it is an angle at which the dopants are irradiated onto both the bottoms 61 and the sidewalls 62 of the trench portions.

[0102] In step S140, a trench bottom region 65 is formed by ion-implanting a dopant from the front surface 21 side of the semiconductor substrate 10. The implanted dopant may be boron or aluminum.

[0103] In step S140, the step of forming the trench bottom region 65 may include the step of implanting dopants into the bottoms 61 of the plurality of trench portions through the openings 63 of the plurality of trench portions in the depth direction of the semiconductor substrate 10. In this way, the dopants can be implanted near the bottoms 61 of the trench portions, and the trench bottom region 65 can be formed.

[0104] The order of steps S130 and S140 may be reversed. That is, although the first accumulation region 16 and the second accumulation region 26 are formed first and then the trench bottom region 65 is formed in the example described above, the first accumulation region 16 and the second accumulation region 26 may be formed first.

[0105] In step S150, an emitter region 12, a contact region 15, and a base region 14 are formed in the semiconductor substrate 10. These regions can be formed by conventional methods used by those skilled in the art, and therefore will not be described in detail herein.

[0106] Fig. 6B is a diagram showing an example of a manufacturing process of the semiconductor device 100. Fig. 6B is a diagram showing a YZ cross section of the semiconductor substrate 10 at each step of Fig. 6A.

[0107] 6B, step S131 in which dopant ions are implanted from the diagonally upper right and step S132 in which dopant ions are implanted from the diagonally upper left. The acceleration voltage of the ion implantation in step S130 may be 0.1 MeV or more and 2.6 MeV or less.

[0108] In step S131, dopant ions may be implanted from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. In step S131, first ion implantation regions 116 are formed on one of the sidewalls 62 of the plurality of trench portions through the openings 63 of the plurality of trench portions. The first ion implantation regions 116 are regions that will become the first accumulation regions 16 by annealing.

[0109] In step S132, dopant ions may be implanted from a direction having a predetermined inclination with respect to the depth direction of the semiconductor substrate 10. In step S132, first ion implantation regions 116 are formed on the other side of the sidewalls 62 of the plurality of trench portions through the openings 63 of the plurality of trench portions.

[0110] In both steps S131 and S132, dopants may be ion-implanted into the bottoms 61 of the trenches through the openings 63 of the trenches from a direction tilted at a predetermined angle with respect to the depth direction of the semiconductor substrate 10. In steps S131 and S132, second ion-implanted regions 126 are formed below the bottoms 61 of the trenches. The second ion-implanted regions 126 are regions that will become the second accumulation regions 26 by annealing.

[0111] In step S130, the steps of forming the first ion implantation region 116 and the second ion implantation region 126 may be performed simultaneously or separately. In the embodiment shown in Figure 6B, they are formed simultaneously by ion implantation. That is, in Figure 6B, the first accumulation region 16 is formed by implanting dopants into the sidewalls 62 of the trench portions through the openings 63 of the trench portions, and the second accumulation region 26 is formed by implanting dopants into the bottoms 61 of the trench portions through the openings 63 of the trench portions.

[0112] In step S130, a dopant is implanted into the sidewalls 62 of the trench portions through the trench openings 63, thereby forming a doping concentration distribution including a flat profile. Also, by implanting the dopant into the bottoms 61 of the trench portions through the trench openings 63, a second ion implantation region 126 can be formed below the bottoms 61 of the trench portions and at a position deeper than the region where the trench bottom implantation region 165 is formed.

[0113] In step S140, dopants are implanted into the bottoms 61 of the trenches from the front surface 21 side of the semiconductor substrate 10 through the openings 63 of the trenches to form trench bottom implantation regions 165. The trench bottom implantation regions 165 are regions that will become the trench bottom regions 65 by annealing.

[0114] The annealing process for the first ion implantation region 116, the second ion implantation region 126, and the trench bottom implantation region 165 may be performed at any time. In one example, the annealing process is performed after step S140. The annealing process may be performed between steps S130 and S140.

[0115] In this example, in step S140, dopants are implanted above the second ion implantation region 126. This makes it possible to suppress thermal diffusion in the depth direction of the trench bottom implantation region 165 during the annealing process and to control the thickness of the trench bottom region 65 in the depth direction of the semiconductor substrate 10. That is, because the position of the lower end of the trench bottom region 65 is limited by the second accumulation region 26, the thickness of the trench bottom region 65 can be controlled to be thinner than in a case where the second accumulation region 26 is not provided.

[0116] Since the semiconductor device 100 of this example has the second accumulation region 26, the thickness of the trench bottom region 65 is thinner than that of the comparative example that does not have the second accumulation region 26. The effect of forming the trench bottom region 65 thin will be explained using Tables 1 and 2.

[0117] Table 1 shows whether or not turn-on oscillation occurred in the comparative example and each example. Examples 1 to 3 differ in the dopant implantation angle in step S130. Example 1 has the smallest implantation angle, Example 3 has the largest, and Example 2 has the intermediate implantation angle between the maximum and minimum.

[0118] As shown in Table 1, in the comparative example that did not have the second accumulation region 26 and had a thick trench bottom region 65, gate oscillation was observed for all relative values ​​of gate resistance of 10 or more. On the other hand, in Examples 1 to 3 in which the second accumulation region 26 was formed and the trench bottom region 65 was thinner than the comparative example, gate oscillation was not observed for all gate resistance values ​​tested.

[0119] Table 2 shows whether arm short-circuit oscillation occurred in the comparative example and each example. As shown in Table 2, in the comparative example which did not have the second accumulation region 26 and had a thick trench bottom region 65, arm short-circuit oscillation was observed at all power supply voltages for which experiments were performed. On the other hand, in examples 1 to 3 in which the second accumulation region 26 was formed and the trench bottom region 65 was thinner than the comparative example, when the power supply voltage was 500 V, only slight arm short-circuit oscillation was observed in example 3, and no arm short-circuit oscillation was observed in the other examples.

[0120] As shown in Tables 1 and 2, the semiconductor device 100 of this example can suppress gate oscillation and arm short-circuit oscillation by forming the second accumulation region 26 and thereby controlling the thickness of the trench bottom region 65 to be thinner than that of the comparative example. Furthermore, by forming the trench bottom region 65, the on-loss Eon can be reduced.

[0121] Fig. 7A is a flowchart showing a modified example of the manufacturing process of the semiconductor device 100. In the modified example of Fig. 7A, the order in which the regions are formed is different from the example shown in Fig. 6A. The following describes the differences from the example shown in Fig. 6A.

[0122] In step S210, the second accumulation region 26 is formed. As in the example shown in Fig. 6A, the first accumulation region 16 may be formed at the same time. The acceleration voltage for ion implantation when forming the second accumulation region 26 may be 8.0 MeV or more and 10.0 MeV or less.

[0123] In step S220, a trench bottom region 65 is formed. The trench bottom region 65 is formed closer to the front surface 21 of the semiconductor substrate 10 than the second accumulation region 26. The acceleration voltage used in the ion implantation to form the trench bottom region 65 may be lower than the acceleration voltage used in the ion implantation to form the second accumulation region 26. The acceleration voltage used in the ion implantation to form the trench bottom region 65 may be equal to or higher than 3.0 MeV and may be equal to or lower than 5.0 MeV.

[0124] In step S230, the first accumulation region 16 is formed. The first accumulation region 16 is formed closer to the front surface 21 of the semiconductor substrate 10 than the trench bottom region 65. The first accumulation region 16 may be formed by a single ion implantation, or may be formed by multiple ion implantations. By forming the first accumulation region 16 by multiple ion implantations, the doping concentration of the first accumulation region 16 can have a profile that includes a flat region.

[0125] In step S230, the acceleration voltage in the ion implantation when forming the first accumulation region 16 may be lower than the acceleration voltage in the ion implantation when forming the trench bottom region 65. The acceleration voltage in the ion implantation when forming the first accumulation region 16 may be 2.0 MeV or more and 4.0 MeV or less.

[0126] In step S240, a plurality of trench portions are formed in the front surface 21 of the semiconductor substrate 10. That is, in the modification shown in Fig. 7A, the steps of forming the second accumulation region 26, the trench bottom region 65, and the first accumulation region 16 are performed before the step of forming the plurality of trench portions. This makes the concentration distribution of the second accumulation region 26, the trench bottom region 65, and the first accumulation region 16 uniform in the trench arrangement direction, thereby reducing variation in the characteristics of the semiconductor device 100.

[0127] 7B is a diagram showing a modified example of the manufacturing process of the semiconductor device 100. FIG. 7B is a diagram showing a YZ cross section of the semiconductor substrate 10 at each step of FIG. 7A.

[0128] In step S210, dopant ions are implanted from the front surface 21 side of the semiconductor substrate 10 where the drift region 18 is formed, thereby forming a second ion implantation region 126. The second ion implantation region 126 is a region that will become the second accumulation region 26 by annealing treatment.

[0129] In step S220, a trench bottom implantation region 165 is formed by ion implanting dopant from the front surface 21 side of the semiconductor substrate 10. The trench bottom implantation region 165 is a region that will become the trench bottom region 65 by annealing. In step S220, the acceleration voltage during ion implantation is set lower than in step S210, so that the trench bottom implantation region 165 can be formed closer to the front surface 21 side of the semiconductor substrate 10 than the second ion implantation region 126.

[0130] In step S230, a first ion implantation region 116 is formed by ion implanting a dopant from the front surface 21 side of the semiconductor substrate 10. The first ion implantation region 116 is a region that will become the first accumulation region 16 by annealing. The dopant used to form the first ion implantation region 116 and the dopant used to form the second ion implantation region 126 may be the same or different. Figure 7B shows an example in which the first ion implantation region 116 is formed by a single ion implantation.

[0131] In step S240, a plurality of trench portions are formed in the front surface 21 of the semiconductor substrate 10. Each of the plurality of trench portions has a bottom 61, sidewalls 62, and an opening 63. The plurality of trench portions are formed such that the bottom 61 is located in the trench bottom implantation region 165.

[0132] 7A and 7B , the second ion implantation region 126, the trench bottom implantation region 165, and the first ion implantation region 116 are formed in this order, but the present invention is not limited to this. That is, steps S210, S220, and S230 may be performed in any order, and the second ion implantation region 126, the first ion implantation region 116, and the trench bottom implantation region 165 may be formed in this order. In the modified example shown in FIGS. 7A and 7B , there is no need to form a mask 64 on the front surface 21 of the semiconductor substrate 10, and therefore costs can be reduced compared to the example shown in FIGS. 6A and 6B .

[0133] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0134] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0135] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...First accumulation region, 17...Well region, 18...Drift region, 19...Anode region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 26...Second accumulation region, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extended portion, 42...Gate insulating film, 43...Connection portion, 44...Gate Gate conductive portion, 50...gate metal layer, 52...emitter electrode, 54...contact hole, 55...contact hole, 56...contact hole, 61...bottom, 62...side wall, 63...opening, 64...mask, 65...trench bottom region, 66...carrier passage region, 67...protruding portion, 70...transistor portion, 71...mesa portion, 80...diode portion, 81...mesa portion, 82...cathode region, 90...boundary portion, 91...mesa portion, 100...semiconductor device, 116...first ion implantation region, 126...second ion implantation region, 165...trench bottom implantation region

Claims

1. A semiconductor device including a transistor portion, A plurality of trench portions including a gate trench portion provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a first accumulation region of a first conductivity type provided below the base region and having a doping concentration higher than that of the drift region; a trench bottom region of a second conductivity type provided below the first accumulation region and having a doping concentration higher than that of the base region; a second accumulation region of the first conductivity type that is provided deeper than the trench bottom region in a depth direction of the semiconductor substrate and has a doping concentration higher than that of the drift region; Equipped with The transistor portion has a collector region of a second conductivity type on the back surface of the semiconductor substrate. Semiconductor device.

2. An upper end of the trench bottom region contacts a lower end of the first accumulation region. The semiconductor device according to claim 1 .

3. A lower end of the trench bottom region contacts an upper end of the second accumulation region. The semiconductor device according to claim 1 .

4. The trench bottom region is provided to extend from a lower end of one of the plurality of trench portions to a lower end of the other of the plurality of trench portions in a trench arrangement direction of the plurality of trench portions. The semiconductor device according to claim 1 .

5. A thickness of the trench bottom region in a depth direction of the semiconductor substrate is 20% or more and 100% or less of a trench depth of the plurality of trench portions. The semiconductor device according to claim 1 .

6. The thickness of the trench bottom region in the depth direction of the semiconductor substrate is 1 μm or more and 5 μm or less. The semiconductor device according to claim 1 .

7. The trench bottom region is a first region provided below the plurality of trench portions; a second region provided below a mesa portion sandwiched between the plurality of trench portions; Including, The doping concentration of the first region is higher than the doping concentration of the second region. The semiconductor device according to claim 1 .

8. The trench bottom region is a first region provided below the plurality of trench portions; a second region provided below a mesa portion sandwiched between the plurality of trench portions; Including, The doping concentration of the first region is the same as the doping concentration of the second region. The semiconductor device according to claim 1 .

9. a first conductivity type carrier passage region below the first accumulation region, in which the trench bottom region is not provided; The semiconductor device according to claim 1 .

10. The second accumulation region has a protruding portion that protrudes from below the trench bottom region beyond an end of the trench bottom region to the outside of the trench bottom region in the trench arrangement direction of the plurality of trench portions. The semiconductor device according to claim 1 .

11. The doping concentration in the first accumulation region has a profile in which a region having a doping concentration of 50% or more of a maximum value of the doping concentration in the first accumulation region occupies 60% or more and 100% or less of a thickness of the first accumulation region in a depth direction of the semiconductor substrate. The semiconductor device according to claim 1 .

12. The doping concentration in the first accumulation region has one or more doping concentration peaks in a depth direction of the semiconductor substrate. The semiconductor device according to claim 1 .

13. The thickness of the region having a doping concentration of 50% or more of the maximum doping concentration in the first accumulation region in the depth direction of the semiconductor substrate is 1 μm or more and 4 μm or less. The semiconductor device according to claim 11.

14. The doping concentration in the first accumulation region is different from the doping concentration in the second accumulation region. The semiconductor device according to claim 1 .

15. A diode portion having a cathode region of a first conductivity type on the back surface of the semiconductor substrate, In the diode portion, lower ends of the plurality of trench portions are in contact with a first conductivity type region. The semiconductor device according to claim 1 .

16. A method for manufacturing a semiconductor device having a transistor portion, comprising: forming a plurality of trench portions in a front surface of a semiconductor substrate; forming a base region of a second conductivity type disposed above a drift region of a first conductivity type; forming an emitter region of a first conductivity type above the base region, the emitter region having a doping concentration higher than that of the drift region; forming a first accumulation region of a first conductivity type having a higher doping concentration than the drift region by ion-implanting dopants from a front surface side of the semiconductor substrate; forming a trench bottom region of a second conductivity type having a higher doping concentration than the base region below the first accumulation region by ion-implanting a dopant from a front surface side of the semiconductor substrate; forming a second accumulation region of a first conductivity type having a doping concentration higher than that of the drift region at a position deeper than the trench bottom region in a depth direction of the semiconductor substrate by ion-implanting a dopant from a front surface side of the semiconductor substrate; Equipped with The transistor portion has a collector region of a second conductivity type on the back surface of the semiconductor substrate. A method for manufacturing a semiconductor device.

17. forming the first accumulation region includes implanting a dopant into sidewalls of the trench portions through openings of the trench portions from a direction having a predetermined inclination with respect to a depth direction of the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 16.

18. forming the trench bottom region includes implanting a dopant into bottoms of the trench portions through openings of the trench portions in a depth direction of the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 16.

19. forming the second accumulation region includes injecting a dopant into bottoms of the trench portions through openings of the trench portions from a direction having a predetermined inclination with respect to a depth direction of the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 16.

20. forming the first accumulation region and implanting the second accumulation region; The ion implantation step includes the steps of forming the first accumulation region by implanting dopants into sidewalls of the plurality of trench portions through openings of the plurality of trench portions, and forming the second accumulation region by implanting dopants into bottoms of the plurality of trench portions through openings of the plurality of trench portions. The method for manufacturing a semiconductor device according to any one of claims 16 to 19.

21. forming the second accumulation region, forming the trench bottom region, and forming the first accumulation region are performed prior to forming the plurality of trench portions. The method for manufacturing a semiconductor device according to claim 16.

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