Semiconductor device and production method for same

Abstract

A semiconductor device according to the present invention includes an oxide insulation layer, an oxide semiconductor layer that is above the oxide insulation layer, a gate insulation layer that is above the oxide semiconductor layer, and a gate electrode that is above the gate insulation layer. In a first region in which the oxide insulation layer, the oxide semiconductor layer, the gate insulation layer, and the gate electrode are layered in the given order, the gate electrode includes impurities. In a second region in which the gate electrode is not present and the oxide insulation layer, the oxide semiconductor layer, and the gate insulation layer are layered in the given order, the oxide insulation layer, the oxide semiconductor layer, and the gate insulation layer include impurities. In a third region in which the gate electrode and the oxide semiconductor layer are not present and the oxide insulation layer and the gate insulation layer are layered in the given order, the oxide insulation layer and the gate insulation layer include impurities. A concentration profile for the impurities includes a first peak and a second peak in the layering direction of the second region.

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a semiconductor device that uses an oxide semiconductor as a channel and a method for manufacturing the same. [Background technology]

[0002] In recent years, development of semiconductor devices using oxide semiconductor films as channels instead of silicon semiconductor films using amorphous silicon, low-temperature polysilicon, single-crystal silicon, etc. has been progressing (see, for example, Patent Documents 1 to 6). Semiconductor devices including such oxide semiconductor films can be manufactured using a simple structure and a low-temperature process, similar to thin-film transistors including amorphous silicon films. Furthermore, semiconductor devices including oxide semiconductor films are known to have higher field-effect mobility than semiconductor devices including amorphous silicon films. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141338 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-099601 [Patent Document 3] Japanese Patent Publication No. 2021-153196 [Patent Document 4] Japanese Patent Application Publication No. 2018-006730 [Patent Document 5] Japanese Patent Application Laid-Open No. 2016-184771 [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] In an oxide semiconductor, carriers are generated when hydrogen bonds to oxygen defects. By utilizing this mechanism, oxygen defects can be formed in an oxide semiconductor layer in a semiconductor device, and hydrogen can be supplied to the formed oxygen defects to form low-resistance source and drain regions. On the other hand, diffusion of hydrogen into the channel region of the oxide semiconductor layer reduces its function as a channel of the semiconductor device. Specifically, the diffusion of hydrogen into the channel region changes the threshold voltage in the electrical characteristics of the semiconductor device, increasing the variation in threshold voltage and reducing the manufacturing yield of the semiconductor device. Therefore, by using an oxide layer containing excess oxygen capable of trapping hydrogen as an insulating layer in contact with the oxide semiconductor layer, the penetration of hydrogen into the channel region is suppressed.

[0005] However, an oxide layer containing excess oxygen functions as an electron trap, which significantly reduces the reliability of a semiconductor device including such an oxide layer. Therefore, there is a need for a semiconductor device that can suppress the reduction in reliability, supply hydrogen to the source and drain regions of the oxide semiconductor layer, and prevent hydrogen from entering the channel region of the oxide semiconductor layer.

[0006] In view of the above-mentioned problems, one object of one embodiment of the present invention is to provide a semiconductor device including a hydrogen trapping region that prevents hydrogen from entering a channel region. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode on the gate insulating layer, wherein in a first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order, the gate electrode contains impurities but does not contain the gate electrode; in a second region where the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in this order, the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer contain impurities but do not contain the gate electrode or the oxide semiconductor layer; and in a third region where the oxide insulating layer and the gate insulating layer are stacked in this order, the oxide insulating layer and the gate insulating layer contain impurities, and a concentration profile of the impurities in the stacking direction in the second region includes a first peak and a second peak.

[0008] A semiconductor device according to one embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode on the gate insulating layer, wherein in a first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order, the gate electrode contains impurities but does not contain the gate electrode; in a second region where the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in this order, the oxide semiconductor layer and the gate insulating layer contain impurities but do not contain the gate electrode or the oxide semiconductor layer; and in a third region where the oxide insulating layer and the gate insulating layer are stacked in this order, the oxide insulating layer and the gate insulating layer contain impurities, and a concentration profile of the impurities in the stacking direction in the third region includes a first peak and a second peak.

[0009] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming an oxide insulating layer, forming a mask layer having a first pattern on the oxide insulating layer, injecting a first impurity into the oxide insulating layer using the mask layer as a mask, forming an oxide semiconductor layer having a second pattern on the oxide insulating layer, covering the oxide semiconductor layer, forming a gate insulating layer on the oxide insulating layer and the oxide semiconductor layer, forming a gate electrode having a third pattern on the gate insulating layer, and injecting a second impurity into the oxide semiconductor layer using the gate electrode as a mask.

[0010] A method for manufacturing a semiconductor device according to one embodiment of the present invention includes forming an oxide insulating layer, forming an oxide semiconductor layer having a first pattern on the oxide insulating layer, injecting a first impurity into the oxide insulating layer using a resist having the first pattern on which the oxide semiconductor layer is formed as a mask, covering the oxide semiconductor layer, forming a gate insulating layer on the oxide insulating layer and the oxide semiconductor layer, forming a gate electrode having a second pattern on the gate insulating layer, and injecting a second impurity into the oxide semiconductor layer using the gate electrode as a mask. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention; [Figure 4] 3 is a graph showing profiles of impurity concentrations in first to third regions in a semiconductor device according to one embodiment of the present invention. [Figure 5] 3 is a graph showing profiles of impurity concentrations in first to third regions in a semiconductor device according to one embodiment of the present invention. [Figure 6] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12]1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] 3 is a schematic cross-sectional view illustrating hydrogen trapping regions in a second region and a third region in a semiconductor device according to one embodiment of the present invention. FIG. [Figure 20] 3 is a schematic cross-sectional view illustrating hydrogen trapping regions in a second region and a third region in a semiconductor device according to one embodiment of the present invention. FIG. [Figure 21] 1 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention; [Figure 22] 3 is a graph showing profiles of impurity concentrations in first to third regions in a semiconductor device according to one embodiment of the present invention. [Figure 23] 3 is a graph showing profiles of impurity concentrations in first to third regions in a semiconductor device according to one embodiment of the present invention. [Figure 24] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 25] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0013] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the description. However, for example, the hierarchical relationship between the substrate and the oxide semiconductor layer may be reversed from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the hierarchical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0014] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0015] In this specification, the term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, in the embodiments described below, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer will be used as examples of display devices, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0016] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0017] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0018] First Embodiment 1 to 20, a semiconductor device 10 according to one embodiment of the present invention will be described. The semiconductor device 10 according to the embodiment described below may be used in an integrated circuit (IC) such as a microprocessor (micro-processing unit: MPU) or a memory circuit, in addition to a transistor used in a display device.

[0019] 1. Configuration of Semiconductor Device 10 The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. Figure 2 is a plan view showing an overview of the semiconductor device 10 according to one embodiment of the present invention. Specifically, Figure 1 is a cross-sectional view taken along line A-A' in Figure 2.

[0020] 1, a semiconductor device 10 is provided above a substrate 100. The semiconductor device 10 includes a light-shielding layer 105, a nitride insulating layer 110, an oxide insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrode 200.

[0021] The light-shielding layer 105 is provided on the substrate 100. The nitride insulating layer 110 and the oxide insulating layer 120 are provided on the substrate 100 and the light-shielding layer 105. The nitride insulating layer 110 covers the upper surface and edges of the light-shielding layer 105. The oxide semiconductor layer 140 is provided on the oxide insulating layer 120. The oxide semiconductor layer 140 is patterned. A portion of the oxide insulating layer 120 extends beyond the edges of the oxide semiconductor layer 140 and outside the pattern of the oxide semiconductor layer 140.

[0022] In this embodiment, a configuration in which the oxide insulating layer 120 and the oxide semiconductor layer 140 are in contact with each other is illustrated; however, the present invention is not limited to this configuration. For example, a metal oxide layer may be provided between the oxide insulating layer 120 and the oxide semiconductor layer 140. For example, a metal oxide containing aluminum as a main component may be used as the metal oxide layer. Specifically, aluminum oxide may be used as the metal oxide layer.

[0023] The gate insulating layer 150 covers an upper surface 141 and a side surface 143 of the oxide semiconductor layer 140 and is provided on the oxide semiconductor layer 140. That is, the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140 are in contact with the gate insulating layer 150, and the lower surface 142 of the oxide semiconductor layer 140 is in contact with the oxide insulating layer 120. The gate electrode 160 is provided on the gate insulating layer 150 so as to face the oxide semiconductor layer 140.

[0024] The insulating layer 170 is provided on the gate insulating layer 150 and the gate electrode 160. The insulating layer 170 covers the gate electrode 160. The insulating layer 180 is provided on the insulating layer 170. Openings 171 and 173 that reach the oxide semiconductor layer 140 are provided in the insulating layers 170 and 180. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0025] The light-shielding layer 105 has a function of blocking light incident on the oxide semiconductor layer 140 from the substrate 100 side. The nitride insulating layer 110 has a function as a barrier film that blocks impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The light-shielding layer 105 may also have a function as a bottom gate of the semiconductor device 10. In this case, the nitride insulating layer 110 and the oxide insulating layer 120 have a function as gate insulating layers for the bottom gate.

[0026] The operation of the semiconductor device 10 is controlled mainly by the voltage supplied to the gate electrode 160. When the light-shielding layer 105 functions as a bottom gate, an auxiliary voltage is supplied to the light-shielding layer 105. However, the same voltage as that of the gate electrode 160 may be supplied to the light-shielding layer 105. On the other hand, when the light-shielding layer 105 is used simply as a light-shielding film, no specific voltage may be supplied to the light-shielding layer 105, and the potential of the light-shielding layer 105 may be floating. Alternatively, the light-shielding layer 105 may be an insulator.

[0027] The semiconductor device 10 is divided into a first region A1, a second region A2, and a third region A3 based on the patterns of the gate electrode 160 and the oxide semiconductor layer 140. The first region A1 is a region overlapping with the gate electrode 160 in a planar view. In the first region A1, the oxide insulating layer 120, the oxide semiconductor layer 140, the gate insulating layer 150, and the gate electrode 160 are stacked in this order. The second region A2 is a region overlapping with the oxide semiconductor layer 140 but not with the gate electrode 160 in a planar view. In the second region A2, the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150 are stacked in this order. The third region A3 is a region overlapping with neither the gate electrode 160 nor the oxide semiconductor layer 140 in a planar view. In the third region A3, the oxide insulating layer 120 and the gate insulating layer 150 are stacked in this order.

[0028] The thickness of the gate insulating layer 150 is, for example, 100 nm or more, and may be 250 nm or more, or 300 nm or more.

[0029] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the pattern of the gate electrode 160. The source region S and the drain region D belong to the second region A2. The channel region CH belongs to the first region A1. In a plan view, an edge of the channel region CH coincides with an edge of the gate electrode 160. The oxide semiconductor layer 140 in the channel region CH has semiconductor properties. The oxide semiconductor layer 140 in each of the source region S and the drain region D has conductive properties. That is, the carrier concentration of the oxide semiconductor layer 140 in the source region S and the drain region D is higher than the carrier concentration of the oxide semiconductor layer 140 in the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a multilayer structure.

[0030] In this embodiment, a configuration in which a top-gate transistor in which the gate electrode 160 is provided above the oxide semiconductor layer 140 is used as the semiconductor device 10 is exemplified, but the present invention is not limited to this configuration. For example, as described above, the semiconductor device 10 may be a dual-gate transistor in which the light-shielding layer 105 functions as a gate in addition to the gate electrode 160. Alternatively, the semiconductor device 10 may be a bottom-gate transistor in which the light-shielding layer 105 mainly functions as a gate. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0031] 2, the width of the light-shielding layer 105 is greater than the width of the gate electrode 160. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of a region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W. The light-shielding layer 105 and the gate electrode 160 extend in the D2 direction.

[0032] 2 illustrates a configuration in which the source-drain electrode 200 does not overlap the light-shielding layer 105 and the gate electrode 160 in a plan view, but the present invention is not limited to this configuration. For example, the source-drain electrode 200 may overlap at least one of the light-shielding layer 105 and the gate electrode 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0033] 2. Materials of Components of Semiconductor Device 10 The substrate 100 may be a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate. When the substrate 100 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, may be used. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top-emission display, the substrate 100 does not need to be transparent, and therefore impurities that deteriorate the transparency of the substrate 100 may be used. When the semiconductor device 10 is used in an integrated circuit other than a display device, a non-optically transparent substrate, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, may be used as the substrate 100.

[0034] Common metal materials are used for the light-shielding layer 105, gate electrode 160, and source / drain electrodes 200. Examples of materials that can be used for these components include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The above materials may be used as the light-shielding layer 105, gate electrode 160, and source / drain electrodes 200 in a single layer or a multilayer configuration. If electrical conductivity is not required for the light-shielding layer 105, materials other than the above metal materials may be used. For example, a black matrix such as a black resin may be used as the light-shielding layer 105. The light-shielding layer 105 may have a single-layer structure or a multilayer structure. For example, the light-shielding layer 105 may have a multilayer structure of red, green, and blue color filters.

[0035] A general insulating material is used for the nitride insulating layer 110, the oxide insulating layer 120, and the insulating layers 170 and 180. For example, silicon oxide (SiO x), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y The nitride insulating layer 110 and the insulating layer 170 may be made of silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), aluminum oxide nitride (AlN x O y However, the insulating layer 170 may be made of an inorganic insulating layer such as silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y ) may be used as the insulating layer 180. x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), or aluminum oxide nitride (AlN x O y ) or other inorganic insulating layers may also be used.

[0036] The gate insulating layer 150 is an insulating layer containing oxygen among the above insulating layers. For example, the gate insulating layer 150 is made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y ) or other inorganic insulating layers are used.

[0037] An insulating layer having a function of releasing oxygen by heat treatment is used as the oxide insulating layer 120. That is, an oxide insulating layer containing excess oxygen is used as the oxide insulating layer 120. The temperature of heat treatment at which the oxide insulating layer 120 releases oxygen is, for example, 600°C or lower, 500°C or lower, 450°C or lower, or 400°C or lower. That is, the oxide insulating layer 120 releases oxygen at a heat treatment temperature that is used in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 100. At least one of the insulating layers 170 and 180 may be an insulating layer having a function of releasing oxygen by heat treatment, similar to the oxide insulating layer 120.

[0038] An insulating layer with few defects is used as the gate insulating layer 150. For example, when the oxygen composition ratio in the gate insulating layer 150 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, the gate insulating layer 150 and the insulating layer 180 each contain silicon oxide (SiO x ), the oxygen composition ratio in the silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 180. For example, the gate insulating layer 150 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0039] The above SiO x N y and AlO x N y is a silicon and aluminum compound containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0040] The oxide semiconductor layer 140 can be made of a metal oxide having semiconductor properties. 。

[0041] The oxide semiconductor layer 140 can be formed by sputtering, although the detailed manufacturing method of the oxide semiconductor layer 140 will be described later. The composition of the oxide semiconductor layer 140 formed by sputtering depends on the composition of the sputtering target. .child In this case, the composition of the metal elements in the oxide semiconductor layer 140 can be determined based on the composition of the metal elements in the sputtering target.

[0042] When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer may be determined by X-ray diffraction (XRD). Specifically, the composition of the metal elements in the oxide semiconductor layer can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by XRD. Furthermore, the composition of the metal elements in the oxide semiconductor layer 140 can also be determined by X-ray fluorescence analysis or electron probe microanalyzer (EPMA) analysis. However, this is not limited to this because the oxygen contained in the oxide semiconductor layer 140 varies depending on the sputtering process conditions, etc.

[0043] As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. 。

[0044] As described above, when a metal oxide layer is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, a metal oxide containing aluminum as a main component is used as the metal oxide layer. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), or aluminum nitride (AlN x) is used. "A metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0045] [3. Hydrogen trapping area configuration] The hydrogen trapping region is formed in the oxide insulating layer 120 and the gate insulating layer 150. The configuration of the hydrogen trapping region formed in the oxide insulating layer 120 and the gate insulating layer 150 will now be described with reference to FIGS.

[0046] Fig. 3 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. Specifically, Fig. 3 is an enlarged cross-sectional view of region P in Fig. 1. Region P shown in Fig. 3 is a region near drain region D, but the region near source region S also has a similar configuration to region P.

[0047] As will be described in detail later, the source region S and the drain region D of the oxide semiconductor layer 140 are formed by ion implantation of impurities using the gate electrode 160 as a mask. Examples of impurities that can be used include boron (B), phosphorus (P), argon (Ar), and nitrogen (N). The ion implantation of impurities generates oxygen defects in the source region S and the drain region D. Hydrogen bonds with the generated oxygen defects, thereby reducing the resistance of the source region S and the drain region D. Silicon nitride contains more hydrogen than silicon oxide, so for example, by using silicon nitride as the insulating layer 170, hydrogen is diffused from the insulating layer 170, thereby reducing the resistance of the source region S and the drain region D.

[0048] The impurity ions are implanted using the gate electrode 160 as a mask, but the impurity ions are implanted into the oxide semiconductor layer 140 via the gate insulating layer 150. Therefore, the impurity is also introduced into the gate insulating layer 150 in the second region A2 and the third region A3, thereby forming dangling bond defects DB in the gate insulating layer 150. Furthermore, in the second region A2 and the third region A3, the impurity may pass through the oxide semiconductor layer 140 and the gate insulating layer 150 and be introduced into the oxide insulating layer 120. Note that in this embodiment, in order to form dangling bond defects DB in the oxide insulating layer 120 in the second region A2 and the third region A3, the impurity ions are implanted into the oxide insulating layer 120 separately from the above-described impurity ion implantation.

[0049] 3, in the second region A2 and the third region A3, dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150. When silicon oxide is used for each of the oxide insulating layer 120 and the gate insulating layer 150, silicon dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150.

[0050] Dangling bond defects DB formed in the oxide insulating layer 120 and the gate insulating layer 150 trap hydrogen. That is, hydrogen trapping regions are formed in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3. Therefore, for example, hydrogen diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped in the hydrogen trapping regions of the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3, thereby preventing hydrogen from entering the channel region CH. Note that, because hydrogen is trapped in the hydrogen trapping regions, after the insulating layer 170 is formed, the hydrogen concentration of the gate insulating layer 150 in the second region A2 and the third region A3 is higher than the hydrogen concentration of the gate insulating layer 150 in the first region A1. Similarly, the hydrogen concentration of the oxide insulating layer 120 in the second region A2 and the third region A3 is higher than the hydrogen concentration of the oxide insulating layer 120 in the first region A1.

[0051] As described above, the dangling bond defects DB in the hydrogen trapping region are formed by ion implantation, and therefore the oxide insulating layer 120 and the gate insulating layer 150 contain impurities introduced by ion implantation. The distribution of the amount of dangling bond defects DB formed in the oxide insulating layer 120 and the gate insulating layer 150 corresponds to the concentration profile of the impurities contained therein. In other words, the positions and amounts of the dangling bond defects DB can be adjusted by adjusting the concentration profile of the impurities introduced by ion implantation.

[0052] To prevent abnormalities in the electrical characteristics of the semiconductor device 10 from occurring due to hydrogen penetration into the channel region CH, it is effective to form dangling bond defects DB in the oxide insulating layer 120 in the second region A2 and the third region A3. Therefore, in this embodiment, impurity ions are implanted into the oxide insulating layer 120 without passing through the gate insulating layer 150. This allows hydrogen trapping regions to be formed in the oxide insulating layer 120 in the second region A2 and the third region A3, regardless of the thickness of the gate insulating layer 150. Furthermore, increasing the thickness of the gate insulating layer 150 can improve the high-voltage resistance of the gate insulating layer 150. For example, the thickness of the gate insulating layer 150 is 200 nm or more.

[0053] 4 and 5 are graphs showing the concentration profiles of impurities in the first region A1 to the third region A3 in a semiconductor device according to one embodiment of the present invention. The vertical axis of each of the three concentration profiles shown in each of FIGS. 4 and 5 represents the concentration of impurities per unit volume (Concentration [ / cm 3 ]), and the horizontal axis indicates the names of layers in the stacking direction (thickness direction). "UC" on the horizontal axis corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the gate insulating layer 150. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170.

[0054] As shown in FIG. 4, in the first region A1, the concentration profile of the impurity has a peak in the gate electrode 160 (GL). That is, the first region A1 includes one peak. Metallic materials have a high blocking power for impurities introduced by ion implantation. When a metallic material is used for the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the gate insulating layer 150 (GI). Therefore, dangling bond defects DB caused by the introduction of impurities are not formed in the gate insulating layer 150 in the first region A1. However, the impurities may reach the gate insulating layer 150 as long as they do not affect the electrical characteristics of the semiconductor device 10.

[0055] In the second region A2, the impurity concentration profile has peaks in the oxide insulating layer 120 (UC) and the oxide semiconductor layer 140 (OS). That is, the second region A2 includes two peaks. In the stacking direction in the second region A2, the impurity concentrations at the peak positions of the oxide insulating layer 120 and the oxide semiconductor layer 140 are higher than the impurity concentrations contained in the gate insulating layer 150. Because the purpose of doping the impurity in the second region A2 is to form the source region S and the drain region D, it is preferable, but not limited to, to set the ion implantation conditions so as to obtain the above-described concentration profile. The impurity concentration profile in the second region A2 may have peaks in the oxide insulating layer 120 (UC) and the gate insulating layer 150 (GI) (see FIG. 5 ). In this case, in the stacking direction in the second region A2, the impurity concentrations at the peak positions of the oxide insulating layer 120 and the gate insulating layer 150 may be higher than the impurity concentrations contained in the oxide semiconductor layer 140.

[0056] In the third region A3, the impurity concentration profile has a peak in the oxide insulating layer 120 (UC). That is, the third region A3 includes one peak. In the stacking direction in the third region A3, the impurity concentration at the peak position of the oxide insulating layer 120 may be higher than the impurity concentration contained in the gate insulating layer 150. The impurity concentration profile of the gate insulating layer 150 in the third region A3 is substantially the same as the impurity concentration profile of the gate insulating layer 150 in the second region A2. Therefore, the impurity concentration profile in the third region A3 shown in FIG. 5 may have peaks in the oxide insulating layer 120 (UC) and the gate insulating layer 150 (GI). In this case, the third region A3 includes two peaks.

[0057] As will be described in detail later, in this embodiment, at least two impurity ion implantations are performed. In the first impurity ion implantation, the impurity is introduced into the oxide insulating layer 120 in the second region A2 and the third region A3. On the other hand, in the second impurity ion implantation, the impurity is introduced into the oxide insulating layer 120 in the second region A2 and the third region A3 via the gate insulating layer 150. Therefore, in the oxide insulating layer 120 in the first region A1, the second region A2, and the third region A3, the impurity concentration may increase in the order of the first region A1, the second region, and the third region.

[0058] In this embodiment, the concentration of impurities contained at a predetermined position in the oxide insulating layer 120 in the stacking direction in the third region A3 is 1×10 16 / cm 3 That's it, 1×10 17 / cm 3 or more, or 1 x 10 18 / cm 3 That is all. The predetermined position may be the peak position of the concentration profile, or may be a position corresponding to the interface between the oxide insulating layer 120 and the gate insulating layer 150. Alternatively, the predetermined position may be a position shifted a predetermined depth in the direction of the oxide insulating layer 120 from the position corresponding to the interface.

[0059] 2, the channel region CH belongs to the first region A1, the source region S and the drain region D belong to the second region A2, and the regions other than the channel region CH, the source region S, and the drain region D belong to the third region A3. That is, the channel region CH is sandwiched between the second regions A2 and surrounded by the third region A3. Therefore, for example, hydrogen diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by the hydrogen trapping regions formed in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3 located around the channel region CH. As a result, the hydrogen can be prevented from penetrating into the channel region CH.

[0060] 4. Method for Manufacturing Semiconductor Device 10 A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 6 to 15. Figure 6 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 7 to 15 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0061] As shown in FIGS. 6 and 7, a light-shielding layer 105 is formed on a substrate 100, and a nitride insulating layer 110 and an oxide insulating layer 120 are formed on the light-shielding layer 105 (step S1010, "Insulating layer / light-shielding layer formation" in FIG. 6). The nitride insulating layer 110 is formed, for example, from silicon nitride. The oxide insulating layer 120 is formed, for example, from silicon oxide. The nitride insulating layer 110 and the oxide insulating layer 120 are formed by a chemical vapor deposition (CVD) method. For example, the thickness of the nitride insulating layer 110 is 50 nm to 500 nm, or 150 nm to 300 nm. The thickness of the oxide insulating layer 120 is 50 nm to 500 nm, or 150 nm to 300 nm.

[0062] When silicon nitride is used for the nitride insulating layer 110, the nitride insulating layer 110 can block impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. For example, silicon oxide used for the oxide insulating layer 120 is silicon oxide that has the physical property of releasing oxygen by heat treatment.

[0063] 6 and 8, an oxide semiconductor layer 140 is formed on the oxide insulating layer 120 ("OS film formation" in step S1020 in FIG. 6). The oxide semiconductor layer 140 is formed by sputtering or atomic layer deposition (ALD).

[0064] When a metal oxide layer containing aluminum as its main component is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, the metal oxide layer is also formed by sputtering or atomic layer deposition in the same manner as described above.

[0065] The oxide semiconductor layer 140 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, the oxide semiconductor layer 140 has a thickness of 30 nm. The oxide semiconductor layer 140 is amorphous before heat treatment (OS annealing) described later.

[0066] example For example, when the oxide semiconductor layer 140 is formed by sputtering, the oxide semiconductor layer 140 is formed while controlling the temperature of the object on which the film is to be formed (the substrate 100 and the structure formed thereon).

[0067] When a film is formed on an object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the object, causing the temperature of the object to rise during the film formation process. . aboveIn order to control the temperature of the object to be film-formed as described above, for example, the film can be formed while cooling the object to be film-formed. For example, the object to be film-formed can be cooled from the surface opposite to the surface to be film-formed so that the temperature of the surface to be film-formed of the object to be film-formed (hereinafter referred to as "film formation temperature") becomes 100°C or less, 70°C or less, 50°C or less, or 30°C or less. .acid The partial pressure of oxygen in the film formation conditions for the compound semiconductor layer 140 is 2% or more and 20% or less, 3% or more and 15% or less, or 3% or more and 10% or less.

[0068] As shown in FIGS. 6 and 9, a pattern of the oxide semiconductor layer 140 is formed ("OS pattern formation" in step S1030 in FIG. 6). Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. Wet etching or dry etching may be used to etch the oxide semiconductor layer 140. Wet etching can be performed using an acidic etchant. Examples of etchants that can be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, and hydrofluoric acid. 。

[0069] After the oxide semiconductor layer 140 is patterned, the oxide semiconductor layer 140 is subjected to heat treatment (OS annealing) ("OS annealing" in step S1040 of FIG. 6). In the OS annealing, the oxide semiconductor layer 140 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300°C or higher and 500°C or lower, or 350°C or higher and 450°C or lower. The holding time at the target temperature is 15 minutes or higher and 120 minutes or lower, or 30 minutes or higher and 60 minutes or lower. In this embodiment, the oxide semiconductor layer 140 is crystallized by this OS annealing. However, the oxide semiconductor layer 140 does not necessarily have to be crystallized by the OS annealing.

[0070] As shown in FIGS. 6 and 10 , a mask layer 300 having a predetermined pattern is formed on the oxide semiconductor layer 140 ("Formation of mask layer" in step S1050 of FIG. 6 ). The mask layer 300 may be formed using a resist or a metal. The mask layer 300 is patterned through a photolithography process. The predetermined pattern of the mask layer 300 may substantially match the pattern of the gate electrode 160, or may be different. When the predetermined pattern of the mask layer 300 is different from the pattern of the gate electrode 160, the mask layer 300 is formed so that the width of the mask layer 300 substantially matches the width of the gate electrode 160 in a cross-sectional view.

[0071] As shown in FIGS. 6 and 11, impurity ions are implanted into the oxide insulating layer 120 using the mask layer 300 as a mask ("first ion implantation" in step S1060 in FIG. 6). Examples of impurities used include boron (B), phosphorus (P), argon (Ar), and nitrogen (N). This allows the impurity, such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N), to be introduced into the oxide insulating layer 120. The impurity introduced into the oxide insulating layer 120 forms dangling bond defects DB. The region of the oxide insulating layer 120 where the dangling bond defects DB are formed can function as a hydrogen trap region.

[0072] In the first ion implantation in step S1060, it is important to form dangling bond defects DB in the oxide insulating layer 120 while not forming dangling bond defects DB in the nitride insulating layer 110. Therefore, in the first ion implantation, impurity ions are implanted so as to have a concentration profile with a peak in the oxide insulating layer 120. The position of the peak and the amount of impurity can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, the dose is 1×10 14 / cm 2 That's it, 5 x 10 14 / cm 2 , or 1×10 15 / cm 2For example, the acceleration voltage is greater than 10 keV, 15 keV or more, or 20 keV or more.

[0073] In step S1060, impurities are also introduced into the oxide semiconductor layer 140. Therefore, oxygen defects are formed in the oxide semiconductor layer 140, and the source region S and the drain region D are formed. However, in step S1060, it is not necessary that sufficient oxygen defects are formed in the oxide semiconductor layer 140.

[0074] As shown in FIGS. 6 and 12, a gate insulating layer 150 is formed ("GI formation" in step S1070 of FIG. 6). The gate insulating layer 150 is formed, for example, of silicon oxide. The gate insulating layer 150 is formed by a CVD method. For example, in order to form an insulating layer with few defects as the gate insulating layer 150 as described above, the gate insulating layer 150 may be formed at a film formation temperature of 350°C or higher. The thickness of the gate insulating layer 150 is, for example, 100 nm to 500 nm, 200 nm to 400 nm, or 250 nm to 350 nm. After the gate insulating layer 150 is formed, a process of implanting oxygen into the upper part of the gate insulating layer 150 may be performed. As the oxygen implantation process, a configuration in which a metal oxide layer is formed on the gate insulating layer 150 by a sputtering method may be performed.

[0075] With the gate insulating layer 150 formed on the oxide semiconductor layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 ("oxidation annealing" in step S1080 of FIG. 6). During the process from when the oxide semiconductor layer 140 is formed until when the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen vacancies are generated on the top surface 141 and side surface 143 of the oxide semiconductor layer 140. By the above-mentioned oxidation annealing, oxygen released from the oxide insulating layer 120 and the gate insulating layer 150 is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired. If a process of implanting oxygen into the gate insulating layer 150 is not performed, the oxidation annealing may be performed with an insulating layer that releases oxygen by heat treatment formed on the gate insulating layer 150.

[0076] In order to increase the amount of oxygen supplied from the gate insulating layer 150 to the oxide semiconductor layer 140, a metal oxide layer containing aluminum as a main component may be formed on the gate insulating layer 150 by sputtering, and oxidation annealing may be performed in this state. By using aluminum oxide, which has high gas barrier properties, as this metal oxide layer, it is possible to prevent outward diffusion of oxygen implanted into the gate insulating layer 150 during oxidation annealing. By forming the metal oxide layer and performing oxidation annealing as described above, the oxygen implanted into the gate insulating layer 150 is efficiently supplied to the oxide semiconductor layer 140.

[0077] 6 and 13, the gate electrode 160 is formed and patterned ("GE formation" in step S1090 of FIG. 6). The gate electrode 160 is formed by sputtering or atomic layer deposition. The gate electrode 160 is patterned through a photolithography process.

[0078] 6 and 14, impurity ions are implanted into the oxide semiconductor layer 140 using the gate electrode 160 as a mask ("second ion implantation" in step S1100 in FIG. 6). As the impurity, for example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is used. The impurity in the second ion implantation in step S1090 may be the same as or different from the impurity in the first ion implantation in step S1060. As a result, boron (B), phosphorus (P), argon (Ar), nitrogen (N), or the like is introduced into the oxide semiconductor layer 140.

[0079] In the second ion implantation in step S1100, the gate electrode 160 is used as a mask. Therefore, impurities are introduced into regions of the oxide semiconductor layer 140 that do not overlap with the gate electrode 160, and oxygen defects are formed. Hydrogen is bonded to the generated oxygen defects, thereby reducing the resistance of the oxide semiconductor layer 140. That is, a source region S and a drain region D are formed in the oxide semiconductor layer 140. On the other hand, impurities are not introduced into regions of the oxide semiconductor layer 140 that overlap with the gate electrode 160, and no oxygen defects are formed. That is, a channel region CH is formed in the oxide semiconductor layer 140. Note that impurities are introduced into the gate electrode 160 that was used as a mask.

[0080] Furthermore, in the second ion implantation in step S1100, impurities are also introduced into the gate insulating layer 150 and the oxide insulating layer 120. The impurities introduced into the gate insulating layer 150 and the oxide insulating layer 120 form dangling bond defects DB. The regions of the gate insulating layer 150 and the oxide insulating layer 120 where the dangling bond defects DB are formed can function as hydrogen trapping regions.

[0081] The first ion implantation in step S1060 and the second ion implantation in step S1100 form a first region A1, a second region A2, and a third region A3. In the first region A1, the gate electrode 160 contains impurities. In the second region A2, the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150 contain impurities. The oxide semiconductor layer 140 in the second region A2 functions as a source region or a drain region. The oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 function as a hydrogen trapping region. In the third region A3, the oxide insulating layer 120 and the gate insulating layer 150 contain impurities. The oxide insulating layer 120 and the gate insulating layer 150 in the third region A3 function as a hydrogen trapping region.

[0082] In the second ion implantation in step S1100, impurity ions are implanted so as to have a concentration profile with a peak in one of the oxide semiconductor layer 140 and the gate insulating layer 150 in the second region A2. The position of the peak and the amount of impurity can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, the dose is 1×10 14 / cm 2 That's it, 5 x 10 14 / cm 2 , or 1×10 15 / cm 2 For example, the acceleration voltage is greater than 10 keV, 15 keV or more, or 20 keV or more.

[0083] Hydrogen is introduced into the oxygen defects in the source region S and the drain region D to reduce their resistance. However, if hydrogen penetrates into the channel region CH, the channel region CH also becomes less resistant, causing humps or depression, deteriorating the electrical characteristics of the semiconductor device. Therefore, it is necessary to form a hydrogen trapping region that suppresses hydrogen penetration into the channel region CH. In particular, in the formation of the insulating layer 170 described below, it is important to form a hydrogen trapping region not only in the gate insulating layer 150 but also in the oxide insulating layer 120. In this embodiment, before forming the gate insulating layer 150, a first ion implantation is performed in step S1060 to form a hydrogen trapping region in the oxide insulating layer 120. Therefore, even if the gate insulating layer 150 is thick (for example, if the gate insulating layer 150 is 200 nm or thicker), sufficient impurities can be ion-implanted into the oxide insulating layer 120 to form dangling bond defects DB and form a hydrogen trapping region.

[0084] As shown in FIGS. 6 and 15, insulating layers 170 and 180 are formed as interlayer films on the gate insulating layer 150 and the gate electrode 160 (step S1110 "interlayer film formation" in FIG. 6). The insulating layers 170 and 180 are formed by a CVD method. For example, a silicon nitride layer is formed as the insulating layer 170, and a silicon oxide layer is formed as the insulating layer 180. However, the materials used for the insulating layers 170 and 180 are not limited to those mentioned above. The thickness of the insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.

[0085] 6 and 16, openings 171 and 173 are formed in the insulating layers 170 and 180 ("contact hole" in step S1120 of FIG. 6). The source region S is exposed through the opening 171. The drain region D is exposed through the opening 173. By forming source-drain electrodes 200 on the source region S and drain region D exposed through the openings 171 and 173 and on the insulating layer 180 ("SD formation" in step S1130 of FIG. 6), the semiconductor device 10 shown in FIG. 1 is completed.

[0086] The method for manufacturing the semiconductor device 10 shown in Fig. 1 is not limited to the method described above. For example, steps S1050 and S1060 may be performed after step S1010. In this case, a mask layer 300 having a predetermined pattern is formed on the oxide insulating layer 120 (see Fig. 17). Furthermore, impurity ions are implanted into the oxide insulating layer 120 using the mask layer 300 as a mask (see Fig. 18). Then, steps S1020 to S1040 and steps S1070 to S1130 are performed in this order.

[0087] [5. Hydrogen trapping at dangling bond defects (DB)] 19 and 20 are schematic cross-sectional views illustrating hydrogen trapping regions in the second and third regions in a semiconductor device according to one embodiment of the present invention.

[0088] As shown in FIG. 19, the first ion implantation in step S1060 and the second ion implantation in step S1100 introduce impurities into the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3, and dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150 in the second region A2 and the third region A3.

[0089] FIG. 20 shows the insulating layer 170 after it has been formed. To allow the insulating layer 170 to function as a blocker of impurities diffused from above, it is preferable that the insulating layer 170 be a dense film with few defects. To obtain such an insulating layer 170, the insulating layer 170 must be formed at a high temperature. For example, when a silicon nitride layer is formed as the insulating layer 170, the insulating layer 170 contains a large amount of hydrogen, and a large amount of hydrogen diffuses from the insulating layer 170 to the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate insulating layer 150 due to the film formation temperature. Therefore, if hydrogen trapping regions are not formed in the oxide insulating layer 120 and the gate insulating layer 150, hydrogen will diffuse not only into the source region S and the drain region D but also into the channel region CH through the oxide insulating layer 120 and the gate insulating layer 150.

[0090] On the other hand, as shown in FIG. 20 , when dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150, hydrogen H diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by the dangling bond defects DB (shown as a circle overlaid on an x). That is, the regions including the dangling bond defects DB in the oxide insulating layer 120 and the gate insulating layer 150 function as hydrogen trapping regions. Therefore, in step S1110, hydrogen H diffused from the insulating layer 170 during or after the formation can be prevented from penetrating into the channel region CH. Therefore, a film containing a large amount of hydrogen can be used as the insulating layer 170, thereby realizing an insulating layer 170 with a high impurity blocking function. Furthermore, the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D can be sufficiently reduced.

[0091] In this embodiment, based on the distribution of dangling bond defects DB formed in the oxide insulating layer 120, the amount of trapped hydrogen H may increase in the order of the oxide insulating layer 120 in the first region A1, the oxide insulating layer 120 in the second region A2, and the oxide insulating layer 120 in the third region A3.

[0092] In this embodiment, in the second region A2 and the third region A3 surrounding the channel region CH, hydrogen trapping regions including many dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150, thereby suppressing hydrogen from penetrating into the channel region CH. As a result, a semiconductor device 10 having electrical characteristics in which humps are suppressed can be obtained.

[0093] Second Embodiment 21 to 26, a semiconductor device 20 according to one embodiment of the present invention will be described. In the following, when the configuration of the semiconductor device 20 is similar to that of the semiconductor device 10, the description of the semiconductor device 20 may be omitted.

[0094] [1. Configuration of semiconductor device 20 and materials of each component] The semiconductor device 20 has an outline similar to that of the semiconductor device 10 shown in Figures 1 and 2, and therefore a description thereof will be omitted here. Furthermore, the materials of the components of the semiconductor device 20 are also similar to those of the semiconductor device 10, and therefore a description thereof will be omitted here.

[0095] [2. Hydrogen trapping area configuration] The hydrogen trapping region is formed in the oxide insulating layer 120 and the gate insulating layer 150. The configuration of the hydrogen trapping region formed in the oxide insulating layer 120 and the gate insulating layer 150 will now be described with reference to FIGS.

[0096] Fig. 21 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. Specifically, Fig. 21 is an enlarged cross-sectional view of region P in Fig. 1. Region P shown in Fig. 21 is a region near drain region D, but the region near source region S also has a similar configuration to region P.

[0097] The gate electrode 160 is used as a mask for the ion implantation of impurities to form the source region S and the drain region D, but the ion implantation of impurities into the oxide semiconductor layer 140 is performed through the gate insulating layer 150. Therefore, the impurities are also introduced into the gate insulating layer 150 in the second region A2 and the third region A3, thereby forming dangling bond defects DB in the gate insulating layer 150. Furthermore, in the second region A2 and the third region A3, the impurities may pass through the oxide semiconductor layer 140 and the gate insulating layer 150 and be introduced into the oxide insulating layer 120. Note that in this embodiment, in order to form dangling bond defects DB in the oxide insulating layer 120 in the third region A3, the ion implantation of impurities is performed into the oxide insulating layer 120 separately from the ion implantation of impurities described above.

[0098] 21 , in the second region A2, dangling bond defects DB are formed in the gate insulating layer 150, and in the third region A3, dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150. When silicon oxide is used for each of the oxide insulating layer 120 and the gate insulating layer 150, silicon dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150.

[0099] 22 and 23 are graphs showing the concentration profiles of impurities in the first region A1 to the third region A3 in a semiconductor device according to one embodiment of the present invention. The vertical axis of each of the three concentration profiles shown in each of FIGS. 22 and 23 represents the concentration of impurities per unit volume (Concentration [ / cm 3]), and the horizontal axis indicates the names of layers in the stacking direction (thickness direction). "UC" on the horizontal axis corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the gate insulating layer 150. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170.

[0100] As shown in FIG. 22, in the first region A1, the concentration profile of the impurity has a peak in the gate electrode 160 (GL). That is, the first region A1 includes one peak. Metallic materials have a high blocking power for impurities introduced by ion implantation. When a metallic material is used for the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the gate insulating layer 150 (GI). Therefore, dangling bond defects DB caused by the introduction of impurities are not formed in the gate insulating layer 150 in the first region A1. However, the impurities may reach the gate insulating layer 150 as long as they do not affect the electrical characteristics of the semiconductor device 10.

[0101] In the second region A2, the impurity concentration profile has a peak in the oxide semiconductor layer 140 (OS). That is, the second region A2 includes one peak. In the stacking direction in the second region A2, the impurity concentration at the peak position in the oxide semiconductor layer 140 is higher than the impurity concentration contained in the gate insulating layer 150. Since the purpose of doping the impurity in the second region A2 is to form the source region S and the drain region D, it is preferable, but not limited to, to set the ion implantation conditions so as to obtain the above-described concentration profile. The impurity concentration profile in the second region A2 may have a peak in the gate insulating layer 150 (GI) (see FIG. 23). In this case, in the stacking direction in the second region A2, the impurity concentration at the peak position in the gate insulating layer 150 is higher than the impurity concentration contained in the oxide semiconductor layer 140.

[0102] In the third region A3, the impurity concentration profile has a peak in the oxide insulating layer 120 (UC). That is, the third region A3 includes one peak. In the stacking direction in the third region A3, the impurity concentration at the peak position of the oxide insulating layer 120 is higher than the impurity concentration contained in the gate insulating layer 150. The impurity concentration profile of the gate insulating layer 150 in the third region A3 is substantially the same as the impurity concentration profile of the gate insulating layer 150 in the second region A2. Therefore, the impurity concentration profile in the third region A3 shown in FIG. 23 may have peaks in the oxide insulating layer 120 (UC) and the gate insulating layer 150 (GI). In this case, the third region A3 includes two peaks.

[0103] As will be described in detail later, in this embodiment, at least two impurity ion implantations are performed. In the first impurity ion implantation, the impurity is introduced into the oxide insulating layer 120 in the third region A3. On the other hand, in the second impurity ion implantation, the impurity is introduced into the oxide insulating layer 120 in the second region A2 and the third region A3 via the gate insulating layer 150. Note that in the second impurity ion implantation, the impurity may be introduced into the oxide insulating layer 120. Therefore, in the oxide insulating layer 120 in the first region A1, the second region A2, and the third region A3, the impurity concentrations may increase in the order of the first region A1, the second region A2, and the third region A3. Note that when an impurity is introduced into the oxide insulating layer 120 in the second region A2, the impurity concentration of the oxide insulating layer 120 in the second region A2 becomes 1×10 16 / cm 3 is less than.

[0104] In this embodiment, the concentration of impurities contained at a predetermined position in the oxide insulating layer 120 in the stacking direction in the third region A3 is 1×10 16 / cm 3 That's it, 1×10 17 / cm 3 or more, or 1 x 10 18 / cm 3That is all. The predetermined position may be the peak position of the concentration profile, or may be a position corresponding to the interface between the oxide insulating layer 120 and the gate insulating layer 150. Alternatively, the predetermined position may be a position shifted a predetermined depth in the direction of the oxide insulating layer 120 from the position corresponding to the interface.

[0105] 2, the channel region CH belongs to the first region A1, the source region S and the drain region D belong to the second region A2, and the regions other than the channel region CH, the source region S, and the drain region D belong to the third region A3. That is, the channel region CH is sandwiched between the second region A2 and surrounded by the third region A3. Therefore, for example, hydrogen diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by hydrogen trapping regions formed in the gate insulating layer 150 in the second region A2 and the third region A3 located around the channel region CH and in the oxide insulating layer 120 in the third region A3. As a result, the hydrogen can be prevented from penetrating into the channel region CH.

[0106] 3. Method for Manufacturing Semiconductor Device 10 A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 24 to 26. Figure 24 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 25 and 26 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0107] Steps S2010 to S2030 shown in Fig. 24 are similar to steps S1010 to S1030 shown in Fig. 5. However, in step S2030, the resist mask 310 used for patterning the oxide semiconductor layer 140 is not removed but remains as it is, as shown in Fig. 25.

[0108] As shown in FIGS. 24 and 26, impurity ions are implanted into the oxide insulating layer 120 using the resist mask 310 as a mask ("first ion implantation" in step S2040 in FIG. 24). As the impurity, for example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is used. As a result, the impurity such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is introduced into the oxide insulating layer 120. The impurity introduced into the oxide insulating layer 120 forms dangling bond defects DB. The region of the oxide insulating layer 120 where the dangling bond defects DB are formed can function as a hydrogen trap region.

[0109] In the first ion implantation in step S2040, it is important to form dangling bond defects DB in the oxide insulating layer 120 while not forming dangling bond defects DB in the nitride insulating layer 110. Therefore, in the first ion implantation, impurity ions are implanted so as to have a concentration profile with a peak in the oxide insulating layer 120. The position of the peak and the amount of impurity can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, the dose is 1×10 14 / cm 2 That's it, 5 x 10 14 / cm 2 , or 1×10 15 / cm 2 For example, the acceleration voltage is greater than 10 keV, 15 keV or more, or 20 keV or more.

[0110] Note that after the impurities are added to the oxide insulating layer 120, the resist mask 310 is removed.

[0111] After the first ion implantation in step S2040, heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 ("OS annealing" in step S2050 in FIG. 24). Step S2040 is similar to step S1050.

[0112] Steps S2060 to S2120 shown in FIG. 24 are the same as steps S1070 to S1130 shown in FIG.

[0113] In this embodiment, based on the distribution of dangling bond defects DB formed in the oxide insulating layer 120, the amount of trapped hydrogen H may increase in the order of the oxide insulating layer 120 in the first region A1, the oxide insulating layer 120 in the second region A2, and the oxide insulating layer 120 in the third region A3.

[0114] In this embodiment, in the second region A2 and the third region A3 surrounding the channel region CH, hydrogen trapping regions including many dangling bond defects DB are formed in the oxide insulating layer 120 and the gate insulating layer 150, thereby suppressing hydrogen from penetrating into the channel region CH. As a result, a semiconductor device 20 having electrical characteristics in which humps are suppressed can be obtained.

[0115] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits steps or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0116] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0117] 10, 20: semiconductor device, 100: substrate, 105: light-shielding layer, 110: nitride insulating layer, 120: oxide insulating layer, 140: oxide semiconductor layer, 141: upper surface, 142: lower surface, 143: side surface, 150: gate insulating layer, 160: gate electrode, 165A: oxide insulating layer, 170: insulating layer, 171: opening, 173: opening, 180: insulating layer, 200: source / drain electrode, 201: source electrode, 203: drain electrode, 300: mask layer, 310: resist mask, A1: first region, A2: second region, A3: third region, CH: channel region, D: drain region, DB: dangling bond defect, S: source region

Claims

1. A semiconductor device comprising: an oxide insulating layer; an oxide semiconductor layer on the oxide insulating layer; a gate insulating layer on the oxide semiconductor layer; and a gate electrode on the gate insulating layer, wherein in a first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order, the gate electrode contains an impurity; in a second region not including the gate electrode and where the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in this order, the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer contain the impurity; in a third region not including the gate electrode and the oxide semiconductor layer and where the oxide insulating layer and the gate insulating layer are stacked in this order, the oxide insulating layer and the gate insulating layer contain the impurity, and a concentration profile of the impurity in the stacking direction in the second region includes a first peak and a second peak.

2. The semiconductor device according to claim 1, wherein the first peak is included in the oxide insulating layer.

3. The semiconductor device according to claim 2, wherein the second peak is included in the oxide semiconductor layer.

4. The semiconductor device according to claim 2, wherein the second peak is included in the gate insulating layer.

5. The semiconductor device according to claim 1, wherein the impurity concentration profile in the stacking direction of the third region includes a third peak and a fourth peak.

6. The semiconductor device according to claim 5, wherein the third peak is included in the oxide insulating layer.

7. The semiconductor device according to claim 6, wherein the fourth peak is included in the gate insulating layer.

8. A semiconductor device comprising: an oxide insulating layer; an oxide semiconductor layer on the oxide insulating layer; a gate insulating layer on the oxide semiconductor layer; and a gate electrode on the gate insulating layer, wherein in a first region where the oxide insulating layer, the oxide semiconductor layer, the gate insulating layer, and the gate electrode are stacked in this order, the gate electrode contains an impurity; in a second region not including the gate electrode and where the oxide insulating layer, the oxide semiconductor layer, and the gate insulating layer are stacked in this order, the oxide semiconductor layer and the gate insulating layer contain the impurity; in a third region not including the gate electrode and the oxide semiconductor layer and where the oxide insulating layer and the gate insulating layer are stacked in this order, the oxide insulating layer and the gate insulating layer contain the impurity, and a concentration profile of the impurity in the stacking direction in the third region includes a first peak and a second peak.

9. The semiconductor device according to claim 8, wherein the first peak is contained in the oxide insulating layer.

10. The semiconductor device according to claim 9, wherein the second peak is included in the gate insulating layer.

11. In the second region, the concentration of the impurity contained in the oxide insulating layer is 1×10 １６ / cm ３ The semiconductor device according to claim 8 , wherein the thickness is less than 100 nm.

12. The semiconductor device according to claim 1, wherein the impurity is one selected from the group consisting of boron, phosphorus, argon, and nitrogen.

13. The semiconductor device according to claim 1, wherein the gate insulating layer has a thickness of 100 nm or more.

14. A method for manufacturing a semiconductor device, comprising: forming an oxide insulating layer; forming a mask layer having a first pattern on the oxide insulating layer; injecting a first impurity into the oxide insulating layer using the mask layer as a mask; forming an oxide semiconductor layer having a second pattern on the oxide insulating layer; covering the oxide semiconductor layer, forming a gate insulating layer on the oxide insulating layer and the oxide semiconductor layer; forming a gate electrode having a third pattern on the gate insulating layer; and injecting a second impurity into the oxide semiconductor layer using the gate electrode as a mask.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the first pattern and the third pattern substantially coincide with each other.

16. A method for manufacturing a semiconductor device, comprising: forming an oxide insulating layer; forming an oxide semiconductor layer having a first pattern on the oxide insulating layer; injecting a first impurity into the oxide insulating layer using a resist having the first pattern on which the oxide semiconductor layer is formed as a mask; covering the oxide semiconductor layer, forming a gate insulating layer on the oxide insulating layer and the oxide semiconductor layer; forming a gate electrode having a second pattern on the gate insulating layer; and injecting a second impurity into the oxide semiconductor layer using the gate electrode as a mask.

17. A method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein the first impurity and the second impurity are the same element.

18. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein the first impurity and the second impurity are different elements.

19. A method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein each of the first impurity and the second impurity is one selected from the group consisting of boron, phosphorus, argon, and nitrogen.

20. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein the gate insulating layer has a thickness of 100 nm or more.