Photoelectric conversion element and imaging device

Abstract

This photoelectric conversion element comprises: a photoelectric conversion layer (4) that contains a donor semiconductor material (4A) and an acceptor semiconductor material (4B) and converts light into a signal charge; a first electrode (2) that collects the signal charge; a second electrode (7) that faces the first electrode (2) from across the photoelectric conversion layer (4); and a charge injection layer (5) located between the second electrode (7) and the photoelectric conversion layer (4). The charge injection layer (5) includes a first layer (6A), and a second layer (6B) stacked on the first layer (6A). The ionization potential of the first layer (6A) is greater than the ionization potential of the second layer (6B). The electron affinity of the first layer (6A) is greater than the electron affinity of the second layer (6B). The difference (ΔE1) between the electron affinity of the first layer (6A) and the ionization potential of the second layer (6B) is smaller than the difference (ΔE2) between the electron affinity of the acceptor semiconductor material (4B) and the ionization potential of the donor semiconductor material (4A).

Description

Photoelectric conversion element and imaging device

[0001] The present disclosure relates to a photoelectric conversion element and an imaging device.

[0002] Photoelectric conversion elements using semiconductor thin films can be used as optical sensors, etc., by extracting charges generated by light as an electrical signal. For example, Patent Document 1 discloses a photoelectric conversion element that includes an electron-blocking layer or a hole-blocking layer between the photoelectric conversion material thin film and the electrode to prevent backflow of charges from the electrode. Patent Document 2 also discloses a method of changing the bias voltage applied to electrodes connected to both ends of the photoelectric conversion element.

[0003] Japanese Patent No. 5969843 Japanese Patent Application Laid-Open No. 2018-092990

[0004] When a photoelectric conversion element is used in an imaging device or the like, it is desirable to reduce parasitic sensitivity, which is unintended sensitivity, in order to improve the S / N (signal-to-noise) ratio of the imaging device or the like.

[0005] Therefore, an object of the present disclosure is to provide a photoelectric conversion element or the like that can reduce parasitic sensitivity.

[0006] A photoelectric conversion element according to one aspect of the present disclosure includes a photoelectric conversion layer containing a donor semiconductor material and an acceptor semiconductor material and converting light into signal charges, a first electrode collecting the signal charges, a second electrode facing the first electrode across the photoelectric conversion layer, and a charge injection layer located between the second electrode and the photoelectric conversion layer. The charge injection layer includes a first layer and a second layer stacked on the first layer. The ionization potential of the first layer is greater than the ionization potential of the second layer. The electron affinity of the first layer is greater than the electron affinity of the second layer. The difference between the electron affinity of the first layer and the ionization potential of the second layer is smaller than the difference between the electron affinity of the acceptor semiconductor material and the ionization potential of the donor semiconductor material.

[0007] An imaging device according to an aspect of the present disclosure includes the photoelectric conversion element and a charge accumulation region electrically connected to the first electrode and configured to accumulate the signal charge.

[0008] According to the present disclosure, it is possible to provide a photoelectric conversion element or the like that can reduce parasitic sensitivity.

[0009] FIG. 1 is a schematic cross-sectional view showing the configuration of a photoelectric conversion element according to an embodiment. FIG. 2 is an exemplary energy band diagram of a photoelectric conversion element according to an embodiment. FIG. 3 is an exemplary energy band diagram of a photoelectric conversion element according to an embodiment when a reverse bias voltage is applied. FIG. 4 is an exemplary energy band diagram of a photoelectric conversion element according to an embodiment when a forward bias voltage is applied. FIG. 5 is a schematic cross-sectional view showing the configuration of another photoelectric conversion element according to an embodiment. FIG. 6 is an exemplary energy band diagram of another photoelectric conversion element according to an embodiment. FIG. 7 is a diagram showing an example of a circuit configuration of an imaging device according to an embodiment. FIG. 8 is a schematic cross-sectional view showing the device structure of a pixel in an imaging device according to an embodiment. FIG. 9 is a diagram showing a portion of a schematic circuit configuration of a pixel according to an embodiment. FIG. 10 is a timing chart showing an example of a voltage supplied to an upper electrode of a photoelectric conversion unit according to an embodiment and an example of the timing of operations in each row of a pixel array of an imaging device. FIG. 11 is a timing chart showing an example of an operation for adjusting photoelectric conversion sensitivity using a pulse duty control system in an imaging device according to an embodiment. FIG. 12 is a diagram showing current density-voltage characteristics when a bias voltage is applied to a photoelectric conversion element in an example. FIG. 13 is a diagram showing the current density-voltage characteristics when a bias voltage is applied to the photoelectric conversion element in the comparative example.

[0010] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, examples of a photoelectric conversion element and an imaging device according to the present disclosure will be described below.

[0011] A photoelectric conversion element according to a first aspect of the present disclosure includes a photoelectric conversion layer containing a donor semiconductor material and an acceptor semiconductor material and converting light into signal charges, a first electrode collecting the signal charges, a second electrode facing the first electrode across the photoelectric conversion layer, and a charge injection layer located between the second electrode and the photoelectric conversion layer. The charge injection layer includes a first layer and a second layer stacked on the first layer. The ionization potential of the first layer is greater than the ionization potential of the second layer. The electron affinity of the first layer is greater than the electron affinity of the second layer. The difference between the electron affinity of the first layer and the ionization potential of the second layer is smaller than the difference between the electron affinity of the acceptor semiconductor material and the ionization potential of the donor semiconductor material.

[0012] In a charge injection layer including first and second layers with such ionization potentials and electron affinities, charge is likely to be generated at the interface between the first and second layers. Therefore, when the signal charge migration to the first electrode is stopped and the signal charge collected by the first electrode is read, signal charge remains in the photoelectric conversion layer. However, among the charges generated in the charge injection layer, charges of opposite polarity to the signal charge migrate toward the first electrode and can recombine with the signal charge remaining in the photoelectric conversion layer. This suppresses the migration of signal charge to the first electrode during signal charge readout, regardless of the amount of light irradiated onto the photoelectric conversion layer, thereby suppressing the occurrence of unintended sensitivity. Therefore, according to this aspect, parasitic sensitivity can be reduced.

[0013] Furthermore, for example, a photoelectric conversion element according to a second aspect of the present disclosure may be the photoelectric conversion element according to the first aspect, in which the signal charges are holes.

[0014] This allows the holes remaining in the photoelectric conversion layer to recombine with the electrons generated in the charge injection layer when the holes are read out as signal charges, thereby reducing parasitic sensitivity.

[0015] Furthermore, for example, a photoelectric conversion element according to a third aspect of the present disclosure may be the photoelectric conversion element according to the second aspect, in which the first layer is located between the second layer and the photoelectric conversion layer.

[0016] This can suppress the energy barrier that occurs when electrons generated in the charge injection layer move to the photoelectric conversion layer.

[0017] Furthermore, for example, the photoelectric conversion element according to the fourth aspect of the present disclosure may be a photoelectric conversion element according to the second or third aspect, further comprising an electron blocking layer located between the first electrode and the photoelectric conversion layer.

[0018] This makes it possible to suppress dark current.

[0019] Furthermore, for example, a photoelectric conversion element according to a fifth aspect of the present disclosure may be the photoelectric conversion element according to the first aspect, in which the signal charges are electrons.

[0020] This allows the electrons remaining in the photoelectric conversion layer to recombine with the holes generated in the charge injection layer when the electrons are read out as signal charges, thereby reducing parasitic sensitivity.

[0021] Furthermore, for example, a photoelectric conversion element according to a sixth aspect of the present disclosure may be the photoelectric conversion element according to the fifth aspect, wherein the second layer is located between the first layer and the photoelectric conversion layer.

[0022] This can suppress the energy barrier that occurs when holes generated in the charge injection layer move to the photoelectric conversion layer.

[0023] Furthermore, for example, the photoelectric conversion element according to the seventh aspect of the present disclosure may be the photoelectric conversion element according to the fifth or sixth aspect, further comprising a hole-blocking layer located between the first electrode and the photoelectric conversion layer.

[0024] This makes it possible to suppress dark current.

[0025] Furthermore, for example, a photoelectric conversion element according to an eighth aspect of the present disclosure is the photoelectric conversion element according to any one of the first to seventh aspects, and the first layer may contain the same material as the acceptor semiconductor material.

[0026] This makes it possible to realize a photoelectric conversion element that can reduce parasitic sensitivity using a small number of materials.

[0027] Furthermore, for example, a photoelectric conversion element according to a ninth aspect of the present disclosure may be the photoelectric conversion element according to any one of the first to eighth aspects, wherein the second layer contains the same material as the donor semiconductor material.

[0028] This makes it possible to realize a photoelectric conversion element that can reduce parasitic sensitivity using a small number of materials.

[0029] Furthermore, for example, a photoelectric conversion element according to a tenth aspect of the present disclosure is the photoelectric conversion element according to any one of the first to seventh aspects, in which the photoelectric conversion layer may be a mixed film containing the donor semiconductor material and the acceptor semiconductor material, the first layer may contain the same material as the acceptor semiconductor material, and the second layer may contain the same material as the donor semiconductor material.

[0030] As a result, in the mixed film, the donor semiconductor material and the acceptor semiconductor material are less susceptible to stabilization than in a single-material film, and the difference between the electron affinity and the ionization potential is wider. Therefore, even if the charge injection layer and the photoelectric conversion layer contain the same material, the difference between the electron affinity of the first layer and the ionization potential of the second layer is smaller than the difference between the electron affinity of the acceptor semiconductor material and the ionization potential of the donor semiconductor material in the photoelectric conversion layer. Therefore, a configuration having the above-mentioned relationship between electron affinity and ionization potential can be easily realized.

[0031] In addition, an imaging device according to an eleventh aspect of the present disclosure includes a photoelectric conversion element according to any one of the first to tenth aspects, and a charge accumulation region electrically connected to the first electrode and accumulating the signal charge.

[0032] As a result, the imaging device according to this aspect includes the photoelectric conversion element, and therefore can suppress parasitic sensitivity.

[0033] Also, for example, an imaging device according to a twelfth aspect of the present disclosure may be the imaging device according to the eleventh aspect, further comprising a voltage supply circuit electrically connected to the second electrode and applying a potential difference between the first electrode and the second electrode, and the voltage supply circuit may supply a first voltage to the second electrode during a first period, and supply a second voltage different from the first voltage during a second period different from the first period.

[0034] Thus, by setting the first voltage and the second voltage in accordance with the characteristics of the photoelectric conversion element, the timing of photoelectric conversion and the timing of readout can be separated, and parasitic sensitivity can be further reduced.

[0035] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0036] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0037] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0038] Furthermore, in this specification, terms indicating the relationship between elements, such as vertical, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0039] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are used not only when two components are arranged with a gap between them and another component exists between them, but also when two components are arranged closely together and are in contact with each other.

[0040] In this specification, electromagnetic waves in general, including visible light, infrared light, and ultraviolet light, are referred to as "light" for convenience.

[0041] (Embodiment) Hereinafter, the present embodiment will be described.

[0042] [Photoelectric Conversion Element] First, a photoelectric conversion element according to the present embodiment will be described. The photoelectric conversion element according to the present embodiment is a charge readout type photoelectric conversion element. The photoelectric conversion element according to the present embodiment is used in, for example, an imaging device, a photosensor, or a photodetector. Fig. 1 is a schematic cross-sectional view showing the configuration of a photoelectric conversion element 10 according to the present embodiment.

[0043] 1 , photoelectric conversion element 10 is supported on support substrate 1, and includes a pair of electrodes, an upper electrode 7 and a lower electrode 2, a photoelectric conversion layer 4 located between the upper electrode 7 and the lower electrode 2, a charge injection layer 5 located between the upper electrode 7 and the photoelectric conversion layer 4, and an electron blocking layer 3 located between the lower electrode 2 and the photoelectric conversion layer 4. In this embodiment, the upper electrode 7 is an example of a second electrode, and the lower electrode 2 is an example of a first electrode.

[0044] Hereinafter, each component of the photoelectric conversion element 10 according to this embodiment will be described.

[0045] The support substrate 1 may be any substrate that is commonly used to support a photoelectric conversion element, such as a glass substrate, a quartz substrate, a semiconductor substrate, or a plastic substrate.

[0046] The lower electrode 2 collects signal charges generated in the photoelectric conversion layer 4. The lower electrode 2 is formed from a metal, a metal nitride, a metal oxide, or polysilicon that has been given electrical conductivity. Examples of metals include aluminum, copper, titanium, and tungsten. An example of a method for giving electrical conductivity to polysilicon is doping with impurities.

[0047] The upper electrode 7 is disposed opposite the lower electrode 2 with the photoelectric conversion layer 4 interposed therebetween. The upper electrode 7 is, for example, a transparent electrode formed from a transparent conductive material. Examples of materials for the upper electrode 7 include transparent conductive oxide (TCO), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), and SnO. ２ and TiO ２ The upper electrode 7 may be made of a TCO and a metal material such as aluminum (Al) or gold (Au) either singly or in combination, depending on the desired transmittance.

[0048] The materials for the lower electrode 2 and the upper electrode 7 are not limited to the conductive materials described above, and other materials may be used. For example, the lower electrode 2 may be a transparent electrode.

[0049] The lower electrode 2 and the upper electrode 7 can be fabricated by various methods depending on the materials used. For example, when ITO is used, methods such as an electron beam method, a sputtering method, a resistance heating vapor deposition method, a chemical reaction method such as a sol-gel method, or the application of a dispersion of indium tin oxide can be used. In this case, the lower electrode 2 and the upper electrode 7 can be fabricated by further performing UV-ozone treatment, plasma treatment, or the like after forming an ITO film.

[0050] The photoelectric conversion layer 4 includes a donor semiconductor material and an acceptor semiconductor material. The photoelectric conversion layer 4 is made of, for example, an organic semiconductor material. The photoelectric conversion layer 4 can be made by, for example, a wet method such as a coating method using spin coating or a dry method such as a vacuum deposition method. The vacuum deposition method is a method in which a layer material is vaporized by heating under vacuum and deposited on a substrate. The charge injection layer 5 can also be made by the same method as the photoelectric conversion layer 4.

[0051] The photoelectric conversion layer 4 is, for example, a mixed film with a bulk heterostructure containing a donor semiconductor material such as a donor organic semiconductor material and an acceptor semiconductor material such as an acceptor organic semiconductor material. The photoelectric conversion layer 4 may have a laminated structure in which a layer of the donor semiconductor material and a layer of the acceptor semiconductor material are laminated.

[0052] The photoelectric conversion layer 4 can be easily formed as a thin film by including a donor organic semiconductor material and an acceptor organic semiconductor material. Specific examples of donor organic semiconductor materials and acceptor organic semiconductor materials are given below.

[0053] Examples of donor organic semiconductor materials include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, naphthalocyanine compounds, subphthalocyanine compounds, cyanine compounds, merocyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, fused aromatic carbon ring compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives), and metal complexes having nitrogen-containing heterocyclic compounds as ligands. However, without being limited thereto, any organic compound having a smaller ionization potential than the organic compound used as the acceptor organic semiconductor material may be used as the donor organic semiconductor material.

[0054] Examples of the acceptor organic semiconductor material include fullerenes (e.g., C60 fullerene and C70 fullerene), fullerene derivatives (e.g., PCBM (phenyl C61 butyric acid methyl ester) and ICBA (indene C60 bisadduct)), fused aromatic carbocyclic compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives), 5- to 7-membered heterocyclic compounds containing nitrogen atoms, oxygen atoms, and sulfur atoms (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, Examples of the acceptor organic semiconductor material include metal complexes having isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, tribenzazepine, etc.), polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, and nitrogen-containing heterocyclic compounds as ligands. However, the acceptor organic semiconductor material is not limited thereto, and any organic compound having a larger electron affinity than the organic compound used as the donor organic semiconductor material may be used as the acceptor organic semiconductor material.

[0055] The donor organic semiconductor material and the acceptor organic semiconductor material are not limited to the above examples. Low-molecular-weight organic compounds and high-molecular-weight organic compounds may be used as the donor organic semiconductor material and the acceptor organic semiconductor material constituting the photoelectric conversion layer 4, as long as they are organic compounds that can be formed into a film as a photoelectric conversion layer by either a dry method or a wet method.

[0056] The photoelectric conversion layer 4 may also contain semiconductor materials other than those mentioned above as donor semiconductor materials and acceptor semiconductor materials. The photoelectric conversion layer 4 may also contain, as semiconductor materials, for example, silicon semiconductors, compound semiconductors, quantum dots, perovskite materials, carbon nanotubes, etc., or a mixture of two or more of these.

[0057] The photoelectric conversion element 10 according to this embodiment includes an electron blocking layer 3 provided between the lower electrode 2 and the photoelectric conversion layer 4, and a charge injection layer 5 provided between the upper electrode 7 and the photoelectric conversion layer 4. The electron blocking layer 3 is in contact with, for example, the lower electrode 2 and the photoelectric conversion layer 4. The charge injection layer 5 is in contact with, for example, the upper electrode 7 and the photoelectric conversion layer 4. Note that the photoelectric conversion element 10 does not necessarily have to include the electron blocking layer 3.

[0058] The charge injection layer 5 has a first layer 6A and a second layer 6B stacked on the first layer 6A. The first layer 6A and the second layer 6B are in contact with each other. In the photoelectric conversion element 10, the first layer 6A is located between the second layer 6B and the photoelectric conversion layer 4. The first layer 6A is in contact with the photoelectric conversion layer 4, for example. The second layer 6B is in contact with the upper electrode 7, for example.

[0059] Here, the functions of the electron blocking layer 3, the photoelectric conversion layer 4, and the charge injection layer 5 will be described with reference to energy band diagrams. Fig. 2 is an exemplary energy band diagram for the photoelectric conversion element 10 shown in Fig. 1. In Fig. 2, the energy band of each layer is indicated by a rectangle.

[0060] The photoelectric conversion layer 4 generates electron-hole pairs inside when irradiated with light. In the photoelectric conversion element 10, the holes in these pairs are collected by the lower electrode 2 and used as signal charges to be read out. In other words, the photoelectric conversion layer 4 converts light into signal charges. Note that the signal charges may be electrons. An example in which the signal charges are electrons will be described later.

[0061] Electron-hole pairs generated in the photoelectric conversion layer 4 are separated into electrons and holes by the electric field applied to the photoelectric conversion layer 4. The electrons and holes move toward the lower electrode 2 or the upper electrode 7, respectively, according to the electric field. Here, among the electron-hole pairs generated by absorbing light, the semiconductor material that donates the electrons to the other material is a donor semiconductor material, and the semiconductor material that accepts the electrons is an acceptor semiconductor material. When the photoelectric conversion layer 4 is irradiated with light, for example, the donor semiconductor material generates electron-hole pairs and donates the electrons to the acceptor semiconductor material. This allows the electrons and holes to be easily separated.

[0062] FIG. 2 shows an example of energy bands when organic semiconductor materials are used as donor and acceptor semiconductor materials. When two different types of organic semiconductor materials are used, which one serves as the donor semiconductor material and which one serves as the acceptor semiconductor material is generally determined by the relative positions of the HOMO (Highest-Occupied-Molecular-Orbital) and LUMO (Lowest-Unoccupied-Molecular-Orbital) energy levels of each of the two organic semiconductor materials at the contact interface. In FIG. 2 , the top end of the rectangle representing the energy band is the LUMO energy level, and the bottom end is the HOMO energy level. The energy difference between the vacuum level and the HOMO energy level is referred to as the ionization potential. The energy difference between the vacuum level and the LUMO energy level is referred to as the electron affinity. In this specification, in energy band diagrams such as Fig. 2, the electron affinity and ionization potential increase toward the lower side. When the semiconductor material contained in photoelectric conversion layer 4 is an inorganic semiconductor material, the HOMO and LUMO can be interpreted as the valence band and conduction band, respectively.

[0063] As shown in Fig. 2, of the two types of organic semiconductor materials, the one with the smaller LUMO energy level, i.e., the smaller electron affinity, is the donor organic semiconductor material 4A. Furthermore, of the two types of organic semiconductor materials contained in the photoelectric conversion layer 4, the one with the larger LUMO energy level, i.e., the larger electron affinity, is the acceptor organic semiconductor material 4B. Note that in Fig. 2, the energy bands of the donor organic semiconductor material 4A and the acceptor organic semiconductor material 4B are shown slightly shifted in the horizontal direction, but this is for ease of viewing and does not represent the distribution of the donor organic semiconductor material 4A and the acceptor organic semiconductor material 4B in the photoelectric conversion layer 4.

[0064] The electron blocking layer 3 is provided to reduce dark current caused by electron injection from the lower electrode 2, and suppresses electrons from the lower electrode 2 from being injected into the photoelectric conversion layer 4. This reduces noise signals that adversely affect the S / N ratio. As shown in FIG. 2 , in order to suppress electrons from the lower electrode 2 from being injected into the photoelectric conversion layer 4, the electron affinity of the material of the electron blocking layer 3 is smaller than the work function of the lower electrode 2 and the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4.

[0065] 2 , the ionization potential of the electron blocking layer 3 is greater than the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4. The electron affinity of the electron blocking layer 3 is smaller than the electron affinity of the donor organic semiconductor material 4A of the photoelectric conversion layer 4.

[0066] The electron blocking layer 3 may be made of the semiconductor material exemplified above as the donor semiconductor material or a hole transporting organic compound.

[0067] The first layer 6A and the second layer 6B in the charge injection layer 5 have an acceptor-donor relationship, respectively. The first layer 6A is a layer that can function as an acceptor that accepts electrons from the second layer 6B, and the second layer 6B is a layer that can function as a donor that donates electrons to the first layer 6A. Specifically, the ionization potential of the first layer 6A is greater than the ionization potential of the second layer 6B, and the electron affinity of the first layer 6A is greater than the electron affinity of the second layer 6B.

[0068] As a result, at the interface where the first layer 6A and the second layer 6B come into contact, thermal electronic excitation occurs from the HOMO of the second layer 6B to the LUMO of the first layer 6A, generating charges regardless of the state of light irradiation on the photoelectric conversion element 10. When such electronic excitation occurs, electrons are present in the first layer 6A and holes are present in the second layer 6B. Furthermore, in the charge injection layer 5, because the electron affinity of the first layer 6A is greater than that of the second layer 6B, thermal electronic excitation at the interface is more likely to occur than thermal electronic excitation within the first layer 6A.

[0069] Furthermore, the difference ΔE1 between the electron affinity of the first layer 6A and the ionization potential of the second layer 6B is smaller than the difference ΔE2 between the electron affinity of the acceptor organic semiconductor material 4B and the ionization potential of the donor organic semiconductor material 4A. As a result, the energy difference at the interface between the first layer 6A and the second layer 6B is smaller than the energy difference at the interface between the donor organic semiconductor material 4A and the acceptor organic semiconductor material 4B, and therefore more charges are generated by thermal excitation in the charge injection layer 5 than in the photoelectric conversion layer 4. This makes it easier for electrons to be injected from the charge injection layer 5 into the photoelectric conversion layer 4.

[0070] The charge injection layer 5 may also function as a hole-blocking layer to reduce dark current caused by holes injected from the upper electrode 7. This can reduce noise signals that adversely affect the S / N ratio. To prevent holes from being injected from the upper electrode 7 into the photoelectric conversion layer 4, the ionization potential of at least the material of the first layer 6A is greater than the work function of the upper electrode 7 and the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4. In FIG. 2, the ionization potential of the second layer 6B is smaller than the ionization potential of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4, but is not limited thereto and may be equal to or greater than the ionization potential of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4.

[0071] The material for the first layer 6A can be any of the semiconductor materials exemplified above as the acceptor semiconductor material or an electron transporting organic compound, and the material for the second layer 6B can be any of the semiconductor materials exemplified above as the donor semiconductor material or a hole transporting organic compound.

[0072] The material of the first layer 6A may be the same as the acceptor semiconductor material contained in the photoelectric conversion layer 4. The material of the second layer 6B may be the same as the donor semiconductor material contained in the photoelectric conversion layer 4. In this way, by having at least one of the first layer 6A and the second layer 6B contain the same material as the material contained in the photoelectric conversion layer 4, the photoelectric conversion element 10 can be manufactured using a smaller number of materials.

[0073] Alternatively, the first layer 6A may contain the same material as the acceptor semiconductor material contained in the photoelectric conversion layer 4, and the second layer 6B may contain the same material as the donor semiconductor material contained in the photoelectric conversion layer 4. For example, the first layer 6A may be composed of the acceptor organic semiconductor material 4B, and the second layer 6B may be composed of the donor organic semiconductor material 4A. When the photoelectric conversion layer 4 is a mixed film with a bulk heterostructure, the donor organic semiconductor material 4A and the acceptor organic semiconductor material 4B are less susceptible to stabilization than when they are single-material films, and the difference between the HOMO energy level and the LUMO energy level widens. As a result, even if the charge injection layer 5 and the photoelectric conversion layer 4 have the same material composition, the difference ΔE1 between the electron affinity of the first layer 6A and the ionization potential of the second layer 6B is smaller than the difference ΔE2 between the electron affinity of the acceptor organic semiconductor material 4B and the ionization potential of the donor organic semiconductor material 4A. Therefore, it is possible to easily realize a configuration in which ΔE1 is smaller than ΔE2.

[0074] Here, the driving of the photoelectric conversion element 10 will be described.

[0075] 2, when the lower electrode 2 is used in, for example, an imaging device, it is electrically connected to a charge storage node (described later). The charge storage node stores holes generated in the photoelectric conversion layer 4 and collected by the lower electrode 2.

[0076] 3 is an exemplary energy band diagram of the photoelectric conversion element 10 when a reverse bias voltage is applied between the lower electrode 2 and the upper electrode 7. Also, FIG. 4 is an exemplary energy band diagram of the photoelectric conversion element 10 when a forward bias voltage is applied between the lower electrode 2 and the upper electrode 7. In this specification, when the signal charges are holes, a voltage applied between the upper electrode 7 and the lower electrode 2 such that the potential of the upper electrode 7 is higher than the potential of the lower electrode 2 is referred to as a reverse bias, or so-called reverse bias voltage. Also, in this specification, when the signal charges are holes, a voltage applied between the upper electrode 7 and the lower electrode 2 such that the potential of the upper electrode 7 is lower than the potential of the lower electrode 2 is referred to as a forward bias, or so-called forward bias voltage.

[0077] The photoelectric conversion element 10 is driven by switching between, for example, a photoelectric conversion mode and a signal readout mode. In the photoelectric conversion mode, a reverse bias voltage as shown in FIG. 3 is applied between the upper electrode 7 and the lower electrode 2. The absolute value of this voltage is, for example, about 1 V to 10 V. In the signal readout mode, a forward bias voltage as shown in FIG. 4 is applied between the upper electrode 7 and the lower electrode 2. The absolute value of this voltage is, for example, about 0 V to 3 V.

[0078] For example, in the state shown in Fig. 3 as a photoelectric conversion mode, when light is incident on the photoelectric conversion layer 4, pairs of electrons and holes are generated in the photoelectric conversion layer 4, and of the generated electron-hole pairs, the holes, which are signal charges, move to the lower electrode 2, while the electrons, which are charges of the opposite polarity to the signal charges, move to the upper electrode 7. The holes that have moved to the lower electrode 2 are accumulated, for example, in a charge storage node. Thereafter, in the state shown in Fig. 4 as a signal readout mode, a signal based on the holes accumulated in the charge storage node is read out via the lower electrode 2.

[0079] In this case, when holes move from the photoelectric conversion layer 4 to the lower electrode 2 in the photoelectric conversion mode, they may not be able to move to the lower electrode 2 within the photoelectric conversion mode time and may remain in the photoelectric conversion layer 4 during the signal readout mode. When an organic semiconductor material is used for the photoelectric conversion layer 4, charge mobility is likely to be low, and holes are particularly likely to remain in the photoelectric conversion layer 4. Therefore, if holes remaining in the photoelectric conversion layer 4 move to the lower electrode 2 after the transition from the photoelectric conversion mode to the signal readout mode, this will manifest as parasitic sensitivity, an unintended sensitivity that may cause noise. In the photoelectric conversion element 10, thermal electronic excitation at the interface between the first layer 6A and the second layer 6B described above tends to cause electrons to be present in the first layer 6A. These electrons move toward the lower electrode 2 and recombine with holes remaining in the photoelectric conversion layer 4. As a result, the movement of holes remaining in the photoelectric conversion layer 4 to the lower electrode 2 during the signal readout mode is suppressed. This reduces parasitic sensitivity caused by holes remaining in the photoelectric conversion layer 4 migrating to the lower electrode 2. In particular, by positioning the first layer 6A between the second layer 6B and the photoelectric conversion layer 4, the second layer 6B does not act as a barrier to the movement of electrons to the photoelectric conversion layer 4, and therefore the electrons present in the first layer 6A are more likely to move to the photoelectric conversion layer 4. Note that even when the second layer 6B is positioned between the first layer 6A and the photoelectric conversion layer 4, the electrons present in the first layer 6A can still move to the photoelectric conversion layer 4, thereby achieving the effect of suppressing parasitic sensitivity.

[0080] As described above, the photoelectric conversion element 10 according to the present embodiment includes the photoelectric conversion layer 4 and the charge injection layer 5 having the above-described energy band configuration, and therefore, when reading out a signal based on holes that are signal charges, electrons are injected from the charge injection layer 5 into the photoelectric conversion layer 4, and the injected electrons recombine with the holes remaining in the photoelectric conversion layer 4. Therefore, when reading out a signal, the holes remaining in the photoelectric conversion layer 4 are prevented from moving to the lower electrode 2, and it is possible to effectively reduce parasitic sensitivity in a method of reading out holes from the lower electrode 2.

[0081] [Another Example of Photoelectric Conversion Element] Although the example in which the signal charges collected by the lower electrode 2 are holes has been described above, the signal charges may also be electrons. Another photoelectric conversion element according to this embodiment that uses electrons as signal charges will be described below with reference to FIGS. 5 and 6 .

[0082] Fig. 5 is a schematic cross-sectional view showing the configuration of another photoelectric conversion element 110 according to the present embodiment. Fig. 6 is an exemplary energy band diagram of the photoelectric conversion element 110 shown in Fig. 5. In the following description of the photoelectric conversion element 110, differences from the photoelectric conversion element 10 will be mainly described, and descriptions of commonalities will be omitted or simplified.

[0083] 5 and 6 , photoelectric conversion element 110 differs from photoelectric conversion element 10 described above in that it includes a hole blocking layer 103 and a charge injection layer 105 instead of electron blocking layer 3 and charge injection layer 5. Specifically, photoelectric conversion element 110 is supported on a support substrate 1, and includes a pair of electrodes: an upper electrode 7 and a lower electrode 2, a photoelectric conversion layer 4 located between the upper electrode 7 and the lower electrode 2, a charge injection layer 105 located between the upper electrode 7 and the photoelectric conversion layer 4, and a hole blocking layer 103 located between the lower electrode 2 and the photoelectric conversion layer 4. Note that photoelectric conversion element 110 does not necessarily have to include hole blocking layer 103.

[0084] The charge injection layer 105 is identical to the charge injection layer 5 in that it has a first layer 6A and a second layer 6B, but the positions of the first layer 6A and the second layer 6B are swapped with those of the charge injection layer 5. In the photoelectric conversion element 110, the second layer 6B is located between the first layer 6A and the photoelectric conversion layer 4. The first layer 6A is in contact with the upper electrode 7, for example. The second layer 6B is in contact with the photoelectric conversion layer 4, for example.

[0085] The hole-blocking layer 103 is provided to reduce dark current caused by holes injected from the lower electrode 2, and suppresses holes from being injected from the lower electrode 2 into the photoelectric conversion layer 4. This reduces noise signals that adversely affect the S / N ratio. As shown in Figure 6, in order to suppress holes from being injected from the lower electrode 2 into the photoelectric conversion layer 4, the ionization potential of the material of the hole-blocking layer 103 is greater than the work function of the lower electrode 2 and the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4.

[0086] 6 , the electron affinity of the hole-blocking layer 103 is smaller than the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4. The ionization potential of the hole-blocking layer 103 is larger than the ionization potential of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4.

[0087] The hole-blocking layer 103 may be made of the semiconductor material exemplified above as the acceptor semiconductor material or an electron-transporting organic compound.

[0088] As in the photoelectric conversion element 10, in the photoelectric conversion element 110, the ionization potential of the first layer 6A is greater than the ionization potential of the second layer 6B, and the electron affinity of the first layer 6A is greater than the electron affinity of the second layer 6B. Furthermore, the difference ΔE1 between the electron affinity of the first layer 6A and the ionization potential of the second layer 6B is smaller than the difference ΔE2 between the electron affinity of the acceptor organic semiconductor material 4B and the ionization potential of the donor organic semiconductor material 4A. This facilitates hole injection from the charge injection layer 105 to the photoelectric conversion layer 4.

[0089] The charge injection layer 105 may also function as an electron blocking layer to reduce dark current caused by electron injection from the upper electrode 7. This can reduce noise signals that adversely affect the S / N ratio. To prevent electrons from being injected from the upper electrode 7 into the photoelectric conversion layer 4, the electron affinity of at least the material of the second layer 6B is smaller than the work function of the upper electrode 7 and the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4. In FIG. 6 , the electron affinity of the first layer 6A is larger than the electron affinity of the donor organic semiconductor material 4A of the photoelectric conversion layer 4, but is not limited thereto and may be smaller than the electron affinity of the donor organic semiconductor material 4A of the photoelectric conversion layer 4.

[0090] In this specification, when the signal charges are electrons, a voltage applied between the upper electrode 7 and the lower electrode 2 such that the potential of the upper electrode 7 is lower than the potential of the lower electrode 2 is referred to as a reverse bias, or so-called reverse bias voltage. Also, in this specification, when the signal charges are electrons, a voltage applied between the upper electrode 7 and the lower electrode 2 such that the potential of the upper electrode 7 is higher than the potential of the lower electrode 2 is referred to as a forward bias, or so-called forward bias voltage. Therefore, even if the bias voltages are in the same direction, the polarities are reversed between the photoelectric conversion element 10 and the photoelectric conversion element 110.

[0091] In the photoelectric conversion mode of the photoelectric conversion element 110, when light is incident on the photoelectric conversion layer 4, pairs of electrons and holes are generated in the photoelectric conversion layer 4, and of the generated pairs of electrons and holes, the electrons which are signal charges move to the lower electrode 2, while the holes which are charges of the opposite polarity to the signal charges move to the upper electrode 7. Thereafter, in the signal readout mode, a signal based on the electrons accumulated in the charge accumulation node is read out via the lower electrode 2.

[0092] In this case, when electrons move from the photoelectric conversion layer 4 to the lower electrode 2 in the photoelectric conversion mode, they may not be able to move to the lower electrode 2 within the photoelectric conversion mode time and may remain in the photoelectric conversion layer 4 during the signal readout mode. Therefore, if the electrons remaining in the photoelectric conversion layer 4 move to the lower electrode 2 after the transition from the photoelectric conversion mode to the signal readout mode, they may appear as parasitic sensitivity, an unintended sensitivity that may cause noise. In the photoelectric conversion element 110, thermal electron excitation at the interface between the first layer 6A and the second layer 6B tends to cause holes to exist in the second layer 6B. These holes move toward the lower electrode 2 and recombine with electrons remaining in the photoelectric conversion layer 4. As a result, the movement of electrons remaining in the photoelectric conversion layer 4 to the lower electrode 2 during the signal readout mode is suppressed. This reduces the parasitic sensitivity caused by electrons remaining in the photoelectric conversion layer 4. In particular, by positioning the second layer 6B between the first layer 6A and the photoelectric conversion layer 4, the first layer 6A does not act as a barrier to the movement of holes to the photoelectric conversion layer 4, and therefore the holes present in the second layer 6B are more likely to move to the photoelectric conversion layer 4. Note that even when the first layer 6A is positioned between the second layer 6B and the photoelectric conversion layer 4, the holes present in the second layer 6B can still move to the photoelectric conversion layer 4, and therefore the effect of suppressing parasitic sensitivity can be obtained.

[0093] [Imaging Device] Next, an imaging device using the photoelectric conversion element according to this embodiment will be described with reference to Figures 7 and 8. Figure 7 is a diagram showing an example of the circuit configuration of an imaging device 100 that implements a photoelectric conversion unit 10A using the photoelectric conversion element 10 shown in Figure 1. Figure 8 is a schematic cross-sectional view showing an example of the device structure of a pixel 24 in the imaging device 100 according to this embodiment. Figure 7 representatively shows the lower electrode 2, photoelectric conversion layer 4, and upper electrode 7 of the configuration of the photoelectric conversion unit 10A, and omits the electron blocking layer 3 and charge injection layer 5.

[0094] As shown in FIGS. 7 and 8 , the imaging device 100 according to this embodiment includes a semiconductor substrate 40, a charge detection circuit 35 provided on the semiconductor substrate 40, a photoelectric conversion unit 10A provided on the semiconductor substrate 40, and a plurality of pixels 24, each including a charge storage node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion units 10A of the plurality of pixels 24 are configured with the photoelectric conversion elements 10 described above. That is, each of the plurality of pixels 24 includes a photoelectric conversion unit 10A including an upper electrode 7, a lower electrode 2, a photoelectric conversion layer 4, a charge injection layer 5, and an electron blocking layer 3. In this embodiment, the charge storage node 34 is an example of a charge storage region. Below, a case will be described in which the photoelectric conversion unit 10A has the same configuration as the photoelectric conversion element 10, and the signal charge is a hole. It should be noted that the photoelectric conversion unit 10A may also have the same configuration as the photoelectric conversion element 110, and the signal charge may be an electron.

[0095] The charge accumulation node 34 accumulates the signal charge generated by the photoelectric conversion unit 10A, and the charge detection circuit 35 detects the signal charge accumulated in the charge accumulation node 34. The charge detection circuit 35 provided on the semiconductor substrate 40 may be provided on the semiconductor substrate 40 or may be provided directly in the semiconductor substrate 40.

[0096] As shown in Fig. 7, the imaging device 100 includes a plurality of pixels 24 and peripheral circuits. The imaging device 100 is an image sensor realized by a single-chip integrated circuit, and includes a pixel array PA including a plurality of pixels 24 arranged two-dimensionally. The imaging device 100 is, for example, an imaging device that operates using a global shutter system in which the exposure periods of all of the plurality of pixels 24 are unified. In other words, the imaging device 100 has a global shutter function. Details of the exposure period will be described later.

[0097] A plurality of pixels 24 are arranged two-dimensionally, i.e., in row and column directions, on the semiconductor substrate 40 to form a photosensitive region, which is a pixel region. FIG. 7 shows an example in which the pixels 24 are arranged in a matrix of two rows and two columns. For convenience of illustration, FIG. 7 omits the illustration of a circuit (e.g., a pixel electrode control circuit) for individually setting the sensitivity of the pixels 24. The imaging device 100 may also be a line sensor. In this case, the plurality of pixels 24 may be arranged one-dimensionally. In this specification, the row direction refers to the direction extending along the rows, and the column direction refers to the direction extending along the columns. In this specification, the horizontal direction refers to the row direction, and the vertical direction refers to the column direction.

[0098] 7 and 8, each pixel 24 includes a photoelectric conversion unit 10A and a charge storage node 34 electrically connected to a charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0099] The photoelectric conversion unit 10A includes a lower electrode 2 provided as a pixel electrode and an upper electrode 7 provided as a counter electrode. A voltage for applying a predetermined bias voltage is supplied to the upper electrode 7 via a counter electrode signal line 26.

[0100] The lower electrode 2 is connected to the gate electrode 21G of the amplification transistor 21, and the signal charges collected by the lower electrode 2 are stored in a charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplification transistor 21. The charge storage node 34 is electrically connected to the lower electrode 2 and stores holes, which are signal charges generated in the photoelectric conversion layer 4.

[0101] A voltage corresponding to the amount of signal charge stored in the charge storage node 34 is applied to the gate electrode 21G of the amplifier transistor 21. The amplifier transistor 21 amplifies this voltage, and the amplified voltage is selectively read out as a signal voltage by the address transistor 23. The reset transistor 22 has its source / drain electrodes connected to the lower electrode 2 via the charge storage node 34, and resets the signal charge stored in the charge storage node 34. In other words, the reset transistor 22 resets the potentials of the gate electrode 21G of the amplifier transistor 21 and the lower electrode 2.

[0102] In order to selectively perform the above-described operations in the plurality of pixels 24, the imaging device 100 has a power supply wiring 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, which are connected to each pixel 24. Specifically, the power supply wiring 31 is connected to the source / drain electrode of the amplification transistor 21, and the vertical signal line 27 is connected to the source / drain electrode of the address transistor 23. The address signal line 36 is connected to the gate electrode 23G of the address transistor 23. The reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0103] The peripheral circuits include a voltage supply circuit 19 , a vertical scanning circuit 25 , a horizontal signal readout circuit 20 , a plurality of column signal processing circuits 29 , a plurality of load circuits 28 , and a plurality of differential amplifiers 32 .

[0104] The voltage supply circuit 19 is electrically connected to the upper electrode 7 via the counter electrode signal line 26. The voltage supply circuit 19 applies a voltage to the upper electrode 7, thereby creating a potential difference between the upper electrode 7 and the lower electrode 2. For example, the voltage supply circuit 19 supplies a first voltage to the upper electrode 7 during a first period such as an exposure period described below, and supplies a second voltage different from the first voltage during a second period such as a non-exposure period different from the first period.

[0105] The vertical scanning circuit 25 is connected to address signal lines 36 and reset signal lines 37, and selects the multiple pixels 24 arranged in each row on a row-by-row basis to read out the signal voltage and reset the potential of the lower electrode 2. A power supply wiring 31, which is a source follower power supply, supplies a predetermined power supply voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to multiple column signal processing circuits 29. The column signal processing circuits 29 are electrically connected to the pixels 24 arranged in each column via vertical signal lines 27 corresponding to each column. A load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplification transistor 21 form a source follower circuit.

[0106] A plurality of differential amplifiers 32 are provided corresponding to each column. The negative input terminals of the differential amplifiers 32 are connected to the corresponding vertical signal lines 27. The output terminals of the differential amplifiers 32 are connected to the pixels 24 via feedback lines 33 corresponding to each column.

[0107] The vertical scanning circuit 25 applies a row selection signal, which controls the on / off of the address transistor 23, to the gate electrode 23G of the address transistor 23 via the address signal line 36. This scans and selects the row to be read out. A signal voltage is read out from the pixels 24 in the selected row to the vertical signal line 27. The vertical scanning circuit 25 also applies a reset signal, which controls the on / off of the reset transistor 22, to the gate electrode 22G of the reset transistor 22 via the reset signal line 37. This selects the row of pixels 24 to be subjected to the reset operation. The vertical signal line 27 transmits the signal voltage read out from the pixel 24 selected by the vertical scanning circuit 25 to the column signal processing circuit 29.

[0108] The column signal processing circuit 29 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

[0109] The horizontal signal readout circuit 20 sequentially reads out signals from the plurality of column signal processing circuits 29 to a horizontal common signal line.

[0110] The differential amplifier 32 is connected to the drain electrode of the reset transistor 22 via a feedback line 33. Therefore, the differential amplifier 32 receives the output value of the address transistor 23 at its negative terminal. The differential amplifier 32 performs a feedback operation so that the gate potential of the amplifying transistor 21 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 32 is 0 V or a positive voltage close to 0 V. The feedback voltage means the output voltage of the differential amplifier 32.

[0111] As shown in FIG. 8, the pixel 24 includes a semiconductor substrate 40, a charge detection circuit 35, a photoelectric conversion unit 10A, and a charge storage node 34 (see FIG. 7).

[0112] The semiconductor substrate 40 may be an insulating substrate having a semiconductor layer formed on the surface on which the photosensitive region is formed, such as a p-type silicon substrate. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S and an element isolation region 41 for electrical isolation between the pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the element isolation region 41 is provided between the impurity region 21D and the impurity region 22D. This suppresses leakage of signal charge accumulated in the charge storage node 34. The element isolation region 41 is formed, for example, by implanting acceptor ions under predetermined implantation conditions.

[0113] The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed in the semiconductor substrate 40. As shown in FIG. 8 , the amplifier transistor 21 includes the impurity region 21S, the impurity region 21D, and the gate electrode 21G. The impurity region 21S and the impurity region 21D function as, for example, a source region and a drain region, respectively, of the amplifier transistor 21. A channel region of the amplifier transistor 21 is formed between the impurity region 21S and the impurity region 21D.

[0114] Similarly, the address transistor 23 includes an impurity region 23S, an impurity region 21S, and a gate electrode 23G connected to an address signal line 36. In this example, the amplifier transistor 21 and the address transistor 23 are electrically connected to each other by sharing the impurity region 21S. The impurity region 23S functions as, for example, a source region of the address transistor 23. The impurity region 23S is connected to the vertical signal line 27 shown in FIG. 7 .

[0115] The reset transistor 22 includes impurity regions 22D and 22S and a gate electrode 22G connected to a reset signal line 37. The impurity region 22S functions as, for example, a source region of the reset transistor 22. The impurity region 22S is connected to the reset signal line 37 shown in FIG.

[0116] An interlayer insulating layer 50 is stacked on the semiconductor substrate 40 so as to cover the amplifier transistor 21, the address transistor 23, and the reset transistor 22. For ease of viewing, hatching indicating a cross section of the interlayer insulating layer 50 is omitted in FIG.

[0117] A wiring layer (not shown) may be disposed in the interlayer insulating layer 50. The wiring layer may be formed of a metal such as copper, and may include, as a part thereof, wiring such as the above-mentioned vertical signal line 27. The number of insulating layers in the interlayer insulating layer 50 and the number of layers included in the wiring layer disposed in the interlayer insulating layer 50 may be set arbitrarily.

[0118] In the interlayer insulating layer 50, there are arranged a contact plug 53 connected to the gate electrode 21G of the amplifier transistor 21, a contact plug 54 connected to the impurity region 22D of the reset transistor 22, a contact plug 51 connected to the lower electrode 2, and a wiring 52 connecting the contact plug 51, the contact plug 54, and the contact plug 53. As a result, the impurity region 22D of the reset transistor 22 is electrically connected to the gate electrode 21G of the amplifier transistor 21. In the configuration illustrated in FIG. 8 , the contact plugs 51, 53, and 54, the wiring 52, the gate electrode 21G of the amplifier transistor 21, and the impurity region 22D of the reset transistor 22 form at least a part of the charge storage node 34.

[0119] The charge detection circuit 35 detects the signal charge captured by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23, and is formed on a semiconductor substrate 40.

[0120] The amplification transistor 21 is formed in a semiconductor substrate 40 and includes an impurity region 21D and an impurity region 21S that function as a drain electrode and a source electrode, respectively, a gate insulating layer 21X formed on the semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X.

[0121] The reset transistor 22 is formed in a semiconductor substrate 40 and includes an impurity region 22D and an impurity region 22S that function as a drain electrode and a source electrode, respectively, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X.

[0122] The address transistor 23 is formed in a semiconductor substrate 40 and includes impurity regions 21S and 23S that function as a drain electrode and a source electrode, respectively, a gate insulating layer 23X formed on the semiconductor substrate 40, and a gate electrode 23G formed on the gate insulating layer 23X. The impurity region 21S is connected in series to the amplifier transistor 21 and the address transistor 23.

[0123] The above-described photoelectric conversion unit 10A is disposed on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on a semiconductor substrate 40. The plurality of pixels 24 arranged two-dimensionally on the semiconductor substrate 40 form a photosensitive region. The distance between two connected pixels 24 (i.e., pixel pitch) may be, for example, approximately 2 μm.

[0124] A color filter 60 is formed above the photoelectric conversion unit 10A, and a microlens 61 is formed above the color filter 60. The color filter 60 is formed, for example, as an on-chip color filter by patterning, and is made of a photosensitive resin in which a dye or a pigment is dispersed. The microlens 61 is formed, for example, as an on-chip microlens, and is made of an ultraviolet-sensitive material.

[0125] A general semiconductor manufacturing process can be used to manufacture the imaging device 100. In particular, when a silicon substrate is used as the semiconductor substrate 40, the imaging device 100 can be manufactured using various silicon semiconductor processes.

[0126] [Operation of the Imaging Device] Next, the operation of the imaging device 100 will be described with reference to Figures 9 and 10. Here, the operation of the imaging device 100 when holes are used as signal charges as described above will be described.

[0127] 9 is a diagram showing a part of a schematic circuit configuration of a pixel 24. For ease of explanation, one end of the charge storage node 34 is grounded and the potential is zero. This state corresponds to the case where the feedback line 33 shown in FIG. 7 is set to 0 V, for example. In this state, if the voltage of the charge storage node 34 is Vc, then Vc is zero.

[0128] The voltage supply circuit 19 shown in FIG. 7 supplies different voltages to the upper electrode 7 via the counter electrode signal line 26 between an exposure period, which is an example of a first period, and a non-exposure period, which is an example of a second period. In this specification, the term "exposure period" refers to a period during which one of electrons and holes generated by photoelectric conversion is accumulated in the charge accumulation node 34 as signal charge. In other words, the "exposure period" may also be referred to as a "charge accumulation period." In this specification, a period other than the exposure period during operation of the imaging device 100 is referred to as a "non-exposure period." The "non-exposure period" may be a period during which light is blocked from entering the photoelectric conversion unit 10A, or a period during which light is irradiated onto the photoelectric conversion unit 10A but charge is not substantially accumulated in the charge accumulation node 34.

[0129] For example, when the imaging device 100 is driven, a bias voltage in a first voltage range or a second voltage range is applied to the photoelectric conversion unit 10A.

[0130] The first voltage range is a voltage range in which the dependency of the current change in the photoelectric conversion layer 4 on the bias voltage applied between the lower electrode 2 and the upper electrode 7 and on the amount of light incident on the photoelectric conversion layer 4 is smaller than that in the second voltage range. In other words, in the first voltage range, it can be considered that the difference between the current value that flows when light is incident on the photoelectric conversion layer 4 and the current value that flows when no light is incident is small. In the first voltage range, even if hole-electron pairs are generated by the incidence of light on the photoelectric conversion layer 4, the absolute value of the voltage applied between the lower electrode 2 and the upper electrode 7 is not large, so that the holes and electrons are likely to recombine before they separate. The first voltage range includes, for example, a forward bias voltage range.

[0131] The second voltage range is a reverse bias voltage range in which the current value increases as the amount of light incident on the photoelectric conversion layer 4 and the bias voltage applied between the lower electrode 2 and the upper electrode 7 increase.

[0132] In the initial state, the potential difference between the lower electrode 2 and the upper electrode 7 of the photoelectric conversion unit 10A, i.e., the bias voltage applied to the photoelectric conversion layer 4, the electron blocking layer 3, and the charge injection layer 5, is set to a value within a first voltage range. For example, the voltage supply circuit 19 supplies a voltage equal to the voltage of the lower electrode 2 to the upper electrode 7 using the counter electrode signal line 26. Here, let V2 be the voltage supplied to the upper electrode 7, and V2 be the reference voltage Vref. In this case, let Vo be the bias voltage applied to the photoelectric conversion unit 10A, and therefore Vo=V2-Vc, and therefore Vo=0.

[0133] Next, the operation during the exposure period will be described. At the start of the exposure period, the voltage supply circuit 19 supplies a voltage V2 to the upper electrode 7 using the counter electrode signal line 26 so that a bias voltage within the second voltage range, i.e., a reverse bias voltage, is applied to the photoelectric conversion unit 10A. In other words, during the exposure period, the voltage supply circuit 19 supplies the upper electrode 7 with a voltage V2 that generates photoelectric conversion sensitivity in the photoelectric conversion layer 4. The voltage V2 supplied by the voltage supply circuit 19 during the exposure period is an example of a first voltage. For example, when the photoelectric conversion layer 4 is made of an organic semiconductor material, the voltage V2 is a voltage of several volts to approximately 10 volts. As a result, holes are accumulated as signal charges in the charge storage node 34 of each pixel 24, in an amount corresponding to the amount of light incident on the photoelectric conversion layer 4.

[0134] Next, the operation during the non-exposure period will be described. After the exposure period ends, the voltage supply circuit 19 supplies a voltage V2 to the upper electrode 7 using the counter electrode signal line 26 so that a voltage within the first voltage range is applied to the photoelectric conversion unit 10A. That is, during the non-exposure period, the voltage supply circuit 19 supplies the upper electrode 7 with a voltage V2 that recombines electrons and holes in the photoelectric conversion layer 4. The voltage V2 supplied by the voltage supply circuit 19 during the non-exposure period is an example of a second voltage. For example, the voltage V2 supplied to the upper electrode 7 is set to a reference voltage Vref. Holes corresponding to the amount of light incident on the photoelectric conversion layer 4 during the exposure period are accumulated in the charge storage node 34 of each pixel 24, and the value of Vc differs depending on the pixel 24. Since Vo = V2 - Vc, Vo is also zero for pixels 24 that are not exposed and whose Vc remains unchanged. However, for pixels 24 whose Vc has changed, Vo is not zero but becomes a forward bias voltage.

[0135] When the voltage V2 in the first voltage range is supplied to the upper electrode 7, holes are less likely to move to the charge storage node 34 even when light is incident on the pixel 24. In other words, the voltage supply circuit 19 supplies a voltage to the upper electrode 7 so that the photoelectric conversion efficiency of the plurality of pixels 24, specifically the photoelectric conversion unit 10A, differs between the exposure period and the non-exposure period. Furthermore, when the voltage V2 in the first voltage range is supplied to the upper electrode 7, holes stored in the charge storage node 34 are less likely to be discharged to the lower electrode 2, and charges supplied from the voltage supply circuit 19 via the lower electrode 2 are less likely to flow into the charge storage node 34.

[0136] Therefore, the holes accumulated in the charge storage node 34 of each pixel 24 are maintained at an amount corresponding to the amount of light incident on the photoelectric conversion layer 4. In other words, the holes accumulated in the charge storage node 34 of each pixel 24 can be maintained even if light is again incident on the photoelectric conversion layer 4, as long as the holes in the charge storage node 34 are not reset. Therefore, even when a readout operation is performed sequentially for each row during a non-exposure period, new holes are unlikely to accumulate in the charge storage node 34 during the readout operation. Therefore, for example, a global shutter function can be realized with a simple pixel circuit such as the pixel 24 without requiring a transfer transistor and an additional storage capacitor. Therefore, for example, rolling distortion, which occurs in a rolling shutter, does not occur. Because the pixel circuit is simple, the imaging device 100 can advantageously miniaturize the pixels 24. Furthermore, in the imaging device 100, even if holes generated in the photoelectric conversion layer 4 during the exposure period remain during the non-exposure period, the presence of the charge injection layer 5 promotes recombination of the remaining holes and electrons, thereby suppressing the occurrence of parasitic sensitivity.

[0137] 10 is a timing chart showing an example of the voltage V2 supplied to the upper electrode 7 of the photoelectric conversion unit 10A and the timing of operations in each row of the pixel array PA of the image pickup device 100. For ease of understanding, FIG. 10 only shows the change in voltage V2 and the timing of exposure and signal readout for each row of the pixel array PA indicated by R0 to R7. In the image pickup device 100, during the non-exposure period N, the voltage supply circuit 19 supplies the upper electrode 7 with a voltage Vb as the voltage V2 that causes the bias voltage Vo to fall within a first voltage range, and during the exposure period E, it supplies a voltage Va as the voltage V2 that causes the bias voltage Vo to fall within a second voltage range.

[0138] As shown in FIG. 10 , during the non-exposure period N, signal readout R of the pixels 24 in each row R0 to R7 is performed sequentially. As described above, during the non-exposure period N, the bias voltage Vo is in the second voltage range, making it difficult for new holes to accumulate in the charge storage node 34 during the readout operation. Furthermore, the presence of the charge injection layer 5 promotes recombination of remaining holes and electrons, thereby suppressing the occurrence of parasitic sensitivity. Furthermore, the start and end timings of the exposure period E are consistent for the pixels 24 in all rows R0 to R7. In other words, the imaging device 100 realizes a global shutter function in which all rows of the pixel array PA are simultaneously exposed while sequentially reading out signals from the pixels 24 in each row.

[0139] As described above, according to this embodiment, it is possible to provide the imaging device 100 that can reduce the parasitic sensitivity.

[0140] The operation of the imaging device 100 is not limited to the above example, and for example, the imaging device 100 may perform an operation that realizes an electronic ND (Neutral Density) filter function that adjusts the sensitivity of photoelectric conversion.

[0141] For example, during the exposure period E in Figure 10, the voltage supply circuit 19 supplies, as voltage V2, instead of voltage Va, to the upper electrode 7 a voltage equivalent to an ND value, which is a predetermined sensitivity reduction factor, based on the relationship between the bias voltage and the current value at that voltage (i.e., the amount of holes generated in the photoelectric conversion layer 4 that are extracted), thereby realizing the electronic ND filter function of the imaging device 100.

[0142] FIG. 11 is a timing chart showing an example of an operation of adjusting the photoelectric conversion sensitivity using a pulse duty control method in the imaging device 100. As shown in FIG. 11 , the voltage supply circuit 19 supplies a pulsed voltage that alternates between the voltages Va and Vb during the exposure period E, for example. Thus, the first period during which the voltage supply circuit 19 supplies the voltage Va, which is an example of the first voltage, and the second period during which the voltage supply circuit 19 supplies the voltage Vb, which is an example of the second voltage, may be included in the exposure period E within the same frame. In this case, the voltage supply circuit 19 supplies a voltage to the upper electrode 7 with a duty ratio of the pulsed voltage that alternates between the voltages Va and Vb, which corresponds to a predetermined ND value. This also allows the imaging device 100 to achieve its electronic ND filter function. In this case, during the second period during the exposure period E during which the voltage Vb is applied to the upper electrode 7, parasitic sensitivity is reduced, similar to the non-exposure period N described above, making it easier to accurately achieve the set ND value.

[0143] In this way, even if the imaging device 100 has an electronic ND filter function, the parasitic sensitivity of the imaging device 100 is reduced as described above, and therefore the imaging device 100 can achieve imaging with less noise.

[0144] The photoelectric conversion element according to the present disclosure will be specifically described below in examples, but the present disclosure is not limited to the following examples. In detail, a photoelectric conversion element according to an embodiment of the present disclosure and a photoelectric conversion element for characteristic comparison were fabricated, and the parasitic sensitivity was evaluated.

[0145] (Fabrication of Photoelectric Conversion Elements) Photoelectric conversion elements in Examples and Comparative Examples were fabricated.

[0146] A glass substrate having an ITO film formed thereon was used as a support substrate. The ITO film was used as the lower electrode 2, and an electron-blocking layer 3 was formed on the lower electrode 2 by vacuum deposition of 9,9'-[1,1'-biphenyl]-4,4'-diylbis[3,6-bis(1,1-dimethylethyl)]-9H-carbazole (tBu-CBP).

[0147] Next, on the electron blocking layer 3, a photoelectric conversion layer 4 was formed by co-depositing, by vacuum deposition, a donor organic semiconductor material, subphthalocyanine, and an acceptor organic semiconductor material, C60 fullerene, at a weight ratio of 1:3. The photoelectric conversion layer 4 thus obtained had a thickness of approximately 400 nm. The subphthalocyanine used was boron subphthalocyanine chloride (SubPc), which has boron (B) as the central metal and in which chloride ions are coordinated to the B as ligands.

[0148] Next, a 10 nm thick film of C60 fullerene was formed on the photoelectric conversion layer 4 by vacuum deposition through a metal shadow mask as the material for the first layer 6A of the charge injection layer 5. Furthermore, a 10 nm thick film of SubPc was formed on the first layer 6A as the material for the second layer 6B of the charge injection layer 5.

[0149] Next, an ITO film was formed as the upper electrode 7 on the second layer 6B of the charge injection layer 5 by a sputtering method to a thickness of 30 nm, and then an Al film was formed as a sealing film. ２ O ３ The film was formed on the upper electrode 7 by atomic layer deposition, thereby obtaining the photoelectric conversion element of the example.

[0150] Comparative Example A photoelectric conversion element according to a comparative example was produced in the same manner as in the example, except that the first layer 6A was not formed.

[0151] (Measurement of Ionization Potential and Electron Affinity of Materials) The ionization potential and electron affinity of each material used in the examples and comparative examples were measured.

[0152] In measuring the ionization potential, first, a sample was prepared by forming a film of each material used in the examples and comparative examples on a glass substrate on which an ITO film had been formed. Next, for the prepared sample, the number of photoelectrons was measured using an atmospheric photoelectron spectrometer (AC-3, manufactured by Riken Keiki) while changing the energy of ultraviolet irradiation, and the energy position at which photoelectrons began to be detected was taken as the ionization potential.

[0153] In measuring the electron affinity, first, a sample was prepared by depositing each material used in the examples and comparative examples on a quartz substrate. Next, the absorption spectrum of the prepared sample was measured using a spectrophotometer (U4100, manufactured by Hitachi High-Technologies Corporation), and the optical band gap was calculated from the absorption edge of the obtained absorption spectrum. The electron affinity was estimated by subtracting the ionization potential obtained by the above ionization potential measurement from the calculated optical band gap.

[0154] Table 1 shows the ionization potential and electron affinity of each material used in the examples and comparative examples.

[0155]

[0156] As shown in Table 1, in the photoelectric conversion element of the example, the electron affinity of the C60 fullerene constituting the first layer 6A of the charge injection layer 5 is 4.2 eV, and the ionization potential of the SubPc constituting the second layer 6B of the charge injection layer 5 is 5.5 eV, the difference between the two being 1.3 eV.

[0157] On the other hand, like the charge injection layer 5, the photoelectric conversion layer 4 also contains SubPc and C60 fullerene, but because each material in the bulk heterostructure mixed film is less susceptible to stabilization than a single-material film, the difference between the ionization potential and electron affinity of each material is larger than in a single-material film. Therefore, the difference between the electron affinity of C60 fullerene, which is the acceptor organic semiconductor material in the photoelectric conversion layer 4, and the ionization potential of SubPc, which is the donor organic semiconductor material, is larger than in the charge injection layer 5. In other words, the difference between the electron affinity of C60 fullerene, which is the acceptor organic semiconductor material in the photoelectric conversion layer 4, and the ionization potential of SubPc, which is the donor organic semiconductor material, is greater than 1.3 eV.

[0158] Therefore, in the photoelectric conversion element of the embodiment, the difference between the electron affinity of the first layer 6A and the ionization potential of the second layer 6B is smaller than the difference between the electron affinity of the acceptor organic semiconductor material and the ionization potential of the donor organic semiconductor material in the photoelectric conversion layer 4.

[0159] The ionization potential of the C60 fullerene constituting the first layer 6A is greater than the ionization potential of the SubPc constituting the second layer 6B, and the electron affinity of the C60 fullerene constituting the first layer 6A is greater than the electron affinity of the SubPc constituting the second layer 6B.

[0160] In the photoelectric conversion element in the examples, the materials of the first layer 6A and the second layer 6B in the charge injection layer 5 and the donor organic semiconductor material and the acceptor organic semiconductor material contained in the photoelectric conversion layer 4 were the same, but they may be different as long as they are materials that satisfy the above-mentioned energy magnitude relationship.

[0161] (Evaluation of Parasitic Sensitivity) To evaluate the parasitic sensitivity of the photoelectric conversion elements in the examples and comparative examples, the current density was measured under light conditions (under 1000 lx illumination) and in the dark. A semiconductor device parameter analyzer (B1500A, manufactured by Keysight Technologies) was used to measure the current density. Specifically, the bias voltage applied between a pair of electrodes of the photoelectric conversion element, i.e., between the upper electrode 7 and the lower electrode 2, was changed, and the current-voltage characteristics were measured under light conditions and in the dark.

[0162] In addition, the reverse bias and forward bias of the bias voltage are defined as applying a negative voltage to the lower electrode 2 or a positive voltage to the upper electrode 7, and applying a positive voltage to the lower electrode 2 or a negative voltage to the upper electrode 7, respectively.

[0163] FIG. 12 shows the current density-voltage characteristics when a bias voltage is applied to the photoelectric conversion element of the example. Meanwhile, FIG. 13 shows the current density-voltage characteristics when a bias voltage is applied to the photoelectric conversion element of the comparative example. In FIGS. 12 and 13, the vertical axis is logarithmic and indicates the difference between the current density in the light state and the current density in the dark state. In addition, in FIGS. 12 and 13, the horizontal axis indicates voltage on the normal axis. In the voltage on this horizontal axis, the reverse bias voltage is a positive voltage, and the forward bias voltage is a negative voltage.

[0164] As shown in Figure 13, in the photoelectric conversion element in the comparative example, there is a difference in current density between dark and light conditions except for a very small bias voltage around 0 V, so it can be said that the parasitic sensitivity is large no matter what voltage is set in the non-exposure period, and there is almost no voltage that can be applied to the non-exposure period.

[0165] In contrast, as shown in Figure 12, in the photoelectric conversion element of the embodiment, there is almost no difference in current density between light and dark conditions over a wide range of bias voltages below 0 V, and by setting the voltage during the non-exposure period so that the bias voltage is within this voltage range, it is possible to reduce parasitic sensitivity.

[0166] As described above, in the photoelectric conversion element according to the present disclosure, like the photoelectric conversion element in the examples, the ionization potential of the first layer 6A is greater than the ionization potential of the second layer 6B, the electron affinity of the first layer 6A is greater than the electron affinity of the second layer 6B, and the difference between the electron affinity of the first layer 6A and the ionization potential of the second layer 6B is smaller than the difference between the electron affinity of the acceptor organic semiconductor material and the ionization potential of the donor organic semiconductor material, and therefore it has been confirmed that the difference in current density between light and dark conditions is reduced, and the effect of reducing parasitic sensitivity can be obtained.

[0167] While the photoelectric conversion element and imaging device according to the present disclosure have been described above based on the embodiments and examples, the present disclosure is not limited to these embodiments and examples. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments and examples, as well as other forms constructed by combining some of the components of the embodiments and examples, are also included within the scope of the present disclosure.

[0168] The photoelectric conversion element according to the present disclosure can be applied to imaging devices, optical sensors, photodetectors, etc. Furthermore, the imaging device according to the present disclosure can be applied to various camera systems and sensor systems, such as medical cameras, surveillance cameras, vehicle-mounted cameras, distance measuring cameras, microscope cameras, drone cameras, and robot cameras.

[0169] REFERENCE SIGNS LIST 1 Support substrate 2 Lower electrode 3 Electron blocking layer 4 Photoelectric conversion layer 4A Donor organic semiconductor material 4B Acceptor organic semiconductor material 5, 105 Charge injection layer 6A First layer 6B Second layer 7 Upper electrode 10, 110 Photoelectric conversion element 10A Photoelectric conversion section 19 Voltage supply circuit 20 Horizontal signal readout circuit 21 Amplifying transistor 22 Reset transistor 23 Address transistor 21D, 21S, 22D, 22S, 23S Impurity region 21G, 22G, 23G Gate electrode 21X, 22X, 23X Gate insulating layer 24 Pixel 25 Vertical scanning circuit 26 Counter electrode signal line 27 Vertical signal line 28 Load circuit 29 Column signal processing circuit 31 Power supply wiring 32 Differential amplifier 33 Feedback line 34 Charge storage node 35 Charge detection circuit 36 ​​Address signal line 37 Reset signal line 40 Semiconductor substrate 41 Element isolation region 50 Interlayer insulating layer 51, 53, 54 Contact plug 52 Wiring 60 Color filter 61 Microlens 100 Imaging device 103 Hole blocking layer

Claims

1. a photoelectric conversion layer containing a donor semiconductor material and an acceptor semiconductor material and converting light into signal charges; a first electrode for collecting the signal charges; a second electrode facing the first electrode with the photoelectric conversion layer interposed therebetween; a charge injection layer located between the second electrode and the photoelectric conversion layer, the charge injection layer includes a first layer and a second layer stacked on the first layer; an ionization potential of the first layer greater than an ionization potential of the second layer; the electron affinity of the first layer is greater than the electron affinity of the second layer; a difference between the electron affinity of the first layer and the ionization potential of the second layer is smaller than a difference between the electron affinity of the acceptor semiconductor material and the ionization potential of the donor semiconductor material; the signal charges are holes, the first layer is located between the second layer and the photoelectric conversion layer; Photoelectric conversion element.

2. further comprising an electron blocking layer located between the first electrode and the photoelectric conversion layer; The photoelectric conversion element according to claim 1 .

3. A photoelectric conversion layer containing a donor semiconductor material and an acceptor semiconductor material, which converts light into signal charges; a first electrode for collecting the signal charges; a second electrode facing the first electrode with the photoelectric conversion layer interposed therebetween; a charge injection layer located between the second electrode and the photoelectric conversion layer; Equipped with the charge injection layer includes a first layer and a second layer stacked on the first layer; an ionization potential of the first layer greater than an ionization potential of the second layer; the electron affinity of the first layer is greater than the electron affinity of the second layer; a difference between the electron affinity of the first layer and the ionization potential of the second layer is smaller than a difference between the electron affinity of the acceptor semiconductor material and the ionization potential of the donor semiconductor material; the signal charges are electrons, the second layer is located between the first layer and the photoelectric conversion layer; Photoelectric conversion element.

4. further comprising a hole blocking layer located between the first electrode and the photoelectric conversion layer; The photoelectric conversion element according to claim 3 .

5. the first layer contains the same material as the acceptor semiconductor material; The photoelectric conversion element according to claim 1 .

6. A photoelectric conversion layer containing a donor semiconductor material and an acceptor semiconductor material, which converts light into signal charges; a first electrode for collecting the signal charges; a second electrode facing the first electrode with the photoelectric conversion layer interposed therebetween; a charge injection layer located between the second electrode and the photoelectric conversion layer; Equipped with the charge injection layer includes a first layer and a second layer stacked on the first layer; an ionization potential of the first layer greater than an ionization potential of the second layer; the electron affinity of the first layer is greater than the electron affinity of the second layer; a difference between the electron affinity of the first layer and the ionization potential of the second layer is smaller than a difference between the electron affinity of the acceptor semiconductor material and the ionization potential of the donor semiconductor material; the second layer contains the same material as the donor semiconductor material; Photoelectric conversion element.

7. the photoelectric conversion layer is a mixed film containing the donor semiconductor material and the acceptor semiconductor material, the first layer contains the same material as the acceptor semiconductor material; The photoelectric conversion element according to claim 6 .

8. The photoelectric conversion element according to any one of claims 1 to 4, a charge accumulation region electrically connected to the first electrode and configured to accumulate the signal charges; Imaging device.

9. a voltage supply circuit electrically connected to the second electrode and applying a potential difference between the first electrode and the second electrode; the voltage supply circuit supplies a first voltage to the second electrode in a first period, and supplies a second voltage different from the first voltage to the second electrode in a second period different from the first period; The imaging device according to claim 8 .