Semiconductor device and method for manufacturing semiconductor device

Abstract

Generation of a high surge voltage is suppressed. This semiconductor device comprises: a trench provided from the upper surface of a base layer into a first impurity layer and further to the inside of a first pillar layer; a first gate electrode provided in the trench so as to be surrounded by a first insulating film; and a second gate electrode provided so as to be in contact with a collector layer sandwiched between a buffer layer and a second impurity layer via a second insulating film and so as not to reach the first pillar layer. The first pillar layer and a second pillar layer are alternately arranged side by side in a direction crossing the depth direction of the first pillar layer.

Description

Semiconductor device and method for manufacturing the same

[0001] The technology disclosed in this specification relates to semiconductor technology.

[0002] Some conventional semiconductor devices have a superjunction structure (a structure in which p-type columnar layers and n-type columnar layers are alternately arranged) in the drift region (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2002-26320

[0004] Conventional structures have a thin superjunction structure (voltage retention section), so when the recovery current is large, the voltage retention section can become completely depleted, resulting in a high surge voltage.

[0005] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology for suppressing the occurrence of high surge voltages in semiconductor devices having a superjunction structure.

[0006] a first conductivity type first pillar layer; a plurality of second conductivity type second pillar layers provided at a depth extending from an upper surface of the first pillar layer to within the first pillar layer; a first conductivity type first impurity layer provided on the upper surface of the first pillar layer; a second conductivity type base layer provided in a surface layer of the upper surface of the first impurity layer; a trench provided from the upper surface of the base layer to the first impurity layer and further to the inside of the first pillar layer; a first gate electrode provided in the trench and surrounded by a first insulating film; a first conductivity type source layer provided in a portion of the surface layer of the upper surface of the base layer and in contact with the first insulating film; an emitter electrode provided to cover the base layer, the source layer, and the first interlayer film; a buffer layer of a first conductivity type provided on a lower surface of the first pillar layer; a collector layer of a second conductivity type provided in a surface layer of the lower surface of the buffer layer; a second impurity layer of the first conductivity type provided in a part of the surface layer of the lower surface of the collector layer; a second gate electrode provided in contact with the collector layer sandwiched between the buffer layer and the second impurity layer via a second insulating film and not reaching the first pillar layer; a second interlayer film provided to cover the second gate electrode; and a collector electrode provided to cover the collector layer and the second interlayer film, wherein the first pillar layers and the second pillar layers are arranged alternately in a direction intersecting a depth direction of the first pillar layers.

[0007] According to at least the first aspect of the technique disclosed in the present specification, it is possible to suppress the occurrence of high surge voltages in a semiconductor device having a superjunction structure.

[0008] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below.

[0009] 1 is a plan view showing an example of the configuration of a semiconductor device according to an embodiment. It is a cross-sectional view showing an example of the configuration of the element region of the configuration shown in FIG. 1 taken along the line A-B. It is a cross-sectional view showing another example of the configuration of the element region of the configuration shown in FIG. 1 taken along the line A-B. It is a diagram conceptually showing an example of the configuration of a semiconductor device according to an embodiment. It is a diagram showing a state in which the semiconductor devices shown in FIG. 4 are connected in series. It is a diagram showing an example of distinguishing current modes when the current detected by the current detection means in FIG. 4 is determined by the current mode determination means. It is a diagram showing an example of gate signals for each current mode of the collector current. It is a diagram showing an example of how to determine a large current region and a small current region when the polarity of the collector current is positive. It is a diagram conceptually showing an example of the configuration of a semiconductor device according to an embodiment. It is a diagram showing an example of distinguishing voltage modes when the voltage detected by the voltage detection means in FIG. 9 is determined by the voltage mode determination means. It is a diagram showing an example of how to determine a large voltage region and a small voltage region when the polarity of the collector-emitter voltage is positive. It is a plan view showing an example of the configuration of a semiconductor device according to an embodiment. It is a cross-sectional view showing an example of the configuration of the element region and the termination region of the configuration shown in FIG. 12. It is a cross-sectional view showing a modified example of the configuration shown in FIG. 13. FIG. 14 is a cross-sectional view showing another modified example of the configuration shown in FIG. 13.

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0011] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0012] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0013] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0014] Furthermore, in the description of this specification, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to make it easier to understand the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0015] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0016] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude the interposition of another component "C" between A and B.

[0017] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0018] 1 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in the example in Fig. 1, the semiconductor device includes an element region 12 and a termination region 14 that surrounds the element region 12 in a plan view.

[0019] FIG. 2 is a cross-sectional view showing an example of the configuration of the element region 12 taken along the line AB in the configuration shown in FIG.

[0020] 2, the element region 12 includes an n-type pillar layer 22 and a plurality of p-type pillar layers 24 provided from the top surface of the n-type pillar layer 22 to a predetermined depth within the n-type pillar layer 22. Here, the structure in which the n-type pillar layers 22 and the p-type pillar layers 24 are alternately arranged in a direction perpendicular to the depth direction is also referred to as a breakdown voltage maintaining section.

[0021] The element region 12 also includes an n-type buffer layer 26 provided on the lower surface of the n-type pillar layer 22 and an emitter-side n-type layer 28 provided on the upper surface of the n-type pillar layer 22 .

[0022] The element region 12 also includes a p-type collector layer 30 provided on the surface layer on the lower surface side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper surface side of the emitter-side n-type layer 28.

[0023] The element region 12 also includes a trench 50 extending from the lower surface of the p-type collector layer 30 to the inside of the n-type buffer layer 26, and a trench 52 extending from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the inside of the n-type pillar layer 22. The trench 50 includes an insulating film 54 extending along the bottom and side surfaces of the trench 50, and a collector-side gate electrode 58 enclosed by the insulating film 54 within the trench 50. The trench 52 includes an insulating film 56 extending along the bottom and side surfaces of the trench 52, and an emitter-side gate electrode 60 enclosed by the insulating film 56 within the trench 52. The collector-side gate electrode 58 contacts, via the insulating film 54, the p-type collector layer 30 sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34. The collector-side gate electrode 58 is provided without reaching the n-type pillar layer 22.

[0024] The element region 12 also includes a collector-side n-type layer 34 provided in part of the surface layer on the lower surface of the p-type collector layer 30 and in contact with the insulating film 54, and an n-type source layer 36 provided in part of the surface layer on the upper surface of the p-type base layer 32 and in contact with the insulating film 56. Here, the n-type source layer 36, the p-type base layer 32, the insulating film 56, and the emitter-side gate electrode 60 are also collectively referred to as an emitter-side channel portion. The collector-side n-type layer 34, the p-type collector layer 30, the insulating film 54, and the collector-side gate electrode 58 are also collectively referred to as a collector-side channel portion.

[0025] The element region 12 also includes an interlayer film 38 provided to cover a portion of the collector-side n-type layer 34 and the collector-side gate electrode 58, a collector electrode 42 provided to cover the p-type collector layer 30, the collector-side n-type layer 34, and the interlayer film 38, an interlayer film 40 provided to cover a portion of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 provided to cover the p-type base layer 32, the n-type source layer 36, and the interlayer film 40.

[0026] The emitter-side n-type layer 28 is formed between the p-type base layer 32 and the breakdown voltage maintaining portion, and is shallower than the bottom of the emitter-side gate electrode 60. The breakdown voltage maintaining portion consisting of the n-type pillar layer 22 and the p-type pillar layer 24 is also called a superjunction structure.

[0027] The peak impurity concentration of the n-type source layer 36 is, for example, 1×10 １８ cm －３ or more, and 1 x 10 ２１ cm －３ The peak impurity concentration of the p-type base layer 32 is, for example, 1×10 １７ cm －３ is.

[0028] The peak impurity concentration of the emitter-side n-type layer 28 is, for example, 1×10 １５ cm －３ or more, and 1 x 10 １７ cm －３ The peak impurity concentration of the n-type buffer layer 26 is, for example, 1×10 １５ cm －３ or more, and 1 x 10１８ cm －３ The following is the result.

[0029] The peak impurity concentration of the p-type collector layer 30 is, for example, 1×10 １７ cm －３ or more, and 1 x 10 １９ cm －３ The peak impurity concentration of the collector-side n-type layer 34 is, for example, 1×10 １８ cm －３ or more, and 1 x 10 ２１ cm －３ The following is the result.

[0030] If the breakdown voltage maintaining section is made up of an n-type drift layer, the impurity concentration is 1×10 １４ cm －３ In the case of the superjunction structure described above, the impurity concentration of the n-type pillar layer 22 and the p-type pillar layer 24 is about 1×10 １５ cm －３ That's about it.

[0031] The repeating interval between the emitter-side gate electrodes 60 (emitter-side gate pitch) and the repeating interval between the collector-side gate electrodes 58 (collector-side gate pitch) do not have to be the same.

[0032] FIG. 3 is a cross-sectional view showing another example of the configuration of the element region 12 taken along the line AB in the configuration shown in FIG.

[0033] As shown in FIG. 3, the element region 12 includes an n-type pillar layer 22, a p-type pillar layer 24, an n-type buffer layer 26A provided on the lower surface of the n-type pillar layer 22, and an emitter-side n-type layer 28.

[0034] The element region 12 also includes a p-type collector layer 30A provided on a portion of the surface layer on the lower surface side of the n-type buffer layer 26A, a p-type base layer 32, and a trench 52. The trench 52 includes an insulating film 56 and an emitter-side gate electrode 60.

[0035] The element region 12 also includes a collector-side n-type layer 34A provided on a portion of the surface layer on the lower surface side of the p-type collector layer 30A, and an n-type source layer 36.

[0036] The element region 12 also includes an insulating film 54A covering a portion of the p-type collector layer 30A, the collector-side n-type layer 34A, and the exposed n-type buffer layer 26A, a collector-side gate electrode 58A covering the insulating film 54A, an interlayer film 38A covering the collector-side gate electrode 58A, a collector electrode 42 provided to cover the p-type collector layer 30A and the interlayer film 38A, an interlayer film 40, and an emitter electrode 44. The collector-side gate electrode 58A contacts, via the insulating film 54A, the p-type collector layer 30A sandwiched between the n-type buffer layer 26A and the collector-side n-type layer 34A. The collector-side gate electrode 58A is provided so as not to reach the n-type pillar layer 22.

[0037] In the reverse conducting state, a positive voltage is applied to the collector-side gate electrode 58, and the collector-side n-type layer 34 and the breakdown voltage holding portion are electrically connected in the collector-side channel portion.

[0038] In this case, when the emitter-side gate electrode 60 is turned on (a state in which a positive voltage is applied), unipolar operation occurs, and when the emitter-side gate electrode 60 is turned off (a state in which a positive voltage is not applied), bipolar operation occurs. Here, unipolar operation refers to an operation in which electrons pass from the collector-side n-type layer 34 through the channel, flow through the breakdown voltage holding portion, and reach the n-type source layer 36. Also, bipolar operation refers to an operation in which holes are injected from the p-type base layer 32 when electrons pass from the collector-side n-type layer 34 through the channel, flow through the breakdown voltage holding portion, and reach the p-type base layer 32.

[0039] In reverse recovery (hereinafter also referred to as recovery), which is the transition process from the reverse conducting state to the cutoff state, electrons are discharged into the collector-side n-type layer 34 and holes are discharged into the p-type base layer 32, and depletion layers spread from both sides of the breakdown voltage maintaining portion.

[0040] When the breakdown voltage holding portion is made thinner using the superjunction structure, it becomes easier for the breakdown voltage holding portion to become completely depleted during bipolar recovery. When the breakdown voltage holding portion becomes completely depleted, the recovery current is suddenly cut off, and if the breakdown voltage holding portion becomes completely depleted while a large recovery current is flowing, a large surge voltage occurs.

[0041] The emitter-side n-type layer 28 reduces hole injection from the p-type base layer 32 during bipolar reverse conduction, thereby reducing carrier accumulation on the emitter side. This promotes depletion from the emitter side during bipolar recovery. This in turn suppresses depletion from the collector side, preventing the generation of a large surge voltage due to complete depletion.

[0042] As described above, the semiconductor device according to this embodiment can avoid a large surge voltage during bipolar recovery, thereby allowing current to flow in both directions while suppressing electromagnetic noise or breakdown caused by the large surge voltage.

[0043] Second Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0044] <Configuration of the Semiconductor Device> Fig. 4 is a conceptual diagram illustrating an example of the configuration of a semiconductor device according to this embodiment. As shown in Fig. 4, the semiconductor device includes collector-side gate driver 102 for driving collector-side gate electrode 58 of Fig. 1, emitter-side gate driver 104 for driving emitter-side gate electrode 60 of Fig. 1, PWM (Pulse Width Modulation) control circuit 106 for outputting control signals to collector-side gate driver 102 and emitter-side gate driver 104, current detector 108 for detecting the collector current (load current), and current mode determiner 110 for determining the current mode based on the current value detected by current detector 108.

[0045] FIG. 5 is a diagram showing a state in which the semiconductor devices shown in FIG. 4 are connected in series.

[0046] FIG. 6 is a diagram showing an example of current mode discrimination when the current mode discrimination means 110 discriminates the current detected by the current detection means 108 in FIG.

[0047] 6, when the current detection means 108 detects a collector current with positive polarity, the current mode determination means 110 sets the emitter-side gate signal as a PWM control signal (i.e., a PWM control signal is output from the PWM control means 106 to the emitter-side gate drive means 104 based on the determination result of the current mode determination means 110). In this case, the current mode determination means 110 turns off the collector-side gate signal (i.e., the signal that drives the collector-side gate electrode 58) when the collector current value is larger than a predetermined threshold value, and turns on the collector-side gate signal when the collector current value is smaller than the predetermined threshold value.

[0048] 6, the current mode determination means 110 turns on the collector-side gate signal when the current detection means 108 detects a collector current with negative polarity. In this case, the current mode determination means 110 sets the emitter-side gate signal to a PWM control signal when the collector current value is smaller than a predetermined threshold value, and cuts off the PWM control signal and does not output the emitter-side gate signal when the collector current value is larger than the predetermined threshold value.

[0049] 7 is a diagram showing examples of gate signals for different collector current modes. As shown in the example in Fig. 7, when the collector current polarity is positive and the collector current value is large (i.e., in the large current region), the collector-side gate signal is turned off to achieve bipolar operation.

[0050] Also, as shown in the example in FIG. 7, when the collector current polarity is positive and the collector current is small (i.e., in the small current region), the collector side gate signal is turned on to achieve unipolar operation.

[0051] As shown in the example of FIG. 7, when the polarity of the collector current is negative and the collector current is small, the collector side gate signal is turned on to perform unipolar operation.

[0052] Also, as shown in the example in Figure 7, when the polarity of the collector current is negative and the collector current is large, the PWM control signal of the emitter side gate is cut off and the collector side gate signal is turned on, resulting in bipolar operation.

[0053] 8 is a diagram showing an example of how to determine the large current region and the small current region when the collector current polarity is positive. Fig. 8 shows the collector current X1 when the collector-side gate signal is turned on and the collector current X2 when the collector-side gate signal is turned off. In Fig. 8, the vertical axis represents the magnitude of the collector current, and the horizontal axis represents the magnitude of the voltage between the collector electrode and the emitter electrode.

[0054] 8, as the voltage between the collector electrode and the emitter electrode increases, both the collector current X1 and the collector current X2 increase. Furthermore, the collector current X2 is smaller than the collector current X1 in a range where the voltage between the collector electrode and the emitter electrode is small, and is larger than the collector current X1 in a range where the voltage between the collector electrode and the emitter electrode is large.

[0055] The value of the collector current at the timing when the magnitude relationship between the collector current X1 and the collector current X2 is reversed can be determined as the boundary value between the large current region and the small current region.

[0056] The collector current (polarity / large / small) during inverter operation transitions in the following order: (positive large), (positive small), (negative small), (negative large), (negative small), (positive small), (positive large), (positive small), ... However, the operating mode (current mode) remains the same before and after the polarity reversal of the collector current. Therefore, there is no need to detect the current when the polarity of the collector current is reversed (detecting that the current is 0 A).

[0057] As described above, according to the semiconductor device of this embodiment, there is no need to detect 0 A, which is difficult to detect due to noise.

[0058] Therefore, it is possible to prevent the semiconductor device from being destroyed due to erroneous detection of 0 A, while allowing current to flow in both directions through the semiconductor device.

[0059] Third Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0060] <Configuration of the Semiconductor Device> Fig. 9 is a conceptual diagram showing an example of the configuration of a semiconductor device according to this embodiment. As shown in Fig. 9, the semiconductor device includes collector-side gate drive means 102 for driving the collector-side gate electrode 58 of Fig. 1, emitter-side gate drive means 104 for driving the emitter-side gate electrode 60 of Fig. 1, PWM control means 106 for outputting control signals to the collector-side gate drive means 102 and the emitter-side gate drive means 104, voltage detection means 112 for detecting the collector-emitter voltage, and voltage mode determination means 114 for determining the voltage mode based on the voltage value detected by the voltage detection means 112.

[0061] The above semiconductor devices are connected in series as shown in FIG.

[0062] FIG. 10 is a diagram showing an example of how the voltage mode is distinguished when the voltage detected by the voltage detection means 112 in FIG. 9 is judged by the voltage mode judgment means 114. In FIG.

[0063] 10 , when the voltage detection means 112 detects a collector-emitter voltage with positive polarity, the voltage mode determination means 114 sets the emitter-side gate signal as a PWM control signal (i.e., a PWM control signal is output from the PWM control means 106 to the emitter-side gate drive means 104 based on the determination result of the voltage mode determination means 114). In this case, the voltage mode determination means 114 turns off the collector-side gate signal (i.e., the signal that drives the collector-side gate electrode 58) when the collector-emitter voltage is greater than a predetermined threshold, and turns on the collector-side gate signal when the collector current value is smaller than the predetermined threshold.

[0064] 10, the voltage mode determination means 114 turns on the collector-side gate signal when a collector current with negative polarity is detected by the voltage detection means 112. In this case, the voltage mode determination means 114 sets the emitter-side gate signal to a PWM control signal when the collector-emitter voltage is smaller than a predetermined threshold value, and cuts off the PWM control signal and does not output the emitter-side gate signal when the collector-emitter voltage is larger than the predetermined threshold value.

[0065] When the polarity of the collector-emitter voltage is positive and the collector-emitter voltage is large, the collector-side gate is turned off to achieve bipolar operation.

[0066] When the polarity of the collector-emitter voltage is positive and the collector-emitter voltage is small, the collector-side gate is turned on to achieve unipolar operation.

[0067] When the polarity of the collector-emitter voltage is negative and the collector-emitter voltage is small, the collector-side gate is turned on to achieve unipolar operation.

[0068] When the polarity of the collector-emitter voltage is negative and the collector-emitter voltage is large, the PWM control signal to the emitter side gate is cut off and the collector side gate is turned on, resulting in bipolar operation.

[0069] Figure 11 is a diagram showing an example of how to determine the high-voltage region and the low-voltage region when the polarity of the collector-emitter voltage is positive. Figure 11 shows the collector current Y1 when the collector-side gate signal is turned on and the collector current Y2 when the collector-side gate signal is turned off. In Figure 11, the vertical axis represents the magnitude of the collector current, and the horizontal axis represents the magnitude of the voltage between the collector electrode and the emitter electrode.

[0070] 11, as the voltage between the collector electrode and the emitter electrode increases, both the collector current Y1 and the collector current Y2 increase. Furthermore, the collector current Y2 is smaller than the collector current Y1 in a range where the voltage between the collector electrode and the emitter electrode is small, and is larger than the collector current Y1 in a range where the voltage between the collector electrode and the emitter electrode is large.

[0071] The value of the collector-emitter voltage at the timing when the magnitude relationship between the collector current Y1 and the collector current Y2 is reversed can be determined as the boundary value between the high voltage region and the low voltage region.

[0072] During inverter operation, the collector-emitter voltage (polarity / magnitude / level) transitions in the following order: (positive / large), (positive / small), (negative / small), (negative / large), (negative / small), (positive / small), (positive / large), (positive / small), ... However, the operating mode (voltage mode) remains the same before and after the polarity reversal of the collector-emitter voltage. Therefore, there is no need to detect the voltage (detect that the voltage is 0 V) ​​when the polarity of the collector-emitter voltage is reversed.

[0073] As described above, according to the semiconductor device of this embodiment, there is no need to detect 0 V, which is difficult to detect due to noise.

[0074] Therefore, it is possible to prevent the semiconductor device from being destroyed due to erroneous detection of 0V, and to allow current to flow in both directions in the semiconductor device.

[0075] Fourth Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0076] 12 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in the example in Fig. 12, the semiconductor device includes an element region 12 and a termination region 14A that surrounds the element region 12 in a plan view.

[0077] FIG. 13 is a cross-sectional view showing an example of the configuration of the structure shown in FIG. 12, taken along the line AB across the element region 12 and the termination region 14A.

[0078] As shown in the example in FIG. 13, the device region 12 and the termination region 14A are provided with an n-type pillar layer 22 and a plurality of p-type pillar layers 24.

[0079] The element region 12 and the termination region 14A are provided with an n-type buffer layer 26. The element region 12 is also provided with an emitter-side n-type layer 28 provided on the top surface of the n-type pillar layer 22.

[0080] The element region 12 also includes a p-type collector layer 30 provided on the surface layer on the lower surface side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper surface side of the emitter-side n-type layer 28.

[0081] The termination region 14A also includes an n-type cathode layer 62 provided in the surface layer on the lower surface side of the n-type buffer layer 26, and a plurality of p-type well layers 64 provided in the surface layer on the upper surface side of the n-type pillar layer 22 across the p-type pillar layer 24. Here, the peak impurity concentration of the n-type cathode layer 62 is, for example, 1×10 １８ cm －３ or more, and 1 x 10 ２１ cm －３ The following is the result.

[0082] The element region 12 is also provided with a trench 50 and a trench 52. The trench 50 is provided with an insulating film 54 and a collector-side gate electrode 58. The trench 52 is provided with an insulating film 56 and an emitter-side gate electrode 60.

[0083] The element region 12 also includes a collector-side n-type layer 34 and an n-type source layer 36 .

[0084] The element region 12 is also provided with an interlayer film 38 , a collector electrode 42 , an interlayer film 40 , and an emitter electrode 44 .

[0085] The termination region 14A also includes an interlayer film 66 provided to cover a portion of the p-type well layer 64, an interlayer film 68 provided to cover a portion of the p-type well layer 64 and the p-type pillar layer 24, an interlayer film 70 provided to cover a portion of the p-type well layer 64 and the n-type pillar layer 22, an electrode 72 provided to cover a portion of the interlayer film 66, a portion of the interlayer film 68, and the exposed p-type well layer 64, and an electrode 74 provided to cover a portion of the interlayer film 68, a portion of the interlayer film 70, and the exposed p-type well layer 64. A portion of the interlayer film 66 is covered by the emitter electrode 44. A collector electrode 42 is provided to cover the n-type cathode layer 62.

[0086] Although termination region 14A shown in FIGS. 12 and 13 has a field limiting ring (FLR) structure, it may have a reduced surface electric field (RESURF) structure or a variation of lateral doping (VLD) structure.

[0087] In the termination region 14A, a pn diode is formed, which is made up of a p-type layer (p-type pillar layer 24, p-type well layer 64) on the surface side of the n-type pillar layer 22 and an n-type cathode layer 62 on the back side of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, and damage to the semiconductor device can be suppressed.

[0088] <Regarding Modification 1> FIG. 14 is a cross-sectional view showing a modification of the configuration shown in FIG.

[0089] As shown in the example in FIG. 14, the device region 12B and the termination region 14B are provided with an n-type pillar layer 22 and a plurality of p-type pillar layers 24.

[0090] The element region 12B and the termination region 14B are provided with an n-type buffer layer 26. The element region 12B is also provided with an emitter-side n-type layer 28 provided on the top surface of the n-type pillar layer 22.

[0091] The element region 12B also includes a p-type collector layer 30B provided on a portion of the surface layer on the lower surface side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper surface side of the emitter-side n-type layer 28.

[0092] The termination region 14B also includes an n-type cathode layer 62B provided in the surface layer on the lower surface side of the n-type buffer layer 26, and multiple p-type well layers 64 provided in the surface layer on the upper surface side of the n-type pillar layer 22, spanning the p-type pillar layers 24. The n-type cathode layer 62B is also provided in part of the surface layer on the lower surface side of the n-type buffer layer 26 in the element region 12B. The n-type cathode layer 62B provided in the element region 12B and the n-type cathode layer 62B provided in the termination region 14B may be continuous or discontinuous. That is, the n-type cathode layer 62B provided in the element region 12B may be provided discretely in the element region 12B.

[0093] The element region 12B is provided with a trench 50 and a trench 52. The trench 50 is provided with an insulating film 54 and a collector-side gate electrode 58. The trench 52 is provided with an insulating film 56 and an emitter-side gate electrode 60.

[0094] The element region 12B also includes a collector-side n-type layer 34 and an n-type source layer 36 .

[0095] The element region 12B is provided with an interlayer film 38, a collector electrode 42, an interlayer film 40, and an emitter electrode 44. The collector electrode 42 is provided to cover the p-type collector layer 30B and the n-type cathode layer 62B.

[0096] Furthermore, the termination region 14B is provided with an interlayer film 66, an interlayer film 68, an interlayer film 70, an electrode 72, and an electrode 74. A portion of the interlayer film 66 is covered with the emitter electrode 44.

[0097] In the termination region 14B, a pn diode is formed, which is made up of a p-type layer (p-type pillar layer 24, p-type well layer 64) on the surface side of the n-type pillar layer 22 and an n-type cathode layer 62B on the back side of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, and breakdown of the semiconductor device can be suppressed.

[0098] <Regarding Modification 2> FIG. 15 is a cross-sectional view showing another modification of the configuration shown in FIG.

[0099] As shown in the example in FIG. 15, an n-type pillar layer 22 and a plurality of p-type pillar layers 24 are provided in the device region 12C and the termination region 14C.

[0100] The element region 12C and the termination region 14C are provided with an n-type buffer layer 26. The element region 12C is also provided with an emitter-side n-type layer 28 provided on the top surface of the n-type pillar layer 22.

[0101] The element region 12C also includes a p-type collector layer 30B provided on a portion of the surface layer on the lower surface side of the n-type buffer layer 26, and a p-type base layer 32 provided on the surface layer on the upper surface side of the emitter-side n-type layer 28.

[0102] The termination region 14C also includes an n-type cathode layer 62C provided in the surface layer on the lower surface side of the n-type buffer layer 26, and multiple p-type well layers 64 provided in the surface layer on the upper surface side of the n-type pillar layer 22, spanning the p-type pillar layer 24. The n-type cathode layer 62C is also provided in part of the surface layer on the lower surface side of the n-type buffer layer 26 in the element region 12C. The n-type cathode layer 62C provided in the element region 12C and the n-type cathode layer 62C provided in the termination region 14C may be continuous or discontinuous. In other words, the n-type cathode layer 62C provided in the element region 12C may be provided discretely in the element region 12C. The n-type cathode layer 62C is a layer formed to have at least one of the impurity concentration and depth identical to that of the collector-side n-type layer 34. The term "identical impurity concentration" or "identical depth" includes deviations of, for example, several percent within the range of measurement error.

[0103] The element region 12C is also provided with a trench 50 and a trench 52. The trench 50 is provided with an insulating film 54 and a collector-side gate electrode 58. The trench 52 is provided with an insulating film 56 and an emitter-side gate electrode 60.

[0104] The element region 12C also includes a collector-side n-type layer 34 and an n-type source layer 36 .

[0105] The element region 12C is provided with an interlayer film 38, a collector electrode 42, an interlayer film 40, and an emitter electrode 44.

[0106] Furthermore, the termination region 14C is provided with an interlayer film 66, an interlayer film 68, an interlayer film 70, an electrode 72, and an electrode 74. A portion of the interlayer film 66 is covered with the emitter electrode 44.

[0107] 15 , first, n-type pillar layers 22 and p-type pillar layers 24 are provided in the device region 12C and the termination region 14C. Here, the p-type pillar layers 24 are provided to a depth that extends from the top surface of the n-type pillar layers 22 to the interior of the n-type pillar layers 22. The n-type pillar layers 22 and the p-type pillar layers 24 are formed alternately in a direction perpendicular to the depth direction of the n-type pillar layers 22.

[0108] Next, in the element region 12C, an emitter-side n-type layer 28 is provided on the upper surface of the n-type pillar layer 22, and a p-type base layer 32 is provided in the surface layer of the upper surface of the emitter-side n-type layer 28. Next, in the element region 12C, an n-type source layer 36 is provided in part of the surface layer of the upper surface of the p-type base layer 32.

[0109] Next, in the element region 12C, a trench 52 is provided that extends from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the inside of the n-type pillar layer 22 so as to contact the n-type source layer 36, and an emitter-side gate electrode 60 surrounded by an insulating film 56 is provided within the trench 52.

[0110] Next, in the element region 12C, an interlayer film 40 is provided to cover part of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 is provided to cover the p-type base layer 32, the n-type source layer 36 and the interlayer film 40.

[0111] On the other hand, in the device region 12C and the termination region 14C, an n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22.

[0112] Next, in the element region 12C, a p-type collector layer 30B is provided on a part of the surface layer below the n-type buffer layer 26.

[0113] Next, in the element region 12C, an n-type cathode layer 62C is provided on another part of the surface layer of the lower surface of the n-type buffer layer 26, and a collector-side n-type layer 34 is provided on a part of the surface layer of the lower surface of the p-type collector layer 30B. At the same time, in the termination region 14C, an n-type cathode layer 62C is provided on the surface layer of the lower surface of the n-type buffer layer 26.

[0114] Next, in the element region 12C, a collector-side gate electrode 58 is provided in contact with the p-type collector layer 30B sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54, but so as not to reach the n-type pillar layer 22. In Fig. 15, a trench 50 is provided in the element region 12C, extending from the lower surface of the p-type collector layer 30B to the inside of the n-type buffer layer 26 but not to reach the n-type pillar layer 22, so as to be in contact with the collector-side n-type layer 34, and a collector-side gate electrode 58 surrounded by the insulating film 54 is provided in the trench 50.

[0115] Next, in the element region 12C, the interlayer film 38 is provided to cover the collector-side gate electrode 58. Next, in the element region 12C and the termination region 14C, the collector electrode 42 is provided to cover the p-type collector layer 30B, the interlayer film 38, and the n-type cathode layer 62C.

[0116] In the termination region 14C, a pn diode is formed, which is made up of a p-type layer (p-type pillar layer 24, p-type well layer 64) on the surface side of the n-type pillar layer 22 and an n-type cathode layer 62C on the back side of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, and damage to the semiconductor device can be suppressed.

[0117] <Regarding the Effects Produced by the Multiple Embodiments Described Above> Next, examples of the effects produced by the multiple embodiments described above will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the multiple embodiments described above, but these may be replaced with other specific configurations exemplified in the present specification to the extent that similar effects are produced. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0118] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0119] According to the embodiment described above, the semiconductor device includes a first pillar layer of a first conductivity type (n-type), a plurality of second pillar layers of a second conductivity type (p-type), a first n-type impurity layer, a p-type base layer, a trench 52, a first gate electrode, an n-type source layer, a first interlayer film, an emitter electrode 44, an n-type buffer layer, a p-type collector layer, a second impurity layer, a second gate electrode, a second interlayer film, and a collector electrode 42. Here, the first pillar layer corresponds to, for example, the n-type pillar layer 22. The second pillar layer corresponds to, for example, the p-type pillar layer 24. The first impurity layer corresponds to, for example, the emitter-side n-type layer 28. The base layer corresponds to, for example, the p-type base layer 32. The first gate electrode corresponds to, for example, the emitter-side gate electrode 60. The source layer corresponds to, for example, an n-type source layer 36. The first interlayer film corresponds to, for example, an interlayer film 40. The buffer layer corresponds to, for example, an n-type buffer layer 26, an n-type buffer layer 26A. The collector layer corresponds to, for example, a p-type collector layer 30, a p-type collector layer 30A, a p-type collector layer 30B. The second impurity layer corresponds to, for example, a collector-side n-type layer 34, a collector-side n-type layer 34A. The second gate electrode corresponds to, for example, a collector-side gate electrode 58, a collector-side gate electrode 58A. The second interlayer film corresponds to, for example, an interlayer film 38, an interlayer film 38A. The p-type pillar layer 24 is provided to a depth that reaches from the top surface of the n-type pillar layer 22 into the n-type pillar layer 22. The emitter-side n-type layer 28 is provided on the upper surface of the n-type pillar layer 22. The p-type base layer 32 is provided in a surface layer on the upper surface of the emitter-side n-type layer 28. The trench 52 is provided from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the inside of the n-type pillar layer 22. The emitter-side gate electrode 60 is provided in the trench 52 and surrounded by a first insulating film. Here, the first insulating film corresponds to, for example, the insulating film 56.The n-type source layer 36 is provided on a portion of the surface layer of the upper surface of the p-type base layer 32 and is in contact with the insulating film 56. The interlayer film 40 is provided so as to cover a portion of the n-type source layer 36 and the emitter-side gate electrode 60. The emitter electrode 44 is provided so as to cover the p-type base layer 32, the n-type source layer 36, and the interlayer film 40. The n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22. The p-type collector layer 30 is provided on the surface layer of the lower surface of the n-type buffer layer 26. The collector-side n-type layer 34 is provided on a portion of the surface layer of the lower surface of the p-type collector layer 30. The collector-side gate electrode 58 is provided so as to contact the p-type collector layer 30 sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via a second insulating film, but does not reach the n-type pillar layer 22. Here, the second insulating film corresponds to, for example, the insulating film 54, the insulating film 54A, etc. The interlayer film 38 is provided to cover the collector-side gate electrode 58. The collector electrode 42 is provided to cover the p-type collector layer 30 and the interlayer film 38. The n-type pillar layers 22 and the p-type pillar layers 24 are arranged alternately in a direction intersecting the depth direction of the n-type pillar layers 22.

[0120] This configuration can suppress the occurrence of high surge voltages in semiconductor devices with a superjunction structure. Specifically, the presence of the emitter-side n-type layer 28 reduces hole injection from the p-type base layer 32 during bipolar reverse conduction. This reduces carrier accumulation on the emitter side. This promotes depletion from the emitter side during bipolar recovery. This in turn suppresses depletion from the collector side, thereby suppressing the occurrence of large surge voltages due to complete depletion.

[0121] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0122] According to the above-described embodiment, the semiconductor device includes a current detection unit and a control unit. Here, the current detection unit corresponds to, for example, the current detection means 108. The control unit corresponds to, for example, the current mode determination means 110 and the PWM control means 106. The current detection means 108 detects the collector current output via the collector electrode 42. The control unit controls the voltages applied to the emitter-side gate electrode 60 and the collector-side gate electrode 58 based on the polarity and current value of the collector current detected by the current detection means 108. With this configuration, the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 is switched depending on the detected collector current, allowing the semiconductor device to operate in either bipolar or unipolar mode, thereby suppressing the generation of large surge voltages.

[0123] Furthermore, according to the embodiment described above, when the polarity of the collector current is positive and the current value of the collector current is greater than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 on and the collector-side gate electrode 58 off. When the polarity of the collector current is positive and the current value of the collector current is smaller than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 on and the collector-side gate electrode 58 on. When the polarity of the collector current is negative and the current value of the collector current is smaller than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 on and the collector-side gate electrode 58 on. When the polarity of the collector current is negative and the current value of the collector current is greater than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 off and the collector-side gate electrode 58 on. With this configuration, the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 is switched depending on the detected collector current, and the semiconductor device is selectively operated in bipolar or unipolar mode, thereby suppressing the generation of large surge voltages.

[0124] According to the above-described embodiment, the semiconductor device includes a voltage detection unit and a control unit. Here, the voltage detection unit corresponds to, for example, the voltage detection means 112. The control unit corresponds to, for example, the voltage mode determination means 114 and the PWM control means 106. The voltage detection means 112 detects an inter-electrode voltage, which is a voltage applied between the collector electrode 42 and the emitter electrode. The control unit controls the voltages applied to the emitter-side gate electrode 60 and the collector-side gate electrode 58 based on the polarity and voltage value of the inter-electrode voltage detected by the voltage detection means 112. With this configuration, the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 is switched depending on the detected collector-emitter voltage, allowing the semiconductor device to operate in either bipolar or unipolar mode, thereby suppressing the generation of large surge voltages.

[0125] Furthermore, according to the embodiment described above, when the polarity of the interelectrode voltage is positive and the voltage value of the interelectrode voltage is greater than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 on and the collector-side gate electrode 58 off. Furthermore, when the polarity of the interelectrode voltage is positive and the voltage value of the interelectrode voltage is less than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 on and the collector-side gate electrode 58 on. Furthermore, when the polarity of the interelectrode voltage is negative and the voltage value of the interelectrode voltage is less than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 on and the collector-side gate electrode 58 on. Furthermore, when the polarity of the interelectrode voltage is negative and the voltage value of the interelectrode voltage is greater than a predetermined threshold, the control unit turns the emitter-side gate electrode 60 off and the collector-side gate electrode 58 on. With this configuration, the operation of the emitter-side gate electrode 60 and the collector-side gate electrode 58 is switched depending on the detected collector-emitter voltage, and the semiconductor device is selectively operated in bipolar or unipolar mode, thereby suppressing the generation of large surge voltages.

[0126] Furthermore, according to the embodiment described above, the semiconductor device includes the element region 12 (or the element region 12B or 12C) and the termination region 14A (or the termination region 14B or 14C) surrounding the element region 12 in a planar view. In the element region 12 and the termination region 14A, n-type pillar layers 22, p-type pillar layers 24, and an n-type buffer layer 26 are provided. Here, the semiconductor device includes an n-type cathode layer provided in the surface layer of the lower surface of the n-type buffer layer 26 in the termination region 14A. The cathode layer corresponds to, for example, the n-type cathode layer 62, the n-type cathode layer 62B, the n-type cathode layer 62C, etc. Furthermore, in the termination region 14A, a collector electrode 42 is provided to cover the n-type cathode layer 62. With this configuration, a pn diode is formed in the termination region 14A, consisting of the p-type layer (p-type pillar layer 24, p-type well layer 64) on the front side of the n-type pillar layer 22 and the n-type cathode layer 62 on the back side of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, and damage to the semiconductor device can be suppressed.

[0127] Furthermore, according to the embodiment described above, the n-type cathode layer 62B (or the n-type cathode layer 62C) is provided in a portion of the surface layer of the lower surface of the n-type buffer layer 26 in the device region 12B (or the device region 12C). The p-type collector layer 30B is provided in another portion of the surface layer of the lower surface of the n-type buffer layer 26. In the device region 12B and the termination region 14B (or the termination region 14C), the collector electrode 42 is provided to cover the p-type collector layer 30B and the n-type cathode layer 62B (or the n-type cathode layer 62C). With this configuration, a pn diode is formed in the termination region 14B, consisting of the p-type layer (p-type pillar layer 24, p-type well layer 64) on the surface side of the n-type pillar layer 22 and the n-type cathode layer 62B on the back side of the n-type pillar layer 22. Therefore, even if the collector-side gate signal is stopped due to a malfunction, reverse conduction is possible, and breakdown of the semiconductor device can be suppressed.

[0128] Furthermore, according to the embodiment described above, the n-type cathode layer 62C and the collector-side n-type layer 34 are formed in the same process, so that they have the same impurity concentration or depth. With this configuration, the collector-side n-type layer 34 in the element region 12C and the n-type cathode layer 62C in the element region 12C and the termination region 14C are formed in the same process, which reduces the number of manufacturing steps compared to when they are formed separately in different processes.

[0129] According to the embodiment described above, in the method for manufacturing a semiconductor device, the semiconductor device includes an element region 12C and a termination region 14C that surrounds the element region 12C in a planar view. In the element region 12C and the termination region 14C, n-type pillar layers 22 and multiple p-type pillar layers 24 that are provided at a depth extending from the upper surfaces of the n-type pillar layers 22 into the n-type pillar layers 22 are alternately arranged in a direction intersecting the depth direction of the n-type pillar layers 22. In the element region 12C, an emitter-side n-type layer 28 is provided on the upper surfaces of the n-type pillar layers 22, and a p-type base layer 32 is provided in the surface layer of the upper surface of the emitter-side n-type layer 28. In the element region 12C, an n-type source layer 36 is provided in a portion of the surface layer of the upper surface of the p-type base layer 32. In the element region 12C, a trench 52 is provided extending from the upper surface of the p-type base layer 32 to the emitter-side n-type layer 28 and further to the interior of the n-type pillar layer 22 so as to be in contact with the n-type source layer 36. An emitter-side gate electrode 60 surrounded by an insulating film 56 is provided in the trench 52. In the element region 12C, an interlayer film 40 is provided covering a portion of the n-type source layer 36 and the emitter-side gate electrode 60, and an emitter electrode 44 is provided covering the p-type base layer 32, the n-type source layer 36, and the interlayer film 40. In the element region 12C and the termination region 14C, an n-type buffer layer 26 is provided on the lower surface of the n-type pillar layer 22. In the element region 12C, a p-type collector layer 30B is provided in a portion of the surface layer of the lower surface of the n-type buffer layer 26. In the device region 12C, an n-type cathode layer 62C is provided on another portion of the surface layer of the lower surface of the n-type buffer layer 26, and a collector-side n-type layer 34 is provided on a portion of the surface layer of the lower surface of the p-type collector layer 30B. At the same time, in the termination region 14C, the n-type cathode layer 62C is provided on the surface layer of the lower surface of the n-type buffer layer 26. In the device region 12C, a collector-side gate electrode 58 is provided in contact with the p-type collector layer 30B sandwiched between the n-type buffer layer 26 and the collector-side n-type layer 34 via the insulating film 54 (or insulating film 54A), but not reaching the n-type pillar layer 22. In the device region 12C, an interlayer film 38 is provided covering the collector-side gate electrode 58. In the device region 12C and the termination region 14C, a collector electrode 42 is provided covering the p-type collector layer 30B, the interlayer film 38, and the n-type cathode layer 62C.

[0130] This configuration can suppress the occurrence of high surge voltages in a semiconductor device having a superjunction structure. Furthermore, because the collector-side n-type layer 34 in the element region 12C and the n-type cathode layer 62C in the element region 12C and the termination region 14C are formed in the same process, the number of manufacturing steps can be reduced compared to when they are formed separately in separate processes.

[0131] Unless otherwise specified, the order in which the processes are performed can be changed.

[0132] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0133] <Regarding Modifications of the Multiple Embodiments Described Above> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0134] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0135] Furthermore, in at least one embodiment described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0136] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may be provided.

[0137] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to a part of a structure, and even cases where multiple components are provided in one structure.

[0138] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0139] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0140] 12 Element region, 12B Element region, 12C Element region, 14 Termination region, 14A Termination region, 14B Termination region, 14C Termination region, 22 n-type pillar layer, 24 p-type pillar layer, 26 n-type buffer layer, 26A n-type buffer layer, 28 Emitter-side n-type layer, 30 p-type collector layer, 30A p-type collector layer, 30B p-type collector layer, 32 p-type base layer, 34 Collector-side n-type layer, 34A Collector-side n-type layer, 36 n-type source layer, 38 Interlayer film, 38A Interlayer film, 40 Interlayer film, 42 Collector electrode, 44 Emitter electrode, 50 Trench, 52 Trench, 54 Insulating film, 54A Insulating film, 56 Insulating film, 58 Collector-side gate electrode, 58A Collector-side gate electrode, 60 Emitter-side gate electrode, 62 n-type cathode layer, 62B n-type cathode layer, 62C n-type cathode layer, 64 p-type well layer, 66 interlayer film, 68 interlayer film, 70 interlayer film, 72 electrode, 74 electrode, 102 collector-side gate drive means, 104 emitter-side gate drive means, 106 PWM control means, 108 current detection means, 110 current mode determination means, 112 voltage detection means, 114 voltage mode determination means, X1 collector current, X2 collector current, Y1 collector current, Y2 collector current.

Claims

1. a first pillar layer of a first conductivity type; a plurality of second pillar layers of a second conductivity type provided at a depth reaching from the upper surface of the first pillar layer into the first pillar layer; a first impurity layer of the first conductivity type provided on the upper surface of the first pillar layer; a base layer of the second conductivity type provided on the surface layer of the upper surface of the first impurity layer; a trench provided from the upper surface of the base layer reaching into the first impurity layer and further into the first pillar layer; a first gate electrode provided in the trench and surrounded by a first insulating film; a source layer of the first conductivity type provided on a part of the surface layer of the upper surface of the base layer and in contact with the first insulating film; a first interlayer film provided covering a part of the source layer and the first gate electrode; an emitter electrode provided covering the base layer, the source layer, and the first interlayer film; a buffer layer of the first conductivity type provided on the lower surface of the first pillar layer; a collector layer of the second conductivity type provided on the surface layer of the lower surface of the buffer layer; a second impurity layer of the first conductivity type provided on a part of the surface layer of the lower surface of the collector layer; a second gate electrode in contact with the collector layer sandwiched between the buffer layer and the second impurity layer via a second insulating film and provided without reaching the first pillar layer; a second interlayer film provided covering the second gate electrode; and a collector electrode provided covering the collector layer and the second interlayer film, wherein the first pillar layer and the second pillar layer are alternately arranged side by side in a direction intersecting the depth direction of the first pillar layer, a semiconductor device.

2. The semiconductor device according to claim 1, further comprising a current detection unit that detects a collector current output via the collector electrode, and a control unit that controls the voltages applied to the first gate electrode and the second gate electrode based on the polarity and current value of the collector current detected by the current detection unit. a semiconductor device.

3. The semiconductor device according to claim 2, wherein when the polarity of the collector current is positive and the current value of the collector current is greater than a predetermined threshold value, the control unit turns on the first gate electrode and turns off the second gate electrode. When the polarity of the collector current is positive and the current value of the collector current is smaller than a predetermined threshold value, the first gate electrode is turned on and the second gate electrode is turned on. When the polarity of the collector current is negative and the current value of the collector current is smaller than a predetermined threshold value, the first gate electrode is turned on and the second gate electrode is turned on. When the polarity of the collector current is negative and the current value of the collector current is larger than a predetermined threshold value, the first gate electrode is turned off and the second gate electrode is turned on. Semiconductor device.

4. The semiconductor device according to claim 1, a voltage detection unit that detects an inter-electrode voltage, which is a voltage applied between the collector electrode and the emitter electrode; and a control unit that controls the voltages applied to the first gate electrode and the second gate electrode based on the polarity and voltage value of the inter-electrode voltage detected by the voltage detection unit. Semiconductor device.

5. The semiconductor device according to claim 4, wherein the control unit turns on the first gate electrode and turns off the second gate electrode when the polarity of the inter-electrode voltage is positive and the voltage value of the inter-electrode voltage is larger than a predetermined threshold value; turns on the first gate electrode and turns on the second gate electrode when the polarity of the inter-electrode voltage is positive and the voltage value of the inter-electrode voltage is smaller than a predetermined threshold value; turns on the first gate electrode and turns on the second gate electrode when the polarity of the inter-electrode voltage is negative and the voltage value of the inter-electrode voltage is smaller than a predetermined threshold value; turns off the first gate electrode and turns on the second gate electrode when the polarity of the inter-electrode voltage is negative and the voltage value of the inter-electrode voltage is larger than a predetermined threshold value. Semiconductor device.

6. The semiconductor device according to any one of claims 1 to 5, comprising an element region and a termination region surrounding the element region in a plan view, wherein the first pillar layer, the second pillar layer, and the buffer layer are provided in the element region and the termination region. In the above semiconductor device, in the terminal region, the semiconductor device further includes a cathode layer of a first conductivity type provided on the surface layer of the lower surface of the buffer layer. In the terminal region, the collector electrode is provided to cover the cathode layer. Semiconductor device.

7. The semiconductor device according to claim 6, wherein the cathode layer is provided on a part of the surface layer of the lower surface of the buffer layer in the element region, the collector layer is provided on another part of the surface layer of the lower surface of the buffer layer, and in the element region and the terminal region, the collector electrode is provided to cover the collector layer and the cathode layer. Semiconductor device.

8. The semiconductor device according to claim 6, wherein the cathode layer and the second impurity layer are formed in the same process. Semiconductor device.

9. The semiconductor device according to claim 7, wherein the cathode layer and the second impurity layer are formed in the same process. Semiconductor device.

10. The semiconductor device according to claim 8, wherein at least one of the impurity concentration or the depth of the cathode layer and the second impurity layer is the same. Semiconductor device.

11. The semiconductor device according to claim 9, wherein at least one of the impurity concentration or the depth of the cathode layer and the second impurity layer is the same. Semiconductor device.

12. A method for manufacturing a semiconductor device including an element region and a terminal region surrounding the element region in a plan view, wherein in the element region and the terminal region, a first pillar layer of a first conductivity type and a plurality of second pillar layers of a second conductivity type provided at a depth reaching from the upper surface of the first pillar layer into the first pillar layer are alternately arranged in a direction intersecting the depth direction of the first pillar layer, in the element region, a first impurity layer of the first conductivity type is provided on the upper surface of the first pillar layer, and a base layer of the second conductivity type is provided on the surface layer of the upper surface of the first impurity layer, in the element region, a source layer of the first conductivity type is provided on a part of the surface layer of the upper surface of the base layer, in the element region, a trench reaching from the upper surface of the base layer to the first impurity layer and further into the first pillar layer is provided to contact the source layer, and in the trench, a first gate electrode surrounded by a first insulating film is provided. In the element region, a first interlayer film is provided to cover a part of the source layer and the first gate electrode, and an emitter electrode is provided to cover the base layer, the source layer, and the first interlayer film. In the element region and the terminal region, a buffer layer of a first conductivity type is provided on the lower surface of the first pillar layer. In the element region, a collector layer of a second conductivity type is provided on a part of the surface layer of the lower surface of the buffer layer. In the element region, a cathode layer of a first conductivity type is provided on another part of the surface layer of the lower surface of the buffer layer, and a first impurity layer of a first conductivity type is provided on a part of the surface layer of the lower surface of the collector layer. At the same time, in the terminal region, the cathode layer is provided on the surface layer of the lower surface of the buffer layer. In the element region, a second gate electrode is provided to contact the collector layer sandwiched between the buffer layer and the second impurity layer through a second insulating film and not reach the first pillar layer. In the element region, a second interlayer film is provided to cover the second gate electrode. In the element region and the terminal region, a collector electrode is provided to cover the collector layer, the second interlayer film, and the cathode layer. A method for manufacturing a semiconductor device.