Interruption simulation device, interruption simulation method, and interruption simulation program

Abstract

An interruption simulation device (10) is provided with an accumulative addition unit (14) and a branch addition unit (15). The accumulative addition unit (14) uses, as a target basic block, each of a plurality of basic blocks obtained by dividing a target program (20) being a computer program, to add an accumulative addition process of adding a value corresponding to an estimated execution time of the target basic block to a counter variable corresponding to an accumulated execution time of the target program (20) when the target basic block is executed in the target program (20). The branch addition unit (15) adds, to the target program (20), a conditional branch process to be executed when the value of the counter variable satisfies a trigger condition.

Description

Interrupt simulation device, interrupt simulation method, and interrupt simulation program

[0001] The present disclosure relates to an interrupt simulation device, an interrupt simulation method, and an interrupt simulation program.

[0002] In the development of embedded programs, there are cases where the actual machine that will serve as the embedded program's operating environment is not readily available. Furthermore, since embedded programs often require real-time performance, it is important to estimate the execution time of the embedded program from the early stages of development. When the actual machine is not readily available in the early stages of development, it is common to estimate the execution time of the embedded program using an emulator or simulator. However, when using an emulator or simulator, there is a problem that it takes a long time to estimate the execution time of the embedded program due to the execution time overhead caused by the emulation or simulation. Patent Document 1 proposes a method to solve this problem by using a compiler-based program analysis technology to estimate the execution time of an embedded program without using an emulator or simulator.

[0003] International Publication No. 2010 / 001766

[0004] Some embedded programs use interrupts. An interrupt is a mechanism that executes a pre-specified process when an interrupt event occurs. An interrupt event is an external event, such as a timer firing. The technique proposed in Patent Document 1 lacks a mechanism for simulating interrupt events, making it impossible to estimate the execution time of a program that handles interrupts. When using this technique to estimate the execution time of an embedded program that handles interrupts, a problem occurs in the branch history information generation process shown in FIG. 3 of Patent Document 1. As a specific example, consider a case in which the value of variable X is changed when a timer fires, and the main process waits until the value of variable X changes. In this case, the branch history information generation process cannot simulate the timer firing event, so the main process does not execute the process after the wait process. As a result, the expected execution time estimate cannot be obtained. The present disclosure aims to simulate timer interrupt events without using an emulator or simulator by utilizing compiler-based program analysis technology. Here, a timer interrupt event is an interrupt event triggered by a timer firing.

[0005] The interrupt simulation device according to the present disclosure includes: an accumulation addition unit that, when a target program, which is a computer program, is divided into a plurality of basic blocks, treats each basic block of the plurality of basic blocks as a target basic block, and adds an accumulation addition process to the target program, when the target basic block is executed, to add a value corresponding to the estimated execution time of the target basic block to a counter variable corresponding to the accumulated execution time of the target program; and a branch addition unit that adds, to the target program, a conditional branch process that is executed when the value of the counter variable satisfies an ignition criterion condition.

[0006] When a target program modified according to the present disclosure is executed, the cumulative execution time of the target program is managed using a counter variable, and a conditional branch process is executed when the value of the counter variable satisfies a trigger criteria condition. Here, the conditional branch process corresponds to a timer interrupt event, and the cumulative execution time is the cumulative estimated execution time of each basic block. Each basic block may be divided by utilizing a program analysis technique by a compiler. Therefore, according to the present disclosure, by utilizing the program analysis technique by a compiler, it is possible to simulate a timer interrupt event without using an emulator or simulator.

[0007] FIG. 1 is a diagram showing an example of the configuration of an interrupt simulator 10 according to the first embodiment. FIG. 2 is a diagram explaining a processed program 29 according to the first embodiment. FIG. 3 is a diagram showing an example of the hardware configuration of the interrupt simulator 10 according to the first embodiment. FIG. 4 is a flowchart showing the operation of a definition adding unit 13 according to the first embodiment. FIG. 5 is a diagram explaining a target program 21 according to the first embodiment. FIG. 6 is a flowchart showing the operation of an accumulation adding unit 14 according to the first embodiment. FIG. 7 is a flowchart showing the operation of a branch adding unit 15 according to the first embodiment. FIG. 8 is a diagram explaining a setting file 28 and a processed program 29 according to the first embodiment. FIG. 9 is a diagram showing an example of the hardware configuration of an interrupt simulator 10 according to a modification of the first embodiment.

[0008] In the description of the embodiments and the drawings, the same elements and corresponding elements are given the same reference numerals. The description of elements given the same reference numerals will be omitted or simplified as appropriate. Arrows in the drawings mainly indicate the flow of data or the flow of processing. Furthermore, "unit" may be read as "circuit," "step," "procedure," "process," or "circuitry" as appropriate.

[0009] First Embodiment Hereinafter, the present embodiment will be described in detail with reference to the drawings.

[0010] ***Description of Configuration*** FIG. 1 shows an example of the software configuration of an interrupt simulator 10. As shown in FIG. 1, the interrupt simulator 10 includes a division unit 11, an estimation unit 12, a definition addition unit 13, a storage addition unit 14, and a branch addition unit 15. The division unit 11 and the estimation unit 12 execute static estimation processing to statically estimate the execution time of each basic block included in a target program 20. The target program 20 is a computer program. In this specification, a computer program is simply referred to as a "program." The definition addition unit 13, the storage addition unit 14, and the branch addition unit 15 add processing to simulate a timer interrupt event to the target program 20 based on the results of the static estimation processing and a configuration file 28. The configuration file 28 is, as a specific example, a file created by the user.

[0011] The dividing unit 11 is a software module that receives a target program 20 as input, divides the received target program 20 into a plurality of basic blocks, and outputs a basic block set consisting of the divided basic blocks. The target program 20 is a program whose execution time is to be measured, and a specific example is an embedded program. The dividing unit 11 divides the target program 20 into a plurality of basic blocks using a known algorithm. As a specific example, the algorithm is provided as a function of the open-source compiler platform LLVM (Low Level Virtual Machine).

[0012] The estimation unit 12 is a software module that receives a set of basic blocks as input, estimates the execution time for each element of the received set of basic blocks, and outputs the estimated execution time. An example of an algorithm for estimating execution time is disclosed in Patent Document 1.

[0013] The definition adding unit 13 is a software module that adds a counter variable to the target program 20. Here, the counter variable is a variable that corresponds to the cumulative execution time of the target program 20, and is a global variable that holds the cumulative value of the current estimated execution time during execution of the target program 20.

[0014] The accumulative addition unit 14 is a software module that adds an accumulative addition process to a counter variable on a basic block-by-basic block basis. That is, when a target program is divided into a plurality of basic blocks, the accumulative addition unit 14 sets each basic block of the plurality of basic blocks as a target basic block and adds an accumulative addition process corresponding to the target basic block in the target program. The accumulative addition process is a process of adding a value corresponding to the estimated execution time of the target basic block to a counter variable when the target basic block is executed. The accumulative addition process accumulates a cumulative value of the current estimated execution time required to simulate timer firing. The target program is a collective term for the target program 20, the target program 21, and the target program 22. The target program 22 is the target program 21 to which the accumulative addition process has been added by the accumulative addition unit 14. The target program 21 is the target program 20 to which the definition of the counter variable has been added by the definition adding unit 13. The accumulative addition unit 14 may add an accumulative addition process corresponding to the target basic block to the end of the target basic block.

[0015] The branch addition unit 15 is a software module that adds a conditional branch process to simulate a timer interrupt event based on the configuration file 28. The conditional branch process may be executed when the value of a counter variable satisfies a trigger condition. The trigger condition may be any condition. The trigger condition may be a condition specified by the configuration file 28, i.e., an externally set condition. The branch addition unit 15 outputs a program in which a conditional branch process has been added to the target program as a modified program 29. The branch addition unit 15 may add a conditional branch process to the end of a basic block corresponding to the conditional branch process. A timer interrupt event can be simulated by executing the modified program 29 on a computer having the hardware configuration shown in FIG. 3. In the modified program 29, a basic block is a partial instruction sequence of a program having only one branch instruction at the end. The modified program 29 accumulates the estimated execution time of each basic block passed through during execution of the target program 20, thereby simulating a timer interrupt event based on the estimated execution time.

[0016] 2 is a diagram illustrating a modified program 29. The target program 20 shown in FIG. 2 does not have a mechanism for simulating a timer interrupt event. Therefore, even when the target program 20 is executed on a computer, the processing after the while statement corresponding to waiting for the TimerHandler to complete is not executed. On the other hand, by the interrupt simulator 10 modifying the target program 20, a modified program 29 is generated in which simulation processing of a timer interrupt event based on the configuration file 28 is added to the target program 20. When the modified program 29 is executed on a computer, the processing after the while statement corresponding to waiting for the TimerHandler to complete is also executed.

[0017] 3 is a diagram illustrating an example of the hardware configuration of the interrupt simulator 10. The interrupt simulator 10 is a computer and includes, as hardware components, a processor 51, a memory 52, a secondary storage device 53, an input device 54, an output device 55, and a bus 59. The processor 51 is a hardware unit that performs calculations and control based on instructions written in a program, and is, for example, a CPU (Central Processing Unit). The interrupt simulator 10 may include multiple processors that replace the processor 51. The multiple processors share the role of the processor 51. The memory 52 is a volatile storage device and is a hardware unit that stores programs and data. For example, the memory 52 is a RAM (Random Access Memory). The secondary storage device 53 is a non-volatile storage device and is a hardware unit that stores the interrupt simulator program and the configuration file 28. The secondary storage device 53 is, for example, a hard disk drive (HDD) or a solid state drive (SSD). The input device 54 is a hardware unit that allows the user to input data to the system. For example, the input device 54 is a keyboard and a mouse. The output device 55 is a hardware unit that transmits processing results from the system to the user. For example, the output device 55 is a display. These hardware units are connected to each other via a bus 59.

[0018] The secondary storage device 53 stores an interrupt simulation program. The interrupt simulation program is a program that causes a computer to realize the functions of each unit of the interrupt simulation device 10. The functions of each unit of the interrupt simulation device 10 are realized by software. The interrupt simulation program may be recorded on a computer-readable non-volatile recording medium. Specific examples of the non-volatile recording medium include an optical disk or a flash memory. The interrupt simulation program may be provided as a program product. The processor 51 reads the interrupt simulation program stored in the memory 52 and performs calculations, control, etc. in accordance with the instructions written in the interrupt simulation program. If the instruction is a memory read / write instruction, the processor 51 reads and writes data from a corresponding area in the memory 52. ​​If the instruction is a file read / write instruction, the processor 51 reads and writes a file from a corresponding area in the secondary storage device 53. If the instruction is an input instruction, the processor 51 obtains data from the input device 54 and writes the obtained data to the memory 52. If the command is an output command, the processor 51 acquires the data to be output from the memory 52 and outputs the acquired data to be output to the output device 55 .

[0019] ***Explanation of Operation*** The operating procedure of the interrupt simulator 10 corresponds to an interrupt simulator method. Also, the program that realizes the operation of the interrupt simulator 10 corresponds to an interrupt simulator program.

[0020] 4 is a flowchart showing an example of the processing of the definition adding unit 13. The processing of the definition adding unit 13 will be described with reference to FIG.

[0021] (Step S101) The definition adding unit 13 receives the target program 20 as input and adds a definition of a counter variable to the global variable area of ​​the received target program 20. The definition adding unit 13 adds the definition of the counter variable in a format that conforms to the grammar of the language of the target program 20. As a specific example, if the target program 20 is written in C language, a definition statement of the global variable CurrentTime is added as the definition of the counter variable, as shown in Figure 5. In addition, the initial value of the counter variable is set to 0.

[0022] Fig. 6 is a flowchart showing an example of the processing of the accumulation adding unit 14. The processing of the accumulation adding unit 14 will be described using Fig. 6. Note that in this flowchart, it is assumed that the processing of the division unit 11, the processing of the estimation unit 12, and the processing of the definition adding unit 13 have already been executed.

[0023] (Step S111) This step is a loop for adding an accumulation addition process to each element of the basic block set. The accumulation addition unit 14 receives as input the output of the estimation unit 12 and the output of the definition addition unit 13. In addition, the accumulation addition unit 14 selects one element of the basic block set as the target basic block in each iteration of the loop. Here, "BB" indicates the target basic block.

[0024] (Step S112) The accumulation adding unit 14 acquires the estimated execution time corresponding to the target basic block as the target execution time.

[0025] (Step S113) The accumulating and adding unit 14 adds an accumulating and adding process to the target basic block. As a specific example, the accumulating and adding unit 14 adds a process to accumulate and add a value corresponding to the target execution time to a counter variable at the end of the target basic block.

[0026] 7 is a flowchart showing an example of the processing of the branch addition unit 15. The processing of the branch addition unit 15 will be described using Fig. 7. In this flowchart, the branch addition unit 15 receives the output of the accumulation addition unit 14 and the configuration file 28 as input, and adds a conditional branch for simulating an interrupt event to the target program 22 based on the configuration file 28.

[0027] (Step S121) This step is a loop for adding a conditional branch to each element of the basic block set. In each iteration of the loop, the accumulation and addition unit 14 selects one element of the basic block set as a target basic block.

[0028] (Step S122) This step is a loop for adding a conditional branch corresponding to each entry indicated by the configuration file 28. In each iteration of the loop, the branch adding unit 15 selects one entry indicated by the configuration file 28 as a target entry.

[0029] (Step S123) The branch addition unit 15 adds a conditional branch corresponding to the target entry to the end of the target basic block. As a specific example, the branch addition unit 15 acquires the condition expression and processing content for the conditional branch from the configuration file 28. Here, the condition expression can include a counter variable and a global variable included in the target program 22. The processing content can include a call to a function included in the target program 22.

[0030] 8 shows a specific example of a settings file 28 and a modified program 29. In FIG. 8, the first entry simulates a timer interrupt event, i.e., simulates the firing of a timer. The description in the first entry causes the TimerHandler function to be called when the current estimated execution time exceeds 1000. Furthermore, the value of FlagTimerHandler is set by calling the TimerHandler function, and thus the wait for TimerHandler completion in the main function is released. Furthermore, as in the second and third entries shown in FIG. 8, global variables defined in the target program 20 can be described in the conditional expressions.

[0031] ***Explanation of Effects of First Embodiment*** As described above, according to this embodiment, simulating a timer interrupt event does not require either an actual machine that serves as the operating environment of the program, or an emulator or simulator having an interrupt model. Therefore, according to this embodiment, it is possible to simulate a timer interrupt event based on the elapsed time during program execution even in the early stages of development when it is not possible to prepare an actual machine, etc. Furthermore, according to this embodiment, no execution time overhead due to emulation or simulation occurs in simulating a timer interrupt event, thereby speeding up the simulation of the timer interrupt event.

[0032] ***Other Configurations*** <Modification 1> Fig. 9 shows an example of the hardware configuration of the interrupt simulator 10 according to this modification. The interrupt simulator 10 includes a processing circuit 58 instead of the processor 51, the processor 51 and memory 52, the processor 51 and secondary storage device 53, or the processor 51, memory 52, and secondary storage device 53. The processing circuit 58 is hardware that realizes at least a part of the components included in the interrupt simulator 10. The processing circuit 58 may be dedicated hardware, or may be a processor that executes a program stored in the memory 52.

[0033] When the processing circuit 58 is dedicated hardware, the processing circuit 58 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. The interrupt simulator 10 may include multiple processing circuits that replace the processing circuit 58. The multiple processing circuits share the role of the processing circuit 58.

[0034] In the interrupt simulator 10, some of the functions may be realized by dedicated hardware, and the remaining functions may be realized by software or firmware.

[0035] The processing circuit 58 is realized by, for example, hardware, software, firmware, or a combination of these. The processor 51, memory 52, secondary storage device 53, and processing circuit 58 are collectively referred to as the "processing circuitry." In other words, the functions of each functional component of the interrupt simulator 10 are realized by the processing circuitry.

[0036] ***Other Embodiments*** Although the first embodiment has been described, it is also possible to combine multiple parts of this embodiment and implement it. Alternatively, it is also possible to implement this embodiment in part. In addition, this embodiment may be modified in various ways as needed, and may be implemented in any combination, either as a whole or in part. Note that the above-described embodiments are essentially preferred examples and are not intended to limit the scope of the present disclosure, its applications, and uses. The procedures described using flowcharts, etc. may be modified as appropriate.

[0037] 10 interrupt simulator, 11 division unit, 12 estimation unit, 13 definition addition unit, 14 accumulation addition unit, 15 branch addition unit, 20, 21, 22 target program, 28 setting file, 29 processed program, 51 processor, 52 memory, 53 secondary storage device, 54 input device, 55 output device, 58 processing circuit, 59 bus.

Claims

1. an accumulation adding unit which, when a target program which is a computer program is divided into a plurality of basic blocks, treats each basic block of the plurality of basic blocks as a target basic block, and adds an accumulation addition process which adds a value corresponding to an estimated execution time of the target basic block to a counter variable corresponding to an accumulated execution time of the target program when the target basic block is executed in the target program; a branch addition unit that adds a conditional branch process to the target program, the conditional branch process being executed when the value of the counter variable satisfies an ignition criteria condition; An interrupt simulation device comprising:

2. 2. The interrupt simulator according to claim 1, wherein the target program is an embedded program.

3. the accumulation addition unit adds an accumulation addition process corresponding to the target basic block to an end of the target basic block; 3. The interrupt simulator according to claim 1, wherein the branch addition unit adds the conditional branch processing to an end of a basic block corresponding to the conditional branch processing.

4. 3. The interrupt simulator according to claim 1, wherein the ignition criteria are conditions specified in a setting file.

5. 3. The interrupt simulator according to claim 1, wherein the counter variable is a global variable.

6. a computer adds an accumulative addition process for, when a target program, which is a computer program, is divided into a plurality of basic blocks, treating each basic block of the plurality of basic blocks as a target basic block, and, when a target basic block is executed in the target program, adding a value corresponding to an estimated execution time of the target basic block to a counter variable corresponding to an accumulated execution time of the target program; The interrupt simulation method, in which the computer adds, to the target program, a conditional branch process that is executed when the value of the counter variable satisfies an ignition reference condition.

7. an accumulation addition process for adding an accumulation addition process for adding a value corresponding to an estimated execution time of a target basic block to a counter variable corresponding to an accumulated execution time of the target program when the target program is divided into a plurality of basic blocks and each basic block of the plurality of basic blocks is set as a target basic block and the target basic block is executed in the target program; a branch addition process for adding a conditional branch process to the target program, the conditional branch process being executed when the value of the counter variable satisfies an ignition criterion condition; An interrupt simulation program that causes an interrupt simulation device, which is a computer, to execute the above.