Semiconductor device and semiconductor device production method

Abstract

Provided is a semiconductor device comprising: a chip that has a main surface; a gate electrode that is formed on the main surface; an interlayer film that covers the gate electrode; an opening that is formed in the interlayer film separately from an electrode side part of the gate electrode in a lateral direction along the main surface, and that exposes a part of the main surface as a contact surface; and a surface electrode that is formed on the interlayer film and that is mechanically and electrically connected to the contact surface in the opening. The interlayer film includes an insulation upper part which contacts an electrode upper part of the gate electrode, an insulation side part which contacts the electrode side part, and an insulation corner part which contacts an electrode corner part of the gate electrode. The corner part thickness of the interlayer film at the insulation corner part is greater than at least one of the upper part thickness of the interlayer film at the insulation upper part and the side part thickness of the interlayer film at the insulation side part.

Description

Semiconductor device and method for manufacturing the same Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-044003 filed with the Japan Patent Office on March 20, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] Patent Document 1 describes － A plurality of p-type body regions are formed on the surface of a SiC semiconductor layer, each constituting a unit cell, an n-type source region formed inside the p-type body region, a gate electrode facing the p-type body region via a gate insulating film, and n-type gate electrodes formed adjacent to each other on the back surface of the SiC semiconductor layer. ＋ type drain region and p ＋ a p-type collector region, a p-type body region, and a ＋ between the n-type drain region － and a p-type drift region. ＋ The present invention discloses a SiC semiconductor device in which the collector region is formed so as to cover a region including at least two unit cells in the X-axis along the surface of the SiC semiconductor layer.

[0004] JP 2015-207588 A

[0005] An embodiment of the present disclosure provides a semiconductor device capable of improving the breakdown voltage reliability between a gate electrode and a surface electrode, and a method for manufacturing the same.

[0006] One embodiment of the present disclosure provides a semiconductor device including: a chip having a main surface; a gate electrode formed on the main surface, the gate electrode having an electrode upper portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion formed by removing a portion of the material of the gate electrode and connecting the electrode upper portion and the electrode side portion; an interlayer film covering the gate electrode; an opening formed in the interlayer film spaced laterally along the main surface from the electrode side portion and exposing a portion of the main surface as a contact surface; and a surface electrode formed on the interlayer film and mechanically and electrically connected to the contact surface within the opening, the interlayer film including an insulating upper portion in contact with the electrode upper portion, an insulating side portion in contact with the electrode side portion, and an insulating corner portion in contact with the electrode corner portion, and the corner thickness of the interlayer film at the insulating corner portion is thicker than at least one of an upper thickness of the interlayer film at the insulating upper portion and a side thickness of the interlayer film at the insulating side portion.

[0007] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of: forming a base electrode on a main surface of a wafer; selectively isotropically etching the base electrode in a thickness direction, followed by anisotropically etching the base electrode, to form a gate electrode having an electrode upper portion along the main surface, electrode side portions rising from the main surface, and electrode corner portions connecting the electrode upper portion and the electrode side portions and including an arc-shaped recess curved inward of the base electrode; forming an interlayer film on the main surface to cover the gate electrode; forming an opening in the interlayer film to expose a portion of the main surface as a contact surface, the opening being spaced apart from the electrode side portions in a lateral direction along the main surface; and forming a surface electrode on the interlayer film to be mechanically and electrically connected to the contact surface within the opening.

[0008] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of: forming a base electrode on a main surface of a wafer; selectively anisotropically taper-etching the base electrode in a thickness direction, followed by anisotropic vertical etching, to form a gate electrode having an electrode upper portion along the main surface, electrode side portions rising from the main surface, and electrode corner portions connecting the electrode upper portion and the electrode side portions and including flat inclined walls sloping down from the electrode upper portion to the electrode side portions; forming an interlayer film on the main surface to cover the gate electrode; forming an opening in the interlayer film to expose a portion of the main surface as a contact surface, the opening being spaced apart from the electrode side portions in a lateral direction along the main surface; and forming a surface electrode on the interlayer film to be mechanically and electrically connected to the contact surface within the opening.

[0009] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of: forming a base electrode including polysilicon on a main surface of a wafer; selectively anisotropically etching the base electrode in a thickness direction to form a gate electrode having an upper electrode portion along the main surface, electrode side portions rising from the main surface, and electrode corner portions connecting the upper electrode portion and the electrode side portions; thermally oxidizing the gate electrode to form arc-shaped rounded portions at the electrode corner portions that curve obliquely upward from the gate electrode; forming an interlayer film on the main surface to cover the gate electrode; forming openings in the interlayer film to expose a portion of the main surface as a contact surface, the openings being spaced apart from the electrode side portions in a lateral direction along the main surface; and forming a surface electrode on the interlayer film to be mechanically and electrically connected to the contact surface within the opening.

[0010] According to an embodiment of the present disclosure, it is possible to provide a semiconductor device capable of improving the breakdown voltage reliability between a gate electrode and a surface electrode, and a method for manufacturing the same.

[0011] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing further main portions of the first main surface. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is an enlarged cross-sectional view showing a main portion of FIG. 6 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is an enlarged cross-sectional view showing a main portion of FIG. 8 . FIG. 10 is an enlarged cross-sectional view showing a main portion of FIG. 7 . FIG. 11 is a schematic diagram showing a wafer. FIG. 12A is a cross-sectional view showing a method for manufacturing a semiconductor device. FIG. 12B is a cross-sectional view showing a process subsequent to FIG. 12A . FIG. 12C is a cross-sectional view showing a process subsequent to FIG. 12B . FIG. 12D is a cross-sectional view showing a process subsequent to FIG. 12C . FIG. 12E is a cross-sectional view showing a process subsequent to FIG. 12D . FIG. 12F is a cross-sectional view showing a process subsequent to FIG. 12E . FIG. 12G is a cross-sectional view showing a step after FIG. 12F. FIG. 12H is a cross-sectional view showing a step after FIG. 12G. FIG. 12I is a cross-sectional view showing a step after FIG. 12H. FIG. 12J is a cross-sectional view showing a step after FIG. 12I. FIG. 12K is a cross-sectional view showing a step after FIG. 12J. FIG. 12L is a cross-sectional view showing a step after FIG. 12K. FIG. 12M is a cross-sectional view showing a step after FIG. 12L. FIG. 13 is a cross-sectional view showing a first modified example of a gate electrode. FIG. 14A is a view showing a step related to forming the gate electrode of FIG. 13. FIG. 14B is a cross-sectional view showing a step after FIG. 14A. FIG. 15 is a cross-sectional view showing a second modified example of a gate electrode. FIG. 16A is a view showing a step related to forming the gate electrode of FIG. 15. FIG. 16B is a cross-sectional view showing a step after FIG. 16A.

[0012] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0013] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0014] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0015] Fig. 1 is a plan view showing a semiconductor device 1 according to an embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of the first main surface 3. Fig. 5 is an enlarged plan view showing further main portions of the first main surface 3.

[0016] Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 5. Fig. 7 is an enlarged cross-sectional view showing a main part of Fig. 6. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 5. Fig. 9 is an enlarged cross-sectional view showing a main part of Fig. 8.

[0017] 1 to 9, semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip."

[0018] In this embodiment, the chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0019] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0020] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0021] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0022] In the following description, one side of the first direction X refers to the third side surface 5C side, and the other side of the first direction X refers to the fourth side surface 5D side. Furthermore, one side of the second direction Y refers to the first side surface 5A side, and the other side of the second direction Y refers to the second side surface 5B side. In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0023] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off-axis direction by the off-axis angle. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off-axis angle.

[0024] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0025] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0026] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer portion) on the first main surface 3 side of the chip 2. The first semiconductor region 6 may also be referred to as a "drift region," a "drain drift region," a "drain region," or the like. A drain potential as a high potential (first potential) is applied to the first semiconductor region 6. The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).

[0027] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as a "drain region," etc. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 within the chip 2.

[0028] The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.

[0029] The semiconductor device 1 includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 and spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0030] The semiconductor device 1 includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a plan view. The peripheral region 9 extends in a strip shape along the active region 8 in a plan view, and is set in a polygonal ring shape (a square ring in this embodiment) surrounding the active region 8.

[0031] The semiconductor device 1 includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 in the active region 8. A source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential). The plurality of body regions 20 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 20 are arranged in a strip shape extending in the second direction Y.

[0032] The plurality of body regions 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of body regions 20 are preferably formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The plurality of body regions 20 are exposed from the first main surface 3.

[0033] The semiconductor device 1 includes a p-type outer body region 21 formed in the peripheral region 9 in a surface layer portion of the first main surface 3. The outer body region 21 preferably has a p-type impurity concentration substantially equal to the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the outer body region 21 may be lower than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.

[0034] The outer body region 21 is formed at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip shape along the active region 8. The outer body region 21 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0035] In this embodiment, the outer body region 21 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. In other words, the outer body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4 ).

[0036] The outer body region 21 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 21 is connected to the plurality of body regions 20 in a portion extending in the first direction X. As a result, the outer body region 21 is fixed to the same potential as the plurality of body regions 20.

[0037] The outer body region 21 preferably has a width greater than that of the body region 20. The width of the body region 20 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the outer body region 21 is the width in a direction perpendicular to the extending direction. Of course, the width of the outer body region 21 may be approximately equal to the width of the body region 20 or may be less than the thickness of the body region 20.

[0038] The ratio of the width of the outer body region 21 to the width of the body region 20 may be 10 or greater and 50 or less. The width ratio is preferably 20 or greater and 40 or less.

[0039] The outer body region 21 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The outer body region 21 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.

[0040] The outer body region 21 preferably has a thickness (depth) approximately equal to the thickness (depth) of the body region 20. Of course, the thickness of the outer body region 21 may be less than the thickness of the body region 20 or may be greater than the thickness of the body region 20.

[0041] The semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed in a surface portion of the first main surface 3. In this embodiment, the plurality of surface drift regions 22 are each made of a part of the first semiconductor region 6. Of course, the plurality of surface drift regions 22 may have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6, or may have an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6.

[0042] The surface drift regions 22 are each defined in a region between adjacent body regions 20 in the first direction X. Specifically, the surface drift regions 22 are each defined by the body regions 20 and the outer body regions 21 in the surface portion of the first main surface 3. The surface drift regions 22 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. In other words, the surface drift regions 22 are formed in a stripe shape extending in the second direction Y.

[0043] The semiconductor device 1 includes a plurality of n-type source regions 23, 24 formed in the surface layer portions of the plurality of body regions 20. The plurality of source regions 23, 24 have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the plurality of source regions 23, 24.

[0044] The plurality of source regions 23, 24 include, in a surface layer portion of each body region 20, a first source region 23 located on one side in the first direction X and a second source region 24 located on the other side in the first direction X. In this embodiment, one first source region 23 is formed on one end side of the body region 20 in the first direction X, and one second source region 24 is formed on the other end side of the body region 20.

[0045] The first source region 23 is formed at a distance from one end of the body region 20 to the other end, and extends in a strip shape along the extension direction of the body region 20. The first source region 23 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the first source region 23 is not formed in the outer body region 21. The first source region 23 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the body region 20 in between.

[0046] The second source region 24 is formed at a distance from the first source region 23 on the other end side of the body region 20. The second source region 24 is formed at a distance from the other end of the body region 20 to one end side, and extends in a strip shape along the extension direction of the body region 20. The second source region 24 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the second source region 24 is not formed in the outer body region 21. The second source region 24 is formed at a distance from the bottom of the body region 20 towards the first main surface 3, and faces the first semiconductor region 6 across a part of the body region 20.

[0047] When a plurality of first source regions 23 are formed in one body region 20, the plurality of first source regions 23 may be formed at intervals in the extension direction of the body region 20. In this case, each first source region 23 may be formed in a strip shape extending in the second direction Y. Similarly, when a plurality of second source regions 24 are formed in one body region 20, the plurality of second source regions 24 may be formed at intervals in the extension direction of the body region 20. In this case, each second source region 24 may be formed in a strip shape extending in the second direction Y.

[0048] The semiconductor device 1 includes a plurality of p-type contact regions 25 formed in the surface layer portions of the plurality of body regions 20 in the active region 8. The contact regions 25 may also be referred to as "back gate regions." A source potential is applied to the plurality of contact regions 25. The contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0049] In this embodiment, one contact region 25 is interposed in a region between the first source region 23 and the second source region 24 in a surface layer portion of the corresponding body region 20. The contact region 25 extends in a strip shape along the extension direction of the body region 20 (the source regions 23, 24). The contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the contact region 25 is not formed in the outer body region 21. The contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the body region 20 in between.

[0050] When multiple contact regions 25 are formed in one body region 20, the multiple contact regions 25 may be formed at intervals in the extension direction of the body region 20. In this case, each contact region 25 may be formed in a strip shape extending in the second direction Y.

[0051] The semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 26, 27 are defined in the surface layer portions of the plurality of body regions 20, respectively, in regions between ends of the plurality of body regions 20 (a plurality of surface drift regions 22) and peripheral edges of the plurality of source regions 23, 24. In this embodiment, the plurality of channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 26, 27 are arranged in stripes extending in the second direction Y.

[0052] The plurality of channel regions 26, 27 includes a plurality of first channel regions 26 and a plurality of second channel regions 27. The plurality of first channel regions 26 are each defined as a region between one end of the plurality of body regions 20 (surface drift region 22) and the plurality of first source regions 23, and form a current path extending in the horizontal direction. The plurality of second channel regions 27 are each defined as a region between the other end of the plurality of body regions 20 (surface drift region 22) and the plurality of second source regions 24, and form a current path extending in the horizontal direction.

[0053] The semiconductor device 1 includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8. The plurality of gate structures 30 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y. The extending direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.

[0054] Each gate structure 30 is disposed on at least one channel region 26, 27. In this embodiment, each gate structure 30 is disposed across one surface drift region 22 to straddle two adjacent body regions 20, and covers a plurality of channel regions 26, 27. Specifically, each gate structure 30 is disposed across a first source region 23 on one body region 20 side and a second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0055] The configuration of one gate structure 30 will be described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The gate structure 30 does not have insulating sidewall structures (spacers) on the sides of the gate electrode 32. The insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 include a silicon oxide film made of an oxide of the chip 2.

[0056] The insulating film 31 covers the first main surface 3 in a film-like manner and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, and covers the multiple channel regions 26, 27.

[0057] Specifically, the insulating film 31 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0058] The insulating film 31 partially covers the first source region 23 at a distance from the contact region 25, and exposes a part of the first source region 23 and the contact region 25 from the first main surface 3. The insulating film 31 partially covers the second source region 24 at a distance from the contact region 25, and exposes a part of the second source region 24 and the contact region 25 from the first main surface 3.

[0059] The thickness of the insulating film 31 may be 10 nm or more and 150 nm or less. The thickness of the insulating film 31 may be a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. The thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.

[0060] The gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26, 27 across the insulating film 31. A gate potential as a control potential is applied to the gate electrode 32. The gate electrode 32 controls inversion and non-inversion of at least one of the channel regions 26, 27 in response to the gate potential.

[0061] The gate electrode 32 includes a conductive semiconductor polycrystalline. The gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted depending on the gate threshold voltage to be achieved. The gate electrode 32 may also be referred to as a "polysilicon gate," a "poly gate," or the like.

[0062] The gate electrode 32 is formed in a strip shape extending in the second direction Y. That is, the extending direction of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed spaced apart inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 so as to cross one surface drift region 22 and straddle two adjacent body regions 20, and faces the multiple channel regions 26, 27 across the insulating film 31.

[0063] Specifically, the gate electrode 32 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 across the insulating film 31.

[0064] The gate electrode 32 has an electrode upper portion 33, a first electrode side portion 34 on one side in the first direction X, and a second electrode side portion 35 on the other side in the first direction X. The electrode upper portion 33 extends along the insulating film 31 (first main surface 3). The electrode upper portion 33 may extend substantially parallel to the insulating film 31 (first main surface 3). The electrode upper portion 33 may also be referred to as an electrode upper wall.

[0065] The first electrode side portion 34 is formed at a distance from one end of the insulating film 31 to the other end in the first direction X, and extends in the vertical direction Z. The second electrode side portion 35 is formed at a distance from the other end of the insulating film 31 to the one end in the first direction X, and extends in the vertical direction Z.

[0066] The first electrode side portion 34 and the second electrode side portion 35 may extend perpendicular to the insulating film 31. That is, the gate electrode 32 may be formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view. The first electrode side portion 34 and the second electrode side portion 35 may be obliquely inclined toward the electrode upper portion 33. That is, the gate electrode 32 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view. The first electrode side portion 34 and the second electrode side portion 35 may be referred to as a first electrode sidewall and a second electrode sidewall, respectively.

[0067] The width of the gate structure 30 may be 1 μm or more and 10 μm or less. The width of the gate structure 30 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the gate structure 30 is preferably 1 μm or more and 5 μm or less.

[0068] The thickness of the gate structure 30 may be 0.1 μm or more and 2.0 μm or less, and preferably 0.2 μm or more and 1.0 μm or less.

[0069] 6 and 7 , the gate electrode 32 includes an electrode corner 41 that connects the electrode upper portion 33 to the first electrode side portion 34 and the second electrode side portion 35. The electrode corner 41 is a portion formed by removing a portion of the material of the gate electrode 32. In this embodiment, the electrode corner 41 is formed by a recess that curves inward of the gate electrode 32. As a result, the electrode upper portion 33 is partially formed on the surface portion of each gate electrode 32 in a plan view.

[0070] In plan view, the electrode upper portion 33 is formed at a distance inward from at least one of the first electrode side portion 34 and the second electrode side portion 35 of the gate electrode 32, and at least one of the peripheral edge portions on the first electrode side portion 34 side and the second electrode side portion 35 side is exposed. In this embodiment, the electrode upper portion 33 is formed at a distance inward from both the first electrode side portion 34 and the second electrode side portion 35, and both the peripheral edge portions on the first electrode side portion 34 side and the second electrode side portion 35 side are exposed in plan view.

[0071] The upper electrode portion 33 is formed in a strip shape extending along the gate electrode 32 in a plan view. That is, the extending direction of the upper electrode portion 33 coincides with the off-direction of the SiC single crystal. The upper electrode portion 33 faces one surface drift region 22 in the stacking direction. The upper electrode portion 33 may be formed at an interval toward the surface drift region 22 from two adjacent body regions 20 in a plan view, and may face only one surface drift region 22 in the stacking direction.

[0072] The electrode upper portion 33 may extend across one surface drift region 22 and across two adjacent body regions 20 in a plan view. In this case, the electrode upper portion 33 may be formed at an interval toward the surface drift region 22 from the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and may face the surface drift region 22, the first channel region 26, and the second channel region 27 in the stacking direction.

[0073] In this embodiment, the upper electrode portion 33 is formed to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 in the stacking direction.

[0074] In consideration of the response of the switching speed, it is preferable that the electrode upper portion 33 faces either one or both (preferably both) of the first channel region 26 and the second channel region 27. It is preferable that the electrode upper portion 33 faces the entire first channel region 26 in the stacking direction in a cross-sectional view. It is preferable that the electrode upper portion 33 faces the entire second channel region 27 in the stacking direction in a cross-sectional view.

[0075] The electrode corners 41 may have various layouts depending on the layout of the electrode upper parts 33. When the electrode upper parts 33 are formed at an interval inward from at least one of the first electrode side parts 34 and the second electrode side parts 35 of the gate electrode 32 in a plan view, the electrode corners 41 are formed in regions on at least one side of the first electrode side parts 34 and the second electrode side parts 35.

[0076] In this embodiment, the electrode upper portion 33 is formed at a distance inward from both the first electrode side portion 34 and the second electrode side portion 35 of the gate electrode 32. Therefore, the electrode corner portion 41 has one electrode corner portion 41A defined in an area on the first electrode side portion 34 side of the electrode upper portion 33, and the other electrode corner portion 41B defined in an area on the second electrode side portion 35 side of the electrode upper portion 33 (see FIGS. 5 and 7 ).

[0077] One electrode corner 41A continues from the peripheral edge on one side of the electrode upper portion 33 to the first electrode side portion 34. One electrode corner 41A extends in a strip shape in the second direction Y along the electrode upper portion 33. The other electrode corner 41B continues from the peripheral edge on the other side of the electrode upper portion 33 to the second electrode side portion 35. The other electrode corner 41B faces the one electrode corner 41A in the first direction X across the electrode upper portion 33, and extends in a strip shape in the second direction Y along the electrode upper portion 33.

[0078] One electrode corner 41A faces the first source region 23 in the stacking direction. One electrode corner 41A may face only the first source region 23 in the stacking direction. One electrode corner 41A may face the first source region 23 and the first channel region 26 in the stacking direction. One electrode corner 41A may face the surface drift region 22, the first source region 23, and the first channel region 26 in the stacking direction.

[0079] In consideration of the response of the switching speed, it is preferable that one of the electrode corner portions 41A is formed at a distance from the first channel region 26 toward the first electrode side portion 34 in a plan view. In other words, it is preferable that one of the electrode corner portions 41A does not face the first channel region 26 in the stacking direction in a cross-sectional view.

[0080] The other electrode corner 41B faces the second source region 24 in the stacking direction. The other electrode corner 41B may face only the second source region 24 in the stacking direction. The other electrode corner 41B may face the second source region 24 and the second channel region 27 in the stacking direction. The other electrode corner 41B may face the surface drift region 22, the second source region 24, and the second channel region 27 in the stacking direction.

[0081] In consideration of the response of the switching speed, it is preferable that the other electrode corner 41B is formed at a distance from the second channel region 27 toward the second electrode side portion 35 in a plan view. In other words, it is preferable that the other electrode corner 41B does not face the second channel region 27 in the stacking direction in a cross-sectional view.

[0082] 4 , 5 , and 8 , semiconductor device 1 includes a p-type termination region 45 formed on first main surface 3 in peripheral region 9. Termination region 45 may also be referred to as a “well region,” “termination well region,” or the like. Termination region 45 may have a p-type impurity concentration substantially equal to the p-type impurity concentration of outer body region 21. The p-type impurity concentration of termination region 45 may be higher than the p-type impurity concentration of outer body region 21, or may be lower than the p-type impurity concentration of outer body region 21.

[0083] Termination region 45 is spaced inward from the periphery of first main surface 3 and is formed in a region between the periphery of first main surface 3 and outer body region 21. Termination region 45 extends in a band shape along outer body region 21 in a plan view. Termination region 45 has a portion extending in a band shape in first direction X and a portion extending in a band shape in second direction Y in a plan view, and defines active region 8 from multiple directions.

[0084] In this embodiment, the termination region 45 surrounds the outer body region 21 in a plan view and is defined as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The termination region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4 ).

[0085] The termination region 45 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The termination region 45 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The termination region 45 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21. The thickness of the termination region 45 may be greater than or less than the thickness of the outer body region 21.

[0086] The termination region 45 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3. The inner edge of the termination region 45 is connected to the outer edge of the outer body region 21. As a result, the termination region 45 is fixed to the same potential as the outer body region 21 and is electrically connected to the plurality of body regions 20 via the outer body region 21. In this embodiment, the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21 along the entire periphery.

[0087] The termination region 45 (inner edge portion) has an overlap region 46 that overlaps the outer edge portion of the outer body region 21. The overlap region 46 is a high-concentration region that includes the outer edge portion of the outer body region 21 and the inner edge portion of the termination region 45. In other words, the overlap region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 45, and has a p-type impurity concentration that is higher than both the p-type impurity concentrations of the outer body region 21 and the termination region 45.

[0088] The overlap region 46 extends in a band shape along the outer body region 21 in a plan view. The overlap region 46 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, thereby partitioning the active region 8 from multiple directions. In this embodiment, the overlap region 46 is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3. The width of the overlap region 46 is preferably greater than the width of the body region 20. Of course, the width of the overlap region 46 may be equal to or less than the width of the body region 20.

[0089] The semiconductor device 1 may have a relatively high-concentration p-type well region (46) instead of the overlap region 46. In this case, the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45. The well region (46) may be formed in either or both of the surface layer portion of the outer body region 21 and the surface layer portion of the termination region 45.

[0090] The semiconductor device 1 includes at least one (preferably two to 20) p-type field region 47 formed in the surface layer portion of the first main surface 3 in the peripheral region 9. The number of the multiple field regions 47 is typically three to eight. In this embodiment, the semiconductor device 1 includes three field regions 47. The multiple field regions 47 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, spacing, width, depth, p-type impurity concentration, etc. of the field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0091] The field region 47 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20 (termination region 45). The p-type impurity concentration of the field region 47 may be higher than the p-type impurity concentration of the body region 20 (termination region 45), or may be lower than the p-type impurity concentration of the body region 20 (termination region 45).

[0092] The plurality of field regions 47 are formed inwardly from the periphery of the first main surface 3 at intervals inward from the periphery of the first main surface 3 in a region between the periphery of the first main surface 3 and the active region 8. Specifically, the plurality of field regions 47 are formed in a region between the periphery of the first main surface 3 and the outer body region 21. More specifically, the plurality of field regions 47 are arranged in a region between the periphery of the first main surface 3 and the termination region 45 at intervals on the periphery side of the first main surface 3 from the termination region 45.

[0093] The field regions 47 are formed in strip shapes extending along the active region 8 (termination region 45) in plan view. Each of the field regions 47 has a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the field regions 47 are formed in polygonal ring shapes (quadrilateral ring shapes in this embodiment) surrounding the active region 8 (termination region 45) in plan view. The field regions 47 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0094] The plurality of field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of field regions 47 are preferably formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3.

[0095] 8, the semiconductor device 1 includes a peripheral insulating film 51 that covers the first main surface 3 in the peripheral region 9. The peripheral insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the peripheral insulating film 51 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 51 includes a silicon oxide film made of an oxide of the chip 2. The peripheral insulating film 51 is preferably made of the same insulating material as the insulating material of the insulating film 31. The peripheral insulating film 51 preferably has a thickness approximately equal to that of the insulating film 31.

[0096] The peripheral insulating film 51 covers the first main surface 3 in the peripheral region 9 in a film-like manner. The peripheral insulating film 51 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47. The peripheral insulating film 51 is connected to the plurality of insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is formed integrally with the plurality of insulating films 31, and together with the plurality of insulating films 31, forms a single insulating film.

[0097] 4, 5, and 8, the semiconductor device 1 includes a gate wiring 52 arranged on the first main surface 3 in the peripheral region 9. The semiconductor device 1 does not have insulating sidewall structures (spacers) on the sides of the gate wiring 52. The gate wiring 52 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the plurality of gate electrodes 32. The gate wiring 52 is connected to the plurality of gate electrodes 32 and applies gate signals to the plurality of gate electrodes 32. The gate wiring 52 may also be referred to as a "polysilicon gate wiring," a "poly gate wiring," a "second gate electrode," or the like.

[0098] The gate wiring 52 includes a conductive semiconductor polycrystalline. The gate wiring 52 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 52 preferably has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is adjusted according to the conductivity type of the gate electrode 32.

[0099] The gate wiring 52 is disposed on the peripheral insulating film 51 in the peripheral region 9. Specifically, the gate wiring 52 is disposed on a portion of the peripheral insulating film 51 that covers the outer body region 21, and faces the outer body region 21 across the peripheral insulating film 51. The gate wiring 52 is formed at a distance from the periphery of the first main surface 3 toward the active region 8, and extends in a strip shape along the active region 8. The gate wiring 52 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0100] In this embodiment, the gate wiring 52 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The gate wiring 52 may be terminated or endless. In this embodiment, the gate wiring 52 extends in a strip shape (a ring shape in this embodiment) along the outer body region 21 in a plan view and faces the outer body region 21 across the outer insulating film 51 over the entire area in the stacking direction. The gate wiring 52 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0101] The gate wiring 52 is formed to be narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21. That is, in this embodiment, the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 52 is connected to the multiple gate electrodes 32 above the outer body region 21.

[0102] The width of the gate wiring 52 is preferably larger than the width of the gate electrode 32. The width of the gate wiring 52 is the width in a direction perpendicular to the extending direction. Of course, the width of the gate wiring 52 may be equal to or smaller than the width of the gate electrode 32. The width of the gate wiring 52 may be larger than the width of the outer body region 21. The thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.

[0103] The gate wiring 52 has a wiring upper portion 53, a first wiring side portion 54 on the inner edge side, and a second wiring side portion 55 on the outer edge side. The wiring upper portion 53 extends along the peripheral insulating film 51 (first main surface 3). The wiring upper portion 53 may extend substantially parallel to the peripheral insulating film 51 (first main surface 3). The wiring upper portion 53 may also be referred to as a wiring upper wall. The first wiring side portion 54 extends in the vertical direction Z on the peripheral insulating film 51, and the second wiring side portion 55 extends in the vertical direction Z on the peripheral insulating film 51.

[0104] The first wiring side 54 is connected to the plurality of gate electrodes 32 (the first electrode side 34 and the second electrode side 35) in a portion extending in the first direction X. In other words, the gate wiring 52 has a plurality of portions connected in a T-shape to the plurality of gate electrodes 32. As a result, the gate wiring 52 is fixed to the same potential as the plurality of gate electrodes 32.

[0105] The first wiring side 54 and the second wiring side 55 may extend perpendicular to the peripheral insulating film 51. That is, the gate wiring 52 may be formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view. The first wiring side 54 and the second wiring side 55 may be obliquely inclined toward the wiring upper portion 53. That is, the gate wiring 52 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view. The first wiring side 54 and the second wiring side 55 may be referred to as a first wiring sidewall and a second wiring sidewall, respectively.

[0106] 8 and 9 , the gate wiring 52 includes a wiring corner 61 that connects the wiring upper portion 53 to the first wiring side portion 54 and the second wiring side portion 55. The wiring corner 61 is a portion formed by removing a portion of the material of the gate wiring 52. In this embodiment, the wiring corner 61 is formed by a recess that curves inwardly of the gate wiring 52. As a result, the wiring upper portion 53 is partially formed on the surface portion of each gate wiring 52 in a plan view.

[0107] In a plan view, the wiring upper portion 53 is formed at a distance inward from at least one of the first wiring side portion 54 and the second wiring side portion 55 of the gate wiring 52, and at least one of the peripheral edge portions on the first wiring side portion 54 side and the second wiring side portion 55 side is exposed in the wiring upper portion 53. In this embodiment, the wiring upper portion 53 is formed at a distance inward from both the first wiring side portion 54 and the second wiring side portion 55, and both the peripheral edge portions on the first wiring side portion 54 side and the second wiring side portion 55 side are exposed in the wiring upper portion 53.

[0108] The wiring upper portion 53 extends in a strip shape along the gate wiring 52 in a plan view and faces the outer body region 21 in the stacking direction. The wiring upper portion 53 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view. In this embodiment, the wiring upper portion 53 surrounds the active region 8 in a plan view and is defined in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0109] The wiring upper portion 53 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view.

[0110] The wiring upper portion 53 is continuous with the plurality of electrode upper portions 33 at the connection portion between the plurality of gate electrodes 32 and the gate wiring 52. In other words, the wiring upper portion 53 is formed integrally with the plurality of electrode upper portions 33, and has a plurality of portions connected in a T-shape to the plurality of electrode upper portions 33 (see FIG. 5 ).

[0111] The wiring corner 61 may have various layouts depending on the layout of the wiring upper portion 53. When the wiring upper portion 53 is formed spaced inward from at least one of the first wiring side portion 54 and the second wiring side portion 55 of the gate wiring 52, the wiring corner 61 is formed in a region of the wiring upper portion 53 on at least one side of the first wiring side portion 54 and the second wiring side portion 55.

[0112] In this embodiment, the wiring upper portion 53 is formed at a distance inward from both the first wiring side portion 54 and the second wiring side portion 55 of the gate wiring 52. Therefore, the wiring corner portion 61 has one wiring corner portion 61A defined in an area on the first wiring side portion 54 side of the wiring upper portion 53, and the other wiring corner portion 61B defined in an area on the second wiring side portion 55 side of the wiring upper portion 53 (see FIGS. 5 and 9 ).

[0113] One wiring corner 61A continues from the peripheral edge on one side of the wiring upper portion 53 to the first wiring side portion 54 of the gate wiring 52. One wiring corner 61A extends in a band shape along the wiring upper portion 53. The other wiring corner 61B continues from the other side of the wiring upper portion 53 to the second wiring side portion 55 of the gate wiring 52. The other wiring corner 61B faces the wiring corner 61B on one side across the wiring upper portion 53, and extends in a band shape along the wiring upper portion 53.

[0114] The wiring corner 61 (one wiring corner 61A) is continuous with the plurality of electrode corners 41 at the connection portion of the plurality of gate electrodes 32 and gate wiring 52. In other words, the wiring corner 61 is formed integrally with the plurality of electrode corners 41. The wiring corner 61 has a plurality of portions that are connected in an L-shape to the plurality of electrode corners 41 at the connection corner portion of the plurality of gate electrodes 32 and gate wiring 52 (see FIG. 5 ).

[0115] The semiconductor device 1 includes an insulating interlayer film 70 that covers the first main surface 3. The interlayer film 70 may also be referred to as an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 70 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.

[0116] The interlayer film 70 covers the multiple gate structures 30 in the active region 8. The interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32 for each gate structure 30. In other words, the interlayer film 70 has portions that directly cover the electrode upper portion 33, the first electrode side portion 34, the second electrode side portion 35, and the electrode corner portion 41 of the gate electrode 32.

[0117] The interlayer film 70 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 therebetween. The interlayer film 70 directly covers both the peripheral insulating film 51 and the gate wiring 52. That is, the interlayer film 70 has portions that directly cover the wiring upper portion 53, the first wiring side portion 54, the second wiring side portion 55, and the wiring corner portion 61 of the gate wiring 52. In this embodiment, the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 70 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral portion of the first main surface 3 (the first semiconductor region 6).

[0118] In this embodiment, the interlayer film 70 has a layered structure including a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) stacked in this order from the first main surface 3 side. The first oxide film 72 has a single-layer structure made of a silicon oxide film with no added impurities. The first oxide film 72 may also be referred to as an NSG film (nondoped silicate glass film).

[0119] The first oxide film 72 collectively covers the active region 8 and the peripheral region 9. The first oxide film 72 collectively covers the plurality of gate structures 30 in the active region 8. The first oxide film 72 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.

[0120] The first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76. The first covering portion 74 extends horizontally in a film shape along the insulating film 31 (first main surface 3), and has a portion that contacts the first electrode side portion 34 (second electrode side portion 35) of the gate electrode 32. In this embodiment, the first covering portion 74 (first oxide film 72) has a thickness less than the thickness of the gate electrode 32, and covers the insulating film 31 at a distance from the height position of the electrode upper portion 33 of the gate electrode 32 toward the insulating film 31.

[0121] The second covering portion 75 is drawn out from the first covering portion 74 toward the electrode upper portion 33 in the stacking direction, and directly covers the first electrode side portion 34 (second electrode side portion 35) and the electrode corner portion 41 in a film-like manner.

[0122] The third covering portion 76 is drawn out from the second covering portion 75 toward the electrode upper portion 33 and extends in a film-like manner in the horizontal direction along the electrode upper portion 33. The third covering portion 76 directly covers the entire area of ​​the electrode upper portion 33 between one electrode corner portion 41A and the other electrode corner portion 41B.

[0123] In the peripheral region 9, the first oxide film 72 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47 with the peripheral insulating film 51 sandwiched therebetween. The first oxide film 72 covers the gate wiring 52 in the peripheral region 9.

[0124] The first oxide film 72 has a first wire-coating portion 77, a second wire-coating portion 78, and a third wire-coating portion 79. The first wire-coating portion 77 extends horizontally in the form of a film along the peripheral insulating film 51 (first main surface 3), and has a portion that contacts the first wire side portion 54 (second wire side portion 55) of the gate wiring 52. In this embodiment, the first wire-coating portion 77 (first oxide film 72) has a thickness less than the thickness of the gate wiring 52, and covers the peripheral insulating film 51 at a distance from the height position of the wiring upper portion 53 of the gate wiring 52 toward the peripheral insulating film 51.

[0125] The second wiring coating portion 78 is pulled out from the first wiring coating portion 77 toward the wiring upper portion 53 in the stacking direction, and directly coats the first electrode side portion 34 (second electrode side portion 35) and the wiring corner portion 61 in a film-like manner.

[0126] The third wire coating 79 is drawn out from the second wire coating 78 toward the wire upper portion 53 and extends in a film-like manner in the horizontal direction along the wire upper portion 53. The third wire coating 79 directly covers the entire area of ​​the wire upper portion 53 between one wire corner 61A and the other wire corner 61B.

[0127] The second oxide film 73 may have a single-layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass Film). The silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass Film).

[0128] The second oxide film 73 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 72. The second oxide film 73 may have a layered structure including a PSG film stacked on the first oxide film 72 and a BPSG film stacked on the PSG film. The second oxide film 73 may have a layered structure including a BPSG film stacked on the first oxide film 72 and a PSG film stacked on the BPSG film. In this embodiment, the second oxide film 73 has a single layer structure made of a PSG film, for example.

[0129] The second oxide film 73 covers the first oxide film 72 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 72 sandwiched therebetween. The second oxide film 73 collectively covers the plurality of gate structures 30 in the active region 8 with the first oxide film 72 sandwiched therebetween. Specifically, the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 72 sandwiched therebetween.

[0130] The second oxide film 73 includes a first upper covering portion 80 and a second upper covering portion 81. The first upper covering portion 80 covers the first covering portion 74 and the second covering portion 75 of the first oxide film 72. The first upper covering portion 80 covers the insulating film 31 in a portion located above the first covering portion 74, with the first covering portion 74 sandwiched between them.

[0131] The first upper covering portion 80 extends in a film shape in the stacking direction from above the first covering portion 74 along the second covering portion 75, and covers the first electrode side portion 34 (second electrode side portion 35) and electrode corner portion 41 of the gate structure 30 with the second covering portion 75 in between. In other words, the first upper covering portion 80 has portions that cover the first electrode side portion 34 (second electrode side portion 35) and electrode corner portion 41 with the second covering portion 75 in between.

[0132] The second upper covering portion 81 covers the third covering portion 76 of the first oxide film 72. The second upper covering portion 81 extends horizontally in the form of a film along the third covering portion 76 from the first upper covering portion 80, and covers the upper electrode portion 33 of the gate structure 30 with the third covering portion 76 in between. The second upper covering portion 81 covers the entire upper electrode portion 33 with the third covering portion 76 in between one electrode corner 41A and the other electrode corner 41B.

[0133] The second upper covering portion 81 has a portion that covers the upper portion 33 of the electrode with the first oxide film 72 (third covering portion 76) sandwiched therebetween, and a portion that covers the electrode corner portion 41 with the first oxide film 72 (second covering portion 75) sandwiched therebetween.

[0134] In the peripheral region 9, the second oxide film 73 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47, sandwiching the peripheral insulating film 51 and the first oxide film 72 therebetween. In the peripheral region 9, the second oxide film 73 covers the gate wiring 52, sandwiching the first oxide film 72 therebetween.

[0135] The second oxide film 73 includes a first upper wire-coating portion 82 and a second upper wire-coating portion 83. The first upper wire-coating portion 82 coats the first wire-coating portion 77 and the second wire-coating portion 78 of the first oxide film 72. The first upper wire-coating portion 82 coats the peripheral insulating film 51 in a portion located above the first wire-coating portion 77, with the first wire-coating portion 77 sandwiched therebetween.

[0136] The first upper wire coating 82 extends in a film-like shape in the stacking direction from above the first wire coating 77 along the second wire coating 78, and covers the first wire side 54 (second wire side 55) and the wire corner 61 with the second wire coating 78 in between. In other words, the first upper wire coating 82 has portions that cover the first wire side 54 (second wire side 55) and the wire corner 61 with the second wire coating 78 in between.

[0137] The second upper wire coating portion 83 coats the third wire coating portion 79 of the first oxide film 72. The second upper wire coating portion 83 extends in a film-like manner in the horizontal direction from the first upper wire coating portion 82 along the third wire coating portion 79, and coats the wire upper portion 53 with the third wire coating portion 79 in between. The second upper wire coating portion 83 coats the entire wire upper portion 53 with the third wire coating portion 79 in between one wire corner portion 61A and the other wire corner portion 61B.

[0138] The second upper wiring coating portion 83 has a portion that covers the upper portion 53 of the wiring by sandwiching the first oxide film 72 (third wiring coating portion 79), and a portion that covers the corner portion 61 of the wiring by sandwiching the first oxide film 72 (second wiring coating portion 78).

[0139] The semiconductor device 1 includes a plurality of source openings 90 formed in the interlayer film 70 in the active region 8. The plurality of source openings 90 are formed in regions on the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2). Specifically, the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32, respectively, and penetrate the insulating film 31 and the interlayer film 70.

[0140] The plurality of source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73. The plurality of source openings 90 expose the corresponding plurality of source regions 23, 24 and contact regions 25, respectively.

[0141] In this embodiment, the source openings 90 are formed at intervals in the first direction X and in stripes extending in the second direction Y. That is, the source openings 90 are formed in stripes extending in the second direction Y. The source openings 90 are formed at intervals from the gate wiring 52 in the second direction Y. That is, the source openings 90 are formed in a region surrounded by the gate electrodes 32 and the gate wiring 52.

[0142] A plurality of source openings 90 may be formed in a region between two gate structures 30 adjacent to each other in the first direction X. In this case, the plurality of source openings 90 may be formed in a line at intervals in the second direction Y. Furthermore, in this case, each source opening 90 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.

[0143] The source opening 90 may have a width W of 0.2 μm or more and 3 μm or less. The width W of the source opening 90 is preferably 0.3 μm or more and 1 μm or less. The source opening 90 may have a depth D of 0.2 μm or more and 2 μm or less. The depth D of the source opening 90 is preferably 0.5 μm or more and 1 μm or less.

[0144] The source opening 90 preferably has an aspect ratio D / W of 0.3 or more and 3 or less. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 90 to the width W of the source opening 90. The aspect ratio D / W is preferably 0.5 or more and 2 or less. It is particularly preferable that the aspect ratio D / W exceeds 1. According to this configuration, the multiple gate structures 30 are arranged at a narrow pitch.

[0145] The semiconductor device 1 includes a plurality of source recesses 91 formed in the first main surface 3 in portions exposed from the plurality of source openings 90. The semiconductor device 1 does not necessarily have to have the source recesses 91. Therefore, a configuration not including the source recesses 91 may be employed.

[0146] The plurality of source recesses 91 each have a planar shape that matches the planar shape of the corresponding source opening 90, and are recessed from the first main surface 3 toward the second main surface 4. The plurality of source recesses 91 are formed at intervals from the bottoms of the corresponding body regions 20 toward the first main surface 3, and expose the corresponding plurality of source regions 23, 24 and contact regions 25. Specifically, the plurality of source recesses 91 are formed at intervals from the bottoms of the corresponding plurality of source regions 23, 24 (contact regions 25) toward the first main surface 3.

[0147] The semiconductor device 1 includes at least one outer opening 92 (a plurality of outer openings in this embodiment) formed in the interlayer film 70 in the peripheral region 9. The plurality of outer openings 92 are formed in a portion of the interlayer film 70 that covers the termination region 45. The plurality of outer openings 92 penetrate the interlayer film 70 to expose the termination region 45. In this embodiment, the plurality of outer openings 92 are formed in a portion of the interlayer film 70 that covers the overlap region 46 of the termination region 45 to expose the overlap region 46.

[0148] The outer openings 92 may expose the outer body region 21 instead of or in addition to the termination region 45 (overlap region 46). The outer openings 92 penetrate both the first oxide film 72 and the second oxide film 73 and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73.

[0149] The outer openings 92 are spaced apart along the termination region 45 (overlap region 46) (see FIGS. 4 and 5). The outer openings 92 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The outer openings 92 may be formed in a strip shape extending along the termination region 45 (overlap region 46) in a plan view. The outer openings 92 may have an aspect ratio D / W (preferably greater than 1), similar to the source openings 90.

[0150] The semiconductor device 1 may have a single outer opening 92. The single outer opening 92 may be formed in a strip shape extending along the termination region 45 (overlap region 46). The single outer opening 92 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0151] The single outer opening 92 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single outer opening 92 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the termination region 45 (overlap region 46) in a plan view.

[0152] The semiconductor device 1 includes a plurality of outer recesses 93 formed in the first main surface 3 in the portions exposed from the plurality of outer openings 92. The semiconductor device 1 does not necessarily have to have the outer recesses 93. Therefore, a configuration not having the outer recesses 93 may be employed.

[0153] The multiple outer recesses 93 each have a planar shape that matches the planar shape of the corresponding outer opening 92, and are recessed from the first main surface 3 toward the second main surface 4. The multiple outer recesses 93 are formed at intervals from the bottom of the termination region 45 (overlap region 46) toward the first main surface 3, and each exposes the termination region 45 (overlap region 46). When a single outer opening 92 is formed, a single outer recess 93 that matches the planar shape of the single outer opening 92 is formed.

[0154] The semiconductor device 1 includes at least one gate opening 94 (in this embodiment, a plurality of gate openings 94) formed in the interlayer film 70 in the peripheral region 9. The plurality of gate openings 94 are formed in a portion of the interlayer film 70 that covers the gate wiring 52. The plurality of gate openings 94 penetrate the interlayer film 70 and expose the wiring upper portion 53 of the gate wiring 52.

[0155] Specifically, the multiple gate openings 94 expose the wiring upper portions 53 of the gate wiring 52. More specifically, the multiple gate openings 94 expose the wiring upper portions 53 at intervals inward from the wiring corner portions 61. The multiple gate openings 94 expose only the wiring upper portions 53, and do not expose the wiring corner portions 61. Of course, one or more gate openings 94 exposing the wiring corner portions 61 may be formed.

[0156] The plurality of gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73 and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73 .

[0157] The multiple gate openings 94 are formed at intervals along the gate wiring 52 (wiring upper portion 53) (see FIGS. 4 and 5). The multiple gate openings 94 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The multiple gate openings 94 may be formed in a strip shape extending along the gate wiring 52 in a plan view. Like the source openings 90, the gate openings 94 may have an aspect ratio D / W (preferably greater than 1).

[0158] The semiconductor device 1 may have a single gate opening 94. The single gate opening 94 may be formed in a strip shape extending along the gate wiring 52. The single gate opening 94 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0159] The single gate opening 94 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single gate opening 94 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the gate wiring 52 (wiring upper portion 53) in a plan view.

[0160] 1 and other figures, the semiconductor device 1 includes a source pad electrode 95 disposed on the interlayer film 70. The source pad electrode 95 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 95 may also be referred to as a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0161] The source pad electrode 95 is disposed on a portion of the interlayer film 70 that covers the active region 8. The source pad electrode 95 covers the plurality of gate electrodes 32 with the interlayer film 70 in between, and is electrically separated from the plurality of gate electrodes 32 by the interlayer film 70. The source pad electrode 95 is electrically connected to the plurality of body regions 20, the outer body region 21, the plurality of source regions 23 and 24, the contact region 25, etc. via the plurality of source openings 90.

[0162] In this embodiment, the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98. The first pad portion 96 has a relatively large planar area and forms the main body of the source pad electrode 95. In this embodiment, the first pad portion 96 is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the active region 8. The first pad portion 96 covers the multiple gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the multiple body regions 20 and the like via the multiple source openings 90.

[0163] The second pad portion 97 has a planar area smaller than that of the first pad portion 96, and is drawn out in a strip shape (rectangular shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The second pad portion 97 covers the plurality of gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 90.

[0164] The third pad portion 98 has a plane area smaller than that of the first pad portion 96, and is drawn out in a strip shape (rectangular shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 97 in the second direction Y. The third pad portion 98 covers the plurality of gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 90.

[0165] The planar area of ​​the third pad portion 98 may be approximately equal to the planar area of ​​the second pad portion 97. Of course, the planar area of ​​the third pad portion 98 may be larger than the planar area of ​​the second pad portion 97, or may be smaller than the planar area of ​​the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 may be used as a terminal portion for monitoring a current.

[0166] The source pad electrode 95 does not necessarily have to have both the second pad portion 97 and the third pad portion 98. The source pad electrode 95 may have only one of the second pad portion 97 and the third pad portion 98. Of course, the source pad electrode 95 may be made up of only the first pad portion 96, and may not have the second pad portion 97 or the third pad portion 98.

[0167] 6 and 7, the source pad electrode 95 includes a first underlying electrode film 100 and a first main electrode film 102. The first underlying electrode film 100 may be referred to as a "source underlying electrode film," and the first main electrode film 102 may be referred to as a "source main electrode film."

[0168] The first underlying electrode film 100 forms a lower layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98), and covers the interlayer film 70 in the active region 8. The first underlying electrode film 100 collectively covers the region of the interlayer film 70 where the multiple source openings 90 are formed. In other words, the first underlying electrode film 100 extends from above the interlayer film 70 into the multiple source openings 90.

[0169] The first base electrode film 100 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the plurality of source openings 90 in a film-like manner. The first base electrode film 100 defines recesses in each of the plurality of source openings 90. The first base electrode film 100 may have a portion that partially covers the gate wiring 52 with the interlayer film 70 sandwiched therebetween. The first base electrode film 100 may be formed spaced inward from the gate wiring 52 in a plan view.

[0170] 7, in this embodiment, the first base electrode film 100 has a laminated structure including a first electrode film 103 laminated on the interlayer film 70 and a second electrode film 104 laminated on the first electrode film 103. In this embodiment, the first electrode film 103 includes a Ti film, and the second electrode film 104 includes a TiN film.

[0171] The first base electrode film 100 does not necessarily have a laminated structure, but may have a single-layer structure consisting of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film). The thickness of the first electrode film 103 may be 10 nm or more and 100 nm or less. The thickness of the second electrode film 104 may be 50 nm or more and 200 nm or less.

[0172] The first electrode film 103 collectively covers the region of the interlayer film 70 where the multiple source openings 90 are formed, and extends into the multiple source openings 90 from above the interlayer film 70. The first electrode film 103 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner. The first electrode film 103 directly covers the interlayer film 70.

[0173] That is, the first electrode film 103 directly covers the second oxide film 73. The first electrode film 103 faces the plurality of gate electrodes 32 with the interlayer film 70 interposed therebetween.

[0174] The first electrode film 103 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73. The first electrode film 103 faces the first electrode side 34 (second electrode side 35) of the gate electrode 32 with the interlayer film 70 interposed therebetween.

[0175] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the plurality of source regions 23, 24 and the contact region 25.

[0176] The first electrode film 103 may cover the source recess 91 in a film-like manner at a distance from the height position of the first main surface 3 to the bottom side of the source recess 91. The first electrode film 103 may have a portion located on the bottom side of the source recess 91 relative to the height position of the first main surface 3, and a portion located on the insulating film 31 side relative to the height position of the first main surface 3.

[0177] The second electrode film 104 collectively covers, in a film form, the region of the interlayer film 70 on the first electrode film 103 where the multiple source openings 90 are formed. The second electrode film 104 has a portion that covers, in a film form, the upper surface of the interlayer film 70 with the first electrode film 103 in between, and a portion that covers, in a film form, the wall surfaces of the multiple source openings 90 with the first electrode film 103 in between. The second electrode film 104 faces the multiple gate electrodes 32 with the first electrode film 103 and the interlayer film 70 in between.

[0178] The second electrode film 104 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 interposed therebetween. The second electrode film 104 faces the first electrode side 34 (second electrode side 35) of the gate electrode 32 with the first electrode film 103 and the interlayer film 70 interposed therebetween.

[0179] The second electrode film 104 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, sandwiching the first electrode film 103 therebetween, and is electrically connected to the plurality of source regions 23, 24 and the contact region 25 via the first electrode film 103. When the first electrode film 103 is located on the bottom side of the source recess 91 with respect to the first main surface 3, the second electrode film 104 may have a portion that is located within the source recess 91. When the first electrode film 103 has a portion that is located above the first main surface 3, the entire second electrode film 104 is located above the source recess 91.

[0180] The first main electrode film 102 forms an upper layer of the source pad electrode 95 (the first pad portion 96, the second pad portion 97, and the third pad portion 98), and covers the first base electrode film 100 in a film form. The first main electrode film 102 contains a conductive material different from the conductive material of the first base electrode film 100.

[0181] The first main electrode film 102 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 100.

[0182] The thickness of the first main electrode film 102 may be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 102 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0183] The first main electrode film 102 extends into the multiple source openings 90 from above the interlayer film 70, and is mechanically and electrically connected to the multiple source regions 23, 24 and the contact region 25. As a result, the first main electrode film 102 faces the multiple gate electrodes 32 with the first base electrode film 100 and the interlayer film 70 interposed therebetween. In other words, the first main electrode film 102 faces the electrode upper portions 33 and electrode corner portions 41 of each gate electrode 32 with the first base electrode film 100 and the interlayer film 70 interposed therebetween.

[0184] Semiconductor device 1 includes source finger electrodes 110 extending from source pad electrode 95 onto peripheral region 9. Source finger electrode 110 transmits a source potential applied to source pad electrode 95 to peripheral region 9. In this embodiment, source finger electrode 110 is routed from a portion of source pad electrode 95 (first pad portion 96) on the fourth side surface 5D side onto a portion of interlayer film 70 covering peripheral region 9.

[0185] Source finger electrodes 110 are extended onto termination region 45 and electrically connected to termination region 45 through a plurality of outer openings 92. Specifically, source finger electrodes 110 are electrically connected to overlap region 46 of termination region 45 through a plurality of outer openings 92.

[0186] The source finger electrodes 110 extend in a strip shape along the termination region 45 (overlap region 46). In plan view, the source finger electrodes 110 have a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the source finger electrodes 110 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surround the source pad electrode 95. The source finger electrodes 110 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in plan view (see FIG. 4 ).

[0187] Like the source pad electrode 95, the source finger electrode 110 includes a first underlying electrode film 100 and a first main electrode film 102. The first underlying electrode film 100 forms a lower layer portion of the source finger electrode 110 and covers the interlayer film 70 in the peripheral region 9.

[0188] The first underlying electrode film 100 collectively covers, in a film-like manner, the regions of the interlayer film 70 where the multiple outer openings 92 are formed. That is, the first underlying electrode film 100 extends from above the interlayer film 70 into the multiple outer openings 92. The first underlying electrode film 100 has a portion that covers, in a film-like manner, the upper surface of the interlayer film 70, and a portion that covers, in a film-like manner, the wall surfaces of the multiple outer openings 92. The first underlying electrode film 100 defines recesses within the multiple outer openings 92.

[0189] Similar to the source pad electrode 95, the first base electrode film 100 has a laminated structure including a first electrode film 103 and a second electrode film 104. The first electrode film 103 collectively covers the region of the interlayer film 70 where the multiple outer openings 92 are formed, and extends into the multiple outer openings 92 from above the interlayer film 70. In other words, the first electrode film 103 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.

[0190] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 103 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the termination region 45 (overlap region 46) within the outer recess 93.

[0191] The first electrode film 103 may cover the outer recess 93 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the outer recess 93. The first electrode film 103 may have a portion located on the bottom side of the outer recess 93 relative to the height position of the first main surface 3, and a portion located on the peripheral insulating film 51 side relative to the height position of the first main surface 3.

[0192] The second electrode film 104 is located on the first electrode film 103 and collectively covers the region of the interlayer film 70 where the multiple outer openings 92 are formed. That is, the second electrode film 104 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner with the first electrode film 103 in between, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner with the first electrode film 103 in between.

[0193] The second electrode film 104 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, sandwiching the first electrode film 103 therebetween, and is electrically connected to the termination region 45 (overlapping region 46) via the first electrode film 103. When the first electrode film 103 is located on the bottom side of the outer recess 93 with respect to the first main surface 3, the second electrode film 104 may have a portion that is located within the outer recess 93. When the first electrode film 103 has a portion that is located above the first main surface 3, the entire second electrode film 104 is located above the outer recess 93.

[0194] The first main electrode film 102 forms an upper layer of the source finger electrode 110, and covers the first base electrode film 100 in a film form. The first main electrode film 102 enters the outer openings 92 from above the interlayer film 70, and is mechanically and electrically connected to the termination region 45 (overlap region 46).

[0195] The semiconductor device 1 includes gate finger electrodes 115 selectively routed on the interlayer film 70. The gate finger electrodes 115 transmit a gate potential to the gate wiring 52. The gate finger electrodes 115 are routed on a portion of the interlayer film 70 that covers the gate wiring 52 (i.e., on the outer periphery region 9), and are electrically connected to the gate wiring 52 through a plurality of gate openings 94.

[0196] The gate finger electrode 115 is disposed in a region between the source pad electrode 95 and the source finger electrode 110 and is spaced apart from the source pad electrode 95 and the source finger electrode 110. The gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip shape along the gate wiring 52. The gate finger electrode 115 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0197] In this embodiment, the gate finger electrode 115 is formed in a band shape with four sides parallel to the periphery of the first main surface 3 and surrounds the source pad electrode 95. The gate finger electrode 115 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The gate finger electrode 115 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 110 passes.

[0198] 9 , the gate finger electrode 115 includes a second underlying electrode film 120 and a second main electrode film 122. The second underlying electrode film 120 may be referred to as a “gate underlying electrode film,” and the second main electrode film 122 may be referred to as a “gate main electrode film.”

[0199] The second base electrode film 120 forms a lower layer of the gate finger electrode 115 and covers the interlayer film 70 in the peripheral region 9. The second base electrode film 120 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed. In other words, the second base electrode film 120 extends from above the interlayer film 70 into the multiple gate openings 94. The second base electrode film 120 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner. The second base electrode film 120 defines multiple recesses within the multiple gate openings 94.

[0200] The second base electrode film 120 has a layered structure including a first electrode film 123 layered on the interlayer film 70, and a second electrode film 124 layered on the first electrode film 123. It is preferable that the first electrode film 123 contains the same type of conductive material as the first electrode film 103 on the source side, and the second electrode film 124 contains the same type of conductive material as the second electrode film 104 on the source side. In this embodiment, the first electrode film 123 contains a Ti film, and the second electrode film 124 contains a TiN film.

[0201] The second base electrode film 120 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 123 (Ti film) or the second electrode film 124 (TiN film). The first electrode film 123 may have a thickness approximately equal to that of the first electrode film 103 on the source side. The second electrode film 124 may have a thickness approximately equal to that of the second electrode film 104 on the source side.

[0202] The first electrode film 123 collectively covers the region of the interlayer film 70 where the multiple gate openings 94 are formed, and extends into the multiple gate openings 94 from above the interlayer film 70. In other words, the first electrode film 123 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.

[0203] The first electrode film 123 covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is electrically connected to the gate wiring 52. Specifically, the first electrode film 123 has a portion that covers the wiring upper portion 53 of the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is mechanically and electrically connected to the wiring upper portion 53.

[0204] The first electrode film 123 is mechanically connected to the wiring upper portion 53 at a distance inward from the wiring corner portion 61. In other words, the first electrode film 123 is mechanically connected only to the wiring upper portion 53, and is not mechanically connected to the wiring corner portion 61. The first electrode film 123 is electrically connected to the wiring corner portion 61 via the wiring upper portion 53. Of course, the first electrode film 123 (second base electrode film 120) may have a portion connected to the wiring corner portion 61.

[0205] The second electrode film 124 collectively covers, in a film-like manner, the region of the interlayer film 70 on the first electrode film 123 where the multiple gate openings 94 are formed. That is, the second electrode film 124 has a portion that covers, in a film-like manner, the upper surface of the interlayer film 70 with the first electrode film 123 in between, and a portion that covers, in a film-like manner, the wall surfaces of the multiple gate openings 94 with the first electrode film 123 in between.

[0206] The second electrode film 124 has a portion that covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, with the first electrode film 123 sandwiched therebetween, and is electrically connected to the gate wiring 52 via the first electrode film 123. Specifically, the second electrode film 124 has a portion that covers the wiring upper portion 53 of the gate wiring 52 in a film-like manner, with the first electrode film 123 sandwiched therebetween, and is electrically connected to the wiring upper portion 53 via the first electrode film 123.

[0207] The second electrode film 124 is positioned above the wiring upper portion 53 with a gap inward from the wiring corner 61. In other words, the second electrode film 124 faces only the wiring upper portion 53 across the first electrode film 123, and does not face the wiring corner 61. The second electrode film 124 is electrically connected to the wiring corner 61 via the first electrode film 123 and the wiring upper portion 53. Of course, the second electrode film 124 may have a portion facing the wiring corner 61 across the first electrode film 123.

[0208] The second main electrode film 122 forms an upper layer of the gate finger electrode 115 and covers the second base electrode film 120 in a film form. The second main electrode film 122 contains a conductive material different from the conductive material of the second base electrode film 120.

[0209] The second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The second main electrode film 122 preferably includes the same type of conductive material as the conductive material of the first main electrode film 102. The second main electrode film 122 may have a thickness approximately equal to that of the first main electrode film 102.

[0210] The second main electrode film 122 extends from above the interlayer film 70 into the plurality of gate openings 94 and is mechanically and electrically connected to the upper wiring portions 53 .

[0211] The semiconductor device 1 includes a gate pad electrode 130 disposed on the interlayer film 70. The gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 130 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. The gate pad electrode 130 is disposed in a region between the source pad electrode 95 and the source finger electrodes 110 and spaced apart from the source pad electrode 95 and the source finger electrodes 110.

[0212] In this embodiment, the gate pad electrode 130 is disposed in a region on the third side surface 5C side with respect to the first pad portion 96, and is sandwiched between the second pad portion 97 and the third pad portion 98. In other words, the gate pad electrode 130 faces the first pad portion 96 in the first direction X, and faces the second pad portion 97 and the third pad portion 98 in the second direction Y.

[0213] The gate pad electrode 130 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 130 has a planar area less than that of the source pad electrode 95 (first pad portion 96). The gate pad electrode 130 may have a planar area less than that of the second pad portion 97 (third pad portion 98).

[0214] The gate pad electrode 130 is disposed on a portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 115. The gate pad electrode 130 may cover the plurality of gate electrodes 32 with the interlayer film 70 interposed therebetween, or may cover the gate wiring 52 with the interlayer film 70 interposed therebetween.

[0215] Similar to the gate finger electrode 115, the gate pad electrode 130 includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 forms a lower layer of the gate pad electrode 130 and covers the interlayer film 70 in a film-like manner. Similar to the gate finger electrode 115, the second base electrode film 120 has a layered structure including a first electrode film 123 and a second electrode film 124. The first electrode film 123 covers the interlayer film 70 in a film-like manner, and the second electrode film 124 covers the first electrode film 123 in a film-like manner. The second main electrode film 122 forms an upper layer of the gate pad electrode 130 and covers the second base electrode film 120 in a film-like manner.

[0216] The gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 via the gate finger electrode 115. The gate potential is transmitted to the plurality of gate electrodes 32 via a wiring path (current path) along the gate wiring 52. This turns on the plurality of gate electrodes 32, controlling the on / off of the plurality of channel regions 26, 27.

[0217] The semiconductor device 1 includes a drain pad electrode 140 covering the second main surface 4. The drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 140 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like. The drain pad electrode 140 is electrically connected to the second semiconductor region 7. The drain pad electrode 140 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain pad electrode 140 may also partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0218] The breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0219] Next, the structures of the gate structure 30 and the interlayer film 70 will be described in detail with reference to Fig. 10. Fig. 10 is an enlarged cross-sectional view showing the main part of Fig. 7, showing an enlarged view of the vicinity of the electrode corner 41 of the gate electrode 32. Fig. 10 explains the structure in the vicinity of the electrode corner 41B, but this structure can also be applied to the structure in the vicinity of the electrode corner 41A and the structure in the vicinity of the wiring corners 61A and 61B.

[0220] As described above, the gate electrode 32 integrally includes the electrode upper portion 33, the electrode side portions 34 and 35, and the electrode corner portions 41. As a result, the gate electrode 32 is formed into a shape having a protrusion 37 that partially protrudes upward in a cross-sectional view. For example, the gate electrode 32 may include a base portion 36 extending from the lower surface (contact surface with the insulating film 31) of the gate electrode 32 to the upper ends of the electrode side portions 34 and 35, and a protrusion 37 whose width is narrowed by the electrode corner portions 41 and that forms the electrode upper portion 33. The upper side of the base portion 36 near the electrode side portions 34 and 35 is removed by the electrode corner portions 41, creating a space, so the film thickness is selectively thin. Conversely, the region where the protrusion 37 is formed is a portion of the gate electrode 32 where the film thickness is selectively thick.

[0221] In this configuration, the protrusion 37 overlaps the first source region 23 and the first channel region 26. This allows the thickness of the gate electrode 32 to be increased above the first channel region 26. Therefore, even if the electrode corners 41 are formed, the resistance value of the gate electrode 32 can be maintained low above the first channel region 26, thereby suppressing a decrease in switching speed response.

[0222] The interlayer film 70 integrally includes an insulating upper portion 84 in contact with the electrode upper portion 33 , insulating side portions 85 in contact with the electrode side portions 34 and 35 , and insulating corner portions 86 in contact with the electrode corner portions 41 .

[0223] The insulating upper portion 84 extends horizontally in a film-like manner along the electrode upper portion 33, covering the electrode upper portion 33. The insulating side portion 85 rises vertically from the insulating film 31, extends in a film-like manner along the electrode side portions 34, 35, covering the electrode side portions 34, 35.

[0224] The insulating corner 86 is recessed into the electrode corner 41 formed by the recess 42 that curves inwardly of the gate electrode 32. More specifically, the insulating corner 86 has a first convex surface 87 that curves inwardly of the gate electrode 32 along the curved surface of the recess 42, and a second convex surface 88 that contacts the source pad electrode 95 on the opposite side of the first convex surface 87 and curves obliquely upwardly of the gate electrode 32. In a cross-sectional view, the insulating corner 86 has the first convex surface 87 and the second convex surface 88 that curve in both directions away from each other. As a result, the thickness of the insulating corner 86 (corner thickness T3) is greater than the thickness of the insulating upper portion 84 (upper thickness T1) and the thickness of the insulating side portion 85 (side thickness T2).

[0225] The corner thickness T3 may be, for example, the thickness of the interlayer film 70 in the normal direction n of both the first tangent L1 to the first convex surface 87 and the second tangent L2 parallel to the first tangent L1 to the second convex surface 88. In this embodiment, the top thickness T1 and the side thickness T2 are, for example, 1000 Å or more and 5000 Å or less, and the corner thickness T3 is thicker than the top thickness T1 and the side thickness T2. Note that the corner thickness T3 only needs to be thicker than the top thickness T1 and the side thickness T2 in the total thickness of the interlayer film 70 including the first oxide film 72 and the second oxide film 73.

[0226] 11 is a schematic diagram showing a wafer 150 used in manufacturing the semiconductor device 1. Referring to FIG. 11, the wafer 150 is a base material of the chip 2 and includes a SiC single crystal. The wafer 150 is formed in a flat disk shape. Of course, the wafer 150 may also be formed in a flat rectangular parallelepiped shape. The wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0227] The first wafer main surface 151 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal. The first wafer main surface 151 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal. The wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.

[0228] The wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal. The mark 154 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 151 in a plan view.

[0229] The mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0230] The wafer 150 includes a first semiconductor region 6 in a region (surface layer portion) on the first wafer main surface 151 side. The first semiconductor region 6 is formed in a layer shape extending along the first wafer main surface 151. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).

[0231] The wafer 150 includes a second semiconductor region 7 in a region (surface layer portion) on the second wafer main surface 152 side. The second semiconductor region 7 is formed in a layer extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this embodiment, the second semiconductor region 7 is made of the wafer main body (specifically, a SiC wafer). That is, in this embodiment, the wafer 150 is made of an epitaxial wafer (a so-called epiwafer) having a layered structure including the wafer main body and an epitaxial layer.

[0232] For example, a plurality of device regions 155 and a plurality of cutting lines 156 are set on the wafer 150 by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1. Each of the plurality of device regions 155 is set to have a quadrangular shape in a plan view.

[0233] In this embodiment, the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are set at intervals inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 155.

[0234] 12A to 12M are cross-sectional views showing a method for manufacturing the semiconductor device 1. In each of Figures 12A to 12M, a cross section of a part of the active region 8 of one device region 155 is shown.

[0235] 12A , first, the aforementioned wafer 150 is prepared. Next, referring to FIG. 12B , p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of body regions 20. Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming an outer body region 21. Furthermore, n-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of source regions 23, 24.

[0236] Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of contact regions 25. Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a termination region 45. Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of field regions 47.

[0237] The steps of forming the body region 20, the outer body region 21, the source regions 23 and 24, the contact region 25, the termination region 45, and the field region 47 may be performed in any order. The step of forming the outer body region 21 may be performed simultaneously with the step of forming the body region 20. The step of forming the field region 47 may be performed simultaneously with the step of forming the body region 20 or the step of forming the termination region 45.

[0238] 12C , a base insulating film 160 is formed to cover the first wafer main surface 151. The base insulating film 160 is a base for the insulating film 31 and the peripheral insulating film 51. The base insulating film 160 may be formed by a chemical vapor deposition (CVD) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0239] 12D , a base electrode 161 is formed on the base insulating film 160. The base electrode 161 is a base for the gate electrode 32 and the gate wiring 52. The base electrode 161 includes conductive polysilicon. The base electrode 161 may be formed by a CVD method. The base electrode 161 has a base electrode surface 162 that extends along the base insulating film 160.

[0240] 12E , a mask 168 having a predetermined layout is formed on the base electrode 161 (base electrode surface 162). The mask 168 may be an organic mask (e.g., a resist mask). The mask 168 has a plurality of openings 169 that expose areas other than the plurality of mask portions that cover the areas where the plurality of gate electrodes 32 are to be formed.

[0241] The next step is the etching step of the base electrode 161. In this step, isotropic etching is performed using a mask 168, followed by anisotropic etching. First, referring to FIG. 12F , the base electrode 161 is isotropically removed from the base electrode surface 162 in the thickness direction and the lateral direction by isotropic etching using the mask 168. As a result, a recess 163 is formed in the base electrode 161 directly below the opening 169. The recess 163 has recess corners 164 that curve inward of the base electrode 161 at both lateral ends along the first wafer main surface 151.

[0242] 12G, the remaining portion of base electrode 161 is removed in the thickness direction from the bottom of recess 163 to base insulating film 160 by anisotropic etching using mask 168. This forms a plurality of gate electrodes 32, each having an electrode upper portion 33, electrode side portions 34 and 35, and electrode corner portion 41. Arc-shaped electrode corner portion 41 is formed by recess corner portion 164. Furthermore, gate wiring 52 is formed, having wiring upper portion 53, wiring side portions 54 and 55, and wiring corner portion 61. After the process of forming gate electrode 32 and gate wiring 52, mask 168 is removed.

[0243] 12H , an interlayer film 70 is formed on the first wafer main surface 151. In this step, the interlayer film 70 is formed to have portions that directly cover the electrode upper portion 33, the first electrode side portion 34, the second electrode side portion 35, and the electrode corner portion 41 of the gate electrode 32. The interlayer film 70 is also formed to have portions that directly cover the wiring upper portion 53, the first wiring side portion 54, the second wiring side portion 55, and the wiring corner portion 61 of the gate wiring 52.

[0244] In this embodiment, the interlayer film 70 has a stacked structure including a first oxide film 72 and a second oxide film 73 (see FIG. 7). The first oxide film 72 includes a silicon oxide film with no added impurities. The second oxide film 73 includes a silicon oxide film containing phosphorus. The first oxide film 72 may be formed by a CVD method. The second oxide film 73 may be formed by a CVD method. After the step of forming the second oxide film 73, a reflow step (heat treatment step) is performed on the interlayer film 70. This smoothes the corners and rough surfaces of the interlayer film 70.

[0245] 12I, a mask 174 having a predetermined layout is placed on the interlayer film 70. The mask 174 exposes regions where the plurality of source openings 90, the plurality of outer openings 92, and the plurality of gate openings 94 are to be formed, and covers the other regions.

[0246] 12J , unnecessary portions of the interlayer film 70 and the base insulating film 160 are removed by etching using a mask 174. In this step, the unnecessary portions of the second oxide film 73, the unnecessary portions of the first oxide film 72, and the unnecessary portions of the base insulating film 160 are removed in this order. The etching method may be wet etching and / or dry etching. Preferably, the etching method is anisotropic dry etching (e.g., RIE (Reactive Ion Etching)).

[0247] As a result, a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 are formed in the interlayer film 70. In addition, an insulating film 31 and a peripheral insulating film 51 are formed. This process may include the process of forming a plurality of source recesses 91 and the process of forming a plurality of outer recesses 93. In this case, a process of further digging down portions of the first wafer main surface 151 exposed from the plurality of source openings 90 and the plurality of outer openings 92 toward the second wafer main surface 152 is performed. The mask 174 is then removed.

[0248] 12K, a reflow process forms a second convex surface 88 at the upper corner of the interlayer film 70, which curves obliquely upward relative to the gate electrode 32. The reflow conditions are not particularly limited as long as they allow the sharp upper corner of the interlayer film 70 to become arc-shaped after the etching shown in FIG. 12J. The reflow conditions may be appropriately determined depending on, for example, the film thickness and film quality of the interlayer film 70, the opening width of the source opening 90, and the like.

[0249] 12L, the first underlying electrode film 100 and the second underlying electrode film 120 are formed on the interlayer film 70. The first underlying electrode film 100 and the second underlying electrode film 120 may be formed by sputtering or vapor deposition.

[0250] 12M, the first main electrode film 102 and the second main electrode film 122 are formed on the first base electrode film 100 and the second base electrode film 120, respectively. The first main electrode film 102 and the second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 and the second main electrode film 122 may be formed by sputtering or vapor deposition.

[0251] Thereafter, a drain pad electrode 140 is formed on the second wafer main surface 152. The drain pad electrode 140 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the cutting lines 156 to cut out a plurality of semiconductor devices 1. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0252] For example, in order to meet the demand for device miniaturization, multiple gate structures 30 may be arranged at a narrow pitch. Because the distance between adjacent gate structures 30 is narrow, if the interlayer film 70 is made uniformly thick to ensure sufficient breakdown voltage, the width W of the source opening 90 for source contact becomes very small. Reducing the width W of the source opening 90 reduces the embeddability of the metal (source pad electrode 95) in the source opening 90. This reduced embeddability can result in voids at the source opening 90, leading to problems such as the infiltration of plating solution and wire bonding defects (e.g., insufficient strength during wire bonding). On the other hand, if the interlayer film 70 is thinned to address this issue, the insulating corner 86 cannot be sufficiently thick after reflow of the interlayer film 70, reducing the reliability of the gate-source insulation.

[0253] Therefore, in this semiconductor device 1, because the electrode corner 41 is formed in the gate electrode 32, the corner thickness T3 of the interlayer film 70 can be selectively made thicker than the top thickness T1 and the side thickness T2. As a result, after the source opening 90 is formed, the insulating corner 86 is shaped into an arc-like shape like the second convex surface 88 by reflow, and even if it becomes thinner than before reflow (see FIG. 12K), a sufficient thickness of the insulating corner 86 can be ensured above the electrode corner 41. This allows the gate structure 30 to meet the demand for a narrower pitch and improves breakdown voltage reliability. Meanwhile, the side thickness T2 can be formed relatively thin, thereby suppressing the generation of voids in the source opening 90.

[0254] In particular, in the case of the semiconductor device 1 having SiC, due to its characteristics (physical properties), an extremely high voltage is applied, unlike lateral type Si semiconductor devices such as LSIs, etc. Therefore, by improving the insulation reliability between the gate and source, a semiconductor device 1 having appropriate electrical characteristics is provided.

[0255] The following describes modifications of the gate electrode 32. FIG.

[0256] 13 , the electrode corner 41 of the gate electrode 32 does not necessarily have to be formed in an arc shape. For example, the electrode corner 41 may be formed by a flat inclined wall 43 that slopes downward from the electrode upper portion 33 to the electrode side portions 34, 35. The electrode corner 41 may also be a flat inclined wall 43 that slopes upward and inward in the width direction of the gate electrode 32 from the upper ends of the electrode side portions 34, 35. In this case, the insulating corner 86 may have a flat surface 44 that contacts the inclined wall 43 and slopes along the inclined wall 43.

[0257] Even when the electrode corner 41 is formed by an inclined wall 43, the thickness of the insulating corner 86 (corner thickness T3) can be made thicker than the thickness of the insulating upper portion 84 (upper thickness T1) and the thickness of the insulating side portion 85 (side thickness T2).

[0258] 14A-14B are diagrams illustrating the steps involved in forming the gate electrode 32 of FIG.

[0259] 14A , to form the electrode corner 41 having the inclined wall 43, a mask 168 is formed on the base electrode 161 (base electrode surface 162) (see FIG. 12E ), and then the base electrode 161 is tapered from the base electrode surface 162 in the thickness direction by anisotropic taper etching via the mask 168. At this time, the dry etching conditions may be appropriately set so that the base electrode 161 is etched obliquely rather than vertically. As a result, a recess 165 is formed in the base electrode 161 directly below the opening 169. The recess 165 has recess corners 166 formed by flat inclined walls that slope obliquely upward from the base electrode 161 at both lateral ends along the first wafer main surface 151.

[0260] 14B , the remaining portion of base electrode 161 is removed in the thickness direction from the bottom of recess 165 to base insulating film 160 by anisotropic vertical etching using mask 168. This results in the formation of multiple gate electrodes 32, each having electrode upper portion 33, electrode side portions 34 and 35, and electrode corner portion 41 (inclined wall 43). Inclined wall 43 of electrode corner portion 41 is formed by recess corner portion 166.

[0261] Thereafter, the steps of FIGS. 12H to 12M are carried out to obtain the semiconductor device 1 shown in FIG.

[0262] 15 is a cross-sectional view showing a second modified example of a gate electrode. Referring to FIG. 15 , the electrode corner 41 of the gate electrode 32 does not necessarily have to be formed in an arc shape. For example, the electrode corner 41 may be formed by a rounded portion 48 that connects the electrode upper portion 33 and the electrode side portions 34 and 35 in an arc shape that curves obliquely upward of the gate electrode 32. In this case, the insulating corner 86 may have a concave surface 49 that contacts the rounded portion 48 and is formed in an arc shape along the rounded portion 48. The concave surface 49 is a surface that curves in the same direction as the second convex surface 88 of the insulating corner 86.

[0263] Even when the electrode corner 41 is formed by the rounded portion 48, the thickness of the insulating corner 86 (corner thickness T3) can be made thicker than the thickness of the insulating upper portion 84 (upper thickness T1) and the thickness of the insulating side portion 85 (side thickness T2).

[0264] 16A-16B are diagrams illustrating the steps involved in forming the gate electrode 32 of FIG.

[0265] 16A, to form the electrode corners 41 having the rounded portions 48, a mask 168 is formed on the base electrode 161 (base electrode surface 162) (see FIG. 12E), and then the base electrode 161 is removed in the thickness direction from the base electrode surface 162 to the base insulating film 160 by anisotropic etching via the mask 168. This forms a plurality of gate electrodes 32 with sharp electrode corners 41.

[0266] 16B , a thermal oxidation process is performed to form a thermal oxide film 50 on the surface of gate electrode 32. The thermal oxidation of gate electrode 32 progresses vertically (longitudinal) from electrode upper portion 33 and horizontally (laterally) from electrode side portions 34 and 35. At electrode corner 41, thermal oxidation progresses both vertically and horizontally, causing the sharp corners of electrode corner 41 to be oxidized and chipped, forming arc-shaped rounded portions 48.

[0267] Thereafter, the steps of FIGS. 12H to 12M are carried out to obtain the semiconductor device 1 shown in FIG.

[0268] Although the embodiments of the present disclosure have been described above, the semiconductor device 1 of the present disclosure can also be embodied in other forms.

[0269] For example, in each of the above-described embodiments, a configuration in which the relationship between the a-axis direction and the m-axis direction is interchanged may be adopted. A specific configuration in this case can be obtained by interchangeing the "a-axis direction (off direction)" and the "m-axis direction (direction perpendicular to the off direction)" in the above description and the accompanying drawings.

[0270] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0271] In the above-described embodiments, the chip 2 (first semiconductor region 6 and second semiconductor region 7) includes single crystal SiC. However, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may include single crystal wide bandgap semiconductors other than single crystal SiC. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of single crystal wide bandgap semiconductors include gallium nitride, diamond, and gallium oxide. Of course, the chip 2 (first semiconductor region 6 and second semiconductor region 7) may include single crystal silicon.

[0272] In the above-described embodiments, the n-type second semiconductor region 7 has been described. However, a p-type second semiconductor region 7 may be adopted instead of the n-type second semiconductor region 7. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0273] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0274] [Supplementary Note 1-1] A chip (2) having a principal surface (3); a gate electrode (32) formed on the principal surface (3), the gate electrode (32) having an electrode upper portion (33) along the principal surface (3), electrode side portions (34, 35) rising from the principal surface (3), and electrode corner portions (41) formed by removing a portion of the material of the gate electrode (32) and connecting the electrode upper portion (33) and the electrode side portions (34, 35); an interlayer film (70) covering the gate electrode (32); an opening (90) formed in the interlayer film (70) spaced apart from the electrode side portions (34, 35) in a lateral direction along the principal surface (3), the opening exposing a portion of the principal surface (3) as a contact surface; and a surface electrode (95) formed on the interlayer film (70) and mechanically and electrically connected to the contact surface within the opening (90), The interlayer film (70) includes an insulating upper portion (84) in contact with the electrode upper portion (33), an insulating side portion (85) in contact with the electrode side portions (34, 35), and an insulating corner portion (86) in contact with the electrode corner portion (41), and a corner thickness (T3) of the interlayer film (70) at the insulating corner portion (86) is thicker than at least one of the upper thickness (T1) of the interlayer film (70) at the insulating upper portion (84) and the side thickness (T2) of the interlayer film (70) at the insulating side portion (85).

[0275] For example, to meet the demand for device miniaturization, multiple gate electrodes (32) may be arranged at a narrow pitch. Since the distance between adjacent gate electrodes (32) is narrow, if the interlayer film (70) is made uniformly thick to ensure sufficient breakdown voltage, the width of the opening (90) exposing the contact surface becomes very small. Reducing the width of the opening (90) reduces the metal embeddability into the opening (90). This reduced embeddability leads to voids at the opening (90), which can cause problems such as the infiltration of plating solution and wire bonding defects (e.g., insufficient strength during wire bonding). On the other hand, if the interlayer film (70) is thinned to address this issue, the insulating corner (86) cannot be sufficiently thick after reflow of the interlayer film (70), resulting in reduced insulation reliability.

[0276] Therefore, according to this embodiment, since the electrode corners (41) are formed in the gate electrode (32) by removing a portion of the material of the gate electrode (32), the corner thickness (T3) of the interlayer film (70) can be selectively made thicker than the top thickness (T1) and the side thickness (T2). This ensures that the insulating corners (86) are sufficiently thick above the electrode corners (41) even if the insulating corners (86) are thinner after the openings (90) are formed than before reflow. This allows for the gate electrodes (32) to meet the requirement for a narrower pitch and improves breakdown voltage reliability. Meanwhile, the side thickness (T2) can be formed relatively thin, thereby suppressing the generation of voids in the openings (90).

[0277] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein the electrode corner (41) includes an arc-shaped recess (42) that curves inward of the gate electrode (32).

[0278] [Supplementary Note 1-3] The semiconductor device (1) according to Supplementary Note 1-2, wherein the insulating corner (86) has a first convex surface (87) that curves inward of the gate electrode (32) along the curved surface of the recess (42), and the corner thickness (T3) includes a thickness of the interlayer film (70) in a normal direction (n) of a tangent (L1) to the first convex surface (87).

[0279] [Supplementary Note 1-4] The semiconductor device (1) according to Supplementary Note 1-2, wherein the insulating corner (86) has a first convex surface (87) that curves inward of the gate electrode (32) along the curved surface of the recess (42), and a second convex surface (88) that contacts the surface electrode (95) on the opposite side of the first convex surface (87) and curves obliquely upward of the gate electrode (32), and the corner thickness (T3) includes thicknesses of the interlayer film (70) in normal directions (n) of both a first tangent (L1) to the first convex surface (87) and a second tangent (L2) to the second convex surface (88) that is parallel to the first tangent (L1).

[0280] [Appendix 1-5] The semiconductor device (1) according to appendix 1-1, wherein the electrode corner (41) includes a flat inclined wall (43) that slopes downward from the electrode top (33) to the electrode side (34, 35).

[0281] [Appendix 1-6] The semiconductor device (1) according to Appendix 1-1, wherein the electrode corner portion (41) includes a round portion (48) that connects the electrode upper portion (33) and the electrode side portion (34, 35) in an arc shape that curves obliquely upward from the gate electrode (32).

[0282] [Supplementary Note 1-7] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, further comprising a plurality of the gate electrodes (32) arranged at intervals on the main surface (3), and the opening (90) is defined in a region between the plurality of the gate electrodes (32).

[0283] [Appendix 1-8] The semiconductor device (1) according to any one of Appendices 1-1 to 1-7, wherein the opening (90) has a vertical aspect ratio (D / W) along a depth direction of the opening (90), and the corner thickness (T3) is greater than both the top thickness (T1) and the side thickness (T2).

[0284] [Appendix 1-9] The semiconductor device (1) according to any one of Appendices 1-1 to 1-8, wherein the top thickness (T1) and the side thickness (T2) are 1000 Å or more and 5000 Å or less.

[0285] [Appendix 1-10] The semiconductor device (1) according to any one of Appendices 1-1 to 1-9, wherein the width of the opening (90) is 0.2 μm or more and 3 μm or less, and the depth of the opening (90) is 0.2 μm or more and 2 μm or less.

[0286] [Appendix 1-11] The semiconductor device (1) according to any one of Appendices 1-1 to 1-10, wherein the interlayer film (70) includes a first oxide film (72) with no impurities added thereto that covers the gate electrode (32), and a second oxide film (73) that contains phosphorus and covers the first oxide film (72), and the opening (90) penetrates both the first oxide film (72) and the second oxide film (73).

[0287] [Supplementary Note 1-12] The semiconductor device further includes: a semiconductor region (6) of a first conductivity type formed in a surface layer portion of the main surface (3); a body region (20) of a second conductivity type formed in a surface layer portion of the semiconductor region (6); impurity regions (23, 24) of the first conductivity type formed in a surface layer portion of the body region (20); channels (26, 27) formed in a region between the semiconductor region (6) and the impurity regions (23, 24) in the surface layer portion of the body region (20); and an insulating film (31) covering the channels (26, 27) on the main surface (3) and sandwiched between the gate electrode (32) and the channels (26, 27); the opening (90) exposes a portion of the impurity regions (23, 24) to the contact surface; The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-11, wherein the surface electrode (95) is electrically connected to the impurity regions (23, 24) within the opening (90).

[0288] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, wherein the chip (2) is a SiC chip (2).

[0289] [Appendix 1-14] A step of forming a base electrode (161) on a main surface (151) of a wafer (150); a step of selectively isotropically etching the base electrode (161) in a thickness direction, followed by anisotropic etching, to form a gate electrode (32) having an electrode upper portion (33) along the main surface (151), electrode side portions (34, 35) rising from the main surface (151), and an electrode corner portion (41) connecting the electrode upper portion (33) and the electrode side portions (34, 35) and including an arc-shaped recess (42) curved inward of the base electrode (161); and a step of forming an interlayer film (70) on the main surface (151) so as to cover the gate electrode (32). A method for manufacturing a semiconductor device (1), comprising: forming an opening (90) in the interlayer film (70) that exposes a portion of the main surface (151) as a contact surface, the opening (90) being spaced apart from the electrode side portions (34, 35) in a lateral direction along the main surface (151); and forming a surface electrode (95) on the interlayer film (70) so as to be mechanically and electrically connected to the contact surface within the opening (90).

[0290] [Appendix 1-15] A process of forming a base electrode (161) on a main surface (151) of a wafer (150); a process of selectively anisotropically tapering the base electrode (161) in a thickness direction, followed by anisotropically vertically etching the base electrode (161), thereby forming a gate electrode (32) having an electrode upper portion (33) along the main surface (151), electrode side portions (34, 35) rising from the main surface (151), and an electrode corner portion (41) including a flat inclined wall (43) that connects the electrode upper portion (33) and the electrode side portions (34, 35) and slopes downward from the electrode upper portion (33) to the electrode side portions (34, 35); and a process of forming an interlayer film (70) on the main surface (151) so as to cover the gate electrode (32). A method for manufacturing a semiconductor device (1), comprising: forming an opening (90) in the interlayer film (70) that exposes a portion of the main surface (151) as a contact surface, the opening (90) being spaced apart from the electrode side portions (34, 35) in a lateral direction along the main surface (151); and forming a surface electrode (95) on the interlayer film (70) so as to be mechanically and electrically connected to the contact surface within the opening (90).

[0291] [Appendix 1-16] A step of forming a base electrode (161) containing polysilicon on a main surface (151) of a wafer (150); a step of selectively anisotropically etching the base electrode (161) in a thickness direction to form a gate electrode (32) having an electrode upper portion (33) along the main surface (151), electrode side portions (34, 35) rising from the main surface (151), and electrode corner portions (41) connecting the electrode upper portion (33) and the electrode side portions (34, 35); a step of thermally oxidizing the gate electrode (32) to form a circular arc-shaped round portion (48) curved obliquely upward from the gate electrode (32) at the electrode corner portion (41); and a step of forming an interlayer film (70) on the main surface (151) so as to cover the gate electrode (32). A method for manufacturing a semiconductor device (1), comprising: forming an opening (90) in the interlayer film (70) that exposes a portion of the main surface (151) as a contact surface, the opening (90) being spaced apart from the electrode side portions (34, 35) in a lateral direction along the main surface (151); and forming a surface electrode (95) on the interlayer film (70) so as to be mechanically and electrically connected to the contact surface within the opening (90).

[0292] [Appendix 1-17] A method for manufacturing a semiconductor device (1) according to any one of Appendices 1-14 to 1-16, comprising a step of forming a convex surface (88) curved obliquely upward of the gate electrode (32) at an upper corner of the opening (90) in the interlayer film (70) by reflow treatment.

[0293] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor region 7: Second semiconductor region 8: Active region 9: Peripheral region 20: Body region 21: Outer body region 22: Surface drift region 23: First source region 24: Second source region 25: Contact region 26: First channel region 27: Second channel region 30: Gate structure 31: Insulating film 32: Gate electrode 33: Upper electrode portion 34: First electrode side portion 35: Second electrode side portion 36: Base portion 37: Protrusion portion 41: Electrode corner portion 41A: Electrode corner portion 41B: Electrode corner portion 42: Recess portion 43: Inclined wall 44: Flat surface 45: Termination region 46: Overlap region 47: Field region 48: Rounded portion 49: Concave surface 50: Thermal oxide film 51: Peripheral insulating film 52: Gate wiring 53: Upper portion of wiring 54: First wiring side 55: Second wiring side 61: Wiring corner 61A: Wiring corner 61B: Wiring corner 70: Interlayer film 72: First oxide film 73: Second oxide film 74: First coating portion 75: Second coating portion 76: Third coating portion 77: First wiring coating portion 78: Second wiring coating portion 79: Third wiring coating portion 80: First upper coating portion 81: Second upper coating portion 82: First upper wiring coating portion 83 : second upper wiring covering portion 84 : insulating upper portion 85 : insulating side portion 86 : insulating corner portion 87 : first convex surface 88 : second convex surface 90 : source opening 91 : source recess 92 : outer opening 93 : outer recess 94 : gate opening 95 : source pad electrode 96 : first pad portion 97 : second pad portion 98 : third pad portion 100 : first base electrode film 102 : first main electrode film 103 : first electrode film 104 : second electrode film 110 : source finger electrode 115 : gate finger electrode 120 : second base electrode film 122 : second main electrode film 123 : first electrode film 124 : second electrode film 130 : gate pad electrode 140 : drain pad electrode150: Wafer 151: First wafer main surface 152: Second wafer main surface 153: Wafer side surface 154: Mark 155: Device region 156: Cutting line 160: Base insulating film 161: Base electrode 162: Base electrode surface 163: Recess 164: Recess corner 165: Recess 166: Recess corner 168: Mask 169: Opening 174: Mask L1: First tangent L2: Second tangent T1: Upper thickness T2: Side thickness T3: Corner thickness X: First direction Y: Second direction Z: Vertical direction n: Normal direction

Claims

1. a chip having a major surface; a gate electrode formed on the main surface, the gate electrode having an electrode upper portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion formed by removing a part of the material of the gate electrode and connecting the electrode upper portion and the electrode side portion; an interlayer film covering the gate electrode; an opening formed in the interlayer film at a distance from the electrode side in a lateral direction along the main surface, the opening exposing a part of the main surface as a contact surface; a surface electrode formed on the interlayer film and mechanically and electrically connected to the contact surface within the opening; the interlayer film includes an insulating upper portion in contact with the upper portion of the electrode, an insulating side portion in contact with the side portion of the electrode, and an insulating corner portion in contact with the corner portion of the electrode, A semiconductor device, wherein the corner thickness of the interlayer film at the insulating corner portion is thicker than at least one of the top thickness of the interlayer film at the insulating top portion and the side thickness of the interlayer film at the insulating side portion.

2. 2. The semiconductor device according to claim 1, wherein said electrode corner includes an arc-shaped recess curved inward of said gate electrode.

3. the insulating corner portion has a first convex surface that curves inward of the gate electrode along a curved surface of the recess, 3. The semiconductor device according to claim 2, wherein said corner thickness includes a thickness of said interlayer film in a direction normal to a tangent to said first convex surface.

4. the insulating corner portion has a first convex surface that curves inward of the gate electrode along the curved surface of the recess, and a second convex surface that contacts the surface electrode on the opposite side of the first convex surface and curves obliquely upward of the gate electrode, 3. The semiconductor device according to claim 2, wherein the corner thickness includes a thickness of the interlayer film in directions normal to both a first tangent to the first convex surface and a second tangent to the second convex surface that is parallel to the first tangent.

5. 2. The semiconductor device according to claim 1, wherein said electrode corner includes a flat inclined wall that slopes downward from an upper portion of said electrode to a side portion of said electrode.

6. 2. The semiconductor device according to claim 1, wherein said electrode corner portion includes a rounded portion that connects said electrode upper portion and said electrode side portion in an arc shape that curves obliquely upward of said gate electrode.

7. further comprising a plurality of the gate electrodes arranged at intervals on the main surface; 7. The semiconductor device according to claim 1, wherein the opening is defined in a region between a plurality of the gate electrodes.

8. The opening has an aspect ratio of a vertical length along a depth direction of the opening, The semiconductor device of claim 7 , wherein the corner thickness is greater than both the top thickness and the side thickness.

9. 9. The semiconductor device of claim 8, wherein the top thickness and the side thickness are between 1000 Å and 5000 Å.

10. 10. The semiconductor device according to claim 9, wherein the width of said opening is 0.2 μm or more and 3 μm or less, and the depth of said opening is 0.2 μm or more and 2 μm or less.

11. the interlayer film includes a first oxide film with no impurities added thereto that covers the gate electrode, and a second oxide film that contains phosphorus and covers the first oxide film; 7. The semiconductor device according to claim 1, wherein said opening penetrates both said first oxide film and said second oxide film.

12. a first conductivity type semiconductor region formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the semiconductor region; an impurity region of a first conductivity type formed in a surface layer portion of the body region; a channel formed in a region between the semiconductor region and the impurity region in a surface layer portion of the body region; an insulating film covering the channel on the main surface and sandwiched between the gate electrode and the channel; the opening exposes a portion of the impurity region to the contact surface; 7. The semiconductor device according to claim 1, wherein said surface electrode is electrically connected to said impurity region within said opening.

13. 7. The semiconductor device according to claim 1, wherein the chip is a SiC chip.

14. forming a base electrode on a main surface of the wafer; a step of selectively isotropically etching the base electrode in a thickness direction, followed by anisotropically etching the base electrode, to form a gate electrode having an electrode upper portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion connecting the electrode upper portion and the electrode side portion and including an arc-shaped recess curved inward of the base electrode; forming an interlayer film on the main surface so as to cover the gate electrode; forming an opening in the interlayer film to expose a portion of the main surface as a contact surface, the opening being spaced apart from the electrode side portion in a lateral direction along the main surface; forming a surface electrode on the interlayer film so as to be mechanically and electrically connected to the contact surface within the opening.

15. forming a base electrode on a main surface of the wafer; a step of selectively anisotropically taper-etching the base electrode in a thickness direction, followed by anisotropically vertical etching, to form a gate electrode having an electrode upper portion along the main surface, electrode side portions rising from the main surface, and electrode corner portions connecting the electrode upper portion and the electrode side portions and including flat inclined walls inclined downward from the electrode upper portion to the electrode side portions; forming an interlayer film on the main surface so as to cover the gate electrode; forming an opening in the interlayer film to expose a portion of the main surface as a contact surface, the opening being spaced apart from the electrode side portion in a lateral direction along the main surface; forming a surface electrode on the interlayer film so as to be mechanically and electrically connected to the contact surface within the opening.

16. forming a base electrode comprising polysilicon on a main surface of the wafer; a step of selectively anisotropically etching the base electrode in a thickness direction to form a gate electrode having an electrode upper portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion connecting the electrode upper portion and the electrode side portion; a step of thermally oxidizing the gate electrode to form a rounded portion at a corner of the electrode, the rounded portion having an arc shape that curves obliquely upward of the gate electrode; forming an interlayer film on the main surface so as to cover the gate electrode; forming an opening in the interlayer film to expose a portion of the main surface as a contact surface, the opening being spaced apart from the electrode side portion in a lateral direction along the main surface; forming a surface electrode on the interlayer film so as to be mechanically and electrically connected to the contact surface within the opening.

17. 17. The method for manufacturing a semiconductor device according to claim 14, further comprising the step of forming a convex surface curved obliquely upward of the gate electrode at an upper corner of the opening in the interlayer film by reflow treatment.