Semiconductor device

Abstract

A semiconductor device according to one embodiment of the present disclosure is provided with: a first substrate that has a first surface and a second surface that face each other, and has a plurality of semiconductor elements formed on the first surface side; a second substrate which is mounted on the second surface of the first substrate, and which is composed of a laminate of a plurality of semiconductor layers each having one or a plurality of circuits; and a third substrate which is disposed alongside the second substrate and is mounted on the second surface of the first substrate, the third substrate being composed of a laminate of one or a plurality of semiconductor layers each having one or a plurality of circuits.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device having a three-dimensional structure.

[0002] For example, Patent Document 1 discloses a back-illuminated solid-state imaging device in which individualized memory circuits and logic circuits are laid out horizontally below a solid-state imaging element and buried in an oxide film.

[0003] International Publication No. 2019 / 087764

[0004] Incidentally, there is a demand for imaging devices that offer both high performance and reduced costs.

[0005] It is desirable to provide a semiconductor device that achieves both high performance and reduced cost.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a first substrate having opposing first and second surfaces and having a plurality of semiconductor elements formed on the first surface side; a second substrate mounted on the second surface of the first substrate and comprising a plurality of stacked semiconductor layers, each having one or more circuits; and a third substrate arranged in parallel with the second substrate and mounted on the second surface of the first substrate, comprising one or more stacked semiconductor layers, each having one or more circuits.

[0007] In a semiconductor device according to an embodiment of the present disclosure, a first substrate has a plurality of semiconductor elements formed on a first surface thereof, and a second substrate and a third substrate are mounted on a second surface opposite the first surface. The second substrate has a plurality of stacked semiconductor layers, each having one or more circuits. The third substrate has a plurality of stacked semiconductor layers, each having one or more circuits. This allows desired circuit chips to be mounted in desired positions.

[0008] FIG. 1 is a cross-sectional view schematically illustrating an example of the configuration of an imaging device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view schematically illustrating another example of the configuration of an imaging device according to an embodiment of the present disclosure. FIG. 3 is a flow chart illustrating a manufacturing process for the imaging device shown in FIGS. 1 and 2. FIG. 4 is an exploded perspective view illustrating an example of the schematic configuration of the imaging device shown in FIGS. 1 and 3. FIG. 5 is an exploded perspective view illustrating a connection state of a pixel array section of the imaging device shown in FIG. 2. FIG. 6 is a diagram illustrating the connection state of the sensor pixels, readout circuits, and circuits provided in multiple semiconductor layers constituting the first CoW layer shown in FIG. 5. FIG. 7 is an exploded perspective view illustrating a connection state of a peripheral section of the imaging device shown in FIG. 2. FIG. 8 is an exploded perspective view illustrating a connection state of a pixel array section of an imaging device according to a first modification of the present disclosure. FIG. 9 is an exploded perspective view illustrating a connection state of a peripheral section of an imaging device according to the first modification of the present disclosure. FIG. 10 is a cross-sectional view schematically illustrating an example of the configuration of an imaging device according to a second modification of the present disclosure. FIG. 11 is a cross-sectional view schematically illustrating another example of the configuration of an imaging device according to the second modification of the present disclosure. FIG. 12 is a cross-sectional schematic diagram illustrating another example of the configuration of an imaging device according to Modification 2 of the present disclosure. FIG. 13 is a cross-sectional schematic diagram illustrating an example of the configuration of an imaging device according to Modification 3 of the present disclosure. FIG. 14 is a block diagram of circuits mounted on the first CoW layer and the second CoW layer of the imaging device shown in FIG. 13. FIG. 15 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and Modifications 1 to 4. FIG. 16 is a diagram illustrating an example of an imaging procedure in the imaging system of FIG. 15. FIG. 17 is a block diagram illustrating an example of a schematic configuration of a vehicle control system. FIG. 18 is an explanatory diagram illustrating an example of the installation positions of an outside vehicle information detection unit and an imaging unit. FIG. 19 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. FIG. 20 is a block diagram illustrating an example of the functional configuration of a camera head and a CCU. FIG. 21 is a cross-sectional schematic diagram illustrating an example of the configuration of an imaging device according to Modification 4 of the present disclosure. FIG. 22A is a cross-sectional schematic diagram illustrating an example of a manufacturing process for the imaging device shown in FIG. 21. FIG. 22B is a cross-sectional schematic diagram illustrating a process subsequent to FIG. 22A. Fig. 22C is a schematic cross-sectional view showing a step subsequent to Fig. 22B, Fig. 22D is a schematic cross-sectional view showing a step subsequent to Fig. 22C, and Fig. 22E is a schematic cross-sectional view showing a step subsequent to Fig. 22D.22F is a schematic cross-sectional view illustrating a step subsequent to FIG. 22E. FIG. 22G is a schematic cross-sectional view illustrating a step subsequent to FIG. 22F. FIG. 22H is a schematic cross-sectional view illustrating a step subsequent to FIG. 22G. FIG. 23 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 5 of the present disclosure. FIG. 24 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 6 of the present disclosure. FIG. 25 is a schematic cross-sectional view illustrating another example of a configuration of an imaging device according to Modification 6 of the present disclosure. FIG. 26 is a schematic cross-sectional view illustrating another example of a configuration of an imaging device according to Modification 6 of the present disclosure. FIG. 27 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 7 of the present disclosure. FIG. 28 is a schematic cross-sectional view illustrating another example of a configuration of an imaging device according to Modification 7 of the present disclosure. FIG. 29 is a schematic cross-sectional view illustrating another example of a configuration of an imaging device according to Modification 7 of the present disclosure. FIG. 30 is a schematic cross-sectional view illustrating another example of a configuration of an imaging device according to Modification 7 of the present disclosure.

[0009] An embodiment of the present disclosure will be described in detail below with reference to the drawings. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Furthermore, the present disclosure is not limited to the arrangement, dimensions, dimensional ratios, etc. of the components shown in the drawings. The order of description is as follows: 1. Embodiment (Example of an imaging device in which a plurality of CoW layers, each consisting of one or more layers, are mounted in the planar direction on the surface side of a sensor substrate) 2. Modifications 2-1. Modification 1 (Another example of connection of a pixel array section of an imaging device) 2-2. Modification 2 (Another example of the configuration of an imaging device) 2-3. Modification 3 (Another example of the configuration of an imaging device) 2-4. Modification 4 (Another example of the configuration of an imaging device) 2-5. Modification 5 (Another example of the configuration of an imaging device) 2-6. Modification 6 (Another example of the configuration of an imaging device) 2-7. Modification 7 (Another example of the configuration of an imaging device) 3. Application Examples 4. Application Examples

[0010] 1 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure. The imaging device 1 has a three-dimensional structure in which, below a sensor substrate 100, multiple layers (hereinafter referred to as CoW layers) having a chip-on-wafer (CoW) structure in which one or more semiconductor layers are stacked are arranged side by side in the in-plane directions (X and Y directions) of the sensor substrate 100.

[0011] [Configuration of the Imaging Device] The imaging device 1 is a so-called backside illumination imaging device that receives light from the backside of the sensor substrate 100 (for example, the backside (surface 100S1) of the semiconductor layer 100S constituting the sensor substrate 100). The imaging device 1 has multiple (here, two) CoW layers (a first CoW layer 200 and a second CoW layer 300) formed by stacking one or more semiconductor layers, mounted side by side on the front side (surface 100S2) of the sensor substrate 100. The sensor substrate 100 and the first CoW layer 200, and the sensor substrate 100 and the second CoW layer 300, are electrically connected to each other by hybrid junctions. The first CoW layer 200 and the second CoW layer 300 are electrically connected to each other via the sensor substrate 100. An insulating layer 410 is embedded between the first CoW layer 200 and the second CoW layer 300. A support substrate 400 common to the first CoW layer 200 and the second CoW layer 300 is provided on the surface of the first CoW layer 200 and the second CoW layer 300 opposite to the surface facing the sensor substrate 100 .

[0012] The sensor substrate 100 corresponds to a specific example of a "first substrate" in the embodiment of the present disclosure. The first CoW layer 200 corresponds to a specific example of a "second substrate" in the embodiment of the present disclosure. The second CoW layer 300 corresponds to a specific example of a "third substrate" in the embodiment of the present disclosure.

[0013] The sensor substrate 100 includes a semiconductor layer 100S having a pair of opposing surfaces (a front surface (surface 100S2) and a back surface (surface 100S2)), and a wiring layer 100T provided on the surface 100S2 side of the semiconductor layer 100S.

[0014] The semiconductor layer 100S has a pixel array section 110 in which a plurality of sensor pixels P are arranged in an array, and a peripheral section 120 provided around the pixel array section 110. In the pixel array section 110, for example, a photodiode PD that performs photoelectric conversion is embedded in each of the plurality of sensor pixels P as a light receiving element 111. Furthermore, a surface 100S2 of the semiconductor layer 100S is provided with, for example, one floating diffusion FD (not shown) for each sensor pixel P or for multiple sensor pixels P, and multiple pixel transistors (e.g., multiple p-MOS transistors 112 and multiple n-MOS transistors 113) that constitute a readout circuit that outputs pixel signals based on the charges output from the sensor pixels P. In addition to the multiple p-MOS transistors 112 and multiple n-MOS transistors 113, the peripheral section 120 is provided with, for example, an opening H that reaches a pad electrode 123X for electrical connection to the outside. The pad electrode 123X is exposed on the surface 100S1 side through an opening H that penetrates between the surface 100S1 and the surface 100S2 of the semiconductor layer 100S.

[0015] The semiconductor layer 100S is configured, for example, by a silicon (Si) substrate. In addition to a Si substrate, the semiconductor layer 100S can also be configured by a semiconductor substrate made of germanium (Ge), selenium (Se), carbon (C), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs).

[0016] In the wiring layer 100T, for example, wiring connected to the floating diffusion FD, wiring including the gates of the plurality of p-MOS transistors 112 and the plurality of n-MOS transistors 113 that constitute the readout circuit, and wiring 122, 123 including a pad electrode 123X are formed within an interlayer insulating layer 121. A plurality of pad portions 124 used for bonding and electrical connection with the first CoW layer 200 and the second CoW layer 300 are exposed on the surface of the wiring layer 100T (specifically, the surface of the interlayer insulating layer 121). Although not shown, the plurality of pad portions 124 are connected to the floating diffusion FD and the gates of the plurality of p-MOS transistors 112 and the plurality of n-MOS transistors 113, for example, via vias.

[0017] On the surface 100S1 side of the semiconductor layer 100S, for example, a color filter 131 and a light receiving lens 132 are provided.

[0018] The first CoW layer 200 is mounted, for example, at a position corresponding to the pixel array section 110 of the sensor substrate 100. The first CoW layer 200 has a chip structure in which multiple semiconductor layers (here, a first layer 210, a second layer 220, and a third layer 230) are stacked. One or more circuits having different technology nodes are formed in the first layer 210, the second layer 220, and the third layer 230.

[0019] Here, "different technology nodes" means that at least one of the following is different: minimum power supply voltage (Vdd), thickness of the gate insulating film of the transistors constituting each circuit, gate length (lg) and minimum gate pitch (Pg) of the transistors constituting each circuit, and wiring width and minimum wiring pitch (Pm) of the wiring provided in each circuit.

[0020] Specifically, for example, a 22 nm node analog circuit is formed on the first layer 210. For example, a 5 nm node logic circuit is formed on the second layer 220. For example, a memory such as a dynamic random access memory (DRAM) is mounted on the third layer 230. The first layer 210, the second layer 220, and the third layer 230 are electrically connected to each other by hybrid junctions.

[0021] The first layer 210 includes a semiconductor layer 210S having a pair of opposing surfaces 210S1 and 210S2, a wiring layer 210T-1 provided on the surface 210S1 side of the semiconductor layer 210S, and a wiring layer 210T-2 provided on the surface 210S2 side of the semiconductor layer 210S. A plurality of p-MOS transistors 211 and a plurality of n-MOS transistors 212 that constitute an analog circuit are provided on the surface 210S1 of the semiconductor layer 210S. The wiring layer 210T-1 includes a plurality of wirings 213 and has a plurality of pad portions 214 exposed on its surface. The wiring layer 210T-2 includes a plurality of wirings 215 and has a plurality of pad portions 216 exposed on its surface. The wiring layer 210T-1 and the wiring layer 210T-2 are electrically connected by, for example, through wirings 217 that penetrate the semiconductor layer 210S.

[0022] The second layer 220 includes a semiconductor layer 220S having a pair of opposing surfaces 220S1 and 220S2, a wiring layer 220T-1 provided on the surface 220S1 side of the semiconductor layer 220S, and a wiring layer 220T-2 provided on the surface 220S2 side of the semiconductor layer 220S. A plurality of p-MOS transistors 221 and a plurality of n-MOS transistors 222 that constitute a logic circuit are provided on the surface 220S1 of the semiconductor layer 220S. The wiring layer 220T-1 includes a plurality of wirings 223 and has a plurality of pad portions 224 exposed on its surface. The wiring layer 220T-2 includes a plurality of wirings 225 and has a plurality of pad portions 226 exposed on its surface. The wiring layer 220T-1 and the wiring layer 220T-2 are electrically connected by, for example, through wirings 227 that penetrate the semiconductor layer 220S.

[0023] The third layer 230 has a semiconductor layer 230S having a pair of opposing surfaces 230S1 and 230S2, and a wiring layer 230T provided on the surface 230S1 side of the semiconductor layer 230S. A plurality of p-MOS transistors 231 and a plurality of n-MOS transistors 232 that constitute a circuit including a MEM are provided on the surface 230S1 of the semiconductor layer 230S. The wiring layer 230T includes a plurality of wires 233, and has a plurality of pad portions 234 exposed on the surface.

[0024] The semiconductor layers 210S, 220S, and 230S are each formed of, for example, a silicon substrate. Alternatively, the semiconductor layers 210S, 220S, and 230S may be formed using different semiconductor materials. For example, the semiconductor layers 210S, 220S, and 230S may be formed using semiconductor substrates made of germanium (Ge), selenium (Se), carbon (C), or the like. For example, the semiconductor layers 210S, 220S, and 230S may be formed using compound semiconductor substrates made of silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs). For example, the semiconductor layers 210S, 220S, and 230S may be formed using a one-dimensional material such as carbon nanotubes, or a two-dimensional material such as transition metal dichalcogenides (TMDs) or graphene.

[0025] Furthermore, the plurality of p-MOS transistors 211, 221, 231 and the plurality of n-MOS transistors 212, 222, 232 provided in the first layer 210, the second layer 220, and the third layer 230 may be made of different semiconductor materials. For example, SiGe or Ge may be used for the p-MOS transistors 211, 221, 231, and Si material may be used for the n-MOS transistors 212, 222, 232. Alternatively, for example, Si material may be used for the p-MOS transistors 211, 221, 231, and GaN, GaAs, nGaAs, or the like may be used for the n-MOS transistors 212, 222, 232.

[0026] The first layer 210 and the second layer 220 are electrically connected to each other by bonding a plurality of pads 216, 224 exposed on the surfaces of the opposing wiring layers 210T-2 and 220T-1. The second layer 220 and the third layer 230 are electrically connected to each other by bonding a plurality of pads 226, 34 exposed on the surfaces of the opposing wiring layers 220T-2 and 230T-1. The sensor substrate 100 and the first CoW layer 200 are electrically connected to each other by bonding a plurality of pads 124, 214 exposed on the surfaces of the opposing wiring layers 100T and 210T-1. Each of the plurality of pads 124, 214, 216, 224, 226, 234 is formed using, for example, copper (Cu). That is, the sensor substrate 100, the first CoW layer 200, and the first layer 210, the second layer 220, and the third layer 230 constituting the first CoW layer 200 are electrically connected to one another by so-called CuCu junctions.

[0027] The second CoW layer 300 is mounted, for example, at a position corresponding to the peripheral portion 120 of the sensor substrate 100. The second CoW layer 300 is a single-layer chip including a semiconductor layer 300S having a pair of opposing surfaces 300S1 and 300S2, and a wiring layer 300T provided on the surface 300S1 side of the semiconductor layer 300S. For example, a 3 nm node logic circuit is formed in the semiconductor layer 300S. A plurality of p-MOS transistors 311 and a plurality of n-MOS transistors 312 that constitute the logic circuit are provided on the surface 300S1 of the semiconductor layer 300S. The wiring layer 300T includes a plurality of wirings 313 and has a plurality of pad portions 314 exposed on its surface.

[0028] The semiconductor layer 300S is formed, for example, by a silicon substrate. The semiconductor layer 300S may be a semiconductor substrate made of germanium (Ge), selenium (Se), carbon (C), or the like. For example, the semiconductor layer 300S may be a compound semiconductor substrate made of silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs). For example, the semiconductor layer 300S may be formed using a one-dimensional material such as carbon nanotubes, or a two-dimensional material such as transition metal dichalcogenide (TMD) or graphene.

[0029] Furthermore, the plurality of p-MOS transistors 311 and the plurality of n-MOS transistors 312 provided in the semiconductor layer 300S may be made using different semiconductor materials. For example, SiGe or Ge may be used for the p-MOS transistors 311, and Si material may be used for the n-MOS transistors 312. Alternatively, for example, Si material may be used for the p-MOS transistors 311, and GaN, GaAs, nGaAs, etc. may be used for the n-MOS transistors 312.

[0030] The sensor substrate 100 and the second CoW layer 300 are electrically connected to each other by bonding a plurality of pads 124, 314 exposed on the surfaces of the opposing wiring layers 100T and 300T. The pads 314 are formed using, for example, copper (Cu), similar to the pads 124. That is, the sensor substrate 100 and the second CoW layer 300 are electrically connected to each other by so-called Cu-Cu bonding.

[0031] 2 is a schematic diagram illustrating another example of a cross-sectional configuration of an image pickup device (image pickup device 2) according to an embodiment of the present disclosure. As shown in FIG. 2, the sensor substrate 100 may have a laminated configuration including a semiconductor layer 100S-1 in which a photodiode PD is embedded in each of a plurality of sensor pixels P, and a semiconductor layer 100S-2 having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel P.

[0032] A surface 100S2 of the semiconductor layer 100S-1 is provided with, for example, one floating diffusion FD for each sensor pixel P or for multiple sensor pixels P, multiple p-MOS transistors 112 such as transfer transistors, and multiple n-MOS transistors 113. On the surface 100S2 side of the semiconductor layer 100S, a wiring layer 100T-1 is provided within an interlayer insulating layer 121. The wiring layer 100T-1 has wirings 122 and 123 including wirings including gates of the multiple p-MOS transistors 112 and multiple n-MOS transistors 113 and pad electrodes 123X. A surface of the wiring layer 100T-1 (specifically, the surface of the interlayer insulating layer 121) has exposed pad portions 124 used for bonding and electrical connection with the semiconductor layer 100S-2.

[0033] A surface 100S3 of the semiconductor layer 100S-2 facing the semiconductor layer 100S-1 is provided with a plurality of p-MOS transistors and a plurality of n-MOS transistors that constitute a readout circuit. A wiring layer 100T-2 is provided on the surface 100S3 side of the semiconductor layer 100S-2, and the wiring layer 100T-2 has wirings 142 and 143, including wirings including gates of the plurality of p-MOS transistors and the plurality of n-MOS transistors, within an interlayer insulating layer 141. A plurality of pad portions 144 used for bonding and electrical connection with the semiconductor layer 100S-1 are exposed on the surface of the wiring layer 100T-2 (specifically, the surface of the interlayer insulating layer 141). A wiring layer 100T-3 is provided on the surface 100S4 side of the semiconductor layer 100S-2, and has wirings 146 within an interlayer insulating layer 145. A plurality of pads 147 are exposed on the surface of the wiring layer 100T-3 (specifically, the surface of the interlayer insulating layer 145) and are used for bonding and electrical connection with the first CoW layer 200 and the second CoW layer 300. The wiring layer 100T-2 and the wiring layer 100T-3 are electrically connected by, for example, through-wiring 148 that penetrates the semiconductor layer 100S-2.

[0034] In the imaging device 2, the sensor substrate 100 and the first CoW layer 200, and the sensor substrate 100 and the second CoW layer 300 are electrically connected to each other by joining a plurality of pad portions 147 and a plurality of pad portions 214, 314 exposed on their respective opposing surfaces.

[0035] [Method of Manufacturing Imaging Device] Fig. 3 shows a flow of a manufacturing process for the imaging devices 1 and 2 shown in Fig. 1 and Fig. 2. The imaging devices 1 and 2 can be manufactured, for example, as follows.

[0036] First, the first layer 210, the second layer 220, and the third layer 230 are connected to each other by Cu-Cu bonding to form the first CoW layer 200 (step S101). Next, the sensor substrate 100 is connected to the first CoW layer 200 and the second CoW layer 300 by Cu-Cu bonding, and the first CoW layer 200 and the second CoW layer 300 are mounted on the sensor substrate 100 (step S102).

[0037] Next, the surfaces 200SS2 and 300S2 of the first CoW layer 200 and the second CoW layer 300 are polished by, for example, chemical mechanical polishing (CMP) to thin them down to a predetermined thickness (step S103). Next, the insulating layer 410 is buried between the first CoW layer 200 and the second CoW layer 300 by, for example, chemical vapor deposition (CVD) (step S104).

[0038] Next, the surfaces of the films 410 provided on the surfaces 200SS2 and 300S2 of the first CoW layer 200 and the second CoW layer 300 are planarized by, for example, CMP, and then a support substrate 400 is bonded to the surfaces 200SS2 and 300S2 of the first CoW layer 200 and the second CoW layer 300. Thereafter, a back surface process is performed to form the light receiving element 111, the color filter 131, and the light receiving lens 132 on the surface 100S1 side of the sensor substrate 100. Through the above steps, the imaging devices 1 and 2 shown in FIGS. 1 and 2 are completed.

[0039] [Example of Connection of Imaging Devices] Fig. 4 shows an example of the circuit configuration of the imaging devices 1 and 2. Figs. 5 and 6 are exploded perspective views showing the manner of connection of the pixel array unit 110 of the imaging device 2 shown in Fig. 2, for example.

[0040] The first CoW layer 200 is provided at a position corresponding to the pixel array section 110 of the sensor substrate 100, and as described above, three layers (first layer 210, second layer 220 and third layer 230) with different technology nodes are stacked.

[0041] The first layer 210, including the semiconductor layer 100S-2 of the sensor substrate 100, has an analog circuit formed thereon, including a circuit configuration that amplifies pixel signals generated in the plurality of sensor pixels P and converts them into digital signals. The analog circuit is part of the image capture device 2, such as an analog-to-digital converter (ADC) 610 or a control unit that controls various components within the image capture device 1, and has a circuit configuration to which a power supply voltage for the analog circuit is supplied. As an example, the analog circuit includes various transistors (readout circuits) that read analog pixel signals from the sensor pixels P, a vertical drive circuit that drives the sensor pixels P arranged in a two-dimensional lattice pattern in rows and columns, a comparator and counter for the ADC 610, a reference voltage supply unit that supplies a reference voltage to the comparator, a phase-locked loop (PLL) circuit, a load MOS, and the like.

[0042] The second layer 220 may include, for example, a logic circuit that corrects and modulates the digital signal converted by the analog circuit 210. As an example, the second layer 220 may include a latch circuit 620, a sensor interface (SIF) 630, a digital unit (DU) 640, etc. The second layer 220 may further include an application processor (AP) or the like that includes a circuit configuration capable of machine learning such as a deep neural network (DNN).

[0043] A memory 650 such as a DRAM is formed on the third layer 230. In addition, a circuit section 660 including an interface driver (IFD) and a physical layer (PHY) is formed on the third layer 230.

[0044] The imaging device 2 has a configuration capable of analog conversion on a pixel-by-pixel basis. Specifically, for example, a signal output from a sensor pixel P is converted on a pixel-by-pixel basis in an analog circuit of, for example, a 22 nm node in the first layer 210, and correction processing is performed in a logic circuit of, for example, a 5 nm node in the second layer 220. A memory 650 is formed in the third layer 230, and is capable of linking with a learning function such as DNN.

[0045] FIG. 7 is an exploded perspective view showing a connection state of the peripheral portion 120 of the imaging device 2 shown in FIG.

[0046] As described above, the second CoW layer 300 is mounted at a position corresponding to the peripheral portion 120 of the sensor substrate 100. An interface circuit (IF) 670 is formed on the second CoW layer 300. The IF 670 includes a circuit configuration that outputs data (digital signals) processed in a logic circuit or the like formed on the second layer 220 of the first CoW layer 200 to the outside. Specifically, data processed in the DU 640 formed on the second layer 220 of the first CoW layer 200 is supplied to the IF 670, and the data is output to the outside via a pad electrode 123X provided on the sensor substrate 100.

[0047] [Functions and Effects] In the imaging device 1 of this embodiment, a first CoW layer 200 and a second CoW layer 300, each of which is formed by stacking one or more semiconductor layers having one or more circuits, are mounted side by side in the in-plane direction on the surface 100S2 of the sensor substrate 100 opposite the light incident surface (surface 100S1) on which a plurality of light receiving elements 111 are formed in an array. This allows a desired circuit chip to be mounted in a desired position. This will be described below.

[0048] In recent years, three-dimensional image sensors have been developed in which the sensor section and the control circuit section are fabricated on separate wafers and then stacked. Three-dimensional image sensors tend to require an increase in the number of signal processing circuits for correction within the sensor, as well as an increase in the amount of memory required to store processed information. To address this, image sensors equipped with a single-layer chip that combines various functions on a single chip, and image sensors equipped with three or more stacked layers of chips have been proposed.

[0049] However, image sensors with single-layer chips have limitations on the circuit area they can accommodate, making it difficult to implement the desired functions. Furthermore, simply increasing the number of stacked chips to accommodate more circuits creates issues such as increased costs and power consumption, as well as degradation of performance and reliability due to heat generated by densely packed stacked circuits. Furthermore, longer wiring distances between chips raise concerns about signal delays and increased power consumption.

[0050] In contrast, in the present embodiment, as described above, the first CoW layer 200 and the second CoW layer 300, each formed by stacking one or more semiconductor layers having one or more circuits, are mounted side by side in the in-plane direction on the surface 100S2 side opposite the light incident surface (surface 100S1) of the sensor substrate 100. As an example, the first CoW layer 200, formed by stacking three semiconductor layers (first layer 210, second layer 220, and third layer 230) on which one or more circuits of different technology nodes are formed, is mounted at a position corresponding to the pixel array section 110 of the sensor substrate 100. The second CoW layer 300, formed by a single layer (semiconductor layer 310S), is mounted at a position corresponding to the peripheral section 120 of the sensor substrate 100.

[0051] In this way, a CoW layer (e.g., the first CoW layer 200) made up of multiple stacked semiconductor layers is installed in locations where a large circuit area is required, and a single layer or a CoW layer with a small number of stacked layers (e.g., the second CoW layer 300) is installed in locations where a small circuit area is required, thereby making it possible to suppress cost increases while achieving the desired circuit operation.

[0052] As described above, the imaging devices 1 and 2 of the present embodiment can achieve both high functionality and cost reduction.

[0053] Furthermore, in the image pickup devices 1 and 2 of the present embodiment, a CoW layer formed by selectively stacking multiple semiconductor layers is mounted only in locations where a large circuit area is required, thereby reducing heat generation due to the density of the stacked circuits. For example, in the image pickup devices 1 and 2 of the present embodiment, the chip (second CoW layer 300) on which the IF circuit 670, which generates a large amount of heat, is formed has a single-layer structure, which allows the heat generated in the IF circuit 670 to dissipate to the support substrate 400. This makes it possible to reduce the occurrence of circuit defects due to chip heat generation.

[0054] Furthermore, in the imaging devices 1 and 2 of the present embodiment, a CoW layer made up of multiple semiconductor layers is mounted in a location where a large circuit area is required, which shortens the wiring distance compared to when multiple semiconductor layers are mounted side by side in a planar direction, thereby reducing signal delays and an increase in power consumption.

[0055] Furthermore, in the imaging devices 1 and 2 of the present embodiment, CoW layers having a plurality of functions can be manufactured in parallel, thereby shortening the time required for manufacturing.

[0056] Modifications of the above embodiment (Modifications 1 to 7) will be described below. In the following description, the same components as those in the above embodiment will be denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0057] 8 is an exploded perspective view showing a connection state of a pixel array unit 110 of an imaging device according to Modification 1 of the present disclosure (for example, imaging device 2). Fig. 9 is an exploded perspective view showing a connection state of a peripheral unit 120 of an imaging device according to Modification 1 of the present disclosure (for example, imaging device 2).

[0058] In the above embodiment, an example in which analog conversion is possible on a pixel-by-pixel basis has been shown, but this is not limiting. In this modified example, each sensor pixel P and the ADC 610 are connected on a circuit block basis, rather than on a pixel-by-pixel basis.

[0059] The imaging device 2 of this modified example has a plurality of vertical drive circuits and a plurality (four in this example) of AD blocks 611, 612, 613, and 614 as an ADC 610. The AD blocks 611 and 612 are provided in the semiconductor layer 100S-2 of the sensor substrate 100, and the AD blocks 613 and 614 are provided in the semiconductor layer 210S of the first layer 210 of the first CoW layer.

[0060] The plurality of sensor pixels P arranged in an array in the pixel array unit 110 are divided into a plurality of blocks (for example, four pixel blocks), and each pixel block is connected to the AD blocks 611, 612, 613, and 614 via a vertical signal line. The pixel signals output from the AD blocks 611, 612, 613, and 614 are supplied in this order to the SIF 630 and the DU 640 provided in the second layer 220.

[0061] In this manner, in this modification, each sensor pixel P is connected to the ADC 610 in circuit block units. This enables the imaging device 2 to perform high-speed driving and complex driving in addition to the same effects as those of the above embodiment.

[0062] Furthermore, in the imaging device 2 of this modified example, multiple AD blocks (AD blocks 611, 612, 613, 614) are arranged in multiple semiconductor layers (for example, semiconductor layer 100S-2 and semiconductor layer 210S), which enables high-speed driving and complex driving without increasing the size of the device.

[0063] (2-2. Modification 2) Fig. 10 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 3) according to an embodiment of the present disclosure. Fig. 11 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 4) according to an embodiment of the present disclosure. Fig. 12 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 5) according to an embodiment of the present disclosure.

[0064] In the above embodiment, an example has been shown in which the first CoW layer 200 having three stacked layers (first layer 210, second layer 220, and third layer 230) and the second CoW layer 300 having a single layer are mounted side by side on the surface 100S2 side of the sensor substrate 100, but the number of semiconductor layers constituting the first CoW layer 200 and the second CoW layer 300 is not limited to this. The imaging device 3 of this modified example has the first CoW layer 200 having two stacked layers (first layer 210 and second layer 220) and the second CoW layer 300 having two stacked layers (first layer 310 and second layer 320) mounted side by side on the surface 100S2 side of the sensor substrate 100. The imaging device 4 has a first CoW layer 200 having three stacked layers (a first layer 210, a second layer 220, and a third layer 230) and a second CoW layer 300 having three stacked layers (a first layer 310, a second layer 320, and a third layer 330) mounted side by side on the surface 100S2 side of the sensor substrate 100. The imaging device 5 has a first CoW layer 200 having three stacked layers (a first layer 210, a second layer 220, and a third layer 230) and a second CoW layer 300 having two stacked layers (the first layer 310 and the second layer 320) mounted side by side on the surface 100S2 side of the sensor substrate 100.

[0065] As described above, the second CoW layer 300 has a chip structure in which two or three semiconductor layers (the first layer 310 and the second layer 320, or the first layer 310, the second layer 320, and the third layer 330) are stacked. The first layer 310, the second layer 320, and the third layer 330 may each have one or more circuits formed therein that are of the same technology node, or one or more circuits that are different from each other.

[0066] The first layer 310 has a semiconductor layer 310S with a pair of opposing surfaces, and a wiring layer is provided on each of the pair of surfaces of the semiconductor layer 310S. The second layer 320 has a semiconductor layer 320S with a pair of opposing surfaces, and a wiring layer is provided on each of the pair of surfaces of the semiconductor layer 320S. The third layer 330 has a semiconductor layer 330S with a pair of opposing surfaces, and a wiring layer is provided on each of the pair of surfaces of the semiconductor layer 330S. The semiconductor layers 310S, 320S, and 330S are respectively provided with a plurality of p-MOS transistors 311, 322, and 332 and a plurality of n-MOS transistors 312, 322, and 332. A plurality of pad portions are exposed on the surfaces of the opposing wiring layers, and by bonding these, the first layer 310 and the second layer 220, and the second layer 220 and the third layer 230 are electrically connected to each other by hybrid junction, similar to the first CoW layer 200. The wiring layers provided on the pair of surfaces of each of the semiconductor layers 310S and 320S are electrically connected by through-wires 317 and 327 that penetrate the semiconductor layer 310S.

[0067] The semiconductor layers 310S, 320S, and 330S are each formed of, for example, a silicon substrate. The semiconductor layers 310S, 320S, and 330S may be formed of semiconductor substrates made of germanium (Ge), selenium (Se), carbon (C), or the like. For example, the semiconductor layer 300S may be formed of a compound semiconductor substrate made of silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs). For example, the semiconductor layer 300S may be formed of a one-dimensional material such as carbon nanotubes, or a two-dimensional material such as transition metal dichalcogenide (TMD) or graphene.

[0068] Furthermore, the multiple p-MOS transistors 311, 322, and 332 and the multiple n-MOS transistors 312, 322, and 332 provided in the semiconductor layers 310S, 320S, and 330S may be made using different semiconductor materials. For example, SiGe or Ge may be used for the p-MOS transistors 311, 322, and 332, and Si material may be used for the n-MOS transistors 312, 322, and 332. Alternatively, for example, Si material may be used for the p-MOS transistors 311, 322, and 332, and GaN, GaAs, nGaAs, or the like may be used for the n-MOS transistors 312, 322, and 332.

[0069] In this way, the first CoW layer 200 and the second CoW layer 300 mounted on the surface 100S2 side of the sensor substrate 100 may each have two or three semiconductor layers stacked thereon, as in the image pickup devices 3 and 4 shown in Figures 10 and 11. Also, as in the image pickup device 5 shown in Figure 12, the first CoW layer 200 may have three semiconductor layers stacked thereon and the second CoW layer 300 may have two semiconductor layers stacked thereon. In either case, the image pickup devices 3 to 5 of this modification can achieve the same effects as those of the above-described embodiment.

[0070] Alternatively, the first CoW layer 200 may be formed by stacking two semiconductor layers and the second CoW layer 300 may be formed by a single layer, or the first CoW layer 200 and the second CoW layer 300 may each be formed by stacking four or more semiconductor layers.

[0071] (2-3. Modification 3) FIG. 13 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 6) according to an embodiment of the present disclosure.

[0072] In the above embodiment, an example has been shown in which the pad electrodes 123X are provided in the wiring layer 100T of the sensor substrate 100 and connected to the outside from the surface 100S1 side via the pad electrodes 123X exposed by the openings H. However, this is not limiting. In the imaging device 6 of this modified example, terminals for external connection (bumps 515) are provided on the surfaces of the first CoW layer 200 and the second CoW layer 300 opposite to the surfaces facing the sensor substrate 100.

[0073] In the imaging device 6, insulating layers 410 and 510 are laminated on the surfaces of the first CoW layer 200 and the second CoW layer 300 opposite to the surfaces facing the sensor substrate 100. Conductive films 511, 512, and 513 are embedded in the insulating layers 410 and 510. A through electrode 514 that penetrates the semiconductor layer 320S, for example, is connected to the conductive film 511 embedded in the insulating layer 410, and the conductive film 513 is exposed on the surface of the insulating layer 510. A bump 515 used for connection to the outside is formed on the conductive film 513.

[0074] In the imaging device 6, a light-transmitting resin layer 610 and a glass substrate 620 may be provided on the surface 100S1 side of the sensor substrate 100 in order to maintain the mechanical strength of the chip.

[0075] 14 shows an example of the configuration of a circuit block with a communication chip mounted on the first CoW layer 200 and the second CoW layer 300. In the first CoW layer 200 and the second CoW layer 300 mounted on the surface 100S2 side of the sensor substrate 100, for example, an analog front-end (AFE) circuit unit 681 is formed on the second layer 320 of the second CoW layer 300, a radio frequency integrated circuit (RF-IC) 682 is formed on the first layer 310 of the second CoW layer 300, and a baseband (BB) circuit 683 is formed on the second layer 220 of the first CoW layer 200. In this case, a compound semiconductor substrate can be used for the semiconductor layer 320S of the second layer 320 on which the AFE circuit unit 681 is formed. A silicon substrate can be used for the semiconductor layer 310S of the first layer 310 on which the RF-IC 682 is formed.

[0076] In this way, when an antenna is formed below the sensor substrate 100, as in the imaging device 6 of this modified example, it is preferable to provide a terminal (bump 515) for external connection on the surface of the second CoW layer 300 opposite the surface facing the sensor substrate 100, and to provide a light-transmitting resin layer 610 and a glass substrate 620 on the surface 100S1 side of the sensor substrate 100.

[0077] (2-4. Modification 4) FIG. 21 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 7) according to Modification 4 of the present disclosure.

[0078] In the above embodiment, the thickness of the semiconductor layer 300S constituting the second CoW layer 300 is set to match the thickness of the first CoW layer 200 consisting of three layers (first layer 210, second layer 220, and third layer 230), but this is not limiting. The imaging device 7 of this modification has a second layer 320 and a third layer 330, each including a dummy semiconductor layer 320SA and 330SA, stacked on the first layer 310 of the second CoW layer 300 so as to match the heights of the semiconductor layers 210S, 220S, and 230S of the first layer 210, second layer 220, and third layer 230 constituting the first CoW layer 200. Except for this point, the imaging device 7 has substantially the same configuration as the imaging device 2 of the above embodiment.

[0079] Similar to the first CoW layer 200, the second CoW layer 300 has a chip structure in which multiple semiconductor layers (here, a first layer 310, a second layer 320, and a third layer 330) are stacked. The first layer 310 has a semiconductor layer 310S having a pair of opposing surfaces, and a wiring layer 300T is provided on the surface 200S1 side of the pair of surfaces of the semiconductor layer 310S. The semiconductor layer 310S is provided with multiple p-MOS transistors 311 and multiple n-MOS transistors 312. The second layer 320 has a semiconductor layer 320SA having a pair of opposing surfaces, and insulating layers 325A and 325B are provided on the pair of surfaces of the semiconductor layer 320SA, respectively. The third layer 330 has a semiconductor layer 330SA having a pair of opposing surfaces, and an insulating layer 325 is provided on the surface of the semiconductor layer 330SA facing the second layer 220. As described above, the semiconductor layers 320SA and 330SA are dummy semiconductor layers, and unlike the semiconductor layer 310S, no p-MOS transistors or n-MOS transistors are provided. The first layer 310 and the second layer 320, and the second layer 320 and the third layer 330 are bonded to each other by the insulating layer 315 and the insulating layer 325A, and the insulating layer 325B and the insulating layer 335, respectively.

[0080] The imaging device 7 can be manufactured, for example, as follows: Figures 22A to 22H show an example of a manufacturing process for the imaging device 7.

[0081] First, as shown in FIG. 22A, the first layer 210 of the first CoW layer 200 and the first layer 310 of the second CoW layer 300 are connected to the sensor substrate 100 by CuCu bonding.

[0082] 22B, the semiconductor layers 210S and 310S constituting the first layers 210 and 310 of the first CoW layer 200 and the second CoW layer 300 are polished by, for example, CMP to be thinned to a predetermined thickness. Subsequently, as shown in FIG. 22B, an insulating layer 410 is buried between the semiconductor layer 210S and the semiconductor layer 310S by, for example, a CVD method.

[0083] Next, as shown in FIG. 22C, the insulating layer 410 formed on the semiconductor layers 210S and 310S is removed by polishing, for example, by CMP, and then a wiring layer 210T-2 is formed on the semiconductor layer 210S, and an insulating layer 315 is formed on the semiconductor layer 310S.

[0084] Subsequently, as shown in FIG. 22D, second layers 220 and 320 are connected onto the first layers 210 and 310, respectively, by CuCu bonding.

[0085] 22E, the semiconductor layers 220S and 320SA constituting the second layers 220 and 320 of the first CoW layer 200 and the second CoW layer 300 are polished by, for example, CMP to thin them to a predetermined thickness. Subsequently, as shown in FIG. 22E, an insulating layer 410 is buried between the semiconductor layer 220S and the semiconductor layer 320SA by, for example, a CVD method.

[0086] Next, as shown in FIG. 22F, the insulating layer 410 formed on the semiconductor layers 220S and 320SA is removed, for example, by polishing using CMP, and then a wiring layer 220T-2 is formed on the semiconductor layer 220S, and an insulating layer 325B is formed on the semiconductor layer 320SA.

[0087] Subsequently, as shown in FIG. 22G, third layers 230 and 330 are respectively connected onto the second layers 220 and 320 by CuCu bonding.

[0088] Next, as shown in FIG. 22H , the semiconductor layers 230S and 330SA constituting the third layers 230 and 330 of the first CoW layer 200 and the second CoW layer 300, respectively, are polished by, for example, CMP to thin them to a predetermined thickness. Subsequently, as shown in FIG. 22H , an insulating layer 410 is buried between the semiconductor layer 230S and the semiconductor layer 330SA by, for example, a CVD method. Thereafter, a support substrate 400 is bonded onto the insulating layer 410, and then a backside process is performed to form the light receiving element 111, the color filter 131, and the light receiving lens 132 on the surface 100S1 side of the sensor substrate 100. This completes the imaging device 7 shown in FIG. 21 .

[0089] However, the manufacturing process of the imaging device 7 is not limited to this. For example, as in the above embodiment, the first CoW layer 200 and the second CoW layer 300 may be formed in advance by connecting the first layer 210, the second layer 220, and the third layer 230 constituting the first CoW layer 200 and the first layer 310, the second layer 320, and the third layer 330 constituting the second CoW layer 300, respectively, and then the sensor substrate 100 and the first CoW layer 200 and the second CoW layer 300 may be connected to each other by Cu-Cu bonding.

[0090] As described above, in the imaging device 7 of this modification, the second layer 320 and the third layer 330 including the dummy semiconductor layers 320SA and 330SA, respectively, are stacked on the surface 300S2 side of the first layer 310 of the second CoW layer 300 so as to match the heights of the semiconductor layers 210S, 220S, and 230S of the first layer 210, second layer 220, and third layer 230 constituting the first CoW layer 200. As a result, in addition to the effects of the above embodiment, the imaging device 7 of this modification has the advantage that the heights of the semiconductor layers 210S and 310S of the first layers 210 and 310, the semiconductor layers 220S and 320SA of the second layers 220 and 320, and the semiconductor layers 230S and 330SA of the third layers 230 and 330 constituting the first CoW layer 200 and the second CoW layer 300 are aligned, facilitating planarization by grinding.

[0091] Furthermore, in the imaging device 7 of this modification, as described above, the first CoW layer 200 and the second CoW layer 300 have the same semiconductor layer configuration, which makes it possible to match the thermal expansion coefficients of the first CoW layer 200 and the second CoW layer 300. Therefore, compared to the imaging device 1 of the above embodiment, the imaging device 7 of this modification can have improved heat dissipation performance and strength.

[0092] Furthermore, in the imaging device 7 of this modification, the first layers 210, 310, second layers 220, 320, and third layers 230, 330 of the first CoW layer 200 and second CoW layer 300 are stacked on the sensor substrate 100 in order with the thicknesses of the layers being uniform, thereby reducing the embedding depth of the insulating layer 410. Therefore, compared to the above-described embodiment in which the first CoW layer 200 and second CoW layer 300 are formed in advance and then the sensor substrate 100 is connected to the first CoW layer 200 and second CoW layer 300 by Cu-Cu bonding, for example, it is easier to planarize the insulating layer embedded between the first CoW layer 200 and second CoW layer 300.

[0093] (2-5. Modification 5) FIG. 23 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 7A) according to Modification 5 of the present disclosure.

[0094] In the fourth modification, the first layer 310 and the second layer 320, and the second layer 320 and the third layer 330 constituting the second CoW layer 300, are bonded to each other by the insulating layer 315 and the insulating layer 325A, and the insulating layer 325B and the insulating layer 335, respectively. However, this is not limiting. In the imaging device 7A of this modification, a plurality of pad portions 316, 324, 326, and 334 are provided on the surfaces of the insulating layers 315, 325A, 325B, and 335, which are bonded to each other, and are connected to each other by hybrid bonding. Except for this point, the imaging device 7A has substantially the same configuration as the imaging device 7 of the fourth modification.

[0095] In this way, in the imaging device 7A of this modification, the first layer 310 and the second layer 320, and the second layer 320 and the third layer 330 constituting the second CoW layer 300, are connected by hybrid junctions, respectively. Even with this configuration, the imaging device 7A of this modification can achieve the same effects as those of the seventh modification.

[0096] (2-6. Modification 6) FIG. 24 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 8) according to Modification 6 of the present disclosure.

[0097] In the above embodiment, an example was shown in which the semiconductor layer 210S of the first layer 210, the semiconductor layer 220S of the second layer 220, and the semiconductor layer 230S of the third layer 230 constituting the first CoW layer 200 have the same size, but this is not limited to this. In the imaging device 8 of this modification, the second layer 220 constituting the first CoW layer 200 includes two semiconductor layers 220A and 220B that are smaller than the semiconductor layers 210S and 230S of the first layer 210 and the third layer 230, respectively. Except for this point, the imaging device 8 has substantially the same configuration as the imaging device 1 of the above embodiment.

[0098] Note that the present technology can be combined with any of the above-described embodiments and Modifications 1 to 5. For example, the present technology can also be applied to a configuration in which a semiconductor layer 100S-1 in which a photodiode PD is embedded in each of a plurality of sensor pixels P and a semiconductor layer 100S-2 having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel P are stacked, as in the image pickup device 8A shown in FIG. 25. Furthermore, for example, the present technology can also be applied to a configuration in which a first CoW layer 200 has three stacked layers and a second CoW layer 300 has two stacked layers, as in the image pickup device 8B shown in FIG.

[0099] As described above, in the imaging devices 8, 8A, and 8B of this modification, the second layer 220 constituting the first CoW layer 200 includes two semiconductor layers 220A and 220B that are smaller than the semiconductor layers 210S and 230S of the first layer 210 and the third layer 230. This eliminates restrictions on the chips that can be mounted on the sensor substrate 100. In other words, since a general-purpose chip such as a DRAM can be used, the imaging devices 8, 8A, and 8B of this modification can achieve even higher functionality and lower costs compared to the above embodiment.

[0100] (2-7. Modification 7) FIG. 27 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 9) according to Modification 6 of the present disclosure.

[0101] In the sixth modification, the second layer 220 constituting the first CoW layer 200 includes two semiconductor layers 220A and 220B that are smaller than the semiconductor layers 210S and 230S of the first layer 210 and the third layer 230. However, the present invention is not limited to this. In the imaging device 8 of this modification, the first CoW layer 200 includes a third layer 230 on the support substrate 401, in which a plurality of semiconductor layers (here, two semiconductor layers 230SA and 230SB) that are smaller than the semiconductor layers 210S and 220S of the first layer 210 and the second layer 220 are arranged side by side. Except for this point, the imaging device 8 has substantially the same configuration as the imaging device 1 of the above embodiment.

[0102] Note that the present technology can be combined with any of the above-described embodiments and Modifications 1 to 6. For example, the present technology can be applied to a configuration in which a semiconductor layer 100S-1 in which a photodiode PD is embedded in each of a plurality of sensor pixels P and a semiconductor layer 100S-2 having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel P are stacked, as in the image pickup device 9A shown in FIG. 28 . Furthermore, for example, the present technology can be applied to a third layer 230 of the first CoW layer 200 in a configuration in which the first CoW layer 200 has three stacked layers and the second CoW layer 300 has two stacked layers, as in the image pickup device 8B shown in FIG. 29 . Furthermore, for example, the present technology can be applied to a second layer 220 of the first CoW layer 200 in a configuration in which the first CoW layer 200 has two stacked layers and the second CoW layer 300 has one stacked layer, as in the image pickup device 9C shown in FIG. 30 .

[0103] As described above, in the imaging devices 9, 9A, 9B, and 9C of this modification, the semiconductor layer mounted closest to the support substrate 400 in the first CoW layer 200 (e.g., the semiconductor layer 230S of the third layer 230) is made smaller than the semiconductor layers of the other layers (e.g., the semiconductor layers 210S and 220S of the first layer 210 and the second layer 220), and a plurality of these (here, two semiconductor layers 230SA and 230SB) are stacked side by side on the support substrate 401. This eliminates restrictions on the chips mounted on the sensor substrate 100. In other words, since a general-purpose chip such as a DRAM can be used, the imaging devices 9, 9A, 9B, and 9C of this modification can achieve even higher functionality and lower costs compared to the above embodiment.

[0104] 3. Application Examples FIG. 15 shows an example of the schematic configuration of an imaging system 10 including an imaging device (for example, imaging device 1) according to the above-described embodiment and modifications 1 to 4.

[0105] The imaging system 10 is, for example, an electronic device such as a camera, such as a digital still camera or a video camera, or a portable terminal device, such as a smartphone or a tablet terminal. The imaging system 10 includes, for example, an imaging device 1, an optical system 741, a shutter device 742, a DSP circuit 743, a frame memory 744, a display unit 745, a storage unit 746, an operation unit 747, and a power supply unit 748. In the imaging system 10, the imaging device 1, the DSP circuit 743, the frame memory 744, the display unit 745, the storage unit 746, the operation unit 747, and the power supply unit 748 are connected to each other via a bus line 749.

[0106] The imaging device 1 outputs image data corresponding to incident light. The optical system 741 includes one or more lenses, guides light from a subject (incident light) to the imaging device 1, and forms an image on the light-receiving surface of the imaging device 1. The shutter device 742 is disposed between the optical system 741 and the imaging device 1, and controls the light irradiation period and light blocking period of the imaging device 1 under the control of a drive circuit. The DSP circuit 743 is a signal processing circuit that processes signals (image data) output from the imaging device 1. The frame memory 744 temporarily stores the image data processed by the DSP circuit 743 on a frame-by-frame basis. The display unit 745 is a panel-type display device, such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the imaging device 1. The storage unit 746 records image data of moving or still images captured by the imaging device 1 on a recording medium, such as a semiconductor memory or a hard disk. The operation unit 747, in accordance with operations by the user, issues operation commands for various functions of the imaging system 10. The power supply unit 748 appropriately supplies various types of power to the imaging device 1, the DSP circuit 743, the frame memory 744, the display unit 745, the storage unit 746, and the operation unit 747 as operating power sources to these power supply targets.

[0107] Next, the imaging procedure in the imaging system 10 will be described.

[0108] 16 shows an example of a flowchart of the imaging operation in the imaging system 10. The user operates the operation unit 747 to instruct the start of imaging (step S201). The operation unit 747 then transmits an imaging command to the imaging device 1 (step S202). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit) executes imaging using a predetermined imaging method (step S203).

[0109] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 743. Here, image data refers to data for all pixels of pixel signals generated based on the charges temporarily stored in the floating diffusion FD. The DSP circuit 743 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S204). The DSP circuit 743 stores the image data that has undergone the predetermined signal processing in the frame memory 744, and the frame memory 744 stores the image data in the storage unit 746 (step S205). In this manner, imaging is performed in the imaging system 10.

[0110] In this application example, the imaging device (for example, imaging device 1) according to the above-described embodiment and its modified examples 1 to 4 is applied to an imaging system 10. This allows the imaging device 1 to be made smaller or have higher resolution, and therefore a small or high-resolution imaging system 10 can be provided.

[0111] 4. Application Examples (Application Examples to Mobile Bodies) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0112] FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0113] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 17, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown in the figure are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 as functional components of the integrated control unit 12050.

[0114] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0115] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0116] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0117] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0118] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0119] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0120] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0121] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0122] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 17, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0123] FIG. 18 is a diagram showing an example of the installation position of the imaging unit 12031.

[0124] In FIG. 18 , a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0125] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0126] 18 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0127] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0128] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0129] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0130] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0131] The foregoing has described an example of a mobile object control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 1 according to the above-described embodiment and its modified example can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a high-resolution captured image with little noise, thereby enabling high-precision control using the captured image in the mobile object control system.

[0132] (Application Example to Endoscopic Surgery System) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0133] FIG. 19 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0134] 19 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11153 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0135] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0136] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0137] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0138] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0139] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0140] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing the surgical site, etc.

[0141] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0142] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0143] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0144] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0145] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light in a narrower band than the light irradiated during normal observation (i.e., white light) to capture high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, in what is known as narrow band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or may involve locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissues with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0146] FIG. 20 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0147] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0148] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0149] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (so-called single-chip type) or multiple (so-called multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0150] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0151] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0152] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0153] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0154] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0155] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0156] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0157] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0158] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0159] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0160] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0161] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0162] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0163] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby providing a compact or high-resolution endoscope 11100.

[0164] The present disclosure has been described above by giving the embodiments and modifications 1 to 7, as well as application examples and applied examples, but the present disclosure is not limited to the above embodiments, etc., and various modifications are possible.

[0165] Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than the effects described in this specification.

[0166] The present disclosure may also be configured as follows. According to the present technology configured as follows, a desired circuit chip can be mounted at a desired position, thereby achieving both high functionality and cost reduction. (1) A semiconductor device comprising: a first substrate having opposing first and second surfaces and having a plurality of semiconductor elements formed on the first surface; a second substrate mounted on the second surface of the first substrate and formed by stacking a plurality of semiconductor layers, each having one or more circuits; and a third substrate mounted on the second surface of the first substrate in parallel with the second substrate and formed by stacking one or more semiconductor layers, each having one or more circuits. (2) The semiconductor device according to (1), wherein the second substrate and the third substrate are each formed by stacking a plurality of the semiconductor layers. (3) The semiconductor device according to either (1) or (2), wherein the second substrate and the third substrate include a different number of the semiconductor layers. (4) The semiconductor device according to any one of (1) to (3), wherein the first substrate and the second substrate, and the first substrate and the third substrate, are electrically connected to each other by hybrid bonding. (5) The semiconductor device according to any one of (1) to (4), wherein the first substrate and the second substrate, and the first substrate and the third substrate, are electrically connected to each other by Cu-Cu bonding, an insulating film is embedded between the second substrate and the third substrate, and a support substrate common to the second substrate and the third substrate is provided on the surfaces of the second substrate and the third substrate opposite to the surface bonded to the first substrate. (6) The semiconductor device according to any one of (1) to (5), wherein the second substrate and the third substrate include, as the multiple semiconductor layers, dummy semiconductor layers that do not have the one or more circuits. (7) The semiconductor device according to (6), wherein the dummy semiconductor layers are bonded to the other semiconductor layers by insulating films. (8) The semiconductor device according to (6), wherein the dummy semiconductor layer is joined to another of the semiconductor layers by hybrid junction.(9) The semiconductor device according to any one of (1) to (8), wherein the second substrate and the third substrate include semiconductor layers of different sizes as the plurality of semiconductor layers. (10) The semiconductor device according to any one of (1) to (9), wherein at least a portion of the one or more semiconductor layers constituting the second substrate and the third substrate include a plurality of semiconductor layers arranged side by side in an in-plane direction. (11) The semiconductor device according to any one of (1) to (10), wherein the plurality of semiconductor elements are a plurality of light receiving elements, the first substrate has a pixel array section in which a plurality of pixels each having the plurality of light receiving elements are arranged in an array, and a peripheral section provided around the pixel array section, the second substrate is mounted at a position corresponding to the pixel array section, and the third substrate is mounted at a position corresponding to the peripheral section. (12) The semiconductor device according to (11), wherein the first substrate includes a semiconductor layer in which the plurality of light receiving elements are provided, and the semiconductor layer includes a plurality of pixel transistors on a surface opposite to a light incident surface. (13) The semiconductor device according to (11) or (12), wherein the first substrate includes a first semiconductor layer in which the plurality of light receiving elements are provided, and a second semiconductor layer in which a plurality of pixel transistors are provided on the side opposite to the light incident surface of the first semiconductor layer. (14) The semiconductor device according to any one of (11) to (13), wherein the plurality of circuits provided in the plurality of semiconductor layers constituting the second substrate are electrically connected to each pixel. (15) The semiconductor device according to (14), wherein the second substrate includes, as the plurality of semiconductor layers, a third semiconductor layer having a plurality of analog circuits and a fourth semiconductor layer having a plurality of logic circuits, and the third semiconductor layer and the fourth semiconductor layer are stacked in this order from the first substrate side.(16) The semiconductor device according to (15), wherein the third semiconductor layer has a comparator, a negative MOS, and an analog-digital converter circuit as the plurality of analog circuits, the fourth semiconductor layer has a latch circuit, a sensor interface circuit, and a digital unit circuit as the plurality of logic circuits, and the plurality of analog circuits are connected to the plurality of logic circuits. (17) The semiconductor device according to (15) or (16), wherein the second substrate further has a fifth semiconductor layer having a memory element as the plurality of semiconductor layers. (18) The semiconductor device according to any one of (15) to (17), wherein the second substrate further has a sixth semiconductor layer having an interface circuit as the plurality of semiconductor layers. (19) The semiconductor device according to any one of (11) to (18), wherein the plurality of pixels are divided into a plurality of pixel blocks, and the plurality of circuits provided in the plurality of semiconductor layers constituting the second substrate are electrically connected to the plurality of pixel blocks, respectively. (20) The semiconductor device according to (19), wherein the second substrate has, as the plurality of semiconductor layers, a third semiconductor layer having a plurality of analog circuit units and a fourth semiconductor layer having a plurality of logic circuit units, the third semiconductor layer and the fourth semiconductor layer being stacked in this order from the first substrate side. (21) The semiconductor device according to (20), wherein the third semiconductor layer has, as the plurality of analog circuit units, a plurality of analog-digital converter blocks, the plurality of pixel blocks and the plurality of analog-digital converter blocks are respectively connected via vertical signal lines, and the plurality of analog-digital converter blocks are respectively connected to the plurality of logic circuit units. (22) The semiconductor device according to (21), wherein the second substrate further has, as the plurality of semiconductor layers, a fifth semiconductor layer having a memory element. (23) The semiconductor device according to (21) or (22), wherein the third substrate further has, as the plurality of semiconductor layers, a sixth semiconductor layer having an interface circuit.(24) The semiconductor device according to any one of (1) to (23), wherein the semiconductor layers of the second substrate and the third substrate are made of different semiconductor materials. (25) The semiconductor device according to any one of (1) to (24), wherein the semiconductor layers are made of any of silicon, silicon germanium, and germanium. (26) The semiconductor device according to any one of (1) to (25), wherein the semiconductor layers are made of a one-dimensional material or a two-dimensional material. (27) The semiconductor device according to (26), wherein the one-dimensional material is carbon nanotubes. (28) The semiconductor device according to (26), wherein the two-dimensional material is a transition metal dichalcogenide or graphene. (29) The semiconductor device according to any one of (1) to (28), wherein the semiconductor layers are made of a compound semiconductor. (30) The semiconductor device according to any one of (1) to (29), wherein the plurality of semiconductor layers include a semiconductor layer having an n-MOS transistor and a semiconductor layer having a p-MOS transistor, the semiconductor layer having the n-MOS transistor being made of silicon, and the semiconductor layer having the p-MOS transistor being made of silicon germanium or germanium. (31) The semiconductor device according to any one of (1) to (30), wherein the plurality of semiconductor layers include a semiconductor layer having an n-MOS transistor and a semiconductor layer having a p-MOS transistor, the semiconductor layer having the n-MOS transistor being made of a compound semiconductor, and the semiconductor layer having the p-MOS transistor being made of silicon. (32) The semiconductor device according to any one of (1) to (31), wherein the plurality of semiconductor layers include a semiconductor layer made of a compound semiconductor having an analog front-end circuit unit, and a semiconductor layer made of silicon having a high-frequency circuit. (33) The semiconductor device according to any one of (1) to (32), wherein a portion of the plurality of semiconductor layers forms a baseband circuit.(34) The semiconductor device according to any one of (1) to (33), further comprising: a substrate having optical transparency on the first surface side of the first substrate; and an electrode used for connection to the outside, provided on the surface of the third substrate opposite the surface facing the first substrate, wherein the first substrate and the electrode are electrically connected via a through electrode penetrating the third substrate.

[0167] This application claims priority based on Japanese Patent Application No. 2023-042942, filed on March 17, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0168] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A first substrate having opposing first and second surfaces; a second substrate mounted on the second surface of the first substrate and including a plurality of stacked semiconductor layers, each having one or more circuits; a third substrate that is arranged in parallel with the second substrate in a planar direction and mounted on the second surface of the first substrate, and that is formed by stacking one or more semiconductor layers, each having one or more circuits; the first substrate and the second substrate, and the first substrate and the third substrate are electrically connected to each other, the second substrate having the plurality of semiconductor layers and the third substrate are electrically connected; the first substrate has, in a plan view, a first region and a second region provided around the first region; the second substrate is disposed at a position corresponding to the first region; The third substrate is disposed at a position corresponding to the second region. Semiconductor device.

2. The second region is a region surrounding the first region in a plan view. The semiconductor device according to claim 1 .

3. The second substrate is disposed within the first region, and the third substrate is disposed within the second region. The semiconductor device according to claim 2 .

4. The area of ​​the second substrate in a plan view is larger than the area of ​​the third substrate in a plan view. The semiconductor device according to claim 1 .

5. At least one of the second substrate and the third substrate includes a plurality of semiconductor chips arranged side by side in the planar direction. The semiconductor device according to claim 1 .

6. At least one of the second substrate and the third substrate is formed by stacking the plurality of semiconductor layers having mutually different areas in a plan view. The semiconductor device according to claim 1 .

7. Of the plurality of semiconductor layers, a semiconductor layer having a small area has a memory element. The semiconductor device according to claim 6.

8. The plurality of semiconductor layers are electrically connected to each other by hybrid junctions. The semiconductor device according to claim 6.

9. Further comprising a support substrate, Among the plurality of semiconductor layers, a semiconductor layer having a small area is disposed in contact with the support substrate. The semiconductor device according to claim 6.

10. The second substrate and the third substrate are each configured by stacking a plurality of the semiconductor layers, In at least one of the second substrate and the third substrate, the plurality of semiconductor layers are electrically connected by electrode pads facing each other. The semiconductor device according to claim 1 .

11. At least one of the second substrate and the third substrate has a terminal for external connection on a surface opposite to a surface connected to the first substrate. The semiconductor device according to claim 1 .

12. The second substrate and the third substrate are each configured by stacking a plurality of the semiconductor layers, At least one of the second substrate and the third substrate includes a dummy semiconductor layer having no circuit as the plurality of semiconductor layers. The semiconductor device according to claim 1 .

13. Among the plurality of semiconductor layers, the dummy semiconductor layer and the other semiconductor layers are bonded via an insulating film. The semiconductor device according to claim 12.

14. Among the plurality of semiconductor layers, the dummy semiconductor layer and the other semiconductor layers are joined by hybrid junction. The semiconductor device according to claim 12.

15. The second substrate and the third substrate are each configured by stacking a plurality of the semiconductor layers, In at least one of the second substrate and the third substrate, the plurality of semiconductor layers are electrically connected to each other by hybrid junctions. The semiconductor device according to claim 1 .

16. At least one of the first substrate, the second substrate, and the third substrate has a different technology node. The semiconductor device according to claim 1 .

17. The second substrate and the third substrate are each configured by stacking a plurality of the semiconductor layers, The thicknesses of the semiconductor layers in at least one of the second substrate and the third substrate are different from each other. The semiconductor device according to claim 1 .

18. The second substrate and the third substrate have different thicknesses. The semiconductor device according to claim 1 .