Nitride semiconductor device and method for manufacturing same

Abstract

A nitride semiconductor device (10) is provided with: a substrate (12); a drift layer (14); a p-type first underlying layer (16); an electron traveling layer (24) and an electron supply layer (26) that are provided in this order from the substrate (12) side, in a portion along the inner surface of a gate opening part (22), and outside the gate opening part (22) and above the first underlying layer (16); a gate electrode (28) provided above the electron supply layer (26) so as to cover the gate opening part (22); a source electrode (32) provided away from the gate electrode (28); and a drain electrode (34) provided on a side of the substrate (12) opposite the drift layer (14). The electron traveling layer (24) has a bottom part (24a) provided along a bottom surface (22a) of the gate opening part (22), and an outer edge part (24b) provided outside the gate opening part (22). The layer thickness T1 of the bottom part (24a) is thinner than the layer thickness T2 of the outer edge part (24b).

Description

Nitride semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing the same.

[0002] Nitride semiconductors such as gallium nitride (GaN) are wide-gap semiconductors with a large band gap, and are characterized by a large dielectric breakdown field and a higher electron saturation drift velocity than GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors, etc. For this reason, research and development is being conducted on power transistors using nitride semiconductors, which are advantageous for achieving high output and high breakdown voltage.

[0003] For example, Patent Document 1 discloses a semiconductor device formed on a GaN-based stack. The semiconductor device described in Patent Document 1 is a vertical field effect transistor (FET) including a regrowth layer made of an electron transit layer and an electron supply layer positioned so as to cover an opening formed in the GaN-based stack, and a gate electrode positioned on and along the regrowth layer. A channel is formed by two-dimensional electron gas (2DEG) generated in the regrowth layer, resulting in a FET with high mobility and low on-resistance.

[0004] International Publication No. 2015 / 122135

[0005] In a vertical field effect transistor, the electron transport layer at the bottom of the opening becomes thick, which may increase the resistance value.

[0006] Therefore, the present disclosure provides a nitride semiconductor device capable of reducing the on-resistance and a method for manufacturing the same.

[0007] In order to solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a p-type second nitride semiconductor layer provided above the first nitride semiconductor layer, a third nitride semiconductor layer and a fourth nitride semiconductor layer provided in this order from the substrate side along an inner surface of a first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer, and outside the first opening and above the second nitride semiconductor layer, the third nitride semiconductor layer includes a gate electrode provided above the fourth nitride semiconductor layer so as to cover the first opening, a source electrode provided at a distance from the gate electrode, and a drain electrode provided on the substrate on the opposite side from the first nitride semiconductor layer, the third nitride semiconductor layer including a bottom portion provided along the bottom surface of the first opening and an outer edge portion provided outside the first opening, and the thickness of the bottom portion in a direction perpendicular to the main surface of the substrate is thinner than the thickness of the outer edge portion in a direction perpendicular to the main surface.

[0008] a gate electrode formed on the fourth nitride semiconductor layer so as to cover the first opening; a source electrode formed on the fourth nitride semiconductor layer at a position spaced from the gate electrode; and a drain electrode formed on the substrate opposite the first nitride semiconductor layer. The third nitride semiconductor layer is formed by epitaxial growth under conditions that promote growth in a direction parallel to a principal surface of the substrate more than a direction perpendicular to the principal surface of the substrate.

[0009] According to the present disclosure, it is possible to provide a nitride semiconductor device with low on-resistance and a method for manufacturing the same.

[0010] FIG. 1 is a plan view showing a planar layout of a nitride semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view of the nitride semiconductor device according to the embodiment. FIG. 3 is a partially enlarged cross-sectional view of FIG. 2. FIG. 4A is a cross-sectional view showing a nitride semiconductor lamination step in a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 4B is a cross-sectional view showing a resist patterning step in a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 4C is a cross-sectional view showing a gate opening formation step in a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 4D is a cross-sectional view showing a nitride semiconductor regrowth step in a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 4E is a cross-sectional view showing a gate electrode formation step in a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 4F is a cross-sectional view showing a source electrode formation step in a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a modified example of the embodiment.

[0011] (Summary of the Present Disclosure) A nitride semiconductor device according to a first aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided above the substrate, a p-type second nitride semiconductor layer provided above the first nitride semiconductor layer, a third nitride semiconductor layer and a fourth nitride semiconductor layer provided in this order from the substrate side along an inner surface of a first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer, and outside the first opening and above the second nitride semiconductor layer, and a gate electrode provided above the fourth nitride semiconductor layer so as to cover a portion of the fourth nitride semiconductor layer, a source electrode provided at a distance from the gate electrode, and a drain electrode provided on the substrate on the opposite side to the first nitride semiconductor layer, wherein the third nitride semiconductor layer includes a bottom portion provided along a bottom surface of the first opening and an outer edge portion provided outside the first opening, and a layer thickness of the bottom portion in a direction perpendicular to a major surface of the substrate is thinner than a layer thickness of the outer edge portion in a direction perpendicular to the major surface.

[0012] In this way, by thinning the thickness of the bottom of the third nitride semiconductor layer provided along the bottom surface of the first opening through which the source-drain current flows, the on-resistance can be reduced, and therefore, according to this aspect, a nitride semiconductor device with low on-resistance can be realized.

[0013] Furthermore, a nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the third nitride semiconductor layer includes a sidewall portion provided along a sidewall surface of the first opening, and the layer thickness of the sidewall portion in a direction parallel to the main surface is thicker than the layer thickness of the outer edge portion in a direction perpendicular to the main surface.

[0014] This increases the distance between the sidewall portion of the third nitride semiconductor layer and the p-type second nitride semiconductor layer, thereby suppressing a decrease in the carrier concentration of the third nitride semiconductor layer, thereby reducing the on-resistance of the nitride semiconductor device.

[0015] Furthermore, a nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the first or second aspect, further comprising a p-type fifth nitride semiconductor layer provided between the gate electrode and the fourth nitride semiconductor layer.

[0016] This allows the fifth nitride semiconductor layer to reduce the carrier concentration directly below the gate electrode, and shift the threshold voltage of the nitride semiconductor device to the positive side, thereby enabling the nitride semiconductor device according to this aspect to be realized as a normally-off FET.

[0017] Furthermore, a nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to third aspects, wherein the source electrode is provided in a second opening at a position away from the gate electrode, the second opening penetrating the fourth nitride semiconductor layer and the third nitride semiconductor layer and reaching the second nitride semiconductor layer.

[0018] This allows a depletion layer to be formed near the interface between the second nitride semiconductor layer and the first nitride semiconductor layer by a voltage applied between the source electrode and the drain electrode. The formation of the depletion layer can suppress the occurrence of leakage current between the source and drain, thereby increasing the breakdown voltage of the nitride semiconductor device.

[0019] Furthermore, a nitride semiconductor device according to a fifth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to fourth aspects, wherein, when the substrate is viewed in a plan view, the distance between an end of the gate electrode and the source electrode is shorter than the distance between an end of the first opening and the source electrode.

[0020] This allows for improved control of the channel formed in the regrown layer.

[0021] a gate electrode formed on the fourth nitride semiconductor layer so as to cover the first opening; a source electrode formed on the fourth nitride semiconductor layer at a position spaced from the gate electrode; and a drain electrode formed on the substrate opposite the first nitride semiconductor layer. The third nitride semiconductor layer is formed by epitaxial growth under conditions that promote growth in a direction parallel to a main surface of the substrate more than a direction perpendicular to the main surface of the substrate.

[0022] This allows the thickness of the bottom of the third nitride semiconductor layer provided along the bottom surface of the first opening to be thin, making it possible to manufacture a nitride semiconductor device with low on-resistance.

[0023] A seventh aspect of the present disclosure provides a method for manufacturing a nitride semiconductor device according to the sixth aspect, wherein the conditions include a film formation temperature of 1100° C. or higher.

[0024] This allows the thickness of the bottom of the third nitride semiconductor layer provided along the bottom surface of the first opening to be thin, making it possible to manufacture a nitride semiconductor device with low on-resistance.

[0025] A method for manufacturing a nitride semiconductor device according to an eighth aspect of the present disclosure is the method according to the sixth or seventh aspect, wherein the conditions include a V / III ratio of the supply material being 1000 or more.

[0026] This allows the thickness of the bottom of the third nitride semiconductor layer provided along the bottom surface of the first opening to be thin, making it possible to manufacture a nitride semiconductor device with low on-resistance.

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0028] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0029] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0030] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0031] In this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. When the planar shape of the substrate is rectangular, the x-axis and y-axis are directions parallel to a first side of the rectangle and a second side perpendicular to the first side, respectively. The z-axis is the thickness direction of the substrate. In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may also be referred to as the "lateral direction."

[0032] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided (positive side of the z-axis) is considered to be the "upper" or "upper side," and the side of the substrate on which the drain electrode is provided (negative side of the z-axis) is considered to be the "lower" or "lower side."

[0033] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0034] In this specification, unless otherwise specified, "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0035] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0036] (Embodiment) [Configuration] First, the configuration of a nitride semiconductor device according to an embodiment will be described with reference to FIGS. 1 to 3. FIG.

[0037] Fig. 1 is a plan view showing a planar layout of a nitride semiconductor device 10 according to this embodiment. Fig. 2 is a cross-sectional view of the nitride semiconductor device 10 according to this embodiment. Fig. 3 is an enlarged cross-sectional view of a portion of Fig. 2. Specifically, a portion of the electron transit layer 24 in Fig. 2 is shown enlarged.

[0038] Here, (a) of Fig. 1 is a plan view of the nitride semiconductor device 10 as viewed from above. (b) of Fig. 1 is an enlarged view of one unit cell 11 of the nitride semiconductor device 10. Fig. 2 shows a cross section of the nitride semiconductor device 10 according to this embodiment taken along line II-II in Fig. 1.

[0039] As shown in FIG. 1A, a nitride semiconductor device 10 includes a plurality of unit cells 11. The unit cells 11 are arranged two-dimensionally. Each of the unit cells 11 has the same configuration. The shape of each unit cell 11 in a plan view is hexagonal. The unit cells 11 are arranged so that the centers of the respective unit cells 11 are located at the vertices of equilateral triangles that are packed together in a plan view.

[0040] Each unit cell 11 is configured with one source electrode 32 at its center. 2 shows a cross section taken along line II-II passing through the centers of two adjacent unit cells 11.

[0041] In this embodiment, the nitride semiconductor device 10 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 10 has a heterostructure of an AlGaN film and a GaN film.

[0042] In a heterostructure of an AlGaN film and a GaN film, spontaneous polarization or piezoelectric polarization on the C-plane, which is represented by the (0001) plane, generates a high concentration of two-dimensional electron gas (2DEG) 40 at the heterointerface. Therefore, even in an undoped state, a high concentration of 1×10 １３ cm －２ The sheet carrier concentration can be obtained as above.

[0043] As shown in Fig. 2, the nitride semiconductor device 10 includes a substrate 12, a drift layer 14, a first underlayer 16, a second underlayer 18, a third underlayer 20, a gate opening 22, an electron transit layer 24, an electron supply layer 26, a gate electrode 28, a source opening 30, a source electrode 32, and a drain electrode 34. Furthermore, as shown in Fig. 1A, the nitride semiconductor device 10 includes a gate electrode pad 36 and a source electrode pad 38. Note that in Fig. 1A, the outline of the source electrode pad 38 is schematically represented by a dashed line.

[0044] Each of the components included in the nitride semiconductor device 10 will be described in detail below.

[0045] The substrate 12 is made of a nitride semiconductor and has a first major surface 12a and a second major surface 12b facing each other. The first major surface 12a is the major surface on which the drift layer 14 is formed. Specifically, the first major surface 12a substantially coincides with the C-plane. The second major surface 12b is the major surface on which the drain electrode 34 is formed.

[0046] The substrate 12 has a thickness of, for example, 300 μm and a carrier concentration of 1×10 １８ cm －３ The substrate is made of n-type GaN, where n-type and p-type indicate the conductivity types of semiconductors. In this embodiment, n-type is an example of a first conductivity type of a nitride semiconductor. P-type is an example of a second conductivity type having a polarity different from that of the first conductivity type.

[0047] Furthermore, the substrate 12 does not have to be a nitride semiconductor substrate. For example, the substrate 12 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, or the like.

[0048] The drift layer 14 is an example of an n-type first nitride semiconductor layer provided above the first major surface 12a of the substrate 12. The drift layer 14 has a thickness of, for example, 8 μm and a carrier concentration of 1×10 １６ cm －３ The drift layer 14 is a film made of n-type GaN, where n is a GaN film having a conductivity type of 0.1 to 0.2 μm. The drift layer 14 is provided in contact with the first main surface 12 a of the substrate 12 .

[0049] The first underlayer 16 is an example of a p-type second nitride semiconductor layer provided above the drift layer 14. The first underlayer 16 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The first underlayer 16 is a film made of p-type GaN, where p is a p-type GaN film. The first underlayer 16 is provided in contact with the upper surface of the drift layer 14.

[0050] The first underlayer 16 suppresses leakage current between the source electrode 32 and the drain electrode 34. For example, when a reverse voltage is applied to the pn junction formed between the first underlayer 16 and the drift layer 14, specifically when the drain electrode 34 has a higher potential than the source electrode 32, a depletion layer extends into the drift layer 14. This allows the nitride semiconductor device 10 to have a high breakdown voltage.

[0051] The second underlayer 18 is provided on the first underlayer 16. The second underlayer 18 is formed of an insulating or semi-insulating nitride semiconductor. The second underlayer 18 is, for example, a film made of undoped GaN with a thickness of 200 nm. The second underlayer 18 is provided in contact with the first underlayer 16.

[0052] Here, "undoped" means that the GaN is not doped with a dopant such as silicon (Si) or magnesium (Mg) that changes the polarity of the GaN to n-type or p-type. In this embodiment, the second underlayer 18 is doped with carbon, but can be considered an undoped nitride semiconductor. Specifically, the carbon concentration of the second underlayer 18 is higher than the carbon concentration of the first underlayer 16.

[0053] The second underlayer 18 may contain silicon (Si) or oxygen (O) that is mixed in during film formation. In this case, the carbon concentration of the second underlayer 18 is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ The silicon concentration or oxygen concentration of the second underlayer 18 may be, for example, 5×10 １６ cm －３ The following is 2 x 10 １６ cm－３ The following is also acceptable.

[0054] If the nitride semiconductor device 10 does not include the second underlayer 18, a p / n / p stacked structure, i.e., a stacked structure of n-type electron supply layer 26 and electron transit layer 24 / p-type first underlayer 16 / n-type drift layer 14, is formed between the source electrode 32 and the drain electrode 34. This stacked structure forms a parasitic bipolar transistor having a parasitic npn structure.

[0055] When the nitride semiconductor device 10 is in an off state, if a current flows through the first underlayer 16, this parasitic bipolar transistor may turn on, reducing the breakdown voltage of the nitride semiconductor device 10. In this case, the nitride semiconductor device 10 is likely to malfunction.

[0056] The second underlayer 18 suppresses the formation of this parasitic npn structure, thereby reducing malfunction of the nitride semiconductor device 10 due to the formation of the parasitic npn structure. Note that if the current flowing through the first underlayer 16 is sufficiently suppressed, the nitride semiconductor device 10 does not need to include the second underlayer 18.

[0057] The third underlayer 20 is provided on the second underlayer 18. The third underlayer 20 is, for example, an Al 2 O 3 layer having a thickness of 20 nm. ０．２ Ga ０．８ The third underlayer 20 is a film made of N. The third underlayer 20 is provided in contact with the second underlayer 18 .

[0058] The third underlayer 20 suppresses the diffusion of p-type impurities such as Mg from the first underlayer 16. If Mg diffuses into the channel in the electron transit layer 24, the carrier concentration of the two-dimensional electron gas 40 may decrease, resulting in an increase in on-resistance. The degree of Mg diffusion varies depending on the growth conditions of the epitaxial growth, etc. Therefore, if the diffusion of Mg is suppressed, the nitride semiconductor device 10 does not need to include the third underlayer 20.

[0059] The third underlayer 20 may also have a function of supplying electrons to a channel formed at the interface between the electron transit layer 24 and the electron supply layer 26. The third underlayer 20 has a band gap larger than that of the electron supply layer 26, for example.

[0060] The gate opening 22 is an example of a first opening that penetrates the first underlayer 16 and reaches the drift layer 14. Specifically, the gate opening 22 penetrates from the top surface of the third underlayer 20, through the third underlayer 20, the second underlayer 18, and the first underlayer 16 in this order, and reaches the drift layer 14. A bottom surface 22 a of the gate opening 22 is the top surface of the drift layer 14. In this embodiment, as shown in FIG. 2 , the bottom surface 22 a of the gate opening 22 is located below the interface between the drift layer 14 and the first underlayer 16.

[0061] In this embodiment, the gate opening 22 is formed so that the opening area increases with increasing distance from the substrate 12. Specifically, the sidewall surface 22b of the gate opening 22 is inclined obliquely with respect to the first main surface 12a (xy plane) of the substrate 12. For example, the cross-sectional shape of the gate opening 22 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0062] The electron transit layer 24 is an example of a third nitride semiconductor layer provided along the inner surface of the gate opening 22 and outside the gate opening 22 and above the first underlayer 16. Specifically, the electron transit layer 24 is formed along the top surface of the third underlayer 20 and along the sidewall surface 22b and bottom surface 22a of the gate opening 22.

[0063] As shown in FIG. 3, the electron transit layer 24 includes a bottom portion 24a, an outer edge portion 24b, and a sidewall portion 24c.

[0064] The bottom 24a is a portion provided along the bottom surface 22a of the gate opening 22. The bottom surface 24a is a portion whose lower and upper surfaces are parallel and whose thickness is substantially uniform. The lower surface of the bottom 24a contacts the drift layer 14 at the bottom surface 22a of the gate opening 22, and the upper surface of the bottom 24a contacts the electron supply layer 26.

[0065] The outer edge 24b is a portion provided outside the gate opening 22. Specifically, in a plan view, the outer edge 24b corresponds to the section from the upper end of the sidewall surface 22b of the gate opening 22 to the upper end of the sidewall surface 30b of the source opening 30. The lower and upper surfaces of the outer edge 24b are parallel to each other and the thickness is substantially uniform. The lower surface of the outer edge 24b is in contact with the third underlayer 20, and the upper surface of the outer edge 24b is in contact with the electron supply layer 26.

[0066] The sidewall portion 24c is a portion provided along the sidewall surface 22b of the gate opening portion 22. In this embodiment, since the sidewall surface 22b is inclined with respect to the first main surface 12a, the sidewall portion 24c is also inclined obliquely. The lower surface of the sidewall portion 24c is in contact with the side surfaces of the third underlayer 20, the second underlayer 18, and the first underlayer 16 at the sidewall surface 22b of the gate opening portion 22. The upper surface of the sidewall portion 24c is in contact with the electron supply layer 26. The lower and upper surfaces of the sidewall portion 24c are the lower and upper inclined surfaces, respectively, of the surface of the sidewall portion 24c.

[0067] The electron transit layer 24 has a channel. Specifically, a two-dimensional electron gas 40 is generated near the interface between the electron transit layer 24 and the electron supply layer 26. The two-dimensional electron gas 40 functions as the channel of the electron transit layer 24. In FIGS. 2 and 3 , the two-dimensional electron gas 40 is schematically illustrated by a dashed line. The electron transit layer 24 is, for example, a film made of undoped GaN. Alternatively, the electron transit layer 24 may be made n-type by, for example, doping with Si.

[0068] In this embodiment, the thickness of the electron transit layer 24 varies depending on the region. Specifically, the thickness T1 (thickness in the z-axis direction) of the bottom portion 24a in a direction perpendicular to the first major surface 12a of the substrate 12 is thinner than the thickness T2 (thickness in the z-axis direction) of the outer edge portion 24b in a direction perpendicular to the first major surface 12a. For example, the thickness T1 of the bottom portion 24a is 20 nm, and the thickness T2 of the outer edge portion 24b is 100 nm. Note that these values ​​of the thicknesses T1 and T2 are merely examples. For example, the ratio of the thickness T1 of the bottom portion 24a to the thickness T2 of the outer edge portion 24b is in the range of 0.1 to 0.5, and may be 0.1 to 0.2.

[0069] The bottom portion 24a is a portion through which a source-drain current flows in the z-axis direction between the two-dimensional electron gas 40 and the drift layer 14. Since the bottom portion 24a has a small thickness, the on-resistance can be reduced.

[0070] Note that, for example, when the width (length in the x-axis direction) of the bottom surface 22a is short, there may be almost no portion along the bottom surface 22a where the thickness of the electron transit layer 24 is substantially uniform. In this case, the thickness T1 of the bottom portion 24a can be regarded as the minimum value of the thickness of the electron transit layer 24 within the area that overlaps the bottom surface 22a in plan view.

[0071] Alternatively, the thickness T1 of the bottom portion 24 a may be considered to be the thickness of the electron transit layer 24 at the center point in the x-axis direction of the gate opening 22 or the bottom surface 22 a. Similarly, the thickness T2 of the outer edge portion 24 b may be considered to be the thickness of the electron transit layer 24 at the center point in the x-axis direction between the upper end of the sidewall surface 22 b of the gate opening 22 and the upper end of the sidewall surface 30 b of the source opening 30.

[0072] In this embodiment, the thickness T3 of the sidewall portion 24c in a direction parallel to the first major surface 12a of the substrate 12 (thickness in the x-axis direction) is thicker than the thickness T2 of the outer edge portion 24b in a direction perpendicular to the first major surface 12a of the substrate 12 (thickness in the z-axis direction). For example, the thickness T3 of the sidewall portion 24c is 200 nm, and the thickness of the outer edge portion 24b is 100 nm. Note that these values ​​of the thicknesses T2 and T3 are merely examples.

[0073] This increases the distance between the sidewall portion 24c and the p-type second underlayer 18, thereby suppressing a decrease in the carrier concentration of the electron transit layer 24. This makes it possible to reduce the on-resistance of the nitride semiconductor device 10.

[0074] The electron transit layer 24 is an example of a first regrowth layer formed by crystal regrowth after the formation of the gate opening 22. Although not shown, in this embodiment, an AlN film having a thickness of approximately 1 nm is provided as a second regrowth layer between the electron transit layer 24 and the electron supply layer 26. The AlN film can suppress alloy scattering and improve channel mobility. The AlN film does not necessarily have to be provided, and the electron transit layer 24 and the electron supply layer 26 may be in direct contact with each other. The electron supply layer 26 is an example of a third regrowth layer formed by crystal regrowth after the formation of the electron transit layer 24.

[0075] The electron supply layer 26 is an example of a fourth nitride semiconductor layer provided along the inner surface of the gate opening 22, outside the gate opening 22, and above the first underlayer 16. The electron transit layer 24 and the electron supply layer 26 are provided in this order from the substrate 12 side. The electron supply layer 26 is formed with a substantially uniform thickness. The electron supply layer 26 is, for example, a 50 nm thick undoped Al ０．２ Ga ０．８ It is a film made of N.

[0076] The electron supply layer 26 supplies electrons to the channel formed in the electron transit layer 24. As described above, in this embodiment, the third underlayer 20 also has an electron supply function. Both the electron supply layer 26 and the third underlayer 20 are formed of AlGaN, but the Al composition ratio therein is not particularly limited. For example, the Al composition ratio of the electron supply layer 26 may be 20%, and the Al composition ratio of the third underlayer 20 may be 25%.

[0077] The composition ratio of group III elements in a nitride semiconductor (layer) refers to the ratio of the number of atoms of a target group III element among a plurality of group III elements contained in the nitride semiconductor. For example, when a nitride semiconductor layer is made of Al ａ Ga ｂ In the case where the nitride semiconductor layer is made of N (a+b=1, a≧0, b≧0), the Al composition ratio of the nitride semiconductor layer can be expressed as a / (a+b). Similarly, the Ga composition ratio can be expressed as b / (a+b).

[0078] The gate electrode 28 is provided above the electron supply layer 26 and covers the gate opening 22. In this embodiment, the gate electrode 28 is formed to a shape that conforms to the upper surface of the electron supply layer 26, to be in contact with the upper surface of the electron supply layer 26, and to have a substantially uniform thickness.

[0079] The gate electrode 28 is formed using a conductive material such as a metal. For example, the gate electrode 28 is formed using palladium (Pd). Note that the material of the gate electrode 28 can be a material that can be Schottky-connected to an n-type semiconductor, such as a nickel (Ni)-based material, tungsten silicide (WSi), or gold (Au).

[0080] The gate electrode 28 is formed to be spaced apart in a plan view so as not to come into contact with the source electrode 32. Specifically, as shown in Fig. 1B, the gate electrode 28 is provided so as to surround the source electrode 32 in a plan view. More specifically, the gate electrode 28 is formed in the shape of a plate in which a plurality of openings corresponding to the hexagonal source electrodes 32 are provided.

[0081] In this embodiment, in a plan view, the end of the gate electrode 28 is located closer to the source electrode 32 than the end of the gate opening 22. That is, in a plan view, the distance between the end of the gate electrode 28 and the source electrode 32 is shorter than the distance between the end of the gate opening 22 and the source electrode 32. Specifically, in a plan view, the gate opening 22 is provided inside the gate electrode 28. In other words, the gate electrode 28 is provided directly above the upper end of the sidewall surface 22b of the gate opening 22.

[0082] The source opening 30 is an example of a second opening that penetrates the electron supply layer 26 and the electron transit layer 24 at a position away from the gate electrode 28 and reaches the first underlayer 16. Specifically, the source opening 30 penetrates the electron supply layer 26, the electron transit layer 24, the third underlayer 20, and the second underlayer 18 in this order, reaching the first underlayer 16. In this embodiment, as shown in FIG. 2 , a bottom surface 30 a of the source opening 30 is the upper surface of the first underlayer 16. The bottom surface 30 a is located below the interface between the first underlayer 16 and the second underlayer 18. The source opening 30 is located at a position away from the gate opening 22 in a plan view.

[0083] 2, the source opening 30 is formed with a substantially constant opening area. Specifically, the sidewall surfaces 30b of the source opening 30 are parallel to the thickness direction (z-axis direction) of the substrate 12. For example, the cross-sectional shape of the source opening 30 is rectangular. Alternatively, the cross-sectional shape of the source opening 30 may be an inverted trapezoid, similar to the gate opening 22.

[0084] In this embodiment, the opening shape of the source opening 30, i.e., the shape in a plan view, is a regular hexagon as shown in FIG. 1B. The distance from the gate electrode 28 provided so as to surround the outer periphery of the source opening 30 is constant. The sidewall surface 30b of the source opening 30 has a {1-100} plane. Here, the {1-100} plane collectively refers to the (1-100) plane and a plane equivalent to the (1-100) plane.

[0085] The source electrode 32 is provided in the source opening 30. Specifically, the source electrode 32 is provided so as to fill the source opening 30.

[0086] The source electrode 32 is electrically connected to the first underlayer 16. Specifically, the source electrode 32 is in contact with the end faces of the electron supply layer 26, the electron transit layer 24, the third underlayer 20, and the second underlayer 18. The source electrode 32 is in ohmic contact with the electron transit layer 24 and the electron supply layer 26.

[0087] The source electrode 32 is formed using a conductive material such as a metal, and may be made of a material that forms an ohmic contact with the n-type semiconductor layer, such as a layered structure of Ti and Al.

[0088] Since the source electrode 32 is connected to the first underlayer 16, the potential of the p-type first underlayer 16 can be fixed, thereby stabilizing the operation of the nitride semiconductor device 10.

[0089] Furthermore, Al is Schottky-contacted to the first underlayer 16 made of a p-type nitride semiconductor. Therefore, a metal material with a large work function, such as Pd or Ni, which has low contact resistance with the p-type nitride semiconductor, may be provided in the lower layer portion of the source electrode 32. This makes it possible to further stabilize the potential of the first underlayer 16.

[0090] The drain electrode 34 is provided on the second major surface 12b side of the substrate 12. Specifically, the drain electrode 34 is provided in contact with the second major surface 12b. The drain electrode 34 is formed using a conductive material such as a metal. As with the material of the source electrode 32, the material of the drain electrode 34 may be a material that forms an ohmic contact with the n-type semiconductor layer, such as Ti / Al.

[0091] The gate electrode pad 36 is electrically connected to the gate electrode 28. The gate electrode pad 36 is provided, for example, above the gate electrode 28. In this embodiment, the gate electrode 28 is formed in the shape of a single plate, and therefore, as shown in FIG. 1A, the gate electrode pad 36 is provided in only a partial region in a plan view of the nitride semiconductor device 10. A power supply for controlling the gate electrode 28 is connected to the gate electrode pad 36.

[0092] The source electrode pad 38 is electrically connected to each of the plurality of source electrodes 32. The source electrode pad 38 is provided above the source electrodes 32. In the present embodiment, each of the plurality of source electrodes 32 is formed in a hexagonal island shape. Therefore, the source electrode pad 38 is provided in most of the region excluding the gate electrode pad 36 in a plan view of the nitride semiconductor device 10 so as to cover each of the plurality of source electrodes 32.

[0093] As described above, in the nitride semiconductor device 10 according to this embodiment, the interface between the electron transit layer 24 and the electron supply layer 26 is an AlGaN / GaN heterointerface. This generates a two-dimensional electron gas 40 in the electron transit layer 24, forming a channel. The two-dimensional electron gas 40 has a high carrier concentration, which increases the mobility of the channel and reduces the on-resistance. The bottom portion 24a, which is the portion through which the source-drain current flows in the z-axis direction between the two-dimensional electron gas 40 and the drift layer 14, has a thin film thickness, which further reduces the on-resistance.

[0094] [Manufacturing Method] Next, a manufacturing method of nitride semiconductor device 10 according to this embodiment will be described with reference to Figures 4A to 4F. Figures 4A to 4F are cross-sectional views showing respective steps of the manufacturing method of nitride semiconductor device 10 according to this embodiment.

[0095] The following describes a case where each nitride semiconductor layer constituting the nitride semiconductor device 10 is formed by metal organic vapor phase epitaxy (MOVPE). However, the method for forming the nitride semiconductor layers is not limited to this, and they may also be formed by molecular beam epitaxy (MBE), for example.

[0096] An n-type nitride semiconductor is formed by adding, for example, silicon (Si), and a p-type nitride semiconductor is formed by adding magnesium (Mg). Note that the n-type impurities and p-type impurities are not limited to these.

[0097] First, a process of forming a first nitride semiconductor layer and a p-type second nitride semiconductor layer in this order above a substrate is performed. Specifically, a substrate 12 is prepared, which is made of n-type GaN and has a first main surface 12a that is a (0001) plane, i.e., a C-plane. As shown in FIG. 4A , an n-type GaN film 13 doped with Si as an n-type impurity, a p-type GaN film 15 doped with Mg as a p-type impurity, an undoped GaN film 17, and an undoped Al film 18 are formed on the first main surface 12a of the substrate 12. ０．２ Ga ０．８ An undoped AlGaN film 19 made of N is formed in this order.

[0098] Here, n-type GaN film 13 is an example of a first nitride semiconductor layer, and p-type GaN film 15 is an example of a second nitride semiconductor layer. Note that n-type GaN film 13, p-type GaN film 15, undoped GaN film 17, and undoped AlGaN film 19 are patterned into predetermined shapes to become drift layer 14, first underlayer 16, second underlayer 18, and third underlayer 20 shown in FIG. 2 , respectively.

[0099] The thickness and carrier concentration of each layer are, for example, as follows: the n-type GaN film 13 has a thickness of 8 μm and a carrier concentration of 1×10 １６ cm －３ The p-type GaN film 15 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The undoped GaN film 17 has a thickness of 200 nm. The undoped AlGaN film 19 has a thickness of 20 nm. These values ​​are merely examples.

[0100] A step of forming a first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer is performed. Specifically, as shown in Fig. 4B, a resist is first applied to the undoped AlGaN film 19, and the applied resist is patterned by photolithography to form a resist mask 90. ​​The resist mask 90 is a mask for forming the gate opening 22, and has an opening 91 that corresponds to the shape of the gate opening 22 in a plan view.

[0101] Next, as shown in FIG. 4C , a gate opening 22 is formed by dry etching. The gate opening 22 is an example of a first opening, and penetrates the undoped AlGaN film 19, the undoped GaN film 17, and the p-type GaN film 15. The drift layer 14 is formed by removing a surface portion of the n-type GaN film 13. The drift layer 14 is exposed in the gate opening 22. At this time, a bottom surface 22a of the gate opening 22 is parallel to the first main surface 12a of the substrate 12. A sidewall surface 22b of the gate opening 22 is inclined at a predetermined inclination angle with respect to the bottom surface 22a. The inclination angle is, for example, in the range of 20° to 80°.

[0102] Next, a step of forming a third nitride semiconductor layer and a fourth nitride semiconductor layer in this order is performed on the portion along the inner surface of the first opening, the outside of the first opening, and above the second nitride semiconductor layer. Specifically, after removing the resist mask 90, an undoped GaN film 21, an undoped AlN film (not shown), and an undoped AlGaN film 23 are formed in this order by MOVPE over the entire surface along the shape of the gate opening 22, as shown in FIG.

[0103] Here, the undoped GaN film 21 is an example of a third nitride semiconductor layer, and the undoped AlGaN film 23 is an example of a fourth nitride semiconductor layer. The undoped GaN film 21 and the undoped AlGaN film 23 are patterned into predetermined shapes to become an electron transit layer 24 and an electron supply layer 26, respectively.

[0104] In the process of forming the third nitride semiconductor layer, the third nitride semiconductor layer is formed by epitaxial growth under conditions that promote growth in a direction parallel to the substrate's main surface more than in a direction perpendicular to the main surface. Specifically, when depositing the undoped GaN film 21 that forms the basis of the electron transit layer 24, epitaxial growth is performed under conditions that promote growth in directions parallel to the first main surface 12a (x-axis and y-axis directions) of the substrate 12 more than in a direction perpendicular to the first main surface 12a (z-axis direction). These conditions promote migration of the supplied materials during epitaxial growth. This allows the thickness of the electron transit layer 24 to be different at the bottom 24a, outer edge 24b, and sidewall 24c.

[0105] Generally, film formation progresses in the z-axis direction along the bottom surface 22a of the gate opening 22, while film formation progresses in the x-axis direction along the sidewall surface 22b of the gate opening 22. By promoting migration, the source material that reaches the bottom surface 22a of the gate opening 22 moves actively and is easily incorporated into the portion along the sidewall surface 22b of the gate opening 22. Therefore, film formation from the sidewall surface 22b of the gate opening 22 in the x-axis direction is promoted, resulting in a thicker layer in the x-axis direction. Meanwhile, source material is depleted along the bottom surface 22a of the gate opening 22, so film formation in the z-axis direction is suppressed at the bottom surface 22a of the gate opening 22. This allows the layer thickness of the bottom portion 24a along the bottom surface 22a of the gate opening 22 to be thinned without thinning the layer thickness of the outer peripheral portion 24b of the gate opening 22.

[0106] One condition for promoting migration is increasing the film formation temperature. Experimental results showed that when the film formation temperature of the undoped GaN film 21 was set to 1080°C, the thickness T2 of the outer edge portion 24b, the thickness T1 of the bottom portion 24a, and the thickness T3 of the sidewall portion were 100 nm, 150 nm, and 100 nm, respectively. In contrast, when the film formation temperature of the electron transit layer was increased by 20°C to 1100°C, the thickness T2 of the outer edge portion 24b, the thickness T1 of the bottom portion 24a, and the thickness T3 of the sidewall portion 24c were 100 nm, 20 nm, and 200 nm, respectively. This shows that by increasing the film formation temperature and promoting migration, the thickness T1 of the bottom portion 24a of the electron transit layer 24 can be reduced.

[0107] For example, the deposition temperature of the undoped GaN film 21 is 1100°C or higher and 1200°C or lower. The deposition temperature range exemplified here is merely an example. For example, the lower limit of the deposition temperature may be 1100°C, 1100°C, 1120°C, 1130°C, 1140°C, or 1150°C. The upper limit of the deposition temperature may be 1200°C, 1190°C, 1180°C, 1170°C, 1160°C, or 1150°C. Increasing the deposition temperature promotes crystal growth in the x-axis direction and can further reduce the layer thickness T1 of the bottom portion 24a. On the other hand, not raising the deposition temperature too high can suppress decomposition of GaN and improve the surface condition, thereby improving the reliability of the nitride semiconductor device 10.

[0108] Another condition for promoting migration is to increase the V / III ratio. The V / III ratio is the molar ratio of the Group V source material to the Group III source material per unit time, and is expressed as (molar amount of Group V source material) / (molar amount of Group III source material). For example, migration can be promoted by keeping the supply amount of ammonia, a Group V source material, constant and decreasing the supply amount of trimethylgallium, a Group III source material, and the same effect as increasing the film formation temperature can be obtained.

[0109] For example, the V / III ratio during deposition of the undoped GaN film 21 is 1,000 or more and 50,000 or less. The V / III ratio may be 5,000 or more and 20,000 or less. Note that the V / III ratio ranges exemplified here are merely examples. For example, the lower limit of the V / III ratio may be 1,000, 5,000, 7,000, or 10,000. The upper limit of the V / III ratio may be 50,000, 40,000, 30,000, or 20,000. Increasing the V / III ratio promotes crystal growth in the x-axis direction, thereby making the layer thickness T1 of the bottom portion 24a thinner. On the other hand, not increasing the V / III ratio too much can shorten the deposition time, thereby improving productivity.

[0110] To promote migration, both the film formation temperature and the V / III ratio may be adjusted.

[0111] The undoped AlN film has a thickness of 1 nm, and the undoped AlGaN film 23 has a thickness of 50 nm. These values ​​are merely examples.

[0112] Next, a step of forming a gate electrode above the fourth nitride semiconductor layer is performed so as to cover the first opening. Specifically, a gate metal film made of Pd is formed by evaporation, sputtering, or the like so as to cover the gate opening 22. As shown in FIG. 4E , the formed gate metal film is patterned to form a gate electrode 28.

[0113] Furthermore, a step of forming a source electrode is performed at a position away from the gate electrode. Specifically, a source opening 30 is formed at a position away from the gate electrode 28, penetrating the undoped AlGaN film 23, the undoped AlN film (not shown), the undoped GaN film 21, the undoped AlGaN film 19, and the undoped GaN film 17 and reaching the p-type GaN film 15. The source opening 30 is formed by photolithography and dry etching, similar to the gate opening 22. As shown in FIG. 4F , the undoped AlGaN film 23, the undoped GaN film 21, the undoped AlGaN film 19, the undoped GaN film 17, and the p-type GaN film 15 are each patterned to form an electron supply layer 26, an electron transit layer 24, a third underlayer 20, a second underlayer 18, and a first underlayer 16.

[0114] Subsequently, a source metal film made of Ti and Au is formed by vapor deposition or sputtering so as to fill the source opening 30 and is then patterned to form a source electrode 32 .

[0115] Furthermore, a step of forming a drain electrode is performed on the side of the substrate opposite to the first nitride semiconductor layer. Specifically, a drain metal film made of Ti and Al is formed on the second main surface 12b of the substrate 12 by vapor deposition or sputtering, and is patterned as necessary to form the drain electrode 34.

[0116] Through the above steps, the nitride semiconductor device 10 shown in FIG. 2 is formed.

[0117] After the gate electrode 28 and the source electrode 32 are formed, an insulating film is formed, and contact holes are formed in the formed insulating film to expose a portion of each of the plurality of source electrodes 32 and a portion of the gate electrode 28. Thereafter, a metal film is formed and patterned to form the gate electrode pad 36 and the source electrode pad 38.

[0118] [Modification] A modification of the nitride semiconductor device 10 according to the present embodiment will now be described with reference to FIG.

[0119] Fig. 5 is a cross-sectional view of a nitride semiconductor device 110 according to this modification. As shown in Fig. 5, the nitride semiconductor device 110 differs from the nitride semiconductor device 10 shown in Fig. 2 in that it includes a threshold control layer 42. The following description will focus on the differences from the embodiment, and description of the commonalities will be omitted or simplified.

[0120] The threshold control layer 42 is an example of a p-type fifth nitride semiconductor layer provided between the gate electrode 28 and the electron supply layer 26. The threshold control layer 42 is provided on the electron supply layer 26 and is in contact with the electron supply layer 26 and the gate electrode 28.

[0121] In this modification, when the substrate 12 is viewed from above, the end of the threshold control layer 42 is located closer to the source electrode 32 than the end of the gate electrode 28. The threshold control layer 42 and the source electrode 32 are spaced apart and do not contact each other.

[0122] The threshold control layer 42 has a thickness of 100 nm and a carrier concentration of 1×10 １７ cm －３ p-type Al ０．２ Ga ０．８ The threshold control layer 42 is a nitride semiconductor layer made of N. The threshold control layer 42 is formed by depositing the undoped AlGaN film 23 that forms the electron supply layer 26 by MOVPE and then patterning it.

[0123] According to this modification, the potential of the conduction band edge of the channel portion is increased by the threshold control layer 42. This increases the threshold voltage of the nitride semiconductor device 110. This allows the nitride semiconductor device 110 to be realized as a normally-off type FET.

[0124] While nitride semiconductor devices according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0125] For example, in a plan view, the edge of the gate electrode 28 may coincide with the edge of the gate opening 22. Alternatively, in a plan view, the gate electrode 28 may be provided inside the gate opening 22.

[0126] Furthermore, for example, the planar shapes of the source electrodes 32 and the source openings 30 are not limited to hexagons, and may be rectangular shapes that are elongated in one direction (e.g., the y-axis direction). In this case, the multiple source electrodes 32 are arranged in a striped pattern in a planar view. The planar shapes of the portions of the gate electrodes 28 and the gate openings 22 located between adjacent source electrodes 32 are also elongated rectangular shapes, and are arranged in a striped pattern.

[0127] Furthermore, for example, in the above embodiment, the source opening 30 is provided so as to reach the first underlayer 16, but this is not limiting. For example, the source opening 30 may be an opening that reaches the electron transit layer 24, and the source electrode 32 may be connected to the electron transit layer 24 but not to the first underlayer 16.

[0128] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0129] The present disclosure can be used as a nitride semiconductor device with low on-resistance, and can be used, for example, in a power transistor used in a power supply circuit of a consumer device such as a television.

[0130] REFERENCE SIGNS LIST 10, 110 nitride semiconductor device 11 unit cell 12 substrate 12a first main surface 12b second main surface 13 n-type GaN film 14 drift layer 15 p-type GaN film 16 first underlayer 17, 21 undoped GaN film 18 second underlayer 19, 23 undoped AlGaN film 20 third underlayer 22 gate opening 22a, 30a bottom surface 22b, 30b sidewall surface 24 electron transit layer 24a bottom portion 24b outer edge portion 24c sidewall portion 26 electron supply layer 28 gate electrode 30 source opening 32 source electrode 34 drain electrode 36 gate electrode pad 38 source electrode pad 40 two-dimensional electron gas 42 threshold control layer 90 resist mask 91 opening

Claims

1. A substrate; a first nitride semiconductor layer provided above the substrate; a p-type second nitride semiconductor layer provided above the first nitride semiconductor layer; a third nitride semiconductor layer and a fourth nitride semiconductor layer provided in this order from the substrate side along an inner surface of a first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer, and outside the first opening and above the second nitride semiconductor layer; a gate electrode provided above the fourth nitride semiconductor layer; a source electrode provided apart from the gate electrode; a drain electrode provided on the substrate on the opposite side to the first nitride semiconductor layer, The third nitride semiconductor layer comprises: a bottom portion provided along a bottom surface of the first opening; an outer edge portion provided outside the first opening, a thickness of the bottom portion in a direction perpendicular to the main surface of the substrate is thinner than a thickness of the outer edge portion in a direction perpendicular to the main surface; Nitride semiconductor devices.

2. the third nitride semiconductor layer includes a sidewall portion provided along a sidewall surface of the first opening, a thickness of the sidewall portion in a direction parallel to the main surface is greater than a thickness of the outer edge portion in a direction perpendicular to the main surface; The nitride semiconductor device according to claim 1 .

3. a p-type fifth nitride semiconductor layer provided between the gate electrode and the fourth nitride semiconductor layer; 3. The nitride semiconductor device according to claim 1.

4. the source electrode is provided in a second opening that penetrates the fourth nitride semiconductor layer and the third nitride semiconductor layer at a position away from the gate electrode and reaches the second nitride semiconductor layer; 3. The nitride semiconductor device according to claim 1.

5. When the substrate is viewed from above, a distance between an edge of the gate electrode and the source electrode is shorter than a distance between an edge of the first opening and the source electrode.

3. The nitride semiconductor device according to claim 1.

6. forming a first nitride semiconductor layer and a p-type second nitride semiconductor layer in this order above a substrate; forming a first opening that penetrates the second nitride semiconductor layer and reaches the first nitride semiconductor layer; forming a third nitride semiconductor layer and a fourth nitride semiconductor layer in this order along an inner surface of the first opening, outside the first opening, and above the second nitride semiconductor layer; forming a gate electrode above the fourth nitride semiconductor layer; forming a source electrode at a location spaced from the gate electrode; forming a drain electrode on the substrate on the opposite side to the first nitride semiconductor layer; In forming the third nitride semiconductor layer, the third nitride semiconductor layer is formed by epitaxial growth under conditions that promote growth in a direction parallel to the main surface of the substrate more than in a direction perpendicular to the main surface of the substrate. A method for manufacturing a nitride semiconductor device.

7. The conditions include a film formation temperature of 1100°C or higher. The method for manufacturing a nitride semiconductor device according to claim 6 .

8. The conditions include a V / III ratio of the feedstock of 1000 or more. The method for manufacturing a nitride semiconductor device according to claim 6 or 7.