Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor chip that is formed from a single layer having a first main surface and a second main surface on the reverse side from the first main surface; a first semiconductor region of a first conductivity type formed on the first main surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second main surface side of the semiconductor chip in relation to the first semiconductor region; and a first trench structure including a first trench that penetrates the first semiconductor region from the first main surface and partitions the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view, a control insulation film that covers the inner wall of the first trench, and a control electrode that is embedded in the first trench with the control insulation film sandwiched therebetween and controls a channel in the second semiconductor region for causing conduction between the first region and the second region in a lateral direction along the first main surface.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application Nos. 2023-056606, 2023-056607, 2023-056608, 2023-056609, and 2023-056614, filed with the Japan Patent Office on March 30, 2023, the entire disclosures of which are incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including a semiconductor chip having a first main surface, an n-type drift layer formed on a surface layer portion of the first main surface, a trench gate structure formed on the first main surface so as to be in contact with the drift layer, a p-type channel region formed in the drift layer so as to cover a sidewall of the trench gate structure, and a first source / drain region and a second source / drain region formed at an interval in a region of the drift layer along the sidewall of the trench gate structure so as to face each other across the channel region.

[0004] International Publication No. 2021 / 065740

[0005] An embodiment of the present disclosure provides a semiconductor device that can achieve simplification of the manufacturing process.

[0006] One embodiment of the present disclosure provides an in-hand device including: a semiconductor chip consisting of a single layer having a first main surface and a second main surface opposite to the first main surface; a first semiconductor region of a first conductivity type formed on the first main surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second main surface side of the semiconductor chip relative to the first semiconductor region; a first trench extending from the first main surface through the first semiconductor region and partitioning the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view; a control insulating film covering an inner wall of the first trench; and a first trench structure including a control electrode embedded in the first trench across the control insulating film and controlling a channel in the second semiconductor region that connects the first region and the second region in a lateral direction along the first main surface.

[0007] According to an embodiment of the present disclosure, it is possible to provide a semiconductor device that can achieve simplification of the manufacturing process.

[0008] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a schematic perspective view of the semiconductor device according to the first embodiment of the present disclosure. FIG. 3 is a plan view of the semiconductor device of FIG. 2. FIG. 4 is a plan view showing the internal structure of the semiconductor device of FIG. 2. FIG. 5 is a plan view showing the internal structure of the semiconductor device of FIG. 2. FIG. 6 is a plan view showing the internal structure of the semiconductor device of FIG. 2. FIG. 7 is a plan view showing the internal structure of the semiconductor device of FIG. 2. FIG. 8 is an enlarged view of a portion surrounded by a two-dot chain line VIII in FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8. FIG. 13A is a diagram showing a part of a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. FIG. 13B is a diagram showing a process subsequent to that of FIG. 13A. FIG. 13C is a diagram showing a process subsequent to that of FIG. 13B. 13D is a diagram showing a step subsequent to that of FIG. 13C. FIG. 13E is a diagram showing a step subsequent to that of FIG. 13D. FIG. 13F is a diagram showing a step subsequent to that of FIG. 13E. FIG. 13G is a diagram showing a step subsequent to that of FIG. 13F. FIG. 13H is a diagram showing a step subsequent to that of FIG. 13G. FIG. 13I is a diagram showing a step subsequent to that of FIG. 13H. FIG. 13J is a diagram showing a step subsequent to that of FIG. 13I. FIG. 14 is a cross-sectional view showing a current path in the semiconductor device according to the first embodiment of the present disclosure. FIG. 15 is a plan view showing a current path in the semiconductor device according to the first embodiment of the present disclosure. FIG. 16 is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is a cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a schematic plan view showing the internal structure of the semiconductor device according to the second embodiment of the present disclosure. FIG. 20 is an enlarged view of a portion surrounded by a two-dot chain line XX in FIG. 19. Fig. 21 is an enlarged view of a portion surrounded by a two-dot chain line XX in Fig. 19. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 20. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 20. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 20. Fig. 25A is a view showing a part of a manufacturing process of a semiconductor device according to a second embodiment of the present disclosure.25B is a diagram illustrating a step subsequent to that of FIG. 25A. FIG. 25C is a diagram illustrating a step subsequent to that of FIG. 25B. FIG. 25D is a diagram illustrating a step subsequent to that of FIG. 25C. FIG. 25E is a diagram illustrating a step subsequent to that of FIG. 25D. FIG. 25F is a diagram illustrating a step subsequent to that of FIG. 25E. FIG. 25G is a diagram illustrating a step subsequent to that of FIG. 25F. FIG. 25H is a diagram illustrating a step subsequent to that of FIG. 25G. FIG. 25I is a diagram illustrating a step subsequent to that of FIG. 25H. FIG. 25J is a diagram illustrating a step subsequent to that of FIG. 25I. FIG. 26 is a cross-sectional view illustrating a current path of a semiconductor device according to a second embodiment of the present disclosure. FIG. 27 is a plan view illustrating a current path of a semiconductor device according to a second embodiment of the present disclosure. FIG. 28 is a diagram illustrating an effect of improving the breakdown voltage of the semiconductor device according to the second embodiment of the present disclosure. FIG. 29 is a diagram illustrating an effect of improving the breakdown voltage of the semiconductor device according to the second embodiment of the present disclosure. FIG. 30 is a diagram illustrating an effect of improving the breakdown voltage of the semiconductor device according to the second embodiment of the present disclosure. Fig. 31 is a diagram for explaining the effect of improving the breakdown voltage of the semiconductor device according to the second embodiment of the present disclosure. Fig. 32 is a diagram for explaining the effect of improving the breakdown voltage of the semiconductor device according to the second embodiment of the present disclosure. Fig. 33 is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment of the present disclosure. Fig. 34 is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment of the present disclosure. Fig. 35 is a cross-sectional view showing a third modified example of the semiconductor device according to the second embodiment of the present disclosure.

[0009] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0010] First Embodiment (1) Structure of Semiconductor Device 1A FIG. 1 is a circuit diagram of a semiconductor device 1A according to a first embodiment of the present disclosure.

[0011] The semiconductor device 1A includes a common source-drain type MISFET (Metal Insulator Semiconductor Field Effect Transistor) 2. The MISFET 2 includes a base B, a gate G, a first source-drain SD1, and a second source-drain SD2. The first source-drain SD1 and the second source-drain SD2 serve as both a source and a drain. For example, depending on the connection topology of the semiconductor device 1A, the first source-drain SD1 may be the source and the second source-drain SD2 may be the drain. Alternatively, the first source-drain SD1 may be the drain and the second source-drain SD2 may be the source.

[0012] A reference voltage (e.g., ground voltage) is applied to the base B. A gate voltage VG, which is referenced to the base B, is applied to the gate G. The gate G controls the conduction and blocking of a current I flowing between the first source-drain SD1 and the second source-drain SD2. A first source-drain voltage VSD1 (first voltage) is applied to the first source-drain SD1. A second source-drain voltage VSD2 (second voltage), which is different from the first source-drain voltage VSD1, is applied to the second source-drain SD2.

[0013] The semiconductor device 1A further includes a diode pair 3 connected to the first source-drain SD1 and the second source-drain SD2. The diode pair 3 regulates (cuts off) a current I flowing between the first source-drain SD1 and the second source-drain SD2 when the MISFET 2 is in an off state.

[0014] Specifically, the diode pair 3 includes a first body diode D1 and a second body diode D2 that are reverse-bias connected. The first body diode D1 and the second body diode D2 each include an anode and a cathode.

[0015] The anode of the first body diode D1 is connected to the base B. The cathode of the first body diode D1 is connected to the first source-drain SD1. The anode of the second body diode D2 is connected to the base B. The cathode of the second body diode D2 is connected to the second source-drain SD2.

[0016] The semiconductor device 1A is a four-terminal device including four external terminals 4, 5, 6, and 7. Specifically, the external terminals 4 to 7 include a base terminal 4, a gate terminal 5, a first source-drain terminal 6, and a second source-drain terminal 7. The base terminal 4 is connected to the base B. The gate terminal 5 is connected to the gate G. The first source-drain terminal 6 is connected to the first source-drain SD1. The second source-drain terminal 7 is connected to the second source-drain SD2.

[0017] The MISFET 2 is a bidirectional device that allows a current I to flow in both directions between the first source-drain terminal 6 and the second source-drain terminal 7. That is, when the first source-drain terminal 6 is connected to the high-voltage side (input side), the second source-drain terminal 7 is connected to the low-voltage side (output side). On the other hand, when the first source-drain terminal 6 is connected to the low-voltage side (output side), the second source-drain terminal 7 is connected to the high-voltage side (input side).

[0018] When a gate voltage VG (Vth≦VG) equal to or greater than the gate threshold voltage Vth is applied to the gate terminal 5, a current I flows between the first source-drain terminal 6 and the second source-drain terminal 7. When a gate voltage VG (VG<Vth) less than the gate threshold voltage Vth is applied to the gate terminal 5, no current I flows between the first source-drain terminal 6 and the second source-drain terminal 7. In this manner, the on / off of the MISFET 2 is controlled.

[0019] The semiconductor device 1A can realize, with one MISFET 2, the functionality of a circuit in which the drains of two MISFETs that are not of a common source-drain type are connected to each other. Therefore, the semiconductor device 1A can achieve a low on-resistance by shortening the current path. The specific structure of the semiconductor device 1A will be described below.

[0020] Fig. 2 is a schematic perspective view of a semiconductor device 1A according to a first embodiment of the present disclosure. Fig. 3 is a plan view of the semiconductor device 1A of Fig. 2. Below, an example will be described in which the semiconductor device 1A is formed of a chip-size package having a package size equal to the size of the chip.

[0021] 2 and 3, the semiconductor device 1A has a laminated structure including a semiconductor chip 8 and an insulating layer 9.

[0022] The semiconductor chip 8 is formed in a rectangular parallelepiped shape. The semiconductor chip 8 includes a first main surface 10 on one side, a second main surface 11 on the other side, and side surfaces 12A, 12B, 12C, and 12D connecting the first main surface 10 and the second main surface 11. The side surfaces 12A to 12D specifically include the first side surface 12A, the second side surface 12B, the third side surface 12C, and the fourth side surface 12D.

[0023] The insulating layer 9 is formed on the first main surface 10. The insulating layer 9 includes an insulating main surface 13 and insulating side surfaces 14A, 14B, 14C, and 14D. Specifically, the insulating side surfaces 14A to 14D include a first insulating side surface 14A, a second insulating side surface 14B, a third insulating side surface 14C, and a fourth insulating side surface 14D. The insulating side surfaces 14A to 14D extend from the periphery of the insulating main surface 13 toward the semiconductor chip 8 and are continuous with the side surfaces 12A to 12D. Specifically, the insulating side surfaces 14A to 14D are formed flush with the side surfaces 12A to 12D.

[0024] The plurality of external terminals 4 to 7 are formed on the insulating main surface 13. In this embodiment, the plurality of external terminals 4 to 7 are arranged in a matrix of 5 rows and 5 columns at intervals in the first direction X and the second direction Y.

[0025] The base terminal 4 is arranged in the third row and the first column. The gate terminal 5 is arranged in the third row and the fifth column. The gate terminal 5 faces the base terminal 4 in the first direction X. The plurality of first source-drain terminals 6 are arranged in the first to fifth columns of the first row and the first to fifth columns of the fourth row. The plurality of second source-drain terminals 7 are arranged in the first to fifth columns of the second row and the first to fifth columns of the fifth row.

[0026] The second source-drain terminals 7 arranged in the second row face the first source-drain terminals 6 arranged in the first row in a one-to-one correspondence in the second direction Y. The second source-drain terminals 7 arranged in the fifth row face the first source-drain terminals 6 arranged in the fourth row in a one-to-one correspondence in the second direction Y.

[0027] In this embodiment, spaces are provided in the second, third, and fourth columns of the third row. Any one of the base terminal 4, gate terminal 5, first source / drain terminal 6, and second source / drain terminal 7 may be disposed in each space. An electrically open terminal may be disposed in each space. The number and arrangement of the base terminals 4, gate terminals 5, first source / drain terminals 6, and second source / drain terminals 7 are arbitrary and are not limited to the number and arrangement shown in FIGS. 2 and 3 .

[0028] Figures 4 to 7 are plan views showing the internal structure of the semiconductor device 1A of Figure 2. Figure 4 shows the planar structure of the semiconductor chip 8, and Figures 5 to 7 show the wiring pattern inside the insulating layer 9.

[0029] 4 to 7, an active region 15 and a peripheral region 16 surrounding the active region 15 are defined on a first main surface 10 of the semiconductor chip 8. As shown in FIG.

[0030] The outer peripheral region 16 may coincide with the annular peripheral portion along the side surfaces 12A to 12D of the semiconductor chip 8. The outer peripheral region 16 may be an annular region extending from the side surfaces 12A to 12D of the semiconductor chip 8 to a position approximately several μm inward. The active region 15 may be a central region of the semiconductor chip 8 surrounded by the outer peripheral region 16. The active region 15 may be, for example, a region in which most of the element structure of the MISFET 2 is formed.

[0031] 4, an element structure of a MISFET 2 is formed in the active region 15. In this embodiment, the element structure is a trench gate lateral type MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure.

[0032] The MISFET 2 includes a first trench structure 17 and a trench connection structure 18 as trench structures formed in the first main surface 10 .

[0033] The first trench structure 17 may also be referred to as a "trench gate structure." The multiple first trench structures 17 are each formed in an inner portion of the first main surface 10 at intervals from the periphery of the first main surface 10. The multiple first trench structures 17 are arranged at intervals in the first direction X and each formed in a band shape extending in the second direction Y. The multiple first trench structures 17 are formed in a stripe shape extending in the second direction Y in a plan view. Each of the multiple first trench structures 17 has a first end on one side and a second end on the other side in the second direction Y.

[0034] The trench connection structure 18 is connected to the first trench structure 17. The multiple (two in this embodiment) trench connection structures 18 include a trench connection structure 18 on one side (the third side surface 12C side) connecting first ends of the multiple first trench structures 17, and a trench connection structure 18 on the other side (the fourth side surface 12D side) connecting second ends of the multiple first trench structures 17.

[0035] The trench connection structure 18 is formed in an inner portion of the first main surface 10 at a distance from the periphery of the first main surface 10. The trench connection structure 18 is formed in a strip shape extending in a direction (specifically, the first direction X) intersecting the direction in which the plurality of first trench structures 17 extend, and is connected to first ends and second ends of the plurality of first trench structures 17. As a result, a plurality of closed regions surrounded by pairs of first trench structures 17 and pairs of trench connection structures 18 are formed on the first main surface 10.

[0036] Each of the multiple closed regions 19-21 is sandwiched between first trench structures 17 in the first direction X and is formed in a strip shape extending in the second direction Y. The multiple closed regions 19-21 are arranged in the first direction X with the first trench structures 17 separating them, and are formed in a stripe shape as a whole. The multiple closed regions 19-21 may include a first source / drain region 19, a second source / drain region 20, and a drift region 21.

[0037] In this embodiment, the first source / drain region 19 and the second source / drain region 20 face each other across the drift region 21. A first trench structure 17 is formed between the first source / drain region 19 and the drift region 21, and between the drift region 21 and the second source / drain region 20, to separate them.

[0038] The plurality of first source / drain regions 19 and the plurality of second source / drain regions 20 are alternately arranged at intervals in the first direction X so that the drift region 21 is sandwiched between adjacent first source / drain regions 19 and second source / drain regions 20. In Fig. 4, from the left side of the page, a set of the first source / drain region 19, the drift region 21, the second source / drain region 20, and the drift region 21 is repeatedly arranged in the first direction X.

[0039] A first contact region 22 is formed in the first source / drain region 19. The first contact region 22 may also be referred to as a "first source / drain contact region." In this embodiment, a strip-shaped first contact region 22 extending in the second direction Y is formed in an inner region of each first source / drain region 19. The first contact region 22 has an annular outer periphery in a portion spaced inward from the first trench structure 17 and the trench connection structure 18.

[0040] A first lower contact 23 is formed in the first contact region 22. The first lower contact 23 may also be referred to as a "first source-drain contact." In this embodiment, a plurality of first lower contacts 23 are formed at intervals in the second direction Y. Each first lower contact 23 is formed in a rectangular shape in plan view that is long along the second direction Y. Only one first lower contact 23 may be formed in each first contact region 22.

[0041] A second contact region 24 is formed in the second source / drain region 20. The second contact region 24 may also be referred to as a "second source / drain contact region." In this embodiment, a strip-shaped second contact region 24 extending in the second direction Y is formed in an inner region of each second source / drain region 20. The second contact region 24 has an annular outer periphery at a portion spaced inward from the first trench structure 17 and the trench connection structure 18.

[0042] A second lower contact 25 is formed in the second contact region 24. The second lower contact 25 may also be referred to as a "second source-drain contact." In this embodiment, a plurality of second lower contacts 25 are formed at intervals in the second direction Y. Each second lower contact 25 is formed in a rectangular shape in plan view that is long along the second direction Y. Only one second lower contact 25 may be formed in each second contact region 24.

[0043] A first base contact 26 is formed in the drift region 21. In this embodiment, a plurality of first base contacts 26 are formed at intervals in the second direction Y. Each first base contact 26 is formed in a rectangular shape in plan view that is long along the second direction Y. Only one first base contact 26 may be formed in each drift region 21.

[0044] In this embodiment, the first lower contact 23, the second lower contact 25, and the first base contact 26 are electrically isolated from one another and fixed to different potentials. The first lower contacts 23, the second lower contacts 25, and the first base contacts 26 are discretely arranged on the first main surface 10. In this embodiment, the first lower contacts 23, the second lower contacts 25, and the first base contacts 26 are arranged with a regularity such that contacts of the same type (same potential) are aligned in the first direction X.

[0045] 4, from the top of the page, a row of multiple first lower contacts 23 aligned in the first direction X, a row of multiple first base contacts 26 aligned in the first direction X, and a row of multiple second lower contacts 25 aligned in the first direction X are formed in this order. As a result, the multiple first lower contacts 23, the multiple second lower contacts 25, and the multiple first base contacts 26 do not face contacts of different types in the first direction X.

[0046] A first gate contact 27 is formed in the trench connection structure 18. In this embodiment, the plurality of first gate contacts 27 are arranged at intervals in the first direction X. The plurality of first gate contacts 27 may include a first gate contact 27 arranged at an intersection of the trench connection structure 18 and the first trench structure 17. The plurality of first gate contacts 27 may be arranged at a position facing at least one of the first source / drain region 19, the second source / drain region 20, and the drift region 21 in the second direction Y.

[0047] 5 to 7, a plurality of wiring layers are formed on the first main surface 10 of the semiconductor chip 8, and the above-mentioned plurality of external terminals are connected to the uppermost layer of the plurality of wiring layers. The plurality of wiring layers form a multilayer wiring structure, and include, for example, a first wiring layer 28 shown by a solid line in Fig. 5 and a second wiring layer 29 shown by a solid line in Fig. 6, in this order from the first main surface 10 upward. In this embodiment, the external terminals are connected to the second wiring layer 29, as shown in Fig. 7.

[0048] The first wiring layer 28 may be referred to as a "first metal." Referring to FIG. 5 , the first wiring layer 28 includes a first gate wiring layer 30, a first lower wiring layer 31, a second lower wiring layer 32, and a first base wiring layer 33. The first gate wiring layer 30, the first lower wiring layer 31, the second lower wiring layer 32, and the first base wiring layer 33 are wiring layers that are physically independent from one another. The first lower wiring layer 31 may be referred to as a "first lower source / drain wiring layer." The second lower wiring layer 32 may be referred to as a "second lower source / drain wiring layer."

[0049] The first gate wiring layer 30 is formed along the peripheral region 16 of the semiconductor chip 8. The first gate wiring layer 30 has a shape that surrounds the active region 15. For example, the first gate wiring layer 30 surrounds the active region 15 on three sides and has a shape that is open on one side (the first side 12A in FIG. 5 ) of the side faces 12A to 12D of the semiconductor chip 8. The first gate wiring layer 30 is formed by three straight line portions that extend along the peripheral region 16. Of the three straight line portions, a pair of straight line portions that face each other in the second direction Y cover and are connected to the plurality of first gate contacts 27.

[0050] The first lower wiring layer 31 is formed to cover the first lower contacts 23 and is connected to the first lower contacts 23. In this embodiment, the first lower wiring layer 31 is formed in a strip shape extending in the first direction X so as to collectively cover the plurality of first lower contacts 23 that are aligned linearly in the first direction X.

[0051] The second lower wiring layer 32 is formed to cover the second lower contacts 25 and is connected to the second lower contacts 25. In this embodiment, the second lower wiring layer 32 is formed in a strip shape extending in the first direction X so as to collectively cover the plurality of second lower contacts 25 that are aligned linearly in the first direction X.

[0052] The plurality of first lower wiring layers 31 and the plurality of second lower wiring layers 32 are alternately arranged at intervals in the second direction Y. In this embodiment, two strip-shaped first lower wiring layers 31 and two strip-shaped second lower wiring layers 32 are formed in a stripe shape at intervals from each other.

[0053] The first base wiring layer 33 is formed to cover the first base contacts 26 and is connected to the first base contacts 26. In this embodiment, the first base wiring layer 33 is formed in a strip shape extending in the first direction X so as to collectively cover the plurality of first base contacts 26 that are linearly aligned in the first direction X. In this embodiment, the strip-shaped first base wiring layer 33 is disposed one by one in the region between the first lower wiring layer 31 and the second lower wiring layer 32. All of the first base wiring layers 33 are connected collectively on the open side (the side of the first side surface 12A) of the first gate wiring layer 30.

[0054] The second wiring layer 29 may be referred to as a "second metal." Referring to FIG. 6 , the second wiring layer 29 includes a second gate wiring layer 34, a first upper wiring layer 35, a second upper wiring layer 36, and a second base wiring layer 37. The second gate wiring layer 34, the first upper wiring layer 35, the second upper wiring layer 36, and the second base wiring layer 37 are wiring layers that are physically independent from one another. The first upper wiring layer 35 may be referred to as a "first upper source-drain wiring layer." The second upper wiring layer 36 may be referred to as a "second upper source-drain wiring layer." In FIG. 6 , the first wiring layer 28 is indicated by a dashed line to clarify the relationship between the second wiring layer 29 and the first wiring layer 28.

[0055] The second gate wiring layer 34 and the second base wiring layer 37 are each formed in a rectangular shape in a plan view. The second gate wiring layer 34 and the second base wiring layer 37 are formed in positions facing each other in the first direction X in the center of the semiconductor chip 8 in the second direction Y. In this embodiment, the second gate wiring layer 34 is arranged near the first side surface 12A of the side surfaces 12A to 12D of the semiconductor chip 8, and the second base wiring layer 37 is arranged near the opposite second side surface 12B. The second gate wiring layer 34 is connected to the first gate wiring layer 30 via a second gate contact 38. The second base wiring layer 37 is connected to the first base wiring layer 33 via a second base contact 39.

[0056] The first upper wiring layer 35 is formed in a strip shape extending along the first lower wiring layer 31, and covers the first lower wiring layer 31. The first upper wiring layer 35 is connected to the first lower wiring layer 31 via a first upper contact 40. A plurality of first upper contacts 40 may be formed and arranged at intervals in the first direction X.

[0057] The second upper wiring layer 36 is formed in a strip shape extending along the second lower wiring layer 32, and covers the second lower wiring layer 32. The second upper wiring layer 36 is connected to the second lower wiring layer 32 via second upper contacts 41. A plurality of second upper contacts 41 may be formed and arranged at intervals in the first direction X.

[0058] 7, the plurality of external terminals are arranged on corresponding second wiring layers 29. In Fig. 7, the second wiring layers 29 are shown by dashed lines to clarify the relationship between the plurality of external terminals and the second wiring layers 29.

[0059] The gate terminal 5 is provided on the second gate wiring layer 34 and connected to the second gate wiring layer 34 via a gate terminal contact 42. The base terminal 4 is provided on the second base wiring layer 37 and connected to the second base wiring layer 37 via a base terminal contact 43.

[0060] The plurality of first source-drain terminals 6 are arranged at intervals in the longitudinal direction of the strip-shaped first upper wiring layer 35. Each of the first source-drain terminals 6 is connected to the first upper wiring layer 35 via a first terminal contact 44.

[0061] The second source-drain terminals 7 are arranged at intervals in the longitudinal direction of the strip-shaped second upper wiring layer 36. Each second source-drain terminal 7 is connected to the second upper wiring layer 36 via a second terminal contact 45.

[0062] Fig. 8 is an enlarged view of the portion surrounded by the two-dot chain line VIII in Fig. 4. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 8. Fig. 10 is a cross-sectional view taken along line XX in Fig. 8. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 8. Fig. 12 is a cross-sectional view taken along line XII-XII in Fig. 8.

[0063] 9 to 12, the semiconductor device 1A includes a semiconductor chip 8. The semiconductor chip 8 is a semiconductor chip 8 consisting of a single layer. The semiconductor chip 8 consisting of a single layer has a single structure of a semiconductor substrate without an epitaxial layer. In this embodiment, the semiconductor chip 8 includes a single crystal of Si (silicon) or a wide bandgap semiconductor without an epitaxial layer. A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si. The semiconductor chip 8 may be a Si chip or a SiC (silicon carbide) chip.

[0064] The semiconductor device 1A includes an n-type (first conductivity type) first semiconductor region 46 formed in a region on the first main surface 10 side in the semiconductor chip 8. The first semiconductor region 46 may also be referred to as a "drift layer." The first semiconductor region 46 is formed in the semiconductor chip 8 at an interval from the second main surface 11 toward the first main surface 10. The first semiconductor region 46 is formed in a layer shape extending along the first main surface 10 in a surface layer portion of the first main surface 10, and is exposed from the entire first main surface 10 and from portions of the first to fourth side surfaces 12A to 12D.

[0065] Of course, the first semiconductor region 46 may be formed in the inner part of the first main surface 10 at intervals from the first to fourth side surfaces 12A to 12D in a plan view. １４ cm －３ 1x10 or more １８ cm －３ The first semiconductor region 46 may have a thickness of 0.1 μm or more and 10 μm or less (preferably 0.5 μm or more and 2 μm or less).

[0066] The semiconductor device 1A includes a p-type (second conductivity type) second semiconductor region 47 formed in a region of the semiconductor chip 8 closer to the second main surface 11 than the first semiconductor region 46. The second semiconductor region 47 may also be referred to as a "base layer." The second semiconductor region 47 has a 1×10 １３ cm －３ 1x10 or more １６ cm －３ More specifically, the p-type impurity concentration of the second semiconductor region 47 over the entire area from the second main surface 11 to the first semiconductor region 46 in the thickness direction of the semiconductor chip 8 may be 1×10 １３ cm －３ 1x10 or more １６ cm －３ The following is the result.

[0067] The reason why the p-type impurity concentration of the second semiconductor region 47 is almost constant in the thickness direction of the semiconductor chip 8 is that the semiconductor chip 8 is composed of a single-structure semiconductor substrate without an epitaxial layer. Normally, when an epitaxial layer is grown on a semiconductor substrate (base substrate), the impurity concentration of the epitaxial layer is made relatively low to ensure a high breakdown voltage, even if the epitaxial layer has the same conductivity type as the base substrate. On the other hand, the impurity concentration of the base substrate is made high to reduce the ohmic resistance of the back electrode formed on the second main surface 11.

[0068] In this embodiment, the MISFET 2 is a lateral type, and the current path 97 (see FIGS. 14 and 15 ) extends only laterally along the first main surface 10, so that no current flows in the thickness direction of the second semiconductor region 47. Therefore, even if the p-type impurity concentration of the second semiconductor region 47 is low throughout, there is little concern that the on-resistance will increase. For example, the resistance value of the second semiconductor region 47 may be 10 Ω·cm or more and 100 Ω·cm or less throughout the entire thickness direction of the semiconductor chip 8, from the second main surface 11 to the boundary 60 between the first semiconductor region 46 and the second semiconductor region 47.

[0069] The second semiconductor region 47 is formed in a layer shape extending along the first main surface 10 (first semiconductor region 46) within the semiconductor chip 8, and is exposed from a portion of the first to fourth side surfaces 12A to 12D. The second semiconductor region 47 is electrically connected to the first semiconductor region 46 within the semiconductor chip 8. Specifically, the second semiconductor region 47 forms a pn junction with the first semiconductor region 46. The second semiconductor region 47 may have a thickness of 0.5 μm or more and 755 μm or less.

[0070] The plurality of first trench structures 17 penetrate the first semiconductor region 46 to reach the second semiconductor region 47. In this form, the plurality of first trench structures 17 each have a bottom wall located within the second semiconductor region 47. The plurality of first trench structures 17 are configured to respectively control inversion and non-inversion of a channel (a channel 96 described below) in the second semiconductor region 47.

[0071] The plurality of first trench structures 17 may be arranged at intervals (pitch) of 0.02 μm or more and 20 μm or less (preferably 0.2 μm or more and 5 μm or less). The plurality of first trench structures 17 are preferably arranged at approximately equal intervals in the first direction X. Each of the plurality of first trench structures 17 may have a width in the first direction X of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.5 μm or less). Each of the plurality of first trench structures 17 may have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less).

[0072] The following describes the internal structure of one first trench structure 17. The first trench structure 17 includes a first trench 48, a gate insulating film 49 (control insulating film), a gate electrode 50 (control electrode), and a buried insulator 51.

[0073] The first trench 48 may also be referred to as a “gate trench.” The first trench 48 is formed in the first main surface 10 and defines the wall surfaces (side walls and bottom wall) of the first trench structure 17. The first trench 48 exposes the first semiconductor region 46 and the second semiconductor region 47 from the wall surfaces.

[0074] The first trench 48 may be formed in a tapered shape in which the opening width narrows from the first main surface 10 side toward the bottom wall side in a cross-sectional view. Of course, the first trench 48 may be formed perpendicular to the first main surface 10. The corners on the bottom wall side of the first trench 48 may be formed in a curved shape. Of course, the entire bottom wall of the first trench 48 may be formed in a curved shape toward the second main surface 11 side.

[0075] The gate insulating film 49 coats the sidewalls and bottom wall of the first trench 48 in a film-like manner. In this embodiment, the gate insulating film 49 coats the sidewalls and bottom wall of the first trench 48 on the bottom wall side and defines a recess space on the bottom wall side of the first trench 48. The gate insulating film 49 may have a thickness of 5 nm to 1000 nm in the normal direction to the wall surface of the first trench 48. The gate insulating film 49 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The gate insulating film 49 is preferably made of a silicon oxide film. It is particularly preferable that the gate insulating film 49 be made of an oxide (thermal oxide film) of the semiconductor chip 8.

[0076] The gate electrode 50 is embedded in the first trench 48 with a gate insulating film 49 sandwiched therebetween. Specifically, the gate electrode 50 is embedded in a recess space defined by the gate insulating film 49 on the bottom wall side of the first trench 48, and faces the second semiconductor region 47 with the gate insulating film 49 sandwiched therebetween. The gate electrode 50 crosses the depth position of a boundary portion 60 between the first semiconductor region 46 and the second semiconductor region 47 in the depth direction of the first trench 48.

[0077] 8 and 12 , the gate electrode 50 includes a plurality of lead-out portions 52 that are led from the bottom wall side of the first trench 48 to the opening side. The number of the lead-out portions 52 is arbitrary. In this embodiment, the plurality of lead-out portions 52 includes a pair of lead-out portions 52 that are spaced apart in the second direction Y. In this embodiment, the pair of lead-out portions 52 are formed at both ends of the first trench 48, respectively. The plurality of lead-out portions 52 each extend in the second direction Y in a plan view.

[0078] The multiple lead-out portions 52 define an opening-side recess from the wall surface of the first trench 48 on the opening side of the first trench 48. The opening-side recess is defined in a strip shape extending in the second direction Y in a plan view. The multiple lead-out portions 52 may protrude above the first main surface 10. The multiple lead-out portions 52 may be led out from the first trench 48 onto the first main surface 10 with part of the gate insulating film 49 sandwiched between them. Of course, the multiple lead-out portions 52 may be located on the bottom wall side of the first trench 48 with respect to the first main surface 10.

[0079] The gate electrode 50 may include at least one of a metal and a non-metal conductor. The gate electrode 50 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The gate electrode 50 preferably includes a non-metal conductor (conductive polysilicon). The conductive polysilicon may be p-type polysilicon or n-type polysilicon. The conductive polysilicon is preferably n-type polysilicon.

[0080] The buried insulator 51 is buried on the opening side of the first trench 48 so as to cover the gate electrode 50 within the first trench 48. Specifically, the buried insulator 51 is buried in a recess on the opening side defined by the gate electrode 50. The buried insulator 51 is provided as a field insulator that relieves the electric field with respect to the first trench 48. The buried insulator 51 is configured so that the area facing the first semiconductor region 46 exceeds the area facing the gate electrode 50 with respect to the second semiconductor region 47.

[0081] The buried insulator 51 has a thickness greater than the thickness of the gate electrode 50 in the depth direction of the first trench 48. The buried insulator 51 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The buried insulator 51 is preferably made of a silicon oxide film. The buried insulator 51 is preferably made of the same material as the gate insulating film 49. In this case, the buried insulator 51 is preferably made of an insulating vapor-deposited film and has a density different from that of the gate insulating film 49.

[0082] 8 to 11 , the semiconductor device 1A includes a plurality of mesas 53 to 55 defined on the first main surface 10 (first semiconductor region 46) by a plurality of first trench structures 17. The plurality of mesas 53 to 55 are defined in strip shapes extending in the second direction Y in regions between pairs of adjacent first trench structures 17. The plurality of mesas 53 to 55 include a plurality of first mesas 53, a plurality of second mesas 54, and a plurality of drift mesas 55.

[0083] The first mesa 53 and the second mesa 54 are arranged at an interval in the first direction X so as to sandwich one drift mesa 55. The first mesa 53 forms a first source / drain region 19 and may be referred to as a "first source / drain mesa." The second mesa 54 forms a second source / drain region 20 and may be referred to as a "second source / drain mesa." The drift mesa 55 forms a drift region 21.

[0084] 8 and 12, the plurality of trench connection structures 18 penetrate the first semiconductor region 46 to reach the second semiconductor region 47. In other words, the trench connection structure 18, together with the plurality of first trench structures 17, defines a plurality of mesas 53 to 55 (a plurality of first mesas 53, a plurality of second mesas 54, and a plurality of drift mesas 55).

[0085] The trench connection structure 18 may have a width in the second direction Y of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 2 μm or less). The trench connection structure 18 may have a width approximately equal to the width of the first trench structure 17. The trench connection structures 18 may each have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less). The trench connection structure 18 may have a depth approximately equal to the depth of the first trench structure 17.

[0086] The trench connection structure 18 includes a connection trench 56, a connection insulating film 57, and a connection electrode 58. The connection trench 56 is formed in the first main surface 10 so as to communicate with the plurality of first trenches 48, and defines the wall surfaces (side walls and bottom wall) of the trench connection structure 18. The wall surfaces (side walls and bottom wall) of the trench connection structure 18 are continuous with the wall surfaces (side walls and bottom wall) of the plurality of first trenches 48. The connection trench 56 exposes the first semiconductor region 46 and the second semiconductor region 47 from the wall surfaces.

[0087] The connection trench 56 may be formed in a tapered shape in which the opening width narrows from the first main surface 10 side toward the bottom wall side in a cross-sectional view. Of course, the connection trench 56 may be formed perpendicular to the first main surface 10. The corners on the bottom wall side of the connection trench 56 may be formed in a curved shape. Of course, the entire bottom wall of the connection trench 56 may be formed in a curved shape toward the second main surface 11 side.

[0088] The connection insulating film 57 coats the sidewalls and bottom wall of the connection trench 56 in a film-like manner. In this embodiment, the connection insulating film 57 coats the sidewalls and bottom wall on the opening side and bottom wall side of the connection trench 56, and defines a recess space within the connection trench 56. The connection insulating film 57 is continuous with the plurality of gate insulating films 49 at the communicating portions with the plurality of first trenches 48.

[0089] The connection insulating film 57 may have a thickness of 5 nm or more and 1000 nm or less. The connection insulating film 57 preferably has a thickness substantially equal to that of the gate insulating film 49. The connection insulating film 57 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The connection insulating film 57 is preferably made of the same material as the gate insulating layer.

[0090] The connection electrode 58 is embedded in the connection trench 56 with the connection insulating film 57 interposed therebetween, and faces the first semiconductor region 46 and the second semiconductor region 47. The connection electrode 58 is connected to the plurality of gate electrodes 50 at the communicating portions with the plurality of first trenches 48. Specifically, the connection electrode 58 is connected to the plurality of lead-out portions 52. As a result, the connection electrode 58 is fixed to the same potential as the gate electrodes 50.

[0091] The portion of the connection electrode 58 that is continuous with the lead-out portion 52 may be included in the components of the connection electrode 58, or may be included in the components of the gate electrode 50. The connection electrode 58 has an upper end that is located on the first main surface 10 side with respect to the upper end of the gate electrode 50. The connection electrode 58 may protrude above the first main surface 10. The connection electrode 58 may be drawn out from the connection trench 56 onto the first main surface 10 with part of the connection insulating film 57 sandwiched therebetween. Of course, the connection electrode 58 may be located on the bottom wall side of the connection trench 56 with respect to the first main surface 10.

[0092] The connection electrode 58 may include at least one of a metal and a non-metal conductor. The connection electrode 58 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The connection electrode 58 is preferably made of the same material as the gate electrode 50.

[0093] In the plurality of first mesas 53, the first source / drain regions 19 are formed by the first semiconductor regions 46. The first contact regions 22 are formed in the surface layer portions of the first source / drain regions 19. The first contact regions 22 have a higher n-type impurity concentration than the first semiconductor regions 46. The n-type impurity concentration of the first contact regions 22 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ or less (in this form, 1 × 10 １９ cm －３ (degree).

[0094] The first contact region 22 is preferably formed in the center of the corresponding first mesa portion 53 in plan view. The first contact region 22 has a length in the second direction Y that is less than the length of the first trench structure 17, and is formed at a distance inward from both ends of the first trench structure 17. Both ends of the first contact region 22 face the trench connection structure 18 in the second direction Y, with part of the first semiconductor region 46 interposed therebetween.

[0095] The first contact region 22 extends in the lateral direction (second direction Y) along the first major surface 10 in a cross-sectional view. Specifically, the first contact region 22 is formed at a depth position closer to the first major surface 10 than the upper end of the gate electrode 50. The first contact region 22 faces the buried insulator 51 in the lateral direction along the first major surface 10, with a part of the first semiconductor region 46 sandwiched between them. The first contact region 22 is spaced from the upper end of the gate electrode 50 toward the first major surface 10, and does not face the gate electrode 50 in the lateral direction along the first major surface 10. This reduces the electric field applied to the multiple first trench structures 17.

[0096] The first contact region 22 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The first contact region 22 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 50 in the thickness direction (normal direction Z) of the semiconductor chip 8.

[0097] In the multiple second mesas 54, the second source / drain regions 20 are formed by the first semiconductor regions 46. The second contact regions 24 are formed in the surface layer portions of the second source / drain regions 20. The second contact regions 24 have a higher n-type impurity concentration than the first semiconductor regions 46. The n-type impurity concentration of the second contact regions 24 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ or less (in this form, 1 × 10 １９ cm －３ (degree).

[0098] The second contact region 24 is preferably formed in the center of the corresponding second mesa portion 54 in plan view. The second contact region 24 has a length in the second direction Y that is less than the length of the first trench structure 17, and is formed at a distance inward from both ends of the first trench structure 17. Both ends of the second contact region 24 face the trench connection structure 18 in the second direction Y, with part of the first semiconductor region 46 interposed therebetween.

[0099] The second contact region 24 extends in the lateral direction (second direction Y) along the first major surface 10 in a cross-sectional view. Specifically, the second contact region 24 is formed at a depth position closer to the first major surface 10 than the upper end of the gate electrode 50. The second contact region 24 faces the buried insulator 51 in the lateral direction along the first major surface 10, with a part of the first semiconductor region 46 sandwiched between them. The second contact region 24 is spaced from the upper end of the gate electrode 50 toward the first major surface 10, and does not face the gate electrode 50 in the lateral direction along the first major surface 10. This reduces the electric field applied to the plurality of first trench structures 17.

[0100] The second contact region 24 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The second contact region 24 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 50 in the thickness direction (normal direction Z) of the semiconductor chip 8.

[0101] 8 and 11 , p-type protrusions 59 are formed in the plurality of drift mesas 55, selectively protruding from the second semiconductor region 47 toward the first major surface 10 into the first semiconductor region 46. Referring to FIG. 11 , the protrusions 59 may extend upward in a parabolic shape from a boundary 60 between the first semiconductor region 46 and the second semiconductor region 47 and have an apex in the vicinity of the first major surface 10. In this embodiment, the protrusions 59 have an apex at a position away from the first major surface 10 toward the second major surface 11. Parts of the drift region 21 may be formed on both sides of the protrusions 59 in the first direction X. The portions of the drift region 21 are sandwiched between the protrusions 59 and the first trench structure 17.

[0102] 8 , the protrusions 59 are selectively formed on the drift mesa 55 in the second direction Y. In this embodiment, the protrusions 59 are arranged at intervals along the second direction Y. Each protrusion 59 is formed across the first trench structure 17 on one side and the first trench structure 17 on the other side in the first direction X. As a result, the drift region 21 is divided by the protrusions 59 at multiple locations along the second direction Y.

[0103] The protruding portion 59 has a higher p-type impurity concentration than the second semiconductor region 47. The p-type impurity concentration of the protruding portion 59 is 1×10 １６ cm －３ 1x10 or more ２２ cm －３ or less (in this form, 1 × 10 １９ cm －３ (degree).

[0104] 8 , the multiple protrusions 59 divide the drift region 21 in the second direction Y into multiple contact regions 61 and multiple current regions 62. Each contact region 61 is a region in which a protrusion 59 is formed in a plan view. Each current region 62 is a region in which no protrusion 59 is formed in a plan view and which is formed by the first semiconductor region 46 (drift region 21) from the boundary portion 60 to the first main surface 10.

[0105] In the second direction Y, the contact region 61 may be shorter than the current region 62. For example, the length of the contact region 61 in the second direction Y may be 0.1 μm or more and 100 μm or less, and the length of the current region 62 in the second direction Y may be 1 μm or more and 3000 μm or less.

[0106] First impurity regions 63 are further formed in the plurality of drift mesas 55. The first impurity regions 63 are omitted in FIG. 8 . The first impurity regions 63 are selectively formed in the contact region 61 out of the contact region 61 and the current region 62. The first impurity regions 63 are formed in the surface layer portion of the first main surface 10, in contact with the tops of the protrusions 59. The first impurity regions 63 have a higher n-type impurity concentration than the first semiconductor region 46. The n-type impurity concentration of the first impurity regions 63 is 1×10 １５ cm －３ 1x10 or more ２０ cm －３ or less (in this form, 1 × 10 １８ cm －３ (degree).

[0107] The semiconductor device 1A includes a main surface insulating film 64 that selectively covers the first main surface 10. The main surface insulating film 64 may be part of the insulating layer 9 described above. The main surface insulating film 64 covers the first trench structures 17 and the trench connection structures 18 on the first main surface 10. In this embodiment, the main surface insulating film 64 covers the entire first main surface 10 and is continuous with the first to fourth side surfaces 12A to 12D.

[0108] The main surface insulating film 64 may have a thickness of 0.1 μm or more and 2 μm or less. The thickness of the main surface insulating film 64 preferably exceeds the thickness of the gate insulating film 49. The main surface insulating film 64 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The main surface insulating film 64 is preferably made of a silicon oxide film.

[0109] In this embodiment, the main surface insulating film 64 is made of the same material as the buried insulator 51 and is formed integrally with the buried insulator 51. That is, the main surface insulating film 64 extends from above the first main surface 10 into the plurality of first trenches 48 as part of the buried insulator 51. In other words, the main surface insulating film 64 is made of an insulating film in which the portions of the plurality of buried insulators 51 that protrude from the plurality of first trenches 48 are integrated into a film shape on the first main surface 10.

[0110] 8 and 9 , the semiconductor device 1A includes a plurality of first electrodes 65 electrically connected to the first semiconductor region 46 in the plurality of first mesas 53. In this embodiment, the plurality of first electrodes 65 are provided as "first lower contacts 23." The plurality of first electrodes 65 penetrate the main surface insulating film 64 and are connected to the plurality of first mesas 53, respectively. Specifically, the plurality of first electrodes 65 are respectively arranged in a plurality of first connection openings 66 formed in the main surface insulating film 64.

[0111] Each of the multiple first electrodes 65 is made of metal. In this embodiment, each of the multiple first electrodes 65 has a layered structure including a first barrier film 67 and a first electrode body 68. The first barrier film 67 is formed in a film shape along the inner wall of the first connection opening 66. The first barrier film 67 may be made of a titanium-based metal film. The first barrier film 67 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film.

[0112] The first electrode body 68 is embedded in the first connection opening 66 with the first barrier film 67 sandwiched therebetween, and is electrically connected to the first mesa portion 53 (first contact region 22) with the first barrier film 67 sandwiched therebetween. The first electrode body 68 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the first electrode body 68 contains tungsten. Of course, the multiple first electrodes 65 may be formed only by the first electrode body 68 without the first barrier film 67.

[0113] 8 and 10 , the semiconductor device 1A includes a plurality of second electrodes 69 electrically connected to the first semiconductor region 46 in the plurality of second mesas 54. In this embodiment, the plurality of second electrodes 69 are provided as "second lower contacts 25." The plurality of second electrodes 69 penetrate the main surface insulating film 64 and are connected to the plurality of second mesas 54, respectively. Specifically, the plurality of second electrodes 69 are respectively arranged in a plurality of second connection openings 70 formed in the main surface insulating film 64.

[0114] Each of the plurality of second electrodes 69 is made of metal. In this embodiment, each of the plurality of second electrodes 69 has a layered structure including a second barrier film 71 and a second electrode body 72. The second barrier film 71 is formed in a film shape along the inner wall of the second connection opening 70. The second barrier film 71 may be made of a titanium-based metal film. The second barrier film 71 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film.

[0115] The second electrode body 72 is embedded in the second connection opening 70 with the second barrier film 71 sandwiched therebetween, and is electrically connected to the second mesa portion 54 (second contact region 24) with the second barrier film 71 sandwiched therebetween. The second electrode body 72 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the second electrode body 72 contains tungsten. Of course, the multiple second electrodes 69 may be formed only by the second electrode body 72 without the second barrier film 71.

[0116] 8 and 11, the semiconductor device 1A includes a plurality of second trench structures 73 formed in the first main surface 10 in the plurality of drift mesas 55.

[0117] In this embodiment, the plurality of second trench structures 73 are formed in the corresponding drift mesa portions 55, penetrating the main surface insulating film 64. Specifically, the plurality of second trench structures 73 are formed in the drift mesa portions 55 via a plurality of base connection openings 74 formed in the main surface insulating film 64. Referring to FIG. 8 , the second trench structures 73 are selectively formed in the contact region 61, and are not formed in the current region 62.

[0118] 11 , the plurality of second trench structures 73 are formed to reach the protruding portion 59. In this embodiment, the plurality of second trench structures 73 are formed shallower than the plurality of first trench structures 17. Specifically, the plurality of second trench structures 73 penetrate the first impurity region 63 and reach the protruding portion 59. Each of the plurality of second trench structures 73 has a bottom wall located within the protruding portion 59.

[0119] The spacing between the first trench structure 17 and the second trench structure 73 may be 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.5 μm or less). Each of the second trench structures 73 may have a width in the first direction X of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.5 μm or less). The width of each of the second trench structures 73 may be equal to or greater than the width of the first trench structure 17, or may be less than the width of the first trench structure 17. Each of the second trench structures 73 may have a depth of 0.1 μm or more and 10 μm or less (preferably 0.2 μm or more and 0.5 μm or less). This depth allows a silicide layer 79 (described below) to be formed over the entire second trench structure 73.

[0120] The second trench structure 73 includes a base trench 75 and a base electrode 76. The base electrode 76 is provided as a "first base contact 26" in this embodiment.

[0121] The base trench 75 is formed in the first main surface 10, penetrating the main surface insulating film 64, and defines the wall surfaces (side walls and bottom wall) of the second trench structure 73. In this embodiment, the base trench 75 includes a base connection opening 74 formed in the main surface insulating film 64. Specifically, the base trench 75 penetrates the main surface insulating film 64 and the first impurity region 63 to reach the protrusion 59. The base trench 75 exposes the first impurity region 63 and the protrusion 59 from the wall surfaces.

[0122] The base trench 75 may be formed in a tapered shape in which the opening width narrows from the first main surface 10 side toward the bottom wall side in a cross-sectional view. Of course, the base trench 75 may be formed perpendicular to the first main surface 10. The corners on the bottom wall side of the base trench 75 may be formed in a curved shape. Of course, the entire bottom wall of the base trench 75 may be formed in a curved shape toward the second main surface 11 side.

[0123] The base electrode 76 is buried in the base trench 75 without an insulating film therebetween. The base electrode 76 is mechanically and electrically connected to the first impurity region 63 and the protruding portion 59 within the base trench 75, and is mechanically connected to the main surface insulating film 64. Within the base trench 75, the base electrode 76 has a portion located on the semiconductor chip 8 side with respect to the first main surface 10, and a portion located on the main surface insulating film 64 side with respect to the first main surface 10. In other words, the base electrode 76 has an upper end portion that protrudes above the first main surface 10. Furthermore, the upper end portion of the base electrode 76 protrudes above the upper end portion of the gate electrode 50 (the upper end portion of the drawn-out portion 52).

[0124] The base electrode 76 may include at least one of a metal and a non-metal conductor. The base electrode 76 is preferably formed of a conductive material different from that of the gate electrode 50. The base electrode 76 preferably includes a metal. In this embodiment, the base electrode 76 has a layered structure including a base barrier film 77 and a base electrode body 78.

[0125] The base barrier film 77 is formed in a film shape along the sidewalls and bottom wall of the base trench 75, and covers the first impurity region 63, the protrusion 59, and the main surface insulating film 64 within the base trench 75. The base barrier film 77 defines a recess space within the base trench 75. The base barrier film 77 may be made of a titanium-based metal film. The base barrier film 77 may have a single-layer structure or a multilayer structure including either or both of a titanium film and a titanium nitride film. The base barrier film 77 is preferably made of the same material as the first barrier film 67 and the second barrier film 71.

[0126] The base electrode body 78 is buried in the base trench 75 with a base barrier film 77 sandwiched therebetween, and covers the first impurity region 63, the protrusion 59, and the main surface insulating film 64 with the base barrier film 77 sandwiched therebetween. The base electrode body 78 is electrically connected to the first impurity region 63 and the protrusion 59 via the base barrier film 77. The base electrode body 78 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The base electrode body 78 is preferably made of the same material as the first electrode body 68 and the second electrode body 72. In this embodiment, the base electrode body 78 contains tungsten. Of course, the base electrode 76 may be formed only by the base electrode body 78 without the base barrier film 77.

[0127] A silicide layer 79 is formed on the inner wall of the base trench 75. The silicide layer 79 is formed over the entire sidewall and bottom wall of the base trench 75 at the boundary between the semiconductor chip 8 and the base barrier film 77. The silicide layer 79 may cross the boundary between the first impurity region 63 and the protrusion 59 in the thickness direction of the semiconductor chip 8 from top to bottom.

[0128] If the silicide layer 79 is formed over the entire sidewalls and bottom wall of the base trench 75, the surface condition of the inner wall of the base trench 75 can be improved and smoothed, thereby achieving good contact between the base electrode body 78 and the base trench 75. This reduces the contact resistance of the base electrode body 78. As a result, even if the second trench structure 73 is not formed in the current region 62 but is only formed in the contact region 61, the effect of fixing the potential of the second semiconductor region 47 at a predetermined potential can be sufficiently obtained.

[0129] 8 and 12 , the semiconductor device 1A includes a plurality of third electrodes 80 electrically connected to the plurality of first trench structures 17. The plurality of third electrodes 80 are provided as "first gate contacts 27." The plurality of third electrodes 80 penetrate the main surface insulating film 64 and are mechanically and electrically connected to either or both of the plurality of first trench structures 17 (lead-out portions 52) and the plurality of trench connection structures 18 (connection electrodes 58).

[0130] Specifically, the multiple third electrodes 80 are respectively disposed in multiple third connection openings 81 formed in the main surface insulating film 64. In this embodiment, the multiple third electrodes 80 are mechanically and electrically connected to the multiple trench connection structures 18. That is, the multiple third electrodes 80 are electrically connected to the multiple first trench structures 17 via the multiple trench connection structures 18.

[0131] 8 , in this embodiment, the multiple third electrodes 80 are formed at intervals along the trench connection structures 18 in a plan view. The multiple third electrodes 80 may have any planar shape. The multiple third electrodes 80 may be formed in a circular or rectangular shape in a plan view. Of course, the multiple third electrodes 80 may each be formed in a strip shape extending along the corresponding trench connection structure 18 in a plan view.

[0132] Each of the multiple third electrodes 80 is made of metal. In this embodiment, each of the multiple third electrodes 80 has a layered structure including a third barrier film 82 and a third electrode body 83. The third barrier film 82 is formed in a film shape along the inner wall of the third connection opening 81. The third barrier film 82 may be made of a titanium-based metal film. The third barrier film 82 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film. The third barrier film 82 is preferably made of the same material as the first barrier film 67, the second barrier film 71, and the base barrier film 77.

[0133] The third electrode body 83 is embedded in the third connection opening 81 with the third barrier film 82 sandwiched therebetween and is electrically connected to the lead portion 52 (connection electrode 58) with the third barrier film 82 sandwiched therebetween. The third electrode body 83 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The third electrode body 83 is preferably made of the same material as the first electrode body 68. In this embodiment, the third electrode body 83 contains tungsten. Of course, the multiple third electrodes 80 may be composed only of the third electrode body 83 without having the third barrier film 82.

[0134] 9 to 12, the semiconductor device 1A includes a p-type bottom wall impurity region 84 formed in the second semiconductor region 47 in a region along the bottom wall of the first trench structure 17. In this embodiment, the bottom wall impurity region 84 is formed in the second semiconductor region 47 and has a higher p-type impurity concentration than the second semiconductor region 47. The p-type impurity concentration of the bottom wall impurity region 84 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ or less (in this form, 1 × 10 １７ cm －３ (degree).

[0135] The bottom wall impurity region 84 is formed in a strip shape extending along the bottom wall of the first trench structure 17 at intervals from the plurality of second trench structures 73 in a plan view. The bottom wall impurity region 84 faces the gate electrode 50 on the bottom wall of the first trench structure 17 with the gate insulating film 49 interposed therebetween. The bottom wall impurity region 84 may cover the bottom wall and sidewall of the first trench structure 17 at the lower end of the first trench structure 17.

[0136] The bottom wall impurity region 84 may cover the bottom wall of the trench connection structure 18 in the second semiconductor region 47. In this case, the bottom wall impurity region 84 may be formed in a strip shape extending along the bottom wall of the trench connection structure 18 in a plan view. Of course, the bottom wall impurity region 84 may expose the bottom wall of the trench connection structure 18.

[0137] The bottom wall impurity region 84 may have a thickness of 10 nm or more and 500 nm or less. The thickness of the bottom wall impurity region 84 is preferably 100 nm or more and 300 nm or less. The thickness of the bottom wall impurity region 84 is the distance between the bottom wall of the first trench structure 17 and the bottom of the bottom wall impurity region 84. The bottom wall impurity region 84 has a width in the first direction X that exceeds the width of the bottom wall of the first trench structure 17. The width of the bottom wall impurity region 84 is defined by the width of the most protruding region in the bottom wall impurity region 84. The width of the bottom wall impurity region 84 may exceed the opening width of the first trench structure 17. The width of the bottom wall impurity region 84 may be 0.1 μm or more and 0.5 μm or less.

[0138] 9 to 12, the semiconductor device 1A includes a first interlayer insulating film 85 stacked on the main surface insulating film 64. The first interlayer insulating film 85 may be a part of the insulating layer 9 described above. The first interlayer insulating film 85 may include at least one of silicon oxide and silicon nitride. The first interlayer insulating film 85 covers the entire main surface insulating film 64 and is continuous with the first to fourth side surfaces 12A to 12D. The first interlayer insulating film 85 may have a flat surface extending along the first main surface 10. The flat surface of the first interlayer insulating film 85 may have grinding marks.

[0139] A first wiring layer 28 is formed on the first interlayer insulating film 85. The first wiring layer 28 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The first wiring layer 28 may contain at least one of a Cu film (a Cu film having a purity of 99% or more), a pure Al film (an Al film having a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0140] As described above, the first wiring layer 28 includes a first gate wiring layer 30, a first lower wiring layer 31, a second lower wiring layer 32, and a first base wiring layer 33. The first gate wiring layer 30 is connected to the first gate contact 27 (FIG. 12), and the first lower wiring layer 31 is connected to the first lower contact 23 (FIG. 9). The second lower wiring layer 32 is connected to the second lower contact 25 (FIG. 10), and the first base wiring layer 33 is connected to the first base contact 26 (FIG. 11).

[0141] 9 to 12, semiconductor device 1A includes second interlayer insulating film 86 stacked on first interlayer insulating film 85 so as to cover first wiring layer 28. Second interlayer insulating film 86 may be part of insulating layer 9 described above. Second interlayer insulating film 86 may include at least one of silicon oxide and silicon nitride. Second interlayer insulating film 86 covers the entire first interlayer insulating film 85 and is continuous with first to fourth side surfaces 12A to 12D. Second interlayer insulating film 86 may have a flat surface extending along first main surface 10. The flat surface of second interlayer insulating film 86 may have grinding marks.

[0142] A second wiring layer 29 is formed on the second interlayer insulating film 86. The second wiring layer 29 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The second wiring layer 29 may contain at least one of a Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0143] As described above, the second wiring layer 29 includes the second gate wiring layer 34, the first upper wiring layer 35, the second upper wiring layer 36, and the second base wiring layer 37. The second gate wiring layer 34 is connected to the first gate wiring layer 30 via a second gate contact 38 penetrating the second interlayer insulating film 86 ( FIG. 6 ). The first upper wiring layer 35 is connected to the first lower wiring layer 31 via a first upper contact 40 penetrating the second interlayer insulating film 86 ( FIG. 6 ). The second upper wiring layer 36 is connected to the second lower wiring layer 32 via a second upper contact 41 penetrating the second interlayer insulating film 86 ( FIG. 6 ). The second base wiring layer 37 is connected to the first base wiring layer 33 via a second base contact 39 penetrating the second interlayer insulating film 86 ( FIG. 6 ).

[0144] Referring to FIG. 12 , the semiconductor device 1A includes a top insulating film 87 formed on the second interlayer insulating film 86. The top insulating film 87 is omitted in FIGS. 9 to 11 . The top insulating film 87 may be part of the insulating layer 9 described above. The top insulating film 87 may also be referred to as a “passivation film.” The top insulating film 87 may have a layered structure including an inorganic insulating film (inorganic film) and an organic insulating film (organic film) stacked in this order from the second interlayer insulating film 86 side. Of course, the top insulating film 87 may have a single-layer structure made of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film is preferably made of an insulating material different from that of the second interlayer insulating film 86. The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0145] A plurality of external terminals 4 to 7 are formed on the top insulating film 87 (see FIG. 7 ). As described above, the plurality of external terminals 4 to 7 include the base terminal 4, the gate terminal 5, the first source / drain terminal 6, and the second source / drain terminal 7. The base terminal 4 is connected to the second base wiring layer 37 via a base terminal contact 43 that penetrates the top insulating film 87 ( FIG. 7 ), and the gate terminal 5 is connected to the second gate wiring layer 34 via a gate terminal contact 42 that penetrates the top insulating film 87 ( FIG. 7 ). The first source / drain terminal 6 is connected to the first upper wiring layer 35 via a first terminal contact 44 that penetrates the top insulating film 87 ( FIG. 7 ), and the second source / drain terminal 7 is connected to the second upper wiring layer 36 via a second terminal contact 45 that penetrates the top insulating film 87 ( FIG. 7 ).

[0146] 9 to 12, the semiconductor device 1A includes a back surface protective film 88 that covers the second main surface 11 of the semiconductor chip 8. In this embodiment, the back surface protective film 88 covers the entire second main surface 11 and also covers the first to fourth side surfaces 12A to 12D (FIG. 12). The back surface protective film 88 may have a single-layer structure made of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0147] 9 to 11 , the semiconductor device 1A includes a first pn junction 89 and a second pn junction 90 each formed inside the semiconductor chip 8. The first pn junction 89 is formed at the boundary 60 between the first semiconductor region 46 and the second semiconductor region 47 on the first mesa 53 side. As a result, a first body diode D1 including the second semiconductor region 47 as an anode region and the first semiconductor region 46 as a cathode region is formed in the first mesa 53.

[0148] The second pn junction 90 is formed at the boundary 60 between the first semiconductor region 46 and the second semiconductor region 47 on the second mesa 54 side. As a result, a second body diode D2 including the second semiconductor region 47 as an anode region and the first semiconductor region 46 as a cathode region is formed in the second mesa 54. The anode of the second body diode D2 (second pn junction 90) is electrically connected to the anode of the first body diode D1 (first pn junction 89) via the second semiconductor region 47.

[0149] (2) Manufacturing Process of Semiconductor Device 1A Next, an example of a manufacturing method of the semiconductor device 1A will be described. Figures 13A to 13J are cross-sectional views showing an example of a manufacturing method of the semiconductor device 1A shown in Figure 1. Figures 13A to 13J are all cross-sectional views of the region corresponding to Figure 11.

[0150] 13A , a disk-shaped wafer 91 is prepared. The wafer 91 includes a first wafer main surface 92 on one side and a second wafer main surface 93 on the other side. The wafer 91 is made of a p-type semiconductor substrate entirely formed of the second semiconductor region 47. Next, the first semiconductor region 46 is formed in the surface layer portion of the first wafer main surface 92. The first semiconductor region 46 is formed by introducing n-type impurities into the surface layer portion of the first wafer main surface 92 by ion implantation. The n-type impurities may be introduced into the entire surface layer portion of the first wafer main surface 92 without using an ion implantation mask.

[0151] Of course, n-type impurities may be introduced via an ion implantation mask into regions in the surface layer of the first wafer main surface 92 where the first semiconductor regions 46 are to be formed. Alternatively, the first semiconductor regions 46 may be formed by growing silicon from the second semiconductor regions 47 (semiconductor substrate) by epitaxial growth. In this case, the first wafer main surface 92 is formed by the crystal plane (crystal growth plane) of the first semiconductor regions 46.

[0152] Referring to FIG. 13B , a plurality of first trenches 48 and a plurality of connection trenches 56 are formed on the first wafer main surface 92. In this process, unnecessary portions of the wafer 91 are selectively removed by etching via a hard mask (not shown). The etching may be wet etching and / or dry etching. The etching is preferably RIE (Reactive Ion Etching), an example of a dry etching method. This forms a plurality of first trenches 48 and a plurality of connection trenches 56. Furthermore, a plurality of mesas 53 to 55 are defined on the first wafer main surface 92 by the plurality of first trenches 48 (a plurality of connection trenches 56). The hard mask is then removed.

[0153] 13C , a first base insulating film 94 that serves as a base for the plurality of gate insulating films 49 and the plurality of connection insulating films 57 is formed on the first wafer main surface 92. The first base insulating film 94 is formed on the first wafer main surface 92, including the inner walls of the plurality of first trenches 48 and the inner walls of the plurality of connection trenches 56. The first base insulating film 94 may be formed by an oxidation process and / or a CVD process (preferably a thermal oxidation process).

[0154] 13D , a plurality of bottom wall impurity regions 84 are formed in the second semiconductor region 47 in regions along the bottom walls of the plurality of first trenches 48 and the bottom walls of the plurality of connection trenches 56. Concurrently, protrusions 59 are selectively formed in the drift mesa portion 55. In this step, first, an ion implantation mask (not shown) having a predetermined pattern is formed on the first wafer main surface 92. Next, p-type impurities are selectively introduced into the second semiconductor region 47 by ion implantation via the ion implantation mask. This forms the plurality of bottom wall impurity regions 84 and the protrusions 59. The ion implantation mask is then removed.

[0155] 13E , a plurality of first contact regions 22, a plurality of second contact regions 24, and a plurality of first impurity regions 63 are formed. In this step, first, an ion implantation mask (not shown) having a predetermined pattern is formed on the first wafer main surface 92. Next, n-type impurities are selectively introduced into the first semiconductor region 46 by ion implantation via the ion implantation mask. This forms a plurality of first contact regions 22, a plurality of second contact regions 24, and a plurality of first impurity regions 63. The ion implantation mask is then removed.

[0156] 13F , a first base electrode (not shown) that serves as a base for the plurality of gate electrodes 50, the plurality of lead portions 52, and the plurality of connection electrodes 58 is formed on the first wafer main surface 92. The first base electrode is formed in the form of a film that fills the plurality of first trenches 48 and the plurality of connection trenches 56 and covers the first wafer main surface 92. In this embodiment, the first base electrode includes conductive polysilicon. The first base electrode may be formed by a CVD method. Next, unnecessary portions of the first base electrode are removed. This results in the formation of the plurality of gate electrodes 50, the plurality of lead portions 52, and the plurality of connection electrodes 58.

[0157] 13G, a second base insulating film 95, which serves as a base for the buried insulator 51 and the main surface insulating film 64, is formed on the first wafer main surface 92. In this embodiment, the second base insulating film 95 is made of a silicon oxide film. The second base insulating film 95 may be formed by a CVD method. The CVD method for the second base insulating film 95 is preferably a high density plasma (HDP)-CVD method.

[0158] The second base insulating film 95 fills recess spaces defined by the plurality of lead portions 52 in the plurality of first trenches 48, and covers the first wafer main surface 92, the plurality of lead portions 52, and the connection electrodes 58. This forms the buried insulator 51 located in the first trenches 48 and the main surface insulating film 64 located on the first wafer main surface 92.

[0159] 13H , a plurality of first connection openings 66, a plurality of second connection openings 70, a plurality of third connection openings 81, and a plurality of base trenches 75 (base connection openings 74) are formed in the first wafer main surface 92. In this process, a resist mask (not shown) having a predetermined pattern is first formed on the main surface insulating film 64. Next, unnecessary portions of the main surface insulating film 64 are selectively removed by etching through the resist mask. The etching method may be wet etching and / or dry etching (preferably RIE). As a result, a plurality of first connection openings 66, a plurality of second connection openings 70, a plurality of third connection openings 81, and a plurality of base connection openings 74 are formed in the main surface insulating film 64.

[0160] Next, unnecessary portions of the wafer 91 are removed by etching through the resist mask. The etching may be wet etching and / or dry etching (preferably RIE). The unnecessary portions of the wafer 91 are removed until they penetrate the first impurity regions 63 and expose the protrusions 59. This forms a plurality of base trenches 75, each including a base connection opening 74, in the first wafer main surface 92. The resist mask is then removed.

[0161] Referring to FIG. 13I , a second base electrode (not shown) serving as a base for the plurality of first electrodes 65, the plurality of second electrodes 69, the plurality of base electrodes 76, and the plurality of third electrodes 80 is formed on the main surface insulating film 64. In this embodiment, the second base electrode includes a base barrier film and an electrode body film stacked in this order from the wafer 91 side. Next, unnecessary portions of the second base electrode are selectively removed by etching. The etching may be wet etching and / or dry etching (preferably RIE). The second base electrode is removed until the main surface insulating film 64 is exposed. This results in the formation of the plurality of first electrodes 65, the plurality of second electrodes 69, the plurality of base electrodes 76, and the plurality of third electrodes 80. After the formation of these electrodes, a silicide layer 79 is formed on the inner wall of the base trench 75 by annealing (e.g., at a temperature of 500° C. or higher and 1100° C. or lower).

[0162] 13J, first interlayer insulating film 85, first wiring layer 28, second interlayer insulating film 86, second wiring layer 29, top insulating film 87, back surface protective film 88, and external terminals 4 to 7 are formed, and wafer 91 is selectively cut in the thickness direction. Through the steps including those described above, semiconductor device 1A is manufactured.

[0163] (3) Operation and Technical Effects of Semiconductor Device 1A Fig. 14 is a cross-sectional view showing a current path 97 of semiconductor device 1A according to the first embodiment of the present disclosure. Fig. 15 is a plan view showing a current path 97 of semiconductor device 1A according to the first embodiment of the present disclosure.

[0164] The semiconductor device 1A has a trench-gate lateral MISFET structure. In this MISFET structure, a gate potential is applied to the first trench structure 17 (gate electrode 50), a drain potential is applied to the first mesa portion 53, and a source potential is applied to the second mesa portion 54. As a result, a channel 96 is formed in the second semiconductor region 47 in a region below the first trench structure 17, and a lateral current path 97 is formed connecting the first electrode 65 (first mesa portion 53) and the second electrode 69 (second mesa portion 54).

[0165] As shown in FIG. 14 , the current path 97 is a path through which current flows in the following order: first mesa portion 53 (first semiconductor region 46) → bottom wall impurity region 84 (high-concentration p-type region) → drift mesa portion 55 (first semiconductor region 46) → bottom wall impurity region 84 (high-concentration p-type region) → second mesa portion 54 (first semiconductor region 46). In other words, the current path 97 is hardly formed in the second semiconductor region 47. Therefore, even if the semiconductor chip 8 is formed using a single structure of a semiconductor substrate with high resistance (in this embodiment, 10 Ω·cm to 100 Ω·cm), an increase in the on-resistance of the semiconductor device 1A can be suppressed. As a result, there is no need to form an epitaxial layer on the wafer 91 during the manufacturing process of the semiconductor device 1A, which simplifies the manufacturing process and reduces materials and costs.

[0166] 8 , in the semiconductor device 1A, the drift region 21 is divided into a contact region 61 and a current region 62 in the second direction Y. A base electrode 76 for fixing the potential (substrate potential) of the second semiconductor region 47 is selectively formed in the contact region 61, but not in the current region 62. This allows a current path 97 that connects the first electrode 65 and the second electrode 69 over the shortest distance to be formed in the current region 62. In other words, by separately arranging the contact region 61 for fixing the substrate potential and the current region 62 for the current path 97, a current can flow without detouring around the base electrode 76, thereby reducing the on-resistance.

[0167] 11 , the contact region 61 has a protrusion 59 extending toward the first major surface 10. This allows the contact point with the second semiconductor region 47 to be raised toward the first major surface 10 beyond the boundary 60 between the first semiconductor region 46 and the second semiconductor region 47. Therefore, there is no need to form a second trench structure 73 that reaches the boundary 60, and the substrate potential can be fixed by the relatively shallow second trench structure 73. Because the base trench 75 can be shallow, contact with the substrate potential can be ensured with a simple structure.

[0168] 11 , for example, if the second trench structure 73 has a depth reaching the second main surface 11 side beyond the boundary portion 60, the silicide layer 79 may be formed only locally on the inner wall of the base trench 75. Specifically, the silicide layer 79 may be formed locally on the bottom wall and the upper end of the sidewall of the base trench 75, and not on other portions of the inner wall. In contrast, in the structure shown in FIG. 11 , the base trench 75 is shallow, so the silicide layer 79 can be formed over the entire second trench structure 73. This can improve the smoothness of the surface condition of the inner wall of the base trench 75, thereby ensuring good contact between the base electrode body 78 and the base trench 75. This can reduce the contact resistance of the base electrode body 78.

[0169] Because the contact region 61 for fixing the substrate potential is formed in the active region 15, there is no need to form a peripheral structure for fixing the substrate potential in the peripheral region 16. This allows the area of ​​the peripheral region 16 to be narrowed and the area of ​​the active region 15 to be enlarged. As a result, the current characteristics of the semiconductor device 1A can be improved. For example, in the semiconductor device 1A, the occupancy rate of the active region 15 on the first main surface 10 may be 10% or more and 99.9% or less.

[0170] (4) Modifications of the Semiconductor Device 1A Next, modifications of the semiconductor device 1A will be described with reference to FIGS.

[0171] FIG. 16 is a cross-sectional view showing a first modified example of the semiconductor device 1A according to the first embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG.

[0172] 16 , the protrusion 59 may extend from the second semiconductor region 47 through the drift mesa 55 and reach the first main surface 10. As a result, the protrusion 59 may have a top 98 exposed from the first main surface 10 in the contact region 61. In this case, the base electrode 76 does not have to be formed as the second trench structure 73. The base electrode 76 may be embedded in the base connection opening 74 and have a bottom on the first main surface 10. As a result, the base electrode 76 is connected to the protrusion 59 at the first main surface 10. With this configuration, the step of forming the second trench structure 73 can be omitted, simplifying the manufacturing process and reducing materials and costs.

[0173] FIG. 17 is a cross-sectional view showing a second modification of the semiconductor device 1A according to the first embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG.

[0174] 17 , the second trench structure 73 may be deeper than the first trench structure 17. Specifically, a base trench 75 deeper than the first trench 48 may cross the boundary portion 60 and reach the second semiconductor region 47. This makes it possible to omit the step of forming the protrusion 59, thereby simplifying the manufacturing process and reducing materials and costs.

[0175] FIG. 18 is a cross-sectional view showing a third modified example of the semiconductor device 1A according to the first embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG.

[0176] 18 , the back surface protective film 88 does not have to be formed on the second main surface 11 of the semiconductor chip 8. The second main surface 11 of the semiconductor chip 8 may be an exposed surface. This allows the step of forming the back surface protective film 88 to be omitted, thereby simplifying the manufacturing process and reducing materials and costs.

[0177] 19 is a schematic plan view showing the internal structure of a semiconductor device 1B according to a second embodiment of the present disclosure. In the second embodiment, the description of the external structure of the semiconductor device 1B, such as the arrangement of the external terminals 4 to 7 shown in FIGS. 2 and 3, will be omitted, and the description will be focused mainly on the internal structure of the semiconductor device 1B.

[0178] The semiconductor device 1B includes a semiconductor chip 101. The semiconductor chip 101 is formed in a rectangular parallelepiped shape. The semiconductor chip 101 includes a first main surface 102 on one side, a second main surface 103 on the other side (see FIG. 22 and subsequent figures), and side surfaces 104A, 104B, 104C, and 104D connecting the first main surface 102 and the second main surface 103. The side surfaces 104A to 104D specifically include the first side surface 104A, the second side surface 104B, the third side surface 104C, and the fourth side surface 104D.

[0179] An active area 105 and a peripheral area 106 surrounding the active area 105 are defined on a first main surface 102 of the semiconductor chip 101 .

[0180] The outer peripheral region 106 may coincide with the annular periphery along the side surfaces 104A to 104D of the semiconductor chip 101. The outer peripheral region 106 may be an annular region extending from the side surfaces 104A to 104D of the semiconductor chip 101 to a position several μm inward. The active region 105 may be a central region of the semiconductor chip 101 surrounded by the outer peripheral region 106. The active region 105 may be, for example, a region in which most of the element structure of the MISFET 2 is formed.

[0181] The active region 105 has an element structure of a MISFET 2. In this embodiment, the element structure is a trench gate lateral type MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure.

[0182] The MISFET 2 includes a first source / drain region 107 , a second source / drain region 108 , and a drift region 109 as an element structure formed in the active region 105 .

[0183] In this embodiment, a plurality of first source / drain regions 107 and a plurality of second source / drain regions 108 are alternately arranged at intervals in the first direction X. A drift region 109 is sandwiched between adjacent first source / drain regions 107 and second source / drain regions 108. As a result, the first source / drain regions 107 and the second source / drain regions 108 face each other with the drift region 109 sandwiched between them. In FIG. 19 , sets of the first source / drain region 107, drift region 109, second source / drain region 108, and drift region 109 are repeatedly arranged in the first direction X, in that order from the top of the page.

[0184] In the first main surface 102, a repeating structure of a plurality of first source / drain regions 107, a plurality of second source / drain regions 108, and a plurality of drift regions 109 is divided into a plurality of sections. The plurality of sections includes a plurality of cell regions 110. The plurality of cell regions 110 is partitioned by a plurality of wiring regions 111 extending in the first direction X. In this embodiment, two wiring regions 111 extend in the first direction X, dividing the first main surface 102 into three parts. A region of a constant width sandwiched between the two wiring regions 111 and a region outside each wiring region 111 in the second direction Y are the cell regions 110. As a result, a plurality of (three in FIG. 19 ) cell regions 110 are arranged at intervals in the second direction Y. The wiring region 111 extends in the first direction X between adjacent cell regions 110 and crosses the vicinity of each end of the plurality of first source / drain regions 107 and the plurality of second source / drain regions 108 .

[0185] In each cell region 110, the first source / drain region 107 and the second source / drain region 108 are formed in a strip shape extending in the second direction Y. The first source / drain regions 107, the second source / drain regions 108, and the drift regions 109 are arranged with a regularity such that regions of the same type are aligned in the second direction Y.

[0186] 19 , from the top of the page, rows of a plurality of first source / drain regions 107 aligned in the second direction Y and rows of a plurality of second source / drain regions 108 aligned in the second direction Y are alternately formed. Between these rows, rows of a plurality of drift regions 109 aligned in the second direction Y are formed. As a result, the plurality of first source / drain regions 107, the plurality of second source / drain regions 108, and the plurality of drift regions 109 do not face regions of different species in the second direction Y. In other words, in FIG. 19 , the plurality of first source / drain regions 107, the plurality of second source / drain regions 108, and the plurality of drift regions 109 extending in a strip shape in the second direction Y may be divided into a plurality of portions by a plurality of wiring regions 111, and each portion may constitute one first source / drain region 107, one second source / drain region 108, and one drift region 109.

[0187] A plurality of wiring layers are formed on the first main surface 102 of the semiconductor chip 101, and the above-mentioned plurality of external terminals are connected to the uppermost layer of the plurality of wiring layers. The plurality of wiring layers form a multilayer wiring structure, and only the first wiring layer 112 is shown in FIG.

[0188] The first wiring layer 112 may be referred to as the "first metal." The first wiring layer 112 includes a first gate wiring layer 113 and a first base wiring layer 114. The first wiring layer 112 includes other wiring layers, which will be described later. The first gate wiring layer 113 and the first base wiring layer 114 are wiring layers that are physically independent of each other.

[0189] The first gate wiring layer 113 includes a gate periphery 115 extending along the periphery region 106 and gate branch portions 116 extending from the gate periphery 115 toward the inside of the semiconductor chip 101, on the wiring region 111, and along the periphery of the semiconductor chip 101. The gate periphery 115 extends linearly along the third side surface 104C on one side of the plurality of cell regions 110 in the first direction X (in this embodiment, the third side surface 104C side). Parts of the gate branch portions 116 are formed linearly, extending in pairs from midway along the longitudinal direction of the gate periphery 115 toward each wiring region 111. The pair of gate branch portions 116 are parallel to each other. Other portions of the gate branch portions 116 extend linearly on the periphery region 106 from each of both ends of the gate periphery 115.

[0190] The first gate wiring layer 113 is connected to a first gate contact 117. In this embodiment, the plurality of first gate contacts 117 are covered by the gate branch portion 116. In each gate branch portion 116, the plurality of first gate contacts 117 are arranged at intervals in the first direction X.

[0191] The first base wiring layer 114 includes a base peripheral portion 118 extending along the peripheral region 106 and a base branch portion 119 extending from the base peripheral portion 118 toward the inside of the semiconductor chip 101 over the wiring region 111. The base peripheral portion 118 is formed in a closed ring shape that collectively surrounds the multiple cell regions 110 and the first gate wiring layer 113. In this configuration, the base peripheral portion 118 is formed in a rectangular ring shape in a plan view. The base branch portions 119 are formed in linear shapes that extend one by one from the middle of one longitudinal side of the base peripheral portion 118 toward each wiring region 111. In this configuration, each base branch portion 119 is arranged between a pair of gate branch portions 116 arranged in the wiring region 111 and is sandwiched between the pair of gate branch portions 116.

[0192] The first base wiring layer 114 is connected to the first base contacts 120. In this embodiment, the plurality of first base contacts 120 are covered by the base branch portion 119. In each base branch portion 119, the plurality of first base contacts 120 are arranged at intervals in the first direction X.

[0193] Fig. 20 is an enlarged view of a portion surrounded by a two-dot chain line XX in Fig. 19. Fig. 21 is an enlarged view of a portion surrounded by a two-dot chain line XX in Fig. 19. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 20. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 20. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 20.

[0194] 20 to 24, the semiconductor device 1B includes a semiconductor chip 101. The semiconductor chip 101 is a semiconductor chip 101 made of a single layer. The semiconductor chip 101 made of a single layer has a single structure of a semiconductor substrate without an epitaxial layer. In this embodiment, the semiconductor chip 101 includes a single crystal of Si (silicon) or a wide bandgap semiconductor without an epitaxial layer. A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si. The semiconductor chip 101 may be a Si chip or a SiC (silicon carbide) chip.

[0195] The semiconductor device 1B includes a first semiconductor region 121 of n-type (first conductivity type) formed in a region on the first main surface 102 side of the semiconductor chip 101. The first semiconductor region 121 may also be referred to as a "drift layer." The first semiconductor region 121 is formed in the semiconductor chip 101 at an interval from the second main surface 103 toward the first main surface 102. The first semiconductor region 121 is formed in a layer shape extending along the first main surface 102 in a surface layer portion of the first main surface 102, and is exposed from the entire first main surface 102 and portions of the first to fourth side surfaces 104A to 104D.

[0196] Of course, the first semiconductor region 121 may be formed in the inner part of the first main surface 102 at intervals from the first to fourth side surfaces 104A to 104D in a plan view. １４ cm －３ 1x10 or more １８ cm －３ The first semiconductor region 121 may have a thickness of 0.1 μm or more and 10 μm or less (preferably 0.5 μm or more and 2 μm or less).

[0197] The semiconductor device 1B includes a p-type (second conductivity type) second semiconductor region 122 formed in a region of the semiconductor chip 101 closer to the second main surface 103 than the first semiconductor region 121. The second semiconductor region 122 may be referred to as a "base layer." The second semiconductor region 122 has a conductivity of 1×10 １３ cm －３ 1x10 or more １６ cm －３ More specifically, the p-type impurity concentration of the second semiconductor region 122 over the entire area from the second main surface 103 to the first semiconductor region 121 in the thickness direction of the semiconductor chip 101 may be 1×10 １３ cm －３ 1x10 or more １６ cm －３ The following is the result.

[0198] The reason why the p-type impurity concentration of the second semiconductor region 122 is almost constant in the thickness direction of the semiconductor chip 101 is that the semiconductor chip 101 is composed of a single-structure semiconductor substrate without an epitaxial layer. Normally, when an epitaxial layer is grown on a semiconductor substrate (base substrate), the impurity concentration of the epitaxial layer is made relatively low to ensure a breakdown voltage, even if the epitaxial layer has the same conductivity type as the base substrate. On the other hand, the impurity concentration of the base substrate is made high to reduce the ohmic resistance of the back electrode formed on the second main surface 103.

[0199] However, in this embodiment, the MISFET 2 is of the lateral type, and the current path 185 (see FIGS. 26 and 27 ) is only in the lateral direction along the first main surface 102, so that no current flows in the thickness direction of the second semiconductor region 122. Therefore, even if the p-type impurity concentration of the second semiconductor region 122 is low throughout, there is little concern that the on-resistance will increase. For example, the resistance value of the second semiconductor region 122 may be 10 Ω·cm or more and 100 Ω·cm or less throughout the entire thickness direction of the semiconductor chip 101, from the second main surface 103 to the first semiconductor region 121.

[0200] The second semiconductor region 122 is formed in a layer shape extending along the first main surface 102 (first semiconductor region 121) within the semiconductor chip 101, and is exposed from a portion of the first to fourth side surfaces 104A to 104D. The second semiconductor region 122 is electrically connected to the first semiconductor region 121 within the semiconductor chip 101. Specifically, the second semiconductor region 122 forms a pn junction with the first semiconductor region 121. The second semiconductor region 122 may have a thickness of 0.5 μm or more and 755 μm or less.

[0201] The MISFET 2 includes a first trench structure 123 , a trench connection structure 124 , and a trench breakdown withstanding structure 125 as trench structures formed in the first main surface 102 .

[0202] The multiple first trench structures 123 may also be referred to as "trench gate structures." The multiple first trench structures 123 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. The multiple first trench structures 123 are formed in a stripe shape extending in the second direction Y in a plan view. Each of the multiple first trench structures 123 has a first end on one side and a second end on the other side in the second direction Y.

[0203] The plurality of first trench structures 123 penetrate the first semiconductor region 121 to reach the second semiconductor region 122. In this form, the plurality of first trench structures 123 each have a bottom wall located within the second semiconductor region 122. The plurality of first trench structures 123 are configured to respectively control inversion and non-inversion of a channel (a channel 184 described below) in the second semiconductor region 122.

[0204] The plurality of first trench structures 123 may be arranged at intervals (pitch) of 0.03 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.3 μm or less). The plurality of first trench structures 123 are preferably arranged at approximately equal intervals in the first direction X. Each of the plurality of first trench structures 123 may have a width in the first direction X of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 0.5 μm or less). Each of the plurality of first trench structures 123 may have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less).

[0205] The following describes the internal structure of one first trench structure 123. The first trench structure 123 includes a first trench 126, a gate insulating film 127 (control insulating film), a gate electrode 128 (control electrode), and a buried insulator 129.

[0206] The first trench 126 may also be referred to as a “gate trench.” The first trench 126 is formed in the first main surface 102 and defines the wall surfaces (side walls and bottom wall) of the first trench structure 123. The first trench 126 exposes the first semiconductor region 121 and the second semiconductor region 122 from the wall surfaces.

[0207] The first trench 126 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, the first trench 126 may be formed perpendicular to the first main surface 102. The corners on the bottom wall side of the first trench 126 may be formed in a curved shape. Of course, the entire bottom wall of the first trench 126 may be formed in a curved shape toward the second main surface 103 side.

[0208] The gate insulating film 127 coats the sidewalls and bottom wall of the first trench 126 in a film-like manner. In this embodiment, the gate insulating film 127 coats the sidewalls and bottom wall of the first trench 126 on the bottom wall side and defines a recess space on the bottom wall side of the first trench 126. The gate insulating film 127 may have a thickness of 5 nm to 1000 nm in the normal direction to the wall surface of the first trench 126. The gate insulating film 127 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The gate insulating film 127 is preferably made of a silicon oxide film. It is particularly preferable that the gate insulating film 127 be made of an oxide (thermal oxide film) of the semiconductor chip 101.

[0209] The gate electrode 128 is embedded in the first trench 126 with a gate insulating film 127 sandwiched therebetween. Specifically, the gate electrode 128 is embedded in a recess space defined by the gate insulating film 127 on the bottom wall side of the first trench 126, and faces the second semiconductor region 122 with the gate insulating film 127 sandwiched therebetween. The gate electrode 128 crosses the depth position of the boundary between the first semiconductor region 121 and the second semiconductor region 122 in the depth direction of the first trench 126.

[0210] The gate electrode 128 includes a plurality of lead-out portions 130 that are led out from the bottom wall side of the first trench 126 to the opening side. The number of the lead-out portions 130 is arbitrary. In this embodiment, the plurality of lead-out portions 130 includes a pair of lead-out portions 130 that are spaced apart in the second direction Y. In this embodiment, the pair of lead-out portions 130 are formed at both ends of the first trench 126, respectively. The plurality of lead-out portions 130 each extend in the second direction Y in a plan view.

[0211] The multiple lead-out portions 130 define an opening-side recess from the wall surface of the first trench 126 on the opening side of the first trench 126. The opening-side recess is defined in a strip shape extending in the second direction Y in a plan view. The multiple lead-out portions 130 may protrude above the first main surface 102. The multiple lead-out portions 130 may be led out from the first trench 126 onto the first main surface 102 with part of the gate insulating film 127 sandwiched therebetween. Of course, the multiple lead-out portions 130 may be located on the bottom wall side of the first trench 126 with respect to the first main surface 102.

[0212] The gate electrode 128 may include at least one of a metal and a non-metal conductor. The gate electrode 128 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The gate electrode 128 preferably includes a non-metal conductor (conductive polysilicon). The conductive polysilicon may be p-type polysilicon or n-type polysilicon. The conductive polysilicon is preferably n-type polysilicon.

[0213] The buried insulator 129 is buried on the opening side of the first trench 126 so as to cover the gate electrode 128 within the first trench 126. Specifically, the buried insulator 129 is buried in a recess on the opening side defined by the gate electrode 128. The buried insulator 129 is provided as a field insulator that relieves the electric field with respect to the first trench 126. The buried insulator 129 is configured so that the area facing the first semiconductor region 121 exceeds the area facing the gate electrode 128 with respect to the first semiconductor region 121.

[0214] The buried insulator 129 has a thickness greater than the thickness of the gate electrode 128 in the depth direction of the first trench 126. The buried insulator 129 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The buried insulator 129 is preferably made of a silicon oxide film. The buried insulator 129 is preferably made of the same material as the gate insulating film 127. In this case, the buried insulator 129 is preferably made of an insulating vapor-deposited film and has a density different from that of the gate insulating film 127.

[0215] The semiconductor device 1B includes a plurality of mesas 131-133 defined on the first main surface 102 (first semiconductor region 121) by a plurality of first trench structures 123. The plurality of mesas 131-133 are defined in strip shapes extending in the second direction Y in regions between pairs of adjacent first trench structures 123. The plurality of mesas 131-133 include a plurality of first mesas 131, a plurality of second mesas 132, and a plurality of drift mesas 133.

[0216] The first mesa 131 and the second mesa 132 are arranged at an interval in the first direction X so as to sandwich one drift mesa 133. The first mesa 131 forms the first source / drain region 107 and may be referred to as the "first source / drain mesa." The second mesa 132 forms the second source / drain region 108 and may be referred to as the "second source / drain mesa." The drift mesa 133 forms the drift region 109.

[0217] The trench connection structure 124 is connected to the first trench structure 123. The plurality of trench connection structures 124 includes a trench connection structure 124 on one side connecting first ends of the plurality of first trench structures 123, and a trench connection structure 124 on the other side connecting second ends of the plurality of first trench structures 123.

[0218] In this embodiment, the trench connection structure 124 connects the ends of a pair of first trench structures 123 adjacent to each other in the first direction X. Specifically, one trench connection structure 124 is connected to each of the first ends and second ends of the pair of first trench structures 123. As a result, a plurality of closed regions surrounded by the pair of first trench structures 123 and the pair of trench connection structures 124 are formed on the first main surface 10.

[0219] The pair of first trench structures 123 and the pair of trench connection structures 124 define the first source / drain region 107 and the second source / drain region 108. In other words, the semiconductor device 1B has, on the first main surface 102 side, the first source / drain region 107 and the second source / drain region 108 that are separated and independent from each other and are surrounded by a trench structure that is rectangular in plan view and is formed by the pair of first trench structures 123 and the pair of trench connection structures 124.

[0220] The plurality of trench connection structures 124 penetrate the first semiconductor region 121 to reach the second semiconductor region 122. In other words, the trench connection structure 124, together with the plurality of first trench structures 123, defines a plurality of mesas 131 to 133 (a plurality of first mesas 131, a plurality of second mesas 132, and a plurality of drift mesas 133).

[0221] The trench connection structure 124 may have a width in the second direction Y of 0.01 μm to 10 μm (preferably 0.1 μm to 2 μm). The trench connection structure 124 may have a width substantially equal to the width of the first trench structure 123. The trench connection structures 124 may each have a depth of 0.2 μm to 30 μm (preferably 0.5 μm to 10 μm). The trench connection structure 124 may have a depth substantially equal to the depth of the first trench structure 123.

[0222] The trench connection structure 124 includes a connection trench 134, a connection insulating film 135, and a connection electrode 136. The connection trench 134 is formed in the first main surface 102 so as to communicate with the multiple first trenches 126, and defines the wall surfaces (side walls and bottom wall) of the trench connection structure 124. The wall surfaces (side walls and bottom wall) of the trench connection structure 124 are integrally connected to the wall surfaces (side walls and bottom walls) of the multiple first trenches 126. The connection trench 134 exposes the first semiconductor region 121 and the second semiconductor region 122 from the wall surfaces.

[0223] The connection trench 134 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, the connection trench 134 may be formed perpendicular to the first main surface 102. The corners on the bottom wall side of the connection trench 134 may be formed in a curved shape. Of course, the entire bottom wall of the connection trench 134 may be formed in a curved shape toward the second main surface 103 side.

[0224] The connection insulating film 135 coats the sidewalls and bottom wall of the connection trench 134 in a film-like manner. In this embodiment, the connection insulating film 135 coats the sidewalls and bottom wall on the opening side and bottom wall side of the connection trench 134, and defines a recess space within the connection trench 134. The connection insulating film 135 is integrally connected to the plurality of gate insulating films 127 at the communicating portions with the plurality of first trenches 126.

[0225] The connection insulating film 135 may have a thickness of 5 nm or more and 1000 nm or less. The connection insulating film 135 preferably has a thickness substantially equal to that of the gate insulating film 127. The connection insulating film 135 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The connection insulating film 135 is preferably made of the same material as the gate insulating layer.

[0226] The connection electrode 136 is embedded in the connection trench 134 with the connection insulating film 135 interposed therebetween, and faces the first semiconductor region 121 and the second semiconductor region 122. The connection electrode 136 is connected to the plurality of gate electrodes 128 at the communicating portions with the plurality of first trenches 126. Specifically, the connection electrode 136 is connected to the plurality of lead-out portions 130. As a result, the connection electrode 136 is fixed to the same potential as the gate electrodes 128.

[0227] The portion of the connection electrode 136 that is continuous with the lead-out portion 130 may be included in the components of the connection electrode 136, or may be included in the components of the gate electrode 128. The connection electrode 136 has an upper end that is located on the first main surface 102 side with respect to the upper end of the gate electrode 128. The connection electrode 136 may protrude above the first main surface 102. The connection electrode 136 may be drawn out from the connection trench 134 onto the first main surface 102 with part of the connection insulating film 135 sandwiched therebetween. Of course, the connection electrode 136 may be located on the bottom wall side of the connection trench 134 with respect to the first main surface 102.

[0228] The connection electrode 136 may include at least one of a metal and a non-metal conductor. The connection electrode 136 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The connection electrode 136 is preferably made of the same material as the gate electrode 128.

[0229] 20 , the plurality of trench breakdown withstanding structures 125 are each formed across a pair of first trench structures 123 in the first direction X. Specifically, each trench breakdown withstanding structure 125 crosses each of the first source / drain regions 107 and each of the second source / drain regions 108 from one of the pair of first trench structures 123 to the other, dividing the first source / drain regions 107 and the second source / drain regions 108 at each end.

[0230] As a result, an isolation region 137, in which parts of the first source / drain region 107 and the second source / drain region 108 are separated, is formed between the trench connection structure 124 and the trench breakdown withstanding structure 125. The isolation region 137 is a region surrounded by the pair of first trench structures 123, the trench connection structure 124, and the trench breakdown withstanding structure 125. Due to the formation of the isolation region 137, the first source / drain region 107 and the second source / drain region 108 are separated from the trench connection structure 124 in the second direction Y by the isolation region 137.

[0231] The trench breakdown withstanding structure 125 covers the ends in the second direction Y of the first source / drain region 107 and the second source / drain region 108 that are remote from the trench connection structure 124 .

[0232] The plurality of trench breakdown withstanding structures 125 penetrate the first semiconductor region 121 to reach the second semiconductor region 122. In this embodiment, the plurality of trench breakdown withstanding structures 125 each have a bottom wall located within the second semiconductor region 122.

[0233] The trench breakdown withstanding structure 125 may have a width in the second direction Y of 0.01 μm or more and 10 μm or less (preferably 0.1 μm or more and 2 μm or less). The trench breakdown withstanding structure 125 may have a width approximately equal to the width of the first trench structure 123. The trench breakdown withstanding structures 125 may each have a depth of 0.2 μm or more and 30 μm or less (preferably 0.5 μm or more and 10 μm or less). The trench breakdown withstanding structure 125 may have a depth approximately equal to the depth of the first trench structure 123.

[0234] The trench voltage-resistant structure 125 includes a voltage-resistant trench 138 , a voltage-resistant insulating film 139 , a voltage-resistant electrode 140 and a voltage-resistant insulator 141 .

[0235] The breakdown voltage trench 138 is formed in the first main surface 102 and defines the wall surfaces (side walls and bottom wall) of the trench breakdown voltage structure 125. The wall surfaces (side walls and bottom wall) of the trench breakdown voltage structure 125 are integrally connected to the wall surfaces (side walls and bottom walls) of the multiple first trenches 126. The breakdown voltage trench 138 exposes the first semiconductor region 121 and the second semiconductor region 122 from the wall surfaces.

[0236] The voltage-resistant trench 138 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, the voltage-resistant trench 138 may be formed perpendicular to the first main surface 102. The corners on the bottom wall side of the voltage-resistant trench 138 may be formed in a curved shape. Of course, the entire bottom wall of the voltage-resistant trench 138 may be formed in a curved shape toward the second main surface 103 side.

[0237] The voltage-resistant insulating film 139 coats the sidewalls and bottom wall of the voltage-resistant trench 138 in a film-like manner. In this embodiment, the voltage-resistant insulating film 139 coats the sidewalls and bottom wall on the bottom wall side of the voltage-resistant trench 138 and defines a recess space on the bottom wall side of the voltage-resistant trench 138. The voltage-resistant insulating film 139 is integrally connected to the multiple gate insulating films 127. The voltage-resistant insulating film 139 may have a thickness of 5 nm or more and 1000 nm or less in the normal direction of the wall surface of the voltage-resistant trench 138. It is preferable that the voltage-resistant insulating film 139 have a thickness approximately equal to that of the gate insulating film 127.

[0238] The voltage-resistant insulating film 139 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The voltage-resistant insulating film 139 is preferably made of the same material as the gate insulating layer.

[0239] The voltage-withstanding electrode 140 is embedded in the voltage-withstanding trench 138 with a voltage-withstanding insulating film 139 sandwiched therebetween. Specifically, the voltage-withstanding electrode 140 is embedded in a recess space partitioned by the voltage-withstanding insulating film 139 on the bottom wall side of the voltage-withstanding trench 138, and faces the second semiconductor region 122 with the voltage-withstanding insulating film 139 sandwiched therebetween. The voltage-withstanding electrode 140 is integrally connected to the gate electrode 128. The voltage-withstanding electrode 140 traverses the depth position of the boundary between the first semiconductor region 121 and the second semiconductor region 122 in the depth direction of the voltage-withstanding trench 138.

[0240] The voltage-withstanding electrode 140 may include at least one of a metal and a non-metal conductor. The voltage-withstanding electrode 140 may include at least one of tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The voltage-withstanding electrode 140 preferably includes a non-metal conductor (conductive polysilicon). The conductive polysilicon may be p-type polysilicon or n-type polysilicon. The conductive polysilicon is preferably n-type polysilicon.

[0241] The voltage-withstanding insulator 141 is embedded in the voltage-withstanding trench 138 on the opening side of the voltage-withstanding trench 138 so as to cover the voltage-withstanding electrode 140. Specifically, the voltage-withstanding insulator 141 is embedded in an opening-side recess defined by the voltage-withstanding electrode 140. The voltage-withstanding insulator 141 is provided as a field insulator that relieves the electric field with respect to the voltage-withstanding trench 138. The voltage-withstanding insulator 141 is configured so that the facing area of ​​the voltage-withstanding insulator 141 with respect to the first semiconductor region 121 exceeds the facing area of ​​the voltage-withstanding electrode 140 with respect to the second semiconductor region 122.

[0242] The voltage insulator 141 has a thickness greater than the thickness of the voltage electrode 140 in the depth direction of the voltage trench 138. The voltage insulator 141 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The voltage insulator 141 is preferably made of a silicon oxide film. The voltage insulator 141 is preferably made of the same material as the voltage insulating film 139. In this case, the voltage insulator 141 is preferably made of an insulating vapor-deposited film and has a density different from that of the voltage insulating film 139.

[0243] In the plurality of first mesas 131, the first source / drain regions 107 are formed by the first semiconductor regions 121. First contact regions 142 are formed in the surface layer portions of the first source / drain regions 107. The first contact regions 142 have a higher n-type impurity concentration than the first semiconductor regions 121. The n-type impurity concentration of the first contact regions 142 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３or less (in this form, 1 × 10 １９ cm －３ (degree).

[0244] The first contact region 142 is preferably formed in the center of the corresponding first mesa portion 131 in plan view. The first contact region 142 has a length in the second direction Y that is less than the length of the first trench structure 123, and is formed at a distance inward from both ends of the first trench structure 123. Both ends of the first contact region 142 face the trench breakdown withstanding structure 125 in the second direction Y, with part of the first semiconductor region 121 sandwiched therebetween.

[0245] The first contact region 142 extends in the lateral direction (second direction Y) along the first major surface 102 in a cross-sectional view. Specifically, the first contact region 142 is formed at a depth position on the first major surface 102 side with respect to the upper end of the gate electrode 128. The first contact region 142 faces the buried insulator 129 with a part of the first semiconductor region 121 interposed therebetween in the lateral direction along the first major surface 102. The first contact region 142 is spaced from the upper end of the gate electrode 128 toward the first major surface 102 and does not face the gate electrode 128 in the lateral direction along the first major surface 102. This reduces the electric field applied to the plurality of first trench structures 123.

[0246] The first contact region 142 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The first contact region 142 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 128 in the thickness direction (normal direction Z) of the semiconductor chip 101.

[0247] In the plurality of second mesas 132, the second source / drain regions 108 are formed by the first semiconductor regions 121. Second contact regions 143 are formed in the surface layers of the second source / drain regions 108. The second contact regions 143 have a higher n-type impurity concentration than the first semiconductor regions 121. The n-type impurity concentration of the second contact regions 143 is 1×10 １８ cm －３1x10 or more ２１ cm －３ or less (in this form, 1 × 10 １９ cm －３ (degree).

[0248] The second contact region 143 is preferably formed in the center of the corresponding second mesa portion 132 in plan view. The second contact region 143 has a length in the second direction Y that is less than the length of the first trench structure 123, and is formed at a distance inward from both ends of the first trench structure 123. Both ends of the second contact region 143 face the trench breakdown withstanding structure 125 in the second direction Y, with part of the first semiconductor region 121 sandwiched therebetween.

[0249] The second contact region 143 extends in the lateral direction (second direction Y) along the first major surface 102 in a cross-sectional view. Specifically, the second contact region 143 is formed at a depth position on the first major surface 102 side with respect to the upper end of the gate electrode 128. The second contact region 143 faces the buried insulator 129 with a part of the first semiconductor region 121 interposed therebetween in the lateral direction along the first major surface 102. The second contact region 143 is spaced from the upper end of the gate electrode 128 toward the first major surface 102 and does not face the gate electrode 128 in the lateral direction along the first major surface 102. This reduces the electric field applied to the plurality of first trench structures 123.

[0250] The second contact region 143 may have a thickness of 10 nm to 150 nm (preferably 50 nm to 100 nm). The second contact region 143 is preferably formed at a distance of 0.1 μm to 2 μm (preferably 0.5 μm to 1.5 μm) from the upper end of the gate electrode 128 in the thickness direction (normal direction Z) of the semiconductor chip 101.

[0251] In the multiple drift mesas 133, the drift region 109 is formed by the first semiconductor region 121. In this embodiment, the drift region 109 is formed by the first semiconductor region 121 over the entire area from a boundary 144 between the first semiconductor region 121 and the second semiconductor region 122 to the first main surface 102. The width of the drift region 109 in the first direction X is narrower than the width of the drift region 21 in the first embodiment. For example, the width of the drift region 21 is not less than 0.2 μm and not more than 10 μm, whereas the width of the drift region 109 is not less than 0.01 μm and not more than 0.3 μm.

[0252] The wiring region 111 is formed by the first semiconductor region 121 between adjacent cell regions 110. The wiring region 111 is integrally connected to the end of the drift region 109 in the second direction Y.

[0253] In the wiring region 111, a p-type protrusion 145 is formed, which selectively protrudes from the second semiconductor region 122 toward the first main surface 102 and into the first semiconductor region 121. Referring to FIG. 24 , the protrusion 145 may extend upward in a parabolic shape from a boundary 144 between the first semiconductor region 121 and the second semiconductor region 122 and have an apex near the first main surface 102. In this embodiment, the protrusion 145 has an apex at a position away from the first main surface 102 toward the second main surface 103. A part of the wiring region 111 (drift region 109) may be formed between the apex of the protrusion 145 and the first main surface 102. Referring to FIG. 20 , the protrusion 145 is formed in a strip shape extending in the first direction X. Because the protrusion 145 is formed in the wiring region 111 (in this embodiment, a region where a current path 185 (described later) is not formed), the protrusion 145 can be formed in a strip shape. This makes it possible to form a contact for the substrate potential at any position in the wiring region 111. Of course, a plurality of protruding portions 145 may be arranged at intervals in the first direction X.

[0254] The protruding portion 145 has a higher p-type impurity concentration than the second semiconductor region 122. The p-type impurity concentration of the protruding portion 145 is 1×10 １６ cm －３ 1x10 or more ２２ cm －３or less (in this form, 1 x 10 １９ cm －３ (degree).

[0255] First impurity regions 146 are further formed in the plurality of isolation regions 137 and the wiring region 111. The first impurity regions 146 are omitted in FIG. 20 . The first impurity regions 146 are formed in contact with the tops of the protruding portions 145 in the surface layer portion of the first main surface 102. The first impurity regions 146 have a higher n-type impurity concentration than the first semiconductor region 121. The n-type impurity concentration of the first impurity regions 146 is 1×10 １５ cm －３ 1x10 or more ２０ cm －３ or less (in this form, 1 × 10 １８ cm －３ (degree).

[0256] The semiconductor device 1B includes a main surface insulating film 147 that selectively covers the first main surface 102. The main surface insulating film 147 may be part of the insulating layer 9 described above. The main surface insulating film 147 covers the first trench structures 123, the trench connection structures 124, and the trench breakdown withstanding structures 125 on the first main surface 102. In this embodiment, the main surface insulating film 147 covers the entire first main surface 102 and is continuous with the first to fourth side surfaces 104A to 104D.

[0257] The main surface insulating film 147 may have a thickness of 0.1 μm or more and 2 μm or less. The thickness of the main surface insulating film 147 preferably exceeds the thickness of the gate insulating film 127. The main surface insulating film 147 includes at least one of a silicon oxide film, a silicon nitride film, an aluminum oxide film, a zirconium oxide film, a hafnium oxide film, and a tantalum oxide film. The main surface insulating film 147 is preferably made of a silicon oxide film.

[0258] In this embodiment, the main surface insulating film 147 is made of the same material as the buried insulators 129 and the voltage-resistant insulators 141, and is formed integrally with the buried insulators 129 and the voltage-resistant insulators 141. That is, the main surface insulating film 147 extends from above the first main surface 102 into the plurality of first trenches 126 and the voltage-resistant trenches 138 as part of the buried insulators 129 and the voltage-resistant insulators 141. In other words, the main surface insulating film 147 is made of an insulating film in which the portions of the plurality of buried insulators 129 protruding from the plurality of first trenches 126 and the portions of the plurality of voltage-resistant insulators 141 protruding from the plurality of voltage-resistant trenches 138 are integrated into a film shape on the first main surface 102.

[0259] The semiconductor device 1B includes a plurality of first electrodes 148 electrically connected to the first semiconductor region 121 in the plurality of first mesas 131. In this embodiment, the plurality of first electrodes 148 are provided as "first lower contacts." The plurality of first electrodes 148 penetrate the main surface insulating film 147 and are connected to the plurality of first mesas 131, respectively. Specifically, the plurality of first electrodes 148 are respectively arranged in a plurality of first connection openings 149 formed in the main surface insulating film 147.

[0260] Each of the plurality of first electrodes 148 is made of metal. In this embodiment, each of the plurality of first electrodes 148 has a layered structure including a first barrier film 150 and a first electrode body 151. The first barrier film 150 is formed in a film shape along the inner wall of the first connection opening 149. The first barrier film 150 may be made of a titanium-based metal film. The first barrier film 150 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film.

[0261] The first electrode body 151 is embedded in the first connection opening 149 with the first barrier film 150 sandwiched therebetween, and is electrically connected to the first mesa portion 131 (first contact region 142) with the first barrier film 150 sandwiched therebetween. The first electrode body 151 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the first electrode body 151 contains tungsten. Of course, the multiple first electrodes 148 may be formed only by the first electrode body 151 without having the first barrier film 150.

[0262] The semiconductor device 1B includes a plurality of second electrodes 152 electrically connected to the first semiconductor region 121 in the plurality of second mesas 132. In this embodiment, the plurality of second electrodes 152 are provided as "second lower contacts." The plurality of second electrodes 152 penetrate the main surface insulating film 147 and are connected to the plurality of second mesas 132, respectively. Specifically, the plurality of second electrodes 152 are respectively arranged in a plurality of second connection openings 153 formed in the main surface insulating film 147.

[0263] Each of the multiple second electrodes 152 is made of metal. In this embodiment, each of the multiple second electrodes 152 has a layered structure including a second barrier film 154 and a second electrode body 155. The second barrier film 154 is formed in a film shape along the inner wall of the second connection opening 153. The second barrier film 154 may be made of a titanium-based metal film. The second barrier film 154 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film.

[0264] The second electrode body 155 is embedded in the second connection opening 153 with the second barrier film 154 sandwiched therebetween, and is electrically connected to the second mesa portion 132 (second contact region 143) with the second barrier film 154 sandwiched therebetween. The second electrode body 155 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. In this embodiment, the second electrode body 155 contains tungsten. Of course, the multiple second electrodes 152 may be formed only by the second electrode body 155 without the second barrier film 154.

[0265] The semiconductor device 1B includes a plurality of second trench structures 156 formed in the first main surface 102 in the wiring region 111 .

[0266] In this embodiment, the multiple second trench structures 156 are arranged at intervals in the first direction X. For example, if the multiple protrusions 145 are formed at intervals in the first direction X, the multiple second trench structures 156 may be formed in a one-to-one correspondence with each protrusion 145. Each second trench structure 156 is arranged in a position facing each drift region 109 near the end of each drift region 109 in the second direction Y. In this embodiment, the second trench structures 156 are arranged adjacent to each other at both ends of the drift region 109 in the second direction Y.

[0267] The second trench structure 156 is formed to reach the protruding portion 145. In this embodiment, the second trench structure 156 is formed shallower than the first trench structure 123. Specifically, the second trench structure 156 penetrates the first impurity region 146 and reaches the protruding portion 145. The second trench structure 156 has a bottom wall located within the protruding portion 145.

[0268] The width of the second trench structure 156 may be equal to or greater than the width of the first trench structure 123, or may be less than the width of the first trench structure 123. The second trench structure 156 may have a depth of 0.1 μm to 10 μm (preferably 0.2 μm to 0.5 μm). This depth allows a silicide layer 162 (described below) to be formed over the entire second trench structure 156.

[0269] The second trench structure 156 includes a base trench 157 and a base electrode 158. The base electrode 158 is provided as a "first base contact 120" in this embodiment.

[0270] The base trench 157 is formed in the first main surface 102, penetrating the main surface insulating film 147, and defines the wall surfaces (sidewalls and bottom wall) of the second trench structure 156. In this embodiment, the base trench 157 includes a base connection opening 159 formed in the main surface insulating film 147. Specifically, the base trench 157 penetrates the main surface insulating film 147 and the first impurity region 146 to reach the protruding portion 145. The base trench 157 exposes the first impurity region 146 and the protruding portion 145 from the wall surfaces.

[0271] The base trench 157 may be formed in a tapered shape in which the opening width narrows from the first main surface 102 side toward the bottom wall side in a cross-sectional view. Of course, the base trench 157 may be formed perpendicular to the first main surface 102. The corners on the bottom wall side of the base trench 157 may be formed in a curved shape. Of course, the entire bottom wall of the base trench 157 may be formed in a curved shape toward the second main surface 103 side.

[0272] The base electrode 158 is buried in the base trench 157 without an insulating film therebetween. The base electrode 158 is mechanically and electrically connected to the first impurity region 146 and the protruding portion 145 within the base trench 157, and is mechanically connected to the main surface insulating film 147. Within the base trench 157, the base electrode 158 has a portion located on the semiconductor chip 101 side with respect to the first main surface 102, and a portion located on the main surface insulating film 147 side with respect to the first main surface 102. In other words, the base electrode 158 has an upper end portion that protrudes above the first main surface 102. Furthermore, the upper end portion of the base electrode 158 protrudes above the upper end portion of the gate electrode 128 (the upper end portion of the drawn portion 130).

[0273] The base electrode 158 may include at least one of a metal and a non-metal conductor. The base electrode 158 is preferably formed of a conductive material different from that of the gate electrode 128. The base electrode 158 preferably includes a metal. In this embodiment, the base electrode 158 has a layered structure including a base barrier film 160 and a base electrode body 161.

[0274] The base barrier film 160 is formed in a film shape along the sidewalls and bottom wall of the base trench 157, and covers the first impurity region 146, the protruding portion 145, and the main surface insulating film 147 within the base trench 157. The base barrier film 160 defines a recess space within the base trench 157. The base barrier film 160 may be made of a titanium-based metal film. The base barrier film 160 may have a single-layer structure or a multilayer structure including either or both of a titanium film and a titanium nitride film. The base barrier film 160 is preferably made of the same material as the first barrier film 150 and the second barrier film 154.

[0275] The base electrode body 161 is buried in the base trench 157 with the base barrier film 160 sandwiched therebetween, and covers the first impurity region 146, the protruding portion 145, and the main surface insulating film 147 with the base barrier film 160 sandwiched therebetween. The base electrode body 161 is electrically connected to the first impurity region 146 and the protruding portion 145 via the base barrier film 160. The base electrode body 161 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The base electrode body 161 is preferably made of the same material as the first electrode body 151 and the second electrode body 155. In this embodiment, the base electrode body 161 contains tungsten. Of course, the base electrode 158 may be formed only by the base electrode body 161 without the base barrier film 160.

[0276] A silicide layer 162 is formed on the inner wall of the base trench 157. The silicide layer 162 is formed over the entire sidewall and bottom wall of the base trench 157 at the boundary between the semiconductor chip 101 and the base barrier film 160. The silicide layer 162 may cross the boundary between the first impurity region 146 and the protruding portion 145 in the thickness direction of the semiconductor chip 101 from top to bottom.

[0277] If the silicide layer 162 is formed over the entire sidewall and bottom wall of the base trench 157, the surface condition of the inner wall of the base trench 157 can be improved and smoothed, thereby achieving good contact between the base electrode body 161 and the base trench 157. This allows the contact resistance of the base electrode body 161 to be reduced.

[0278] The semiconductor device 1B includes a plurality of third electrodes 163 electrically connected to the plurality of first trench structures 123. The plurality of third electrodes 163 are provided as "first gate contacts 117." The plurality of third electrodes 163 penetrate the main surface insulating film 147 and are mechanically and electrically connected to either or both of the plurality of first trench structures 123 (lead-out portions 130) and the plurality of trench connection structures 124 (connection electrodes 136).

[0279] Specifically, the multiple third electrodes 163 are respectively disposed in multiple third connection openings 164 formed in the main surface insulating film 147. In this embodiment, the multiple third electrodes 163 are mechanically and electrically connected to the multiple trench connection structures 124. That is, the multiple third electrodes 163 are electrically connected to the multiple first trench structures 123 via the multiple trench connection structures 124.

[0280] In this embodiment, the third electrodes 163 are formed to correspond to the trench connection structures 124 in a plan view. The third electrodes 163 may have any planar shape. The third electrodes 163 may be formed in a circular or rectangular shape in a plan view.

[0281] Each of the multiple third electrodes 163 is made of metal. In this embodiment, each of the multiple third electrodes 163 has a layered structure including a third barrier film 165 and a third electrode body 166. The third barrier film 165 is formed in a film shape along the inner wall of the third connection opening 164. The third barrier film 165 may be made of a titanium-based metal film. The third barrier film 165 may have a single-layer structure or a layered structure including either or both of a titanium film and a titanium nitride film. The third barrier film 165 is preferably made of the same material as the first barrier film 150, the second barrier film 154, and the base barrier film 160.

[0282] The third electrode body 166 is embedded in the third connection opening 164 with the third barrier film 165 sandwiched therebetween and is electrically connected to the lead portion 130 (connection electrode 136) with the third barrier film 165 sandwiched therebetween. The third electrode body 166 may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy. The third electrode body 166 is preferably made of the same material as the first electrode body 151. In this embodiment, the third electrode body 166 contains tungsten. Of course, the multiple third electrodes 163 may be composed only of the third electrode body 166 without having the third barrier film 165.

[0283] The semiconductor device 1B includes a p-type bottom wall impurity region 167 formed in a region along the bottom wall of the first trench structure 123 in the second semiconductor region 122. In this embodiment, the bottom wall impurity region 167 is formed in the second semiconductor region 122 and has a higher p-type impurity concentration than the second semiconductor region 122. The p-type impurity concentration of the bottom wall impurity region 167 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ or less (in this form, 1 × 10 １７ cm －３ (degree).

[0284] The bottom wall impurity region 167 is formed in a strip shape extending along the bottom wall of the first trench structure 123 at intervals from the plurality of second trench structures 156 in a plan view. The bottom wall impurity region 167 faces the gate electrode 128 on the bottom wall of the first trench structure 123, with the gate insulating film 127 interposed therebetween. The bottom wall impurity region 167 may cover the bottom wall and sidewall of the first trench structure 123 at the lower end of the first trench structure 123.

[0285] The bottom wall impurity region 167 may cover the bottom wall of the trench connection structure 124 in the second semiconductor region 122. In this case, the bottom wall impurity region 167 may be formed in a strip shape extending along the bottom wall of the trench connection structure 124 in a plan view. Of course, the bottom wall impurity region 167 may expose the bottom wall of the trench connection structure 124.

[0286] The bottom wall impurity region 167 may cover the bottom wall of the trench breakdown withstanding structure 125 in the second semiconductor region 122. In this case, the bottom wall impurity region 167 may be formed in a strip shape extending along the bottom wall of the trench breakdown withstanding structure 125 in a plan view. Of course, the bottom wall impurity region 167 may expose the bottom wall of the trench breakdown withstanding structure 125.

[0287] The bottom wall impurity region 167 may have a thickness of 10 nm or more and 500 nm or less. The thickness of the bottom wall impurity region 167 is preferably 100 nm or more and 300 nm or less. The thickness of the bottom wall impurity region 167 is the distance between the bottom wall of the first trench structure 123 and the bottom of the bottom wall impurity region 167. The bottom wall impurity region 167 has a width in the first direction X that exceeds the width of the bottom wall of the first trench structure 123. The width of the bottom wall impurity region 167 is defined by the width of the most protruding region in the bottom wall impurity region 167. The width of the bottom wall impurity region 167 may exceed the opening width of the first trench structure 123. The width of the bottom wall impurity region 167 may be 0.1 μm or more and 0.5 μm or less.

[0288] The semiconductor device 1B includes a first interlayer insulating film 168 stacked on the main surface insulating film 147. The first interlayer insulating film 168 may be part of the insulating layer 9 described above. The first interlayer insulating film 168 may include at least one of silicon oxide and silicon nitride. The first interlayer insulating film 168 covers the entire main surface insulating film 147 and is continuous with the first to fourth side surfaces 104A to 104D. The first interlayer insulating film 168 may have a flat surface extending along the first main surface 102. The flat surface of the first interlayer insulating film 168 may have grinding marks.

[0289] A first wiring layer 112 is formed on the first interlayer insulating film 168. The first wiring layer 112 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The first wiring layer 112 may contain at least one of a Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0290] As described above, the first wiring layer 112 includes a first gate wiring layer 113 and a first base wiring layer 114. Referring to Figure 21, one of a pair of first gate wiring layers 113 (gate branch portions 116) extending in the first direction X through the wiring region 111 is connected to the connection electrode 136 of the cell region 110 on one side of the wiring region 111. The other of the pair of first gate wiring layers 113 (gate branch portions 116) is connected to the third electrode 163 (connection electrode 136) of the cell region 110 on the other side of the wiring region 111. In this embodiment, the first gate wiring layer 113 is arranged to cover the trench connection structure 124 but not to cover the trench breakdown withstanding structure 125 in a plan view.

[0291] The first base wiring layer 114 extends in the first direction X through the wiring region 111 and is connected to a plurality of base electrodes 158 (first base contacts 120). In this embodiment, as shown in FIG. 19 , the plurality of first base contacts 120 are disposed below the base periphery 118 and the base branch portion 119 and are connected to the base periphery 118 and the base branch portion 119.

[0292] The first wiring layer 112 further includes a first lower wiring layer 169 and a second lower wiring layer 170. Referring to Fig. 22, the first lower wiring layer 169 penetrates the first interlayer insulating film 168 and is connected to the first electrode 148, and the second lower wiring layer 170 penetrates the first interlayer insulating film 168 and is connected to the second electrode 152.

[0293] The semiconductor device 1B includes a second interlayer insulating film 171 stacked on the first interlayer insulating film 168 so as to cover the first wiring layer 112. The second interlayer insulating film 171 may be part of the insulating layer 9 described above. The second interlayer insulating film 171 may include at least one of silicon oxide and silicon nitride. The second interlayer insulating film 171 covers the entire first interlayer insulating film 168 and is continuous with the first to fourth side surfaces 104A to 104D. The second interlayer insulating film 171 may have a flat surface extending along the first main surface 102. The flat surface of the second interlayer insulating film 171 may have grinding marks.

[0294] A second wiring layer 172 is formed on the second interlayer insulating film 171. The second wiring layer 172 may contain at least one of titanium, tungsten, aluminum, copper, an aluminum alloy, a copper alloy, and conductive polysilicon. The second wiring layer 172 may contain at least one of a Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0295] The second wiring layer 172 includes a first upper wiring layer 173, a second upper wiring layer 174, a second gate wiring layer (not shown), and a second base wiring layer (not shown). The first upper wiring layer 173 is connected to the first lower wiring layer 169 through the second interlayer insulating film 171. The second upper wiring layer 174 is connected to the second lower wiring layer 170 through the second interlayer insulating film 171. The second gate wiring layer is connected to the first gate wiring layer 113 through the second interlayer insulating film 171. The second base wiring layer is connected to the first base wiring layer 114 through the second interlayer insulating film 171.

[0296] The semiconductor device 1B includes a top insulating film 175 formed on the second interlayer insulating film 171. The top insulating film 175 may be part of the insulating layer 9 described above. The top insulating film 175 may also be referred to as a "passivation film." The top insulating film 175 may have a layered structure including an inorganic insulating film (inorganic film) and an organic insulating film (organic film) stacked in this order from the second interlayer insulating film 171 side. Of course, the top insulating film 175 may have a single-layer structure consisting of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film is preferably made of an insulating material different from that of the second interlayer insulating film 171. The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0297] Similar to the first embodiment, a plurality of external terminals 4 to 7 are formed on the uppermost insulating film 175 .

[0298] The semiconductor device 1B includes a back surface protective film 176 that covers the second main surface 103 of the semiconductor chip 101. In this embodiment, the back surface protective film 176 covers the entire second main surface 103 and also covers the first to fourth side surfaces 104A to 104D. The back surface protective film 176 may have a single-layer structure made of an inorganic insulating film (inorganic film) or an organic insulating film (organic film). The inorganic insulating film may be made of, for example, a silicon nitride film. The organic insulating film may be made of a photosensitive resin. The organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0299] 22 , the semiconductor device 1B includes a first pn junction 177 and a second pn junction 178, each formed inside the semiconductor chip 101. The first pn junction 177 is formed at the boundary between the first semiconductor region 121 and the second semiconductor region 122 on the first mesa portion 131 side. As a result, a first body diode D1 is formed in the first mesa portion 131, the first body diode D1 including the second semiconductor region 122 as an anode region and the first semiconductor region 121 as a cathode region.

[0300] The second pn junction 178 is formed at the boundary between the first semiconductor region 121 and the second semiconductor region 122 on the second mesa 132 side. As a result, a second body diode D2 including the second semiconductor region 122 as an anode region and the first semiconductor region 121 as a cathode region is formed in the second mesa 132. The anode of the second body diode D2 (second pn junction 178) is electrically connected to the anode of the first body diode D1 (first pn junction 177) via the second semiconductor region 122.

[0301] (2) Manufacturing Process of Semiconductor Device 1B Next, an example of a manufacturing method of semiconductor device 1B will be described. Figures 25A to 25J are cross-sectional views showing an example of a manufacturing method of semiconductor device 1B shown in Figure 1. Figures 25A to 25J are all cross-sectional views of the region corresponding to Figure 24.

[0302] 25A , a disk-shaped wafer 179 is prepared. The wafer 179 includes a first wafer main surface 180 on one side and a second wafer main surface 181 on the other side. The wafer 179 is made of a p-type semiconductor substrate entirely formed of a second semiconductor region 122. Next, the first semiconductor region 121 is formed in a surface layer portion of the first wafer main surface 180. The first semiconductor region 121 is formed by introducing n-type impurities into the surface layer portion of the first wafer main surface 180 by ion implantation. The n-type impurities may be introduced into the entire surface layer portion of the first wafer main surface 180 without using an ion implantation mask.

[0303] Of course, the n-type impurity may be introduced via an ion implantation mask into a region in the surface layer of the first wafer main surface 180 where the first semiconductor region 121 is to be formed. Alternatively, the first semiconductor region 121 may be formed by growing silicon from the second semiconductor region 122 (semiconductor substrate) by epitaxial growth. In this case, the first wafer main surface 180 is formed by the crystal plane (crystal growth plane) of the first semiconductor region 121.

[0304] Referring to FIG. 25B , a plurality of first trenches 126, a plurality of connection trenches 134, and a plurality of breakdown-resistant trenches 138 are formed on the first wafer main surface 180. In this process, unnecessary portions of the wafer 179 are selectively removed by etching using a hard mask (not shown). The etching may be wet etching and / or dry etching. The etching is preferably RIE (Reactive Ion Etching), an example of a dry etching method. This results in the formation of a plurality of first trenches 126, a plurality of connection trenches 134, and a plurality of breakdown-resistant trenches 138. Furthermore, a plurality of mesas 131 to 133 are defined on the first wafer main surface 180 by the plurality of first trenches 126 (a plurality of connection trenches 134). The hard mask is then removed.

[0305] 25C , a first base insulating film 182 that serves as a base for the plurality of gate insulating films 49, the plurality of connection insulating films 57, and the plurality of voltage-breaking insulating films 139 is formed on the first wafer main surface 180. The first base insulating film 182 is formed on the first wafer main surface 180 including the inner walls of the plurality of first trenches 126, the inner walls of the plurality of connection trenches 134, and the inner walls of the plurality of voltage-breaking trenches 138. The first base insulating film 182 may be formed by an oxidation process and / or a CVD process (preferably a thermal oxidation process).

[0306] 25D , a plurality of bottom wall impurity regions 167 are formed in the second semiconductor region 122 in regions along the bottom walls of the plurality of first trenches 126 and the bottom walls of the plurality of connection trenches 134. Concurrently, protrusions 145 are selectively formed in the wiring region 111. In this step, first, an ion implantation mask (not shown) having a predetermined pattern is formed on the first wafer main surface 180. Next, p-type impurities are selectively introduced into the second semiconductor region 122 by ion implantation via the ion implantation mask. This forms a plurality of bottom wall impurity regions 167 and protrusions 145. The ion implantation mask is then removed.

[0307] 25E , a plurality of first contact regions 142, a plurality of second contact regions 143, and a plurality of first impurity regions 146 are formed. In this step, first, an ion implantation mask (not shown) having a predetermined pattern is formed on the first wafer main surface 180. Next, n-type impurities are selectively introduced into the first semiconductor region 121 by ion implantation via the ion implantation mask. This forms a plurality of first contact regions 142, a plurality of second contact regions 143, and a plurality of first impurity regions 146. The ion implantation mask is then removed.

[0308] 25F , a first base electrode (not shown) serving as a base for the plurality of gate electrodes 128, the plurality of lead portions 130, the plurality of connection electrodes 136, and the plurality of voltage-withstanding electrodes 140 is formed on the first wafer main surface 180. The first base electrode is formed in the form of a film so as to fill the plurality of first trenches 126, the plurality of connection trenches 134, and the plurality of voltage-withstanding trenches 138 and to cover the first wafer main surface 180. In this embodiment, the first base electrode includes conductive polysilicon. The first base electrode may be formed by a CVD method. Next, unnecessary portions of the first base electrode are removed. This results in the formation of the plurality of gate electrodes 128, the plurality of lead portions 130, the plurality of connection electrodes 136, and the plurality of voltage-withstanding electrodes 140.

[0309] 25G , a second base insulating film 183 that serves as a base for buried insulator 129, breakdown insulator 141, and main surface insulating film 147 is formed on first wafer main surface 180. In this embodiment, second base insulating film 183 is made of a silicon oxide film. Second base insulating film 183 may be formed by a CVD method. The CVD method for second base insulating film 183 is preferably a high density plasma (HDP)-CVD method.

[0310] The second base insulating film 183 fills recess spaces defined by the plurality of lead portions 130 in the plurality of first trenches 126 and the plurality of voltage-resistant trenches 138, and covers the first wafer main surface 180, the plurality of lead portions 130, the plurality of voltage-resistant electrodes 140, and the connection electrodes 136. This forms the buried insulator 129 located in the first trench 126, the voltage-resistant insulator 141 located in the voltage-resistant trench 138, and the main surface insulating film 147 located on the first wafer main surface 180.

[0311] 25H , a plurality of first connection openings 149, a plurality of second connection openings 153, a plurality of third connection openings 164, and a plurality of base trenches 157 (base connection openings 159) are formed in the first wafer main surface 180. In this process, a resist mask (not shown) having a predetermined pattern is first formed on the main surface insulating film 147. Next, unnecessary portions of the main surface insulating film 147 are selectively removed by etching via the resist mask. The etching method may be wet etching and / or dry etching (preferably RIE). As a result, a plurality of first connection openings 149, a plurality of second connection openings 153, a plurality of third connection openings 164, and a plurality of base connection openings 159 are formed in the main surface insulating film 147.

[0312] Next, unnecessary portions of the wafer 179 are removed by etching through the resist mask. The etching may be wet etching and / or dry etching (preferably RIE). The unnecessary portions of the wafer 179 are removed until they penetrate the first impurity region 146 and expose the protruding portion 145. This forms a plurality of base trenches 157, each including a base connection opening 159, in the first wafer main surface 180. The resist mask is then removed.

[0313] Referring to FIG. 25I , a second base electrode (not shown) serving as a base for the plurality of first electrodes 148, the plurality of second electrodes 152, the plurality of base electrodes 158, and the plurality of third electrodes 163 is formed on the main surface insulating film 147. In this embodiment, the second base electrode includes a base barrier film and an electrode body film stacked in this order from the wafer 179 side. Next, unnecessary portions of the second base electrode are selectively removed by etching. The etching may be wet etching and / or dry etching (preferably RIE). The second base electrode is removed until the main surface insulating film 147 is exposed. This results in the formation of the plurality of first electrodes 148, the plurality of second electrodes 152, the plurality of base electrodes 158, and the plurality of third electrodes 163. After the formation of these electrodes, a silicide layer 162 is formed on the inner wall of the base trench 157 by annealing (e.g., at a temperature of 500° C. or higher and 1100° C. or lower).

[0314] 25J, first interlayer insulating film 168, first wiring layer 112, second interlayer insulating film 171, second wiring layer 172, top insulating film 175, back surface protective film 176, and external terminals 4 to 7 are formed, and wafer 179 is selectively cut in the thickness direction. Through the steps including those described above, semiconductor device 1B is manufactured.

[0315] (3) Operation and Technical Effects of Semiconductor Device 1B Fig. 26 is a cross-sectional view showing a current path of semiconductor device 1B according to the second embodiment of the present disclosure. Fig. 27 is a plan view showing a current path of semiconductor device 1B according to the second embodiment of the present disclosure.

[0316] The semiconductor device 1B has a trench-gate lateral MISFET structure. In this MISFET structure, a gate potential is applied to the first trench structure 123 (gate electrode 128), a drain potential is applied to the first mesa portion 131, and a source potential is applied to the second mesa portion 132. As a result, a channel 184 is formed in the second semiconductor region 122 in a region below the first trench structure 123, and a lateral current path 185 is formed connecting the first electrode 148 (first mesa portion 131) and the second electrode 152 (second mesa portion 132).

[0317] As shown in FIG. 26 , the current path 185 is a path through which current flows in the following order: first mesa portion 131 (first semiconductor region 121) → bottom wall impurity region 167 (high-concentration p-type region) → drift mesa portion 133 (first semiconductor region 121) → bottom wall impurity region 167 (high-concentration p-type region) → second mesa portion 132 (first semiconductor region 121). In other words, the current path 185 is hardly formed in the second semiconductor region 122. Therefore, even if the semiconductor chip 101 is formed using a single structure of a semiconductor substrate with high resistance (in this embodiment, 10 Ω·cm or more and 100 Ω·cm or less), an increase in the on-resistance of the semiconductor device 1B can be suppressed. As a result, there is no need to form an epitaxial layer on the wafer 179 during the manufacturing process of the semiconductor device 1B, which simplifies the manufacturing process and reduces materials and costs.

[0318] 27 , in the semiconductor device 1B, the base electrode 158 for fixing the potential (substrate potential) of the second semiconductor region 122 is formed in a wiring region 111 that is separated in the second direction Y from the drift region 109 in which the current path 185 is formed, and is not formed in the drift region 109. This allows the current path 185 that connects the first electrode 148 and the second electrode 152 over the shortest distance to be formed throughout the entire drift region 109. In other words, by separately arranging the wiring region 111 for fixing the substrate potential and the drift region 109 for the current path 185, the on-resistance can be reduced.

[0319] Furthermore, because no space for the base electrode 158 is required in the drift region 109, the width of the drift region 109 in the first direction X can be narrowed. This reduces the resistance value of each drift region 109 and increases the number of cells arranged in one cell region 110. As a result, the on-resistance can be reduced.

[0320] 24 , the contact region 61 has a protrusion 59 extending toward the first major surface 10. This allows the contact point with the second semiconductor region 122 to be raised toward the first major surface 10 beyond the boundary 144 between the first semiconductor region 121 and the second semiconductor region 122. Therefore, there is no need to form a second trench structure 156 that reaches the boundary 144, and the substrate potential can be fixed by the relatively shallow second trench structure 156. Because the base trench 157 can be shallow, contact with the substrate potential can be ensured with a simple structure.

[0321] 24 , for example, if the second trench structure 156 has a depth reaching the second main surface 103 side beyond the boundary portion 144, the silicide layer 162 may be formed only locally on the inner wall of the base trench 157. Specifically, the silicide layer 162 may be formed locally on the bottom wall and the upper end of the sidewall of the base trench 157, and not on other portions of the inner wall. In contrast, in the structure shown in FIG. 24 , the base trench 157 is shallow, so the silicide layer 162 can be formed over the entire second trench structure 156. This can improve the smoothness of the surface condition of the inner wall of the base trench 157, thereby achieving good contact between the base electrode body 161 and the base trench 157. This can reduce the contact resistance of the base electrode body 161.

[0322] Because the wiring region 111 for fixing the substrate potential is formed in the active region 105, there is no need to form a peripheral structure for fixing the substrate potential in the peripheral region 106. This allows the area of ​​the peripheral region 106 to be narrowed and the area of ​​the active region 105 to be enlarged. As a result, the current characteristics of the semiconductor device 1B can be improved. For example, in the semiconductor device 1B, the occupancy rate of the active region 105 on the first main surface 102 may be 10% or more and 99.9% or less.

[0323] Furthermore, the ends of the first source / drain region 107 and the second source / drain region 108 in the second direction Y are separated by the trench breakdown structure 125. As a result, the trench breakdown structure 125 is interposed between the first source / drain region 107 and the second source / drain region 108 and the trench connection structure 124, and therefore the breakdown voltage in the lateral direction along the first main surface 102 of the semiconductor device 1B can be improved.

[0324] 28 and 29 show a reference example in which the trench breakdown withstanding structure 125 is not formed in the semiconductor device 1B. Figures 30 and 31 are enlarged views of the vicinity of the trench breakdown withstanding structure 125. The lateral breakdown withstanding voltage of the first source / drain region 107 will be described with reference to Figures 28 to 31, but the lateral breakdown withstanding voltage of the second source / drain region 108 also applies in principle to the same.

[0325] In this reference example, in a region adjacent to the first source / drain region 107, the connection electrode 136 of the trench connection structure 124 is pulled up to the first main surface 102. Therefore, the lateral breakdown voltage along the first main surface 102 depends on the distance L1 between the first contact region 142 and the connection electrode 136. Therefore, in order to improve the lateral breakdown voltage, it is necessary to ensure a large distance L1.

[0326] For example, as shown in FIG. 29 , the distance between the first contact region 142 and the connection electrode 136 can be set to a distance L2, which is greater than the distance L1 shown in FIG. 28 , to ensure a lateral breakdown voltage. Alternatively, as shown in FIG. 30 , the lateral breakdown voltage can be ensured by ensuring the distance L2 and forming a p-type breakdown voltage impurity region 186 in a portion of the surface layer of the first main surface 102. However, in the structures shown in FIGS. 29 and 30 , widening the distance L2 increases unnecessary space in the cell region 110, which may increase the on-resistance. Furthermore, the structure shown in FIG. 30 requires an additional mask to perform the impurity implantation step, which increases the number of steps in the manufacturing process.

[0327] 31 , if a trench breakdown structure 125 is interposed between the first source / drain region 107 and the trench connection structure 124, the electric field can be alleviated by the trench breakdown structure 125. This ensures a sufficient lateral breakdown voltage even if the distance L3 between the first contact region 142 and the connection electrode 136 is short. For example, in a structure in which the trench breakdown structure 125 is formed, the distance L3 may be 0.1 μm or more and 0.4 μm or less.

[0328] Also, unlike the voltage-resistant impurity region 186 that diffuses laterally by annealing, this is a measure using the trench voltage-resistant structure 125 that is formed by etching the semiconductor chip 101 in the vertical direction, so it is possible to reduce unnecessary space in the cell region 110. Furthermore, since the trench voltage-resistant structure 125 and the first trench structure 123 can be formed in the same process, it is also possible to suppress increases in manufacturing process costs.

[0329] The trench voltage-resistant structure 125 may have the same structure as the first trench structure 123, as shown in Figures 24 and 31, or may have a structure in which a voltage-resistant insulator 141 is buried throughout the voltage-resistant trench 138 without having a voltage-resistant electrode 140, as shown in Figure 32.

[0330] (5) Modifications of Semiconductor Device 1B Next, modifications of the semiconductor device 1B will be described with reference to FIGS.

[0331] FIG. 33 is a cross-sectional view showing a first modified example of the semiconductor device 1B according to the second embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG.

[0332] 19, the plurality of first gate contacts 117 and the plurality of first base contacts 120 are arranged at intervals in the first direction X. In contrast to this, as shown in FIG. 33, one first gate contact 117 and one first base contact 120 may be formed to cross regions near each end of the plurality of first source / drain regions 107 and the plurality of second source / drain regions 108.

[0333] FIG. 34 is a cross-sectional view showing a second modification of the semiconductor device 1B according to the second embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG.

[0334] The protruding portion 145 may extend from the second semiconductor region 122 through the first semiconductor region 121 and reach the first main surface 102. As a result, the protruding portion 145 may have a top portion 187 exposed from the first main surface 102 in the wiring region 111. In this case, the base electrode 158 does not have to be formed as the second trench structure 156. The base electrode 158 may be embedded in the base connection opening 159 and have a bottom portion on the first main surface 102. As a result, the base electrode 158 is connected to the protruding portion 145 on the first main surface 102. With this configuration, the step of forming the second trench structure 156 can be omitted, thereby simplifying the manufacturing process and reducing materials and costs.

[0335] FIG. 35 is a cross-sectional view showing a third modified example of the semiconductor device 1B according to the first embodiment of the present disclosure, and is a cross-sectional view corresponding to FIG. 24 .

[0336] 35 , the second trench structure 156 may be deeper than the first trench structure 123. Specifically, a base trench 157 deeper than the first trench 126 may cross the boundary portion 144 and reach the second semiconductor region 122. This makes it possible to omit the step of forming the protrusion 145, thereby simplifying the manufacturing process and reducing materials and costs.

[0337] Although not shown, in the semiconductor device 1B, similar to the semiconductor device 1A shown in Figure 18, the back surface protective film 176 may not be formed on the second main surface 103 of the semiconductor chip 101, and the second main surface 103 may be an exposed surface.

[0338] Although multiple embodiments of the present disclosure have been described above, each embodiment can be implemented in other forms. For example, in the above-described embodiments, an example was described in which the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type." However, a structure in which the "first conductivity type" is "p-type" and the "second conductivity type" is "n-type" may also be adopted. A specific configuration in this case can be obtained by replacing "n-type region" with "p-type region" and "n-type region" with "p-type region" in the above description and the accompanying drawings.

[0339] In the above-described embodiments, when the semiconductor chip 8, 101 includes a SiC single crystal, the semiconductor chip 8, 101 preferably includes a hexagonal SiC single crystal. The hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal, depending on the period of the atomic arrangement. Of the multiple polytypes, the semiconductor chip 8, 101 preferably includes a 4H-SiC single crystal.

[0340] In this case, it is preferable that the first main surfaces 10, 102 are formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surfaces 11, 103 are formed by the carbon surface ((000-1) surface) of the SiC single crystal. Of course, the first main surfaces 10, 102 may be formed by the carbon surface, and the second main surfaces 11, 103 may be formed by the silicon surface. The (0001) surface and the (000-1) surface of the SiC single crystal are called c-planes.

[0341] The first main surfaces 10, 102 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane of the SiC single crystal. The off direction may be the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be 0° or more and 5.0° or less. In this case, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0342] Below, we present examples of features extracted from this specification and the accompanying drawings. Hereinafter, we provide a semiconductor device having a novel structure. Below, alphanumeric characters in parentheses represent corresponding components in the above-described embodiments, but are not intended to limit the scope of each item to the embodiments.

[0343] [Supplementary Note 1-1] A semiconductor chip (8, 101) consisting of a single layer having a first main surface (10, 102) and a second main surface (11, 103) opposite to the first main surface (10, 102), a first semiconductor region (46, 121) of a first conductivity type formed on the first main surface (10, 102) side of the semiconductor chip (8, 101), and a second semiconductor region (47, 122) of a second conductivity type formed on the second main surface (11, 103) side of the first semiconductor region (46, 121) of the semiconductor chip (8, 101), a first trench (48, 126) that penetrates the first semiconductor region (46, 121) from the first main surface (10, 102) and divides the first semiconductor region (46, 121) into a first region (19, 107) on one side and a second region (20, 108) on the other side in a cross-sectional view; a control insulating film (49, 127) that covers the inner wall of the first trench (48, 126); and a first trench structure (17, 123) including a control electrode (50, 128) that is embedded in the first trench (48, 126) with a gate insulating film (17, 128) sandwiched therebetween and controls a channel (96, 184) in the second semiconductor region (47, 122) that conducts electricity between the first region (19, 107) and the second region (20, 108) in a lateral direction along the first main surface (10, 102).

[0344] [Supplementary Note 1-2] In the thickness direction of the semiconductor chip (8, 101), the second conductivity type impurity concentration of the second semiconductor region (47, 122) from the second main surface (11, 103) to the first semiconductor region (46, 121) is 1.0×10 ２０ cm －３ The semiconductor device (1A, 1B) described in Appendix 1-1 is as follows.

[0345] [Appendix 1-3] The semiconductor device (1A, 1B) according to Appendix 1-1 or Appendix 1-2, wherein the second conductivity type impurity concentration of the second semiconductor region (47, 122) from the second main surface (11, 103) to the first semiconductor region (46, 121) is substantially constant in the thickness direction of the semiconductor chip (8, 101).

[0346] [Supplementary Note 1-4] The second conductivity type impurity concentration of the second semiconductor region (47, 122) is 1.0×10 over the entire thickness direction of the semiconductor chip (8, 101) from the second main surface (11, 103) to the first semiconductor region (46, 121). １３ cm －３ Above 1.0 x 10 １６ cm －３ The semiconductor device (1A, 1B) according to any one of Supplementary Notes 1-1 to 1-3, which is as follows:

[0347] [Appendix 1-5] The semiconductor device (1A, 1B) according to any one of Appendices 1-1 to 1-4, wherein the resistance value of the second semiconductor region (47, 122) is 10 Ω·cm or more and 100 Ω·cm or less.

[0348] [Appendix 1-6] The semiconductor device (1A, 1B) according to Appendix 1-5, wherein the resistance value of the second semiconductor region (47, 122) is 10 Ω cm or more and 100 Ω cm or less throughout the entire thickness direction of the semiconductor chip (8, 101) from the second main surface (11, 103) to the first semiconductor region (46, 121).

[0349] [Supplementary Note 1-7] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, wherein the semiconductor chip (8, 101) is a semiconductor substrate that does not have an epitaxial layer.

[0350] [Supplementary Note 1-8] The first conductivity type impurity concentration of the first semiconductor region (46, 121) is 1.0×10 １４ cm －３ Above 1.0 x 10 １８ cm －３ The semiconductor device (1A, 1B) according to any one of Supplementary Notes 1-1 to 1-7, which is as follows:

[0351] [Appendix 1-9] The semiconductor device (1A, 1B) according to any one of Appendices 1-1 to 1-8, further including an insulating protective film (88, 176) covering the entire second main surface (11, 103) of the semiconductor chip (8, 101).

[0352] [Supplementary Note 1-10] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-1 to Supplementary Note 1-8, wherein the second main surface (11, 103) of the semiconductor chip (8, 101) is an exposed surface.

[0353] [Supplementary Note 1-11] The second conductivity type impurity concentration of the second semiconductor region (47, 122) is 1.0×10 over the entire thickness direction of the semiconductor chip (8, 101) from the second main surface (11, 103) to the first semiconductor region (46, 121). １３ cm －３ Above 1.0 x 10 １６ cm －３ The semiconductor device (1A, 1B) according to Appendix 1-1, wherein the resistance value of the second semiconductor region (47, 122) is 10 Ω·cm or more and 100 Ω·cm or less.

[0354] [Appendix 1-12] The semiconductor device (1A, 1B) according to appendix 1-11, wherein the semiconductor chip (8, 101) is a semiconductor substrate that does not have an epitaxial layer.

[0355] [Appendix 1-13] The semiconductor device (1A, 1B) according to appendix 1-11, wherein the semiconductor chip (8, 101) is a Si single crystal substrate or a SiC single crystal substrate having no epitaxial layer.

[0356] [Appendix 1-14] The semiconductor device (1A, 1B) according to appendix 1-13, further comprising an insulating protective film (88, 176) covering the entire second main surface (11, 103) of the semiconductor chip (8, 101).

[0357] [Supplementary Note 1-15] The semiconductor device further includes a drift region (21, 109) sandwiched between a pair of the first trench structures (17, 123), the first region (19, 107) including a first source / drain region (19, 107) facing the drift region (21, 109) across one of the first trench structures (17, 123), the second region (20, 108) including a second source / drain region (20, 108) on the opposite side of the first source / drain region (19, 107) across the drift region (21, 109), a first source / drain electrode (65, 148) electrically connected to the first source / drain region (19, 107), The semiconductor device (1A, 1B) according to any one of Supplementary Notes 1-1 to 1-14, further comprising a second source-drain electrode (69, 152) electrically connected to the second source-drain region (20, 108).

[0358] [Supplementary Note 2-1] A semiconductor chip (8, 101) having a first main surface (10, 102) and a second main surface (11, 103) opposite to the first main surface (10, 102), a first semiconductor region (46, 121) of a first conductivity type formed on the first main surface (10, 102) side of the semiconductor chip (8, 101), and a second semiconductor region (47, 122) of a second conductivity type formed on the second main surface (11, 103) side of the first semiconductor region (46, 121) of the semiconductor chip (8, 101), a first trench structure (17, 123) including: a first trench (48, 126) that penetrates the first semiconductor region (46, 121) from the first main surface (10, 102) and divides the first semiconductor region (46, 121) into a first region (19, 107) on one side and a second region (20, 108) on the other side in a cross-sectional view; a control insulating film (49, 127) that covers an inner wall of the first trench (48, 126); and a control electrode (50, 128) that is embedded in the first trench (48, 126) across the control insulating film (49, 127) and controls a channel (96, 184) in the second semiconductor region (47, 122) that conducts electricity between the first region (19, 107) and the second region (20, 108) in a lateral direction along the first main surface (10, 102); a first electrode (65, 148) electrically connected to the first semiconductor region (46, 121) in the first region (19, 107); a second electrode (69, 152) electrically connected to the first semiconductor region (46, 121) in the second region (20, 108); a protrusion (59, 145) of a second conductivity type selectively protruding from the second semiconductor region (47, 122) toward the first main surface (10, 102) into the first semiconductor region (46, 121); and a contact electrode (76, 158) electrically connected to the protrusion (59, 145) and separated from the first electrode (65, 148) and the second electrode (69, 152).

[0359] [Supplementary Note 2-2] The semiconductor device (1A, 1B) according to Supplementary Note 2-1 further includes a second trench structure (73, 156) including a contact trench (75, 157) extending from the first main surface (10, 102) to the protruding portion (59, 145), and the contact electrode (76, 158) embedded in the contact trench (75, 157) and connected to the protruding portion (59, 145) within the contact trench (75, 157).

[0360] [Supplementary Note 2-3] The semiconductor device (1A, 1B) according to Supplementary Note 2-2, wherein the contact trench (75, 157) is shallower than the first trench (48, 126).

[0361] [Appendix 2-4] The semiconductor device (1A, 1B) according to appendix 2-3, wherein the depth of the contact trench (75, 157) is 0.2 μm or more and 0.5 μm or less.

[0362] [Appendix 2-5] The semiconductor device (1A, 1B) according to any one of Appendices 2-2 to 2-4, wherein the contact electrode (76, 158) includes: a barrier film (77, 160) formed in a film shape along the sidewalls and bottom wall of the contact trench (75, 157) and defining a recess space within the contact trench (75, 157); and an electrode body (78, 161) embedded in the contact trench (75, 157) with the barrier film (77, 160) sandwiched therebetween; and further includes a silicide layer (79, 162) formed along the sidewalls and bottom wall of the contact trench (75, 157) at a boundary between the semiconductor chip (8, 101) and the barrier film (77, 160).

[0363] [Supplementary Note 2-6] The semiconductor device (1A, 1B) according to Supplementary Note 2-5, wherein the silicide layer (79, 162) is formed uniformly over the entire sidewall and bottom wall of the contact trench (75, 157).

[0364] [Appendix 2-7] The semiconductor device (1A, 1B) according to any one of Appendices 2-1 to 2-6, further including a first impurity region (63, 146) of a first conductivity type formed in a surface layer portion of the first main surface (10, 102) in contact with a top of the protrusion (59, 145), and having an impurity concentration higher than that of the first semiconductor region (46, 121).

[0365] [Supplementary Note 2-8] The semiconductor device further includes a drift region (21, 109) sandwiched between a pair of the first trench structures (17, 123), the first region (19, 107) including a first source / drain region (19, 107) facing the drift region (21, 109) across one of the first trench structures (17, 123), the second region (20, 108) including a second source / drain region (20, 108) on the opposite side of the first source / drain region (19, 107) across the drift region (21, 109), and a current path through the channel (96, 184) is formed along a first direction (X) from the first source / drain region (19, 107) across the drift region (21, 109) toward the second source / drain region (20, 108), The semiconductor device (1A, 1B) according to any one of Supplementary Notes 2-1 to 2-7, wherein the second region (20, 108) independently includes, in a second direction (Y) intersecting the first direction (X), a contact region (61) in which the protrusion (59, 145) is selectively formed and in which the contact electrode (76, 158) is arranged, and a current region (62) of a first conductivity type sandwiched between the pair of first trench structures (17, 123).

[0366] [Supplementary Note 2-9] The semiconductor device (1A, 1B) according to Supplementary Note 2-8, wherein the plurality of contact regions (61) are arranged at intervals from each other along the second direction (Y).

[0367] [Supplementary Note 2-10] The semiconductor device (1A, 1B) according to Supplementary Note 2-9, wherein the pair of first trench structures (17, 123) are formed in a band shape extending along the second direction (Y) in a planar view, and the plurality of contact regions (61) are formed so as to divide the drift region (21, 109), which is in a band shape in a planar view and is sandwiched between the pair of first trench structures (17, 123), at a plurality of locations along the second direction (Y).

[0368] [Supplementary Note 2-11] The semiconductor device (1A, 1B) according to any one of Supplementary Note 2-8 to Supplementary Note 2-10, wherein the contact region (61) is shorter than the current region (62) in the second direction (Y).

[0369] [Appendix 2-12] The semiconductor device (1A, 1B) according to Appendix 2-11, wherein the length of the contact region (61) in the second direction (Y) is 0.1 μm or more and 100 μm or less, and the length of the current region (62) in the second direction (Y) is 1 μm or more and 3000 μm or less.

[0370] [Supplementary Note 2-13] The semiconductor device (1A, 1B) according to any one of Supplementary Note 2-1 to Supplementary Note 2-12, wherein the semiconductor chip (8, 101) is a semiconductor substrate that does not have an epitaxial layer.

[0371] [Supplementary Note 2-14] In the thickness direction of the semiconductor chip (8, 101), the second conductivity type impurity concentration of the second semiconductor region (47, 122) from the second main surface (11, 103) to the first semiconductor region (46, 121) is 1.0×10 ２０ cm －３ The semiconductor device (1A, 1B) according to any one of Supplementary Notes 2-1 to 2-13, which is as follows:

[0372] [Appendix 2-15] The semiconductor device (1A, 1B) according to any one of Appendices 2-1 to 2-14, wherein the resistance value of the second semiconductor region (47, 122) is 10 Ω·cm or more and 100 Ω·cm or less.

[0373] [Supplementary Note 3-1] A semiconductor chip (8, 101) having a first main surface (10, 102) and a second main surface (11, 103) opposite to the first main surface (10, 102), and having an active region (15, 105) and a peripheral region (16, 106) surrounding the active region (15, 105); a first semiconductor region (46, 121) of a first conductivity type formed on the first main surface (10, 102) side of the semiconductor chip (8, 101); and a second semiconductor region (47, 122) of a second conductivity type formed on the second main surface (11, 103) side of the first semiconductor region (46, 121) of the semiconductor chip (8, 101); a first trench (48, 126) that penetrates the first semiconductor region (46, 121) from the first main surface (10, 102) in the active region (15, 105) and divides the first semiconductor region (46, 121) into a first region (19, 107) on one side and a second region (20, 108) on the other side in a cross-sectional view; a first trench structure (17, 123) including a control electrode (50, 128) embedded in the first trench (48, 126) with the control insulating film (49, 127) sandwiched therebetween, the control electrode (50, 128) controlling a channel (96, 184) in the second semiconductor region (47, 122) that conducts electricity between the first region (19, 107) and the second region (20, 108) in a lateral direction along the first main surface (10, 102); a first electrode (65, 148) electrically connected to the first semiconductor region (46, 121) in the first region (19, 107); a second electrode (69, 152) electrically connected to the first semiconductor region (46, 121) in the second region (20, 108); and a contact electrode (76, 158) disposed in a drift region (21, 109) in which a current path is formed in the active region (15, 105) for conducting between the first electrode (65, 148) and the second electrode (69, 152), and electrically connected to the second semiconductor region (47, 122).

[0374] [Supplementary Note 3-2] A pair of first trench structures (17, 123) are formed to separate the first region (19, 107) from the drift region (21, 109) and the drift region (21, 109) from the second region (20, 108) so that the first region (19, 107) and the second region (20, 108) face each other with the drift region (21, 109) interposed therebetween, The semiconductor device (1A, 1B) according to Appendix 3-1 further includes a second trench structure (73, 156) including a contact trench (75, 157) formed in the drift region (21, 109) from the first main surface (10, 102) toward the second main surface (11, 103), and the contact electrode (76, 158) embedded in the contact trench (75, 157) and electrically connected to the second semiconductor region (47, 122) within the contact trench (75, 157).

[0375] [Supplementary Note 3-3] The semiconductor device (1A, 1B) according to Supplementary Note 3-2, further including a protrusion (59, 145) of a second conductivity type that selectively protrudes from the second semiconductor region (47, 122) toward the first main surface (10, 102) into the drift region (21, 109), and the contact electrode (76, 158) is connected to the protrusion (59, 145).

[0376] [Supplementary Note 3-4] The semiconductor device (1A, 1B) according to Supplementary Note 3-3, wherein the contact trench (75, 157) is shallower than the first trench (48, 126).

[0377] [Appendix 3-5] The semiconductor device (1A, 1B) according to Appendix 3-4, wherein the depth of the contact trench (75, 157) is not less than 0.2 μm and not more than 0.5 μm.

[0378] [Appendix 3-6] The semiconductor device (1A, 1B) according to Appendix 3-4, wherein the contact electrode (76, 158) includes: a barrier film (77, 160) formed in a film shape along the sidewalls and bottom wall of the contact trench (75, 157) and defining a recess space within the contact trench (75, 157); and an electrode body (78, 161) embedded in the contact trench (75, 157) with the barrier film (77, 160) sandwiched therebetween; and further includes a silicide layer (79, 162) formed along the sidewalls and bottom wall of the contact trench (75, 157) at a boundary between the semiconductor chip (8, 101) and the barrier film (77, 160).

[0379] [Supplementary Note 3-7] The semiconductor device (1A, 1B) according to Supplementary Note 3-6, wherein the silicide layer (79, 162) is formed uniformly over the entire sidewall and bottom wall of the contact trench (75, 157).

[0380] [Supplementary Note 3-8] The semiconductor device (1A, 1B) according to Supplementary Note 3-2, wherein the contact trench (75, 157) is deeper than the first trench (48, 126).

[0381] [Supplementary Note 3-9] A pair of first trench structures (17, 123) are formed to separate the first region (19, 107) from the drift region (21, 109) and the drift region (21, 109) from the second region (20, 108) so that the first region (19, 107) and the second region (20, 108) face each other with the drift region (21, 109) interposed therebetween, and a protrusion (59, 145) of a second conductivity type selectively protruding from the second semiconductor region (47, 122) to the first main surface (10, 102) via the drift region (21, 109), The semiconductor device (1A, 1B) according to Appendix 3-1, wherein the contact electrode (76, 158) has a bottom on the first main surface (10, 102) and is connected to the protrusion (59, 145) on the first main surface (10, 102).

[0382] [Appendix 3-10] The semiconductor device (1A, 1B) according to any one of Appendices 3-1 to 3-9, wherein the first semiconductor region (46, 121) is formed over the entire active region (15, 105) and the outer peripheral region (16, 106) and forms a side surface of the semiconductor chip (8, 101).

[0383] [Appendix 3-11] The semiconductor device (1A, 1B) according to any one of Appendices 3-1 to 3-9, wherein an occupancy rate of the active region (15, 105) on the first main surface (10, 102) of the semiconductor chip (8, 101) is 10% or more and 99.9% or less.

[0384] [Appendix 3-12] The semiconductor device (1A, 1B) according to any one of Appendices 3-1 to 3-9, wherein the first electrode (65, 148) is a first source-drain electrode, and the second electrode (69, 152) is a second source-drain electrode.

[0385] [Appendix 3-13] The semiconductor device (1A, 1B) according to any one of Appendices 3-1 to 3-9, wherein the semiconductor chip (8, 101) is a semiconductor substrate that does not have an epitaxial layer.

[0386] [Supplementary Note 3-14] In the thickness direction of the semiconductor chip (8, 101), the second conductivity type impurity concentration of the second semiconductor region (47, 122) from the second main surface (11, 103) to the first semiconductor region (46, 121) is 1.0×10 ２０ cm －３ The semiconductor device (1A, 1B) described in Appendix 3-13 below.

[0387] [Appendix 3-15] The semiconductor device (1A, 1B) according to appendix 3-13, wherein the resistance value of the second semiconductor region (47, 122) is 10 Ω·cm or more and 100 Ω·cm or less.

[0388] [Supplementary Note 4-1] A semiconductor chip (8, 101) having a first main surface (10, 102) and a second main surface (11, 103) opposite to the first main surface (10, 102), a first semiconductor region (46, 121) of a first conductivity type formed on the first main surface (10, 102) side of the semiconductor chip (8, 101), and a second semiconductor region (47, 122) of a second conductivity type formed on the second main surface (11, 103) side of the first semiconductor region (46, 121) of the semiconductor chip (8, 101), a first trench structure (17, 123) including: a first trench (48, 126) that penetrates the first semiconductor region (46, 121) from the first main surface (10, 102) and divides the first semiconductor region (46, 121) in a first direction (X) into a first region (19, 107) on one side and a second region (20, 108) on the other side; a control insulating film (49, 127) that covers an inner wall of the first trench (48, 126); and a control electrode (50, 128) that is embedded in the first trench (48, 126) across the control insulating film (49, 127) and controls a channel (96, 184) in the second semiconductor region (47, 122) that conducts electricity between the first region (19, 107) and the second region (20, 108) in the first direction (X); a first electrode (65, 148) electrically connected to the first semiconductor region (46, 121) in the first region (19, 107); a second electrode (69, 152) electrically connected to the first semiconductor region (46, 121) in the second region (20, 108); and a contact electrode (76, 158) electrically connected to the second semiconductor region (47, 122), the contact electrode being disposed apart in a second direction (Y) intersecting the first direction (X) from a drift region (21, 109) in the semiconductor chip (8, 101) in which a current path is formed that conducts electricity between the first electrode (65, 148) and the second electrode (69, 152).

[0389] [Supplementary Note 4-2] The semiconductor device (1A, 1B) according to Supplementary Note 4-1, wherein a pair of strip-shaped first trench structures (17, 123) extending along the second direction (Y) are formed to separate the first region (19, 107) from the drift region (21, 109) and the drift region (21, 109) from the second region (20, 108) so that the first region (19, 107) and the second region (20, 108) face each other with the drift region (21, 109) interposed therebetween, and the contact electrode (76, 158) is arranged adjacent to an end, in the second direction (Y), of the strip-shaped drift region (21, 109) extending along the second direction (Y).

[0390] [Appendix 4-3] The semiconductor device (1A, 1B) according to Appendix 4-2, wherein the width of the drift region (21, 109) in the first direction (X) is 0.01 μm or more and 10 μm or less.

[0391] [Appendix 4-4] The semiconductor device (1A, 1B) according to appendix 4-2, wherein the pitch of the pair of first trench structures (17, 123) is 0.03 μm or more and 10 μm or less.

[0392] [Appendix 4-5] The semiconductor device (1A, 1B) according to Appendix 4-2, wherein the contact electrodes (76, 158) are arranged adjacent to both ends of the drift region (21, 109) in the second direction (Y).

[0393] [Supplementary Note 4-6] The first region (19, 107) and the second region (20, 108) respectively include strip-shaped first source / drain regions (19, 107) and second source / drain regions (20, 108) extending along the second direction (Y), the plurality of first source / drain regions (19, 107) and the plurality of second source / drain regions (20, 108) are alternately arranged at intervals in the first direction (X) such that the drift region (21, 109) is sandwiched between adjacent first source / drain regions (19, 107) and second source / drain regions (20, 108), and further include a contact wiring layer (114) arranged in a strip-shaped wiring region (111) extending in a direction crossing the vicinity of each end of the plurality of first source / drain regions (19, 107) and the plurality of second source / drain regions (20, 108), The semiconductor device (1A, 1B) according to any one of appendices 4-1 to 4-5, wherein the contact electrode (76, 158) is arranged below the contact wiring layer (114) in the wiring region (111).

[0394] [Appendix 4-7] The semiconductor device (1A, 1B) according to Appendix 4-6, wherein the contact electrodes (76, 158) are arranged at intervals in the first direction (X), and each of the contact electrodes (76, 158) is disposed at a position facing each of the drift regions (21, 109) in the second direction (Y).

[0395] [Appendix 4-8] The semiconductor device (1A, 1B) according to Appendix 4-6, wherein one of the contact electrodes (76, 158) extends below the contact wiring layer (114) in a direction crossing regions near each end of the plurality of first source-drain regions (19, 107) and the plurality of second source-drain regions (20, 108).

[0396] [Appendix 4-9] The semiconductor device (1A, 1B) according to any one of Appendices 4-6 to 4-8, wherein a plurality of cell regions (110) are formed at intervals in the second direction (Y), in which a plurality of sets of the first source / drain regions (19, 107), the second source / drain regions (20, 108), and the first trench structures (17, 123) therebetween are arranged, and the wiring region (111) is formed between adjacent cell regions (110).

[0397] [Appendix 4-10] The semiconductor device (1A, 1B) according to Appendix 4-9, further comprising a pair of strip-shaped control wiring layers (113) extending in the first direction (X) through the wiring region (111) so as to sandwich the contact wiring layer (114), one of the control wiring layers (113) being electrically connected to the control electrode (50, 128) of the cell region (110) on one side of the wiring region (111), and the other control wiring layer (113) being electrically connected to the control electrode (50, 128) of the cell region (110) on the other side of the wiring region (111).

[0398] [Appendix 4-11] The semiconductor device (1A, 1B) according to Appendix 4-9 or Appendix 4-10, wherein the contact wiring layer (114) includes a peripheral portion (118) extending along the peripheral region of the semiconductor chip (8, 101) and a branch portion (119) extending from the peripheral portion (118) toward the inside of the semiconductor chip (8, 101) on the wiring region (111), and the contact electrode (76, 158) is disposed below both the peripheral portion (118) and the branch portion (119).

[0399] [Appendix 4-12] The semiconductor device (1A, 1B) according to any one of Appendices 4-6 to 4-11, further comprising a second conductivity type protrusion (59, 145) that selectively protrudes from the second semiconductor region (47, 122) toward the first main surface (10, 102) into the wiring region (111), and the contact electrode (76, 158) is connected to the protrusion (59, 145).

[0400] [Appendix 4-13] The semiconductor device (1A, 1B) according to Appendix 4-12 further includes a second trench structure (73, 156) including a contact trench (75, 157) formed in the wiring region (111) from the first main surface (10, 102) toward the second main surface (11, 103), and the contact electrode (76, 158) embedded in the contact trench (75, 157) and connected to the protrusion (59, 145) within the contact trench (75, 157).

[0401] [Appendix 4-14] The semiconductor device (1A, 1B) according to Appendix 4-13, wherein the contact trench (75, 157) is shallower than the first trench (48, 126).

[0402] [Appendix 4-15] The semiconductor device (1A, 1B) according to appendix 4-14, wherein the depth of the contact trench (75, 157) is 0.2 μm or more and 0.5 μm or less.

[0403] [Appendix 4-16] The semiconductor device (1A, 1B) according to any one of Appendices 4-13 to 4-15, wherein the contact electrode (76, 158) includes: a barrier film (77, 160) formed in a film shape along the sidewalls and bottom wall of the contact trench (75, 157) and defining a recess space within the contact trench (75, 157); and an electrode body (78, 161) embedded in the contact trench (75, 157) with the barrier film (77, 160) sandwiched therebetween; and further includes a silicide layer (79, 162) formed along the sidewalls and bottom wall of the contact trench (75, 157) at a boundary between the semiconductor chip (8, 101) and the barrier film (77, 160).

[0404] [Supplementary Note 5-1] A semiconductor chip (8, 101) having a first main surface (10, 102) and a second main surface (11, 103) opposite to the first main surface (10, 102), a first semiconductor region (46, 121) of a first conductivity type formed on the first main surface (10, 102) side of the semiconductor chip (8, 101), and a second semiconductor region (47, 122) of a second conductivity type formed on the second main surface (11, 103) side of the first semiconductor region (46, 121) of the semiconductor chip (8, 101), a first trench structure (17, 123) including: a first trench (48, 126) that penetrates the first semiconductor region (46, 121) from the first main surface (10, 102) and divides the first semiconductor region (46, 121) in a first direction (X) into a first region (19, 107) on one side and a second region (20, 108) on the other side; a control insulating film (49, 127) that covers an inner wall of the first trench (48, 126); and a control electrode (50, 128) that is embedded in the first trench (48, 126) across the control insulating film (49, 127) and controls a channel (96, 184) in the second semiconductor region (47, 122) that conducts electricity between the first region (19, 107) and the second region (20, 108) in the first direction (X); a control connection structure (18, 124) connected to the control electrode (50, 128), drawn out from the first trench structure (17, 123) along a second direction (Y) intersecting the first direction (X), and pulled up to the first main surface (10, 102); and a trench breakdown withstand structure (125) formed between the control connection structure (18, 124) and at least one of the first region (19, 107) and the second region (20, 108).

[0405] [Supplementary Note 5-2] The semiconductor device (1A, 1B) according to Supplementary Note 5-1, wherein the control connection structure (18, 124) includes a trench connection structure (18, 124) including: a connection trench (56, 134) that penetrates from the first main surface (10, 102) through the first semiconductor region (46, 121) and reaches the second semiconductor region (47, 122); a connection insulating film (57, 135) that covers an inner wall of the connection trench (56, 134); and a connection electrode (58, 136) that is embedded in the connection trench (56, 134) with the connection insulating film (57, 135) sandwiched therebetween and faces the first semiconductor region (46, 121) and the second semiconductor region (47, 122).

[0406] [Supplementary Note 5-3] The semiconductor device (1A, 1B) according to Supplementary Note 5-2, wherein the trench voltage-resistant structure (125) includes a voltage-resistant trench (138) that penetrates from the first main surface (10, 102) through the first semiconductor region (46, 121) and reaches the second semiconductor region (47, 122), and a voltage-resistant insulator (141) that is embedded in the voltage-resistant trench (138) and faces the first semiconductor region (46, 121).

[0407] [Supplementary Note 5-4] The semiconductor device (1A, 1B) according to Supplementary Note 5-2, wherein the control electrode (50, 128) is embedded in the first trench (48, 126) at a distance from the first main surface (10, 102) to a bottom wall side of the first trench (48, 126), and the first trench structure (17, 123) includes a first insulator (51, 129) embedded in the first trench (48, 126) so as to cover the control electrode (50, 128).

[0408] [Appendix 5-5] The trench voltage-resistant structure (125) includes a voltage-resistant trench (138) continuous with the first trench (48, 126), a voltage-resistant insulating film (139) covering an inner wall of the voltage-resistant trench (138) and integral with the control insulating film (49, 127), a voltage-resistant electrode (140) embedded in the voltage-resistant trench (138) across the voltage-resistant insulating film (139) at a position spaced apart from the first main surface (10, 102) toward the bottom wall of the voltage-resistant trench (138) and integral with the control electrode (50, 128), and a voltage-resistant insulator (141) embedded in the voltage-resistant trench (138) so as to cover the voltage-resistant electrode (140) and integral with the first insulator (51, 129).

[0409] [Supplementary Note 5-6] The semiconductor device (1A, 1B) according to any one of Supplementary Note 5-1 to Supplementary Note 5-5, wherein the first trench structure (17, 123) is formed in a strip shape extending along the second direction (Y), and the trench breakdown withstanding structure (125) is integrally connected to an end of the first trench structure (17, 123) in the second direction (Y) and extends in a bending direction from the end of the first trench structure (17, 123) so as to cover an end of at least one of the first region (19, 107) and the second region (20, 108) in the second direction (Y).

[0410] [Appendix 5-7] The semiconductor device (1A, 1B) according to Appendix 5-6, wherein a pair of strip-shaped first trench structures (17, 123) extending along the second direction (Y) are formed to sandwich the first region (19, 107), and the trench breakdown withstanding structure (125) is formed across the pair of first trench structures (17, 123) in the first direction (X) and faces an end of the first region (19, 107) sandwiched between the pair of first trench structures (17, 123) in the second direction (Y).

[0411] [Appendix 5-8] The semiconductor device (1A, 1B) according to Appendix 5-6 or Appendix 5-7, wherein a pair of strip-shaped first trench structures (17, 123) extending along the second direction (Y) are formed to sandwich the second region (20, 108), and the trench breakdown withstanding structure (125) is formed across the pair of first trench structures (17, 123) in the first direction (X) and faces an end of the second region (20, 108) sandwiched between the pair of first trench structures (17, 123) in the second direction (Y).

[0412] [Supplementary Note 5-9] The first region (19, 107) and the second region (20, 108) include strip-shaped first source / drain regions (19, 107) and second source / drain regions (20, 108) extending along the second direction (Y), and the first source / drain regions (19, 107) and the second source / drain regions (20, 108) are sandwiched in the first direction (X) by a pair of strip-shaped first trench structures (17, 123) and sandwiched in the second direction (Y) by a pair of trench connection structures (18, 124) integral with the pair of first trench structures (17, 123), thereby being surrounded by the pair of first trench structures (17, 123) and the pair of trench connection structures (18, 124), The semiconductor device (1A, 1B) described in Appendix 5-2, wherein the trench breakdown withstanding structure (125) crosses the first source / drain region (19, 107) and the second source / drain region (20, 108), respectively, from one of the first trench structures (17, 123) toward the other of the first trench structures (17, 123), and divides the first source / drain region (19, 107) and the second source / drain region (20, 108).

[0413] [Supplementary Note 5-10] The semiconductor device (1A, 1B) according to Supplementary Note 5-9, wherein a plurality of the first source / drain regions (19, 107) and a plurality of the second source / drain regions (20, 108) are alternately arranged at intervals in the first direction (X) such that a drift region (21, 109) is sandwiched between adjacent first source / drain regions (19, 107) and second source / drain regions (20, 108), and further includes a control wiring layer (113) arranged in a strip-shaped wiring region (111) extending in a direction crossing vicinities of each end of the plurality of first source / drain regions (19, 107) and the plurality of second source / drain regions (20, 108), wherein the control wiring layer (113) is arranged to cover the trench connection structure (18, 124) but not cover the trench breakdown withstand structure (125) in a plan view, and is connected to the connection electrode (58, 136).

[0414] [Appendix 5-11] The semiconductor device (1A, 1B) according to Appendix 5-10, wherein a plurality of cell regions (110) are formed at intervals in the second direction (Y), in which a plurality of sets of the first source / drain regions (19, 107), the second source / drain regions (20, 108), and the first trench structures (17, 123) therebetween are arranged, and the wiring region (111) is formed between adjacent cell regions (110).

[0415] [Appendix 5-12] The semiconductor device (1A, 1B) according to Appendix 5-11, wherein a pair of strip-shaped control wiring layers (113) are formed extending along the first direction (X) in the wiring region (111), one of the control wiring layers (113) is connected to the connection electrodes (58, 136) of the cell region (110) on one side of the wiring region (111), and the other of the control wiring layers (113) is connected to the connection electrodes (58, 136) of the cell region (110) on the other side of the wiring region (111).

[0416] [Appendix 5-13] The semiconductor device (1A, 1B) according to any one of Appendices 5-9 to 5-12, including a first source-drain electrode (65, 148) connected to the first source-drain region (19, 107), and a second source-drain electrode (69, 152) connected to the second source-drain region (20, 108).

[0417] [Supplementary Note 5-14] The semiconductor device (1A, 1B) according to any one of Supplementary Note 5-1 to Supplementary Note 5-13, wherein the semiconductor chip (8, 101) is a semiconductor substrate that does not have an epitaxial layer.

[0418] [Supplementary Note 5-15] In the thickness direction of the semiconductor chip (8, 101), the second conductivity type impurity concentration of the second semiconductor region (47, 122) from the second main surface (11, 103) to the first semiconductor region (46, 121) is 1.0×10 ２０ cm －３ The semiconductor device (1A, 1B) according to any one of Supplementary Notes 5-1 to 5-14, which is as follows:

[0419] [Appendix 5-16] The semiconductor device (1A, 1B) according to any one of Appendices 5-1 to 5-15, wherein the resistance value of the second semiconductor region (47, 122) is 10 Ω·cm or more and 100 Ω·cm or less.

[0420] 1A: Semiconductor device 1B: Semiconductor device 3: Diode pair 4: Base terminal 5: Gate terminal 6: First source / drain terminal 7: Second source / drain terminal 8: Semiconductor chip 9: Insulating layer 10: First main surface 11: Second main surface 12A: First side surface 12B: Second side surface 12C: Third side surface 12D: Fourth side surface 13: Insulating main surface 14A: First insulating side surface 14B: Second insulating side surface 14C: Third insulating side surface 14D: Fourth insulating side surface 15: Active region 16: Peripheral region 17: First trench structure 18: Trench connection structure 19: First source / drain region 20: Second source / drain region 21: Drift region 22: First contact region 23: First lower contact 24 : Second contact region 25 : Second lower contact 26 : First base contact 27 : First gate contact 28 : First wiring layer 29 : Second wiring layer 30 : First gate wiring layer 31 : First lower wiring layer 32 : Second lower wiring layer 33 : First base wiring layer 34 : Second gate wiring layer 35 : First upper wiring layer 36 : Second upper wiring layer 37 : Second base wiring layer 38 : Second gate contact 39 : Second base contact 40 : First upper contact 41 : Second upper contact 42 : Gate terminal contact 43 : Base terminal contact 44 : First terminal contact 45 : Second terminal contact 46 : First semiconductor region 47 : Second semiconductor region 48 : First trench 49 : Gate insulating film 50 : Gate electrode 51 : Buried insulator 52 : Lead portion 53 : First mesa portion 54 : Second mesa portion 55 : Drift mesa portion 56 : Connection trench 57 : Connection insulating film 58 : Connection electrode 59 : Protrusion 60 : Boundary portion 61 : Contact region 62 : Current region 63 : First impurity region 64 : Main surface insulating film 65 : First electrode 66 : First connection opening 67 : First barrier film68: First electrode body 69: Second electrode 70: Second connection opening 71: Second barrier film 72: Second electrode body 73: Second trench structure 74: Base connection opening 75: Base trench 76: Base electrode 77: Base barrier film 78: Base electrode body 79: Silicide layer 80: Third electrode 81: Third connection opening 82: Third barrier film 83: Third electrode body 84: Bottom wall impurity region 85: First interlayer insulating film 86: Second interlayer insulating film 87: Top insulating film 88: Rear surface protective film 89: First pn junction 90: Second pn junction 91: Wafer 92: First wafer main surface 93: Second wafer main surface 94: First base insulating film 95 : Second base insulating film 96 : Channel 97 : Current path 98 : Top 101 : Semiconductor chip 102 : First main surface 103 : Second main surface 104A : First side surface 104B : Second side surface 104C : Third side surface 104D : Fourth side surface 105 : Active region 106 : Peripheral region 107 : First source / drain region 108 : Second source / drain region 109 : Drift region 110 : Cell region 111 : Wiring region 112 : First wiring layer 113 : First gate wiring layer 114 : First base wiring layer 115 : Gate peripheral portion 116 : Gate branch portion 117 : First gate contact 118 : Base peripheral portion 119 : Base branch portion 120 : First base contact 121: First semiconductor region 122: Second semiconductor region 123: First trench structure 124: Trench connection structure 125: Trench breakdown voltage structure 126: First trench 127: Gate insulating film 128: Gate electrode 129: Buried insulator 130: Lead-out portion 131: First mesa portion 132: Second mesa portion 133: Drift mesa portion 134: Connection trench 135: Connection insulating film 136: Connection electrode 137: Isolation region 138: Breakdown voltage trench 139: Breakdown voltage insulating film 140: Breakdown voltage electrode 141: Breakdown voltage insulator 142: First contact region143: Second contact region 144: Boundary portion 145: Protrusion portion 146: First impurity region 147: Main surface insulating film 148: First electrode 149: First connection opening 150: First barrier film 151: First electrode body 152: Second electrode 153: Second connection opening 154: Second barrier film 155: Second electrode body 156: Second trench structure 157: Base trench 158: Base electrode 159: Base connection opening 160: Base barrier film 161: Base electrode body 162: Silicide layer 163: Third electrode 164: Third connection opening 165: Third barrier film 166: Third electrode body 167: Bottom wall impurity region 168 : First interlayer insulating film 169 : First lower wiring layer 170 : Second lower wiring layer 171 : Second interlayer insulating film 172 : Second wiring layer 173 : First upper wiring layer 174 : Second upper wiring layer 175 : Top insulating film 176 : Back surface protective film 177 : First pn junction 178 : Second pn junction 179 : Wafer 180 : First wafer main surface 181 : Second wafer main surface 182 : First base insulating film 183 : Second base insulating film 184 : Channel 185 : Current path 186 : Voltage-resistant impurity region 187 : Top

Claims

1. a semiconductor chip consisting of a single layer having a first main surface and a second main surface opposite to the first main surface; a first semiconductor region of a first conductivity type formed on the first main surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second main surface side of the first semiconductor region of the semiconductor chip; a first trench structure including: a first trench that penetrates the first semiconductor region from the first main surface and divides the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view; a control insulating film that covers an inner wall of the first trench; and a control electrode that is embedded in the first trench across the control insulating film and controls a channel in the second semiconductor region that connects the first region and the second region in a lateral direction along the first main surface.

2. In the thickness direction of the semiconductor chip, the second conductivity type impurity concentration of the second semiconductor region from the second main surface to the first semiconductor region is 1.0×10 ２０ cm －３ 2. The semiconductor device according to claim 1, wherein:

3. 2. The semiconductor device according to claim 1, wherein the second semiconductor region has a substantially constant impurity concentration of the second conductivity type from the second main surface to the first semiconductor region in a thickness direction of the semiconductor chip.

4. The second semiconductor region has a second conductivity type impurity concentration of 1.0×10 throughout the entire thickness direction of the semiconductor chip from the second main surface to the first semiconductor region. １３ cm －３ Above 1.0 x 10 １６ cm －３ 2. The semiconductor device according to claim 1, wherein:

5. 2. The semiconductor device according to claim 1, wherein the resistance value of the second semiconductor region is not less than 10 Ω·cm and not more than 100 Ω·cm.

6. 6. The semiconductor device according to claim 5, wherein the resistance value of the second semiconductor region is 10 Ω·cm or more and 100 Ω·cm or less over the entire thickness direction of the semiconductor chip from the second main surface to the first semiconductor region.

7. 2. The semiconductor device according to claim 1, wherein the semiconductor chip is a semiconductor substrate having no epitaxial layer.

8. The first conductivity type impurity concentration of the first semiconductor region is 1.0×10 １４ cm －３ Above 1.0 x 10 １８ cm －３ 2. The semiconductor device according to claim 1, wherein:

9. 2. The semiconductor device according to claim 1, further comprising an insulating protective film covering the entire second main surface of said semiconductor chip.

10. The semiconductor device according to claim 1 , wherein the second main surface of the semiconductor chip is an exposed surface.

11. the second semiconductor region has a second conductivity type impurity concentration of 1.0×10 over the entire thickness direction of the semiconductor chip from the second main surface to the first semiconductor region; １３ cm －３ Above 1.0 x 10 １６ cm －３ 2. The semiconductor device according to claim 1, wherein the second semiconductor region has a resistance of 10 Ω·cm or more and 100 Ω·cm or less.

12. 12. The semiconductor device according to claim 11, wherein the semiconductor chip is a semiconductor substrate having no epitaxial layer.

13. 12. The semiconductor device according to claim 11, wherein the semiconductor chip is a single crystal Si substrate or a single crystal SiC substrate having no epitaxial layer.

14. 14. The semiconductor device according to claim 13, further comprising an insulating protective film covering the entire second main surface of the semiconductor chip.

15. a drift region sandwiched between the pair of first trench structures; the first region includes a first source / drain region facing the drift region across one of the first trench structures; the second region includes a second source / drain region on the opposite side of the drift region from the first source / drain region, a first source / drain electrode electrically connected to the first source / drain region; 15. The semiconductor device according to claim 1, further comprising a second source / drain electrode electrically connected to said second source / drain region.