Semiconductor device

Abstract

This semiconductor device comprises: an IGBT region and a diode region that are formed in a semiconductor layer; and a plurality of gate wires that are formed on a first main surface of the semiconductor layer, wherein one of the IGBT region and the diode region is a reference region and the other is a different region that differs from the reference region, in a predetermined region among active regions that include the IGBT region and the diode region, the reference region facing the different region in a first direction that is perpendicular to an extension direction of a gate trench in a plan view, and, in a predetermined region among the active regions the reference region further facing the different region in a second direction that is parallel to the extension direction of the gate trench in a plan view with a first gate wire that is included in the plurality of gate wires interposed therebetween.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-059174 filed with the Japan Patent Office on March 31, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device that includes an IGBT region and a diode region.

[0003] Patent Document 1 discloses an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) as an example of a semiconductor device. The RC-IGBT includes an IGBT region and a diode region fabricated in a common semiconductor layer. The IGBT region includes an IGBT. The diode region includes a diode.

[0004] International Publication No. 2019 / 230851

[0005] An embodiment of the present disclosure provides a semiconductor device that can suppress an increase in localized heat generation in an RC-IGBT.

[0006] One embodiment of the present disclosure provides a semiconductor device including a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, an IGBT region formed in the semiconductor layer, the IGBT region having a gate trench formed therein, a diode region formed in the semiconductor layer, and a plurality of gate interconnects formed on the first main surface. In a predetermined region of an active region including the IGBT region and the diode region, one of the IGBT region and the diode region is a reference region, and the other is a heterogeneous region different from the reference region. The reference region faces the heterogeneous region in a first direction perpendicular to the extension direction of the gate trench in a plan view. In a predetermined region of the active region, the reference region further faces the heterogeneous region in a second direction parallel to the extension direction of the gate trench in a plan view, with a first gate interconnect included in the plurality of gate interconnects sandwiched between them.

[0007] According to an embodiment of the present disclosure, a semiconductor device capable of suppressing an increase in local heat generation in an RC-IGBT can be provided.

[0008] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view schematically illustrating the structure of a first main surface of the semiconductor device. FIG. 3 is a bottom view schematically illustrating the structure of a second main surface of the semiconductor device. FIG. 4 is an enlarged view of a portion surrounded by dashed-dotted line IV in FIG. 1. FIG. 5A is an enlarged view of a portion surrounded by dashed-dotted line VA in FIG. 1. FIG. 5B is an enlarged view of a portion surrounded by dashed-dotted line VB in FIG. 5A. FIG. 6 is an enlarged view of a portion surrounded by dashed-dotted line VI in FIG. 4. FIG. 7 is an enlarged view of a portion surrounded by dashed-dotted line VII in FIG. 6. FIG. 8 is an enlarged view of a portion surrounded by dashed-dotted line VIII in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX in FIG. 8. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 7. FIG. 12 is a schematic plan view of a semiconductor package including the semiconductor device. FIG. 13 is a cross-sectional view showing the mounting structure of the semiconductor package of FIG. 12 . FIG. 14 is a bottom view for explaining a semiconductor device according to a modified example in which the aspects of the collector region and the cathode region are changed. FIG. 15 is a cross-sectional view of a semiconductor device according to the modified example of FIG. 14 , and is a view corresponding to FIG. 10 . FIG. 16 is a schematic plan view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 17 is a plan view schematically showing the structure of a first main surface of the semiconductor device. FIG. 18 is a schematic plan view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 19 is a plan view schematically showing the structure of the first main surface of the semiconductor device. FIG. 20 is a schematic plan view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 21 is a plan view schematically showing the structure of the first main surface of the semiconductor device. FIG. 22 is a schematic cross-sectional view of a semiconductor package including the semiconductor device.

[0009] Fig. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure. Fig. 2 is a plan view schematically showing the structure of a first main surface 3 of the semiconductor device 1. Fig. 3 is a bottom view schematically showing the structure of a second main surface 4 of the semiconductor device 1. Fig. 4 is an enlarged view of a portion surrounded by a dashed-dotted line IV in Fig. 1. Fig. 5A is an enlarged view of a portion surrounded by a dashed-dotted line VA in Fig. 1. Fig. 5B is an enlarged view of a portion surrounded by a dashed-dotted line VB in Fig. 5A.

[0010] The semiconductor device 1 is an electronic component having a reverse conducting-insulated gate bipolar transistor (RC-IGBT) that integrally includes an IGBT and a diode.

[0011] 1 to 3, semiconductor device 1 includes a rectangular parallelepiped semiconductor layer 2. Semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting first main surface 3 and second main surface 4.

[0012] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z. The side surfaces 5A and 5C extend along a first direction X and face a second direction Y that intersects with the first direction X. The side surfaces 5B and 5D extend along the second direction Y and face the first direction X. Specifically, the second direction Y is orthogonal (perpendicular) to the first direction X. The second direction Y includes one side Y1 and another side Y2. The one side Y1 corresponds to the upper side of the paper in FIG. 1 . The other side Y2 corresponds to the lower side of the paper in FIG. 1 .

[0013] The semiconductor layer 2 includes an active region 6 and an outer region 7. The active region 6 is a region in which an RC-IGBT is formed. The active region 6 is set in the center of the semiconductor layer 2, spaced apart from the side surfaces 5A to 5D toward the inner region in plan view. The active region 6 may be set in a rectangular shape having four sides parallel to the side surfaces 5A to 5D in plan view. The thickness of the semiconductor layer 2 may be 50 μm or more and 200 μm or less.

[0014] The outer region 7 is a region outside the active region 6. The outer region 7 extends in a strip shape along the periphery of the active region 6 in a plan view. Specifically, the outer region 7 has an endless shape (a quadrangular ring shape) surrounding the active region 6 in a plan view.

[0015] The active region 6 includes an IGBT region 8 and a diode region 9. For clarity, the IGBT region 8 is shown hatched in Figures 2 and 3. The IGBT region 8 is a region where an IGBT is formed. The diode region 9 is a region where a diode is formed.

[0016] Specifically, the active region 6 includes an RC-IGBT array (region array) 12. A plurality of RC-IGBT arrays 12 (six in this embodiment) are formed at intervals in the second direction Y. The RC-IGBT array 12 has a first end on one side (side surface 5B side) and a second end on the other side (side surface 5D side). The RC-IGBT array 12 has a loop array including repeated IGBT regions 8, diode regions 9, IGBT regions 8, diode regions 9, ... arranged in a line along the first direction X from the first end to the second end. In the RC-IGBT array 12, a plurality of IGBT regions 8 and a plurality of diode regions 9 are alternately arranged along the first direction X.

[0017] A plurality of IGBT regions 8 are dispersed and arranged in the active region 6. The IGBT regions 8 are formed at intervals along the first direction X and the second direction Y. The IGBT regions 8 are arranged in a staggered pattern in a plan view. Specifically, each of the IGBT regions 8 is formed in a rectangular shape extending along the second direction Y. In this embodiment, the IGBT regions 8 have the same width WG (see FIG. 4 ).

[0018] Furthermore, a plurality of diode regions 9 are dispersedly arranged in the active region 6. Specifically, the plurality of diode regions 9 are each formed so as to be adjacent to an IGBT region 8 in the first direction X. The plurality of diode regions 9 are formed at intervals along the first direction X and the second direction Y. The plurality of diode regions 9 are arranged in a staggered manner in a plan view. Specifically, the diode regions 9 are each formed in a rectangular shape extending along the second direction Y. In this embodiment, the plurality of diode regions 9 have the same width WD. In this embodiment, the plurality of IGBT regions 8 and the plurality of diode regions 9 are each arranged in a staggered manner throughout the active region 6.

[0019] In this embodiment, the length of each diode region 9 is shorter than the length of each IGBT region 8. Therefore, the planar area of ​​each diode region 9 is smaller than the planar area of ​​each IGBT region 8. In plan view, the area ratio of the diode region 9 to the active region 6 is 25% or more and 45% or less. In other words, in plan view, the area ratio of the IGBT region 8 to the active region 6 is 55% or more and 75% or less.

[0020] The multiple (e.g., six) RC-IGBT arrays 12 include, in order from one side Y1 in the second direction Y, a first array 12A, a second array 12B, a third array 12C, a fourth array 12D, a fifth array 12E, and a sixth array 12F. The column widths (widths in the second direction Y) of the first array 12A and the sixth array 12F are the same. The column widths (widths in the second direction Y) of the second array 12B and the fifth array 12E are the same. The column widths (widths in the second direction Y) of the third array 12C and the fourth array 12D are the same.

[0021] The first array 12A, the third array 12C, and the fifth array 12E are arranged in the same arrangement pattern. The second array 12B, the fourth array 12D, and the sixth array 12F are arranged in the same arrangement pattern. The second array 12B, the fourth array 12D, and the sixth array 12F are shifted from the first array 12A, the third array 12C, and the fifth array 12E in the positions of the IGBT regions 8 and the diode regions 9 in the first direction X.

[0022] In this embodiment, first ends of the first array 12A, the third array 12C, and the fifth array 12E in the first direction X are formed by IGBT regions 8. The first ends of the first array 12A, the third array 12C, and the fifth array 12E may be formed by diode regions 9. In this embodiment, second ends of the first array 12A, the third array 12C, and the fifth array 12E in the first direction X are formed by IGBT regions 8. The second ends of the first array 12A, the third array 12C, and the fifth array 12E may be formed by diode regions 9.

[0023] In this embodiment, first ends of the second array 12B, the fourth array 12D, and the sixth array 12F in the first direction X are formed by IGBT regions 8. The first ends of the second array 12B, the fourth array 12D, and the sixth array 12F may be formed by diode regions 9. In this embodiment, second ends of the second array 12B, the fourth array 12D, and the sixth array 12F in the first direction X are formed by diode regions 9. The second ends of the second array 12B, the fourth array 12D, and the sixth array 12F in the first direction X may be formed by IGBT regions 8.

[0024] 4, the width WG of each IGBT region 8 may be 10 μm or more and 1000 μm or less. The width WG may be 100 μm or more. The width WG is preferably 200 μm or more.

[0025] The width WD of each diode region 9 may be equal to or less than the width WG of each IGBT region 8. The width WD is the width of the diode region 9 in the first direction X. The width WD of each diode region 9 is preferably less than the width WG of each IGBT region 8.

[0026] 1 and 2 , the active area 6 further includes a sensor area 11 in which a temperature sensor is formed. The sensor area 11 is formed in a region between two RC-IGBT arrays 12 adjacent to each other in the second direction Y. In this embodiment, the sensor area 11 is formed in the center of the active area 6.

[0027] The semiconductor device 1 further includes an emitter terminal electrode 13 (see the dashed line portion in FIG. 1 ). The emitter terminal electrode 13 is formed on the first main surface 3 of the semiconductor layer 2 in the active region 6. The emitter terminal electrode 13 transmits an emitter signal to the active region 6 (IGBT region 8). The emitter signal may be a reference potential or a ground potential.

[0028] 1 , the semiconductor device 1 further includes a plurality of (five in this embodiment) terminal electrodes 14, 15, 16, 17, and 18 formed on the first main surface 3 of the semiconductor layer 2 in the outer region 7. The plurality of terminal electrodes 14 to 18 are arranged at intervals along the side surface 5D. The plurality of terminal electrodes 14 to 18 are formed in a quadrangular shape in a plan view.

[0029] In this embodiment, the multiple terminal electrodes 14 to 18 include a gate terminal electrode 14, a first sense terminal electrode 15, a second sense terminal electrode 16, a current detection terminal electrode 17, and an open terminal electrode 18. The gate terminal electrode 14 transmits a gate signal to the active region 6 (IGBT region 8). The first sense terminal electrode 15 and the second sense terminal electrode 16 transmit a control signal for controlling the sensor region 11 (temperature sensor). The current detection terminal electrode 17 is an electrode for detecting a current flowing through the active region 6 and extracting it to the outside. The open terminal electrode 18 is in an electrically floating state. The gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17, and the open terminal electrode 18 may be arranged in any desired manner. In the example of FIG. 1 , the open terminal electrode 18, the current detection terminal electrode 17, the gate terminal electrode 14, the first sense terminal electrode 15, and the second sense terminal electrode 16 are arranged in this order from the side surface 5A to the side surface 5C.

[0030] The semiconductor device 1 further includes a gate wiring 19 electrically connected to the gate terminal electrode 14. The gate wiring 19 is also referred to as a gate finger. The gate wiring 19 extends from the outer region 7 toward the active region 6. The gate wiring 19 transmits a gate signal applied to the gate terminal electrode 14 to the active region 6 (IGBT region 8). Specifically, the gate wiring 19 includes a first region 19a located in the outer region 7 and a second region 19b located in the active region 6. The first region 19a is electrically connected to the gate terminal electrode 14. In this embodiment, the first region 19a is selectively routed in a region on the side surface 5D side in the outer region 7.

[0031] A plurality of second regions 19b (five in this embodiment) are formed in the active region 6. The second regions 19b are formed at intervals along the second direction Y. The second regions 19b are each formed in a region between two adjacent RC-IGBT arrays 12. The second regions 19b each extend from a region on the side face 5D side toward a region on the side face 5B side in the outer region 7. The second regions 19b are continuous with the first region 19a in the outer region 7. The second regions 19b transmit gate signals to one or both of the two adjacent RC-IGBT arrays 12.

[0032] A gate signal applied to the gate terminal electrode 14 is transmitted to the second region 19b via the first region 19a, whereby the gate signal is transmitted to the active region 6 (IGBT region 8) via the second region 19b.

[0033] A first sense wiring 20 is electrically connected to the first sense terminal electrode 15. The first sense wiring 20 extends from the outer region 7 toward the sensor region 11. The first sense wiring 20 transmits a control signal for the temperature sensor. Specifically, the first sense wiring 20 includes a first region 20a located in the outer region 7 and a second region 20b located in the active region 6. The first region 20a is electrically connected to the first sense terminal electrode 15. The second region 20b is electrically connected to the temperature sensor in the sensor region 11. The second region 20b is continuous with the first region 20a in the outer region 7. An electrical signal applied to the first sense terminal electrode 15 is transmitted to the second region 20b via the first region 20a. As a result, the electrical signal is transmitted to the temperature sensor via the second region 20b.

[0034] A second sense wiring 21 is electrically connected to the second sense terminal electrode 16. The second sense wiring 21 extends from the outer region 7 toward the sensor region 11. The second sense wiring 21 transmits a control signal for the temperature sensor. Specifically, the second sense wiring 21 includes a first region 21a located in the outer region 7 and a second region 21b located in the active region 6. The first region 21a is electrically connected to the second sense terminal electrode 16. The second region 21b is electrically connected to the temperature sensor in the sensor region 11. The second region 21b is continuous with the first region 21a in the outer region 7. An electrical signal applied to the second sense terminal electrode 16 is transmitted to the second region 21b via the first region 21a. As a result, the electrical signal is transmitted to the temperature sensor via the second region 21b.

[0035] In the region where the sensor region 11 is formed between the adjacent RC-IGBT arrays 12, a gate wiring 19, a first sense wiring 20, and a second sense wiring 21 are formed. The gate wiring 19, the first sense wiring 20, and the second sense wiring 21 run parallel to each other in the region between the two adjacent RC-IGBT arrays 12.

[0036] 1 and 5A, the following description focuses on each IGBT region 8 included in the active region 6. For example, the third IGBT region 8B from the other side (side surface 5D) included in the second array 12B will be taken as an example.

[0037] The IGBT region 8B is adjacent to two diode regions 9B on both sides in the first direction X (horizontal direction on the paper). The IGBT region 8B is further adjacent to two diode regions 9A, 9C on both sides in the second direction Y (vertical direction on the paper). Meanwhile, the IGBT region 8B is adjacent to two IGBT regions 8A and two IGBT regions 8C that are independent of the IGBT region 8B on both sides in two diagonal directions that intersect both the first direction X and the second direction Y. This forms a unit array UA of IGBT regions 8 and diode regions 9 in a staggered pattern that covers the entire active region 6. In the unit array UA, the IGBT region 8B located at the center is a reference IGBT region that serves as a reference region. In the unit array UA, four diode regions 9A, 9C on both sides of the IGBT region 8B in the first direction X (horizontal direction on the paper) and the second direction Y (vertical direction on the paper) are heterogeneous diode regions as heterogeneous regions. In the unit array UA, four IGBT regions 8A, 8C adjacent to the IGBT region 8B on both sides of two diagonal directions intersecting both the first direction X and the second direction Y as viewed from the IGBT region 8B and independent from the IGBT region 8B are homogeneous IGBT regions as homogeneous regions.

[0038] Specifically, the IGBT region 8B is adjacent to each of the two diode regions 9B included in the same RC-IGBT array (second array 12B) in the first direction X. In other words, the IGBT region 8B faces each of the two diode regions 9B on either side of it in the first direction X, with a boundary region 72 (see also FIG. 10 ) sandwiched therebetween.

[0039] The IGBT region 8B faces one diode region 9A included in the RC-IGBT array (first array 12A) adjacent to it on one side Y1 in the second direction Y, across one or more second regions 19b of the gate wiring 19 (one in the example of FIG. 5A ; hereinafter, sometimes referred to as "first gate wiring 19bA" (see FIG. 5A )). The IGBT region 8B faces each of the two IGBT regions 8A on both sides of the diode region 9A in the first direction X, across the first gate wiring 19bA, in the second direction Y. The IGBT region 8A is an IGBT region independent from the IGBT region 8B.

[0040] 5A and 5B , the IGBT region 8B faces the IGBT region 8A on one side (side surface 5B side) with a first facing width (facing width) W1. The IGBT region 8B faces the IGBT region 8A on the other side (side surface 5D side) with a second facing width (facing width) W2. The combined width of the first facing width W1 and the second facing width W2 is narrower than the width WG of the IGBT region 8. In the example of FIGS. 5A and 5B , the first facing width W1 is the same as the second facing width W2. The first facing width W1 may be wider than the second facing width W2. The first facing width W1 may be narrower than the second facing width W2.

[0041] 5B , the ratio W1 / WG of the first opposing width W1 to the width WG of the IGBT region 8 (IGBT region 8B) may be 0.001 or more and less than 0.5. W1 / WG may be 0.001 or more and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.35 or more and 0.4 or less, 0.4 or more and 0.45 or less, or 0.45 or more and less than 0.5.

[0042] The first opposing width W1 may be 0.1 μm or more and less than 500 μm. The first opposing width W1 may be 0.1 μm or more and less than 50 μm, 50 μm or more and less than 100 μm, 100 μm or more and less than 150 μm, 150 μm or more and less than 200 μm, 200 μm or more and less than 250 μm, 250 μm or more and less than 300 μm, 300 μm or more and less than 350 μm, 350 μm or more and less than 400 μm, 400 μm or more and less than 450 μm, or 450 μm or more and less than 500 μm.

[0043] The first facing width W1 may be wider than the first distance W5 between the IGBT region 8 and the diode region 9 facing each other in the second direction Y. The first facing width W1 may be the same as the first distance W5. The first facing width W1 may be narrower than the first distance W5.

[0044] The first opposing width W1 may be wider than the second distance W4 between two IGBT regions 8 opposing each other in the second direction Y. The first opposing width W1 may be the same as the second distance W4. The first opposing width W1 may be narrower than the second distance W4.

[0045] The first opposing width W1 may be wider than the line width W3 of the second region 19b of the gate wiring 19. The first opposing width W1 may be the same as the line width W3 of the second region 19b. The first opposing width W1 may be narrower than the line width W3 of the second region 19b.

[0046] The ratio W2 / WG of the second opposing width W2 to the width WG of the IGBT region 8 (IGBT region 8B) may be 0.001 or more and less than 0.5. W2 / WG may be 0.001 or more and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.35 or more and 0.4 or less, 0.4 or more and 0.45 or less, or 0.45 or more and less than 0.5.

[0047] The second opposing width W2 may be 0.1 μm or more and 500 μm or less. The second opposing width W2 may be 0.1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or less, 400 μm or more and 450 μm or less, or 450 μm or more and less than 500 μm.

[0048] The second facing width W2 may be wider than the first distance W5 between the IGBT region 8 and the diode region 9 facing each other in the second direction Y. The second facing width W2 may be the same as the first distance W5. The second facing width W2 may be narrower than the first distance W5.

[0049] The second opposing width W2 may be wider than the second interval W4 between two IGBT regions 8 opposing each other in the second direction Y. The second opposing width W2 may be the same as the second interval W4. The second opposing width W2 may be narrower than the second interval W4.

[0050] The second opposing width W2 may be wider than the line width W3 of the second region 19b of the gate wiring 19. The second opposing width W2 may be the same as the line width W3 of the second region 19b. The second opposing width W2 may be narrower than the line width W3 of the second region 19b.

[0051] 1 and 5A , the IGBT region 8B faces one diode region 9C included in the RC-IGBT array 12 (third array 12C) adjacent to it on the other side Y2 in the second direction Y, across one or more second regions 19b of the gate wiring 19 (one in the example of FIG. 5A ; hereinafter, sometimes referred to as "second gate wiring 19bB" (see FIG. 5A )). The IGBT region 8B faces each of the two IGBT regions 8C on both sides of the diode region 9B in the first direction X, across the second gate wiring 19bB. The second gate wiring 19bB is another gate wiring extending parallel to the first gate wiring 19bA. The IGBT region 8 and the diode region 9 included in one RC-IGBT array 12 (third array 12C) are sandwiched in the second direction Y by the first gate wiring 19bA and the second gate wiring 19bB. The IGBT region 8C is an IGBT region independent from the IGBT region 8B.

[0052] The IGBT region 8B faces the IGBT region 8C on one side (side surface 5B side) of the diode region 9C across a first facing width W1. The IGBT region 8B faces the IGBT region 8C on the other side (side surface 5D side) of the diode region 9C across a second facing width W2.

[0053] The sum of the widths (first opposing width W1+second opposing width W2) of the portions of the IGBT region 8B, which is the reference IGBT region, that oppose the IGBT regions 8A and 8C, which are identical IGBT regions, in the second direction Y is narrow. In the unit array UA, when a current flows through the IGBT region 8, the amount of heat generated does not increase locally in the unit array UA. In the unit array UA, when a current flows through the diode region 9, the amount of heat generated does not increase locally in the unit array UA.

[0054] 5A and 5B , the following can be said about the arrangement of the IGBT regions 8 and the diode regions 9 included in the multiple RC-IGBT arrays 12. That is, the multiple IGBT regions 8 included in each of the arrays 12A to 12F face, in the second direction Y, each of the multiple diode regions 9 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y. Furthermore, the multiple diode regions 9 included in each of the arrays 12A to 12F face, in the second direction Y, each of the multiple IGBT regions 8 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y.

[0055] In the IGBT region 8 and the diode region 9 facing each other in the second direction Y, the center of the IGBT region 8 in the first direction X and the center of the diode region 9 in the first direction X are aligned with each other in the first direction X. In other words, a plurality of IGBT regions 8 and a plurality of diode regions 9 are alternately arranged along the second direction Y.

[0056] Furthermore, one IGBT region 8 included in each of the arrays 12A to 12F is further opposed in the second direction Y to two IGBT regions 8 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y. The sum of the widths of the portions of one IGBT region 8 opposed to the two IGBT regions 8 in the second direction Y (first opposed width W1+second opposed width W2) is narrower than the width WG of the IGBT region 8. In other words, the sum of the widths of the portions of the IGBT regions 8 continuous in the second direction Y opposed to each other in the second direction Y (first opposed width W1+second opposed width W2) in the active region 6 is narrow.

[0057] One diode region 9 included in each of the arrays 12A to 12F does not face, in the second direction Y, the diode region 9 included in the RC-IGBT array (arrays 12A to 12F) adjacent to that array 12A to 12F in the second direction Y. Therefore, the diode regions 9 are not continuous in the second direction Y.

[0058] 3, semiconductor device 1 further includes a collector terminal electrode 32 (see the dashed line portion in FIG. 3) formed on second main surface 4 of semiconductor layer 2. Collector terminal electrode 32 is specifically electrically connected to IGBT region 8 (collector region 34 described next) and diode region 9 (cathode region 61 described next).

[0059] The collector terminal electrode 32 forms an ohmic contact with the second main surface 4. The collector terminal electrode 32 transmits a collector signal to the IGBT region 8 and the diode region 9. The collector terminal electrode 32 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The collector terminal electrode 32 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The collector terminal electrode 32 may have a layered structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are layered in any manner.

[0060] Each IGBT region 8 includes a p-type (second conductivity type) collector region 34 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The collector region 34 is exposed from the second main surface 4. The p-type impurity concentration of the collector region 34 is 1.0×10 １５ cm -３ Above 1.0 x 10 １８ cm -３ The collector region 34 forms an ohmic contact with the collector terminal electrode 32. In this embodiment, the collector region 34 is formed in the surface layer portion of the second main surface 4 over the entire IGBT region 8.

[0061] Each diode region 9 is formed in the surface layer portion of the second main surface 4 of the semiconductor layer 2. ＋ The cathode region 61 includes an n-type cathode region 61. The n-type impurity concentration of the cathode region 61 is higher than the n-type impurity concentration of the drift region 30 (see FIG. 9 and the like) described below. The cathode region 61 is exposed from the second main surface 4. The n-type impurity concentration of the cathode region 61 is 1.0×10 １９ cm -３ Above 1.0 x 10 ２０ cm -３The cathode region 61 forms ohmic contact with the collector terminal electrode 32. In this embodiment, the cathode region 61 is formed in the entire IGBT region 8 in the surface layer portion of the second main surface 4.

[0062] Fig. 6 is an enlarged view of a portion surrounded by dashed line VI in Fig. 4. Fig. 7 is an enlarged view of a portion surrounded by dashed line VII in Fig. 6. Fig. 8 is an enlarged view of a portion surrounded by dashed line VIII in Fig. 6. Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 7. Fig. 10 is a cross-sectional view taken along line XX in Fig. 8. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 7.

[0063] 9 to 11, semiconductor device 1 includes n-type junctions formed inside semiconductor layer 2. - The semiconductor layer 2 further includes an n-type drift region 30. Specifically, the drift region 30 is formed over the entire semiconductor layer 2 in the first direction X and the second direction Y. The drift region 30 is formed in a surface layer portion of the first main surface 3 of the semiconductor layer 2 in the normal direction Z (thickness direction of the semiconductor layer 2). The n-type (first conductivity type) impurity concentration of the drift region 30 is 1.0×10 １３ cm -３ Above 1.0 x 10 １５ cm -３ It may be the following:

[0064] In this embodiment, the semiconductor layer 2 is - The drift region 30 has a single-layer structure including a floating zone (FZ) substrate 31. The floating zone (FZ) substrate 31 may be a silicon substrate formed by a floating zone (FZ) method.

[0065] The semiconductor device 1 includes an n-type buffer layer 33 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The buffer layer 33 may be formed over the entire surface layer portion of the second main surface 4. The n-type impurity concentration of the buffer layer 33 is higher than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the buffer layer 33 is 1.0×10 １５ cm -３ Above 1.0 x 10 １７ cm -３The thickness of the buffer layer 33 may be 0.5 μm or more and 30 μm or less.

[0066] Each IGBT region 8 includes a p-type (second conductivity type) collector region 34 formed in a surface layer portion of the second main surface 4 of the semiconductor layer 2. The collector region 34 is exposed from the second main surface 4. The collector region 34 may be formed in the surface layer portion of the second main surface 4 over the entire IGBT region 8. The p-type impurity concentration of the collector region 34 is 1.0×10 １５ cm -３ Above 1.0 x 10 １８ cm -３ The collector region 34 forms an ohmic contact with the collector terminal electrode 32 .

[0067] 6 to 11 , each IGBT region 8 includes a plurality of FET structures 35 formed on the first main surface 3 of the semiconductor layer 2. Specifically, the FET structures 35 include trench gate structures 36 formed on the first main surface 3. A plurality of trench gate structures 36 are formed at intervals along the first direction X in the IGBT region 8. The distance between two trench gate structures 36 adjacent to each other in the first direction X may be 1 μm or more and 8 μm or less. In FIGS. 6 to 8 , the trench gate structures 36 are indicated by hatching.

[0068] The plurality of trench gate structures 36 are formed in a band shape extending along the second direction Y in a plan view. The plurality of trench gate structures 36 are formed in a stripe shape as a whole. Each of the plurality of trench gate structures 36 has one end on one side in the second direction Y and the other end on the other side in the second direction Y.

[0069] 4 and 5B , the trench gate structure 36 includes a first outer trench gate structure 37 and a second outer trench gate structure 38. The first outer trench gate structure 37 extends along the first direction X and connects one ends of the plurality of trench gate structures 36. The second outer trench gate structure 38 extends along the first direction X and connects the other ends of the plurality of trench gate structures 36.

[0070] Except for the fact that the first outer trench gate structure 37 and the second outer trench gate structure 38 extend in different directions, they have the same structure as the trench gate structure 36. Below, the structure of the trench gate structure 36 will be described, and descriptions of the structures of the first outer trench gate structure 37 and the second outer trench gate structure 38 will be omitted.

[0071] 9 to 11 , each trench gate structure 36 includes a gate trench 39, a gate insulating layer 40, and a gate conductive layer 41. The gate trench 39 is formed in the first main surface 3. The gate trench 39 includes sidewalls and a bottom wall. The sidewalls of the gate trench 39 may be formed perpendicular to the first main surface 3.

[0072] The sidewalls of the gate trench 39 may slope downward from the first main surface 3 toward the bottom wall. The gate trench 39 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the gate trench 39 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 39 may be formed in a curved shape toward the second main surface 4. The gate trench 39 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the gate trench 39. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

[0073] The depth D1 of the gate trench 39 may be 2 μm or more and 10 μm or less. The depth D1 of the gate trench 39 may be defined as the distance between the deepest depth position of the bottom wall of the gate trench 39 and the first main surface 3. The width of the gate trench 39 may be 0.5 μm or more and 3 μm or less. The width of the gate trench 39 is the width of the gate trench 39 in the first direction X.

[0074] The gate insulating layer 40 is formed in a film shape along the inner wall of the gate trench 39. The gate insulating layer 40 defines a recess space within the gate trench 39. In this embodiment, the gate insulating layer 40 includes a silicon oxide film. The gate insulating layer 40 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0075] The gate conductive layer 41 is embedded in the gate trench 39 with the gate insulating layer 40 sandwiched therebetween. Specifically, the gate conductive layer 41 is embedded in a recess space defined by the gate insulating layer 40 in the gate trench 39. The gate conductive layer 41 is controlled by a gate signal. The gate conductive layer 41 may include conductive polysilicon.

[0076] The gate conductive layer 41 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The gate conductive layer 41 has an upper end portion located on the opening side of the gate trench 39. The upper end portion of the gate conductive layer 41 is located on the bottom wall side of the gate trench 39 with respect to the first main surface 3.

[0077] A recess recessed toward the bottom wall of the gate trench 39 is formed at the upper end of the gate conductive layer 41. The recess at the upper end of the gate conductive layer 41 is formed in a tapered shape toward the bottom wall of the gate trench 39. The upper end of the gate conductive layer 41 has a constricted portion that is constricted inside the gate conductive layer 41.

[0078] 9 and 10 , FET structure 35 includes a p-type body region 45 formed in a surface layer portion of first main surface 3 of semiconductor layer 2. The p-type impurity concentration of body region 45 is 1.0×10 １７ cm -３ Above 1.0 x 10 １８ cm -３ The body region 45 may be formed on both sides of the trench gate structure 36. The body region 45 is formed in a strip shape extending along the trench gate structure 36 in a plan view. The body region 45 is exposed from the sidewall of the gate trench 39. The bottom of the body region 45 is formed in a region between the first main surface 3 and the bottom wall of the gate trench 39 in the normal direction Z.

[0079] The FET structure 35 is formed in the surface layer of the body region 45. ＋ The n-type impurity concentration of the emitter region 46 is greater than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the emitter region 46 is 1.0×10 １９ cm -３ Above 1.0 x 10２０ cm -３ It may be the following:

[0080] In this embodiment, the FET structure 35 includes a plurality of emitter regions 46 formed on both sides of the trench gate structure 36. The emitter regions 46 are formed in strip shapes extending along the trench gate structure 36 in a plan view. The emitter regions 46 are exposed from the first main surface 3 and the sidewalls of the gate trench 39. The bottoms of the emitter regions 46 are formed in regions between the upper end of the gate conductive layer 41 and the bottom of the body region 45 in the normal direction Z.

[0081] In this embodiment, the FET structure 35 is an n-type FET formed in a region of the semiconductor layer 2 on the second main surface 4 side with respect to the body region 45. ＋ The n-type impurity concentration of the carrier storage region 47 is greater than the n-type impurity concentration of the drift region 30. The n-type impurity concentration of the carrier storage region 47 is 1.0×10 １５ cm -３ Above 1.0 x 10 １７ cm -３ It may be the following:

[0082] In this embodiment, the FET structure 35 includes a plurality of carrier storage regions 47 formed on both sides of the trench gate structure 36. The carrier storage regions 47 are formed in strip shapes extending along the trench gate structure 36 in a plan view. The carrier storage regions 47 are exposed from the sidewalls of the gate trench 39. The bottoms of the carrier storage regions 47 are formed in regions between the bottoms of the body regions 45 and the bottom walls of the gate trenches 39 in the normal direction Z.

[0083] The carrier storage region 47 prevents carriers (holes) supplied to the semiconductor layer 2 from being drawn back (discharged) to the body region 45. This causes holes to accumulate in the region directly below the FET structure 35 in the semiconductor layer 2. As a result, the on-resistance and the on-voltage are reduced.

[0084] The FET structure 35 includes a contact trench 48 formed in the first major surface 3 of the semiconductor layer 2. In this embodiment, the FET structure 35 includes a plurality of contact trenches 48 formed on both sides of the trench gate structure 36. The contact trenches 48 expose the emitter regions 46. In this embodiment, the contact trenches 48 extend through the emitter regions 46.

[0085] The contact trench 48 is formed at a distance from the trench gate structure 36 in the first direction X. The contact trench 48 extends in a strip shape along the trench gate structure 36 in a plan view. In the second direction Y, the length of the contact trench 48 is equal to or less than the length of the trench gate structure 36. Specifically, the length of the contact trench 48 is less than the length of the trench gate structure 36.

[0086] The FET structure 35 includes a p-type semiconductor layer formed in the body region 45 along the bottom wall of the contact trench 48. ＋ The p-type impurity concentration of the contact region 49 is greater than the p-type impurity concentration of the body region 45. The p-type impurity concentration of the contact region 49 is 1.0×10 １９ cm -３ Above 1.0 x 10 ２０ cm -３ It may be the following:

[0087] The contact region 49 is exposed from the bottom wall of the contact trench 48. In a plan view, the contact region 49 extends in a strip shape along the contact trench 48. The bottom of the contact region 49 is formed in a region between the bottom wall of the contact trench 48 and the bottom of the body region 45 in the normal direction Z.

[0088] Thus, in the FET structure 35, the gate conductive layer 41 faces the body region 45 and the emitter region 46 with the gate insulating layer 40 sandwiched therebetween. In this embodiment, the gate conductive layer 41 also faces the carrier storage region 47 with the gate insulating layer 40 sandwiched therebetween. The channel of the IGBT is formed in the region in the body region 45 between the emitter region 46 and the drift region 30 (carrier storage region 47). The on / off of the channel is controlled by a gate signal.

[0089] Each IGBT region 8 further includes an emitter trench structure 73 formed in the first main surface 3 of the semiconductor layer 2. Specifically, each IGBT region 8 includes a plurality of emitter trench structures 73 formed on both sides of the FET structure 35. The emitter trench structures 73 are formed in regions adjacent to the FET structure 35 in the surface layer portion of the first main surface 3. The emitter trench structures 73 are formed in a strip shape extending along the second direction Y in a plan view. The plurality of emitter trench structures 73 are formed in a stripe shape as a whole. The emitter trench structures 73 may be strip-shaped and parallel to the trench gate structures 36.

[0090] 6 and 7 , in each IGBT region 8, the trench gate structures 36 and the emitter trench structures 73 are alternately arranged at intervals along the first direction X. The trench gate structures 36 and the emitter trench structures 73 may be alternately arranged at equal intervals. The distance between two adjacent trench gate structures 36 and emitter trench structures 73 in the first direction X (first pitch P1 (see FIG. 7 )) may be, for example, not less than 1.0 μm and not more than 3.5 μm.

[0091] 9 and 10 , the emitter trench structure 73 includes an emitter trench 74, an emitter insulating layer 75, and an emitter potential electrode layer 76. The emitter trench 74 is formed in the first main surface 3 of the semiconductor layer 2. The emitter trench 74 includes a sidewall and a bottom wall. The sidewall of the emitter trench 74 may be formed perpendicular to the first main surface 3.

[0092] The sidewalls of the emitter trench 74 may slope downward from the first main surface 3 toward the bottom wall. The emitter trench 74 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The emitter region 46, the body region 45, and the carrier storage region 47 are exposed from the sidewalls (outer sidewalls) of the emitter trench 74 facing the FET structure 35. The bottom wall of the emitter trench 74 may be formed parallel to the first main surface 3. The bottom wall of the emitter trench 74 may be formed in a curved shape toward the second main surface 4. The emitter trench 74 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the emitter trench 74. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4 of the semiconductor layer 2.

[0093] The depth D3 of the emitter trench 74 may be not less than 2 μm and not more than 10 μm. The depth D3 of the emitter trench 74 may be equal to the depth D1 of the gate trench 39. The width of the emitter trench 74 may be not less than 0.5 μm and not more than 3 μm. The width of the emitter trench 74 is the width of the emitter trench 74 in the first direction X. The width of the emitter trench 74 may be equal to the width of the gate trench 39.

[0094] The emitter insulating layer 75 is formed in a film shape along the inner wall of the emitter trench 74. The emitter insulating layer 75 defines a recess space within the emitter trench 74. In this embodiment, the emitter insulating layer 75 includes a silicon oxide film. The emitter insulating layer 75 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0095] The emitter potential electrode layer 76 is embedded in the emitter trench 74 with the emitter insulating layer 75 sandwiched therebetween. Specifically, the emitter potential electrode layer 76 is embedded in a recess space defined by the emitter insulating layer 75 in the emitter trench 74. The emitter potential electrode layer 76 may include conductive polysilicon. The emitter potential electrode layer 76 is controlled by an emitter signal.

[0096] The emitter potential electrode layer 76 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The emitter potential electrode layer 76 has an upper end portion located on the opening side of the emitter trench 74. The upper end portion of the emitter potential electrode layer 76 is located on the bottom wall side of the emitter trench 74 with respect to the first main surface 3.

[0097] A recess that recesses toward the bottom wall of the emitter trench 74 is formed at the upper end of the emitter potential electrode layer 76. The recess at the upper end of the emitter potential electrode layer 76 is formed in a tapered shape that tapers toward the bottom wall of the emitter trench 74. The upper end of the emitter potential electrode layer 76 has a constricted portion that is constricted inside the emitter potential electrode layer 76.

[0098] 6 and 8, each diode region 9 includes a cell isolation structure 63 that defines a diode cell region 69. The cell isolation structure 63 is indicated by hatching in Figures 6 and 8. Specifically, each diode region 9 includes a plurality of cell isolation structures 63 that define a plurality of diode cell regions 69, respectively.

[0099] The plurality of cell isolation structures 63 are each formed in a region between adjacent plurality of diode cell regions 69. Specifically, the plurality of cell isolation structures 63 are each formed in a ring shape (a square ring shape in this embodiment) surrounding the diode cell region 69 in a plan view. The cell isolation structure 63 that partitions one diode cell region 69 and the cell isolation structure 63 that partitions the other diode cell region 69 are integrally formed in the region between adjacent plurality of diode cell regions 69.

[0100] The multiple cell separation structures 63 may be arranged at equal intervals in the first direction X. The multiple cell separation structures 63 are formed in a stripe pattern. The distance between two adjacent cell separation structures 63 in the first direction X (second pitch P2 (see FIG. 8)) may be, for example, 1.0 μm or more and 10.0 μm or less. The second pitch P2 may be the same as the first pitch P1 (see FIG. 7).

[0101] In this embodiment, the diode cell regions 69, which are partitioned by the cell isolation structures 63, are formed at intervals along the first direction X in a plan view. The diode cell regions 69 are each formed in a band shape extending along the second direction Y in a plan view. The diode cell regions 69 are formed in a stripe shape as a whole. With respect to the second direction Y, the length of the diode cell regions 69 may be equal to or less than the length of the trench gate structure 36. The length of the diode cell regions 69 may be shorter than the length of the trench gate structure 36.

[0102] 10 , the cell isolation structure 63 includes a cell isolation trench 64, a cell isolation insulating layer 65, and a cell isolation electrode layer 66. The cell isolation trench 64 is formed in the first main surface 3. The cell isolation trench 64 includes a sidewall and a bottom wall. The sidewall of the cell isolation trench 64 may be formed perpendicular to the first main surface 3.

[0103] The sidewalls of the cell separation trench 64 may slope downward from the first main surface 3 toward the bottom wall. The cell separation trench 64 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the cell separation trench 64 may be formed parallel to the first main surface 3. The bottom wall of the cell separation trench 64 may be formed in a curved shape toward the second main surface 4. The cell separation trench 64 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the cell separation trench 64. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

[0104] The depth D2 of the cell isolation trench 64 may be 2 μm or more and 10 μm or less. The depth D2 of the cell isolation trench 64 may be defined as the distance between the deepest depth position of the bottom wall of the cell isolation trench 64 and the first main surface 3. The depth D2 of the cell isolation trench 64 may be equal to the depth D1 of the gate trench 39 (see FIG. 9 , etc.). The width of the cell isolation trench 64 may be 0.5 μm or more and 3 μm or less. The width of the cell isolation trench 64 is the width of the cell isolation trench 64 in the first direction X. The width of the cell isolation trench 64 may be equal to the width of the gate trench 39.

[0105] The cell isolation insulating layer 65 is formed in the form of a film along the inner wall of the cell isolation trench 64. The cell isolation insulating layer 65 defines a recess space within the cell isolation trench 64. In this embodiment, the cell isolation insulating layer 65 includes a silicon oxide film. The cell isolation insulating layer 65 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0106] The cell isolation electrode layer 66 is embedded in the cell isolation trench 64 with the cell isolation insulating layer 65 sandwiched therebetween. Specifically, the cell isolation electrode layer 66 is embedded in a recess space defined by the cell isolation insulating layer 65 in the cell isolation trench 64. The cell isolation electrode layer 66 is controlled by an emitter signal. The cell isolation electrode layer 66 may include conductive polysilicon.

[0107] The cell separation electrode layer 66 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The cell separation electrode layer 66 has an upper end portion located on the opening side of the cell separation trench 64. The upper end portion of the cell separation electrode layer 66 is located on the bottom wall side of the cell separation trench 64 with respect to the first main surface 3.

[0108] The upper end of the cell separation electrode layer 66 is formed in a tapered shape toward the first main surface 3. A recess that is recessed toward the bottom wall of the cell separation trench 64 is formed at the upper end of the cell separation electrode layer 66. The recess of the cell separation electrode layer 66 is formed in a tapered shape toward the bottom wall of the cell separation trench 64.

[0109] Each diode region 9 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2. - The anode region 62 includes a p-type impurity concentration of 1.0×10. The anode region 62 may have a p-type impurity concentration equal to or lower than the p-type impurity concentration of the body region 45. The anode region 62 preferably has a p-type impurity concentration lower than the p-type impurity concentration of the body region 45. The anode region 62 has a p-type impurity concentration of 1.0×10. １５ cm -３ Above 1.0 x 10 １８ cm -３ It may be less than.

[0110] The anode region 62 is formed in each diode cell region 69. Therefore, the multiple anode regions 62 are arranged at equal intervals in the first direction X, forming a stripe pattern overall. The anode region 62 forms a pn junction 68 with the semiconductor layer 2. This forms a pn junction diode D, with the anode region 62 serving as the anode and the semiconductor layer 2 (cathode region 61) serving as the cathode. When the pn junction diode D switches from an off state to an on state, a forward current flows through the pn junction diode D. This causes a current to flow in the diode region 9.

[0111] In this embodiment, the boundary in the first direction X between the collector region 34 and the cathode region 61 is aligned with the boundary region 72 between the IGBT region 8 and the diode region 9 in plan view.

[0112] Within the cell isolation trench 64, a recess 67 is defined by the sidewall of the cell isolation trench 64, the upper end of the cell isolation electrode layer 66, and the upper end of the cell isolation insulating layer 65. The wide portion of the cell isolation trench 64 is formed by the recess 67. The sidewall of the recess 67 (the sidewall of the cell isolation trench 64) exposes the anode region 62.

[0113] As described above, the sidewall of the terminal emitter trench structure 73A on the side closer to the diode region 9 forms the boundary region 72 between the IGBT region 8 and the diode region 9. In the region between the terminal emitter trench structure 73A and the cell isolation structure 63 closest to the IGBT region 8, the body region 45 and the carrier storage region 47 are formed in this order from the first main surface 3 side, similar to the FET structure 35. However, this region does not have the emitter region 46 formed therein, and is not a structure that forms a channel, so it may also be referred to as a dummy FET structure 42. The dummy FET structure 42 is formed in the diode region 9.

[0114] 9 to 11 , semiconductor device 1 includes an interlayer insulating layer 79 formed on first main surface 3 of semiconductor layer 2. Interlayer insulating layer 79 is formed in the form of a film along first main surface 3, and selectively covers first main surface 3. Specifically, interlayer insulating layer 79 selectively covers IGBT region 8 and diode region 9.

[0115] The interlayer insulating layer 79 may contain silicon oxide or silicon nitride. The interlayer insulating layer 79 may contain at least one of non-doped silicate glass (NSG), phosphorus silicate glass (PSG), and boron phosphorus silicate glass (BPSG). The thickness of the interlayer insulating layer 79 may be 0.1 μm or more and 1 μm or less.

[0116] In this embodiment, the interlayer insulating layer 79 has a stacked structure including a first insulating layer 80, a second insulating layer 81, and a third insulating layer 82 stacked in this order from the first main surface 3 side. The first insulating layer 80 may include silicon oxide (e.g., a thermal oxide film). The second insulating layer 81 may include an NGS layer, a PSG layer, or a BPSG layer. The third insulating layer 82 may include a BPSG layer, an NGS layer, or a PSG layer. The third insulating layer 82 may include an insulating material having properties different from those of the second insulating layer 81.

[0117] The first insulating layer 80 is formed in a film shape on the first main surface 3. The first insulating layer 80 is continuous with the gate insulating layer 40, the region isolation insulating layer 55, and the cell isolation insulating layer 65. The thickness of the first insulating layer 80 may be 500 Å or more and 2000 Å or less. The second insulating layer 81 is formed in a film shape on the first insulating layer 80. The thickness of the second insulating layer 81 may be 500 Å or more and 4000 Å or less. The third insulating layer 82 is formed in a film shape on the second insulating layer 81. The thickness of the third insulating layer 82 may be 1000 Å or more and 8000 Å or less.

[0118] 11 , the gate conductive layer 41 of the FET structure 35 has a gate extraction electrode layer 41a extended from the gate trench 39 onto the first main surface 3. The gate extraction electrode layer 41a is extended from the gate trench 39 of the first outer trench gate structure 37 onto the first main surface 3. The gate extraction electrode layer 41a is extended along the second direction Y.

[0119] Specifically, the gate extraction electrode layer 41a is formed inside the interlayer insulating layer 79. The gate extraction electrode layer 41a is extended onto the first insulating layer 80 and is interposed in the region between the first insulating layer 80 and the second insulating layer 81. The gate extraction electrode layer 41a is electrically connected to the gate wiring 19 (see FIG. 1) in a region not shown. A gate signal applied to the gate terminal electrode 14 is transmitted to the gate conductive layer 41 via the gate wiring 19 and the gate extraction electrode layer 41a.

[0120] The emitter potential electrode layer 76 of the emitter trench structure 73 has an extraction electrode layer 76a that is extracted from the emitter trench 74 onto the first main surface 3. The emitter potential electrode layer 76 is extracted along the second direction Y.

[0121] Specifically, the extraction electrode layer 76a is formed inside the interlayer insulating layer 79. The extraction electrode layer 76a is extracted onto the first insulating layer 80 and is interposed in the region between the first insulating layer 80 and the second insulating layer 81. The extraction electrode layer 76a is electrically connected to the emitter terminal electrode 13. An emitter signal applied to the extraction electrode layer 76a is transmitted to the emitter potential electrode layer 76 via the extraction electrode layer 76a.

[0122] 10 , the interlayer insulating layer 79 includes an emitter opening 83. The emitter opening 83 exposes the contact trench 48. The emitter opening 83 communicates with the contact trench 48. In this embodiment, the contact trench 48 is formed in the first main surface 3, penetrating the first insulating layer 80 and the second insulating layer 81.

[0123] The emitter opening 83 penetrates the third insulating layer 82 and exposes the contact trench 48. The emitter opening 83 forms an opening between itself and the contact trench 48. The edge of the emitter opening 83 is curved inwardly of the interlayer insulating layer 79. As a result, the emitter opening 83 has a larger opening width than the contact trench 48.

[0124] The interlayer insulating layer 79 includes a diode opening 84. The diode opening 84 exposes the diode region 9. Specifically, the diode opening 84 penetrates the interlayer insulating layer 79 and exposes the plurality of anode regions 62 (diode cell regions 69) and the plurality of cell isolation structures 63.

[0125] A portion of the inner wall of the diode opening 84 extending in the second direction Y may be located on the anode region 62. A portion of the inner wall of the diode opening 84 extending in the second direction Y may be located on the cell isolation structure 63. In the example of FIG. 10 , the portion of the inner wall of the diode opening 84 extending in the second direction Y is located on the body region 45 of the dummy FET structure 42.

[0126] 11 , interlayer insulating layer 79 includes a first opening 86. First opening 86 exposes lead electrode layer 76 a in IGBT region 8. First opening 86 is formed such that the opening width narrows from the opening side toward the bottom wall side.

[0127] 9 and 10 , semiconductor device 1 includes an emitter plug electrode 91 embedded in a portion of interlayer insulating layer 79 that covers IGBT region 8. Emitter plug electrode 91 penetrates interlayer insulating layer 79 and is electrically connected to emitter region 46 and contact region 49. Specifically, emitter plug electrode 91 is embedded in contact trench 48. Emitter plug electrode 91 is electrically connected to emitter region 46 and contact region 49 within contact trench 48.

[0128] In this embodiment, the emitter plug electrode 91 has a layered structure including a barrier electrode layer 92 and a main electrode layer 93. The barrier electrode layer 92 is formed in a film shape along the inner wall of the contact trench 48 so as to be in contact with the interlayer insulating layer 79. The barrier electrode layer 92 defines a recess space within the contact trench 48.

[0129] The barrier electrode layer 92 may have a single-layer structure including a titanium layer or a titanium nitride layer, or may have a laminated structure including a titanium layer and a titanium nitride layer, in which case the titanium nitride layer may be laminated on the titanium layer.

[0130] The main electrode layer 93 is embedded in the contact trench 48 with the barrier electrode layer 92 sandwiched therebetween. Specifically, the main electrode layer 93 is embedded in a recess space defined by the barrier electrode layer 92 in the contact trench 48. The main electrode layer 93 may contain tungsten.

[0131] 11 , semiconductor device 1 includes a first plug electrode 94 embedded in first opening 86. First plug electrode 94 is electrically connected to extraction electrode layer 76 a within first opening 86. First plug electrode 94 has a structure corresponding to that of emitter plug electrode 91. The description of emitter plug electrode 91 applies mutatis mutandis to the description of first plug electrode 94. Structures of first plug electrode 94 that are opposite to the structures described for emitter plug electrode 91 are given the same reference numerals, and descriptions thereof will be omitted.

[0132] 9 to 11, the emitter terminal electrode 13 is formed on an interlayer insulating layer 79. The emitter terminal electrode 13 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The emitter terminal electrode 13 may have a single-layer structure containing any one of these conductive materials. The emitter terminal electrode 13 may have a multilayer structure in which at least two of these conductive materials are stacked in any order. The thickness of the emitter terminal electrode 13 may be 1.0 μm or more and 6.0 μm or less.

[0133] In this embodiment, the emitter terminal electrode 13 has a layered structure including a first electrode layer 22, a second electrode layer 23, and a third electrode layer 24, which are layered in this order from the first main surface 3 side. The first electrode layer 22 may contain an aluminum-silicon-copper alloy (Al-Si-Cu). The second electrode layer 23 may contain titanium nitride (TiN). The second electrode layer 23 may also be referred to as a barrier layer. The third electrode layer 24 may also contain an aluminum-copper alloy (Al-Cu).

[0134] The emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 via an emitter plug electrode 91 on the interlayer insulating layer 79. Specifically, the emitter terminal electrode 13 extends from above the interlayer insulating layer 79 into the emitter opening 83. The emitter terminal electrode 13 is electrically connected to the emitter plug electrode 91 in the emitter opening 83. The emitter terminal electrode 13 is electrically connected to the emitter region 46 and the contact region 49 via the emitter plug electrode 91.

[0135] 10, the emitter terminal electrode 13 extends from above the interlayer insulating layer 79 into the diode opening 84 via the inner wall of the diode opening 84. The emitter terminal electrode 13 functions as an anode terminal electrode in the diode region 9.

[0136] The emitter terminal electrode 13 is in contact with the inner wall of the diode opening 84. The emitter terminal electrode 13 is electrically connected to the anode region 62 in the diode opening 84. The emitter terminal electrode 13 is electrically connected to the cell isolation electrode layer 66 in the diode opening 84. In this embodiment, the emitter terminal electrode 13 is directly connected to the anode region 62 and the cell isolation electrode layer 66.

[0137] Specifically, the emitter terminal electrode 13 extends from above the first main surface 3 into the recess 67 (cell separation trench 64) within the diode opening 84. The emitter terminal electrode 13 is connected to the cell separation electrode layer 66 within the recess 67. The emitter terminal electrode 13 is also connected to the anode region 62 on the first main surface 3 and within the recess 67. The emitter terminal electrode 13 forms ohmic contact with the anode region 62.

[0138] 11, the emitter terminal electrode 13 is electrically connected to a first plug electrode 94 on the interlayer insulating layer 79. An emitter signal is transmitted to the emitter potential electrode layer 76 via the first plug electrode 94.

[0139] Although not specifically shown, when a conducting wire (e.g., a bonding wire) is connected to the emitter terminal electrode 13, a single-layer electrode made of a nickel layer or a gold layer, or a laminated electrode including a nickel layer and a gold layer, may be formed on the emitter terminal electrode 13. In the laminated electrode, the gold layer may be formed on the nickel layer.

[0140] Although specific illustrations are omitted, the gate terminal electrode 14, the first sense terminal electrode 15, the second sense terminal electrode 16, the current detection terminal electrode 17 and the open terminal electrode 18 are formed on the interlayer insulating layer 79, similar to the emitter terminal electrode 13.

[0141] The terminal electrodes 14 to 18 may each contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The terminal electrodes 14 to 18 may each have a single-layer structure containing any one of these conductive materials. The terminal electrodes 14 to 18 may each have a layered structure in which at least two of these conductive materials are layered in any order. In this embodiment, the terminal electrodes 14 to 18 contain the same conductive material as the emitter terminal electrode 13.

[0142] When conducting wires (e.g., bonding wires) are connected to each of the terminal electrodes 14 to 18, a single-layer electrode made of a nickel layer or a gold layer, or a laminated electrode including a nickel layer and a gold layer, may be formed on each of the terminal electrodes 14 to 18. In the laminated electrode, the gold layer may be formed on the nickel layer.

[0143] Fig. 12 is a schematic plan view of a semiconductor package 101 including the semiconductor device 1. Fig. 13 is a cross-sectional view showing the mounting structure of the semiconductor package 101 of Fig. 12.

[0144] The semiconductor package 101 includes the semiconductor device 1, electrodes 102 to 107, wires 133 to 136, and a resin package 108. In Fig. 12, the resin package 108 is indicated by a two-dot chain line. As shown in Fig. 13, the semiconductor package 101 is mounted on a mounting substrate 109. Depending on the type of semiconductor device 1, the semiconductor package 101 is used as an electronic component that performs switching functions, rectifying functions, amplifying functions, etc. in an electric circuit.

[0145] The electrode 102 includes a die bonding pad (heat dissipation unit) 110 and a lead 111. The die bonding pad 110 and the lead 111 are made of a conductive material such as copper.

[0146] The die bonding pad 110 is flat. The die bonding pad 110 has an arrangement surface 110A and a back surface 110B. The arrangement surface 110A faces one side of the normal direction Z. One side of the normal direction Z coincides with the upper side of the paper in FIG. 13. The back surface 110B faces the other side of the normal direction Z. The other side of the normal direction Z coincides with the lower side of the paper in FIG. 13. The semiconductor device 1 is arranged on the arrangement surface 110A. A hole 112 is formed in the die bonding pad 110, penetrating from the arrangement surface 110A to the back surface 110B.

[0147] The lead 111 extends linearly from the die bonding pad 110. The lead 111 is for insertion mounting. As shown in FIG. 13 , the lead 111 is inserted into a hole 113. This allows the semiconductor package 101 to be mounted on a mounting substrate 109. The hole 113 is filled with solder 114 to fix the lead 111 to the mounting substrate 109. As shown in FIG. 12 , the lead 111 has a connecting portion 111A and a terminal portion 112B. The lead 111 functions as a collector terminal connected to the collector terminal electrode 32 (see the dashed line in FIG. 3 ) of the semiconductor device 1.

[0148] The connecting portion 111A is connected to the die bonding pad 110. The connecting portion 111A has a shape extending from the die bonding pad 110 in a direction intersecting with the placement surface 110A. The terminal portion 112B is connected to the connecting portion 111A. The terminal portion 112B has a portion that protrudes from the resin package 108.

[0149] Electrode 103 includes a wire bonding pad 115 and a lead 116. Electrode 104 includes a wire bonding pad 117 and a lead 118. Electrode 105 includes a wire bonding pad 119 and a lead 120. Electrode 106 includes a wire bonding pad 121 and a lead 122. Electrode 107 includes a wire bonding pad 123 and a lead 124. Wire bonding pads 115, 117, 119, 121, and 123 and leads 116, 118, 120, 122, and 124 are made of a conductive material such as copper.

[0150] 13 , the leads 116, 118, 120, 122, and 124 are inserted into the holes 113. This allows the semiconductor package 101 to be mounted on the mounting substrate 109. The holes 113 are filled with solder 114 to fix the leads 116, 118, 120, 122, and 124 to the mounting substrate 109.

[0151] Referring mainly to FIG. 13 , resin package 108 covers semiconductor device 1 and electrodes 102 to 107. Resin package 108 is made of epoxy resin. Resin package 108 has a first surface 108A and a second surface 108B. First surface 108A has a flat surface 108C and a tapered surface 108D. First surface 108A of resin package 108 contacts second main surface 4 of semiconductor device 1. Second surface 108B has a plurality of flat surfaces 108E and a plurality of tapered surfaces 108F. Screw holes 108H are formed in resin package 108. Screws 130 are inserted into screw holes 108H to fix resin package 108 to heat sink 129.

[0152] The wires 133 to 136 are made of a metal such as aluminum. The wire 133 is bonded to the emitter terminal electrode 13 of the semiconductor device 1 and the wire bonding pad 115. This electrically connects the emitter terminal electrode 13 to the wire bonding pad 115. The wire 134 is bonded to the current detection terminal electrode 17 of the semiconductor device 1 and the wire bonding pad 119. This electrically connects the current detection terminal electrode 17 to the wire bonding pad 119. The wire 135 is bonded to the first sense terminal electrode 15 or the second sense terminal electrode 16 (the first sense terminal electrode 15 in the example of FIG. 12 ) of the semiconductor device 1 and the wire bonding pad 121. This electrically connects the first sense terminal electrode 15 or the second sense terminal electrode 16 (the first sense terminal electrode 15 in the example of FIG. 12 ) to the wire bonding pad 121. The wire 136 is bonded to the gate terminal electrode 14 of the semiconductor device 1 and the wire bonding pad 123. This electrically connects the gate terminal electrode 14 to the wire bonding pad 123. The wire bonding pad 117 is not electrically connected to the semiconductor device 1.

[0153] Heat generated in the semiconductor device 1 is dissipated via the die bonding pad 110 and the heat sink 129. The placement surface 110A of the die bonding pad 110 contacts the entire second main surface 4 of the semiconductor device 1, thereby uniformly cooling the second main surface 4 of the semiconductor device 1. On the other hand, no member for dissipating heat (heat dissipation unit) contacts the first main surface 3 of the semiconductor device 1.

[0154] As described above, according to this embodiment, the plurality of IGBT regions 8 and the plurality of diode regions 9 are arranged in a staggered pattern in plan view in the active region 6. Therefore, in the active region 6, the sum of the widths of the portions of the IGBT regions 8 that are continuous in the second direction Y and that face the second direction Y (first opposing width W1+second opposing width W2) is narrow.

[0155] In the RC-IGBT semiconductor device described in Patent Document 1, a plurality of IGBT regions and a plurality of diode regions are arranged in a matrix. In the semiconductor device 1, a case is considered in which a plurality of IGBT regions 8 and a plurality of diode regions 9 are arranged in a row along the second direction Y, similar to Patent Document 1.

[0156] When the plurality of IGBT regions 8 and the plurality of diode regions 9 are aligned in a row along the second direction Y, the IGBT regions 8 that are continuous in the second direction Y face each other across a wide area, and the diode regions 9 that are continuous in the second direction Y face each other across a wide area. When the IGBT is turned on, a current flows simultaneously through the plurality of IGBT regions 8. When a current flows through the IGBT regions 8, the IGBT regions 8 generate heat. When the diode is turned on, a current flows simultaneously through the plurality of diode regions 9. When a current flows through the diode regions 9, the diode regions 9 generate heat.

[0157] When a plurality of IGBT regions 8 are arranged in a row along the second direction Y, there is a risk that the amount of heat generated will be locally large in the region where the IGBT regions 8 are arranged. Furthermore, when a plurality of diode regions 9 are arranged in a row along the second direction Y, there is a risk that the amount of heat generated will be locally large in the region where the diode regions 9 are arranged. Therefore, there is a risk that the active region 6 will become locally hot when the IGBT or the diode is on.

[0158] In particular, the center of the active region 6 is surrounded by the IGBT region 8 and the diode region 9, both of which are heat-generating regions. Therefore, the center of the active region 6 is an area that is difficult to dissipate heat. Therefore, when the IGBT or the diode is on, the center of the active region 6 may become particularly hot. On the other hand, in order to prevent the active region 6 from becoming too hot, it is possible to reduce the amount of current flowing through the IGBT region 8 and the diode region 9. However, in order to maintain high current characteristics of the RC-IGBT, it is necessary to ensure a large amount of current flowing through the IGBT region 8 and the diode region 9.

[0159] In the semiconductor device 1 according to the first embodiment, a staggered pattern (unit array UA of the staggered pattern) of IGBT regions 8 and diode regions 9 is formed over the entire active region 6. Therefore, the total width (first opposing width W1+second opposing width W2) of the portions of the IGBT regions 8 that are continuous in the second direction Y and that face the second direction Y is narrow. In addition, the plurality of diode regions 9 do not face each other in the second direction Y.

[0160] Therefore, when the IGBT and the diode are on, it is possible to suppress a local increase in the amount of heat generated in the active region 6. This makes it possible to suppress a temperature rise in the active region 6 without suppressing the amount of current flowing through the IGBT region 8 and the amount of current flowing through the diode region 9. In particular, it is possible to suppress a temperature rise in the center of the active region 6. Therefore, it is possible to reduce the maximum temperature of the semiconductor device 1 while maintaining a high current characteristic of the RC-IGBT.

[0161] Fig. 14 is a bottom view illustrating a semiconductor device 151 according to a modified example in which the collector region 34 and the cathode region 61 are modified. Fig. 14 is a view corresponding to Fig. 3. Fig. 15 is a cross-sectional view of the semiconductor device 151 according to the modified example of Fig. 14.

[0162] 14 and 15 differs from the semiconductor device 1 according to the first embodiment in that the cathode region 61 includes a lead-out region 182. The lead-out region 182 is a region that crosses the boundary region 72 (see FIG. 15 ) between the IGBT region 8 and the diode region 9 and is led out toward the IGBT region 8. The lead-out region 182 is led out from the diode region 9 to the IGBT region 8 along the first direction X.

[0163] 14 , in the semiconductor device 151, the first array 12A, the third array 12C, and the fifth array 12E, the lead-out regions 182 are formed at both ends of the cathode region 61 in the first direction X. Therefore, in the first array 12A, the third array 12C, and the fifth array 12E, the collector region 34 has a smaller area and the cathode region 61 is larger than in the semiconductor device 1 (see FIG. 3 ). FIG. 15 shows cross sections of the IGBT region 8 and the diode region 9 included in the first array 12A, the third array 12C, and the fifth array 12E, and corresponds to FIG. 10 .

[0164] On the other hand, the second array 12B, the fourth array 12D, and the sixth array 12F do not have the lead-out region 182, as in the semiconductor device 1 (see FIG. 3). In the example of FIG. 14, in the first to sixth RC-IGBT arrays 12A to 12F, the boundaries of the collector regions 34 and the cathode regions 61 are all aligned in the first direction X.

[0165] The lead-out region 182 overlaps the IGBT region 8 with a predetermined overlap width W. The start point of the overlap width W is set at the boundary region 72 between the IGBT region 8 and the diode region 9. The end point of the overlap width W is set at the boundary between the collector region 34 and the lead-out region 182.

[0166] The ratio W / WG of the overlap width W to the width WG of the IGBT region 8 (see FIG. 5B , etc.) may be 0.001 or more and 0.5 or less. The ratio W / WG may be 0.001 or more and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.35 or more and 0.4 or less, 0.4 or more and 0.45 or less, or 0.45 or more and 0.5 or less.

[0167] The overlap width W may be 1 μm or more and 200 μm or less. The overlap width W may be 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, or 150 μm or more and 200 μm or less.

[0168] The overlap width W may be 1 μm to 20 μm, 20 μm to 40 μm, 40 μm to 60 μm, 60 μm to 80 μm, 80 μm to 100 μm, 100 μm to 120 μm, 120 μm to 140 μm, 140 μm to 160 μm, 160 μm to 180 μm, or 180 μm to 200 μm. The overlap width W is preferably 10 μm to 150 μm.

[0169] The lead-out region 182 may face one or more FET structures 35 in the normal direction Z. The lead-out region 182 may face 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20 FET structures 35.

[0170] Fig. 16 is a schematic plan view of a semiconductor device 201 according to a second embodiment of the present disclosure. Fig. 17 is a plan view schematically showing the structure of a first main surface 3 of the semiconductor device 201. In the second embodiment, only the portions different from the first embodiment will be mainly described, and the same reference numerals will be used to designate the same components as those described so far, and description thereof will be omitted.

[0171] The semiconductor device 201 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that the area ratio of the diode region 9 to the active region 6 is approximately 50%. In other words, the area ratio of the IGBT 8 to the active region 6 in plan view is approximately 50%. In the active region 6, the planar area of ​​the IGBT 8 and the planar area of ​​the diode region 9 are approximately the same. The width WG of each IGBT region 8 (see FIG. 17) is approximately the same as the width WD of each diode region 9 (see FIG. 17).

[0172] In the semiconductor device 201, a plurality of IGBT regions 8 and a plurality of diode regions 9 are arranged in a staggered pattern in a plan view throughout the active region 6. That is, a staggered pattern (unit array UA of the staggered pattern) of the IGBT regions 8 and the diode regions 9 is formed throughout the active region 6.

[0173] In the semiconductor device 201, each IGBT region 8 faces one diode region 9 included in the RC-IGBT arrangement adjacent to it in the second direction Y, across the second region 19b of the gate wiring 19. Each IGBT region 8 does not face, in the second direction Y, an IGBT region 8 included in the RC-IGBT arrangement adjacent to it in the second direction Y.

[0174] Each diode region 9 faces one IGBT region 8 included in the RC-IGBT array 12 adjacent thereto in the second direction Y, across the second region 19b of the gate wiring 19. Each diode region 9 does not face, in the second direction Y, the diode region 9 included in the RC-IGBT array 12 adjacent thereto in the second direction Y.

[0175] According to the second embodiment, in the active region 6, the multiple IGBT regions 8 and the multiple diode regions 9 are each arranged in a staggered pattern in a plan view. Not only the multiple diode regions 9, but also the multiple IGBT regions 8 do not face the second direction Y. Therefore, compared to the first embodiment, it is possible to further suppress a local increase in the amount of heat generated in the active region 6 when the IGBTs and diodes are on. This makes it possible to further suppress a temperature rise in the active region 6.

[0176] Fig. 18 is a schematic plan view of a semiconductor device 301 according to a third embodiment of the present disclosure, Fig. 19 is a plan view schematically showing the structure of a first main surface 3 of the semiconductor device 301.

[0177] The semiconductor device 301 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that the staggered pattern (unit array UA of the staggered pattern) of the IGBT regions 8 and the diode regions 9 is formed only in the central portion 6 a of the active region 6, rather than over the entire active region 6. In the peripheral portion 6 b of the active region 6, instead of the above-described arrangement pattern, an arrangement pattern in which a plurality of IGBT regions 8 are arranged in rows along the second direction Y and an arrangement pattern in which a plurality of diode regions 9 are arranged in rows along the second direction Y are adopted. In the examples of FIGS. 18 and 19 , in the region of the active region 6 closest to the side surface 5B, a plurality of IGBT regions 8 are arranged in rows along the second direction Y, and in the region on the side surface 5D side of that region, a plurality of diode regions 9 are each arranged in rows along the second direction Y. In addition, in the region of the active region 6 closest to the side surface 5D, multiple IGBT regions 8 are arranged in a row along the second direction Y, and in the region on the side surface 5B side of that region, multiple diode regions 9 are each arranged in a row along the second direction Y.

[0178] The central portion 6a of the active region 6 is a portion that is surrounded by the IGBT region 8 and the diode region 9, both of which are heat generating regions. Therefore, the central portion 6a of the active region 6 is a region that is difficult to dissipate heat.

[0179] The staggered pattern of the IGBT region 8 and the diode region 9 is formed in the central portion 6a of the active region 6, which is difficult to dissipate heat, and therefore it is possible to suppress a temperature rise in the central portion 6a of the active region 6. This makes it possible to reduce the maximum temperature of the semiconductor device 301.

[0180] The package structure of the semiconductor package 101 in FIG. 12 and the mounting structure in FIG. 13 are also applied to the semiconductor device 301.

[0181] Fig. 20 is a schematic plan view of a semiconductor device 401 according to a fourth embodiment of the present disclosure. Fig. 21 is a plan view schematically showing the structure of a first main surface 3 of the semiconductor device 401.

[0182] The semiconductor device 401 according to the fourth embodiment differs from the semiconductor device 1 according to the first embodiment in that the staggered pattern (unit array UA of the staggered pattern) of the IGBT regions 8 and the diode regions 9 is formed only on the outer periphery 6b of the active region 6, rather than over the entire active region 6. In the central portion of the active region 6, instead of the above-described arrangement pattern, an arrangement pattern in which a plurality of IGBT regions 8 are aligned in a row along the second direction Y and an arrangement pattern in which a plurality of diode regions 9 are aligned in a row along the second direction Y are adopted.

[0183] FIG. 22 is a schematic cross-sectional view of a semiconductor package 450 including a semiconductor device 401 .

[0184] The semiconductor package 450 includes a semiconductor device 401, a first heat dissipation pad (heat dissipation unit) 451, a second heat dissipation pad 452, a spacer (heat dissipation unit) 453 for regulating the distance between the top surface of the semiconductor device 401 and the second heat dissipation pad 452, a resin package 454, a first lead 456, a second lead 457, a third lead 458, a fourth lead 459, a fifth lead 460, a sixth lead 461, and wires 471 to 475.

[0185] The first heat dissipation pad 451 is flat and made of a conductive material such as copper. The first heat dissipation pad 451 has a flat mounting surface 451A. The mounting surface 451A faces one side of the normal direction Z. This side of the normal direction Z coincides with the upper side of the paper in FIG. 22 .

[0186] The first lead 456, the second lead 457, the third lead 458, the fourth lead 459, the fifth lead 460, and the sixth lead 461 extend linearly from the first heat dissipation pad 451. The six first lead 456, the second lead 457, the third lead 458, the fourth lead 459, the fifth lead 460, and the sixth lead 461 are arranged in a first direction X. The first direction X is a direction perpendicular to the plane of the paper in FIG. 22 . The first lead 456, the second lead 457, the third lead 458, the fourth lead 459, the fifth lead 460, and the sixth lead 461 are made of a conductive material such as copper.

[0187] The wires 471 to 475 are made of a metal such as aluminum. The wire 471 is joined to the collector terminal electrode 32 (see the dashed line in FIG. 20) of the semiconductor device 401 and the first lead 456. This electrically connects the collector terminal electrode 32 and the first lead 456. The wire 472 is joined to the emitter terminal electrode 13 (see FIG. 20) of the semiconductor device 401 and the second lead 457. This electrically connects the emitter terminal electrode 13 and the second lead 457.

[0188] The wire 473 is joined to the current detection terminal electrode 17 (see FIG. 20 ) of the semiconductor device 401 and the fourth lead 459. This electrically connects the current detection terminal electrode 17 and the fourth lead 459. The wire 474 is joined to the first sense terminal electrode 15 or the second sense terminal electrode 16 (for example, the first sense terminal electrode 15 in this embodiment) of the semiconductor device 401 and the fifth lead 460. This electrically connects the first sense terminal electrode 15 or the second sense terminal electrode 16 (for example, the first sense terminal electrode 15) and the fifth lead 460. The wire 475 is joined to the gate terminal electrode 14 (see FIG. 20 ) of the semiconductor device 401 and the sixth lead 461. This electrically connects the gate terminal electrode 14 and the sixth lead 461. The third lead 458 is not electrically connected to the semiconductor device 401.

[0189] The second heat dissipation pad 452 has a flat plate shape and is made of a conductive material such as copper. The second heat dissipation pad 452 is disposed on one side in the normal direction Z with respect to the first heat dissipation pad 451, with the semiconductor device 401 sandwiched between them.

[0190] The spacer 453 is a columnar body extending in the normal direction Z. The spacer 453 is disposed between the first heat dissipation pad 451 and the second heat dissipation pad 452. The spacer 453 is made of a conductive material such as copper. An end face 453A of the spacer 453 is in contact with the center of the semiconductor device 401, more specifically, the center of the first main surface 3 (the center portion 6a of the active region 6 (see FIG. 20 , etc.)). As a result, only the center portion 6a of the first main surface 3 of the semiconductor device 401 is cooled.

[0191] Heat generated in the semiconductor device 401 is dissipated via the first heat dissipation pad 451, the spacer 453, and the second heat dissipation pad 452. The placement surface 451A of the first heat dissipation pad 451 contacts the entire second main surface 4 of the semiconductor device 401, thereby uniformly cooling the second main surface 4 of the semiconductor device 401. On the other hand, the end surface 453A of the spacer 453 contacts the first main surface 3 of the semiconductor device 401 only at the center.

[0192] 20 and 21 , in the semiconductor device 401, the central portion 6 a of the active region 6 is a region that dissipates heat easily. On the other hand, the peripheral portion 6 b of the active region 6 is a region that dissipates heat less easily than the central portion 6 a. The staggered pattern of the IGBT region 8 and the diode region 9 is formed in the peripheral portion 6 b of the active region 6, which dissipates heat less easily, so that the temperature rise in the peripheral portion 6 b of the active region 6 can be suppressed. This allows the maximum temperature of the semiconductor device 401 to be reduced.

[0193] Furthermore, a package structure similar to the semiconductor package 450 may be applied to the semiconductor device 1, the semiconductor device 151, or the semiconductor device 201.

[0194] The embodiments of the present disclosure may also be embodied in other forms.

[0195] In each of the above-described embodiments, the semiconductor layer 2 is - Instead of the p-type semiconductor substrate 31, a p-type semiconductor substrate and an n-type semiconductor layer formed on the semiconductor substrate are used. - In this case, the p-type semiconductor substrate faces the collector region 34. - The epitaxial layer of the mold faces the drift region 30 .

[0196] The p-type semiconductor substrate may be made of silicon. - The mold epitaxial layer may be made of silicon. - The p-type epitaxial layer is formed by epitaxially growing silicon from the main surface of the p-type semiconductor substrate.

[0197] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be formed as n-type, and an n-type portion may be formed as p-type.

[0198] The following characteristics can be extracted from the description of this specification and the drawings.

[0199] [Supplementary Note 1-1] An active region (6) including a semiconductor layer (2) having a first main surface (3) and a second main surface (4) opposite to the first main surface (3); an IGBT region (8) formed in the semiconductor layer (2), the IGBT region (8) having a gate trench (39) formed therein; a diode region (9) formed in the semiconductor layer (2); and a plurality of gate wirings (19b) formed on the first main surface (3), wherein in a predetermined region of an active region (6) including the IGBT region (8) and the diode region (9), one of the IGBT region (8) and the diode region (9) is a reference region (8B), and the other is a heterogeneous region (9A, 9B, 9C) different from the reference region (8B), and the reference region (8B) faces the heterogeneous region (9B) in a first direction (X) perpendicular to an extension direction of the gate trench (39) in a plan view, In a predetermined region of the active region (6), the reference region (8B) is further opposed to the heterogeneous region (9A) in a second direction (Y) parallel to the extension direction of the gate trench (39) in a planar view, with a first gate wiring (19bA) included in the plurality of gate wirings (19b) sandwiched therebetween.

[0200] According to this configuration, in a predetermined region of the active region (6), one of the reference region (8B) of the IGBT region (8) and the diode region (9) faces the other of the heterogeneous regions (9A) of the IGBT region (8) and the diode region (9) across the first gate wiring (19bA) in a second direction (Y) parallel to the extension direction of the gate trench (39) in a plan view. Therefore, in a predetermined region of the active region (6), the reference region (8B) does not face a homogeneous region (8A) of the same type as the reference region (8B) across the first gate wiring (19bA) in the second direction (Y), or even if the reference region (8B) faces the homogeneous region (8A) in the second direction (Y), the facing width with the homogeneous region (8C) is narrow. This makes it possible to suppress a local increase in heat generation in a predetermined region of the active region (6) when a current flows through the reference region (8B) and the homogeneous region (8A). Therefore, the temperature rise in a predetermined area of ​​the active area (6) can be suppressed.

[0201] [Supplementary Note 1-2] The semiconductor device (1, 151, 201, 301, 401) according to Supplementary Note 1-1, wherein the plurality of gate wirings (19b) include the first gate wiring (19bA) and a second gate wiring (19bB) extending along the first gate wiring (19bA), the reference region (8B) is sandwiched in the second direction (Y) by the first gate wiring (19bA) and the second gate wiring (19bB), and the reference region (8B) further faces the heterogeneous region (9C) in the second direction (Y) with the second gate wiring (19bB) sandwiched therebetween.

[0202] [Supplementary Note 1-3] The semiconductor device (1, 151, 301, 401) according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the reference region (8B) is formed independently from the reference region (8B) and is further opposed to a homogeneous region (8A) of the same type as the reference region (8B) in the second direction (Y) across the first gate wiring (19bA).

[0203] [Appendix 1-4] The semiconductor device (1, 151, 301, 401) according to Appendix 1-3, wherein the reference region (8B) includes a reference IGBT region (8B) made of the IGBT region (8), and the reference IGBT region (8B) faces the homogeneous IGBT region (8A) that is the homogeneous region (8A) in the second direction (Y) across the first gate wiring (19bA).

[0204] [Appendix 1-5] The semiconductor device (1, 151, 301, 401) according to Appendix 1-4, wherein an opposing width (W1, W2) between the reference IGBT region (8A) and the homogeneous IGBT region (8A) in the second direction (Y) is equal to or greater than a line width (W3) of the first gate wiring (19b).

[0205] [Supplementary Note 1-6] The semiconductor device (201) according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the reference region (8B) is formed independently of the reference region (8B) and does not face a homogeneous region (8A) of the same type as the reference region (8B) in the second direction (Y).

[0206] [Supplementary Note 1-7] The semiconductor device (1, 151, 201, 301) according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, wherein the predetermined region is a region including a central portion (6a) of the active region (6) in a planar view.

[0207] [Appendix 1-8] The semiconductor device (1, 151, 201, 301) according to Appendix 1-7, wherein the second main surface (4) is an area that contacts a heat dissipation unit (110) over its entire area, and the heat dissipation unit does not contact the first main surface (3).

[0208] [Supplementary Note 1-9] The semiconductor device (1, 151, 201, 401) according to Supplementary Note 1-1 to Supplementary Note 1-6, wherein the predetermined region is a region including the outer periphery (6b) of the active region (6) in a plan view.

[0209] [Appendix 1-10] The semiconductor device (1, 151, 201, 401) according to Appendix 1-9, wherein the entire second main surface (4) and a central portion (6 a) of the first main surface (3) are regions that come into contact with a heat dissipation unit (451, 453), and the heat dissipation unit does not come into contact with the outer periphery (6 a) of the first main surface (3).

[0210] [Supplementary Note 1-11] The semiconductor device (1, 151, 201) according to Supplementary Note 1-7 or Supplementary Note 1-9, wherein the predetermined area is the entire area of ​​the active area (6).

[0211] [Supplementary Note 1-12] The semiconductor device (1, 151, 201, 301, 401) according to any one of Supplementary Note 1-3 to Supplementary Note 1-6, further comprising a unit array (UA), wherein the unit array (UA) comprises the reference region (8B), a plurality of the heterogeneous regions (9A, 9B, 9C) adjacent to the reference region (8B) in the first direction (X) and the second direction (Y), and the homogeneous regions (8A, 8C) adjacent to the reference region (8B) on both sides of two diagonal directions intersecting both the first direction (X) and the second direction (Y) and independent of the reference region (8B), wherein the unit array (UA) is formed over the entire active region (6) in a planar view.

[0212] [Supplementary Note 1-13] The semiconductor device according to Supplementary Note 1-1, wherein the IGBT region and the diode region respectively include a plurality of the IGBT regions and a plurality of the diode regions, and the first main surface has a plurality of region arrays arranged in the second direction with spaces between them, the plurality of region arrays including the plurality of IGBT regions and the plurality of diode regions being alternately arranged along the first direction, the plurality of IGBT regions included in a predetermined region array among the plurality of region arrays face in the second direction each of the plurality of diode regions included in a region array adjacent in the second direction to the predetermined region array, and the plurality of diode regions included in the predetermined region array face in the second direction each of the plurality of IGBT regions included in a region array adjacent in the second direction to the predetermined region array.

[0213] [Appendix 1-14] The semiconductor device (1, 151, 301, 401) according to any one of Appendices 1-1 to 1-13, wherein the diode region (9) includes a cathode region (61) formed in a surface layer portion of the second main surface (4), and the cathode region (61) includes a lead-out region (182) that crosses the boundary region (72) and is led out to the IGBT region side.

[0214] [Supplementary Note 1-15] The semiconductor device (1, 151, 301, 401) according to any one of Supplementary Note 1-1 to Supplementary Note 1-14, wherein, in a plan view, the area ratio of the diode region (9) to the active region (6) is 25% or more and 45% or less.

[0215] [Supplementary Note 1-16] The semiconductor device (1, 151, 201) according to any one of Supplementary Note 1-1 to Supplementary Note 1-15, wherein the IGBT region (8) and the diode region (9) respectively include a plurality of IGBT regions (8) and a plurality of diode regions (9), and the plurality of IGBT regions (8) and the plurality of diode regions (9) are respectively arranged in a staggered pattern in a plan view.

[0216] 1: Semiconductor device 2: Semiconductor layer 3: First main surface 4: Second main surface 5A: Side surface 5B: Side surface 5C: Side surface 5D: Side surface 6: Active region 6a: Central portion 6b: Peripheral portion 7: Outer region 8: IGBT region 8A: IGBT region (homogeneous IGBT region, homogeneous region) 8B: IGBT region (reference IGBT region, reference region) 8C: IGBT region (homogeneous IGBT region, homogeneous region) 9: Diode region 9A: Diode region (heterogeneous diode region, heterogeneous region) 9B: Diode region (heterogeneous diode region, heterogeneous region) 9C: Diode region (heterogeneous diode region, heterogeneous region) 11: Sensor region 12: IGBT array (region array) 12A: First array 12B : Second array 12C : Third array 12D : Fourth array 12E : Fifth array 12F : Sixth array 13 : Emitter terminal electrode 14 : Gate terminal electrode 15 : First sense terminal electrode 16 : Second sense terminal electrode 17 : Current detection terminal electrode 18 : Open terminal electrode 19 : Gate wiring 19a : First region 19b : Second region 19bA : First gate wiring 19bB : Second gate wiring 20 : First sense wiring 20a : First region 20b : Second region 21 : Second sense wiring 21a : First region 21b : Second region 22 : First electrode layer 23 : Second electrode layer 24 : Third electrode layer 30 : Drift region 31 : Semiconductor substrate 32 : Collector terminal electrode 33 : Buffer layer 34 : Collector region 35 : FET structure 36 : Trench gate structure 37 : First outer trench gate structure 38 : Second outer trench gate structure 39 : Gate trench 40 : Gate insulating layer 41 : Gate conductive layer 41a : Gate extraction electrode layer 42 : Dummy FET structure 45 : Body region 46 : Emitter region 47 : Carrier storage region 48 : Contact trench 49 : Contact region 55 : Region isolation insulating layer 61 : Cathode region62: Anode region 63: Cell isolation structure 64: Cell isolation trench 65: Cell isolation insulating layer 66: Cell isolation electrode layer 67: Recess 68: pn junction 69: Diode cell region 72: Boundary region 73: Emitter trench structure 73A: Terminal emitter trench structure 74: Emitter trench 75: Emitter insulating layer 76: Emitter potential electrode layer 76a: Extraction electrode layer 79: Interlayer insulating layer 80: First insulating layer 81: Second insulating layer 82: Third insulating layer 83: Emitter opening 84: Diode opening 86: First opening 91: Emitter plug electrode 92: Barrier electrode layer 93: Main electrode layer 94: First plug electrode 101: Semiconductor package 102 : Electrode 103 : Electrode 104 : Electrode 105 : Electrode 106 : Electrode 107 : Electrode 108 : Resin package 108A : First surface 108B : Second surface 108C : Flat surface 108D : Tapered surface 108E : Flat surface 108F : Tapered surface 108H : Screw hole 109 : Mounting substrate 110 : Die bonding pad (heat dissipation unit) 110A : Placement surface 110B : Back surface 111 : Lead 111A : Connection portion 112 : Hole 112B : Terminal portion 113 : Hole 114 : Solder 115 : Wire bonding pad 116 : Lead 117 : Wire bonding pad 118 : Lead 119 : Wire bonding pad 120: Lead 121: Wire bonding pad 122: Lead 123: Wire bonding pad 124: Lead 129: Heat sink 130: Screw 133: Wire 134: Wire 135: Wire 136: Wire 151: Semiconductor device 182: Pull-out region 201: Semiconductor device 301: Semiconductor device 401: Semiconductor device 450: Semiconductor package 451: First heat dissipation pad (heat dissipation unit) 451A: Placement surface 452: Second heat dissipation pad 453: Spacer (heat dissipation unit) 453A: End surface 454: Resin package 456: First lead457: Second lead 458: Third lead 459: Fourth lead 460: Fifth lead 461: Sixth lead 471: Wire 472: Wire 473: Wire 474: Wire 475: Wire D: pn junction diode D1: Depth D2: Depth D3: Depth P1: First pitch P2: Second pitch UA: Unit array W: Overlap width W1: First opposing width (opposing width) W2: Second opposing width (opposing width) W3: Line width W4: First interval W5: Second interval WD: Width WG: Width X: First direction Y: Second direction Y1: One side Y2: Other side Z: Normal direction

Claims

1. a semiconductor layer having a first major surface and a second major surface opposite to the first major surface; an IGBT region formed in the semiconductor layer, the IGBT region having a gate trench formed therein; a diode region formed in the semiconductor layer; a plurality of gate wirings formed on the first main surface; In a predetermined region of an active region including the IGBT region and the diode region, one of the IGBT region and the diode region is a reference region, and the other is a heterogeneous region different from the reference region, the reference region faces the different-type region in a first direction perpendicular to an extension direction of the gate trench in a plan view; In a predetermined region of the active region, the reference region is further opposed to the heterogeneous region in a second direction parallel to the extension direction of the gate trench in a planar view, across a first gate wiring included in the plurality of gate wirings.

2. the plurality of gate wirings include the first gate wiring and a second gate wiring extending along the first gate wiring, the reference region is sandwiched between the first gate wiring and the second gate wiring in the second direction, 2. The semiconductor device according to claim 1, wherein said reference region is further opposed to said different type region in said second direction with said second gate wiring interposed therebetween.

3. 2. The semiconductor device according to claim 1, wherein said reference region is formed independently from said reference region, and further faces a homogeneous region of the same type as said reference region in said second direction across said first gate wiring.

4. the reference region includes a reference IGBT region formed of the IGBT region, 4. The semiconductor device according to claim 3, wherein said reference IGBT region faces said homogeneous IGBT region, which is said homogeneous region, in said second direction with said first gate wiring interposed therebetween.

5. 5. The semiconductor device according to claim 4, wherein an opposing width between said reference IGBT region and said homogeneous IGBT region in said second direction is equal to or greater than a line width of said first gate wiring.

6. 2. The semiconductor device according to claim 1, wherein said reference region is formed independently from said reference region and does not face a region of the same type as said reference region in said second direction.

7. 2. The semiconductor device according to claim 1, wherein said predetermined region is a region including a central portion of said active region in a plan view.

8. the second main surface is an area whose entire area is in contact with a heat dissipation unit, The semiconductor device according to claim 7 , wherein a heat dissipation unit is not in contact with said first main surface.

9. 2. The semiconductor device according to claim 1, wherein said predetermined region is a region including a periphery of said active region in a plan view.

10. the entire second main surface and a central portion of the first main surface are in contact with a heat dissipation unit, The semiconductor device according to claim 9 , wherein a heat dissipation unit does not contact an outer periphery of said first main surface.

11. further comprising a unit sequence, the unit array includes the reference region, a plurality of the heterogeneous regions adjacent to the reference region in the first direction and the second direction, and the homogeneous regions adjacent to the reference region on both sides of two diagonal directions intersecting both the first direction and the second direction and independent of the reference region, 7. The semiconductor device according to claim 3, wherein the unit array is formed over the entire active region in a plan view.

12. the IGBT region and the diode region include a plurality of the IGBT regions and a plurality of the diode regions, respectively; a plurality of region arrays including a plurality of the IGBT regions and a plurality of the diode regions, the plurality of IGBT regions and the plurality of the diode regions being alternately arranged along the first direction, the plurality of region arrays being arranged at intervals in the second direction on the first main surface; a plurality of the IGBT regions included in a predetermined region array among the plurality of region arrays face, in the second direction, each of the plurality of diode regions included in a region array adjacent in the second direction to the predetermined region array, 2. The semiconductor device according to claim 1, wherein the plurality of diode regions included in the predetermined region array face, in the second direction, each of the plurality of IGBT regions included in the region array adjacent to the predetermined region array in the second direction.

13. the diode region includes a cathode region formed in a surface layer portion of the second main surface, 13. The semiconductor device according to claim 1, wherein said cathode region includes a lead-out region that crosses a boundary region that is a boundary between said diode region and said IGBT region and is led out to said IGBT region side.

14. 13. The semiconductor device according to claim 1, wherein an area ratio of said diode region to said active region is 25% or more and 45% or less in plan view.

15. the IGBT region and the diode region include a plurality of IGBT regions and a plurality of diode regions, respectively; The semiconductor device according to claim 1 , wherein the plurality of IGBT regions and the plurality of diode regions are respectively arranged in a staggered pattern in a plan view.