Semiconductor device

Abstract

In the present invention, each FLR electrode has an electrode curved portion in which an inner edge and an outer edge of the FLR electrode are arc-shaped in plan view in at least one corner section among four corner sections. In the at least one corner section, each electrode curved portion has an inner edge and an outer edge having different curvature centers and different curvatures, and the size relationships of the curvatures of the inner edge and the outer edge are opposite to each other between two adjacent electrode curved portions. Due to this configuration, in the corner section, each electrode curved portion has a region in which the width between the inner edge and the outer edge is large and a region in which said width is narrow, and a part of the region in which the width is large in each electrode curved portion is electrically connected to a corresponding FLR via an FLR connection electrode which penetrates through an insulating film.

Description

Semiconductor Devices Related Applications

[0001] This application claims priority based on Patent Application No. 2023-056390 filed with the Japan Patent Office on March 30, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device including an active region and an edge termination region surrounding the active region. An IGBT and a free wheel diode are formed in the active region. The edge termination region includes a plurality of guard rings (field limiting rings (FLRs)) and field plate electrodes (FLR electrodes) disposed on the guard rings and electrically connected to the corresponding guard rings.

[0004] Japanese Patent Application Laid-Open No. 2022-882

[0005] An object of the present disclosure is to provide a semiconductor device that can obtain a novel connection structure between a plurality of FLR electrodes and the corresponding FLRs.

[0006] One embodiment of the present disclosure includes a chip having a first main surface that is rectangular in plan view and a second main surface opposite to the first main surface, an active region provided on the first main surface and having an element structure formed therein, a peripheral region outside the active region, the peripheral region being provided on the periphery of the first main surface and having four corner portions, a plurality of field limiting rings (hereinafter referred to as "FLRs") formed in a surface layer portion of the first main surface in the peripheral region so as to surround the active region, an insulating film formed on the first main surface and covering the plurality of FLRs, and a plurality of FLR electrodes arranged opposite each of the plurality of FLRs via the insulating film, wherein each of the FLR electrodes is formed at least one corner of the four corner portions. and a corner portion has electrode curved portions whose inner and outer edges have arcuate shapes in plan view, and at least one of the corner portions has inner and outer edges whose centers of curvature and curvatures are different, and the magnitude relationship of the curvatures of the inner and outer edges between two adjacent electrode curved portions is reversed, so that at the corner portion, each electrode curved portion has a wide region and a narrow region between the inner and outer edges, and part of the wide region in each electrode curved portion is physically and electrically connected to the corresponding FLR via an FLR connection electrode that penetrates the insulating film.

[0007] This configuration provides a novel connection structure between multiple FLR electrodes and their corresponding FLRs.

[0008] The above and other objects, features, and advantages will become apparent from the following description of the embodiments with reference to the accompanying drawings.

[0009] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIG. 2 is a plan view showing a layout of a first main surface. FIG. 3 is an enlarged plan view showing an active region and a peripheral region. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is an enlarged plan view showing an active region and a boundary region. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 7. FIG. 10 is a cross-sectional view taken along line XX in FIG. 1. FIG. 11 is an enlarged plan view showing a pad region. FIG. 12 is an enlarged plan view showing a gate resistor structure shown in FIG. 11. FIG. 13 is an enlarged plan view showing an inner portion of the gate resistor structure shown in FIG. 12. FIG. 14 is an enlarged plan view showing one end of the gate resistor structure shown in FIG. 12. FIG. 15 is an enlarged plan view showing the other end of the gate resistor structure shown in FIG. 12. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 13 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 13 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 13 . FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 13 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 14 . FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 15 . FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 12 . FIG. 23 is a plan view showing the layout of a resistive film, a gate electrode film, and a gate wiring film. FIG. 24 is an electrical circuit diagram showing a gate resistor structure, a gate terminal electrode, and a gate wiring electrode. FIG. 25 is a schematic plan view for explaining the structure of the FLR and FLR electrode at the second corner portion. FIG. 26 is a schematic cross-sectional view taken along line XXVI-XXVI in FIG. 25 . FIG. 27 is a schematic plan view for explaining a modified example of the structure of the FLR and the FLR electrode at the second corner portion.

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrated, and are not necessarily to scale. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] When the phrase "substantially equal" is used in a description in which a comparison target is present, this phrase includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not attached with the intent of limiting the names of each structure.

[0012] FIG. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. FIG. 2 is a plan view showing the layout of a first main surface 3. FIG. 3 is an enlarged plan view showing an active region 6 and a peripheral region 9. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. 3. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 3.

[0013] Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 3. Fig. 7 is an enlarged plan view showing the active region 6 and the boundary region 8. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 7. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 7. Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 1.

[0014] The semiconductor device 1A is an IGBT (Insulated Gate Bipolar Transistor) semiconductor device. With reference to FIGS. 1 to 10 , the semiconductor device 1A includes a chip 2 having a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 2 may also be referred to as a "semiconductor chip." In this embodiment, the chip 2 has a single-layer structure made of a silicon single crystal substrate (semiconductor substrate).

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from a normal direction Z thereto (hereinafter simply referred to as a "planar view"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 has a quadrangular shape when viewed from a planar view.

[0016] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0017] The semiconductor device 1A includes a plurality of active regions 6 spaced apart on the first main surface 3. The plurality of active regions 6 include a first active region 6A and a second active region 6B. The first active region 6A is provided in a region on the first side surface 5A side of a line intersecting the center of the first main surface 3 in the first direction X. The second active region 6B is provided in a region on the second side surface 5B side of a line intersecting the center of the first main surface 3 in the first direction X. In this embodiment, each active region 6 is formed in a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view. The planar shape of each active region 6 is arbitrary.

[0018] An element structure is formed in the active region 6. In this embodiment, the element structure includes an IGBT structure Tr (transistor structure). The element structure may include a transistor other than an IGBT. As disclosed in Japanese Patent Application Laid-Open No. 2022-882, the element structure may include an IGBT structure and a free wheel diode (FWD) structure connected in anti-parallel to the IGBT structure.

[0019] The semiconductor device 1A includes a non-active region 7 provided in a region outside the multiple active regions 6 on the first main surface 3. The non-active region 7 includes a boundary region 8 and a peripheral region 9. The boundary region 8 is provided in a strip shape extending in the first direction X in a region between the first active region 6A and the second active region 6B. In this embodiment, the boundary region 8 is located on a straight line crossing the center of the first main surface 3 in the first direction X.

[0020] The boundary region 8 includes a pad region 10 having a relatively large width in the second direction Y, and a street region 11 having a width in the second direction Y that is smaller than the width of the pad region 10. The pad region 10 may be referred to as a "first boundary region" or a "wide region." The street region 11 may be referred to as a "second boundary region," a "line region," or a "narrow region."

[0021] The pad region 10 is provided in an area on one side in the first direction X (the third side surface 5C side). In this embodiment, the pad region 10 is located on a straight line that crosses the center of the first main surface 3 in the first direction X in a plan view, and is provided in a quadrangular shape near the center of the third side surface 5C. The street region 11 is provided in an area on the other side in the first direction X (the fourth side surface 5D side) of the pad region 10. In this embodiment, the street region 11 is drawn out in a strip shape from the pad region 10 toward the fourth side surface 5D side, and is located on a straight line that crosses the center of the first main surface 3 in the first direction X.

[0022] The peripheral region 9 is provided on the periphery of the chip 2 so as to collectively surround the multiple active regions 6. The peripheral region 9 is provided in a ring shape (a square ring shape in this embodiment) extending along the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The peripheral region 9 is connected to the pad region 10 on one side (the third side surface 5C side) of the first main surface 3, and is connected to the street region 11 on the other side (the fourth side surface 5D side) of the first main surface 3.

[0023] The outer peripheral region 9 has four corners 201, 202, 203, and 204. The corner 201 is sandwiched between the first side surface 5A and the third side surface 5C in a plan view (hereinafter referred to as the "first corner 201"). The corner 202 is sandwiched between the first side surface 5A and the fourth side surface 5D in a plan view (hereinafter referred to as the "second corner 202").

[0024] Corner portion 203 is a corner portion sandwiched between fourth side surface 5D and second side surface 5B in plan view (hereinafter referred to as "third corner portion 203"). Corner portion 204 is a corner portion sandwiched between second side surface 5B and third side surface 5C in plan view (hereinafter referred to as "fourth corner portion 204").

[0025] The semiconductor device 1A includes an n-type (first conductivity type) drift region 12 formed inside the chip 2. The drift region 12 is formed throughout the entire interior of the chip 2. In this embodiment, the chip 2 is made of an n-type semiconductor substrate (n-type semiconductor chip), and the drift region 12 is formed by utilizing the n-type chip 2.

[0026] The semiconductor device 1A includes an n-type buffer region 13 formed in a surface layer portion of the second main surface 4. In this embodiment, the buffer region 13 is formed in a layer shape extending along the entire area of ​​the second main surface 4. The buffer region 13 has a higher n-type impurity concentration than the drift region 12. The presence or absence of the buffer region 13 is optional, and a configuration without the buffer region 13 may also be employed.

[0027] The semiconductor device 1A includes a p-type (second conductivity type) collector region 14 formed in a surface layer portion of the second main surface 4. The collector region 14 is formed in a surface layer portion on the second main surface 4 side of the buffer region 13. In this embodiment, the collector region 14 is formed in a layer shape extending along the second main surface 4 over the entire area of ​​the second main surface 4. The collector region 14 is exposed from the second main surface 4 and portions of the first to fourth side surfaces 5A to 5D.

[0028] The semiconductor device 1A includes a plurality of trench isolation structures 15 formed in the first main surface 3 so as to partition the plurality of active regions 6. A gate potential is applied to the plurality of trench isolation structures 15. The trench isolation structures 15 may also be referred to as "trench gate isolation structures" or "trench gate connection structures." The plurality of trench isolation structures 15 includes a first trench isolation structure 15A on the side of the first active region 6A and a second trench isolation structure 15B on the side of the second active region 6B.

[0029] The first trench isolation structure 15A surrounds the first active region 6A and separates the first active region 6A from the boundary region 8 and the outer periphery region 9. In this embodiment, the first trench isolation structure 15A is formed in a polygonal ring shape having four sides parallel to the periphery of the chip 2 in plan view. The first trench isolation structure 15A has a bent portion in plan view that separates the pad region 10 and the street region 11 in the boundary region 8.

[0030] The second trench isolation structure 15B surrounds the second active region 6B and separates the second active region 6B from the boundary region 8 and the peripheral region 9. In this embodiment, the second trench isolation structure 15B is formed in a polygonal ring shape having four sides parallel to the periphery of the chip 2 in plan view. The second trench isolation structure 15B has a bent portion in plan view that separates the pad region 10 and the street region 11 in the boundary region 8.

[0031] The trench isolation structure 15 preferably has a width less than the width of the street region 11. The width of the trench isolation structure 15 is the width in a direction perpendicular to the direction in which the trench isolation structure 15 extends. The width of the trench isolation structure 15 may be 0.1 μm or more and 2.5 μm or less. The width of the trench isolation structure 15 is preferably 0.3 μm or more and 1 μm or less. The width of the trench isolation structure 15 is preferably 0.4 μm or more and 0.7 μm or less. The trench isolation structure 15 may have a depth of 1 μm or more and 20 μm or less. The depth of the trench isolation structure 15 is preferably 4 μm or more and 10 μm or less.

[0032] The configuration of one trench isolation structure 15 will be described below. The trench isolation structure 15 includes an isolation trench 16, an isolation insulating film 17, and an isolation buried electrode 18. The isolation trench 16 is formed in the first main surface 3 and defines the wall surface of the trench isolation structure 15. The isolation insulating film 17 coats the wall surface of the isolation trench 16 in a film-like manner. The isolation insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0033] The isolation insulating film 17 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the isolation insulating film 17 includes a silicon oxide film made of an oxide of the chip 2. The isolation buried electrode 18 is buried in the isolation trench 16 with the isolation insulating film 17 in between. The isolation buried electrode 18 may include conductive polysilicon. A gate potential is applied to the isolation buried electrode 18.

[0034] The semiconductor device 1A includes an IGBT structure Tr (transistor structure) formed in each active region 6. The IGBT structure Tr is not formed in the non-active region 7. The configuration on the second active region 6B side (the configuration of the IGBT structure Tr) is substantially the same as the configuration on the first active region 6A side (the configuration of the IGBT structure Tr), and therefore the configuration on the first active region 6A side will be described below. In this embodiment, the configuration on the second active region 6B side is axisymmetric to the configuration on the first active region 6A side across the boundary region 8. The description of the structure on the second active region 6B side applies to the description of the structure on the first active region 6A side, and will be omitted.

[0035] In this embodiment, the n-type impurity concentration of the drift region 12 gradually decreases from the surface of the drift region 12 on the first main surface 3 side toward the surface of the drift region 12 on the second main surface 4 side. The n-type impurity concentration of the drift region 12 is, for example, 1.0×10 １３ cm －３ Above 1.0 x 10 １５ cm －３ It is preferable that:

[0036] The semiconductor device 1A includes a p-type channel region 20 formed in a surface layer portion of the first main surface 3 in the first active region 6A. The channel region 20 may also be referred to as a "body region" or a "base region." The channel region 20 is formed in a surface layer portion of the drift region 12 on the first main surface 3 side. The channel region 20 extends in a layered manner along the first main surface 3 and is connected to the inner peripheral wall of the trench isolation structure 15. The channel region 20 is formed shallower than the trench isolation structure 15 and has a bottom located closer to the first main surface 3 than the bottom wall of the trench isolation structure 15. The bottom of the channel region 20 is preferably located closer to the first main surface 3 than the intermediate depth range of the trench isolation structure 15. The thickness of the channel region 20 may be approximately 1 μm.

[0037] The semiconductor device 1A includes a plurality of first trench structures 21 formed in the first main surface 3 in the first active region 6A. A gate potential is applied to the plurality of first trench structures 21. The first trench structures 21 may also be referred to as "trench gate structures." The plurality of first trench structures 21 penetrate the channel region 20 to reach the drift region 12. The plurality of first trench structures 21 are arranged at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of first trench structures 21 are arranged in a strip shape extending in the second direction Y.

[0038] Each first trench structure 21 has one end on the boundary region 8 side and the other end on the periphery region 9 side in the longitudinal direction (second direction Y). One end and the other end of the multiple first trench structures 21 are mechanically and electrically connected to the trench isolation structure 15. That is, the multiple first trench structures 21, together with the trench isolation structure 15, form a single ladder-shaped trench structure. The connection portion between the first trench structure 21 and the trench isolation structure 15 may be considered as part of the trench isolation structure 15 and / or part of the first trench structure 21.

[0039] The interval between the multiple first trench structures 21 is preferably less than the width of the street region 11. The width of the first trench structures 21 is preferably less than the width of the street region 11. The width of the first trench structures 21 is the width in a direction perpendicular to the direction in which the first trench structures 21 extend. The width of the first trench structures 21 may be 0.1 μm or more and 2.5 μm or less. The width of the first trench structures 21 is preferably 0.3 μm or more and 1 μm or less.

[0040] The width of the first trench structure 21 is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the first trench structure 21 is preferably approximately equal to the width of the trench isolation structure 15. The first trench structure 21 may have a depth of 1 μm or more and 20 μm or less. The depth of the first trench structure 21 is preferably 4 μm or more and 10 μm or less. The depth of the first trench structure 21 is preferably approximately equal to the depth of the trench isolation structure 15.

[0041] The configuration of one first trench structure 21 will be described below. The first trench structure 21 includes a first trench 22, a first insulating film 23, and a first buried electrode 24. The first trench 22 is formed in the first main surface 3 and defines the wall surface of the first trench structure 21. In this embodiment, the first trench 22 communicates with the isolation trench 16 at both ends in the second direction Y. Specifically, the sidewalls of the first trench 22 communicate with the sidewalls of the isolation trench 16, and the bottom wall of the first trench 22 communicates with the bottom wall of the isolation trench 16.

[0042] The first insulating film 23 coats the wall surfaces of the first trench 22 in a film-like manner. The first insulating film 23 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The first insulating film 23 preferably has a single-layer structure made of a single insulating film.

[0043] It is particularly preferable that the first insulating film 23 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the first insulating film 23 is made of the same insulating film as the isolation insulating film 17. The first insulating film 23 is connected to the isolation insulating film 17 at the communicating portion between the isolation trench 16 and the first trench 22.

[0044] The first buried electrode 24 is buried in the first trench 22 with a first insulating film 23 sandwiched therebetween. The first buried electrode 24 may include conductive polysilicon. A gate potential is applied to the first buried electrode 24. The first buried electrode 24 is mechanically and electrically connected to the isolation buried electrode 18 at the communicating portion between the isolation trench 16 and the first trench 22.

[0045] The semiconductor device 1A includes a plurality of second trench structures 25 formed in regions between adjacent first trench structures 21 in the first main surface 3 of the first active region 6A. The second trench structures 25 may also be referred to as "emitter trench structures." Each second trench structure 25 is formed at an interval in the first direction X from the plurality of first trench structures 21 in a plan view, and is formed in the shape of a quadrangular ring extending in the second direction Y.

[0046] The width of the second trench structure 25 is preferably less than the width of the street region 11. The width of the second trench structure 25 is the width in a direction perpendicular to the direction in which the second trench structure 25 extends. The width of the second trench structure 25 may be 0.1 μm or more and 2.5 μm or less. The width of the second trench structure 25 is preferably 0.3 μm or more and 1 μm or less.

[0047] The width of the second trench structure 25 is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the second trench structure 25 is preferably approximately equal to the width of the first trench structure 21. The second trench structure 25 may have a depth of 1 μm or more and 20 μm or less. The depth of the second trench structure 25 is preferably 4 μm or more and 10 μm or less. The depth of the second trench structure 25 is preferably approximately equal to the depth of the first trench structure 21.

[0048] The following describes the configuration of one second trench structure 25. The second trench structure 25 includes a second trench 26, a second insulating film 27, and a second buried electrode 28. The second trench 26 is formed in the first main surface 3 and defines the wall surface of the second trench structure 25.

[0049] The second insulating film 27 coats the wall surface of the second trench 26 in a film-like manner. The second insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The second insulating film 27 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the second insulating film 27 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the second insulating film 27 is made of the same insulating film as the first insulating film 23.

[0050] The second buried electrode 28 is buried in the second trench 26 with the second insulating film 27 sandwiched therebetween. The second buried electrode 28 may include conductive polysilicon. An emitter potential is applied to the second buried electrode 28.

[0051] The semiconductor device 1A includes a plurality of n-type emitter regions 29 formed in the surface layer portion of the channel region 20 in the first active region 6A. Each of the plurality of emitter regions 29 has a higher n-type impurity concentration than the drift region 12. The plurality of emitter regions 29 are formed on both sides of the plurality of first trench structures 21, respectively. The n-type impurity concentration of the emitter regions 29 is, for example, 1.0×10 １９ cm －３ Above 1.0 x 10 ２１ cm －３ It is preferable that:

[0052] The multiple emitter regions 29 are each formed in a strip shape extending along the multiple first trench structures 21 in a plan view. Of course, the multiple emitter regions 29 may be formed at intervals along the multiple first trench structures 21 in a plan view. In this embodiment, the multiple emitter regions 29 are formed in regions between the first trench structures 21 and the second trench structures 25 so as to be connected to the first trench structures 21 and the second trench structures 25. It is preferable that the emitter regions 29 are not formed in regions between the trench isolation structure 15 and the outermost second trench structures 25.

[0053] The semiconductor device 1A includes a plurality of contact holes 30 formed in the first main surface 3 so as to expose the emitter regions 29 in the first active region 6A. The plurality of contact holes 30 are formed on both sides of the plurality of first trench structures 21 at intervals from the plurality of first trench structures 21. Each of the plurality of contact holes 30 may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall.

[0054] The plurality of contact holes 30 penetrate the emitter region 29 to reach the channel region 20. The plurality of contact holes 30 may be spaced from the bottom of the emitter region 29 toward the first main surface 3 so as not to reach the channel region 20. The plurality of contact holes 30 are each formed in a strip shape extending along the plurality of first trench structures 21 in a plan view. In terms of the longitudinal direction (second direction Y), the plurality of contact holes 30 are preferably shorter than the plurality of first trench structures 21. It is particularly preferable that the plurality of contact holes 30 are shorter than the plurality of second trench structures 25.

[0055] The semiconductor device 1A includes a plurality of p-type channel contact regions 31 formed in a surface layer portion of the channel region 20 of the first active region 6A in a region different from the plurality of emitter regions 29. The plurality of channel contact regions 31 have a higher p-type impurity concentration than the channel region 20. The plurality of channel contact regions 31 are each formed in a strip shape extending along the corresponding contact hole 30 in a plan view. The bottoms of the plurality of channel contact regions 31 are each formed in a region between the bottom wall of the corresponding contact hole 30 and the bottom of the channel region 20.

[0056] The p-type impurity concentration of the channel region 20 is, for example, 1.0×10 １６ cm －３ Above 1.0 x 10 １８ cm －３ The p-type impurity concentration of the channel contact region 31 is preferably 1.0×10 or less, for example. １８ cm －３ Above 1.0 x 10 ２０ cm －３ It is preferable that:

[0057] The semiconductor device 1A includes a plurality of p-type floating regions 32 formed in regions surrounded by a plurality of second trench structures 25 in the surface layer portion of the first main surface 3 of the first active region 6A. The plurality of floating regions 32 are formed in an electrically floating state. Of course, an emitter potential may be applied to the plurality of floating regions 32. The plurality of floating regions 32 preferably have a higher p-type impurity concentration than the channel region 20.

[0058] Each floating region 32 extends in a layered manner along the first main surface 3 and is connected to the inner peripheral wall of each second trench structure 25. Each floating region 32 is preferably formed deeper than the middle of the depth range of the second trench structure 25. In this embodiment, each floating region 32 is formed deeper than the second trench structure 25 and has a portion covering the bottom wall of the second trench structure 25.

[0059] Thus, the first active region 6A includes, as an IGBT structure Tr, a channel region 20, a plurality of first trench structures 21, a plurality of second trench structures 25, a plurality of emitter regions 29, a plurality of contact holes 30, a plurality of channel contact regions 31, and a plurality of floating regions 32. Similarly to the first active region 6A, the second active region 6B includes, as an IGBT structure Tr, a channel region 20, a plurality of first trench structures 21, a plurality of second trench structures 25, a plurality of emitter regions 29, a plurality of contact holes 30, a plurality of channel contact regions 31, and a plurality of floating regions 32.

[0060] The semiconductor device 1A includes a p-type boundary well region 40 formed in the boundary region 8 in a surface layer portion of the first main surface 3. In this embodiment, the boundary well region 40 has a higher p-type impurity concentration than the channel region 20. Of course, the boundary well region 40 may have a lower p-type impurity concentration than the channel region 20.

[0061] The boundary well region 40 is formed in a strip shape extending in the first direction X along the boundary region 8 in a plan view. That is, the boundary well region 40 is formed in a layer shape extending along the first main surface 3 in a region sandwiched between the first trench isolation structure 15A and the second trench isolation structure 15B, and is exposed from the first main surface 3. The boundary well region 40 is formed in a region sandwiched between the plurality of first trench structures 21 on the first active region 6A side and the plurality of first trench structures 21 on the second active region 6B side.

[0062] The boundary well region 40 includes a first boundary well region 40A formed in the pad region 10 and a second boundary well region 40B formed in the street region 11. The first boundary well region 40A has a relatively large region width in the second direction Y. The first boundary well region 40A is formed in a polygonal shape (a quadrangular shape in this embodiment) in a plan view. The first boundary well region 40A is preferably formed over the entire pad region 10.

[0063] The second boundary well region 40B has a width in the second direction Y that is smaller than the width of the first boundary well region 40A, and extends in a strip shape from the first boundary well region 40A toward the street region 11. In this embodiment, the second boundary well region 40B is located on a line that intersects the center of the first main surface 3 in the first direction X. The second boundary well region 40B extends in a strip shape so as to be located on one side (the third side surface 5C side) and the other side (the fourth side surface 5D side) of the line that intersects the center of the first main surface 3 in the second direction Y.

[0064] The boundary well region 40 is preferably formed deeper than the channel region 20. It is particularly preferable that the boundary well region 40 is formed deeper than the plurality of trench isolation structures 15 (the plurality of first trench structures 21). In this embodiment, the boundary well region 40 has a width in the second direction Y that is greater than the width of the boundary region 8, and is drawn out from the boundary region 8 into the plurality of active regions 6.

[0065] The boundary well region 40 is connected to the plurality of trench isolation structures 15 adjacent to each other in the second direction Y. The boundary well region 40 has portions covering the bottom walls of the plurality of trench isolation structures 15. The boundary well region 40 has portions covering the bottom walls of the plurality of first trench structures 21 across the plurality of trench isolation structures 15.

[0066] The boundary well region 40 covers the sidewalls of the trench isolation structure 15 and the sidewalls of the trench structures in the active regions 6, and is connected to each channel region 20 in the surface layer portion of the first main surface 3. The depth of the boundary well region 40 may be 1 μm or more and 20 μm or less. The depth of the boundary well region 40 is preferably 5 μm or more and 10 μm or less.

[0067] The semiconductor device 1A includes a p-type peripheral well region 41 formed in the peripheral region 9 in a surface layer portion of the first main surface 3. In this embodiment, the peripheral well region 41 has a higher p-type impurity concentration than the channel region 20. Of course, the peripheral well region 41 may have a lower p-type impurity concentration than the channel region 20. It is preferable that the p-type impurity concentration of the peripheral well region 41 is approximately equal to the p-type impurity concentration of the boundary well region 40.

[0068] The peripheral well region 41 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3. The peripheral well region 41 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The peripheral well region 41 is formed in a band shape extending along the multiple active regions 6 in plan view. In this embodiment, the peripheral well region 41 is formed in a ring shape (a quadrangular ring shape in this embodiment) that collectively surrounds the multiple active regions 6 in plan view.

[0069] The peripheral well region 41 is preferably formed deeper than the channel region 20. It is particularly preferable that the peripheral well region 41 is formed deeper than the plurality of trench isolation structures 15 (the plurality of first trench structures 21). It is preferable that the peripheral well region 41 has a depth approximately equal to that of the boundary well region 40.

[0070] The peripheral well region 41 is connected to the plurality of trench isolation structures 15. The peripheral well region 41 has portions that cover the bottom walls of the plurality of trench isolation structures 15. The peripheral well region 41 is drawn out from the peripheral region 9 into the plurality of active regions 6. The peripheral well region 41 has portions that traverse the plurality of trench isolation structures 15 and cover the bottom walls of the plurality of first trench structures 21.

[0071] The periphery well region 41 covers the sidewalls of the trench isolation structure 15 and the sidewalls of the plurality of first trench structures 21 in each active region 6, and is connected to the plurality of channel regions 20 in the surface layer portion of the first main surface 3. The periphery well region 41 is connected to the boundary well region 40 at the connection portion of the boundary region 8 and the periphery region 9. In other words, the periphery well region 41, together with the boundary well region 40, defines the plurality of active regions 6.

[0072] 10 , the semiconductor device 1A includes a plurality of p-type field limiting rings (FLRs) 42 formed in the outer peripheral region 9 on the surface layer of the first main surface 3. Hereinafter, the field limiting rings 42 will be referred to as FLRs 42. The FLRs 42 are provided to reduce the concentration of an electric field at the outer ends of the PN junctions of the semiconductor device 1A. The FLRs 42 may also be referred to as "guard rings."

[0073] The number of FLRs 42 is arbitrary and may be 2 to 20 (typically 3 to 10). In this embodiment, four FLRs 42 are provided.

[0074] The plurality of FLRs 42 may have a p-type impurity concentration higher than that of the channel region 20. The plurality of FLRs 42 may have a p-type impurity concentration higher than that of the peripheral well region 41. The plurality of FLRs 42 may have a p-type impurity concentration lower than that of the peripheral well region 41. The plurality of FLRs 42 may have a p-type impurity concentration approximately equal to that of the peripheral well region 41. The plurality of FLRs 42 are formed in an electrically floating state.

[0075] The multiple FLRs 42 are formed in a region between the periphery of the chip 2 and the peripheral well region 41, with a gap therebetween. The multiple FLRs 42 are formed in a band shape extending along the peripheral well region 41 in a plan view. In this embodiment, the multiple FLRs 42 are formed in a ring shape (quadratic ring shape) surrounding the peripheral well region 41 in a plan view. In each of the corner portions 201 to 204, the FLRs 42 are formed in a curved shape.

[0076] The plurality of FLRs 42 are preferably formed deeper than the channel region 20. The plurality of FLRs 42 may be formed at a depth substantially equal to that of the peripheral well region 41. The plurality of FLRs 42 may be formed shallower than the peripheral well region 41. The plurality of FLRs 42 may be formed at a constant depth. A more detailed structure of the plurality of FLRs 42 will be described later.

[0077] The semiconductor device 1A includes a channel stop region 43 formed in the surface layer portion of the first main surface 3 at an interval from the plurality of FLRs 42 toward the periphery of the chip 2 in the peripheral region 9. The channel stop region 43 has a higher n-type impurity concentration than the drift region 12. Such a channel stop region 43 can be formed simultaneously with the emitter region 29, for example, in the process of forming the emitter region 29.

[0078] The channel stop region 43 is formed in a band shape extending along the periphery of the chip 2 in plan view. In this embodiment, the channel stop region 43 is formed in a ring shape (quadratic ring shape) surrounding the plurality of FLRs 42 in plan view. In each of the corner portions 201 to 204, the channel stop region 43 is formed in a curved shape. The channel stop region 43 may be exposed from the first to fourth side surfaces 5A to 5D. The channel stop region 43 is formed in an electrically floating state.

[0079] The semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 selectively covers the first main surface 3 in the active region 6, the boundary region 8, and the peripheral region 9. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0080] The main surface insulating film 45 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the main surface insulating film 45 includes a silicon oxide film made of an oxide of the chip 2. In this embodiment, the main surface insulating film 45 is made of the same insulating film as the first insulating film 23 (isolation insulating film 17). The main surface insulating film 45 covers the first main surface 3 so as to expose the trench isolation structure 15, the first trench structure 21, and the second trench structure 25.

[0081] Specifically, the main surface insulating film 45 is connected to the isolation insulating film 17, the first insulating film 23, and the second insulating film 27, and exposes the isolation buried electrode 18, the first buried electrode 24, and the second buried electrode 28. The main surface insulating film 45 selectively covers the boundary well region 40, the peripheral well region 41, the FLR 42, and the channel stop region 43 in the boundary region 8 and the peripheral region 9.

[0082] 3 and 5 , the semiconductor device 1A includes a plurality of emitter electrode films 47 arranged on the first main surface 3 so as to cover the plurality of second trench structures 25 in the active region 6. Specifically, the plurality of emitter electrode films 47 are arranged on the main surface insulating film 45. The plurality of emitter electrode films 47 may include conductive polysilicon.

[0083] The plurality of emitter electrode films 47 cover both end portions of the plurality of second trench structures 25 in the second direction Y. In this embodiment, the plurality of emitter electrode films 47 are formed in strip shapes extending in the second direction Y in regions between the corresponding second trench structures 25 and trench isolation structures 15. The plurality of emitter electrode films 47 are formed at intervals from the trench isolation structures 15 toward the second trench structures 25. The plurality of emitter electrode films 47 face the channel region 20 with the main surface insulating film 45 sandwiched therebetween.

[0084] The plurality of emitter electrode films 47 are formed integrally with the second buried electrodes 28 of the plurality of second trench structures 25. That is, the plurality of emitter electrode films 47 are each formed from a portion of the second buried electrode 28 that is extended in a film form onto the first main surface 3 (main surface insulating film 45). Of course, the plurality of emitter electrode films 47 may be formed separately from the second buried electrodes 28.

[0085] Fig. 11 is an enlarged plan view showing the pad region 10. Fig. 12 is an enlarged plan view showing the gate resistor structure 50 shown in Fig. 11. Fig. 13 is an enlarged plan view showing an inner portion of the gate resistor structure 50 shown in Fig. 12. Fig. 14 is an enlarged plan view showing one end of the gate resistor structure 50 shown in Fig. 12. Fig. 15 is an enlarged plan view showing the other end of the gate resistor structure 50 shown in Fig. 12.

[0086] Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 13. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 13. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 13. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 13. Fig. 20 is a cross-sectional view taken along line XX-XX shown in Fig. 14.

[0087] Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in Fig. 15. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 12. Fig. 23 is a plan view showing the layout of the resistance film 60, gate electrode film 64, and gate wiring film 65. Fig. 24 is an electrical circuit diagram showing the gate resistance structure 50, gate terminal electrode 90, and gate wiring electrode 93.

[0088] 11 to 24, the semiconductor device 1A includes a gate resistance structure 50 formed in the pad region 10. The gate resistance structure 50 constitutes a gate resistance RG for the gate of the IGBT (first trench structure 21 of the IGBT structure Tr). The gate resistance structure 50 includes a plurality of trench resistance structures 51 formed on the first main surface 3 in the pad region 10. A gate potential is applied to the plurality of trench resistance structures 51, but the plurality of trench resistance structures 51 do not contribute to channel control.

[0089] In this embodiment, the multiple gate resistance structures 50 form a first trench group 52 and a second trench group 53. The first trench group 52 includes multiple first trench resistance structures 51A that form part of the multiple trench resistance structures 51, and is provided on one side in the second direction Y (the first side surface 5A side). The number of first trench resistance structures 51A is arbitrary and is adjusted based on the resistance value to be achieved.

[0090] For example, the first trench group 52 may include 2 to 100 first trench resistance structures 51A. The number of first trench resistance structures 51A is preferably 50 or less. The number of first trench resistance structures 51A may be 25 or less. The number of first trench resistance structures 51A is preferably 5 or more. Of course, the gate resistance structure 50 may include a single first trench resistance structure 51A instead of the first trench group 52.

[0091] In this embodiment, the first trench group 52 is provided in a region on one side in the second direction Y (first side surface 5A) of a line crossing the center of the first main surface 3 in the first direction X. The first trench group 52 is preferably arranged so as to be biased toward the active region 6 (street region 11 side) relative to the peripheral region 9 in the pad region 10. In this embodiment, the first trench group 52 is arranged at intervals from the center of the pad region 10 toward the active region 6 (street region 11 side). These configurations are effective in suppressing electric field concentration in the multiple first trench resistance structures 51A.

[0092] The multiple first trench resistance structures 51A are formed on the first main surface 3 at intervals from the multiple trench isolation structures 15 (multiple first trench structures 21). The multiple first trench resistance structures 51A are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the multiple first trench resistance structures 51A are arranged in a stripe shape extending in the second direction Y. Each of the multiple first trench resistance structures 51A has one end on one side in the second direction Y (the first side surface 5A side) and the other end on the other side in the second direction Y (the second side surface 5B side).

[0093] The multiple first trench resistance structures 51A are formed at intervals from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3 so as to be located within the boundary well region 40 (first boundary well region 40A), and face the drift region 12 across a part of the boundary well region 40. In other words, the multiple first trench resistance structures 51A do not penetrate the boundary well region 40 (first boundary well region 40A).

[0094] The spacing between the multiple first trench resistance structures 51A is preferably less than the width of the street region 11. The spacing between the multiple first trench resistance structures 51A is preferably approximately equal to the spacing between the first trench structure 21 and the second trench structure 25. The spacing between the multiple first trench resistance structures 51A may be smaller than the spacing between the first trench structure 21 and the second trench structure 25. The spacing between the multiple first trench resistance structures 51A may be larger than the spacing between the first trench structure 21 and the second trench structure 25.

[0095] The width of the first trench resistance structure 51A is preferably less than the width of the street region 11. The width of the first trench resistance structure 51A is the width in a direction perpendicular to the direction in which the first trench resistance structure 51A extends. The width of the first trench resistance structure 51A may be 0.1 μm or more and 2.5 μm or less. The width of the first trench resistance structure 51A is preferably 0.3 μm or more and 1 μm or less.

[0096] The width of the first trench resistance structure 51A is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the first trench resistance structure 51A is preferably approximately equal to the width of the first trench structure 21. The first trench resistance structure 51A may have a depth of 1 μm or more and 20 μm or less. The depth of the first trench resistance structure 51A is preferably 4 μm or more and 10 μm or less. The depth of the first trench resistance structure 51A is preferably approximately equal to the depth of the first trench structure 21.

[0097] The second trench group 53 includes a plurality of second trench resistance structures 51B that constitute part of the plurality of trench resistance structures 51, and are provided at intervals on the other side in the second direction Y (the second side surface 5B side) from the first trench group 52. The number of second trench resistance structures 51B is arbitrary and is adjusted based on the resistance value to be achieved. For example, when a resistance value approximately equal to the resistance value on the first trench group 52 side is to be achieved, the second trench group 53 may include the same number of second trench resistance structures 51B as the number of first trench resistance structures 51A.

[0098] For example, when a resistance value different from the resistance value on the first trench group 52 side is realized, the second trench group 53 may include a number of second trench resistance structures 51B different from the number of first trench resistance structures 51A. For example, when the resistance value on the second trench group 53 side is greater than the resistance value on the first trench group 52 side, the number of second trench resistance structures 51B may be less than the number of first trench resistance structures 51A. For example, when the resistance value on the second trench group 53 side is less than the resistance value on the first trench group 52 side, the number of second trench resistance structures 51B may be more than the number of first trench resistance structures 51A.

[0099] For example, the second trench group 53 may include 2 to 100 second trench resistance structures 51B. The number of second trench resistance structures 51B is preferably 50 or less. The number of second trench resistance structures 51B may be 25 or less. The number of second trench resistance structures 51B is preferably 5 or more. Of course, the semiconductor device 1A may include a single second trench resistance structure 51B instead of the second trench group 53.

[0100] In this embodiment, the second trench group 53 is provided in a region on the other side in the second direction Y (second side surface 5B) of a line intersecting the center of the first main surface 3 in the first direction X. The second trench group 53 faces the first trench group 52 in the second direction Y. The second trench group 53 is preferably arranged in the pad region 10 so as to be biased toward the active region 6 (street region 11) relative to the outer periphery region 9. In this embodiment, the second trench group 53 is arranged at intervals from the center of the pad region 10 toward the active region 6 (street region 11). These configurations are effective in suppressing electric field concentration in the multiple second trench resistance structures 52B.

[0101] The second trench resistance structures 51B are formed on the first main surface 3 at intervals from the trench isolation structures 15 (the first trench structures 21). The second trench resistance structures 51B are arranged at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y.

[0102] That is, the multiple second trench resistance structures 51B are arranged in a stripe pattern extending in the second direction Y. The multiple second trench resistance structures 51B face the multiple first trench resistance structures 51A in a one-to-one correspondence in the second direction Y. That is, the multiple second trench resistance structures 51B are each arranged in the same straight line as the multiple first trench resistance structures 51A. The multiple second trench resistance structures 51B have one end on one side in the second direction Y (the first side surface 5A side) and the other end on the other side in the second direction Y (the second side surface 5B side).

[0103] The second trench resistance structures 51B are formed at intervals from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3 so as to be located within the boundary well region 40 (first boundary well region 40A), and face the drift region 12 across a part of the boundary well region 40. In other words, the second trench resistance structures 51B do not penetrate the boundary well region 40 (first boundary well region 40A).

[0104] The spacing between the multiple second trench resistance structures 51B is preferably less than the width of the street region 11. The spacing between the multiple second trench resistance structures 51B is preferably approximately equal to the spacing between the adjacent first trench structures 21 and second trench structures 25. The spacing between the multiple second trench resistance structures 51B may be smaller than the spacing between the first trench structures 21 and the second trench structures 25. The spacing between the multiple second trench resistance structures 51B may be larger than the spacing between the first trench structures 21 and the second trench structures 25.

[0105] The spacing between the multiple second trench resistance structures 51B may be smaller than the spacing between the multiple first trench resistance structures 51A. The spacing between the multiple second trench resistance structures 51B may be larger than the spacing between the multiple first trench resistance structures 51A. The spacing between the multiple second trench resistance structures 51B is preferably approximately equal to the spacing between the multiple first trench resistance structures 51A.

[0106] The width of the second trench resistance structure 51B is preferably less than the width of the street region 11. The width of the second trench resistance structure 51B is the width in a direction perpendicular to the direction in which the second trench resistance structure 51B extends. The width of the second trench resistance structure 51B may be 0.1 μm or more and 2.5 μm or less. The width of the second trench resistance structure 51B is preferably 0.3 μm or more and 1 μm or less. The width of the second trench resistance structure 51B is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the second trench resistance structure 51B is preferably approximately equal to the width of the first trench resistance structure 51A.

[0107] In this embodiment, the second trench resistance structure 51B has a length approximately equal to that of the first trench resistance structure 51A in the second direction Y. Of course, the second trench resistance structure 51B may be longer than the first trench resistance structure 51A in the second direction Y. Alternatively, the second trench resistance structure 51B may be shorter than the first trench resistance structure 51A in the second direction Y. The lengths of the first trench resistance structure 51A and the second trench resistance structure 51B are adjusted depending on the resistance value to be achieved.

[0108] The second trench resistance structure 51B may have a depth of 1 μm or more and 20 μm or less. The depth of the second trench resistance structure 51B is preferably 4 μm or more and 10 μm or less. The depth of the second trench resistance structure 51B is preferably approximately equal to the depth of the first trench resistance structure 51A (first trench structure 21).

[0109] The following describes the configuration of one trench resistance structure 51 (first trench resistance structure 51A and second trench resistance structure 51B). The trench resistance structure 51 includes a resistance trench 54, a resistance insulating film 55, and a resistance-buried electrode 56. The resistance trench 54 is formed in the first main surface 3 and defines the wall surface of the trench resistance structure 51.

[0110] The resistive insulating film 55 coats the wall surfaces of the resistive trench 54 in a film-like manner. The resistive insulating film 55 is connected to the main surface insulating film 45 on the first main surface 3. The resistive insulating film 55 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The resistive insulating film 55 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the resistive insulating film 55 include a silicon oxide film made of an oxide of the chip 2.

[0111] The resistor-buried electrode 56 is buried in the resistor trench 54 with the resistor insulating film 55 sandwiched therebetween. The resistor-buried electrode 56 may include conductive polysilicon. A gate potential is applied to the resistor-buried electrode 56.

[0112] In this embodiment, the gate resistor structure 50 includes a space region 57 defined in the pad region 10 between the first trench group 52 and the second trench group 53. The space region 57 is formed by a flat portion of the first main surface 3 in a region between the other ends of the plurality of first trench resistor structures 51A and one ends of the plurality of second trench resistor structures 51B.

[0113] In this embodiment, the space region 57 is defined in a quadrangular shape in plan view. The space region 57 exposes the boundary well region 40 from the first main surface 3. In this embodiment, the space region 57 is formed on a straight line that crosses the center of the first main surface 3 in the first direction X in plan view, and faces the street region 11 in the first direction X.

[0114] The space region 57 has a space width along the second direction Y. The space width is larger than the width of the first trench resistance structure 51A (second trench resistance structure 51B) in the first direction X. The space width is larger than the distance between two first trench resistance structures 51A (second trench resistance structures 51B) adjacent to each other in the first direction X. The space width is preferably larger than the width of the first trench group 52 (second trench group 53) in the first direction X. The space width may be smaller than the width of the first trench group 52 (second trench group 53) in the first direction X.

[0115] The space width is preferably smaller than the length of the first trench group 52 (second trench group 53) in the second direction Y. The space width may be approximately equal to the width of the street region 11 in the second direction Y. The space width may be larger than the width of the street region 11 in the second direction Y. The space width may be smaller than the width of the street region 11 in the second direction Y.

[0116] The gate resistor structure 50 includes a resistive film 60 disposed on the first main surface 3 so as to cover the plurality of trench resistor structures 51 in the pad region 10. Specifically, the resistive film 60 is disposed on the main surface insulating film 45. The resistive film 60 includes at least one of a conductive polysilicon film and an alloy film.

[0117] The alloy film may include alloy crystals composed of a metal element and a non-metal element. The alloy film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the resistive film 60 includes conductive polysilicon.

[0118] The thickness of the resistive film 60 is adjusted appropriately depending on the resistance value to be achieved. The thickness of the resistive film 60 is preferably equal to or less than the depth of the first trench resistive structure 51A (second trench resistive structure 51B). It is particularly preferable that the thickness of the resistive film 60 be less than the depth of the first trench resistive structure 51A (second trench resistive structure 51B).

[0119] The thickness of the resistive film 60 is preferably 0.5 times or more the width of the first trench resistor structure 51A (second trench resistor structure 51B). The thickness of the resistive film 60 may be 0.05 μm or more and 2.5 μm or less. The thickness of the resistive film 60 is preferably 0.5 μm or more and 1.5 μm or less. When the resistive film 60 is made of an alloy film, the thickness of the resistive film 60 may be 0.1 nm or more and 100 nm or less.

[0120] The resistive film 60 is formed in a strip shape extending in the second direction Y, and has a first end 60A on one side in the second direction Y (the first side surface 5A side) and a second end 60B on the other side in the second direction Y (the second side surface 5B side). The resistive film 60 has a width in the first direction X that is larger than the width in the first direction X of the first trench group 52 (second trench group 53). The width of the resistive film 60 may be less than the space width. Of course, the width of the resistive film 60 may be equal to or greater than the space width. It is preferable that the resistive film 60 has a uniform width in the first direction X.

[0121] The resistive film 60 has a portion located on one side (the first side surface 5A side) and a portion located on the other side (the second side surface 5B side) in the second direction Y with respect to a line that crosses the center of the first main surface 3 in the first direction X. The resistive film 60 faces the first active region 6A, the second active region 6B, and the street region 11 in the first direction X. In other words, the resistive film 60 faces the plurality of trench isolation structures 15, the plurality of first trench structures 21, and the plurality of second trench structures 25 in the first direction X.

[0122] The resistive film 60 has a first covering portion 61 covering the space region 57, a second covering portion 62 covering the first trench group 52, and a third covering portion 63 covering the second trench group 53. The first covering portion 61 is a portion that covers the first main surface 3 in an area outside the first trench group 52 (plurality of first trench resistance structures 51A) and the second trench group 53 (plurality of second trench resistance structures 51B). The first covering portion 61 is located in an intermediate portion between the first end portion 60A and the second end portion 60B, and faces the boundary well region 40 with the main surface insulating film 45 sandwiched therebetween in the thickness direction.

[0123] The second covering portion 62 forms a first end portion 60A of the resistive film 60 and covers all of the first trench resistance structures 51A. The second covering portion 62 forms the first end portion 60A outside one end portion of the plurality of first trench resistance structures 51A (toward the periphery of the pad region 10). In other words, the first end portion 60A faces the first covering portion 61 across the first trench group 52 in a plan view. The second covering portion 62 is connected to the resistor-buried electrodes 56 of the plurality of first trench resistance structures 51A and faces the boundary well region 40 across the main surface insulating film 45 in the thickness direction.

[0124] The third covering portion 63 forms the second end portion 60B of the resistance film 60 and covers all of the second trench resistance structures 51B. The third covering portion 63 forms the second end portion 60B outside the other ends of the second trench resistance structures 51B (toward the periphery of the pad region 10). In other words, the second end portion 60B faces the first covering portion 61 across the second trench group 53 in a plan view. The third covering portion 63 is connected to the resistor-buried electrodes 56 of the second trench resistance structures 51B and faces the boundary well region 40 across the main surface insulating film 45 in the thickness direction.

[0125] The resistive film 60 is formed integrally with the resistor-buried electrodes 56 of the plurality of first trench resistor structures 51A in the second covering portion 62, and is formed integrally with the resistor-buried electrodes 56 of the plurality of second trench resistor structures 51B in the third covering portion 63. In other words, the resistive film 60 is formed by a portion of the resistor-buried electrode 56 being extended in a film form onto the first main surface 3 (main surface insulating film 45). Of course, the resistive film 60 may be formed separately from the resistor-buried electrode 56.

[0126] The semiconductor device 1A includes a gate electrode film 64 disposed on the first main surface 3 so as to be adjacent to the resistive film 60. Specifically, the gate electrode film 64 is disposed on the main surface insulating film 45. The gate electrode film 64 includes at least one of a conductive polysilicon film and an alloy film. The alloy film may include alloy crystals composed of a metal element and a non-metal element.

[0127] The alloy film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. The gate electrode film 64 is preferably formed of the same resistive material as the resistive film 60. In this embodiment, the gate electrode film 64 includes conductive polysilicon. The gate electrode film 64 preferably has a thickness approximately equal to that of the resistive film 60.

[0128] The gate electrode film 64 is disposed on the main surface insulating film 45 at a distance from the resistive film 60 toward the inner side of the pad region 10 (the third side surface 5C side), and is physically separated from the resistive film 60. The gate electrode film 64 is formed at a distance from the plurality of trench isolation structures 15 toward the inner side of the pad region 10 in plan view.

[0129] The gate electrode film 64 faces the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45. The gate electrode film 64 is formed in a polygonal shape (a quadrangular shape in this embodiment) in a plan view. In this embodiment, the gate electrode film 64 is formed in a rectangular shape extending in the second direction Y along the resistance film 60.

[0130] 11 , 12 and 24 , semiconductor device 1A includes a gate wiring film 65 disposed on first main surface 3 adjacent to resistive film 60 so as to face gate electrode film 64 with resistive film 60 sandwiched therebetween. Specifically, gate wiring film 65 is disposed on main surface insulating film 45. Gate wiring film 65 includes at least one of a conductive polysilicon film and an alloy film. The alloy film may include alloy crystals constituted by a metal element and a non-metal element.

[0131] The alloy film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. The gate wiring film 65 is preferably formed of the same resistive material as the resistive film 60. In this embodiment, the gate wiring film 65 includes conductive polysilicon. The gate wiring film 65 preferably has a thickness approximately equal to that of the resistive film 60.

[0132] The gate wiring film 65 is disposed on the main surface insulating film 45 at a distance from the gate electrode film 64 and is physically separated from the gate electrode film 64. The gate wiring film 65 has a first connection portion connected to the first end 60A of the resistive film 60 and a second connection portion connected to the second end 60B of the resistive film 60.

[0133] That is, the gate wiring film 65 is electrically connected to the plurality of trench resistance structures 51 via the resistive film 60. Specifically, the gate wiring film 65 is electrically connected to the plurality of first trench resistance structures 51A between the first covering portion 61 and the second covering portion 62 of the resistive film 60, and is electrically connected to the plurality of second trench resistance structures 51B between the first covering portion 61 and the third covering portion 63 of the resistive film 60.

[0134] In this embodiment, the gate wiring film 65 includes a first lower wiring portion 66, a second lower wiring portion 67, and a third lower wiring portion 68. The first lower wiring portion 66 is routed to the pad region 10. Specifically, the first lower wiring portion 66 surrounds the resistance film 60 and the gate electrode film 64 in the pad region 10 from multiple directions (three directions in this embodiment).

[0135] The first lower wiring portion 66 includes a first lower line portion 69 and a plurality of second lower line portions 70A, 70B. The first lower line portion 69 is arranged on the street region 11 side of the resistive film 60 in the pad region 10. The first lower line portion 69 is arranged on the first main surface 3 adjacent to the resistive film 60 so as to face the gate electrode film 64 with the resistive film 60 sandwiched between them in a plan view. The first lower line portion 69 faces the boundary well region 40 (first boundary well region 40A) in the thickness direction with the main surface insulating film 45 sandwiched between them.

[0136] The first lower line portion 69 is formed in a strip shape extending in the second direction Y along the resistive film 60. The first lower line portion 69 has a length in the second direction Y that is greater than the length of the resistive film 60 and the length of the gate electrode film 64. The first lower line portion 69 has one end on one side in the second direction Y (the first side surface 5A side) and the other end on the other side in the second direction Y (the second side surface 5B side).

[0137] The plurality of second lower line portions 70A, 70B include a second lower line portion 70A on one side and a second lower line portion 70B on the other side. The second lower line portion 70A is arranged in a region on one side in the second direction Y (toward the first side surface 5A) of the resistive film 60 and the gate electrode film 64 in the pad region 10. The second lower line portion 70B is arranged in a region on the other side in the second direction Y (toward the second side surface 5B) of the resistive film 60 and the gate electrode film 64 in the pad region 10.

[0138] The second lower line portion 70A is formed in a strip shape extending in the first direction X, and has one end connected to one end of the first lower line portion 69 and the other end located on the peripheral edge side (the third side surface 5C side) of the chip 2. The second lower line portion 70A is further connected to the first end 60A of the resistive film 60 and is formed at a distance from the gate electrode film 64. In other words, the second lower line portion 70A constitutes a first connection portion for the first end 60A. The second lower line portion 70A faces the boundary well region 40 (first boundary well region 40A) in the thickness direction, with the main surface insulating film 45 sandwiched therebetween.

[0139] The second lower line portion 70B is formed in a strip shape extending in the first direction X, and has one end connected to the other end of the first lower line portion 69, and the other end located on the peripheral edge side (third side surface 5C side) of the chip 2. The other second lower line portion 70B is further connected to the second end 60B of the resistive film 60, and is formed at a distance from the gate electrode film 64.

[0140] That is, the second lower line portion 70B constitutes a second connection portion for the first end portion 60A. The other second lower line portion 70B faces the one second lower line portion 70A across the gate electrode film 64. The other second lower line portion 70B faces the boundary well region 40 (first boundary well region 40A) across the main surface insulating film 45 in the thickness direction.

[0141] The second lower wiring portion 67 is routed in the street region 11. Specifically, the second lower wiring portion 67 is drawn out from the first lower wiring portion 66 to the street region 11. More specifically, the second lower wiring portion 67 is drawn out from an inner portion (a central portion in this embodiment) of the first lower line portion 69 to the street region 11, and is formed in a band shape extending in the first direction X.

[0142] In this embodiment, the second lower wiring portion 67 crosses the center of the chip 2. The second lower wiring portion 67 extends in a strip shape so as to be located on one side (the third side surface 5C side) and the other side (the fourth side surface 5D side) in the first direction X with respect to a line that crosses the center of the first main surface 3 in the second direction Y. The second lower wiring portion 67 has one end connected to the first lower line portion 69 (the first lower wiring portion 66) on one side in the first direction X, and the other end on the other side in the first direction X.

[0143] The second lower wiring portion 67 faces the boundary well region 40 (second boundary well region 40B) in the thickness direction, with the main surface insulating film 45 sandwiched therebetween. The second lower wiring portion 67 has a width in the second direction Y that is larger than the width of the street region 11, and is drawn out from the street region 11 to the plurality of active regions 6. The second lower wiring portion 67 covers the plurality of trench isolation structures 15 in the plurality of active regions 6.

[0144] Furthermore, the second lower interconnection portion 67 covers the ends of the plurality of first trench structures 21 in the plurality of active regions 6. As a result, the second lower interconnection portion 67 is electrically connected to the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24, and transmits the gate potential to the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24.

[0145] In this embodiment, the second lower wiring portion 67 is formed integrally with the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24. That is, the second lower wiring portion 67 is made up of portions of the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24 that are extended in the form of a film onto the first main surface 3 (main surface insulating film 45). Of course, the second lower wiring portion 67 may be formed separately from the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24.

[0146] The third lower wiring portion 68 is routed in the outer peripheral region 9. Specifically, the third lower wiring portion 68 is drawn out from the first lower wiring portion 66 to the outer peripheral region 9. More specifically, the third lower wiring portion 68 is drawn out from the other ends of the plurality of second lower line portions 70A, 70B to one side (the first side surface 5A side) and the other side (the second side surface 5B side) of the outer peripheral region 9, and is formed in a band shape extending along the outer peripheral region 9.

[0147] The third lower wiring portion 68 sandwiches the active regions 6 together with the second lower wiring portion 67. Specifically, the third lower wiring portion 68 extends along the periphery (first side surfaces 5A to 5D) of the chip 2 so as to surround the active regions 6 in a plan view, and is connected to the other end of the second lower wiring portion 67. As a result, the third lower wiring portion 68 surrounds the active regions 6 together with the second lower wiring portion 67.

[0148] The third lower wiring part 68 faces the inner part of the peripheral well region 41 across the main surface insulating film 45. Specifically, the third lower wiring part 68 faces the inner part of the peripheral well region 41 at intervals inward from the inner and outer edges of the peripheral well region 41 in plan view.

[0149] 3, third lower wiring portion 68 has, in a portion extending along first side surface 5A, a plurality of lead-out portions 68a led from peripheral region 9 to a plurality of active regions 6. The plurality of lead-out portions 68a cover first trench isolation structure 15A on the first active region 6A side, and cover second trench isolation structure 15B on the second active region 6B side.

[0150] That is, the plurality of lead-out portions 68 a cover the ends of the plurality of first trench structures 21. As a result, the third lower wiring portion 68 is electrically connected to the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24 in the first active region 6A, and transmits the gate potential to the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24.

[0151] Of course, a single lead-out portion 68a may be formed on the first active region 6A side so as to extend in a strip shape along the first trench isolation structure 15A, and a single lead-out portion 68a may be formed on the second active region 6B side so as to extend in a strip shape along the second trench isolation structure 15B.

[0152] In this embodiment, the third lower wiring portion 68 is formed integrally with the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24. That is, the third lower wiring portion 68 is made up of portions of the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24 that are extended in the form of a film onto the first main surface 3 (main surface insulating film 45). Of course, the third lower wiring portion 68 may be formed separately from the plurality of isolated buried electrodes 18 and the plurality of first buried electrodes 24.

[0153] 11 to 15, the semiconductor device 1A includes a first slit 71 defined in a region between the resistive film 60 and the gate electrode film 64. The first slit 71 is formed in a strip shape extending in the second direction Y in a plan view, and defines first to third covering portions 61 to 63 of the resistive film 60.

[0154] The first slits 71 expose the main surface insulating film 45. The first slits 71 are formed outward from the plurality of trench resistance structures 51 in a plan view and face the boundary well region 40 (first boundary well region 40A) in the thickness direction. In other words, the first slits 71 do not face the trench resistance structures 51 in the thickness direction.

[0155] The first slit 71 has a first length in the second direction Y. The first slit 71 is formed narrower than the gate electrode film 64 in the first direction X. The first slit 71 is preferably formed narrower than the resistance film 60 in the first direction X. The first slit 71 is preferably formed narrower than the first trench group 52 in the first direction X. The first slit 71 is preferably formed wider than the trench resistance structure 51 in the first direction X.

[0156] The width of the first slit 71 may be 0.1 μm or more and 10 μm or less. The width of the first slit 71 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. The width of the first slit 71 is preferably 3 μm or more and 7 μm or less.

[0157] 11 to 15, the semiconductor device 1A includes a second slit 72 defined in a region between the resistive film 60 and the gate wiring film 65. Specifically, the second slit 72 is defined in a region between the resistive film 60 and the first lower line portion 69. The second slit 72 faces the first slit 71 with the resistive film 60 interposed therebetween.

[0158] The second slits 72 are formed in a strip shape extending in the second direction Y in a plan view, and define the first to third covering portions 61 to 63 of the resistive film 60. That is, the second slits 72 extend parallel to the first slits 71, and define the resistive film 60 together with the first slits 71. The second slits 72 expose the main surface insulating film 45.

[0159] The second slits 72 are formed outward from the plurality of trench resistance structures 51 in plan view and face the boundary well region 40 (first boundary well region 40A) in the thickness direction. In other words, the second slits 72 do not face the trench resistance structures 51 in the thickness direction. The second slits 72 face the first slits 71 in plan view, with the plurality of first trench resistance structures 51A and the plurality of second trench resistance structures 51B sandwiched therebetween.

[0160] The second slit 72 has a second length in the second direction Y. The second length may be different from the first length of the first slit 71. The second length is preferably equal to or shorter than the first length from the viewpoint of properly connecting the resistive film 60 and the gate wiring film 65. In this embodiment, the second length is less than the first length. Of course, the second length may be approximately equal to the first length. Alternatively, the second length may be greater than the first length.

[0161] The second slits 72 are formed narrower than the gate electrode film 64 in the first direction X. The second slits 72 are preferably formed narrower than the first lower line portions 69 in the first direction X. It is particularly preferable that the second slits 72 are formed narrower than the resistance film 60 in the first direction X. The second slits 72 are preferably formed narrower than the first trench group 52 in the first direction X. The second slits 72 are preferably formed wider than the trench resistance structure 51.

[0162] The width of the second slit 72 may be 0.1 μm or more and 10 μm or less. The width of the second slit 72 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. The width of the second slit 72 is preferably 3 μm or more and 7 μm or less. The width of the second slit 72 may be greater than or equal to the width of the first slit 71. The width of the second slit 72 may be less than the width of the first slit 71. The width of the second slit 72 may be approximately equal to the width of the first slit 71.

[0163] 11 to 15, the semiconductor device 1A includes a plurality of third slits 73 defined in a region between the gate electrode film 64 and the gate wiring film 65. Specifically, the plurality of third slits 73 are defined in a region between the gate electrode film 64 and the plurality of second lower line portions 70A, 70B, respectively.

[0164] The multiple third slits 73 are each formed in a strip shape extending in the first direction X in a plan view, and expose the main surface insulating film 45. The multiple third slits 73 are connected to the first slits 71 and face each other in the second direction Y with the gate electrode film 64 sandwiched between them. That is, the multiple third slits 73, together with the first slits 71, define the gate electrode film 64. Furthermore, the multiple third slits 73, together with the first slits 71, physically and electrically separate the gate electrode film 64 from the gate wiring film 65.

[0165] The third slits 73 are formed narrower than the gate electrode film 64. The third slits 73 are preferably formed narrower than the second lower line portions 70A and 70B. The third slits 73 are particularly preferably formed narrower than the resistance film 60. The third slits 73 are preferably formed narrower than the first trench group 52 (second trench group 53). The third slits 73 are preferably formed wider than the trench resistance structure 51.

[0166] The width of the third slit 73 may be 0.1 μm or more and 10 μm or less. The width of the third slit 73 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less. The width of the third slit 73 is preferably 3 μm or more and 7 μm or less. The width of the third slit 73 may be equal to or greater than the width of the first slit 71. The width of the third slit 73 may be less than the width of the first slit 71. The width of the third slit 73 may be approximately equal to the width of the first slit 71.

[0167] The semiconductor device 1A includes an interlayer insulating film 74 that covers the main surface insulating film 45. The interlayer insulating film 74 is thicker than the main surface insulating film 45. The interlayer insulating film 74 may have a single-layer structure made of a single insulating film, or a layered structure including a plurality of insulating films. The interlayer insulating film 74 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0168] The interlayer insulating film 74 may have a layered structure including a plurality of silicon oxide films. In this case, the interlayer insulating film 74 may include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film, which are examples of silicon oxide films. The NSG film, the PSG film, and the BPSG film may be stacked in any order.

[0169] The interlayer insulating film 74 covers the main surface insulating film 45 in the active region 6, the boundary region 8, and the peripheral region 9. The interlayer insulating film 74 covers the plurality of trench isolation structures 15, the plurality of first trench structures 21, and the plurality of second trench structures 25 in the active region 6.

[0170] The interlayer insulating film 74 covers the plurality of trench resistor structures 51 (resistor-buried electrodes 56), the resistor film 60, the gate electrode film 64, and the gate wiring film 65 in the pad region 10. The interlayer insulating film 74 covers the boundary well region 40 (first boundary well region 40A) with the main surface insulating film 45 sandwiched therebetween in the pad region 10. The interlayer insulating film 74 selectively covers the peripheral well region 41, the FLR 42, and the channel stop region 43 with the main surface insulating film 45 sandwiched therebetween in the peripheral region 9. The stacked film of the main surface insulating film 45 and the interlayer insulating film 74 is an example of an "insulating film" in the present disclosure.

[0171] The interlayer insulating film 74 enters the first slit 71 from above the resistance film 60 and the gate electrode film 64, and has a portion that covers the main surface insulating film 45 within the first slit 71. In other words, the interlayer insulating film 74 faces the boundary well region 40 (first boundary well region 40A) in the thickness direction within the first slit 71, with the main surface insulating film 45 sandwiched therebetween. The interlayer insulating film 74 electrically insulates the resistance film 60 and the gate electrode film 64 within the first slit 71.

[0172] The interlayer insulating film 74 extends into the second slit 72 from above the resistance film 60 and the gate wiring film 65 (first lower line portion 69), and has a portion that covers the main surface insulating film 45 within the second slit 72. In other words, the interlayer insulating film 74 faces the boundary well region 40 (first boundary well region 40A) in the thickness direction within the second slit 72, with the main surface insulating film 45 sandwiched between them. The interlayer insulating film 74 electrically insulates the resistance film 60 and the gate wiring film 65 (first lower line portion 69) within the second slit 72.

[0173] The interlayer insulating film 74 extends into the third slits 73 from above the gate electrode film 64 and the gate wiring film 65 (second lower line portions 70A, 70B), and has portions that cover the main surface insulating film 45 within the third slits 73. In other words, the interlayer insulating film 74 faces the boundary well region 40 (first boundary well region 40A) within the third slits 73 in the thickness direction, with the main surface insulating film 45 sandwiched therebetween.

[0174] The interlayer insulating film 74 electrically insulates the gate electrode film 64 and the gate wiring film 65 within the plurality of third slits 73. The interlayer insulating film 74 has an insulating main surface 75 extending along the first main surface 3 (main surface insulating film 45). The insulating main surface 75 has a first recess portion 76, a second recess portion 77, and a plurality of third recess portions 78 in the pad region 10 (see FIGS. 16 to 22). The first recess portion 76 is formed in a portion covering the first slit 71. The first recess portion 76 is recessed toward the first slit 71 and is formed in a strip shape extending in the second direction Y along the first slit 71 in a plan view.

[0175] The second recess portion 77 is formed in a portion covering the second slit 72. The second recess portion 77 is recessed toward the second slit 72 and is formed in a band shape extending in the second direction Y along the second slit 72 in a plan view. The multiple third recess portions 78 are formed in portions covering the multiple third slits 73. The multiple third recess portions 78 are recessed toward the corresponding third slits 73 and are formed in a band shape extending in the first direction X along the corresponding third slit 73 in a plan view.

[0176] 11 to 22 , the semiconductor device 1A includes at least one first resistor-connecting electrode 81 (a plurality of first resistor-connecting electrodes in this embodiment) embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60. The first resistor-connecting electrode 81 may be referred to as a "first resistor via electrode." The first resistor-connecting electrode 81 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the first resistor-connecting electrode 81 has a stacked structure including a Ti film and a W film.

[0177] In this embodiment, the multiple first resistor connection electrodes 81 are connected to the first covering portion 61 of the resistive film 60. That is, the multiple first resistor connection electrodes 81 are connected to a portion of the resistive film 60 that covers an area outside the multiple trench resistance structures 51. Specifically, the multiple first resistor connection electrodes 81 are connected to a portion of the resistive film 60 that covers a space region 57 between the first trench group 52 (the multiple first trench resistance structures 51A) and the second trench group 53 (the multiple second trench resistance structures 51B).

[0178] The multiple first resistor connection electrodes 81 are formed in regions spaced apart from the multiple trench resistor structures 51 in the second direction Y in plan view, and do not face the multiple trench resistor structures 51 in the first direction X. In this embodiment, the multiple first resistor connection electrodes 81 are each formed in a strip shape extending in the first direction X in plan view, and are arranged at intervals in the second direction Y. In other words, the multiple first resistor connection electrodes 81 are arranged in stripes extending in the first direction X in plan view.

[0179] The plurality of first resistor-connecting electrodes 81 extend in a direction intersecting (orthogonal in this embodiment) the extending direction of the resistive film 60 (the plurality of trench resistor structures 51). That is, the plurality of first resistor-connecting electrodes 81 intersect (orthogonal) with the current direction of the resistive film 60. This allows the current to be appropriately spread from the plurality of first resistor-connecting electrodes 81 to the resistive film 60. That is, current constriction caused by the layout of the plurality of first resistor-connecting electrodes 81 is suppressed, and undesired fluctuations (increases) in the resistance value caused by the current constriction are suppressed.

[0180] The plurality of first resistor-connecting electrodes 81 face only the flat portion of the first main surface 3 across the resistive film 60, and do not face the trench resistor structure 51 across the resistive film 60. The plurality of first resistor-connecting electrodes 81 face the boundary well region 40 (first boundary well region 40A) across the resistive film 60 and the main surface insulating film 45. The plurality of first resistor-connecting electrodes 81 are formed in a region sandwiched between the first slits 71 and the second slits 72 and spaced apart from the first slits 71 and the second slits 72 in plan view.

[0181] That is, the multiple first resistor-connecting electrodes 81 are formed to be narrower than the resistive film 60 in the first direction X. In plan view, the multiple first resistor-connecting electrodes 81 face one or multiple first trench resistor structures 51A on one side in the second direction Y (the first side surface 5A side), and face one or multiple second trench resistor structures 51B on the other side in the second direction Y (the second side surface 5B side).

[0182] The multiple first resistor-connection electrodes 81 only need to face at least two of the multiple first trench resistance structures 51A in the second direction Y, and do not need to face all of the first trench resistance structures 51A. In this embodiment, the multiple first resistor-connection electrodes 81 face some of the multiple first trench resistance structures 51A in the second direction Y. Of course, the multiple first resistor-connection electrodes 81 may face all of the first trench resistance structures 51A in the second direction Y.

[0183] Similarly, the multiple first resistor-connection electrodes 81 only need to face at least two of the multiple second trench resistance structures 51B in the second direction Y, and do not need to face all of the first trench resistance structures 51A. In this embodiment, the multiple first resistor-connection electrodes 81 face some of the multiple second trench resistance structures 51B in the second direction Y. Of course, the multiple first resistor-connection electrodes 81 may face all of the second trench resistance structures 51B in the second direction Y.

[0184] The plurality of first resistor-connecting electrodes 81 have a first connection area S1 with respect to the resistive film 60. The first connection area S1 is defined by the total planar area of ​​the plurality of first resistor-connecting electrodes 81. When a single first resistor-connecting electrode 81 is formed, the first connection area S1 is defined by the planar area of ​​the single first resistor-connecting electrode 81. The first connection area S1 is adjusted according to a first current I1 flowing through the first resistor-connecting electrode 81 (see FIG. 12 ).

[0185] 11 to 22, the semiconductor device 1A includes at least one second resistor connection electrode 82 (in this embodiment, a plurality of second resistor connection electrodes 82) embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 at a location different from that of the first resistor connection electrode 81. The second resistor connection electrode 82 may be referred to as a "second resistor via electrode."

[0186] The second resistor-connecting electrode 82 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the second resistor-connecting electrode 82 has a layered structure including a Ti film and a W film.

[0187] In this embodiment, the plurality of second resistor-connecting electrodes 82 are connected to the second covering portion 62 of the resistive film 60. That is, the plurality of second resistor-connecting electrodes 82 are embedded in the portion of the resistive film 60 that covers the first trench group 52 (the plurality of first trench resistor structures 51A).

[0188] The plurality of second resistor-connecting electrodes 82 form a first gate resistor R1 between themselves and the plurality of first resistor-connecting electrodes 81. The first gate resistor R1 is constituted by the resistive film 60 and portions of the plurality of first trench resistor structures 51A that are located in regions between the plurality of first resistor-connecting electrodes 81 and the plurality of second resistor-connecting electrodes 82. The resistance value of the first gate resistor R1 is adjusted by the distance between the plurality of first resistor-connecting electrodes 81 and the plurality of second resistor-connecting electrodes 82.

[0189] The second resistor connection electrodes 82 are formed in a region facing the first trench resistor structures 51A in the first direction X in plan view. In this embodiment, the second resistor connection electrodes 82 extend in a direction different from that of the first resistor connection electrodes 81 in plan view. Specifically, the second resistor connection electrodes 82 are each formed in a strip shape extending in the second direction Y in plan view, and are arranged at intervals in the first direction X. In other words, the second resistor connection electrodes 82 are arranged in a stripe shape extending in the second direction Y in plan view.

[0190] The second resistor-connecting electrodes 82 are respectively arranged in regions between adjacent first trench resistance structures 51A at intervals from the first trench resistance structures 51A in plan view. That is, the second resistor-connecting electrodes 82 and the first trench resistance structures 51A are arranged alternately in the first direction X.

[0191] In this embodiment, the second resistor-connecting electrodes 82 face only the flat portion of the first main surface 3 across the resistive film 60, and do not face the trench resistor structure 51 across the resistive film 60. The second resistor-connecting electrodes 82 face the boundary well region 40 (first boundary well region 40A) across the resistive film 60 and the main surface insulating film 45.

[0192] The second resistor-connecting electrodes 82 may be arranged in a part of the region between the first trench resistance structures 51 A, and are not necessarily arranged in the entire region between the first trench resistance structures 51 A. The second resistor-connecting electrodes 82 may be arranged in at least one region located on the active region 6 side among the regions between the first trench resistance structures 51 A, and are not necessarily arranged in at least one region located on the gate electrode film 64 side.

[0193] At least one of the plurality of second resistor-connecting electrodes 82 preferably faces the plurality of first resistor-connecting electrodes 81 in the second direction Y in plan view. In this case, it is preferable that at least one of the plurality of second resistor-connecting electrodes 82 located on the gate electrode film 64 side faces the plurality of first resistor-connecting electrodes 81 in the second direction Y.

[0194] At least one of the second resistor-connecting electrodes 82 located on the active region 6 side does not have to face the first resistor-connecting electrodes 81 in the second direction Y. Of course, all the second resistor-connecting electrodes 82 may be arranged to face the first resistor-connecting electrodes 81 in the second direction Y.

[0195] The second resistor-connecting electrodes 82 have a length in the second direction Y that is shorter than the length of the first trench resistor structures 51A. The second resistor-connecting electrodes 82 are preferably arranged in a region closer to the other end of the first trench resistor structures 51A than the longitudinal intermediate portion of the first trench resistor structures 51A.

[0196] The length of the second resistor-connecting electrodes 82 is preferably 1 / 100 to 1 / 2 of the length of the first trench resistor structures 51A. The length of the second resistor-connecting electrodes 82 may be 1 / 20 to 1 / 4 of the length of the first trench resistor structures 51A.

[0197] The plurality of second resistor-connecting electrodes 82 have a second connection area S2 with respect to the resistive film 60. The second connection area S2 is defined by the total planar area of ​​the plurality of second resistor-connecting electrodes 82. When a single second resistor-connecting electrode 82 is formed, the second connection area S2 is defined by the planar area of ​​the single second resistor-connecting electrode 82.

[0198] The second connection area S2 may be approximately equal to the first connection area S1. The second connection area S2 may be larger than the first connection area S1. The second connection area S2 may be smaller than the first connection area S1. The second connection area S2 is adjusted according to the current ratio I2 / I1 (shunt ratio) of the second current I2 flowing through the second resistor connection electrode 82 to the first current I1 flowing through the first resistor connection electrode 81 (see FIG. 12 ).

[0199] In this case, the area ratio S2 / S1 of the second connection area S2 to the first connection area S1 is preferably set to be equal to or greater than the current ratio I2 / I1. For example, when the current ratio I2 / I1 is 1, the area ratio S2 / S1 is preferably set to be equal to or greater than 1. For example, when the current ratio I2 / I1 is 1 / 2, the area ratio S2 / S1 is preferably set to be equal to or greater than 1 / 2.

[0200] When the current ratio I2 / I1 is 1 / 4, the area ratio S2 / S1 is preferably set to 1 / 4 or more. In this embodiment, the current ratio I2 / I1 is approximately 1 / 2, and the second connection area S2 is 1 / 2 or more times the first connection area S1. The second connection area S2 is preferably 2 times or less the first connection area S1.

[0201] 11 to 22, the semiconductor device 1A includes at least one (a plurality of in this embodiment) third resistor connection electrodes 83 embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 at a location different from the first resistor connection electrode 81 and the second resistor connection electrode 82. The third resistor connection electrode 83 may be referred to as a "third resistor via electrode."

[0202] The third resistor-connecting electrode 83 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the third resistor-connecting electrode 83 has a layered structure including a Ti film and a W film.

[0203] In this embodiment, the plurality of third resistor-connecting electrodes 83 are connected to the third covering portion 63 of the resistive film 60. That is, the plurality of third resistor-connecting electrodes 83 are embedded in the portion of the resistive film 60 that covers the second trench group 53 (the plurality of second trench resistor structures 51B).

[0204] The third resistor-connecting electrodes 83 form second gate resistors R2 between themselves and the first resistor-connecting electrodes 81. The second gate resistors R2 are formed by the resistive film 60 and the second trench resistor structures 51B in regions between the first resistor-connecting electrodes 81 and the third resistor-connecting electrodes 83.

[0205] The resistance value of the second gate resistor R2 is adjusted by the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83. In this embodiment, the resistance value of the second gate resistor R2 is approximately equal to the resistance value of the first gate resistor R1. Furthermore, the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83 is approximately equal to the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0206] Of course, the resistance value of the second gate resistor R2 may be different from the resistance value of the first gate resistor R1. In this case, the distance between the plurality of first resistor-connecting electrodes 81 and the plurality of third resistor-connecting electrodes 83 may be different from the distance between the plurality of first resistor-connecting electrodes 81 and the plurality of second resistor-connecting electrodes 82.

[0207] For example, the resistance value of the second gate resistor R2 may be less than the resistance value of the first gate resistor R1. In this case, the distance between the plurality of first resistor-connecting electrodes 81 and the plurality of third resistor-connecting electrodes 83 may be set to be less than the distance between the plurality of first resistor-connecting electrodes 81 and the plurality of second resistor-connecting electrodes 82.

[0208] For example, the resistance value of the second gate resistor R2 may be greater than the resistance value of the first gate resistor R1. In this case, the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83 may be set greater than the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0209] The third resistor-connecting electrodes 83 are formed in a region facing the second trench resistor structures 51B in the first direction X in plan view. In this embodiment, the third resistor-connecting electrodes 83 extend in a direction different from that of the first resistor-connecting electrodes 81 in plan view. Specifically, the third resistor-connecting electrodes 83 are each formed in a strip shape extending in the second direction Y in plan view and are arranged at intervals in the first direction X. In other words, the third resistor-connecting electrodes 83 are arranged in stripes extending in the second direction Y in plan view.

[0210] The third resistor-connecting electrodes 83 are respectively arranged in regions between adjacent second trench resistance structures 51B at intervals from the second trench resistance structures 51B in plan view. That is, the third resistor-connecting electrodes 83 and the second trench resistance structures 51B are arranged alternately in the first direction X.

[0211] In this embodiment, the third resistor-connecting electrodes 83 face only the flat portion of the first main surface 3 across the resistive film 60, and do not face the trench resistor structure 51 across the resistive film 60. The third resistor-connecting electrodes 83 face the boundary well region 40 (first boundary well region 40A) across the resistive film 60 and the main surface insulating film 45.

[0212] The third resistor-connecting electrodes 83 may be arranged in a part of the region between the second trench resistance structures 51 B, and are not necessarily arranged in the entire region between the second trench resistance structures 51 B. The third resistor-connecting electrodes 83 may be arranged in at least one region located on the active region 6 side among the regions between the second trench resistance structures 51 B, and are not necessarily arranged in at least one region located on the gate electrode film 64 side.

[0213] At least one of the plurality of third resistor-connecting electrodes 83 preferably faces the plurality of first resistor-connecting electrodes 81 in the second direction Y in plan view. In this case, it is preferable that at least one of the plurality of third resistor-connecting electrodes 83 located on the gate electrode film 64 side faces the plurality of first resistor-connecting electrodes 81 in the second direction Y.

[0214] At least one of the plurality of third resistor-connecting electrodes 83 located on the active region 6 side does not have to face the plurality of first resistor-connecting electrodes 81 in the second direction Y. Of course, all of the third resistor-connecting electrodes 83 may be arranged to face the plurality of first resistor-connecting electrodes 81 in the second direction Y.

[0215] At least one of the plurality of third resistor connection electrodes 83 preferably faces the plurality of second resistor connection electrodes 82 in the second direction Y in plan view. In this embodiment, the number of the plurality of third resistor connection electrodes 83 is set to be equal to the number of the plurality of second resistor connection electrodes 82, and all of the third resistor connection electrodes 83 face all of the second resistor connection electrodes 82 in a one-to-one correspondence in the second direction Y. Of course, the number of the third resistor connection electrodes 83 may be greater than the number of the second resistor connection electrodes 82 or may be less than the number of the second resistor connection electrodes 82.

[0216] The third resistor-connecting electrodes 83 have a length in the second direction Y that is shorter than the length of the second trench resistor structures 51B. The third resistor-connecting electrodes 83 are preferably arranged in a region closer to the other end of the second trench resistor structures 51B than the longitudinal intermediate portion of the second trench resistor structures 51B.

[0217] The length of the multiple third resistor connection electrodes 83 is preferably 1 / 100 to 1 / 2 of the length of the multiple second trench resistance structures 51B. The length of the multiple third resistor connection electrodes 83 may be 1 / 20 to 1 / 4 of the length of the multiple second trench resistance structures 51B. The length of the third resistor connection electrodes 83 may be approximately equal to the length of the second trench resistance structure 51B. The length of the third resistor connection electrode 83 may be greater than the length of the second trench resistance structure 51B. The length of the third resistor connection electrode 83 may be smaller than the length of the second trench resistance structure 51B.

[0218] The plurality of third resistor-connecting electrodes 83 have a third connection area S3 with respect to the resistive film 60. The third connection area S3 is defined by the total planar area of ​​the plurality of third resistor-connecting electrodes 83. When a single third resistor-connecting electrode 83 is formed, the third connection area S3 is defined by the planar area of ​​the single third resistor-connecting electrode 83. The third connection area S3 is adjusted according to the current ratio I3 / I1 (shunt ratio) of the third current I3 flowing through the third resistor-connecting electrode 83 to the first current I1 flowing through the first resistor-connecting electrode 81 (see FIG. 12 ).

[0219] In this case, the value of the current ratio I3 / I1 of the third connection area S3 to the first connection area S1 is preferably set to be equal to or greater than the value of the current ratio I3 / I1. For example, when the current ratio I3 / I1 is 1, the current ratio I3 / I1 is preferably set to be equal to or greater than 1. For example, when the current ratio I3 / I1 is 1 / 2, the current ratio I3 / I1 is preferably set to be equal to or greater than 1 / 2.

[0220] When the current ratio I3 / I1 is 1 / 4, the current ratio I3 / I1 is preferably set to 1 / 4 or more. In this embodiment, since the third current I3 is approximately equal to the second current I2 and the current ratio I3 / I1 is approximately 1 / 2, the third connection area S3 is set to 1 / 2 or more times the first connection area S1. The third connection area S3 is preferably equal to or less than twice the first connection area S1. Of course, the third current I3 may be greater than the second current I2 or smaller than the second current I2.

[0221] 3 to 10 , the semiconductor device 1A includes a plurality of gate connection electrodes 84 embedded in the interlayer insulating film 74 so as to be electrically connected to the gate wiring film 65 in the inactive region 7. The gate connection electrodes 84 may also be referred to as "gate via electrodes." The plurality of gate connection electrodes 84 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the plurality of gate connection electrodes 84 has a stacked structure including a Ti film and a W film.

[0222] The multiple gate connection electrodes 84 include at least one (multiple in this embodiment) first gate connection electrode 84A and at least one (multiple in this embodiment) second gate connection electrode 84B. The multiple first gate connection electrodes 84A are embedded in a portion of the interlayer insulating film 74 that covers the second lower wiring portion 67 in the street region 11, and are electrically connected to the second lower wiring portion 67 (see FIGS. 7 to 9 ). In this embodiment, the multiple first gate connection electrodes 84A are formed at intervals in the second direction Y and in strip shapes extending in the first direction X.

[0223] The plurality of second gate connection electrodes 84B are embedded in a portion of the interlayer insulating film 74 in the outer peripheral region 9 that covers the third lower wiring portion 68, and are electrically connected to the third lower wiring portion 68 (see FIGS. 3 to 6). In this embodiment, the plurality of second gate connection electrodes 84B are formed at intervals from the inner edge side to the outer edge side of the third lower wiring portion 68, and are formed in strip shapes that extend along the third lower wiring portion 68.

[0224] 3 and 4 , the semiconductor device 1A includes a plurality of first emitter connecting electrodes 85 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to the plurality of emitter regions 29 in the active region 6. The first emitter connecting electrodes 85 may also be referred to as “first emitter via electrodes.”

[0225] The first emitter-connecting electrodes 85 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the first emitter-connecting electrodes 85 have a stacked structure including a Ti film and a W film.

[0226] The multiple first emitter connecting electrodes 85 penetrate the interlayer insulating film 74 and the main surface insulating film 45 and are embedded in the multiple contact holes 30, respectively. The multiple first emitter connecting electrodes 85 are each formed in a strip shape extending in the second direction Y along the multiple first trench structures 21 in a plan view. That is, in this embodiment, the multiple first emitter connecting electrodes 85 extend in the same direction as the multiple second resistor connecting electrodes 82 and the multiple third resistor connecting electrodes 83. The multiple first emitter connecting electrodes 85 are electrically connected to the emitter region 29 and the channel contact region 31 in the corresponding contact holes 30, respectively.

[0227] 3 and 5 , the semiconductor device 1A includes a plurality of second emitter connecting electrodes 86 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to the plurality of emitter electrode films 47 in the active region 6. The second emitter connecting electrodes 86 may also be referred to as "second emitter via electrodes."

[0228] The second emitter-connecting electrodes 86 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the second emitter-connecting electrodes 86 have a layered structure including a Ti film and a W film. The second emitter-connecting electrodes 86 are electrically connected to the second buried electrode 28 via the emitter electrode films 47.

[0229] 3 to 6, semiconductor device 1A includes at least one (in this embodiment, a plurality) first well connection electrodes 87 that penetrate main surface insulating film 45 and are embedded in interlayer insulating film 74 so as to be electrically connected to the inner edge of peripheral well region 41. First well connection electrode 87 may also be referred to as a "first well via electrode."

[0230] The first well connection electrodes 87 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the first well connection electrodes 87 have a stacked structure including a Ti film and a W film.

[0231] In this embodiment, the multiple first well connection electrodes 87 are arranged at intervals from the inner edge side to the outer edge side of the peripheral well region 41. The multiple first well connection electrodes 87 are arranged on the inner edge side of the peripheral well region 41 with respect to the widthwise intermediate portion of the peripheral well region 41, and are electrically connected to a region on the inner edge side of the peripheral well region 41. Specifically, the multiple first well connection electrodes 87 are arranged in a region between the inner edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65. The multiple first well connection electrodes 87 each extend in a strip shape along the inner edge of the peripheral well region 41.

[0232] Each of the first well connection electrodes 87 has a plurality of segment portions 87a in a portion extending in the first direction X (see FIG. 3). The segment portions 87a are respectively arranged in regions between the plurality of lead portions 68a of the gate wiring film 65 (third lower wiring portion 68) at intervals from the lead portions 68a. When a single lead portion 68a extending in a strip shape along the trench isolation structure 15 is formed, the plurality of segment portions 87a are omitted.

[0233] 3 to 6, the semiconductor device 1A includes at least one (in this embodiment, a plurality of) second well connection electrodes 88 that penetrate the main surface insulating film 45 and are embedded in the interlayer insulating film 74 so as to be electrically connected to the outer edge of the peripheral well region 41. The second well connection electrode 88 may also be referred to as a "second well via electrode."

[0234] The second well connection electrodes 88 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the second well connection electrodes 88 have a stacked structure including a Ti film and a W film.

[0235] The multiple second well connection electrodes 88 are arranged at intervals from the inner edge side to the outer edge side of the peripheral well region 41. The multiple second well connection electrodes 88 are arranged on the outer edge side of the peripheral well region 41 with respect to the widthwise intermediate portion of the peripheral well region 41, and are electrically connected to a region on the outer edge side of the peripheral well region 41. Specifically, the multiple second well connection electrodes 88 are arranged in a region between the outer edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65. The multiple second well connection electrodes 88 each extend in a strip shape along the outer edge of the peripheral well region 41.

[0236] 1 and 11 to 22, the semiconductor device 1A includes a gate terminal electrode 90 arranged on the first main surface 3 so as to be electrically connected to the gate resistor structure 50 in the pad region 10 (non-active region 7). Specifically, the gate terminal electrode 90 is arranged on the interlayer insulating film 74. The gate terminal electrode 90 may also be referred to as a "gate pad" or a "gate pad electrode."

[0237] The gate terminal electrode 90 is preferably made of a conductive material different from that of the resistance film 60. The gate terminal electrode 90 is preferably made of a conductive material different from that of the gate electrode film 64. The gate terminal electrode 90 has a lower resistance value than the trench resistance structure 51 and the resistance film 60, and is electrically connected to the trench resistance structure 51 via the resistance film 60. The gate terminal electrode 90 has a lower resistance value than that of the gate electrode film 64.

[0238] In this embodiment, the gate terminal electrode 90 is made of a metal film. The gate terminal electrode 90 may also be referred to as a "gate metal terminal." The gate terminal electrode 90 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0239] The gate terminal electrode 90 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate terminal electrode 90 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side.

[0240] The gate terminal electrode 90 preferably has a thickness greater than the thickness of the resistive film 60 (the thickness of the gate electrode film 64). The thickness of the gate terminal electrode 90 may be 1 μm or more and 10 μm or less. The gate terminal electrode 90 preferably has a planar area of ​​1% or more and 30% or less of the planar area of ​​the first main surface 3. It is particularly preferable that the planar area of ​​the gate terminal electrode 90 is 25% or less of the planar area of ​​the first main surface 3. The planar area of ​​the gate terminal electrode 90 may be 10% or less of the planar area of ​​the first main surface 3.

[0241] The gate terminal electrode 90 is disposed on the interlayer insulating film 74 so as to cover the resistive film 60 and the gate electrode film 64 in the pad region 10. The gate terminal electrode 90 covers the plurality of first resistor connection electrodes 81 in the portion covering the resistive film 60, and is electrically connected to the plurality of first resistor connection electrodes 81. In other words, the gate terminal electrode 90 is electrically connected to the resistive film 60 (first covering portion 61) via the plurality of first resistor connection electrodes 81.

[0242] 11 to 22 (particularly FIGS. 11 to 13), the gate terminal electrode 90 includes a first electrode portion 91 and a second electrode portion 92. The first electrode portion 91 has a relatively wide electrode width in the second direction Y. The first electrode portion 91 is a portion that forms the terminal body of the gate terminal electrode 90, and is located in an area outside the first resistor-connecting electrode 81 in a plan view. The first electrode portion 91 may also be referred to as a "terminal body portion."

[0243] For example, a bonding wire is connected to the first electrode portion 91. Therefore, the first electrode portion 91 is formed wider than the bonding wire junction. The first electrode portion 91 is formed in a polygonal shape (a quadrangular shape in this embodiment) having four sides parallel to the periphery of the chip 2 (the periphery of the pad region 10) in a plan view. The first electrode portion 91 is disposed in a region facing the gate electrode film 64 with the interlayer insulating film 74 sandwiched therebetween.

[0244] The first electrode portion 91 preferably covers 50% or more of the area of ​​the gate electrode film 64 in a plan view. It is particularly preferable that the first electrode portion 91 covers 90% or more of the area of ​​the gate electrode film 64 in a plan view. In this embodiment, the first electrode portion 91 has an electrode width wider than the gate electrode film 64 and covers the entire area of ​​the gate electrode film 64.

[0245] The flatness of the first electrode portion 91 is improved by the gate electrode film 64. The first electrode portion 91 may be electrically insulated from the gate electrode film 64 by the interlayer insulating film 74. The first electrode portion 91 may be electrically connected to the gate electrode film 64 via one or more gate connection electrodes 84 embedded in the interlayer insulating film 74.

[0246] The first electrode portion 91 covers the first slit 71 with the interlayer insulating film 74 sandwiched therebetween, and backfills the first recess portion 76 of the interlayer insulating film 74 (insulating main surface 75). When the gate terminal electrode 90 (first electrode portion 91) is formed so as to partially expose the first recess portion 76, there is a risk that electrode residues generated during the process of forming the gate terminal electrode 90 will remain in the first recess portion 76.

[0247] If electrode residue is present, there is a risk that the gate terminal electrode 90 (first electrode portion 91) may be electrically connected to another electrode via the electrode residue. Therefore, it is preferable that the gate terminal electrode 90 (first electrode portion 91) covers the entire area of ​​the first slit 71 with the interlayer insulating film 74 sandwiched therebetween.

[0248] That is, it is preferable that the gate terminal electrode 90 (first electrode portion 91) fills the entire first recess portion 76 of the interlayer insulating film 74 (insulating main surface 75). This configuration provides a layout that avoids the problem of electrode residue in the first recess portion 76. The present disclosure does not exclude a configuration that includes a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess portion 76.

[0249] The first electrode portion 91 is drawn out from above the gate electrode film 64 across the first slit 71 onto the resistive film 60 in a plan view. In this embodiment, the first electrode portion 91 covers the edge of the resistive film 60 with the interlayer insulating film 74 sandwiched therebetween. Specifically, the first electrode portion 91 covers the edge of the resistive film 60 with a gap on the gate electrode film 64 side with respect to a line that crosses the center of the resistive film 60 in the second direction Y.

[0250] The first electrode unit 91 may cover one or more trench resistance structures 51 with the resistive film 60 interposed therebetween in the portion covering the resistive film 60. The first electrode unit 91 may cover one or more first trench resistance structures 51A with the resistive film 60 interposed therebetween. The first electrode unit 91 may cover one or more second trench resistance structures 51B with the resistive film 60 interposed therebetween. In this embodiment, the first electrode unit 91 covers one first trench resistance structure 51A and one second trench resistance structure 51B with the resistive film 60 interposed therebetween.

[0251] The first electrode portion 91 covers the third slits 73 with the interlayer insulating film 74 in between, and backfills the third recesses 78 in the interlayer insulating film 74 (insulating main surface 75). When the gate terminal electrode 90 (first electrode portion 91) is formed so as to partially expose the third recesses 78, there is a risk that electrode residues generated during the process of forming the gate terminal electrode 90 will remain in the third recesses 78.

[0252] If electrode residues are present, there is a risk that the gate terminal electrode 90 (first electrode portion 91) will be electrically connected to another electrode via the electrode residues. Therefore, it is preferable that the gate terminal electrode 90 (first electrode portion 91) covers the entire areas of the multiple third recess portions 78 with the interlayer insulating film 74 sandwiched therebetween.

[0253] That is, it is preferable that the gate terminal electrode 90 (first electrode portion 91) fills the entire third recess portion 78 of the interlayer insulating film 74 (insulating main surface 75). This configuration provides a layout that avoids the problem of electrode residue in the multiple third recess portions 78. The present disclosure does not exclude a configuration that includes a gate terminal electrode 90 (first electrode portion 91) that partially exposes the multiple third recess portions 78.

[0254] In a plan view, the first electrode portion 91 extends from above the gate electrode film 64 across the third slits 73 onto the second lower line portions 70A, 70B. In this embodiment, the first electrode portion 91 covers the edges of the second lower line portions 70A, 70B with the interlayer insulating film 74 sandwiched therebetween.

[0255] The second electrode portion 92 has a smaller electrode width in the second direction Y than the first electrode portion 91, and is composed of a lead portion that is led out in the first direction X so as to protrude from the first electrode portion 91 toward the plurality of first resistor-connecting electrodes 81. The second electrode portion 92 may also be referred to as a "terminal lead portion." For example, a bonding wire is not connected to the second electrode portion 92. Therefore, the second electrode portion 92 is formed to be narrower than the bonding wire joint portion.

[0256] The protruding direction of the second electrode portion 92 is the same as the extending direction of the plurality of first resistor-connecting electrodes 81. In this embodiment, the second electrode portion 92 is drawn out from the center of the first electrode portion 91 and covers all of the first resistor-connecting electrodes 81.

[0257] The second electrode portion 92 is formed at a distance from the first slit 71 toward the second slit 72 in a plan view, and does not intersect with the first slit 71. Furthermore, the second electrode portion 92 is formed at a distance from the second slit 72 toward the first slit 71 in a plan view, and does not intersect with the second slit 72. In other words, the second electrode portion 92 has a width smaller than the width of the resistive film 60 in the first direction X, and is disposed only in the region directly above the resistive film 60.

[0258] The second electrode portion 92 faces the space region 57 across the main surface insulating film 45, the resistive film 60, and the interlayer insulating film 74. That is, the second electrode portion 92 faces the flat portion of the first main surface 3 in the thickness direction. The second electrode portion 92 also faces the boundary well region 40 (first boundary well region 40A) in the thickness direction.

[0259] The second electrode portion 92 has a width in the first direction X that is larger than the width in the first direction X of the trench resistance structure 51. The second electrode portion 92 has a width in the second direction Y that is smaller than the length in the second direction Y of the trench resistance structure 51. It is preferable that the second electrode portion 92 has a width in the second direction Y that is smaller than the space width of the space region 57.

[0260] In this embodiment, the second electrode portion 92 is formed at a distance from the other end portions (first trench group 52) of the plurality of first trench resistance structures 51A toward the space region 57. In addition, in this embodiment, the second electrode portion 92 is formed at a distance from one end portion (second trench group 53) of the plurality of second trench resistance structures 51B toward the space region 57. In other words, the second electrode portion 92 faces only the space region 57 in the thickness direction, and does not face the plurality of trench resistance structures 51 in the thickness direction.

[0261] Of course, the second electrode portion 92 may face the other ends (first trench group 52) of the plurality of first trench resistance structures 51A in the thickness direction. The second electrode portion 92 may also face one ends (second trench group 53) of the plurality of second trench resistance structures 51B in the thickness direction. Considering the flatness of the second electrode portion 92, it is preferable that the second electrode portion 92 be formed in a region outside the plurality of trench resistance structures 51 and spaced apart from the plurality of trench resistance structures 51 in a plan view.

[0262] 11 to 23 , the semiconductor device 1A includes a gate wiring electrode 93 arranged on the first main surface 3 so as to be electrically connected to the gate resistor structure 50 in the pad region 10 (non-active region 7). Specifically, the gate wiring electrode 93 is arranged on the interlayer insulating film 74. The gate wiring electrode 93 may also be referred to as a "gate finger" or a "gate finger electrode."

[0263] The gate wiring electrode 93 is preferably made of a conductive material different from that of the resistance film 60. The gate wiring electrode 93 is preferably made of a conductive material different from that of the gate wiring film 65. The gate wiring electrode 93 has a lower resistance value than the trench resistance structure 51 and the resistance film 60, and is electrically connected to the gate terminal electrode 90 via the trench resistance structure 51 and the resistance film 60. The gate wiring electrode 93 has a lower resistance value than that of the gate wiring film 65.

[0264] In this embodiment, the gate wiring electrode 93 is made of a metal film. The gate wiring electrode 93 may also be referred to as a “gate metal wiring.” The gate wiring electrode 93 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0265] The gate wiring electrode 93 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate wiring film 65 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side. In other words, the gate wiring film 65 has the same electrode configuration as the gate terminal electrode 90.

[0266] The gate wiring electrode 93 preferably has a thickness greater than the thickness of the resistive film 60 (the thickness of the gate wiring film 65). The thickness of the gate wiring electrode 93 may be 1 μm or more and 10 μm or less. The thickness of the gate wiring electrode 93 is preferably approximately equal to the thickness of the gate terminal electrode 90.

[0267] The gate wiring electrode 93 is routed through the region between the active region 6 and the non-active region 7, is electrically connected to the first trench structure 21 (trench isolation structure 15) in the active region 6, and is electrically connected to the resistance film 60 in the non-active region 7. Specifically, the gate wiring electrode 93 is electrically connected to the first end 60A and the second end 60B of the resistance film 60 via the gate wiring film 65.

[0268] That is, the gate wiring electrode 93 constitutes a parallel resistance circuit PR including a first gate resistance R1 and a second gate resistance R2 between itself and the gate terminal electrode 90 (see also FIG. 24 ). The parallel resistance circuit PR constitutes a gate resistance RG interposed between the gate terminal electrode 90 and the gate wiring electrode 93. The parallel resistance circuit PR is also established between the gate electrode film 64 and the gate wiring film 65. The resistance value of the gate resistance RG (parallel resistance circuit PR) is calculated from the combined resistance of the first gate resistance R1 and the second gate resistance R2 (=(R1+R2) / R1·R2).

[0269] In this embodiment, the gate wiring electrode 93 includes a first upper wiring portion 94, a second upper wiring portion 95, and a third upper wiring portion 96. The first upper wiring portion 94 is disposed in the pad region 10 so as to surround the gate terminal electrode 90 from multiple directions (three directions in this embodiment), and is disposed on the first lower wiring portion 66 of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween.

[0270] The first upper wiring portion 94 includes a first upper line portion 97 and a plurality of second upper line portions 98A and 98B. The first upper line portion 97 is disposed in a region in the pad region 10 that covers the first lower line portion 69 of the gate wiring film 65 with the interlayer insulating film 74 interposed therebetween, and is formed in a strip shape extending in the second direction Y.

[0271] The first upper line portion 97 has one end portion on one side in the second direction Y (the first side surface 5A side) and the other end portion on the other side in the second direction Y (the second side surface 5B side). The first upper line portion 97 covers the second slit 72 with the interlayer insulating film 74 in between, and backfills the second recess portion 77 of the interlayer insulating film 74 (insulating main surface 75).

[0272] When a gate terminal electrode 90 (first electrode portion 91 and / or second electrode portion 92) that intersects with the second recess portion 77 and a gate wiring electrode 93 (first upper line portion 97) that partially exposes the second recess portion 77 are formed, there is a risk that electrode residues generated during the formation process of the gate terminal electrode 90 will remain in the multiple second recess portions 77.

[0273] If electrode residues are present, there is a risk that the gate wiring electrode 93 (first upper line portion 97) will be electrically connected to the gate terminal electrode 90 via the electrode residues. In this case, the gate wiring electrode 93 (first upper line portion 97) and the gate terminal electrode 90 (first electrode portion 91) form a short circuit that does not go through the gate resistor structure 50. Therefore, it is preferable that the gate wiring electrode 93 (first upper line portion 97) covers the entire area of ​​the second slit 72 with the interlayer insulating film 74 sandwiched therebetween.

[0274] That is, it is preferable that the gate wiring electrode 93 (first upper line portion 97) fills the entire second recess portion 77 of the interlayer insulating film 74 (insulating main surface 75). This configuration provides a layout that avoids the problem of electrode residue in the second recess portion 77. The present disclosure does not exclude a configuration that includes a gate terminal electrode 90 (first electrode portion 91 and / or second electrode portion 92) that intersects with the second recess portion 77, and a gate wiring electrode 93 (first upper line portion 97) that partially exposes the second recess portion 77.

[0275] The first upper line portion 97 is drawn out from above the gate wiring film 65 (first lower line portion 69) across the second slit 72 onto the resistive film 60 in a plan view. The first upper line portion 97 covers the edge portion of the resistive film 60 with the interlayer insulating film 74 sandwiched therebetween. The first upper line portion 97 may further cross a straight line that crosses the center of the resistive film 60 in the second direction Y, and cover a portion of the resistive film 60 located in a region on the gate electrode film 64 side of the straight line.

[0276] The first upper line portion 97 is formed at a distance in the first direction X from the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90. In this embodiment, the first upper line portion 97 has a recess 97a that is recessed in the first direction X along the second electrode portion 92 of the gate terminal electrode 90 in a portion that is along the second electrode portion 92 of the gate terminal electrode 90.

[0277] The first upper line portion 97 includes a first connection region 101 and a second connection region 102. The first connection region 101 is formed in a region on one side (the first side surface 5A side) of the recess 97a in the second direction Y, and faces the second electrode portion 92 in the second direction Y. The first connection region 101 covers the second covering portion 62 of the resistive film 60 with the interlayer insulating film 74 sandwiched therebetween. In other words, the first connection region 101 covers the first trench group 52 (the plurality of first trench resistance structures 51A) with the interlayer insulating film 74 and the second covering portion 62 of the resistive film 60 sandwiched therebetween.

[0278] The first connection region 101 further covers the plurality of second resistor connection electrodes 82 and is electrically connected to the plurality of second resistor connection electrodes 82. As a result, the first connection region 101 is electrically connected to the second covering portion 62 of the resistive film 60 and the first trench group 52 (the plurality of first trench resistor structures 51A) via the plurality of second resistor connection electrodes 82.

[0279] The first connection region 101 need only cover one or more first trench resistance structures 51A adjacent to one or more second resistor-connection electrodes 82, and does not need to cover all of the first trench resistance structures 51A. Of course, the first connection region 101 may cover all of the first trench resistance structures 51A.

[0280] The second connection region 102 is formed in a region on the other side (the second side surface 5B side) of the recess 97a in the second direction Y, and faces the second electrode portion 92 in the second direction Y. The second connection region 102 covers the third covering portion 63 of the resistive film 60 with the interlayer insulating film 74 sandwiched therebetween. In other words, the second connection region 102 covers the second trench group 53 (the plurality of second trench resistance structures 51B) with the interlayer insulating film 74 and the third covering portion 63 of the resistive film 60 sandwiched therebetween.

[0281] The second connection region 102 further covers the plurality of third resistor connection electrodes 83 and is electrically connected to the plurality of third resistor connection electrodes 83. As a result, the second connection region 102 is electrically connected to the third covering portion 63 of the resistive film 60 and the second trench group 53 (the plurality of second trench resistor structures 51B) via the plurality of third resistor connection electrodes 83.

[0282] The second connection region 102 need only cover one or more second trench resistance structures 51B adjacent to one or more third resistor-connection electrodes 83, and does not need to cover all of the second trench resistance structures 51B. Of course, the second connection region 102 may cover all of the second trench resistance structures 51B.

[0283] The opposing area of ​​the gate wiring electrode 93 (first upper line portion 97) to the resistive film 60 is preferably larger than the opposing area of ​​the gate terminal electrode 90 (first electrode portion 91 and second electrode portion 92) to the resistive film 60. Of course, the opposing area of ​​the gate wiring electrode 93 may be smaller than the opposing area of ​​the gate terminal electrode 90.

[0284] When a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess portion 76 and a first upper line portion 97 that intersects with the first recess portion 76 are formed, there is a risk that electrode residue generated during the formation process of the gate terminal electrode 90 will remain in the multiple first recess portions 76.

[0285] If electrode residues are present, there is a risk that the gate wiring electrode 93 (first upper line portion 97) will be electrically connected to the gate terminal electrode 90 (first electrode portion 91) via the electrode residues. In this case, the gate wiring electrode 93 (first upper line portion 97) and the gate terminal electrode 90 (first electrode portion 91) form a short circuit that does not go through the gate resistor structure 50.

[0286] Therefore, it is preferable that the first upper line portion 97 is formed at a distance from the first recess portion 76 (first slit 71) toward the second recess portion 77 (second slit 72) in plan view, and does not intersect with the first recess portion 76 (first slit 71). In this embodiment, the gate terminal electrode 90 (first electrode portion 91) covers the entire area of ​​the first recess portion 76.

[0287] That is, the first upper line portion 97 faces the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90 in the first direction X in the region above the resistive film 60. This configuration provides a layout that avoids the problem of electrode residue in the first recess portion 76. The present disclosure does not exclude a configuration that includes a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess portion 76 and a first upper line portion 97 that intersects with the first recess portion 76.

[0288] The first current I1 applied to the gate terminal electrode 90 (second electrode portion 92) is transmitted to the first covering portion 61 of the resistive film 60 via the plurality of first resistor connection electrodes 81. The first current I1 transmitted to the first covering portion 61 is divided into a second current I2 on the second covering portion 62 (first trench group 52) side of the resistive film 60 and a third current I3 on ​​the third covering portion 63 (second trench group 53) side of the resistive film 60.

[0289] The second current I2 is transmitted to the first connection region 101 of the first upper line portion 97 via the plurality of second resistor connection electrodes 82, and the third current I3 is transmitted to the second connection region 102 of the first upper line portion 97 via the plurality of third resistor connection electrodes 83. In this manner, the gate wiring electrode 93 (first upper line portion 97) constitutes a parallel resistance circuit PR including the first gate resistor R1 and the second gate resistor R2 between itself and the gate terminal electrode 90 (second electrode portion 92) (see also FIG. 24 ). The plurality of second upper line portions 98A, 98B include a second upper line portion 98A on one side and a second upper line portion 98B on the other side. The second upper line portion 98A is arranged in a region on one side (toward the first side surface 5A) in the second direction Y with respect to the gate terminal electrode 90 in the pad region 10. The second upper line portion 98B is disposed in the pad region 10 on the other side in the second direction Y (the second side surface 5B side) relative to the gate terminal electrode 90.

[0290] The second upper line portion 98A is formed in a strip shape extending in the first direction X, and has one end connected to one end of the first upper line portion 97 and the other end located on the peripheral side (the third side surface 5C side) of the chip 2. The second upper line portion 98A covers the second lower line portion 70A of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween. The second upper line portion 98A is formed at a distance from the first electrode portion 91 of the gate terminal electrode 90 on one side in the second direction Y.

[0291] The second upper line portion 98B is formed in a strip shape extending in the first direction X, and has one end connected to the other end of the first upper line portion 97, and the other end located on the peripheral side (the third side surface 5C side) of the chip 2. The second upper line portion 98B covers the second lower line portion 70B of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween. The second upper line portion 98B is formed at a distance from the first electrode portion 91 of the gate terminal electrode 90 on the other side in the second direction Y, and faces the second upper line portion 98A with the first electrode portion 91 sandwiched therebetween.

[0292] When the gate terminal electrode 90 (first electrode portion 91) partially exposing the first recess portion 76 and the second upper line portions 98A, 98B intersecting the first recess portion 76 are formed, there is a risk that electrode residues generated during the process of forming the gate terminal electrode 90 will remain in the first recess portion 76. If electrode residues exist, there is a risk that the gate wiring electrode 93 (second upper line portions 98A, 98B) will be electrically connected to the gate terminal electrode 90 (first electrode portion 91) via the electrode residues.

[0293] In this case, the gate wiring electrode 93 (second upper line portions 98A, 98B) and the gate terminal electrode 90 (first electrode portion 91) form a short circuit that does not go through the gate resistor structure 50. Therefore, it is preferable that the second upper line portions 98A, 98B are disposed at a distance from the first recess portion 76 and do not have a portion that covers the first recess portion 76 (a portion that intersects with the first recess portion 76).

[0294] This configuration provides a layout that avoids the problem of electrode residue in the first recess portion 76. The present disclosure does not exclude a configuration that includes a gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recess portion 76 and second upper line portions 98A, 98B that intersect with the first recess portion 76. Furthermore, when a gate terminal electrode 90 (first electrode portion 91) that partially exposes the plurality of third recess portions 78 and second upper line portions 98A, 98B that intersect with the plurality of third recess portions 78 are formed, there is a risk that electrode residue generated during the process of forming the gate terminal electrode 90 will remain in the plurality of third recess portions 78. In such cases, the gate wiring electrode 93 (second upper line portions 98A, 98B) and the gate terminal electrode 90 (first electrode portion 91) form a short circuit that does not go through the gate resistor structure 50.

[0295] Therefore, it is preferable that the second upper line portions 98A, 98B are disposed at a distance from the third recess portions 78 and do not have portions that cover the third recess portions 78 (portions that intersect with the third recess portions 78). This configuration provides a layout that avoids the problem of electrode residue in the third recess portions 78. In this embodiment, the gate terminal electrode 90 (first electrode portion 91) covers the entire areas of the third recess portions 78.

[0296] That is, the second upper line portions 98A, 98B face the first electrode portion 91 of the gate terminal electrode 90 in the second direction Y in the region above the second lower line portions 70A, 70B. The present disclosure does not exclude a configuration including a gate terminal electrode 90 (first electrode portion 91) that partially exposes the plurality of third recess portions 78 and the second upper line portions 98A, 98B that intersect with the plurality of third recess portions 78.

[0297] It is preferable that the second upper line portions 98A, 98B cover the inner portions of the second lower line portions 70A, 70B at a distance from the periphery of the second lower line portions 70A, 70B in plan view. In other words, it is preferable that the second upper line portions 98A, 98B face only the second lower line portions 70A, 70B across the interlayer insulating film 74, and do not face the main surface insulating film 45 across the interlayer insulating film 74.

[0298] The second upper wiring portion 95 is drawn from the first upper wiring portion 94 to the street region 11, and covers the second lower wiring portion 67 of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween. Specifically, the second upper wiring portion 95 is drawn from an inner portion (the central portion in this embodiment) of the first upper line portion 97, and is formed in a band shape extending in the first direction X.

[0299] In this embodiment, the second upper wiring portion 95 crosses the center of the chip 2. The second upper wiring portion 95 extends in a strip shape so as to be located on one side (the third side surface 5C side) and the other side (the fourth side surface 5D side) in the first direction X with respect to a line crossing the center of the first main surface 3 in the second direction Y. The second upper wiring portion 95 has one end connected to the first upper wiring portion 94 on one side in the first direction X, and the other end on the other side in the first direction X. In this embodiment, the other end of the second upper wiring portion 95 is an open end.

[0300] The second upper wiring portion 95 covers the plurality of first gate connection electrodes 84A and is electrically connected to the second lower wiring portion 67 via the plurality of first gate connection electrodes 84A. The second upper wiring portion 95 has a width in the second direction Y that is smaller than the width of the street region 11, and is formed at a distance from the plurality of active regions 6 inward of the street region 11. In other words, the second upper wiring portion 95 is formed at a distance from the plurality of trench isolation structures 15 (the plurality of first trench structures 21) in plan view.

[0301] The third upper wiring portion 96 is drawn from the first upper wiring portion 94 to the peripheral region 9, and covers the third lower wiring portion 68 of the gate wiring film 65 with the interlayer insulating film 74 sandwiched therebetween. Specifically, the third upper wiring portion 96 is drawn from the other ends of the plurality of second upper line portions 98A, 98B to one side (the first side surface 5A side) and the other side (the second side surface 5B side) of the peripheral region 9, and is formed in a band shape extending along the peripheral region 9.

[0302] The third upper wiring portion 96 sandwiches the plurality of active regions 6 together with the second upper wiring portion 95. Specifically, the third upper wiring portion 96 extends along the periphery (first side surfaces 5A to 5D) of the chip 2 so as to surround the plurality of active regions 6 in a plan view. As a result, the third upper wiring portion 96 surrounds the plurality of active regions 6 together with the second upper wiring portion 95. In this embodiment, the third upper wiring portion 96 is formed at a distance from the second upper wiring portion 95. The third upper wiring portion 96 may be connected to the second upper wiring portion 95.

[0303] The third upper wiring portion 96 covers the plurality of second gate connection electrodes 84B and is electrically connected to the third lower wiring portion 68 via the plurality of second gate connection electrodes 84B. The third upper wiring portion 96 preferably has a width smaller than the width of the third lower wiring portion 68 in a plan view. The third upper wiring portion 96 preferably covers an inner portion of the third lower wiring portion 68 at a distance from the periphery of the third lower wiring portion 68 in a plan view.

[0304] 1 to 11 , the semiconductor device 1A includes an emitter terminal electrode 103 disposed on the first main surface 3 at a distance from the gate terminal electrode 90 and the gate wiring electrode 93 in the active region 6. Specifically, the emitter terminal electrode 103 is disposed on the interlayer insulating film 74. The emitter terminal electrode 103 may also be referred to as an "emitter pad" or an "emitter pad electrode." The emitter terminal electrode 103 is preferably made of a different conductive material from the resistive film 60. The emitter terminal electrode 103 is preferably made of a different conductive material from the emitter electrode film 47.

[0305] The emitter terminal electrode 103 has a lower resistance value than the trench resistor structure 51 and the resistor film 60. In this embodiment, the emitter terminal electrode 103 is made of a metal film. The emitter terminal electrode 103 may also be referred to as an "emitter metal terminal." The emitter terminal electrode 103 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0306] The emitter terminal electrode 103 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the emitter terminal electrode 103 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side. In other words, the emitter terminal electrode 103 has the same electrode configuration as the gate terminal electrode 90.

[0307] The emitter terminal electrode 103 preferably has a thickness greater than that of the resistive film 60 (the thickness of the gate electrode film 64). The thickness of the emitter terminal electrode 103 may be 1 μm or more and 10 μm or less. The thickness of the emitter terminal electrode 103 is preferably approximately equal to the thickness of the gate terminal electrode 90.

[0308] The emitter terminal electrode 103 has a planar area larger than that of the gate terminal electrode 90. The planar area of ​​the emitter terminal electrode 103 is preferably 50% to 90% of the planar area of ​​the first main surface 3. It is particularly preferable that the planar area of ​​the emitter terminal electrode 103 be 70% or more of the planar area of ​​the first main surface 3.

[0309] In this embodiment, the emitter terminal electrode 103 includes a first emitter terminal electrode 103A and a second emitter terminal electrode 103B. The first emitter terminal electrode 103A is disposed in a region between the second upper wiring portion 95 and the third upper wiring portion 96 on a portion of the interlayer insulating film 74 that covers the first active region 6A. The first emitter terminal electrode 103A is drawn out from the first active region 6A to the peripheral region 9 in a plan view.

[0310] The first emitter terminal electrode 103A covers the plurality of first emitter connecting electrodes 85 and the plurality of second emitter connecting electrodes 86 in the first active region 6A, and covers the plurality of first well connecting electrodes 87 in the peripheral region 9. The first emitter terminal electrode 103A is electrically connected to the plurality of second trench structures 25, the plurality of emitter regions 29, and the plurality of channel contact regions 31 via the plurality of first emitter connecting electrodes 85 and the plurality of second emitter connecting electrodes 86. The first emitter terminal electrode 103A is electrically connected to the inner edge of the peripheral well region 41 via the plurality of first well connecting electrodes 87.

[0311] The second emitter terminal electrode 103B is disposed on a portion of the interlayer insulating film 74 that covers the second active region 6B, in a region between the second upper wiring portion 95 and the third upper wiring portion 96. The second emitter terminal electrode 103B is drawn out from the second active region 6B to the peripheral region 9 in a plan view.

[0312] The second emitter terminal electrode 103B covers the plurality of first emitter connecting electrodes 85 and the plurality of second emitter connecting electrodes 86 in the second active region 6B, and covers the plurality of first well connecting electrodes 87 in the peripheral region 9. The second emitter terminal electrode 103B is electrically connected to the plurality of second trench structures 25, the plurality of emitter regions 29, and the plurality of channel contact regions 31 via the plurality of first emitter connecting electrodes 85 and the plurality of second emitter connecting electrodes 86. The second emitter terminal electrode 103B is electrically connected to the inner edge portion of the peripheral well region 41 via the plurality of first well connecting electrodes 87.

[0313] The semiconductor device 1A includes an emitter wiring electrode 104 that is extended from the emitter terminal electrode 103 to a region outside the gate wiring electrode 93 on the interlayer insulating film 74. The emitter wiring electrode 104 may also be referred to as an "emitter finger" or an "emitter finger electrode." The emitter wiring electrode 104 is preferably made of a different conductive material from the resistive film 60. The emitter wiring electrode 104 is preferably made of a different conductive material from the emitter electrode film 47.

[0314] The emitter wiring electrode 104 has a lower resistance value than the trench resistor structure 51 and the resistor film 60. In this embodiment, the emitter wiring electrode 104 is made of a metal film. The emitter wiring electrode 104 may also be referred to as an "emitter metal wiring." The emitter wiring electrode 104 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0315] The emitter wiring electrode 104 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the emitter wiring electrode 104 has a layered structure including a Ti film and an Al alloy film (an AlCu alloy film in this embodiment) layered in this order from the chip 2 side. In other words, the emitter wiring electrode 104 has the same electrode configuration as the emitter terminal electrode 103.

[0316] The emitter wiring electrode 104 preferably has a thickness greater than that of the resistive film 60 (thickness of the gate electrode film 64). The thickness of the emitter wiring electrode 104 may be 1 μm or more and 10 μm or less. The thickness of the emitter wiring electrode 104 is preferably approximately equal to the thickness of the gate terminal electrode 90 (emitter terminal electrode 103).

[0317] The emitter wiring electrode 104 is connected to both the first emitter terminal electrode 103A and the second emitter terminal electrode 103B, and is drawn out from the first emitter terminal electrode 103A and the second emitter terminal electrode 103B to an area outside the gate wiring electrode 93 (third upper wiring portion 96).

[0318] The emitter wiring electrode 104 is formed in a band shape extending along the periphery of the chip 2 so as to surround the gate terminal electrode 90, the gate wiring electrode 93, the first emitter terminal electrode 103A, and the second emitter terminal electrode 103B. In this embodiment, the emitter wiring electrode 104 is formed in a ring shape (specifically, a quadrangular ring) extending along the periphery of the chip 2 (first to fourth side surfaces 5A to 5D), and collectively surrounds the gate terminal electrode 90, the gate wiring electrode 93, the first emitter terminal electrode 103A, and the second emitter terminal electrode 103B.

[0319] The emitter wiring electrode 104 is routed over a portion of the interlayer insulating film 74 that covers the outer edge of the peripheral well region 41. The emitter wiring electrode 104 covers the plurality of second well connection electrodes 88 and is electrically connected to the outer edge of the peripheral well region 41 via the plurality of second well connection electrodes 88.

[0320] Fig. 25 is a schematic plan view for explaining the structure of the FLR 42 and the FLR electrode 105 in the second corner portion 202. Fig. 26 is a schematic cross-sectional view taken along line XXVI-XXVI shown in Fig. 25. For convenience of explanation, Fig. 25 omits configurations other than the FLR 42 and the FLR electrode 105 (such as the peripheral well region 41, the channel stop region 43, and the channel stop electrode 106). However, Fig. 26 illustrates the channel stop electrode 106 for clarity.

[0321] 1 , 2 , 10 , 25 and 26 , semiconductor device 1A includes a plurality of FLR electrodes 105 arranged on interlayer insulating film 74 in peripheral region 9. The plurality of FLR electrodes 105 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0322] The plurality of FLR electrodes 105 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the plurality of FLR electrodes 105 have a layered structure including a barrier metal film and a main metal film stacked in this order from the chip 2 side. The barrier metal film is made of, for example, a layered film including a Ti film and a TiN film stacked in this order from the chip 2 side. The main metal film is made of, for example, an Al alloy film (an AlCu alloy film in this embodiment).

[0323] The plurality of FLR electrodes 105 are each formed in a strip shape extending along the corresponding FLR 42. In this embodiment, the plurality of FLR electrodes 105 are each formed in a ring shape (quadratic ring shape) extending along the corresponding FLR 42. In this embodiment, the plurality of FLR electrodes 105 are formed in an electrically floating state.

[0324] The plurality of FLR electrodes 105 face the corresponding FLRs 42 via a stacked film of the insulating film 45 and the interlayer insulating film 74. In this embodiment, the plurality of FLR electrodes 105 cover the corresponding FLRs 42.

[0325] Each FLR electrode 105 has curved portions (hereinafter referred to as "electrode curved portions 105A") whose inner and outer edges have arc shapes in plan view at the four corners 201 to 204. Each FLR electrode 105 has electrode straight portions 105B whose shape is linear in plan view between the four corners 201 to 204.

[0326] At each of the corners 201 to 204, each electrode curved portion 105A has an inner edge 105Aa and an outer edge 105Ab that have different centers of curvature and different curvatures. Furthermore, the magnitude relationship of the curvatures of the inner edge 105Aa and the outer edge 105Ab between two adjacent electrode curved portions 105A is opposite to each other.

[0327] The structure of the FLR electrode 105 and the FLR 42 in the second corner portion 202 will be described with reference to FIGS.

[0328] In the second corner 202, the center of curvature of the inner edge 105Aa and the center of curvature of the outer edge 105Ab of each electrode curved portion 105A are located at different positions on a dividing line L0, which is a straight line that divides the apex angle of the second corner 202 in half, and the radii of curvature of the inner edge 105Aa and the outer edge 105Ab are different. Furthermore, the magnitude relationship between the curvatures of the inner edge 105Aa and the outer edge 105Ab is opposite between two adjacent electrode curved portions 105A.

[0329] 25, the center of curvature of the inner edge 105Aa of the innermost electrode curved portion 105A is Q1, and the center of curvature of the outer edge 105Ab of the electrode curved portion 105A is Q2. The radius of curvature of the inner edge 105Aa is r1, and the radius of curvature of the outer edge 105Ab is r2 (r2 > r1). Therefore, the curvature of the inner edge 105Aa is greater than the curvature of the outer edge 105Ab.

[0330] The center of curvature of the inner edge 105Aa of the second innermost electrode curved portion 105A is Q2, and the center of curvature of the outer edge 105Ab of that electrode curved portion 105A is Q1. The radius of curvature of the inner edge 105Aa is larger than the radius of curvature of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.

[0331] The center of curvature of the inner edge 105Aa of the third inner curved electrode portion 105A is Q1, and the center of curvature of the outer edge 105Ab of the same curved electrode portion 105A is Q2. The radius of curvature of the inner edge 105Aa is smaller than the radius of curvature of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is larger than the curvature of the outer edge 105Ab.

[0332] The center of curvature of the inner edge 105Aa of the outermost electrode curved portion 105A is Q2, and the center of curvature of the outer edge 105Ab of the electrode curved portion 105A is Q1. The radius of curvature of the inner edge 105Aa is larger than the radius of curvature of the outer edge 105Ab. Therefore, the curvature of the inner edge 105Aa is smaller than the curvature of the outer edge 105Ab.

[0333] Each electrode curved portion 105A has a wide region and a narrow region between its inner edge 105Aa and outer edge 105Ab. A part of the wide region of each electrode curved portion 105A is physically and electrically connected to the corresponding FLR 42 via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0334] Specifically, the innermost and third innermost electrode curved portions 105A have the narrowest width at the center of their length and the width increases from the center to both ends. Thus, these electrode curved portions 105A have wide portions 211 at both ends.

[0335] On the other hand, the second innermost electrode curved portion 105A and the outermost electrode curved portion 105A have the widest width at the center of their length and the width becomes narrower from the center to both ends. Therefore, these electrode curved portions 105A have a wide portion 211 at the center of their length.

[0336] In the second corner portion 202, with respect to the straight line connecting the center of curvature Q1 and the vertex of the second corner portion 202, the angle in the counterclockwise direction around the center of curvature Q1 is considered negative, and the angle in the clockwise direction around the center of curvature Q1 is considered positive.

[0337] In this embodiment, in the second corner portion 202, one end of the inner edge 105Aa and one end of the outer edge 105Ab of each electrode curved portion 105A are positioned on a line L1 whose rotation angle around the center of curvature Q1 is -45 degrees with respect to the line connecting the center of curvature Q1 and the vertex of the second corner portion 202.

[0338] In addition, in this embodiment, at the second corner portion 202, the other ends of the inner edge 105Aa and the outer edge 105Ab of each electrode curved portion 105A are located on a line L2 that forms an angle of +45 degrees with the center of curvature Q1 as its center with respect to the line connecting the center of curvature Q1 and the vertex of the second corner portion 202.

[0339] In the example of Figure 25, the widths of both ends of the innermost electrode curved portion 105A and the third innermost electrode curved portion 105A are larger than the widths of both ends of the second innermost electrode curved portion 105A and the outermost electrode curved portion 105A, respectively.

[0340] The width of the electrode straight line portions 105B connected to both ends of each electrode curve portion 105A is equal to the width of both ends of the electrode curve portion 105A.

[0341] Each FLR 42 has curved portions (hereinafter referred to as "FLR curved portions 42A") whose inner and outer edges have arc shapes in plan view at the four corners 201 to 204. Each FLR 42 has FLR straight portions 42B whose shape is linear in plan view between the four corners 201 to 204.

[0342] In each of the corners 201 to 204, the FLR curved portion 42A has a center of curvature and an inner edge 42Aa and an outer edge 42Ab that are different from each other. Furthermore, the magnitude relationship of the curvature of the inner edge 42Aa and the outer edge 42Ab between two adjacent FLR curved portions 42A is opposite to each other.

[0343] The structure of the FLR 42 in the second corner portion 202 will be described with reference to FIGS.

[0344] In the second corner 202, the centers of curvature of the inner edge 42Aa and the outer edge 42Ab of each FLR curved portion 42A are located at different positions on a dividing line L0, which is a straight line that divides the apex angle of the second corner 202 in half, and the radii of curvature of the inner edge 42Aa and the outer edge 42Ab are different. Furthermore, the magnitude relationship between the curvatures of the inner edge 42Aa and the outer edge 42Ab is opposite between two adjacent FLR curved portions 42A.

[0345] In the example of Figure 25, the center of curvature of the inner edge 42Aa of the innermost FLR curved portion 42A is Q1, and the center of curvature of the outer edge 42Ab is Q2. The radius of curvature of the inner edge 42Aa is smaller than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is larger than the curvature of the outer edge 42Ab.

[0346] The center of curvature of the inner edge 42Aa of the second-inside FLR curved portion 42A is Q2, and the center of curvature of the outer edge 42Ab is Q1. The radius of curvature of the inner edge 42Aa is larger than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.

[0347] The center of curvature of the inner edge 42Aa of the third innermost FLR curved portion 42A is Q1, and the center of curvature of the outer edge 42Ab is Q2. The radius of curvature of the inner edge 42Aa is smaller than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is larger than the curvature of the outer edge 42Ab.

[0348] The center of curvature of the inner edge 42Aa of the outermost FLR curved portion 42A is Q2, and the center of curvature of the outer edge 42Ab is Q1. The radius of curvature of the inner edge 42Aa is larger than the radius of curvature of the outer edge 42Ab. Therefore, the curvature of the inner edge 42Aa is smaller than the curvature of the outer edge 42Ab.

[0349] In this embodiment, the center of curvature of the inner edge 42Aa of each FLR curved portion 42A coincides with the center of curvature of the inner edge 105Aa of the corresponding electrode curved portion 105 A. Similarly, the center of curvature of the outer edge 42Ab of each FLR curved portion 42A coincides with the center of curvature of the outer edge 105Ab of the corresponding electrode curved portion 105 A.

[0350] In addition, in a plan view, the inner edge 42Aa of each FLR curved portion 42A is set back more inwardly than the inner edge 105Aa of the corresponding electrode curved portion 105A, and the outer edge 42Ab of each FLR curved portion 42A is set back more inwardly than the outer edge 105Ab of the corresponding electrode curved portion 105A. Therefore, the width of each FLR curved portion 42A at each longitudinal position is narrower than the width of the corresponding electrode curved portion 105A at the corresponding longitudinal position.

[0351] The inner edge 42Aa of each FLR curved portion 42A may be positioned further outward than the inner edge 105Aa of the corresponding electrode curved portion 105A. The outer edge 42Ab of each FLR curved portion 42A may be positioned further outward than the outer edge 105Ab of the corresponding electrode curved portion 105A.

[0352] Only one of the inner edge 42Aa and the outer edge 42Ab of each FLR curved portion 42A may extend further outward than the corresponding side edges 105Aa, 105Ab of the corresponding electrode curved portion 105A. Alternatively, both the inner edge 42Aa and the outer edge 42Ab of each FLR curved portion 42A may extend further outward than the corresponding side edges 105Aa, 105Ab of the corresponding electrode curved portion 105A.

[0353] The innermost FLR curved portion 42A and the third innermost FLR curved portion 42A have the narrowest width at the center of their length and the width increases from the center to both ends. Therefore, these FLR curved portions 42A have wide portions 221 at both ends.

[0354] On the other hand, the second innermost FLR curved portion 42A and the outermost FLR curved portion 42A have the widest width at the center of their length and the width becomes narrower from the center to both ends. Therefore, these FLR curved portions 42A have a wide portion 221 at the center of their length.

[0355] In this embodiment, at the second corner portion 202, one end of the inner edge 42Aa and one end of the outer edge 42Ab of each FLR curved portion 42A are disposed on a straight line L1.

[0356] In this embodiment, at the second corner portion 202, the other ends of the inner edge 42Aa and the outer edge 42Ab of each FLR curved portion 42A are disposed on a straight line L2.

[0357] In the example of Figure 25, the widths of both ends of the innermost FLR curve portion 42A and the third FLR curve portion 42A from the inside are greater than the widths of both ends of the second FLR curve portion 42A from the inside and the outermost FLR curve portion 42A, respectively.

[0358] The width of the FLR straight line portion 42B connected to both ends of each FLR curve portion 42A is equal to the width of both ends of the FLR curve portion 42A.

[0359] In the innermost electrode curved portion 105A and the third innermost electrode curved portion 105A, a portion of the wide portion 211 at both ends is physically and electrically connected to the wide portion 221 at both ends of the corresponding FLR curved portion 42A via the FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45, respectively.

[0360] In the third innermost electrode curved portion 105A and the outermost electrode curved portion 105A, a portion of the central length of the wide portion 211 is physically and electrically connected to the central length of the wide portion 221 of the corresponding FLR curved portion 42A via an FLR connection electrode 89 that continuously penetrates the interlayer insulating film 74 and the main surface insulating film 45.

[0361] In this embodiment, the FLR connection electrodes 89 are not formed on portions (straight electrode portions 105B) other than the curved portions 105A of the plurality of FLR electrodes 105. Note that the FLR connection electrodes 89 may be formed on the straight electrode portions 105B of the plurality of FLR electrodes 105.

[0362] The FLR connection electrodes 89 may also be referred to as "FLR via electrodes." The multiple FLR connection electrodes 89 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the multiple FLR connection electrodes 89 have a stacked structure including a Ti film and a W film. The FLR connection electrodes 89 may also be formed integrally with the corresponding FLR electrodes 105 (electrode curved portions 105A).

[0363] The plurality of FLR connection electrodes 89 have a circular shape in a plan view. The plurality of FLR connection electrodes 89 may have a polygonal shape such as a square shape in a plan view, or may have an elliptical shape in a plan view. In this embodiment, the plurality of FLR connection electrodes 89 are formed in an electrically floating state.

[0364] In this embodiment, the FLR 42, the FLR electrode 105, and the FLR connection electrode 89 at the first corner portion 201 have planar shapes that are symmetrical to their planar shapes at the second corner portion 202 with respect to a line that passes through the center of the chip 2 in the first direction X and extends in the second direction Y.

[0365] In this embodiment, the FLR 42, the FLR electrode 105, and the FLR connection electrode 89 at the third corner portion 201 have planar shapes that are symmetrical to their planar shapes at the second corner portion 202 with respect to a line that passes through the center of the chip 2 in the second direction Y and extends in the first direction X.

[0366] In this embodiment, the FLR 42, the FLR electrode 105, and the FLR connection electrode 89 at the fourth corner portion 201 have planar shapes that are symmetrical to their planar shapes at the third corner portion 201 with respect to a line that passes through the center of the chip 2 in the first direction X and extends in the second direction Y.

[0367] In addition, the corner portion of each FLR 42 in each corner portion 201 to 204 (the portion corresponding to the aforementioned FLR curve portion) only needs to have a width greater than that of the FLR connection electrode 89 at the position where the FLR connection electrode 89 is placed, and the planar shape of its inner edge and outer edge does not need to be an arc shape.

[0368] According to this embodiment, a novel connection structure between the FLR 42 and the FLR electrode 105 is obtained.

[0369] The planar shape of the FLR 42 and the FLR electrode 105 at the second corner portion 202 may be as shown in Fig. 27. In Fig. 27, parts corresponding to those in Fig. 25 are denoted by the same reference numerals as in Fig. 25.

[0370] The structure of each electrode curved portion 105A in FIG. 27 is almost the same as the structure of the corresponding electrode curved portion 105A in FIG. 25, but the positions of both ends of each electrode curved portion 105A are different from the positions of both ends of the corresponding electrode curved portion 105A in FIG.

[0371] In Figure 27, the angle between the dividing line L0 and a straight line connecting one end of the inner edge 105Aa of each electrode curved portion 105A to the center of curvature of the inner edge 105Aa, and the angle between the dividing line and a straight line connecting one end of the outer edge 105Ab of each electrode curved portion 105A to the center of curvature of the outer edge 105Ab are set so that the width of one end of each electrode curved portion 105A is a predetermined width W1.

[0372] In addition, the angle between the dividing line L0 and the straight line connecting the other end of the inner edge 105Aa of each electrode curved portion 105A to the center of curvature of the inner edge 105Aa, and the angle between the dividing line L0 and the straight line connecting the other end of the outer edge 105Ab of each electrode curved portion 105A to the center of curvature of the outer edge 105Ab are set so that the width of the other end of each electrode curved portion 105A is a predetermined width W1.

[0373] The width of the straight electrode portions 105B connected to both ends of each curved electrode portion 105A is also formed to a predetermined width W1.

[0374] The structure of each FLR curve portion 42A in FIG. 27 is substantially the same as the structure of the corresponding FLR curve portion 42A in FIG. 25, but the positions of both ends of each FLR curve portion 42A are different from the positions of both ends of the corresponding FLR curve portion 42A in FIG.

[0375] In Figure 27, the angle between the dividing line L0 and a straight line connecting one end of the inner edge 42Aa of each FLR curved portion 42A to the center of curvature of the inner edge 42Aa, and the angle between the dividing line L0 and a straight line connecting one end of the outer edge 42Ab of each FLR curved portion 42A to the center of curvature of the outer edge 42Ab are set so that the width of one end of each FLR curved portion 42A is a predetermined width W2.

[0376] In addition, the angle between the straight line connecting the other end of the inner edge 42Aa of each FLR curved portion 42A and the center of curvature of the inner edge 42Aa and the dividing line L0, and the angle between the straight line connecting the other end of the outer edge 42Ab of each FLR curved portion 42A and the center of curvature of the outer edge 42Ab and the dividing line L0 are set so that the width of the other end of each FLR curved portion 42A is a predetermined width W2.

[0377] The width of the FLR straight line portions 42B connected to both ends of each FLR curved line portion 42A is also formed to a predetermined width W2.

[0378] In the structure of Figure 27, for example, even if the width of the electrode straight portion 105B of the FLR electrode 105 is narrower than the width required to connect the electrode straight portion 105B to the FLR 42 via the FLR connection electrode 89, it is easier to secure an area in the electrode curved portion 105A for connection to the FLR 42 via the FLR connection electrode 89.

[0379] In other words, the width of the electrode straight portion 105B of the FLR electrode 105 can be made narrower than the width required to connect the electrode straight portion 105B to the FLR 42 via the FLR connection electrode 89. This makes it possible to narrow the overall width of the multiple FLR electrodes 105, thereby enabling the chip to be made smaller.

[0380] 1 and 10 , semiconductor device 1A includes a channel stop electrode 106 arranged on interlayer insulating film 74 in peripheral region 9. Channel stop electrode 106 may be referred to as an "EQR (EQui-potential Ring) electrode." Channel stop electrode 106 may include at least one of a Ti film, a TiRiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0381] The channel stop electrode 106 may include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the channel stop electrode 106 has a layered structure including a barrier metal film and a main metal film, which are layered in this order from the chip 2 side. The barrier metal film is made of, for example, a layered film including a Ti film and a TiN film, which are layered in this order from the chip 2 side. The main metal film is made of, for example, an Al alloy film (an AlCu alloy film in this embodiment).

[0382] The channel stop electrode 106 is formed in a band shape extending along the periphery of the chip 2. In this embodiment, the channel stop electrode 106 is formed in a ring shape (quadratic ring shape) extending along the periphery of the chip 2. The channel stop electrode 106 extends from above the interlayer insulating film 74 into the removed portion 46 of the interlayer insulating film 74 and is electrically connected to the channel stop region 43. The channel stop electrode 106 is formed in an electrically floating state. The channel stop region 43 may be formed at a distance inward from the periphery of the chip 2 so as to expose the peripheral portion of the first main surface 3 (channel stop region 43).

[0383] The semiconductor device 1A includes a collector electrode 107 covering the second main surface 4. The collector electrode 107 is electrically connected to the collector region 14 exposed from the second main surface 4. The collector electrode 107 forms an ohmic contact with the collector region 14. The collector electrode 107 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).

[0384] The semiconductor device 1A includes a chip 2, a trench resistor structure 51, a resistive film 60, a gate terminal electrode 90, and a gate wiring electrode 93. The chip 2 has a first main surface 3. The trench resistor structure 51 is formed on the first main surface 3. The resistive film 60 is electrically connected to the trench resistor structure 51 on the first main surface 3.

[0385] The gate terminal electrode 90 has a lower resistance value than the resistance film 60, and is electrically connected to the trench resistance structure 51 via the resistance film 60 on the first main surface 3. The gate wiring electrode 93 has a lower resistance value than the resistance film 60, and is electrically connected to the gate terminal electrode 90 via the trench resistance structure 51 and the resistance film 60 on the first main surface 3.

[0386] According to this configuration, the gate resistor RG including the trench resistor structure 51 and the resistive film 60 can be interposed between the gate terminal electrode 90 and the gate wiring electrode 93. In particular, according to this configuration, the trench resistor structure 51 is incorporated into the chip 2 in the region between the gate terminal electrode 90 and the gate wiring electrode 93, which can suppress an increase in the area occupied by the gate resistor RG relative to the first main surface 3. Therefore, in a configuration including the gate resistor RG, it is possible to provide a semiconductor device 1A having a novel layout that contributes to miniaturization.

[0387] The semiconductor device 1A preferably includes a gate electrode film 64 and a gate wiring film 65. The gate electrode film 64 is disposed on the first main surface 3 adjacent to the resistive film 60. The gate wiring film 65 is disposed on the first main surface 3 adjacent to the resistive film 60 so as to face the gate electrode film 64 with the resistive film 60 in between.

[0388] In such a structure, the gate terminal electrode 90 preferably covers the gate electrode film 64. Furthermore, the gate wiring electrode 93 preferably covers the gate wiring film 65. According to this configuration, in a configuration in which the resistance film 60, the gate electrode film 64, and the gate wiring film 65 are provided on the first main surface 3, it is possible to provide a semiconductor device 1A having a novel layout that contributes to miniaturization.

[0389] The resistive film 60 preferably has a first end 60A on one side and a second end 60B on the other side. In this case, the gate wiring film 65 preferably has a first connection portion connected to the first end 60A of the resistive film 60 and a second connection portion connected to the second end 60B of the resistive film 60. In this case, the gate wiring electrode 93 is preferably electrically connected to the resistive film 60 via the gate wiring film 65.

[0390] According to this configuration, the gate wiring electrode 93 can be electrically connected to the resistance film 60 via the gate wiring film 65, eliminating the need to directly connect the gate wiring electrode 93 to the resistance film 60. This allows the design rules for the gate wiring electrode 93 to be relaxed, and improves the degree of freedom in designing the gate wiring electrode 93.

[0391] The semiconductor device 1A preferably includes a first slit 71 defined between the resistive film 60 and the gate electrode film 64, and a second slit 72 defined between the resistive film 60 and the gate wiring film 65. According to this configuration, the first slit 71 and the second slit 72 can appropriately separate (define) the resistive film 60 from the gate electrode film 64 and the gate wiring film 65. This can improve the accuracy of the resistance value of the resistive film 60.

[0392] The gate terminal electrode 90 preferably crosses the first slit 71 in a plan view and covers the resistance film 60 and the gate electrode film 64. The gate wiring film 65 preferably crosses the second slit 72 in a plan view and covers the resistance film 60 and the gate electrode film 64. The first slit 71 is preferably formed narrower than the resistance film 60. The second slit 72 is preferably formed narrower than the resistance film 60.

[0393] The trench resistance structure 51 preferably extends in a strip shape in the second direction Y (one direction) in a plan view. In this case, the resistance film 60 preferably extends in a strip shape in the second direction Y (one direction) in a plan view. The first slit 71 preferably extends in a strip shape in the second direction Y (one direction) in a plan view. The second slit 72 preferably extends in a strip shape in the second direction Y (one direction) in a plan view. The first slit 71 may have a first length in the second direction Y (one direction), and the second slit 72 may have a second length in the second direction Y (one direction) that is shorter than the first length.

[0394] The semiconductor device 1A preferably includes a third slit 73 defined between the gate electrode film 64 and the gate wiring film 65. With this configuration, the third slit 73 can appropriately separate (define) the gate wiring film 65 from the gate electrode film 64. This can prevent the gate wiring film 65 from forming a short circuit with the gate electrode film 64 that does not go through the resistance film 60. The gate terminal electrode 90 preferably covers the gate electrode film 64 and the gate wiring film 65 across the third slit 73 in plan view.

[0395] Preferably, a plurality of trench resistance structures 51 are formed at intervals on the first main surface 3. In this case, the resistance film 60 preferably covers the plurality of trench resistance structures 51. According to this configuration, the resistance value of the gate resistance RG can be adjusted by utilizing the plurality of trench resistance structures 51.

[0396] The resistive film 60 preferably has a first covering portion 61 that covers the first main surface 3 outside the trench resistive structure 51, and a second covering portion 62 that covers the trench resistive structure 51. In this case, the gate terminal electrode 90 is preferably electrically connected to the resistive film 60 at a portion that covers the first covering portion 61. Furthermore, the gate wiring electrode 93 is preferably electrically connected to the resistive film 60 at a portion that covers the second covering portion 62. With this configuration, a portion of the resistive film 60 and a portion of the trench resistive structure 51 can be appropriately interposed in the region between the gate terminal electrode 90 and the gate wiring electrode 93.

[0397] The semiconductor device 1A preferably includes an interlayer insulating film 74, a first resistor-connecting electrode 81, and a second resistor-connecting electrode 82. The interlayer insulating film 74 covers the resistive film 60. The first resistor-connecting electrode 81 is embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60. The second resistor-connecting electrode 82 is embedded in the interlayer insulating film 74 so as to be electrically connected to the resistive film 60 at a position different from that of the first resistor-connecting electrode 81.

[0398] In this configuration, the gate terminal electrode 90 is preferably disposed on the interlayer insulating film 74 so as to be electrically connected to the resistance film 60 via the first resistor-connecting electrode 81. Furthermore, the gate wiring electrode 93 is preferably disposed on the interlayer insulating film 74 so as to be electrically connected to the resistance film 60 via the second resistor-connecting electrode 82. With this configuration, the gate resistor RG can be configured in the region between the first resistor-connecting electrode 81 and the second resistor-connecting electrode 82. The resistance value of the gate resistor RG can be adjusted by adjusting the distance between the first resistor-connecting electrode 81 and the second resistor-connecting electrode 82.

[0399] The second resistor-connection electrode 82 may extend in a direction different from that of the first resistor-connection electrode 81. For example, the first resistor-connection electrode 81 may extend in a first direction X (one direction) in a plan view, and the second resistor-connection electrode 82 may extend in a second direction Y (intersecting direction) that intersects with the first direction X (one direction) in a plan view.

[0400] The plurality of first resistor-connecting electrodes 81 are preferably embedded in the interlayer insulating film 74. The plurality of second resistor-connecting electrodes 82 are preferably embedded in the interlayer insulating film 74. A second connection area S2 of the second resistor-connecting electrode 82 with respect to the resistive film 60 may be smaller than a first connection area S1 of the first resistor-connecting electrode 81 with respect to the resistive film 60.

[0401] The gate terminal electrode 90 preferably has a first electrode portion 91 located outside the first resistor-connecting electrode 81 in a plan view, and a second electrode portion 92 protruding from the first electrode portion 91 toward the first resistor-connecting electrode 81 with a width narrower than that of the first electrode portion 91. In this case, the first electrode portion 91 is preferably formed as a terminal main body portion of the gate terminal electrode 90. Furthermore, the second electrode portion 92 is preferably formed as a terminal lead portion led out from the terminal main body portion.

[0402] These configurations ensure an area to which the gate potential is applied by the first electrode portion 91, and an area electrically connected to the resistive film 60 by the second electrode portion 92. For example, when a conductive bonding material such as a bonding wire is bonded to the gate terminal electrode 90, the conductive bonding material can be bonded to the first electrode portion 91. This makes it possible to prevent stress caused by the conductive bonding material from occurring in the resistive film 60 and the trench resistor structure 51. This makes it possible to prevent degradation of the electrical characteristics of the gate resistor RG.

[0403] The semiconductor device 1A preferably includes a p-type boundary well region 40 formed in a surface layer portion of the first main surface 3. With this configuration, the boundary well region 40 can improve the breakdown voltage. In this case, the trench resistance structure 51 is preferably formed at a distance from the bottom of the boundary well region 40 toward the first main surface 3. With this configuration, the boundary well region 40 can suppress electric field concentration on the bottom wall of the trench resistance structure 51. Therefore, the breakdown voltage can be appropriately improved.

[0404] The semiconductor device 1A preferably includes an active region 6 provided on the first main surface 3, a non-active region 7 provided outside the active region 6 on the first main surface 3, and a first trench structure 21 (trench gate structure) formed in the active region 6. In this case, the trench resistance structure 51 is preferably formed in the non-active region 7. Furthermore, the resistance film 60 preferably covers the trench resistance structure 51 in the non-active region 7.

[0405] Furthermore, it is preferable that the gate terminal electrode 90 is electrically connected to the resistance film 60 in the non-active region 7. It is also preferable that the gate wiring electrode 93 is electrically connected to the first trench structure 21 in the active region 6, and is electrically connected to the resistance film 60 in the non-active region 7. With these configurations, the gate resistance RG is formed in the non-active region 7, so that shrinkage of the active region 6 can be suppressed.

[0406] For example, in the above-described embodiment, the four corner portions 202 to 204 have the FLR-FLR electrode connection structure shown in Fig. 25 or 27, but it is sufficient if at least one of the four corner portions 202 to 204 has the FLR-FLR electrode connection structure shown in Fig. 25 or 27.

[0407] In the above embodiment, the chip 2 is made of a silicon single crystal substrate, but the chip 2 may be made of a SiC (silicon carbide) single crystal substrate.

[0408] In the above-described embodiments, the n-type semiconductor regions may be replaced with p-type semiconductor regions, and the p-type semiconductor regions may be replaced with n-type semiconductor regions. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0409] In the above-described embodiment, the p-type collector region 14 is shown. However, an n-type drain region may be used instead of the p-type collector region 14. In this case, the buffer region 13 is omitted. The n-type drain region may be formed of an n-type semiconductor substrate, and the n-type drift region 12 may be formed of an n-type epitaxial layer. The n-type impurity concentration of the drift region 12 is preferably lower than the n-type impurity concentration of the drain region.

[0410] In this case, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure is formed instead of the IGBT. The specific configuration in this case can be obtained by replacing the "emitter" with the "source" and the "collector" with the "drain" in the above description.

[0411] In the above-described embodiment, the first direction X and the second direction Y are defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any directions as long as they maintain a mutually intersecting (specifically, perpendicular) relationship. For example, the first direction X may be the extending direction of the third side surface 5C (fourth side surface 5D), and the second direction Y may be the extending direction of the first side surface 5A (second side surface 5B). Furthermore, the first direction X may be a direction intersecting the first to fourth side surfaces 5A to 5D, and the second direction Y may be a direction intersecting the first to fourth side surfaces 5A to 5D.

[0412] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following clauses may be replaced with "semiconductor switching device," "IGBT semiconductor device," "RC-IGBT semiconductor device," or "MISFET semiconductor device."

[0413] [A1] A chip (2) having a first main surface (3) of a rectangular shape in a plan view and a second main surface (4) on the opposite side thereof; an active region (6) provided on the first main surface (3) and having an element structure; a peripheral region (9) outside the active region, provided on the outer periphery of the first main surface (3) and having four corner portions (201-204); a plurality of field limiting rings (hereinafter referred to as "FLRs (42)") formed in the peripheral region (9) on a surface layer of the first main surface (3) so as to surround the active region (6); an insulating film (45, 74) formed on the first main surface (3) and covering the plurality of FLRs (42); and a plurality of FLR electrodes (105) arranged opposite each of the plurality of FLRs (42) via the insulating film (45, 74), Each of the FLR electrodes (105) has an electrode curved portion (105A) whose inner edge (105Aa) and outer edge (105Ab) have arcuate shapes in a plan view in at least one corner (201-204) of the four corners (201-204), and in the at least one corner (201-204), each of the electrode curved portions (105A) has inner edges (105Aa) and outer edges (105Ab) whose centers of curvature and curvatures are different, and the magnitude relationship of the curvatures of the inner edges (105Aa) and outer edges (105Ab) between two adjacent electrode curved portions (105A) is reversed. As a result, in the corner portions (201 to 204), each of the electrode curved portions (105A) has a wide region and a narrow region between the inner edge (105Aa) and the outer edge (105Ab), and a part of the wide region in each of the electrode curved portions (105A) is physically and electrically connected to the corresponding FLR (42) via an FLR connection electrode (89) that penetrates the insulating film (45, 74).

[0414] [A2] The semiconductor device according to [A1], wherein in at least one corner portion (201-204), the center of curvature of the inner edge (105Aa) and the center of curvature of the outer edge (105Ab) of each electrode curved portion (105A) are located at different positions on a dividing line (L0), which is a straight line that divides the apex angle of the corner portion (201-204) in half, and the radii of curvature of the inner edge (105Aa) and the outer edge (105Ab) are different, and the magnitude relationship of the curvature of the inner edge (105Aa) and the outer edge (105Ab) is reversed between two adjacent electrode curved portions (105A).

[0415] [A3] In the at least one corner portion (201 to 204), the angle formed by the dividing line (L0) and a straight line connecting one end of the inner edge (105Aa) of each electrode curved portion (105A) to the center of curvature of the inner edge (105Aa) and the angle formed by the dividing line (L0) and a straight line connecting one end of the outer edge (105Ab) of each electrode curved portion (105A) to the center of curvature of the outer edge (105Ab) are set so that the width of one end of each electrode curved portion (105A) is a predetermined width, The semiconductor device described in [A2], wherein in the corner portions (201 to 204), the angle formed by the straight line connecting the other end of the inner edge (105Aa) of each of the electrode curved portions (105A) to the center of curvature of the inner edge (105Aa) and the dividing line (L0) and the angle formed by the straight line connecting the other end of the outer edge (105Ab) of each of the electrode curved portions (105A) to the center of curvature of the outer edge (105Ab) and the dividing line (L0) are set so that the width of the other end of each of the electrode curved portions (105A) becomes the predetermined width.

[0416] [A4] The plurality of FLR electrodes (105) have, at each of the corners (201 to 204), electrode curved portions (105A) whose inner edges (105Aa) and outer edges (105Ab) have arcuate shapes in plan view, and at each of the corners (201 to 204), the electrode curved portions (105A) have inner edges (105Aa) and outer edges (105Ab) whose centers of curvature and curvatures are different, and the magnitude relationship of the curvatures of the inner edges (105Aa) and outer edges (105Ab) between two adjacent electrode curved portions (105A) is reversed, so that, at each of the corners (201 to 204), the electrode curved portions (105A) have a wide region and a narrow region between their inner edges (105Aa) and outer edges (105Ab), The semiconductor device according to [A1], wherein a portion of the larger width region in each of the electrode curved portions (105A) is electrically connected to the corresponding FLR (42) via an FLR connection electrode (89) penetrating the insulating film (45, 74).

[0417] [A5] The semiconductor device according to [A4], wherein in each of the corners (201 to 204), the center of curvature of the inner edge (105Aa) and the center of curvature of the outer edge (105Ab) of each of the electrode curved portions (105A) are located at different positions on a dividing line (L0), which is a straight line that divides the apex angle of the corner portion (201 to 204) in half, and the radii of curvature of the inner edge (105Aa) and the outer edge (105Ab) are different, and the magnitude relationship of the curvature of the inner edge (105Aa) and the outer edge (105Ab) is reversed between two adjacent electrode curved portions (105A).

[0418] [A6] In each of the corner portions (201 to 204), the angle formed by the dividing line (L0) and a straight line connecting one end of the inner edge (105Aa) of each of the electrode curved portions (105A) to the center of curvature of the inner edge (105Aa) and the angle formed by the dividing line (L0) and a straight line connecting one end of the outer edge (105Ab) of each of the electrode curved portions (105A) to the center of curvature of the outer edge (105Ab) are set so that the width of one end of each of the electrode curved portions (105A) is a predetermined width, The semiconductor device described in [A5], wherein in each corner portion (201 to 204), the angle formed by the straight line connecting the other end of the inner edge (105Aa) of each electrode curved portion (105A) to the center of curvature of the inner edge (105Aa) and the dividing line (L0) and the angle formed by the straight line connecting the other end of the outer edge (105Ab) of each electrode curved portion (105A) to the center of curvature of the outer edge (105Ab) and the dividing line (L0) are set so that the width of the other end of each electrode curved portion (105A) becomes the predetermined width.

[0419] [A7] A semiconductor device according to any one of [A1] to [A6], wherein the FLR connection electrode (89) for electrically connecting each FLR electrode (105) to the corresponding FLR (42) is integrally formed with the FLR electrode (105).

[0420] [A8] The semiconductor device according to any one of [A1] to [A7], including a channel stop region (43) formed in the outer peripheral region (9) on a surface layer of the first main surface (3) so as to surround the plurality of FLRs (42) and covered by the insulating film (45, 74), and a channel stop electrode (106) formed on the insulating film (45, 74) in the outer peripheral region (9) so as to cover a portion of the channel stop region (43).

[0421] [A9] The semiconductor device according to any one of [A1] to [A8], wherein the element structure includes an IGBT structure.

[0422] [A10] The semiconductor device according to [A9], comprising: a first conductivity type drift region (12) formed inside the chip (2); a second conductivity type channel region (20) formed in the active region (6) in a surface layer portion of the first main surface (3); a first conductivity type emitter region (29) formed in a surface layer portion of the channel region (20) and having a higher first conductivity type impurity concentration than the drift region (12); and a trench gate structure (21) in the active region (6) passing through the emitter region (29) and the channel region (20) to reach the drift region (12).

[0423] [A11] The semiconductor device according to [A10], wherein the conductivity type of the FLR (42) is the second conductivity type.

[0424] Although the embodiments have been described in detail above, these are merely specific examples used to clarify the technical content, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited by the appended claims.

[0425] 1 Semiconductor device 2 Chip 3 First main surface 4 Second main surface 5A to 5D First to fourth side surfaces 6 Active region 6A First active region 6B Second active region 7 Non-active region 8 Boundary region (7) 9 Peripheral region (7) 10 Pad region (8) 11 Street region (8) 12 Drift region 13 Buffer layer 14 Collector region 15 Trench isolation structure 15A First trench isolation structure 15B Second trench isolation structure 16 Isolation trench 17 Isolation insulating film 18 Isolation buried electrode 20 Channel region 21 First trench structure 22 First trench 23 First insulating film 24 First buried electrode 25 Second trench structure 26 Second trench 27 Second insulating film 28 Second buried electrode 29 Emitter region 30 Contact hole (first contact hole) 31 REFERENCE SIGNS LIST Channel contact region 32 Floating region 40 Boundary well region 40A First boundary well region 40B Second boundary well region 41 Peripheral well region 42 FLR 42A FLR curved portion 42Aa Inner edge 42Ab Outer edge 42B FLR straight portion 43 Channel stop region 45 Main surface insulating film 46 Removed portion 47 Emitter electrode film 50 Gate resistor structure 51 Trench resistor structure 51A First trench resistor structure 51B Second trench resistor structure 54 Resistor trench 55 Resistor insulating film 56 Resistor buried electrode 57 Space region 60 Resistor film 60A First end of resistor film 60B Second end of resistor film 61 First covered portion of resistor film 62 Second covered portion of resistor film 63 Third covered portion of resistor film 64 Gate electrode film 65 Gate wiring film 66 First lower wiring portion 67 Second lower wiring portion 68 Third lower wiring portion 68a Lead-out portion 69 First lower line portion (66) 70A,70B Second lower line portion (66) 71 First slit 72 Second slit 73 Third slit 74 Interlayer insulating film 75 Main insulating surface 76 First recess portion 77 Second recess portion 78 Third recess portion 81 First resistor connecting electrode 82 Second resistor connecting electrode 83 Third resistor connecting electrode 84 Gate connecting electrode 84A First gate connecting electrode 84B Second gate connecting electrode 85 First emitter connecting electrode (first connecting electrode) 86 Second emitter connecting electrode 87 First well connecting electrode 87a Segment 88 Second well connecting electrode 89 FLR connecting electrode 90 Gate terminal electrode 91 First electrode portion 92 Second electrode portion 93 Gate wiring electrode 94 First upper wiring portion 95 Second upper wiring portion 96 Third upper wiring portion 97 First upper line portion (94) 97a Recessed portion 98A, 98B Second upper line portion (94) 101 First connection region 102 Second connection region 103 Emitter terminal electrode 103A First emitter terminal electrode 103B Second emitter terminal electrode 104 Emitter wiring electrode 105 FLR electrode 105A Electrode curved portion 105Aa Inner edge 105Ab Outer edge 105B Electrode straight portion 106 Channel stop electrode 107 Collector electrode 201 to 204 Corner portions 211, 212 Wide portions Q1, Q2 Center of curvature r1, r2 Radius of curvature X First direction Y Second direction

Claims

1. a chip having a first main surface that is rectangular in plan view and a second main surface on the opposite side thereof; an active region provided on the first main surface and having an element structure formed therein; a peripheral region outside the active region, the peripheral region being provided on the outer periphery of the first main surface and having four corners; a plurality of field limiting rings (hereinafter referred to as "FLRs") formed in the outer peripheral region on a surface layer portion of the first main surface so as to surround the active region; an insulating film formed on the first main surface and covering the plurality of FLRs; a plurality of FLR electrodes disposed opposite the plurality of FLRs via the insulating film, Each of the FLR electrodes has an electrode curved portion, the inner edge and the outer edge of which have a circular arc shape in a plan view, at at least one of the four corner portions; In the at least one corner portion, each of the electrode curved portions has a center of curvature and an inner edge and an outer edge whose curvatures are different from each other, and the magnitude relationship of the curvatures of the inner edge and the outer edge between two adjacent electrode curved portions is reversed from each other, Thus, at the corners, each of the electrode curved portions has a wide region and a narrow region between the inner edge and the outer edge, a part of the larger width region in each of the electrode curved portions is physically and electrically connected to the corresponding FLR via an FLR connection electrode that penetrates the insulating film;

2. 2. The semiconductor device according to claim 1, wherein, in the at least one corner portion, the center of curvature of the inner edge and the center of curvature of the outer edge of each of the electrode curved portions are located at different positions on a dividing line that is a straight line dividing the apex angle of the corner portion in half, and the radii of curvature of the inner edge and the outer edge are different, and the magnitude relationship of the curvature of the inner edge and the outer edge is reversed between two adjacent electrode curved portions.

3. at least one corner portion, an angle formed by a straight line connecting one end of an inner edge of each of the electrode curved portions to the center of curvature of the inner edge and the dividing line, and an angle formed by a straight line connecting one end of an outer edge of each of the electrode curved portions to the center of curvature of the outer edge and the dividing line are set so that a width of one end of each of the electrode curved portions becomes a predetermined width, 3. The semiconductor device according to claim 2, wherein, at the corner portion, an angle formed by a straight line connecting the other end of the inner edge of each of the electrode curved portions to the center of curvature of the inner edge and the dividing line and an angle formed by a straight line connecting the other end of the outer edge of each of the electrode curved portions to the center of curvature of the outer edge and the dividing line are set so that a width of the other end of each of the electrode curved portions becomes the predetermined width.

4. the plurality of FLR electrodes have, at each of the corner portions, electrode curved portions whose inner and outer edges have arc-shaped shapes in a plan view, At each corner, each of the electrode curved portions has a center of curvature and an inner edge and an outer edge whose curvatures are different, and the magnitude relationship of the curvatures of the inner edge and the outer edge between two adjacent electrode curved portions is reversed. Thus, at each corner, each electrode curved portion has a wide region and a narrow region between its inner edge and outer edge, 2. The semiconductor device according to claim 1, wherein a part of said large width region in each of said electrode curved portions is electrically connected to said corresponding FLR via said FLR connection electrode penetrating said insulating film.

5. 5. The semiconductor device according to claim 4, wherein, at each corner, the center of curvature of the inner edge and the center of curvature of the outer edge of each of the electrode curved portions are located at different positions on a dividing line that is a straight line dividing the apex angle of the corner portion in half, and the radii of curvature of the inner edge and the outer edge are different, and the magnitude relationship of the curvature of the inner edge and the outer edge is reversed between two adjacent electrode curved portions.

6. at each corner, an angle formed by a straight line connecting one end of an inner edge of each electrode curved portion to the center of curvature of the inner edge and the dividing line, and an angle formed by a straight line connecting one end of an outer edge of each electrode curved portion to the center of curvature of the outer edge and the dividing line are set so that a width of one end of each electrode curved portion becomes a predetermined width, 6. The semiconductor device according to claim 5, wherein, at each corner, an angle formed by a straight line connecting the other end of the inner edge of each of the electrode curved portions to the center of curvature of the inner edge and the dividing line and an angle formed by a straight line connecting the other end of the outer edge of each of the electrode curved portions to the center of curvature of the outer edge and the dividing line are set so that a width of the other end of each of the electrode curved portions becomes the predetermined width.

7. 7. The semiconductor device according to claim 1, wherein the FLR connection electrodes for electrically connecting the FLR electrodes to the corresponding FLRs are formed integrally with the FLR electrodes.

8. a channel stop region formed in a surface layer portion of the first main surface in the peripheral region so as to surround the plurality of FLRs and covered with the insulating film; a channel stop electrode formed on the insulating film in the peripheral region so as to cover a part of the channel stop region; 7. The semiconductor device according to claim 1, further comprising a channel stop connection electrode connecting said channel stop electrode and said channel stop region.

9. 7. The semiconductor device according to claim 1, wherein the element structure includes an IGBT structure.

10. a drift region of a first conductivity type formed inside the chip; a second conductivity type channel region formed in a surface layer portion of the first main surface in the active region; an emitter region of a first conductivity type formed in a surface layer portion of the channel region and having a first conductivity type impurity concentration higher than that of the drift region; 10. The semiconductor device according to claim 9, further comprising a trench gate structure in said active region, said trench gate structure passing through said emitter region and said channel region and reaching said drift region.

11. The semiconductor device according to claim 10 , wherein the conductivity type of the FLR is the second conductivity type.