Semiconductor device and method for producing same

Abstract

This semiconductor device is provided with: a chip that contains SiC and has a main surface; a gate electrode that is disposed on the main surface, contains polysilicon, and has an electrode surface; a silicide portion formed in a part of a surface portion of the electrode surface; and a polysilicon portion formed in a part other than the silicide portion of the surface portion of the electrode surface.

Description

Semiconductor device and manufacturing method thereof

[0001] This application claims priority to Patent Application No. 2023-056616 filed with the Japan Patent Office on March 30, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device and a manufacturing method thereof.

[0002] Patent Document 1 (US2013 / 0234159A1) discloses a semiconductor device having a gate electrode, which has a stacked structure including a semiconductor layer and a metal semiconductor compound layer (silicide).

[0003] US Patent Application Publication No. 2013 / 0234159

[0004] [Summary] The present disclosure provides a semiconductor device having a novel configuration and a method for manufacturing the same.

[0005] The present disclosure provides a semiconductor device including: a chip including SiC and having a main surface; a gate electrode including polysilicon and arranged on the main surface and having an electrode surface; a silicide portion partially formed on a surface portion of the electrode surface; and a polysilicon portion formed on a portion of the surface portion of the electrode surface other than the silicide portion.

[0006] The present disclosure provides a semiconductor device including a chip including SiC and having a main surface, a gate electrode arranged on the main surface, an interlayer film covering the gate electrode and having an insulating surface, an opening formed in the interlayer film spaced apart from the gate electrode and exposing the main surface, a buried electrode embedded in the opening, having an electrode surface exposed from the opening, and electrically connected to the chip, and a main electrode mechanically and electrically connected to the electrode surface of the buried electrode.

[0007] The present disclosure provides a method for manufacturing a semiconductor device, including the steps of: forming a base electrode containing polysilicon on a wafer containing SiC; forming a metal film partially covering an electrode surface of the base electrode; reacting the polysilicon with the metal film to partially form a silicide portion on a surface portion of the electrode surface; removing an unreacted portion of the metal film from the electrode surface; and removing the base electrode in a thickness direction from a polysilicon portion outside the silicide portion to form a gate electrode having both the silicide portion and the polysilicon portion on a surface portion of the electrode surface.

[0008] The present disclosure provides a method for manufacturing a semiconductor device, including the steps of: forming a gate electrode on a wafer; forming an interlayer film on the wafer to cover the gate electrode; forming an opening in the interlayer film to expose the wafer at a position spaced apart from the gate electrode; embedding an electrode in the opening to be electrically connected to the wafer, thereby forming a buried electrode having an electrode surface exposed from the opening; and forming a main electrode that directly covers the electrode surface of the buried electrode.

[0009] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a plan view showing a semiconductor device according to a specific embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing a layout example of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing a further main portion of the first main surface. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. FIG. 7 is an enlarged cross-sectional view showing the main portion of FIG. 6 together with a gate electrode according to a first example and a source pad electrode according to the first example. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is an enlarged cross-sectional view showing the main portion of FIG. 8 together with a gate wiring according to the first example. FIG. 10A is an enlarged cross-sectional view showing a gate electrode according to a second example. FIG. 10B is an enlarged cross-sectional view showing a gate electrode according to a third example. FIG. 10C is an enlarged cross-sectional view showing a gate electrode according to a fourth example. FIG. 11A is an enlarged cross-sectional view showing a gate wiring according to the second example. FIG. 11B is an enlarged cross-sectional view showing a gate wiring according to a third example. FIG. 11C is an enlarged cross-sectional view showing a gate wiring according to a fourth example. FIG. 12A is an enlarged cross-sectional view showing a source pad electrode according to a second example. FIG. 12B is an enlarged cross-sectional view showing a source pad electrode according to a third example. FIG. 12C is an enlarged cross-sectional view showing a source pad electrode according to a fourth example. FIG. 12D is an enlarged cross-sectional view showing a source pad electrode according to a fifth example. FIG. 13 is a schematic diagram showing a wafer. FIG. 14A is a cross-sectional view showing a method for manufacturing a semiconductor device. FIG. 14B is a cross-sectional view showing a step after FIG. 14A. FIG. 14C is a cross-sectional view showing a step after FIG. 14B. FIG. 14D is a cross-sectional view showing a step after FIG. 14C. FIG. 14E is a cross-sectional view showing a step after FIG. 14D. FIG. 14F is a cross-sectional view showing a step after FIG. 14E. FIG. 14G is a cross-sectional view showing a step after FIG. 14F. FIG. 14H is a cross-sectional view showing a step after FIG. 14G. FIG. 14I is a cross-sectional view showing a step after FIG. 14H. Fig. 14J is a cross-sectional view showing a step after Fig. 14I. Fig. 14K is a cross-sectional view showing a step after Fig. 14J. Fig. 14L is a cross-sectional view showing a step after Fig. 14K. Fig. 14M is a cross-sectional view showing a step after Fig. 14L. Fig. 14N is a cross-sectional view showing a step after Fig. 14M. Fig. 14O is a cross-sectional view showing a step after Fig. 14N. Fig. 14P is a cross-sectional view showing a step after Fig. 14O.Fig. 14Q is a cross-sectional view showing a step after Fig. 14P. Fig. 14R is a cross-sectional view showing a step after Fig. 14Q. Fig. 15 is a cross-sectional view showing a first modified example of the semiconductor device. Fig. 16 is a cross-sectional view showing a second modified example of the semiconductor device.

[0011] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0012] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0013] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0014] Fig. 1 is a plan view showing a semiconductor device 1 according to a specific embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of the first main surface 3. Fig. 5 is an enlarged plan view showing a further main portion of the first main surface 3.

[0015] Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 5. Fig. 7 is an enlarged cross-sectional view showing the main part of Fig. 6 together with the gate electrode 32 according to the first example and the source pad electrode 95 according to the first example. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 5. Fig. 9 is an enlarged cross-sectional view showing the main part of Fig. 8 together with the gate wiring 52 according to the first example.

[0016] 1 to 9, semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip."

[0017] In this embodiment, the chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0018] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0019] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0020] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0021] In the following description, one side of the first direction X refers to the third side surface 5C side, and the other side of the first direction X refers to the fourth side surface 5D side. Furthermore, one side of the second direction Y refers to the first side surface 5A side, and the other side of the second direction Y refers to the second side surface 5B side. In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0022] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off-axis direction by the off-axis angle. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off-axis angle.

[0023] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0024] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0025] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer portion) on the first main surface 3 side of the chip 2. The first semiconductor region 6 may also be referred to as a "drift region," a "drain drift region," a "drain region," or the like. A drain potential as a high potential (first potential) is applied to the first semiconductor region 6. The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).

[0026] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side within the chip 2. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 may also be referred to as a "drain region," etc. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 within the chip 2.

[0027] The second semiconductor region 7 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC substrate). That is, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer. The second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.

[0028] The semiconductor device 1 includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 and spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0029] The semiconductor device 1 includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a plan view. The peripheral region 9 extends in a strip shape along the active region 8 in a plan view, and is set in a polygonal ring shape (a square ring in this embodiment) surrounding the active region 8.

[0030] The semiconductor device 1 includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 in the active region 8. A source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential). The plurality of body regions 20 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of body regions 20 are arranged in a strip shape extending in the second direction Y.

[0031] The plurality of body regions 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of body regions 20 are preferably formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The plurality of body regions 20 are exposed from the first main surface 3.

[0032] The body regions 20 may each have a width of 1 μm to 10 μm. The width of the body regions 20 may be a value belonging to at least one of the following ranges: 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the body region 20 is preferably 2 μm to 5 μm.

[0033] Each of the body regions 20 may have a thickness (depth) of 0.1 μm to 2.5 μm. The thickness of the body region 20 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, and 2 μm to 2.5 μm. The thickness of the body region 20 is preferably 0.5 μm to 1.5 μm.

[0034] The semiconductor device 1 includes a p-type outer body region 21 formed in the peripheral region 9 in a surface layer portion of the first main surface 3. The outer body region 21 preferably has a p-type impurity concentration substantially equal to the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the outer body region 21 may be lower than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.

[0035] The outer body region 21 is formed at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip shape along the active region 8. The outer body region 21 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0036] In this embodiment, the outer body region 21 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. In other words, the outer body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4 ).

[0037] The outer body region 21 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 21 is connected to the plurality of body regions 20 in a portion extending in the first direction X. In this way, the outer body region 21 is electrically connected to the plurality of body regions 20.

[0038] The outer body region 21 preferably has a width greater than that of the body region 20. The width of the body region 20 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the outer body region 21 is the width in a direction perpendicular to the extending direction. Of course, the width of the outer body region 21 may be approximately equal to the width of the body region 20 or may be less than the thickness of the body region 20.

[0039] The ratio of the width of the outer body region 21 to the width of the body region 20 may be 1 or greater and 50 or less. The width ratio may have a value belonging to at least one of the ranges of 1 or greater and 10 or less, 10 or greater and 20 or less, 20 or greater and 30 or less, 30 or greater and 40 or less, and 40 or greater and 50 or less. The width ratio is preferably 10 or greater. The width ratio is preferably 20 or greater and 40 or less.

[0040] The outer body region 21 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The outer body region 21 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.

[0041] The outer body region 21 preferably has a thickness (depth) approximately equal to the thickness (depth) of the body region 20. Of course, the thickness of the outer body region 21 may be less than the thickness of the body region 20 or may be greater than the thickness of the body region 20.

[0042] The semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed in a surface portion of the first main surface 3. In this embodiment, the plurality of surface drift regions 22 are each made of a part of the first semiconductor region 6. Of course, the plurality of surface drift regions 22 may have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6, or may have an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6.

[0043] The plurality of surface drift regions 22 are respectively defined in regions between the plurality of body regions 20 adjacent to each other in the first direction X. Specifically, the plurality of surface drift regions 22 are respectively defined by the plurality of body regions 20 and the outer body region 21 in the surface portion of the first main surface 3.

[0044] The surface drift regions 22 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the surface drift regions 22 are formed in stripes extending in the second direction Y. Each surface drift region 22 forms an n-type (pnp-type) JFET structure together with the body regions 20 located on both sides.

[0045] The surface drift regions 22 may have a width of 0.1 μm to 5 μm. The width of the surface drift regions 22 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0046] The semiconductor device 1 includes a plurality of n-type source regions 23, 24 formed in the surface layer portions of the plurality of body regions 20. The plurality of source regions 23, 24 have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6. A source potential is applied to the plurality of source regions 23, 24.

[0047] The plurality of source regions 23, 24 include, in a surface layer portion of each body region 20, a first source region 23 located on one side in the first direction X and a second source region 24 located on the other side in the first direction X. In this embodiment, one first source region 23 is formed on one end side of the body region 20 in the first direction X, and one second source region 24 is formed on the other end side of the body region 20.

[0048] The first source region 23 is formed at a distance from one end of the body region 20 to the other end, and extends in a strip shape along the extension direction of the body region 20. The first source region 23 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the first source region 23 is not formed in the outer body region 21. The first source region 23 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the body region 20 in between.

[0049] The second source region 24 is formed at a distance from the first source region 23 to the other end side of the body region 20. The second source region 24 is formed at a distance from the other end side of the body region 20 to one end side, and extends in a strip shape along the extension direction of the body region 20. The second source region 24 is formed at a distance from the outer body region 21 in the second direction Y.

[0050] That is, the second source region 24 is not formed in the outer body region 21. The second source region 24 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the body region 20 interposed therebetween.

[0051] When a plurality of first source regions 23 are formed in one body region 20, the plurality of first source regions 23 may be formed at intervals in the extension direction of the body region 20. In this case, each first source region 23 may be formed in a strip shape extending in the second direction Y. Similarly, when a plurality of second source regions 24 are formed in one body region 20, the plurality of second source regions 24 may be formed at intervals in the extension direction of the body region 20. In this case, each second source region 24 may be formed in a strip shape extending in the second direction Y.

[0052] The semiconductor device 1 includes a plurality of p-type contact regions 25 formed in the surface layer portions of the plurality of body regions 20 in the active region 8. The contact regions 25 may also be referred to as "back gate regions." A source potential is applied to the plurality of contact regions 25. The contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0053] In this embodiment, one contact region 25 is interposed in a region between the first source region 23 and the second source region 24 in the surface layer portion of the corresponding body region 20. The contact region 25 extends in a strip shape along the extension direction of the body region 20 (the source regions 23, 24).

[0054] The contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the contact region 25 is not formed in the outer body region 21. The contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the body region 20 sandwiched therebetween.

[0055] When multiple contact regions 25 are formed in one body region 20, the multiple contact regions 25 may be formed at intervals in the extension direction of the body region 20. In this case, each contact region 25 may be formed in a strip shape extending in the second direction Y.

[0056] The semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 26, 27 are defined in the surface layer portions of the plurality of body regions 20, respectively, in regions between ends of the plurality of body regions 20 (a plurality of surface drift regions 22) and peripheral edges of the plurality of source regions 23, 24. In this embodiment, the plurality of channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 26, 27 are arranged in stripes extending in the second direction Y.

[0057] The plurality of channel regions 26, 27 includes a plurality of first channel regions 26 and a plurality of second channel regions 27. The plurality of first channel regions 26 are each defined as a region between one end of the plurality of body regions 20 (surface drift region 22) and the plurality of first source regions 23, and form a current path extending in the horizontal direction. The plurality of second channel regions 27 are each defined as a region between the other end of the plurality of body regions 20 (surface drift region 22) and the plurality of second source regions 24, and form a current path extending in the horizontal direction.

[0058] The semiconductor device 1 includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8. The plurality of gate structures 30 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y. The extending direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.

[0059] Each gate structure 30 is disposed on at least one channel region 26, 27. In this embodiment, each gate structure 30 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, covering a plurality of channel regions 26, 27.

[0060] Specifically, each gate structure 30 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0061] The configuration of one gate structure 30 will be described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The gate structure 30 does not have a sidewall structure (spacer) made of an insulator (such as silicon oxide and / or silicon nitride) on the side of the gate electrode 32. In other words, the gate structure 30 has a configuration that allows for a narrow pitch arrangement.

[0062] The insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 include a silicon oxide film made of an oxide of the chip 2.

[0063] The insulating film 31 covers the first main surface 3 in a film-like manner and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, and covers the multiple channel regions 26, 27.

[0064] Specifically, the insulating film 31 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0065] The insulating film 31 partially covers the first source region 23 at a distance from the contact region 25, and exposes a part of the first source region 23 and the contact region 25 from the first main surface 3. The insulating film 31 partially covers the second source region 24 at a distance from the contact region 25, and exposes a part of the second source region 24 and the contact region 25 from the first main surface 3.

[0066] The insulating film 31 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the insulating film 31 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. The thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.

[0067] The gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26, 27 across the insulating film 31. A gate potential as a control potential is applied to the gate electrode 32. The gate electrode 32 controls inversion and non-inversion of at least one of the channel regions 26, 27 in response to the gate potential.

[0068] The gate electrode 32 includes a conductive semiconductor polycrystalline. The gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted depending on the gate threshold voltage to be achieved. The gate electrode 32 may also be referred to as a "polysilicon gate," a "poly gate," or the like.

[0069] The gate electrode 32 is formed in a strip shape extending in the second direction Y. That is, the extending direction of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed spaced apart inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 so as to cross one surface drift region 22 and straddle two adjacent body regions 20, and faces the multiple channel regions 26, 27 across the insulating film 31.

[0070] Specifically, the gate electrode 32 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 across the insulating film 31.

[0071] The gate electrode 32 has an electrode surface 33, a first sidewall 34 on one side in the first direction X, and a second sidewall 35 on the other side in the first direction X. The electrode surface 33 extends along the insulating film 31 (first main surface 3). The electrode surface 33 may extend substantially parallel to the insulating film 31 (first main surface 3).

[0072] The first sidewall 34 is formed at a distance from one end of the insulating film 31 to the other end in the first direction X, and extends in the vertical direction Z. The second sidewall 35 is formed at a distance from the other end of the insulating film 31 to the one end in the first direction X, and extends in the vertical direction Z.

[0073] The first sidewall 34 and the second sidewall 35 may extend perpendicular to the insulating film 31. That is, the gate electrode 32 may be formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view. The first sidewall 34 and the second sidewall 35 may be obliquely inclined toward the electrode surface 33. That is, the gate electrode 32 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0074] The gate electrode 32 may have a width of 1 μm or more and 10 μm or less. The width of the gate electrode 32 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the gate electrode 32 may have a value belonging to at least one of the ranges of 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, and 7.5 μm or more and 10 μm or less. The width of the gate electrode 32 is preferably 1 μm or more and 5 μm or less.

[0075] The gate electrode 32 may have a thickness of 0.1 μm or more and 2 μm or less. The thickness of the gate electrode 32 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The thickness of the gate electrode 32 is preferably 0.2 μm or more and 1 μm or less.

[0076] 6 and 7 , the gate structure 30 includes a first silicide portion 40 partially formed on the surface portion of the electrode surface 33 of each gate electrode 32. That is, each gate electrode 32 has a first silicide portion 40 formed on the surface portion of the electrode surface 33. The first silicide portion 40 is a polycide portion formed by silicidizing the polysilicon of the gate electrode 32. The first silicide portion 40 may also be referred to as a "first metal semiconductor compound layer," a "first silicide layer (polycide layer)," a "first silicide region (polycide region)," or the like.

[0077] The first silicide portion 40 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first silicide portion 40 is preferably made of Ti silicide, Ni silicide, or Co silicide. The configuration (layout) of the first silicide portion 40 in one gate electrode 32 will be described below.

[0078] The first silicide portion 40 is formed at a distance inward from at least one of the first sidewall 34 and the second sidewall 35 of the gate electrode 32, and exposes at least one of the peripheral edge portions on the first sidewall 34 side and the second sidewall 35 side on the electrode surface 33. In this embodiment, the first silicide portion 40 is formed at a distance inward from both the first sidewall 34 and the second sidewall 35, and exposes both the peripheral edge portions on the first sidewall 34 side and the second sidewall 35 side on the electrode surface 33.

[0079] That is, the first silicide portion 40 is not exposed from either the first sidewall 34 or the second sidewall 35. The first silicide portion 40 is formed over the entire surface portion of the electrode surface 33 in a plan view, spaced apart inward from both the first sidewall 34 and the second sidewall 35. In this embodiment, the first silicide portion 40 has a surface that is flat with respect to the electrode surface 33.

[0080] The first silicide portion 40 is formed at a distance from the insulating film 31 toward the electrode surface 33 in the thickness direction, and faces the insulating film 31 with a part of the gate electrode 32 (polysilicon) sandwiched therebetween. The first silicide portion 40 is preferably formed at a distance from the middle portion of the gate electrode 32 toward the electrode surface 33 in the thickness direction. Of course, when the gate electrode 32 has a relatively small thickness, the first silicide portion 40 may have a bottom portion located on the insulating film 31 side of the middle portion of the gate electrode 32.

[0081] The first silicide portions 40 are formed in a strip shape extending along the gate electrode 32 in plan view. That is, the extending direction of the first silicide portions 40 coincides with the off-direction of the SiC single crystal. The first silicide portions 40 face one surface drift region 22 in the stacking direction. The first silicide portions 40 may be formed at an interval toward the surface drift region 22 from two adjacent body regions 20 in plan view, and may face only one surface drift region 22 in the stacking direction.

[0082] The first silicide portion 40 may extend across two adjacent body regions 20 across one surface drift region 22 in plan view. In this case, the first silicide portion 40 may be formed at an interval toward the surface drift region 22 from the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and may face the surface drift region 22, the first channel region 26, and the second channel region 27 in the stacking direction.

[0083] In this embodiment, the first silicide portion 40 is formed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 in the stacking direction.

[0084] In consideration of the response of the switching speed, it is preferable that the first silicide portion 40 faces either one or both (preferably both) of the first channel region 26 and the second channel region 27. It is preferable that the first silicide portion 40 faces the entire first channel region 26 in the stacking direction in a cross-sectional view. It is preferable that the first silicide portion 40 faces the entire second channel region 27 in the stacking direction in a cross-sectional view.

[0085] The first silicide portions 40 may be formed at intervals of 0.1 μm to 2.5 μm inward from the first sidewall 34 (second sidewall 35). The intervals between the first silicide portions 40 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm. The intervals between the first silicide portions 40 are preferably 0.2 μm to 1 μm. It is particularly preferable that the interval between the first silicide portions 40 be 0.5 μm or less.

[0086] The gate structure 30 includes a first polysilicon portion 41 formed on the electrode surface 33 of each gate electrode 32 in a portion other than the first silicide portion 40. That is, each gate electrode 32 has a first silicide portion 40 and a first polysilicon portion 41 formed on the surface portion of the electrode surface 33. The first polysilicon portion 41 may also be referred to as a "first polysilicon layer," a "first polysilicon region," or the like. The configuration (layout) of the first polysilicon portion 41 in one gate electrode 32 will be described below.

[0087] The first polysilicon portion 41 may have various layouts depending on the layout of the first silicide portion 40. When the first silicide portion 40 is formed spaced inward from at least one of the first sidewall 34 and the second sidewall 35 of the gate electrode 32, the first polysilicon portion 41 is formed in a region on at least one side of the first sidewall 34 and the second sidewall 35 on the electrode surface 33.

[0088] In this embodiment, the first silicide portion 40 is formed at a distance inward from both the first sidewall 34 and the second sidewall 35 of the gate electrode 32. Therefore, the first polysilicon portion 41 has one first polysilicon portion 41A defined in a region on the first sidewall 34 side with respect to the first silicide portion 40, and the other first polysilicon portion 41B defined in a region on the second sidewall 35 side with respect to the first silicide portion 40 (see FIGS. 5 and 7).

[0089] One of the first polysilicon portions 41A forms the first sidewall 34 of the gate electrode 32 in addition to the peripheral portion on one side of the electrode surface 33. One of the first polysilicon portions 41A extends in a strip shape in the second direction Y along the first silicide portion 40. One of the first polysilicon portions 41A forms the first sidewall 34 over the entire area of ​​the gate electrode 32 in a plan view.

[0090] One of the first polysilicon portions 41A faces the first source region 23 in the stacking direction. One of the first polysilicon portions 41A may face only the first source region 23 in the stacking direction. One of the first polysilicon portions 41A may face the first source region 23 and the first channel region 26 in the stacking direction. One of the first polysilicon portions 41A may face the surface drift region 22, the first source region 23, and the first channel region 26 in the stacking direction.

[0091] In consideration of the response of the switching speed, it is preferable that one of the first polysilicon portions 41A is formed at a distance from the first channel region 26 toward the first sidewall 34 in a plan view. In other words, it is preferable that one of the first polysilicon portions 41A does not face the first channel region 26 in the stacking direction in a cross-sectional view.

[0092] The other first polysilicon portion 41B forms the second sidewall 35 of the gate electrode 32 in addition to the peripheral portion on the other side of the electrode surface 33. The other first polysilicon portion 41B faces the one first polysilicon portion 41A in the first direction X across the first silicide portion 40, and extends in a strip shape in the second direction Y along the first silicide portion 40. In other words, the other first polysilicon portion 41B extends approximately parallel to the one first polysilicon portion 41A. The other first polysilicon portion 41B forms the second sidewall 35 over the entire area of ​​the gate electrode 32 in a plan view.

[0093] The other first polysilicon portion 41B faces the second source region 24 in the stacking direction. The other first polysilicon portion 41B may face only the second source region 24 in the stacking direction. The other first polysilicon portion 41B may face the second source region 24 and the second channel region 27 in the stacking direction. The other first polysilicon portion 41B may face the surface drift region 22, the second source region 24, and the second channel region 27 in the stacking direction.

[0094] In consideration of the response of the switching speed, it is preferable that the other first polysilicon portion 41B is formed at a distance from the second channel region 27 toward the second sidewall 35 in a plan view. In other words, it is preferable that the other first polysilicon portion 41B does not face the second channel region 27 in the stacking direction in a cross-sectional view.

[0095] In this embodiment, the first polysilicon portion 41 has a surface that is flat with respect to the electrode surface 33. That is, the first polysilicon portion 41, together with the first silicide portion 40, forms the flat electrode surface 33. The width of the first polysilicon portion 41 corresponds to the spacing between the first silicide portions 40 described above.

[0096] The gate electrode 32 (first silicide portion 40 and first polysilicon portion 41) may have the layout shown in Figures 10A to 10C, which are enlarged cross-sectional views showing gate electrodes 32 according to second, third, and fourth examples.

[0097] The gate electrode 32 does not necessarily have to have any one of the configurations of the first to fourth examples (FIG. 7, FIGS. 10A to 10C). The gate electrode 32 may simultaneously include features of at least two of the configurations of the first to fourth examples. The gate electrodes 32 according to the first to fourth examples are all forms that can be obtained by adjusting process conditions during the manufacturing process.

[0098] 10A (second example), the first silicide portion 40 may have a portion that protrudes upward (opposite the first main surface 3) with respect to the electrode surface 33. The first silicide portion 40 may protrude upward over the entire area of ​​the electrode surface 33. The first polysilicon portion 41 may have a portion that is located on the first main surface 3 (insulating film 31) side with respect to the upper end of the first silicide portion 40. The first polysilicon portion 41 may be located on the first main surface 3 (insulating film 31) side with respect to the upper end of the first silicide portion 40 over the entire area of ​​the electrode surface 33.

[0099] 10B (third example), the first silicide portion 40 may have a portion recessed closer to the first main surface 3 (insulating film 31) than the electrode surface 33. The first silicide portion 40 may be recessed closer to the first main surface 3 (insulating film 31) than the electrode surface 33 over the entire area of ​​the electrode surface 33. The first polysilicon portion 41 may have a portion protruding upward (toward the opposite side from the first main surface 3) than the first silicide portion 40. The first polysilicon portion 41 may protrude upward than the first silicide portion 40 over the entire area of ​​the electrode surface 33.

[0100] 10C (fourth example), the gate electrode 32 may include at least one (in this embodiment, both) of the first electrode recess 42 and the second electrode recess 43. Fig. 10C shows an example in which the first electrode recess 42 and the second electrode recess 43 are applied to the gate electrode 32 according to the first example (see Fig. 7). However, either or both of the first electrode recess 42 and the second electrode recess 43 may be applied to the gate electrode 32 according to the second example (see Fig. 10A) or the gate electrode 32 according to the third example (see Fig. 10B).

[0101] The first electrode recess 42 is recessed toward the first main surface 3 (insulating film 31) at a corner connecting the electrode surface 33 and the first sidewall 34. The first electrode recess 42 is formed in a strip shape extending along the gate electrode 32 (first sidewall 34). The bottom of the first electrode recess 42 is preferably formed with a gap from the middle of the gate electrode 32 toward the electrode surface 33. When the gate electrode 32 has a relatively small thickness, the bottom of the first electrode recess 42 may be located closer to the insulating film 31 than the middle of the gate electrode 32.

[0102] The second electrode recess 43 is recessed toward the first main surface 3 (insulating film 31) at a corner connecting the electrode surface 33 and the second sidewall 35. The second electrode recess 43 is formed in a strip shape extending along the gate electrode 32 (second sidewall 35). It is preferable that the bottom of the second electrode recess 43 be formed at a distance from the middle of the gate electrode 32 toward the electrode surface 33.

[0103] When the gate electrode 32 has a relatively small thickness, the bottom of the second electrode recess 43 may have a bottom located closer to the insulating film 31 than the middle part of the gate electrode 32. The depth of the second electrode recess 43 is preferably approximately equal to the depth of the first electrode recess 42.

[0104] The first silicide portion 40 is formed on the surface portion of the electrode surface 33 at a distance inward from the first electrode recess 42 and the second electrode recess 43, and exposes both the first electrode recess 42 and the second electrode recess 43. The bottom of the first silicide portion 40 may be located on the electrode surface 33 side with respect to the depth position of the bottom of the first electrode recess 42 (second electrode recess 43). The bottom of the first silicide portion 40 may be located on the first main surface 3 (insulating film 31) side with respect to the depth position of the bottom of the first electrode recess 42 (second electrode recess 43).

[0105] The distance between the first silicide portion 40 and the first electrode recess 42 (second electrode recess 43) is preferably greater than the width of the first electrode recess 42 (second electrode recess 43). Of course, the distance between the first silicide portion 40 and the first electrode recess 42 (second electrode recess 43) may be less than the width of the first electrode recess 42 (second electrode recess 43).

[0106] One of the first polysilicon portions 41A has a portion exposed from the first electrode recess 42. In this embodiment, the one of the first polysilicon portions 41A is formed over the entire area of ​​the first electrode recess 42. The one of the first polysilicon portions 41A has a portion located in the region between the first silicide portion 40 and the first electrode recess 42.

[0107] The other first polysilicon portion 41B has a portion exposed from the second electrode recess 43. In this embodiment, the other first polysilicon portion 41B is formed over the entire area of ​​the second electrode recess 43. The other first polysilicon portion 41B has a portion located in the region between the first silicide portion 40 and the second electrode recess 43.

[0108] The gate electrode 32 does not necessarily have to simultaneously include both the first electrode recess 42 and the second electrode recess 43. For example, the gate electrode 32 may have only the first electrode recess 42 and not the second electrode recess 43. For example, the gate electrode 32 may have only the second electrode recess 43 and not the first electrode recess 42.

[0109] 4, 5 and 8, semiconductor device 1 includes a p-type termination region 45 formed on first main surface 3 in peripheral region 9. Termination region 45 may also be referred to as a "well region," a "termination well region," or the like.

[0110] The termination region 45 may have a p-type impurity concentration different from the p-type impurity concentration of the body region 20. The p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the termination region 45 may be lower than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the termination region 45 may be approximately equal to the p-type impurity concentration of the body region 20.

[0111] The termination region 45 may have a p-type impurity concentration different from the p-type impurity concentration of the outer body region 21. The p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the outer body region 21. The p-type impurity concentration of the termination region 45 may be lower than the p-type impurity concentration of the outer body region 21. Of course, the p-type impurity concentration of the termination region 45 may be approximately equal to the p-type impurity concentration of the outer body region 21.

[0112] Termination region 45 is spaced inward from the periphery of first main surface 3 and is formed in a region between the periphery of first main surface 3 and outer body region 21. Termination region 45 extends in a band shape along outer body region 21 in a plan view. Termination region 45 has a portion extending in a band shape in first direction X and a portion extending in a band shape in second direction Y in a plan view, and defines active region 8 from multiple directions.

[0113] In this embodiment, the termination region 45 surrounds the outer body region 21 in a plan view and is defined as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The termination region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4 ).

[0114] The termination region 45 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the first semiconductor region 6. The termination region 45 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The termination region 45 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21. The thickness of the termination region 45 may be greater than or less than the thickness of the outer body region 21.

[0115] The termination region 45 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3. The inner edge of the termination region 45 is connected to the outer edge of the outer body region 21. This electrically connects the termination region 45 to the outer body region 21. That is, in this embodiment, the termination region 45 is electrically connected to the plurality of body regions 20 via the outer body region 21. In this embodiment, the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21 along the entire periphery.

[0116] The termination region 45 (inner edge portion) has an overlap region 46 that overlaps the outer edge portion of the outer body region 21. The overlap region 46 is a high-concentration region that includes the outer edge portion of the outer body region 21 and the inner edge portion of the termination region 45. In other words, the overlap region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 45, and has a p-type impurity concentration that is higher than both the p-type impurity concentrations of the outer body region 21 and the termination region 45.

[0117] The p-type impurity concentration of the overlap region 46 is higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the overlap region 46 may be lower than the p-type impurity concentration of the contact region 25. Of course, the p-type impurity concentration of the overlap region 46 may be higher than the p-type impurity concentration of the contact region 25.

[0118] The overlap region 46 extends in a band shape along the outer body region 21 in a plan view. The overlap region 46 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions. In this embodiment, the overlap region 46 is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0119] The overlap region 46 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The width of the overlap region 46 is preferably greater than the width of the body region 20. Of course, the width of the overlap region 46 may be less than the width of the body region 20.

[0120] The semiconductor device 1 may have a relatively high-concentration p-type well region (46) instead of the overlap region 46. In this case, the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45. The p-type impurity concentration of the well region (46) is higher than the p-type impurity concentration of the body region 20.

[0121] The p-type impurity concentration of the well region (46) may be approximately equal to the p-type impurity concentration of the contact region 25. Of course, the p-type impurity concentration of the well region (46) may be lower than the p-type impurity concentration of the contact region 25, or may be higher than the p-type impurity concentration of the contact region 25.

[0122] The well region (46) may be formed in either or both of the surface layer portion of the outer body region 21 and the surface layer portion of the termination region 45. Such a configuration is effective when the termination region 45 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the outer body region 21 and is formed as part of the outer body region 21 (the drawn portion).

[0123] The semiconductor device 1 includes at least one p-type field region 47 formed in the outer peripheral region 9 in a surface layer portion of the first main surface 3. The plurality of field regions 47 may be formed in an electrically floating state. The plurality of field regions 47 may be fixed to the source potential.

[0124] The number of field regions 47 is arbitrary. The number of field regions 47 may be 1 or more and 20 or less. The number of field regions 47 may have a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 47 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1 includes three field regions 47.

[0125] The plurality of field regions 47 are formed inwardly from the periphery of the first main surface 3 at intervals inward from the periphery of the first main surface 3 in a region between the periphery of the first main surface 3 and the active region 8. Specifically, the plurality of field regions 47 are formed in a region between the periphery of the first main surface 3 and the outer body region 21. More specifically, the plurality of field regions 47 are arranged in a region between the periphery of the first main surface 3 and the termination region 45 at intervals on the periphery side of the first main surface 3 from the termination region 45.

[0126] The field regions 47 are formed in a strip shape extending along the active region 8 (termination region 45) in a plan view. Each of the field regions 47 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0127] In this embodiment, the plurality of field regions 47 are formed in polygonal ring shapes (square ring shapes in this embodiment) surrounding the active region 8 (termination region 45) in plan view. The plurality of field regions 47 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0128] The plurality of field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a part of the first semiconductor region 6. The plurality of field regions 47 are preferably formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3.

[0129] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 47 may be approximately constant or may be non-uniform. The width of the multiple field regions 47 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 47 may gradually decrease toward the periphery of the first main surface 3.

[0130] The depth of the multiple field regions 47 may be approximately constant or may be non-uniform. The depth of the multiple field regions 47 may gradually increase toward the peripheral edge of the first main surface 3. The depth of the multiple field regions 47 may gradually decrease toward the peripheral edge of the first main surface 3. Of course, the multiple field regions 47 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion. The shallow portion may be formed on the inward side, and the deep portion may be formed on the peripheral edge side. The shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inward side.

[0131] The spacing between the multiple field regions 47 may be approximately constant or may be non-uniform. The spacing between the multiple field regions 47 may gradually increase toward the periphery of the first main surface 3. The spacing between the multiple field regions 47 may gradually decrease toward the periphery of the first main surface 3.

[0132] The p-type impurity concentrations of the plurality of field regions 47 may be approximately constant or may be non-uniform. The p-type impurity concentrations of the plurality of field regions 47 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the plurality of field regions 47 may gradually decrease toward the periphery of the first main surface 3.

[0133] The p-type impurity concentrations of the multiple field regions 47 may be approximately equal to the p-type impurity concentration of the body region 20 (outer body region 21). The p-type impurity concentrations of the multiple field regions 47 may be higher than the p-type impurity concentration of the body region 20 (outer body region 21), or may be lower than the p-type impurity concentration of the body region 20 (outer body region 21). The p-type impurity concentrations of the multiple field regions 47 may be approximately equal to the p-type impurity concentration of the termination region 45. The p-type impurity concentrations of the multiple field regions 47 may be higher than the p-type impurity concentration of the termination region 45, or may be lower than the p-type impurity concentration of the termination region 45.

[0134] 8, semiconductor device 1 includes a peripheral insulating film 51 that covers first main surface 3 in peripheral region 9. Peripheral insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0135] In this embodiment, the peripheral insulating film 51 has a single layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 51 includes a silicon oxide film made of an oxide of the chip 2. The peripheral insulating film 51 is preferably made of the same insulating material as the insulating material of the insulating film 31. It is preferable that the peripheral insulating film 51 has a thickness approximately equal to that of the insulating film 31.

[0136] The peripheral insulating film 51 covers the first main surface 3 in the peripheral region 9 in a film-like manner. The peripheral insulating film 51 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47. The peripheral insulating film 51 is connected to the plurality of insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is formed integrally with the plurality of insulating films 31, and together with the plurality of insulating films 31, forms a single insulating film.

[0137] 4, 5 and 8, semiconductor device 1 includes gate wiring 52 arranged on first main surface 3 in peripheral region 9. Semiconductor device 1 does not have a sidewall structure (spacer) made of an insulator (e.g., silicon oxide and / or silicon nitride) on the side of gate wiring 52.

[0138] The gate wiring 52 is selectively routed on the first main surface 3, and has a portion that extends in a different direction from the plurality of gate electrodes 32. The gate wiring 52 is connected to the plurality of gate electrodes 32, and applies gate signals to the plurality of gate electrodes 32. The gate wiring 52 may also be referred to as a "polysilicon gate wiring," a "poly gate wiring," a "second gate electrode," or the like.

[0139] The gate wiring 52 includes a conductive semiconductor polycrystalline. The gate wiring 52 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 52 preferably has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is adjusted according to the conductivity type of the gate electrode 32.

[0140] The gate wiring 52 is disposed on the peripheral insulating film 51 in the peripheral region 9. Specifically, the gate wiring 52 is disposed on a portion of the peripheral insulating film 51 that covers the outer body region 21, and faces the outer body region 21 across the peripheral insulating film 51. The gate wiring 52 is formed at a distance from the periphery of the first main surface 3 toward the active region 8, and extends in a strip shape along the active region 8. The gate wiring 52 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0141] In this embodiment, the gate wiring 52 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The gate wiring 52 may be either terminated or endless.

[0142] In this embodiment, the gate wiring 52 extends in a strip shape (annular shape in this embodiment) along the outer body region 21 in a plan view, and faces the outer body region 21 in the stacking direction over the entire periphery. The gate wiring 52 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0143] The gate wiring 52 is formed to be narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21. That is, in this embodiment, the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 52 is connected to the multiple gate electrodes 32 above the outer body region 21.

[0144] The thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32. The width of the gate wiring 52 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 52 is the width in a direction perpendicular to the extending direction. For example, the ratio of the width of the gate wiring 52 to the width of the gate electrode 32 may be 1 or more and 50 or less.

[0145] The width ratio may have a value belonging to at least one of the ranges of 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50. The width ratio may be 5 or greater. The width ratio may be 20 to 40. Of course, the width of the gate interconnect 52 may be equal to or less than the width of the gate electrode 32. The width of the gate interconnect 52 may be greater than the width of the outer body region 21.

[0146] The gate wiring 52 has a wiring surface 53, a first wiring sidewall 54 on the inner edge side, and a second wiring sidewall 55 on the outer edge side. The wiring surface 53 extends along the peripheral insulating film 51 (first main surface 3). The wiring surface 53 may extend substantially parallel to the peripheral insulating film 51 (first main surface 3). The first wiring sidewall 54 extends in the vertical direction Z on the peripheral insulating film 51, and the second wiring sidewall 55 extends in the vertical direction Z on the peripheral insulating film 51.

[0147] The first wiring sidewall 54 is connected to the plurality of gate electrodes 32 (the first sidewall 34 and the second sidewall 35) in a portion extending in the first direction X. That is, the gate wiring 52 has a plurality of portions connected in a T-shape to the plurality of gate electrodes 32. As a result, the gate wiring 52 is electrically connected to the plurality of gate electrodes 32.

[0148] The first wiring sidewall 54 and the second wiring sidewall 55 may extend perpendicular to the peripheral insulating film 51. That is, the gate wiring 52 may be formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view. The first wiring sidewall 54 and the second wiring sidewall 55 may be obliquely inclined toward the wiring surface 53. That is, the gate wiring 52 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0149] 8 and 9, the semiconductor device 1 includes a second silicide portion 60 partially formed on the surface portion of the wiring surface 53 of the gate wiring 52. That is, the gate wiring 52 has the second silicide portion 60 on the surface portion of the wiring surface 53. The second silicide portion 60 is a polycide portion formed by silicidizing the polysilicon of the gate wiring 52. The second silicide portion 60 may be referred to as a "second metal semiconductor compound layer," a "second silicide layer (polycide layer)," a "second silicide region (polycide region)," or the like.

[0150] The second silicide portion 60 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The second silicide portion 60 is preferably made of Ti silicide, Ni silicide, or Co silicide. The second silicide portion 60 is particularly preferably made of the same type of silicide as the first silicide portion 40.

[0151] The second silicide portion 60 is formed at a distance inward from at least one of the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52, and exposes at least one of the peripheral edge portions on the first wiring sidewall 54 side and the second wiring sidewall 55 side on the wiring surface 53. In this embodiment, the second silicide portion 60 is formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55, and exposes both the peripheral edge portions on the first wiring sidewall 54 side and the second wiring sidewall 55 side on the wiring surface 53.

[0152] That is, the second silicide portion 60 is not exposed from either the first wiring sidewall 54 or the second wiring sidewall 55. The second silicide portion 60 is formed at an interval inward from both the first wiring sidewall 54 and the second wiring sidewall 55 over the entire surface portion of the wiring surface 53 in a plan view.

[0153] The second silicide portion 60 is formed at a distance from the peripheral insulating film 51 toward the wiring surface 53 in the thickness direction, and faces the peripheral insulating film 51 across a part of the gate wiring 52 (polysilicon). The second silicide portion 60 is preferably formed at a distance from the middle of the gate wiring 52 toward the wiring surface 53 in the thickness direction. Of course, when the gate wiring 52 has a relatively small thickness, the second silicide portion 60 may have a bottom portion located closer to the peripheral insulating film 51 than the middle of the gate wiring 52.

[0154] The second silicide portion 60 extends in a strip shape along the gate wiring 52 on the wiring surface 53 and faces the outer body region 21 in the stacking direction. The second silicide portion 60 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view. In this embodiment, the second silicide portion 60 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0155] The second silicide portion 60 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in plan view.

[0156] The second silicide portion 60 is connected to the first silicide portions 40 at the connection portion between the gate electrodes 32 and the gate wirings 52. In other words, the second silicide portion 60 is formed integrally with the first silicide portions 40, and has a plurality of portions connected in a T-shape to the first silicide portions 40 (see FIG. 5).

[0157] In this embodiment, the second silicide portion 60 has a surface that is flat with respect to the wiring surface 53. The second silicide portion 60 preferably forms one flat surface together with the plurality of first silicide portions 40 at the connection portion between the plurality of gate electrodes 32 and the gate wiring 52. In other words, the second silicide portion 60 is preferably formed so as to be substantially flush with the plurality of first silicide portions 40.

[0158] The second silicide portions 60 may be formed at intervals of 0.1 μm to 5 μm inward from the first wiring sidewall 54 (second wiring sidewall 55). The intervals between the second silicide portions 60 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0159] The interval between the second silicide portions 60 is preferably 0.2 μm or more and 1 μm or less. The interval between the second silicide portions 60 is particularly preferably 0.5 μm or less. The interval between the second silicide portions 60 may be approximately equal to the interval between the first silicide portions 40. The interval between the second silicide portions 60 may be larger than the interval between the first silicide portions 40. The interval between the second silicide portions 60 may be smaller than the interval between the first silicide portions 40.

[0160] The semiconductor device 1 includes a second polysilicon portion 61 formed on the wiring surface 53 of each gate wiring 52 in a portion other than the second silicide portion 60. That is, each gate wiring 52 has the second silicide portion 60 and the second polysilicon portion 61 formed on the surface portion of the wiring surface 53. The second polysilicon portion 61 may be referred to as a "second polysilicon layer," a "second polysilicon region," or the like.

[0161] The second polysilicon portion 61 may have various layouts depending on the layout of the second silicide portion 60. When the second silicide portion 60 is formed at an interval inward from at least one of the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52, the second polysilicon portion 61 is formed in a region on at least one side of the first wiring sidewall 54 and the second wiring sidewall 55 on the wiring surface 53.

[0162] In this embodiment, the second silicide portion 60 is formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52. Therefore, the second polysilicon portion 61 has one second polysilicon portion 61A defined in a region on the first wiring sidewall 54 side with respect to the second silicide portion 60, and the other second polysilicon portion 61B defined in a region on the second wiring sidewall 55 side with respect to the second silicide portion 60 (see FIGS. 5 and 9).

[0163] One of the second polysilicon portions 61A forms the first wiring sidewall 54 of the gate wiring 52 in addition to the peripheral portion on one side of the wiring surface 53. One of the second polysilicon portions 61A extends in a strip shape along the second silicide portion 60. In this embodiment, one of the second polysilicon portions 61A forms the first wiring sidewall 54 over the entire area of ​​the gate wiring 52. One of the second polysilicon portions 61A faces the outer body region 21 in the stacking direction.

[0164] The other second polysilicon portion 61B forms the peripheral portion on the other side of the wiring surface 53, as well as the second wiring sidewall 55 of the gate wiring 52. The other second polysilicon portion 61B faces the second polysilicon portion 61B on one side with the second silicide portion 60 in between, and extends in a strip shape along the second silicide portion 60.

[0165] That is, the other second polysilicon portion 61B extends substantially parallel to the one second polysilicon portion 61A. In this embodiment, the other second polysilicon portion 61B forms the second wiring sidewall 55 over the entire area of ​​the gate wiring 52. The other second polysilicon portion 61A faces the outer body region 21 in the stacking direction.

[0166] The second polysilicon portion 61 (one of the second polysilicon portions 61A) is connected to the first polysilicon portions 41 at the connection portion between the gate electrodes 32 and the gate wiring 52. In other words, the second polysilicon portion 61 is formed integrally with the first polysilicon portions 41.

[0167] The second polysilicon portion 61 has a plurality of portions connected in an L-shape to the first polysilicon portions 41 at connection corners of the gate electrodes 32 and the gate wiring 52 (see FIG. 5). In this embodiment, the second polysilicon portion 61 has a surface that is flat with respect to the wiring surface 53. That is, the second polysilicon portion 61, together with the second silicide portion 60, forms the flat wiring surface 53.

[0168] The second polysilicon portion 61 preferably forms one flat surface together with the plurality of first polysilicon portions 41 at the connection portion between the plurality of gate electrodes 32 and the gate wiring 52. In other words, the second polysilicon portion 61 is preferably formed to be substantially flush with the plurality of first polysilicon portions 41. The width of the second silicide portion 60 corresponds to the spacing between the second silicide portions 60 described above.

[0169] The gate wiring 52 (second silicide portion 60 and second polysilicon portion 61) may have the layout shown in Figures 11A to 11C, which are enlarged cross-sectional views showing the gate wiring 52 according to second, third, and fourth examples.

[0170] The gate wiring 52 does not necessarily have to have any one of the configurations of the first to fourth examples (FIG. 9, FIGS. 11A to 11C). The gate wiring 52 may simultaneously include features of at least two of the configurations of the first to fourth examples. The gate wiring 52 according to the first to fourth examples is a form that can be obtained by adjusting process conditions during the manufacturing process.

[0171] 11A (second example), the second silicide portion 60 may have a portion that protrudes upward (toward the opposite side from the first main surface 3) with respect to the wiring surface 53. The second silicide portion 60 may protrude upward over the entire area of ​​the wiring surface 53.

[0172] The second polysilicon portion 61 may have a portion located closer to the first main surface 3 (periphery insulating film 51) than the upper end portion of the second silicide portion 60. The second polysilicon portion 61 may be located closer to the first main surface 3 (periphery insulating film 51) than the upper end portion of the second silicide portion 60 over the entire wiring surface 53.

[0173] For example, when the first silicide portion 40 has a protruding portion, the protruding portion of the second silicide portion 60 may be connected to the protruding portion of the first silicide portion 40. In this case, the second polysilicon portion 61 may be connected to the first polysilicon portion 41 in a region below the protruding portions of the first silicide portion 40 and the second silicide portion 60.

[0174] 11B (third example), the second silicide portion 60 may have a portion recessed closer to the first main surface 3 (peripheral insulating film 51) than the wiring surface 53. The second silicide portion 60 may be recessed closer to the first main surface 3 (peripheral insulating film 51) than the wiring surface 53 over the entire area of ​​the wiring surface 53.

[0175] The second polysilicon portion 61 may have a portion that protrudes upward (on the side opposite to the first main surface 3) from the second silicide portion 60. The second polysilicon portion 61 may protrude upward from the second silicide portion 60 over the entire area of ​​the wiring surface 53.

[0176] For example, when the first silicide portion 40 has a recess, the recess of the second silicide portion 60 may be connected to the recess of the first silicide portion 40. In this case, the second polysilicon portion 61 may be connected to the first polysilicon portion 41 in a region above the recess of the first silicide portion 40 and the recess of the second silicide portion 60.

[0177] 11C (fourth example), the gate wiring 52 may include at least one (in this embodiment, both) of the first wiring recess 62 and the second wiring recess 63. Fig. 11C shows an example in which the first wiring recess 62 and the second wiring recess 63 are applied to the gate wiring 52 according to the first example (see Fig. 9).

[0178] However, either or both of the first wiring recess 62 and the second wiring recess 63 may be applied to the gate wiring 52 according to the second example (see FIG. 11A) or the gate wiring 52 according to the third example (see FIG. 11B).

[0179] The first wiring recess 62 is recessed toward the first main surface 3 (peripheral insulating film 51) at a corner connecting the wiring surface 53 and the first wiring sidewall 54. The first wiring recess 62 is formed in a strip shape extending along the gate wiring 52 (first wiring sidewall 54).

[0180] The bottom of the first wiring recess 62 is preferably formed at a distance from the intermediate portion of the gate wiring 52 toward the wiring surface 53 in the thickness direction. When the gate wiring 52 has a relatively small thickness, the bottom of the first wiring recess 62 may be located closer to the peripheral insulating film 51 than the intermediate portion of the gate wiring 52.

[0181] The second wiring recess 63 is recessed toward the first main surface 3 (peripheral insulating film 51) at a corner connecting the wiring surface 53 and the second wiring sidewall 55. The second wiring recess 63 is formed in a strip shape extending along the gate wiring 52 (second wiring sidewall 55). It is preferable that the bottom of the second wiring recess 63 is formed at a distance from the middle of the gate wiring 52 toward the wiring surface 53 in the thickness direction.

[0182] When the gate wiring 52 has a relatively small thickness, the bottom of the second wiring recess 63 may be located closer to the peripheral insulating film 51 than the middle part of the gate wiring 52. The depth of the second wiring recess 63 is preferably approximately equal to the depth of the first wiring recess 62.

[0183] The second silicide portion 60 is formed on the surface portion of the wiring surface 53 at a distance inward from the first wiring recess 62 and the second wiring recess 63 , exposing both the first wiring recess 62 and the second wiring recess 63 .

[0184] The bottom of the second silicide portion 60 may be located closer to the wiring surface 53 than the depth position of the bottom of the first wiring recess 62 (second wiring recess 63). The bottom of the second silicide portion 60 may be located closer to the first main surface 3 (peripheral insulating film 51) than the depth position of the bottom of the first wiring recess 62 (second wiring recess 63).

[0185] The distance between the second silicide portion 60 and the first wiring recess 62 (second wiring recess 63) is preferably greater than the width of the first wiring recess 62 (second wiring recess 63). Of course, the distance between the second silicide portion 60 and the first wiring recess 62 (second wiring recess 63) may be less than the width of the first wiring recess 62 (second wiring recess 63).

[0186] One of the second polysilicon portions 61A has a portion exposed from the first wiring recess 62. In this embodiment, the one of the second polysilicon portions 61A is formed over the entire area of ​​the first wiring recess 62. The one of the second polysilicon portions 61A has a portion located in the region between the second silicide portion 60 and the first wiring recess 62.

[0187] In this embodiment, the other second polysilicon portion 61B has a portion exposed from the second wiring recess 63. In this embodiment, the other second polysilicon portion 61B is formed over the entire area of ​​the second wiring recess 63. The other second polysilicon portion 61B has a portion located in the region between the second silicide portion 60 and the second wiring recess 63.

[0188] For example, when the gate electrode 32 has the first electrode recess 42 and the second electrode recess 43 , the first wiring recess 62 of the gate wiring 52 may be connected to both the first electrode recess 42 and the second electrode recess 43 .

[0189] That is, the first wiring recess 62 may have a plurality of portions connected in an L-shape to the plurality of first electrode recesses 42 at the connection corner of the plurality of gate electrodes 32 and the gate wiring 52. The first wiring recess 62 may also have a plurality of portions connected in an L-shape to the plurality of second electrode recesses 43 at the connection corner.

[0190] The gate wiring 52 does not necessarily have to include both the first wiring recess 62 and the second wiring recess 63. For example, the gate wiring 52 may have only the first wiring recess 62 and not the second wiring recess 63. For example, the gate wiring 52 may have only the second wiring recess 63 and not the first wiring recess 62.

[0191] At least one of the gate wirings 52 according to the first to fourth examples (see FIG. 9 and FIGS. 11A to 11C) can be combined with at least one of the gate electrodes 32 according to the first to fourth examples (see FIG. 7 and FIGS. 10A to 10C). From the viewpoint of uniformity of the layout of the gate electrodes 32 and the layout of the gate wirings 52, it is preferable that the gate wiring 52 according to the first example (see FIG. 9) be combined with the gate electrode 32 according to the first example (see FIG. 7).

[0192] Similarly, the gate wiring 52 according to the second example (see FIG. 10A) is preferably combined with the gate electrode 32 according to the second example (see FIG. 11A). Similarly, the gate wiring 52 according to the third example (see FIG. 10B) is preferably combined with the gate electrode 32 according to the third example (see FIG. 11B). Similarly, the gate wiring 52 according to the fourth example (see FIG. 10C) is preferably combined with the gate electrode 32 according to the fourth example (see FIG. 11C).

[0193] The semiconductor device 1 includes an insulating interlayer film 70 that covers the first main surface 3. The interlayer film 70 may also be referred to as an "interlayer insulating film," "intermediate insulating film," or the like. The interlayer film 70 has an insulating surface 71 that extends along the first main surface 3. The interlayer film 70 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.

[0194] The interlayer film 70 covers the multiple gate structures 30 in the active region 8. The interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32 for each gate structure 30. That is, the interlayer film 70 has portions that directly cover the electrode surface 33, the first sidewall 34, and the second sidewall 35 of the gate electrode 32.

[0195] Interlayer film 70 collectively covers outer body region 21, termination region 45, and multiple field regions 47 in peripheral region 9, sandwiching peripheral insulating film 51 therebetween. Interlayer film 70 directly covers both peripheral insulating film 51 and gate wiring 52.

[0196] That is, the interlayer film 70 has portions that directly cover the wiring surface 53, the first wiring sidewall 54, and the second wiring sidewall 55 of the gate wiring 52. In this embodiment, the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 70 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral portion of the first main surface 3 (first semiconductor region 6).

[0197] In this embodiment, the interlayer film 70 has a layered structure including a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) stacked in this order from the first main surface 3 side. That is, the interlayer film 70 has an insulating surface 71 formed by the second oxide film 73. The first oxide film 72 has a single-layer structure made of a silicon oxide film with no added impurities. The first oxide film 72 may also be referred to as an NSG film (nondoped silicate glass film).

[0198] The first oxide film 72 collectively covers the active region 8 and the peripheral region 9. The first oxide film 72 collectively covers the plurality of gate structures 30 in the active region 8. The first oxide film 72 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.

[0199] The first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76. The first covering portion 74 extends horizontally in a film shape along the insulating film 31 (first main surface 3), and has a portion that contacts the first sidewall 34 (second sidewall 35) of the gate electrode 32. In this embodiment, the first covering portion 74 (first oxide film 72) has a thickness that is less than the thickness of the gate electrode 32, and covers the insulating film 31 at a distance from the height position of the electrode surface 33 of the gate electrode 32 toward the insulating film 31.

[0200] The second covering portion 75 is extended from the first covering portion 74 toward the electrode surface 33 in the stacking direction, and directly covers the first side wall 34 (second side wall 35) in a film-like manner. The second covering portion 75 (interlayer film 70) directly covers the first polysilicon portion 41 over the entire area of ​​the first side wall 34 (second side wall 35).

[0201] The third covering portion 76 is drawn out from the second covering portion 75 onto the electrode surface 33 and extends horizontally in a film shape along the electrode surface 33. The third covering portion 76 directly covers the entire electrode surface 33 between the first side wall 34 and the second side wall 35.

[0202] The third covering portion 76 (interlayer film 70) has a portion that directly covers the first silicide portion 40 on the electrode surface 33, and a portion that directly covers the first polysilicon portion 41. The third covering portion 76 preferably forms an arc corner portion that is curved in an arc shape together with the second covering portion 75 in the portion that covers the corner portion of the gate electrode 32. The arc corner portion may have a center of curvature on the gate electrode 32 side.

[0203] In the peripheral region 9, the first oxide film 72 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47 with the peripheral insulating film 51 sandwiched therebetween. The first oxide film 72 covers the gate wiring 52 in the peripheral region 9.

[0204] The first oxide film 72 has a first wire coating portion 77, a second wire coating portion 78, and a third wire coating portion 79. The first wire coating portion 77 extends in a film-like manner in the horizontal direction along the peripheral insulating film 51 (first main surface 3), and has a portion that contacts the first wire sidewall 54 (second wire sidewall 55) of the gate wiring 52. In this embodiment, the first wire coating portion 77 (first oxide film 72) has a thickness that is less than the thickness of the gate wiring 52, and covers the peripheral insulating film 51 at a distance from the height position of the wiring surface 53 of the gate wiring 52 toward the peripheral insulating film 51.

[0205] The second wiring coating portion 78 is drawn out from the first wiring coating portion 77 toward the wiring surface 53 in the stacking direction, and directly coats the first sidewall 34 (second sidewall 35) in a film-like manner. The second wiring coating portion 78 (interlayer film 70) directly coats the second polysilicon portion 61 over the entire area of ​​the first wiring sidewall 54 (second wiring sidewall 55).

[0206] The third wiring coating portion 79 is drawn out from the second wiring coating portion 78 onto the wiring surface 53 and extends horizontally in a film-like manner along the wiring surface 53. The third wiring coating portion 79 directly coats the entire wiring surface 53 between the first wiring sidewall 54 and the second wiring sidewall 55.

[0207] The third wire-coating portion 79 (interlayer film 70) has a portion that directly covers the second silicide portion 60 on the wiring surface 53, and a portion that directly covers the second polysilicon portion 61. The third wire-coating portion 79 preferably forms an arc-shaped corner portion together with the second wire-coating portion 78 in a portion that covers the corner portion of the gate wire 52. The arc-shaped corner portion may have a center of curvature on the gate wire 52 side.

[0208] The second oxide film 73 may have a single-layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass Film). The silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass Film).

[0209] The second oxide film 73 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 72. The second oxide film 73 may have a layered structure including a PSG film stacked on the first oxide film 72 and a BPSG film stacked on the PSG film. The second oxide film 73 may have a layered structure including a BPSG film stacked on the first oxide film 72 and a PSG film stacked on the BPSG film. In this embodiment, the second oxide film 73 has a single layer structure made of a PSG film, for example.

[0210] The second oxide film 73 covers the first oxide film 72 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 72 sandwiched therebetween. The second oxide film 73 collectively covers the plurality of gate structures 30 in the active region 8 with the first oxide film 72 sandwiched therebetween. Specifically, the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 72 sandwiched therebetween.

[0211] The second oxide film 73 includes a first upper covering portion 80 and a second upper covering portion 81. The first upper covering portion 80 covers the first covering portion 74 and the second covering portion 75 of the first oxide film 72. The first upper covering portion 80 covers the insulating film 31 in a portion located above the first covering portion 74, with the first covering portion 74 sandwiched between them.

[0212] The first upper covering portion 80 extends in the form of a film in the stacking direction from above the first covering portion 74 along the second covering portion 75, and covers the first sidewall 34 (second sidewall 35) of the gate structure 30 with the second covering portion 75 in between. In other words, the first upper covering portion 80 has a portion that covers the first polysilicon portion 41 with the second covering portion 75 in between.

[0213] The second upper covering portion 81 covers the third covering portion 76 of the first oxide film 72. The second upper covering portion 81 extends horizontally in the form of a film along the third covering portion 76 from the first upper covering portion 80, and covers the electrode surface 33 of the gate structure 30 with the third covering portion 76 in between. The second upper covering portion 81 covers the entire electrode surface 33 with the third covering portion 76 in between the first sidewall 34 and the second sidewall 35.

[0214] The second upper covering portion 81 has a portion that covers the first silicide portion 40 with the first oxide film 72 (third covering portion 76) sandwiched therebetween, and a portion that covers the first polysilicon portion 41 with the first oxide film 72 (third covering portion 76) sandwiched therebetween. The second upper covering portion 81 preferably forms an arc corner portion that is curved in an arc shape together with the first upper covering portion 80 in the portion that covers the corner portion of the gate wiring 52. The arc corner portion may have a center of curvature on the gate wiring 52 side.

[0215] Fluctuations in the electrical characteristics of the gate electrode 32 (first silicide portion 40 and first polysilicon portion 41) due to impurity diffusion in the second oxide film 73 are suppressed by the undoped first oxide film 72. Fluctuations in the insulating characteristics of the second oxide film 73 due to impurity diffusion in the gate electrode 32 are suppressed by the undoped first oxide film 72.

[0216] In the peripheral region 9, the second oxide film 73 collectively covers the outer body region 21, the termination region 45, and the plurality of field regions 47, sandwiching the peripheral insulating film 51 and the first oxide film 72 therebetween. In the peripheral region 9, the second oxide film 73 covers the gate wiring 52, sandwiching the first oxide film 72 therebetween.

[0217] The second oxide film 73 includes a first upper wire-coating portion 82 and a second upper wire-coating portion 83. The first upper wire-coating portion 82 coats the first wire-coating portion 77 and the second wire-coating portion 78 of the first oxide film 72. The first upper wire-coating portion 82 coats the peripheral insulating film 51 in a portion located above the first wire-coating portion 77, with the first wire-coating portion 77 sandwiched therebetween.

[0218] The first upper wire coating portion 82 extends in a film-like shape in the stacking direction from above the first wire coating portion 77 along the second wire coating portion 78, and coats the first wire sidewall 54 (second wire sidewall 55) with the second wire coating portion 78 in between. In other words, the first upper wire coating portion 82 has a portion that coats the second polysilicon portion 61 with the second wire coating portion 78 in between.

[0219] The second upper wire coating portion 83 coats the third wire coating portion 79 of the first oxide film 72. The second upper wire coating portion 83 extends in a film-like manner in the horizontal direction from the first upper wire coating portion 82 along the third wire coating portion 79, and coats the wiring surface 53 with the third wire coating portion 79 in between. The second upper wire coating portion 83 coats the entire wiring surface 53 with the third wire coating portion 79 in between the first wire sidewall 54 and the second wire sidewall 55.

[0220] The second upper wire-coating portion 83 has a portion that covers the second silicide portion 60 with the first oxide film 72 (third wire-coating portion 79) sandwiched therebetween, and a portion that covers the second polysilicon portion 61 with the first oxide film 72 (third wire-coating portion 79) sandwiched therebetween. The second upper wire-coating portion 83 preferably forms an arc-shaped corner portion that is curved in an arc shape together with the first upper wire-coating portion 82 in a portion that covers the corner portion of the gate wire 52. The arc-shaped corner portion may have a center of curvature on the gate wire 52 side.

[0221] Fluctuations in the electrical characteristics of the gate wiring 52 (second silicide portion 60 and second polysilicon portion 61) due to impurity diffusion in the second oxide film 73 are suppressed by the undoped first oxide film 72. Fluctuations in the insulating characteristics of the second oxide film 73 due to impurity diffusion in the gate wiring 52 are suppressed by the undoped first oxide film 72.

[0222] The semiconductor device 1 includes a plurality of source openings 90 formed in the interlayer film 70 in the active region 8. The plurality of source openings 90 are formed in regions on the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2). Specifically, the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32, respectively, and penetrate the insulating film 31 and the interlayer film 70.

[0223] The plurality of source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73. The plurality of source openings 90 each have an opening end defined by a circular arc corner portion of the interlayer film 70. The plurality of source openings 90 expose the corresponding plurality of source regions 23, 24 and contact regions 25, respectively.

[0224] In this embodiment, the source openings 90 are formed at intervals in the first direction X and in stripes extending in the second direction Y. That is, the source openings 90 are formed in stripes extending in the second direction Y. The source openings 90 are formed at intervals from the gate wiring 52 in the second direction Y. That is, the source openings 90 are formed in a region surrounded by the gate electrodes 32 and the gate wiring 52.

[0225] A plurality of source openings 90 may be formed in a region between two gate structures 30 adjacent to each other in the first direction X. In this case, the plurality of source openings 90 may be formed in a line at intervals in the second direction Y. Furthermore, in this case, each source opening 90 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.

[0226] The source opening 90 may have a width W of 0.1 μm or more and 3 μm or less. The width W of the source opening 90 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The width W of the source opening 90 is preferably 0.2 μm or more and 1 μm or less.

[0227] The source opening 90 may have a depth D of 0.1 μm or more and 2 μm or less. The depth D of the source opening 90 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The depth D of the source opening 90 is preferably 0.5 μm or more and 1 μm or less.

[0228] The source opening 90 preferably has an aspect ratio D / W of 0.5 or more and 3 or less. The aspect ratio D / W is defined as the ratio of the depth D of the source opening 90 to the width W of the source opening 90.

[0229] The aspect ratio D / W may have a value belonging to at least one of the ranges of 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio D / W is preferably greater than 1. That is, the source opening 90 preferably has a depth D greater than its width W. With this configuration, the multiple gate structures 30 are arranged at a narrow pitch.

[0230] The semiconductor device 1 includes a plurality of source recesses 91 formed in the first main surface 3 in portions exposed from the plurality of source openings 90. The semiconductor device 1 does not necessarily have to have the source recesses 91. Therefore, a configuration not including the source recesses 91 may be employed.

[0231] The plurality of source recesses 91 each have a planar shape that matches the planar shape of the corresponding source opening 90, and are recessed from the first main surface 3 toward the second main surface 4. The plurality of source recesses 91 are formed at intervals from the bottoms of the corresponding body regions 20 toward the first main surface 3, and expose the corresponding plurality of source regions 23, 24 and contact regions 25. Specifically, the plurality of source recesses 91 are formed at intervals from the bottoms of the corresponding plurality of source regions 23, 24 (contact regions 25) toward the first main surface 3.

[0232] The semiconductor device 1 includes at least one outer opening 92 (a plurality of outer openings in this embodiment) formed in the interlayer film 70 in the peripheral region 9. The plurality of outer openings 92 are formed in a portion of the interlayer film 70 that covers the termination region 45. The plurality of outer openings 92 penetrate the interlayer film 70 to expose the termination region 45. In this embodiment, the plurality of outer openings 92 are formed in a portion of the interlayer film 70 that covers the overlap region 46 of the termination region 45 to expose the overlap region 46.

[0233] The outer openings 92 may expose the outer body region 21 instead of or in addition to the termination region 45 (overlap region 46). The outer openings 92 penetrate both the first oxide film 72 and the second oxide film 73 and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73. The outer openings 92 each have an opening end defined by a circular arc corner portion of the interlayer film 70.

[0234] The outer openings 92 are spaced apart along the termination region 45 (overlap region 46) (see FIGS. 4 and 5). The outer openings 92 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The outer openings 92 may be formed in a strip shape extending along the termination region 45 (overlap region 46) in a plan view. The outer openings 92 may have an aspect ratio D / W (= 0.5 to 3, preferably greater than 1), similar to the source openings 90.

[0235] The semiconductor device 1 may have a single outer opening 92. The single outer opening 92 may be formed in a strip shape extending along the termination region 45 (overlap region 46). The single outer opening 92 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0236] The single outer opening 92 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single outer opening 92 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the termination region 45 (overlap region 46) in a plan view (see FIG. 4 ).

[0237] The semiconductor device 1 includes a plurality of outer recesses 93 formed in the first main surface 3 in the portions exposed from the plurality of outer openings 92. The semiconductor device 1 does not necessarily have to have the outer recesses 93. Therefore, a configuration not having the outer recesses 93 may be employed.

[0238] The outer recesses 93 each have a planar shape that matches the planar shape of the corresponding outer opening 92, and are recessed from the first main surface 3 toward the second main surface 4. The outer recesses 93 are formed at intervals from the bottom of the termination region 45 (overlap region 46) toward the first main surface 3, and each exposes the termination region 45 (overlap region 46).

[0239] The outer recess 93 may have a depth approximately equal to the depth of the source recess 91. When a single outer opening 92 is formed, a single outer recess 93 that matches the planar shape of the single outer opening 92 is formed.

[0240] The semiconductor device 1 includes at least one gate opening 94 (in this embodiment, multiple gate openings 94) formed in the interlayer film 70 in the peripheral region 9. The multiple gate openings 94 are formed in portions of the interlayer film 70 that cover the gate wiring 52. The multiple gate openings 94 penetrate the interlayer film 70 and expose the wiring surface 53 of the gate wiring 52.

[0241] Specifically, the plurality of gate openings 94 expose the second silicide portion 60 of the gate wiring 52. More specifically, the plurality of gate openings 94 expose the second silicide portion 60 at intervals inward from the second polysilicon portion 61. The plurality of gate openings 94 expose only the second silicide portion 60, and do not expose the second polysilicon portion 61. Of course, one or more gate openings 94 exposing the second polysilicon portion 61 may be formed.

[0242] The plurality of gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73. The plurality of gate openings 94 each have an opening end defined by a circular arc corner portion of the interlayer film 70.

[0243] The multiple gate openings 94 are formed at intervals along the gate wiring 52 (second silicide portion 60) (see FIGS. 4 and 5). The multiple gate openings 94 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The multiple gate openings 94 may be formed in a strip shape extending along the gate wiring 52 in a plan view. Like the source openings 90, the gate openings 94 may have an aspect ratio D / W (=0.5 to 3, preferably greater than 1).

[0244] The semiconductor device 1 may have a single gate opening 94. The single gate opening 94 may be formed in a strip shape extending along the gate wiring 52. The single gate opening 94 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0245] The single gate opening 94 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single gate opening 94 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the gate wiring 52 (second silicide portion 60) in plan view (see FIG. 4 ).

[0246] 1 and other figures, the semiconductor device 1 includes a source pad electrode 95 disposed on the interlayer film 70. The source pad electrode 95 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 95 may also be referred to as a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0247] The source pad electrode 95 is disposed on a portion of the interlayer film 70 that covers the active region 8. The source pad electrode 95 covers the plurality of gate electrodes 32 with the interlayer film 70 in between, and is electrically separated from the plurality of gate electrodes 32 by the interlayer film 70. The source pad electrode 95 is electrically connected to the plurality of body regions 20, the outer body region 21, the plurality of source regions 23 and 24, the contact region 25, etc. via the plurality of source openings 90.

[0248] In this embodiment, the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98. The first pad portion 96 has a relatively large planar area and forms the main body of the source pad electrode 95. In this embodiment, the first pad portion 96 is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the active region 8. The first pad portion 96 covers the multiple gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the multiple body regions 20 and the like via the multiple source openings 90.

[0249] The second pad portion 97 has a planar area smaller than that of the first pad portion 96, and is drawn out in a strip shape (rectangular shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The second pad portion 97 covers the plurality of gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 90.

[0250] The third pad portion 98 has a plane area smaller than that of the first pad portion 96, and is drawn out in a strip shape (rectangular shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 97 in the second direction Y. The third pad portion 98 covers the plurality of gate electrodes 32 with the interlayer film 70 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 90.

[0251] The planar area of ​​the third pad portion 98 may be approximately equal to the planar area of ​​the second pad portion 97. Of course, the planar area of ​​the third pad portion 98 may be larger than the planar area of ​​the second pad portion 97, or may be smaller than the planar area of ​​the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 may be used as a terminal portion for monitoring a current.

[0252] The source pad electrode 95 does not necessarily have to have both the second pad portion 97 and the third pad portion 98. The source pad electrode 95 may have only one of the second pad portion 97 and the third pad portion 98. Of course, the source pad electrode 95 may be made up of only the first pad portion 96, and may not have the second pad portion 97 or the third pad portion 98.

[0253] 6 and 7 , the source pad electrode 95 includes a first underlying electrode film 100, a plurality of first buried electrodes 101, and a first main electrode film 102. The first underlying electrode film 100 may be referred to as a "source underlying electrode film," the first buried electrodes 101 may be referred to as "source buried electrodes," and the first main electrode film 102 may be referred to as a "source main electrode film."

[0254] The first underlying electrode film 100 forms a lower layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98), and covers the interlayer film 70 in the active region 8. The first underlying electrode film 100 collectively covers the region of the interlayer film 70 where the multiple source openings 90 are formed. In other words, the first underlying electrode film 100 extends from above the insulating surface 71 into the multiple source openings 90.

[0255] The first base electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the plurality of source openings 90 in a film-like manner. The first base electrode film 100 defines recesses in each of the plurality of source openings 90. The first base electrode film 100 may have a portion that partially covers the gate wiring 52 with the interlayer film 70 sandwiched therebetween. The first base electrode film 100 may be formed spaced inward from the gate wiring 52 in a plan view.

[0256] In this embodiment, the first underlying electrode film 100 has a layered structure including a first electrode film 103 layered on the interlayer film 70 and a second electrode film 104 layered on the first electrode film 103. In this embodiment, the first electrode film 103 includes a Ti film, and the second electrode film 104 includes a TiN film. The first underlying electrode film 100 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film).

[0257] The thickness of the first electrode film 103 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 103 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0258] The thickness of the second electrode film 104 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 104 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the second electrode film 104 is preferably greater than the thickness of the first electrode film 103.

[0259] The first electrode film 103 collectively covers the region of the interlayer film 70 where the multiple source openings 90 are formed, and extends into the multiple source openings 90 from above the insulating surface 71. The first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner. The first electrode film 103 directly covers the insulating surface 71.

[0260] That is, the first electrode film 103 directly covers the second oxide film 73 on the insulating surface 71. The first oxide film 72 faces the plurality of gate electrodes 32 with the interlayer film 70 interposed therebetween in the portion covering the insulating surface 71. That is, the first electrode film 103 faces the first silicide portion 40 and the first polysilicon portion 41 of each gate electrode 32 with the interlayer film 70 interposed therebetween.

[0261] The first electrode film 103 covers the arc corner portion of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner portion, and extends into the source opening 90. In other words, the first electrode film 103 has a portion that extends in an arc shape at the arc corner portion. This improves the film formability of the first electrode film 103 on the interlayer film 70 (wall surface of the source opening 90).

[0262] The first electrode film 103 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73. The first electrode film 103 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 with the interlayer film 70 interposed therebetween. In other words, the first electrode film 103 faces the first polysilicon portion 41 of the gate electrode 32 with the first oxide film 72 and the second oxide film 73 interposed therebetween.

[0263] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the plurality of source regions 23, 24 and the contact region 25.

[0264] The first electrode film 103 may cover the source recess 91 in a film-like manner at a distance from the height position of the first main surface 3 to the bottom side of the source recess 91. The first electrode film 103 may have a portion located on the bottom side of the source recess 91 relative to the height position of the first main surface 3, and a portion located on the insulating film 31 side relative to the height position of the first main surface 3.

[0265] The second electrode film 104 collectively covers, in a film form, the region of the interlayer film 70 on the first electrode film 103 where the plurality of source openings 90 are formed. The second electrode film 104 has a portion that covers, in a film form, the insulating surface 71 of the interlayer film 70 with the first electrode film 103 in between, and a portion that covers, in a film form, the wall surfaces of the plurality of source openings 90 with the first electrode film 103 in between.

[0266] The second electrode film 104 faces the plurality of gate electrodes 32 in the portion covering the insulating surface 71, with the first electrode film 103 and the interlayer film 70 sandwiched therebetween. In other words, the second electrode film 104 faces the first silicide portion 40 and the first polysilicon portion 41 of each gate electrode 32, with the first electrode film 103 and the interlayer film 70 sandwiched therebetween.

[0267] The second electrode film 104, following the first electrode film 103, covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the source opening 90. In other words, the second electrode film 104 has a portion that extends in an arc shape at the arc corners of the interlayer film 70. This improves the film formability of the second electrode film 104 on the interlayer film 70 (wall surface of the source opening 90).

[0268] The second electrode film 104 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 sandwiched therebetween. The second electrode film 104 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 with the first electrode film 103 and the interlayer film 70 sandwiched therebetween. In other words, the second electrode film 104 faces the first polysilicon portion 41 of the gate electrode 32 with the first oxide film 72, the second oxide film 73, and the first electrode film 103 sandwiched therebetween.

[0269] The second electrode film 104 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, sandwiching the first electrode film 103 therebetween, and is electrically connected to the plurality of source regions 23, 24 and the contact region 25 via the first electrode film 103. When the first electrode film 103 is located on the bottom side of the source recess 91 with respect to the first main surface 3, the second electrode film 104 may have a portion that is located within the source recess 91. When the first electrode film 103 has a portion that is located above the first main surface 3, the entire second electrode film 104 is located above the source recess 91.

[0270] The plurality of first buried electrodes 101 form an intermediate layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and are buried in the plurality of source openings 90, respectively. The first buried electrodes 101 contain a conductive material different from the conductive material of the first underlying electrode film 100. The first buried electrodes 101 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the first buried electrodes 101 contain tungsten.

[0271] In this embodiment, the multiple first buried electrodes 101 are buried in a one-to-one correspondence with the multiple source openings 90 via a single first base electrode film 100. The multiple first buried electrodes 101 are electrically connected to the first main surface 3 (chip 2) within the multiple source openings 90. Specifically, the first buried electrode 101 is electrically connected to the multiple source regions 23, 24 and contact region 25 via the first base electrode film 100. The configuration of one first buried electrode 101 will be described below.

[0272] The first buried electrode 101 has a first buried electrode surface 105 exposed from the source opening 90, exposing the insulating surface 71. The first buried electrode surface 105 may be referred to as a "source buried electrode film." The first buried electrode 101 is buried in the source opening 90 at a distance from the insulating surface 71 toward the first main surface 3, and exposes a portion of the first base electrode film 100 (second electrode film 104) that covers the insulating surface 71. In other words, the first buried electrode surface 105 is located closer to the first main surface 3 than the insulating surface 71.

[0273] The first buried electrode 101 does not have a portion that faces the electrode surface 33 of the gate electrode 32 across the interlayer film 70 in the stacking direction (vertical direction Z). In other words, the first buried electrode 101 does not face the first silicide portion 40 and the first polysilicon portion 41 across the interlayer film 70 in the stacking direction (vertical direction Z).

[0274] The first buried electrode 101 covers the first oxide film 72 and the second oxide film 73 with the first base electrode film 100 sandwiched therebetween. The first buried electrode 101 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 in the horizontal direction. In other words, the first buried electrode 101 faces the first polysilicon portion 41 in the horizontal direction.

[0275] When the first underlying electrode film 100 is located on the bottom side of the source recess 91 with respect to the first main surface 3, the first buried electrode 101 may have a portion located within the source recess 91. When the first underlying electrode film 100 has a portion located above the first main surface 3, the entire first buried electrode 101 is located above the source recess 91.

[0276] The first buried electrode surface 105 of the first buried electrode 101 is located closer to the insulating surface 71 than the height position of the first oxide film 72. In this embodiment, the first buried electrode surface 105 is located higher than the electrode surface 33 of the gate electrode 32.

[0277] Specifically, the first buried electrode surface 105 has a recess 106 in the center that is recessed toward the first main surface 3 (chip 2). The bottom of the recess 106 is located on the insulating surface 71 side relative to the height position of the electrode surface 33. That is, in this embodiment, the entire first buried electrode surface 105 is located higher than the electrode surface 33. In this embodiment, the first buried electrode surface 105 has a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 sandwiched therebetween.

[0278] The first main electrode film 102 forms an upper layer of the source pad electrode 95 (the first pad portion 96, the second pad portion 97, and the third pad portion 98), and covers the first base electrode film 100 and the plurality of first buried electrodes 101 in a film form. The first main electrode film 102 contains a conductive material different from the conductive material of the first base electrode film 100 and the conductive material of the first buried electrodes 101.

[0279] The first main electrode film 102 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 100. The first main electrode film 102 has a thickness greater than the thickness of the first buried electrode 101.

[0280] The thickness of the first main electrode film 102 may be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 102 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0281] The first main electrode film 102 is mechanically and electrically connected to the first base electrode film 100 in a portion covering the insulating surface 71. As a result, the first main electrode film 102 faces the multiple gate electrodes 32 with the first base electrode film 100 and the interlayer film 70 sandwiched between them. In other words, the first main electrode film 102 faces the first silicide portion 40 and the first polysilicon portion 41 of each gate electrode 32 with the first base electrode film 100 and the interlayer film 70 sandwiched between them.

[0282] The first main electrode film 102 is mechanically and electrically connected to the plurality of first buried electrodes 101 in the portions covering the plurality of source openings 90. In other words, the first main electrode film 102 is electrically connected to the plurality of body regions 20, the outer body region 21, the plurality of source regions 23 and 24, the contact region 25, etc. via both the first base electrode film 100 and the plurality of first buried electrodes 101.

[0283] The first main electrode film 102 is directly connected to the first buried electrode surface 105 of the first buried electrode 101. In other words, the first main electrode film 102 has a portion that is connected to the first buried electrode surface 105 at a height position on the first main surface 3 side with respect to the height position of the insulating surface 71. The first main electrode film 102 is connected to the first buried electrode surface 105 at a height position higher than the height position of the first oxide film 72.

[0284] In this embodiment, the first main electrode film 102 is connected to the first buried electrode surface 105 above the electrode surface 33 of the gate electrode 32. In other words, the first main electrode film 102 does not have a portion that faces the gate electrode 32 in the horizontal direction. The first main electrode film 102 has a portion that covers the recess 106 of the first buried electrode surface 105. The first main electrode film 102 may also have a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 sandwiched therebetween.

[0285] The film formation properties of the first main electrode film 102 for the multiple source openings 90 are improved by the multiple first buried electrodes 101. This ensures an appropriate current path between the first main surface 3 and the first main electrode film 102. Such a configuration is effective in suppressing film formation defects caused by the multiple source openings 90 and reducing wiring resistance.

[0286] The source pad electrode 95 may have the layout shown in Figures 12A to 12D, which are enlarged cross-sectional views showing the source pad electrode 95 according to second, third, fourth and fifth examples.

[0287] The source pad electrode 95 does not necessarily have to have any one of the configurations of the first to fifth examples (FIG. 7, FIGS. 12A to 12D). The source pad electrode 95 may simultaneously include features of at least two of the configurations of the first to fifth examples. The source pad electrodes 95 according to the first to fifth examples are all formed by adjusting process conditions during the manufacturing process.

[0288] 12A to 12D show examples in which the source pad electrodes 95 according to the first to fifth examples are formed together with the gate electrode 32 according to the first example. However, the source pad electrodes 95 according to the first to fifth examples may be formed together with at least one of the gate electrodes 32 according to the first to fourth examples (FIGS. 7 and 10A to 10C).

[0289] 12A (second example), the source pad electrode 95 may include a plurality of first buried electrodes 101 extending in a vertically elongated columnar shape in a cross-sectional view. That is, the plurality of first buried electrodes 101 may be buried in a plurality of vertically elongated source openings 90 having an aspect ratio D / W greater than 1. In this case, each of the first buried electrodes 101 has an aspect ratio D / W greater than 1 in a cross-sectional view, corresponding to the aspect ratio D / W of the corresponding source opening 90.

[0290] The aspect ratio D / W of the vertically elongated first buried electrode 101 (source opening 90) is preferably greater than 1 and less than or equal to 3. For example, the aspect ratio D / W may have a value belonging to at least one of the following ranges: greater than 1 and less than or equal to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio D / W is preferably 2 or less.

[0291] In this embodiment, the first main electrode film 102 is mechanically and electrically connected to the plurality of first buried electrodes 101 extending in a vertically elongated columnar shape. In this configuration, the plurality of gate electrodes 32 are arranged at a narrow pitch by the plurality of first buried electrodes 101 (plurality of source openings 90) extending in a vertically elongated columnar shape. In particular, since the semiconductor device 1 does not have sidewall structures (spacers) on the sides of the gate electrodes 32, the narrow pitch of the plurality of gate electrodes 32, each having the first silicide portion 40, is not hindered by the sidewall structures (spacers).

[0292] Referring to FIG. 12B (third example), the source pad electrode 95 may include a plurality of first buried electrodes 101 having portions positioned closer to the first main surface 3 than the electrode surface 33 of the gate electrode 32.

[0293] In this embodiment, the plurality of first buried electrodes 101 each have a portion on the first buried electrode surface 105 that is positioned closer to the first main surface 3 than the electrode surface 33, and a portion that is positioned closer to the insulating surface 71 than the electrode surface 33. Specifically, on the first buried electrode surface 105, the bottom of the depression 106 is positioned closer to the first main surface 3 than the electrode surface 33, and the portion outside the depression 106 is positioned closer to the insulating surface 71 than the electrode surface 33.

[0294] In this embodiment, the first main electrode film 102 has a portion connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the first main surface 3 than the electrode surface 33, and a portion connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the insulating surface 71 than the electrode surface 33.

[0295] The first main electrode film 102 covers the interlayer film 70 across a portion of the first base electrode film 100 that covers the wall surface of the source opening 90, and has a portion that faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 in the horizontal direction. In other words, the first main electrode film 102 has a portion that faces the first polysilicon portion 41 in the horizontal direction.

[0296] 12C (fourth example), the source pad electrode 95 may include a plurality of first buried electrodes 101 located closer to the first main surface 3 than the height position of the electrode surface 33 of the gate electrode 32. In other words, the entire first buried electrode surface 105 may be located closer to the first main surface 3 than the electrode surface 33.

[0297] At least a part or all of the first buried electrode surface 105 may be located closer to the insulating surface 71 than the first oxide film 72. For example, the bottom of the recess 106 may be located closer to the insulating surface 71 than the first oxide film 72. In the first buried electrode surface 105, the bottom of the recess 106 may be located closer to the first main surface 3 than the first oxide film 72, and the portion outside the recess 106 may be located closer to the insulating surface 71 than the first oxide film 72. Of course, a configuration may be adopted in which the entire first buried electrode 101 is located closer to the first main surface 3 than the first oxide film 72.

[0298] In this embodiment, the first main electrode film 102 is connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the first principal surface 3 than the electrode surface 33, and does not have a portion connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the insulating surface 71 than the electrode surface 33.

[0299] In this embodiment, the first main electrode film 102 is connected to the first buried electrode surface 105 (first buried electrode 101) in a region above the first oxide film 72. The first main electrode film 102 has a portion that faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 in the horizontal direction. In other words, the first main electrode film 102 faces the first polysilicon portion 41 in the horizontal direction.

[0300] The first main electrode film 102 covers the interlayer film 70 across a portion of the first base electrode film 100 that covers the wall surface of the source opening 90. The first main electrode film 102 may be connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the first main surface 3 than the first oxide film 72.

[0301] 12D (fifth example), the source pad electrode 95 may have a plurality of first buried electrodes 101 that are drawn out onto the insulating surface 71 from the plurality of source openings 90 and cover the insulating surface 71. The plurality of first buried electrodes 101 cover the first underlying electrode film 100 on the insulating surface 71 and have portions that cover the insulating surface 71 with the first underlying electrode film 100 sandwiched therebetween.

[0302] That is, the plurality of first buried electrodes 101 each have a first buried electrode surface 105 exposed from the plurality of source openings 90 above the insulating surface 71. The plurality of first buried electrodes 101 have a portion facing the gate electrode 32 with the first base electrode film 100 and the interlayer film 70 sandwiched therebetween in the stacking direction (vertical direction Z). That is, the plurality of first base electrode films 100 have a portion facing the first silicide portion 40 and the first polysilicon portion 41 of the gate electrode 32 in the stacking direction (vertical direction Z).

[0303] The multiple first buried electrodes 101 are integrated on the insulating surface 71 to form one source intermediate electrode 107. The source intermediate electrode 107 (the multiple first buried electrodes 101) covers the entire area of ​​the first underlying electrode film 100. The electrode surface (first buried electrode surface 105) of the source intermediate electrode 107 is located above the insulating surface 71.

[0304] In this embodiment, the first main electrode film 102 is mechanically and electrically connected to the first buried electrode surfaces 105 of the plurality of first buried electrodes 101 (source intermediate electrodes 107) above the insulating surface 71. The first main electrode film 102 has a portion that faces the insulating surface 71 with the plurality of first buried electrodes 101 (source intermediate electrodes 107) in between. In this embodiment, the first main electrode film 102 does not have a mechanical connection portion to the first base electrode film 100.

[0305] The semiconductor device 1 includes a plurality of first source silicide portions 108 formed on the surface portions of the first main surface 3 that are exposed from the plurality of source openings 90. The plurality of first source silicide portions 108 are formed in film form along the wall surfaces (side walls and bottom walls) of the plurality of source recesses 91, and are mechanically and electrically connected to the first underlying electrode film 100.

[0306] That is, the multiple first source silicide portions 108 are formed in the surface layer portions of the multiple body regions 20, and electrically connect the multiple first buried electrodes 101 to the multiple body regions 20 via the first base electrode film 100.

[0307] The first source silicide portion 108 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first source silicide portion 108 is preferably made of Ti silicide, Ni silicide, or Co silicide.

[0308] Semiconductor device 1 includes source finger electrodes 110 extending from source pad electrode 95 onto peripheral region 9. Source finger electrode 110 transmits a source potential applied to source pad electrode 95 to peripheral region 9. In this embodiment, source finger electrode 110 is routed from a portion of source pad electrode 95 (first pad portion 96) on the fourth side surface 5D side onto a portion of interlayer film 70 covering peripheral region 9.

[0309] The source finger electrodes 110 extend above the termination region 45 and are electrically connected to the termination region 45 via a plurality of outer openings 92. Specifically, the source finger electrodes 110 are electrically connected to the overlap region 46 of the termination region 45 via a plurality of outer openings 92. The source finger electrodes 110 extend in a strip shape along the termination region 45 (overlap region 46). The source finger electrodes 110 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0310] In this embodiment, the source finger electrode 110 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95. The source finger electrode 110 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0311] Like the source pad electrode 95, the source finger electrode 110 includes a first underlying electrode film 100, a plurality of first buried electrodes 101, and a first main electrode film 102. The first underlying electrode film 100 forms a lower layer portion of the source finger electrode 110, and covers the interlayer film 70 in the peripheral region 9.

[0312] The first underlying electrode film 100 collectively covers, in a film-like manner, the regions of the interlayer film 70 where the multiple outer openings 92 are formed. That is, the first underlying electrode film 100 extends from above the insulating surface 71 into the multiple outer openings 92. The first underlying electrode film 100 has a portion that covers, in a film-like manner, the insulating surface 71 of the interlayer film 70, and a portion that covers, in a film-like manner, the wall surfaces of the multiple outer openings 92. The first underlying electrode film 100 defines recesses within the multiple outer openings 92.

[0313] Similar to the source pad electrode 95, the first base electrode film 100 has a laminated structure including a first electrode film 103 and a second electrode film 104. The first electrode film 103 collectively covers the region of the interlayer film 70 where the multiple outer openings 92 are formed, and extends into the multiple outer openings 92 from above the insulating surface 71. In other words, the first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.

[0314] The first electrode film 103 covers the arcuate corners of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arcuate corners of the interlayer film 70 (second oxide film 73), and extends into the outer opening 92. In other words, the first electrode film 103 has a portion that extends in an arcuate shape at the arcuate corners. This improves the film-forming properties of the first electrode film 103 on the interlayer film 70 (wall surface of the outer opening 92). The first electrode film 103 extends along the wall surface of the outer opening 92 and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73.

[0315] The first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 103 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the termination region 45 (overlap region 46) within the outer recess 93.

[0316] The first electrode film 103 may cover the outer recess 93 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the outer recess 93. The first electrode film 103 may have a portion located on the bottom side of the outer recess 93 relative to the height position of the first main surface 3, and a portion located on the peripheral insulating film 51 side relative to the height position of the first main surface 3.

[0317] The second electrode film 104 is located on the first electrode film 103 and collectively covers the region of the interlayer film 70 where the multiple outer openings 92 are formed. That is, the second electrode film 104 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner with the first electrode film 103 in between, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner with the first electrode film 103 in between.

[0318] The second electrode film 104, following the first electrode film 103, covers the arc corner portion of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the outer opening 92. In other words, the second electrode film 104 has a portion that extends in an arc shape at the arc corner portion of the interlayer film 70 (second oxide film 73).

[0319] This improves the film formation property of the second electrode film 104 on the interlayer film 70 (the wall surface of the outer opening 92). The second electrode film 104 extends along the wall surface of the outer opening 92, and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 sandwiched therebetween.

[0320] The second electrode film 104 has a portion at the bottom of each outer opening 92 that sandwiches the first electrode film 103 and covers the outer recess 93 in a film-like manner, and is electrically connected to the termination region 45 (overlap region 46) via the first electrode film 103.

[0321] When the first electrode film 103 is located on the bottom side of the outer recess 93 with respect to the first main surface 3, the second electrode film 104 may have a portion located within the outer recess 93. When the first electrode film 103 has a portion located above the first main surface 3, the entire second electrode film 104 is located above the outer recess 93.

[0322] The plurality of first buried electrodes 101 form middle layers of the source finger electrodes 110 and are buried in the plurality of outer openings 92, respectively. In this embodiment, the plurality of first buried electrodes 101 are buried in the plurality of outer openings 92 in a one-to-one correspondence via a single first base electrode film 100. The plurality of first buried electrodes 101 are electrically connected to the termination region 45 (overlap region 46) via the first base electrode film 100.

[0323] The first buried electrode 101 has a first buried electrode surface 105 exposed from the outer opening 92, exposing the insulating surface 71. Specifically, the first buried electrode 101 is buried in the outer opening 92 at a distance from the insulating surface 71 toward the first main surface 3, exposing a portion of the first base electrode film 100 (second electrode film 104) that covers the insulating surface 71. In other words, the first buried electrode surface 105 is located closer to the first main surface 3 than the insulating surface 71.

[0324] The first buried electrode 101 covers the first oxide film 72 and the second oxide film 73 with the first base electrode film 100 sandwiched therebetween. The first buried electrode surface 105 is located closer to the insulating surface 71 than the height position of the first oxide film 72 in the outer opening 92. The first buried electrode 101 has a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 sandwiched therebetween.

[0325] The first buried electrode 101 may be embedded at a distance from the arc corner portion of the interlayer film 70 toward the peripheral insulating film 51, with the entire arc corner portion being exposed. In this case, the first buried electrode surface 105 may be located closer to the insulating surface 71 than the height position of the first oxide film 72. Of course, the first buried electrode surface 105 may also be located closer to the peripheral insulating film 51 than the height position of the first oxide film 72.

[0326] When the first underlying electrode film 100 is located on the bottom side of the outer recess 93 with respect to the first main surface 3, the first buried electrode 101 may have a portion located within the outer recess 93. When the first underlying electrode film 100 has a portion located above the first main surface 3, the entire first buried electrode 101 is located above the outer recess 93.

[0327] The first main electrode film 102 forms an upper layer portion of the source finger electrode 110, and covers the first underlying electrode film 100 and the plurality of first buried electrodes 101 in a film-like manner. The first main electrode film 102 is mechanically and electrically connected to the first underlying electrode film 100 in the portion covering the insulating surface 71, and is mechanically and electrically connected to the plurality of first buried electrodes 101 in the portion covering the plurality of outer openings 92. In other words, the first main electrode film 102 is electrically connected to the termination region 45 (overlap region 46) via the first underlying electrode film 100 and the plurality of first buried electrodes 101.

[0328] The first main electrode film 102 is also directly connected to the first buried electrode surface 105 of the first buried electrode 101 on the source finger electrode 110 side. In other words, the first main electrode film 102 has a portion that is connected to the first buried electrode surface 105 at a height position on the first main surface 3 side relative to the height position of the insulating surface 71.

[0329] The first main electrode film 102 is connected to the first buried electrode surface 105 at a height higher than the first oxide film 72. The first main electrode film 102 has a portion that covers the depression 106 of the first buried electrode surface 105. The first main electrode film 102 may have a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 sandwiched therebetween.

[0330] The film formation properties of the first main electrode film 102 in the outer openings 92 are improved by the first buried electrodes 101. This ensures an appropriate current path between the termination region 45 (overlap region 46) and the first main electrode film 102. Such a configuration is effective in suppressing film formation defects caused by the outer openings 92 and reducing wiring resistance.

[0331] In addition, the connection mode of the first main electrode film 102 of the source finger electrode 110 to the first buried electrode 101 of the source finger electrode 110 is similar to the connection mode of the first main electrode film 102 of the source pad electrode 95 to the first buried electrode 101 of the source pad electrode 95.

[0332] The semiconductor device 1 includes a plurality of second source silicide portions 111 formed on the surface portions of the first main surface 3 that are exposed from the plurality of outer openings 92. The plurality of second source silicide portions 111 are formed in film form along the wall surfaces (side walls and bottom walls) of the plurality of outer recesses 93, and are mechanically and electrically connected to the first underlying electrode film 100.

[0333] In other words, the multiple second source silicide portions 111 are formed in the surface layer of the termination region 45 (overlap region 46), and electrically connect the multiple first buried electrodes 101 to the termination region 45 (overlap region 46) via the first base electrode film 100.

[0334] The second source silicide portion 111 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The second source silicide portion 111 is preferably made of Ti silicide, Ni silicide, or Co silicide. The second source silicide portion 111 is particularly preferably made of the same type of silicide as the first source silicide portion 108.

[0335] The semiconductor device 1 includes gate finger electrodes 115 selectively routed on the interlayer film 70. The gate finger electrodes 115 transmit a gate potential to the gate wiring 52. The gate finger electrodes 115 are routed on a portion of the interlayer film 70 that covers the gate wiring 52 (i.e., on the outer periphery region 9), and are electrically connected to the gate wiring 52 through a plurality of gate openings 94.

[0336] The gate finger electrode 115 is disposed in a region between the source pad electrode 95 and the source finger electrode 110 and is spaced apart from the source pad electrode 95 and the source finger electrode 110. The gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip shape along the gate wiring 52. The gate finger electrode 115 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0337] In this embodiment, the gate finger electrode 115 is formed in a band shape with four sides parallel to the periphery of the first main surface 3 and surrounds the source pad electrode 95. The gate finger electrode 115 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The gate finger electrode 115 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 110 passes.

[0338] 9 , the gate finger electrode 115 includes a second underlying electrode film 120, at least one (in this embodiment, a plurality) second buried electrodes 121, and a second main electrode film 122. The second underlying electrode film 120 may be referred to as a "gate underlying electrode film," the second buried electrode 121 may be referred to as a "gate buried electrode," and the second main electrode film 122 may be referred to as a "gate main electrode film."

[0339] The second base electrode film 120 forms a lower layer of the gate finger electrode 115, and covers the interlayer film 70 in the peripheral region 9. The second base electrode film 120 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed.

[0340] That is, the second base electrode film 120 extends from above the insulating surface 71 into the plurality of gate openings 94. The second base electrode film 120 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the plurality of gate openings 94 in a film-like manner. The second base electrode film 120 defines a plurality of recesses within the plurality of gate openings 94.

[0341] The second base electrode film 120 has a layered structure including a first electrode film 123 layered on the interlayer film 70, and a second electrode film 124 layered on the first electrode film 123. It is preferable that the first electrode film 123 contains the same type of conductive material as the first electrode film 103 on the source side, and the second electrode film 124 contains the same type of conductive material as the second electrode film 104 on the source side. In this embodiment, the first electrode film 123 contains a Ti film, and the second electrode film 124 contains a TiN film.

[0342] The second base electrode film 120 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 123 (Ti film) or the second electrode film 124 (TiN film). The first electrode film 123 may have a thickness approximately equal to that of the first electrode film 103 on the source side. The second electrode film 124 may have a thickness approximately equal to that of the second electrode film 104 on the source side.

[0343] The first electrode film 123 collectively covers the region of the interlayer film 70 where the multiple gate openings 94 are formed, and extends into the multiple gate openings 94 from above the insulating surface 71. In other words, the first electrode film 123 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.

[0344] The first electrode film 123 covers the arcuate corners of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arcuate corners of the interlayer film 70 (second oxide film 73), and extends into the gate opening 94. In other words, the first electrode film 123 has a portion that extends in an arcuate shape at the arcuate corners. This improves the film formability of the first electrode film 123 on the interlayer film 70 (wall surface of the gate opening 94). The first electrode film 123 extends along the wall surface of the gate opening 94 and covers the first oxide film 72 and the second oxide film 73.

[0345] The first electrode film 123 covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is electrically connected to the gate wiring 52. Specifically, the first electrode film 123 has a portion that covers the second silicide portion 60 of the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is mechanically and electrically connected to the second silicide portion 60.

[0346] The first electrode film 123 is mechanically connected to the second silicide portion 60 at a distance inward from the second polysilicon portion 61. In other words, the first electrode film 123 is mechanically connected only to the second silicide portion 60, and is not mechanically connected to the second polysilicon portion 61. The first electrode film 123 is electrically connected to the second polysilicon portion 61 via the second silicide portion 60. Of course, the first electrode film 123 (second base electrode film 120) may have a portion connected to the second polysilicon portion 61.

[0347] The second electrode film 124 collectively covers, in a film form, the region of the interlayer film 70 on the first electrode film 123 where the multiple gate openings 94 are formed. That is, the second electrode film 124 has a portion that covers, in a film form, the insulating surface 71 of the interlayer film 70 with the first electrode film 123 in between, and a portion that covers, in a film form, the wall surfaces of the multiple gate openings 94 with the first electrode film 123 in between.

[0348] The second electrode film 124, following the first electrode film 123, covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the gate opening 94. In other words, the second electrode film 124 has a portion that extends in an arc shape at the arc corners of the interlayer film 70 (second oxide film 73). This improves the film formability of the second electrode film 124 on the interlayer film 70 (wall surface of the gate opening 94). The second electrode film 124 extends along the wall surface of the gate opening 94 and covers the first oxide film 72 and the second oxide film 73 with the first electrode film 123 sandwiched between them.

[0349] The second electrode film 124 has a portion that covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, with the first electrode film 123 sandwiched therebetween, and is electrically connected to the gate wiring 52 via the first electrode film 123. Specifically, the second electrode film 124 has a portion that covers the second silicide portion 60 of the gate wiring 52 in a film-like manner, with the first electrode film 123 sandwiched therebetween, and is electrically connected to the second silicide portion 60 via the first electrode film 123.

[0350] The second electrode film 124 is located on the second silicide portion 60 with a gap inward from the second polysilicon portion 61. In other words, the second electrode film 124 faces only the second silicide portion 60 across the first electrode film 123, and does not face the second polysilicon portion 61. The second electrode film 124 is electrically connected to the second polysilicon portion 61 via the first electrode film 123 and the second silicide portion 60. Of course, the second electrode film 124 may have a portion facing the second polysilicon portion 61 across the first electrode film 123.

[0351] The plurality of second buried electrodes 121 form middle layers of the gate finger electrodes 115 and are buried in the plurality of gate openings 94, respectively. The second buried electrodes 121 contain a conductive material different from the conductive material of the second underlying electrode film 120. The second buried electrodes 121 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. The second buried electrodes 121 preferably contain the same type of conductive material as the first buried electrodes 101. In this embodiment, the second buried electrodes 121 contain tungsten.

[0352] In this embodiment, the second buried electrodes 121 are buried in one-to-one correspondence with the gate openings 94 via a single second base electrode film 120. The second buried electrodes 121 are electrically connected to the second silicide portions 60 of the gate wiring 52 within the gate openings 94 via the second base electrode film 120.

[0353] The plurality of second buried electrodes 121 are located above the second silicide portion 60 at intervals inward from the second polysilicon portion 61. In other words, the plurality of second buried electrodes 121 face only the second silicide portion 60 across the first electrode film 123, and do not face the second polysilicon portion 61. The plurality of second buried electrodes 121 are electrically connected to the second polysilicon portion 61 via the second base electrode film 120. Of course, the plurality of second buried electrodes 121 may have a portion facing the second polysilicon portion 61 across the second base electrode film 120.

[0354] The second buried electrode 121 has a second buried electrode surface 125 exposed from the gate opening 94, exposing the insulating surface 71. The second buried electrode surface 125 may be referred to as a "gate buried electrode surface." The second buried electrode 121 is buried in the gate opening 94 at a distance from the insulating surface 71 toward the first main surface 3, exposing a portion of the second base electrode film 120 (second electrode film 124) that covers the insulating surface 71. In other words, the second buried electrode surface 125 is located closer to the first main surface 3 than the insulating surface 71.

[0355] The second buried electrode 121 covers the first oxide film 72 and the second oxide film 73 with the second base electrode film 120 sandwiched therebetween. The second buried electrode surface 125 is positioned closer to the insulating surface 71 than the height position of the first oxide film 72. The second buried electrode 121 has a portion that covers the arc corner portion of the interlayer film 70 with the second base electrode film 120 sandwiched therebetween.

[0356] The second buried electrode 121 may be buried at a distance from the arc corner portion of the interlayer film 70 toward the gate wiring 52, with the entire arc corner portion exposed. In this case, the second buried electrode surface 125 may be located closer to the insulating surface 71 than the height position of the first oxide film 72. Of course, the second buried electrode surface 125 may also be located closer to the gate wiring 52 than the height position of the first oxide film 72.

[0357] The second main electrode film 122 forms an upper layer of the gate finger electrode 115, and covers the second base electrode film 120 and the plurality of second buried electrodes 121 in a film form. The second main electrode film 122 contains a conductive material different from the conductive material of the second base electrode film 120 and the conductive material of the second buried electrodes 121.

[0358] The second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The second main electrode film 122 preferably includes the same type of conductive material as the conductive material of the first main electrode film 102. The second main electrode film 122 may have a thickness approximately equal to that of the first main electrode film 102.

[0359] The second main electrode film 122 is mechanically and electrically connected to the second base electrode film 120 in a portion covering the insulating surface 71, and is mechanically and electrically connected to the plurality of second buried electrodes 121 in portions covering the plurality of gate openings 94. As a result, the second main electrode film 122 is electrically connected to the second silicide portion 60 via the second base electrode film 120 and the plurality of second buried electrodes 121.

[0360] The second main electrode film 122 has a portion connected to the second buried electrode 121 at a height position closer to the first main surface 3 than the height position of the insulating surface 71. The second main electrode film 122 is connected to the second buried electrode surface 125 above the height position of the first oxide film 72. The second main electrode film 122 has a portion covering the arc corner portion of the interlayer film 70 with the second base electrode film 120 sandwiched therebetween. When the second buried electrode 121 is located below the first oxide film 72, the second main electrode film 122 may be connected to the second buried electrode 121 in a region below the first oxide film 72.

[0361] The film formation properties of the second main electrode film 122 for the multiple gate openings 94 are improved by the multiple second buried electrodes 121. This ensures an appropriate current path between the gate wiring 52 (second silicide portion 60) and the second main electrode film 122. Such a configuration is effective in suppressing film formation defects caused by the multiple gate openings 94 and reducing wiring resistance.

[0362] The semiconductor device 1 includes a gate pad electrode 130 disposed on the interlayer film 70. The gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 130 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. The gate pad electrode 130 is disposed in a region between the source pad electrode 95 and the source finger electrodes 110 and spaced apart from the source pad electrode 95 and the source finger electrodes 110.

[0363] In this embodiment, the gate pad electrode 130 is disposed in a region on the third side surface 5C side with respect to the first pad portion 96, and is sandwiched between the second pad portion 97 and the third pad portion 98. In other words, the gate pad electrode 130 faces the first pad portion 96 in the first direction X, and faces the second pad portion 97 and the third pad portion 98 in the second direction Y.

[0364] The gate pad electrode 130 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 130 has a planar area less than that of the source pad electrode 95 (first pad portion 96). The gate pad electrode 130 may have a planar area less than that of the second pad portion 97 (third pad portion 98).

[0365] The gate pad electrode 130 is disposed on a portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 115. The gate pad electrode 130 may cover the plurality of gate electrodes 32 with the interlayer film 70 interposed therebetween, or may cover the gate wiring 52 with the interlayer film 70 interposed therebetween.

[0366] Like the gate finger electrode 115, the gate pad electrode 130 includes a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 forms a lower layer of the gate pad electrode 130 and covers the interlayer film 70 in a film form.

[0367] Similar to the gate finger electrode 115, the second base electrode film 120 has a laminated structure including a first electrode film 123 and a second electrode film 124. The first electrode film 123 covers the interlayer film 70 in a film-like manner, and the second electrode film 124 covers the first electrode film 123 in a film-like manner. The second main electrode film 122 forms an upper layer portion of the gate pad electrode 130 and covers the second base electrode film 120 in a film-like manner.

[0368] Although not specifically shown in the drawings, the gate pad electrode 130 may have a plurality of second buried electrodes 121, similar to the gate finger electrode 115. In this case, the gate pad electrode 130 may be electrically connected to the gate wiring 52 (second silicide portion 60) via the plurality of second buried electrodes 121, similar to the gate finger electrode 115.

[0369] When a plurality of gate electrodes 32 are disposed below the gate pad electrode 130, the gate pad electrode 130 may be electrically connected to the plurality of gate electrodes 32 (first silicide portions 40) via a plurality of second buried electrodes 121. Of course, the gate pad electrode 130 does not have to have a plurality of second buried electrodes 121. In other words, the gate pad electrode 130 does not have to have an electrical connection portion to the plurality of gate electrodes 32 and an electrical connection portion to the gate wiring 52 in the region directly below it.

[0370] The gate potential applied to the gate pad electrode 130 is applied to the second silicide portion 60 of the gate wiring 52 via the gate finger electrode 115. The gate potential is transmitted from the second silicide portion 60 to the first silicide portions 40 of the plurality of gate electrodes 32 via a wiring path (current path) along the gate wiring 52.

[0371] This turns on the plurality of gate electrodes 32, thereby controlling the on / off of the plurality of channel regions 26, 27. The wiring resistance (gate resistance) caused by the polysilicon of the gate electrode 32 is reduced by the first silicide portion 40. Similarly, the wiring resistance (gate resistance) caused by the polysilicon of the gate wiring 52 is reduced by the second silicide portion 60.

[0372] The semiconductor device 1 includes a drain pad electrode 140 covering the second main surface 4. The drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 140 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like.

[0373] The drain pad electrode 140 is electrically connected to the second semiconductor region 7. The drain pad electrode 140 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 140 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0374] The breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0375] As described above, the semiconductor device 1 includes the chip 2, the gate electrode 32, the first silicide portion 40, and the first polysilicon portion 41. The chip 2 has a first main surface 3. The gate electrode 32 is disposed on the first main surface 3. The gate electrode 32 includes polysilicon and has an electrode surface 33.

[0376] The first silicide portion 40 is formed partially on the surface portion of the electrode surface 33. The first polysilicon portion 41 is formed on the surface portion of the electrode surface 33 in a portion other than the first silicide portion 40. According to this configuration, the wiring resistance (gate resistance) of the gate electrode 32 is reduced by the first silicide portion 40.

[0377] The gate electrode 32 has a first sidewall 34 and a second sidewall 35. The first silicide portion 40 is preferably formed at a distance inward from at least one of the first sidewall 34 and the second sidewall 35. In other words, the first polysilicon portion 41 is preferably exposed from at least one of the first sidewall 34 and the second sidewall 35.

[0378] According to this configuration, in the manufacturing process (polysilicon etching step) of the gate electrode 32, the first silicide portion 40 is not removed from at least one of the first sidewall 34 and the second sidewall 35. This suppresses metal contamination (metal particle contamination) of other structures on the first main surface 3 and metal contamination (metal particle contamination) of the manufacturing equipment caused by etching of the first silicide portion 40.

[0379] For example, when the gate electrodes 32 are arranged at a narrow pitch, it is difficult to remove metal contamination in the regions to the sides of the gate electrodes 32 (relatively narrow regions between the gate electrodes 32). Therefore, the configuration of the semiconductor device 1 is effective in suppressing metal contamination in the regions to the sides of the gate electrodes 32 (relatively narrow regions between the gate electrodes 32) when the gate electrodes 32 are arranged at a narrow pitch.

[0380] In particular, in the case of the semiconductor device 1 having SiC, due to its characteristics (physical properties), an extremely high voltage is applied, unlike lateral type Si semiconductor devices such as LSIs. Metal contamination on the first main surface 3 may have an unexpected effect on the electrical characteristics of the semiconductor device 1 due to the high voltage. Therefore, by eliminating the possibility of metal contamination on the first main surface 3, a semiconductor device 1 having appropriate electrical characteristics is provided.

[0381] In this case, the first silicide portion 40 is preferably formed at a distance inward from both the first sidewall 34 and the second sidewall 35. That is, the first polysilicon portion 41 is preferably exposed from both the first sidewall 34 and the second sidewall 35. According to this configuration, metal contamination on the first main surface 3 caused by the first silicide portion 40 is appropriately suppressed.

[0382] The first silicide portion 40 is preferably formed at a distance inward from both the first sidewall 34 and the second sidewall 35 over the entire surface of the electrode surface 33. In other words, the first polysilicon portion 41 is preferably exposed from both the first sidewall 34 and the second sidewall 35 over the entire surface of the electrode surface 33.

[0383] The first polysilicon portion 41 may form a flat electrode surface 33 together with the first silicide portion 40 (see FIG. 7). The first polysilicon portion 41 may be recessed closer to the first main surface 3 than the first silicide portion 40 (see FIG. 10A). The first polysilicon portion 41 may protrude upward than the first silicide portion 40 (see FIG. 10B). The first silicide portion 40 may be formed on the surface portion of the electrode surface 33 at a distance from the middle portion of the gate electrode 32 toward the electrode surface 33 in the thickness direction.

[0384] The semiconductor device 1 may include a gate wiring 52 selectively routed on the first main surface 3 so as to be connected to the gate electrode 32. The gate wiring 52 includes polysilicon and has a wiring surface 53.

[0385] In such a configuration, the semiconductor device 1 may include a second silicide portion 60 and a second polysilicon portion 61. The second silicide portion 60 is formed in the surface portion of the wiring surface 53. The second polysilicon portion 61 is formed in a portion of the surface portion of the wiring surface 53 outside the second silicide portion 60. According to this configuration, the wiring resistance of the gate wiring 52 is reduced by the first silicide portion 40.

[0386] The second silicide portion 60 is preferably connected to the first silicide portion 40 at the connection portion of the gate electrode 32 and the gate wiring 52. The second polysilicon portion 61 is preferably connected to the first polysilicon portion 41 at the connection portion of the gate electrode 32 and the gate wiring 52. According to this configuration, a wiring path is formed that reaches the first silicide portion 40 via the second silicide portion 60. This appropriately reduces the wiring resistance in both the gate electrode 32 and the gate wiring 52.

[0387] The gate wiring 52 has a first wiring sidewall 54 and a second wiring sidewall 55. The second silicide portion 60 is preferably formed at a distance inward from at least one of the first wiring sidewall 54 and the second wiring sidewall 55. In other words, the second polysilicon portion 61 is preferably exposed from at least one of the first wiring sidewall 54 and the second wiring sidewall 55.

[0388] According to this configuration, in the manufacturing process of the gate wiring 52 (polysilicon etching step), the second silicide portion 60 is not removed from at least one of the first wiring sidewall 54 and the second wiring sidewall 55. This suppresses metal contamination (metal particle contamination) of other structures on the first main surface 3 and metal contamination (metal particle contamination) of the manufacturing equipment caused by etching the second silicide portion 60. Therefore, a semiconductor device 1 having appropriate electrical characteristics is provided.

[0389] In this case, the second silicide portion 60 is preferably formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55. In other words, the second polysilicon portion 61 is preferably exposed from both the first wiring sidewall 54 and the second wiring sidewall 55. According to this configuration, metal contamination on the first main surface 3 caused by the first silicide portion 40 is appropriately suppressed.

[0390] The second silicide portion 60 is preferably formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55 over the entire surface area of ​​the wiring surface 53. In other words, the second polysilicon portion 61 is preferably exposed from both the first wiring sidewall 54 and the second wiring sidewall 55 over the entire surface area of ​​the wiring surface 53.

[0391] The gate electrode 32 may extend in the second direction Y (one direction). In this case, the gate wiring 52 may have a portion extending in the first direction X (intersecting direction) intersecting the second direction Y (one direction). That is, the gate wiring 52 may be connected to the gate electrode 32 in a T-shape (see FIG. 5). The second silicide portion 60 may be connected to the first silicide portion 40 in a T-shape (see FIG. 5). The second polysilicon portion 61 may be connected to the first polysilicon portion 41 in an L-shape at a connection corner of the gate electrode 32 and the gate wiring 52 (see FIG. 5).

[0392] The semiconductor device 1 may include an interlayer film 70. The interlayer film 70 may cover the gate electrode 32 and have a portion in contact with the first silicide portion 40 and a portion in contact with the first polysilicon portion 41. In this case, the semiconductor device 1 preferably does not have an insulating sidewall structure (spacer) that covers the first sidewall 34 and the second sidewall 35 of the gate electrode 32. In other words, the interlayer film 70 preferably directly covers the first sidewall 34 and the second sidewall 35 of the gate electrode 32.

[0393] The interlayer film 70 may cover the gate wiring 52 and have a portion in contact with the second silicide portion 60 and a portion in contact with the second polysilicon portion 61. In this case, it is preferable that the semiconductor device 1 does not have an insulating sidewall structure (spacer) that covers the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52. In other words, it is preferable that the interlayer film 70 directly covers the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52.

[0394] The interlayer film 70 may have a stacked structure including a first oxide film 72 and a second oxide film 73. The first oxide film 72 may be an oxide film with no impurities added. The first oxide film 72 may have a portion in contact with the first silicide portion 40 and a portion in contact with the first polysilicon portion 41. The second oxide film 73 may be an oxide film containing phosphorus. The second oxide film 73 may have portions that cover the first silicide portion 40 and the first polysilicon portion 41 with the first oxide film 72 sandwiched therebetween.

[0395] The first oxide film 72 may have a portion in contact with the second silicide portion 60 and a portion in contact with the second polysilicon portion 61. The second oxide film 73 may be an oxide film containing phosphorus. The second oxide film 73 may have portions that cover the second silicide portion 60 and the second polysilicon portion 61 with the first oxide film 72 sandwiched therebetween.

[0396] The semiconductor device 1 may include an n-type first semiconductor region 6, a p-type body region 20, n-type source regions 23 and 24 (impurity regions), channel regions 26 and 27 (channels), and an insulating film 31. The first semiconductor region 6 may be formed in a surface layer portion of the first main surface 3. The body region 20 may be formed in a surface layer portion of the first semiconductor region 6. The source regions 23 and 24 may be formed in a surface layer portion of the body region 20.

[0397] The channel regions 26, 27 may be formed in a region between the first semiconductor region 6 and the source regions 23, 24 in a surface layer portion of the body region 20. The insulating film 31 may cover the channel regions 26, 27 on the first main surface 3. In this case, the gate electrode 32 may face the channel regions 26, 27 with the insulating film 31 interposed therebetween.

[0398] From another perspective, the semiconductor device 1 includes a chip 2, a gate electrode 32, an interlayer film 70, a source opening 90, a first buried electrode 101, and a first main electrode film 102. The chip 2 has a first main surface 3. The gate electrode 32 is disposed on the first main surface 3. The interlayer film 70 covers the gate electrode 32 and has an insulating surface 71. The source opening 90 is formed in the interlayer film 70 at a distance from the gate electrode 32, exposing the first main surface 3.

[0399] The first buried electrode 101 is buried in the source opening 90 and electrically connected to the first main surface 3. The first buried electrode 101 has a first buried electrode surface 105 exposed from the source opening 90. The first main electrode film 102 is mechanically and electrically connected to the first buried electrode surface 105 of the first buried electrode 101. According to this configuration, the first buried electrode 101 improves the film formation properties of the first main electrode film 102 in the source opening 90.

[0400] The first buried electrode 101 is preferably buried in the source opening 90 so as to expose the insulating surface 71. In this configuration, the first main electrode film 102 is preferably disposed on the insulating surface 71 of the interlayer film 70 and the first buried electrode surface 105 of the first buried electrode 101. According to this configuration, the step between the insulating surface 71 and the source opening 90 is reduced by the first buried electrode 101. This improves the film formability of the first main electrode film 102 on the insulating surface 71 of the interlayer film 70 and the first buried electrode surface 105 of the first buried electrode 101.

[0401] The first buried electrode surface 105 of the first buried electrode 101 may be located closer to the first principal surface 3 than the insulating surface 71. This configuration appropriately prevents the first buried electrode 101 from protruding above the insulating surface 71. In this case, the first principal electrode film 102 may be connected to the first buried electrode surface 105 of the first buried electrode 101 on the first principal surface 3 side than the insulating surface 71.

[0402] The first buried electrode surface 105 of the first buried electrode 101 is preferably located higher than the electrode surface 33 of the gate electrode 32. With this configuration, the step between the insulating surface 71 and the source opening 90 is reduced by the first buried electrode 101 to a height position higher than the electrode surface 33. This allows the connection portion of the source main electrode to the first buried electrode 101 to be located higher than the electrode surface 33.

[0403] The first buried electrode surface 105 of the first buried electrode 101 may have a recess 106 facing the chip 2. In this case, the bottom of the recess 106 is preferably positioned higher than the height of the gate electrode 32 (electrode surface 33). The source opening 90 preferably has an aspect ratio D / W of its length along the stacking direction.

[0404] According to this configuration, the first buried electrode 101 is buried in the narrow source opening 90. As a result, the first buried electrode 101 improves the film formability of the first main electrode film 102 in the narrow source opening 90. Furthermore, according to this configuration, an increase in the size of the device due to the aspect ratio D / W of the source opening 90 is suppressed.

[0405] The first buried electrode 101 preferably contains tungsten. With this configuration, the first buried electrode 101 is appropriately buried in the source opening 90 by utilizing the physical properties of tungsten. The first main electrode film 102 may contain aluminum. For example, the first buried electrode 101 may contain tungsten, while the first main electrode film 102 may contain aluminum. Such a configuration is effective in improving the film formability of the first main electrode film 102 for the narrow source opening 90 when a relatively narrow source opening 90 is formed.

[0406] The interlayer film 70 may have a stacked structure including a first oxide film 72 and a second oxide film 73. The first oxide film 72 may be an oxide film with no impurities added. The second oxide film 73 may be an oxide film containing phosphorus. In this case, the source opening 90 may penetrate the first oxide film 72 and the second oxide film 73.

[0407] The interlayer film 70 preferably has an arc-shaped corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate electrode 32. In this configuration, the source opening 90 preferably has an opening end defined by the arc-shaped corner portion. With this configuration, the arc-shaped corner portion improves the embedding of the first buried electrode 101 in the source opening 90. In addition, the deposition property of the first main electrode film 102 in the first buried electrode 101 (source opening 90) is improved.

[0408] A plurality of gate electrodes 32 may be arranged at intervals on the first main surface 3. In this case, the source opening 90 may be defined in a region between the plurality of gate electrodes 32. According to this configuration, the first buried electrode 101 improves the film formation property of the first main electrode film 102 in the source opening 90 defined in the region between the plurality of gate electrodes 32.

[0409] The semiconductor device 1 may include a first underlying electrode film 100. The first underlying electrode film 100 may cover the wall surface of the source opening 90 and have a portion electrically connected to the chip 2 within the source opening 90. In this case, the first buried electrode 101 may be buried in the source opening 90 via the first underlying electrode film 100. For example, according to this configuration, the first buried electrode 101 can be buried in the source opening 90 using the first underlying electrode film 100 as a barrier film against the chip 2. For example, the first underlying electrode film 100 may include at least one of a Ti film and a TiN film.

[0410] The first underlying electrode film 100 may be mechanically and electrically connected to the chip 2. The first buried electrode 101 may be electrically connected to the chip 2 via the first underlying electrode film 100. The first underlying electrode film 100 may have a portion that covers the insulating surface 71 outside the source opening 90. The first main electrode film 102 may cover the insulating surface 71 with the first underlying electrode film 100 sandwiched therebetween. For example, according to this configuration, the first main electrode film 102 can be formed on the interlayer film 70 using the first underlying electrode film 100 as a barrier film for the interlayer film 70.

[0411] The semiconductor device 1 may include a first source silicide portion 108 formed in a surface layer portion of the first main surface 3 that is exposed from the source opening 90. In this case, the first source silicide portion 108 may be mechanically and electrically connected to the first underlying electrode film 100. This configuration improves the ohmic contact between the chip 2 and the first underlying electrode film 100 (first buried electrode 101).

[0412] The semiconductor device 1 may include a source recess 91 formed in a portion of the first main surface 3 exposed from the source opening 90. In this case, the first underlying electrode film 100 may have a portion located within the source recess 91.

[0413] The semiconductor device 1 may include a gate wiring 52 selectively routed over the first main surface 3 and connected to the gate electrode 32. According to this configuration, the gate wiring 52 forms a wiring path for the gate electrode 32.

[0414] The semiconductor device 1 may include a gate opening 94, a second buried electrode 121, and a second main electrode film 122. The gate opening 94 may be formed in the interlayer film 70 so as to expose the gate wiring 52. The second buried electrode 121 may be buried in the gate opening 94 and electrically connected to the gate wiring 52.

[0415] The second buried electrode 121 may have a second buried electrode surface 125 exposed from the interlayer film 70. The second main electrode film 122 may be mechanically and electrically connected to the second buried electrode surface 125. According to this configuration, the second buried electrode 121 improves the film formation properties of the second main electrode film 122 with respect to the gate opening 94.

[0416] The semiconductor device 1 may include an n-type first semiconductor region 6, a p-type body region 20, n-type source regions 23 and 24 (first impurity regions), a p-type contact region 25 (second impurity region), channel regions 26 and 27 (channels), and an insulating film 31.

[0417] The first semiconductor region 6 may be formed in a surface layer portion of the first main surface 3. The body region 20 may be formed in a surface layer portion of the first semiconductor region 6. The source regions 23, 24 may be formed in a surface layer portion of the body region 20. The contact region 25 may be formed in a region of the surface layer portion of the body region 20 that is different from the source regions 23, 24.

[0418] The channel regions 26, 27 may be formed in a region between the first semiconductor region 6 and the source regions 23, 24 in a surface layer portion of the body region 20. An insulating film 31 may cover the channel regions 26, 27 on the first main surface 3. In this case, the gate electrode 32 may face the channel regions 26, 27 with the insulating film 31 interposed therebetween. The source opening 90 may expose the source regions 23, 24 and the contact region 25. The first buried electrode 101 may be electrically connected to the source regions 23, 24 and the contact region 25 within the source opening 90.

[0419] The semiconductor device 1 may include a first silicide portion 40 and a first polysilicon portion 41. The first silicide portion 40 may be formed partially on the surface portion of the gate electrode 32. The first polysilicon portion 41 may be formed on the surface portion of the gate electrode 32 in a portion other than the silicide portion. According to this configuration, the wiring resistance (gate resistance) of the gate electrode 32 is reduced by the first silicide portion 40.

[0420] 13 is a schematic diagram showing a wafer 150 used in manufacturing the semiconductor device 1. Referring to FIG. 13, the wafer 150 is a base material of the chip 2 and includes a SiC single crystal. The wafer 150 is formed in a flat disk shape. Of course, the wafer 150 may also be formed in a flat rectangular parallelepiped shape. The wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0421] The first wafer main surface 151 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal. The first wafer main surface 151 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal. The wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.

[0422] The wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal. The mark 154 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 151 in a plan view.

[0423] The mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0424] The wafer 150 includes a first semiconductor region 6 in a region (surface layer portion) on the first wafer main surface 151 side. The first semiconductor region 6 is formed in a layer shape extending along the first wafer main surface 151. In this embodiment, the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).

[0425] The wafer 150 includes a second semiconductor region 7 in a region (surface layer portion) on the second wafer main surface 152 side. The second semiconductor region 7 is formed in a layer extending along the second wafer main surface 152 and is electrically connected to the first semiconductor region 6. In this embodiment, the second semiconductor region 7 is made of the wafer main body (specifically, a SiC wafer). That is, in this embodiment, the wafer 150 is made of an epitaxial wafer (a so-called epiwafer) having a layered structure including the wafer main body and an epitaxial layer.

[0426] For example, a plurality of device regions 155 and a plurality of cutting lines 156 are set on the wafer 150 by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1. Each of the plurality of device regions 155 is set to have a quadrangular shape in a plan view.

[0427] In this embodiment, the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are set at intervals inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 155.

[0428] 14A to 14R are cross-sectional views showing a method for manufacturing the semiconductor device 1. In each of Figures 14A to 14R, a cross section of a part of the active region 8 of one device region 155 is shown.

[0429] 14A, first, the aforementioned wafer 150 is prepared. Next, referring to Fig. 14B, p-type impurities are selectively introduced into a surface layer portion of first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of body regions 20.

[0430] Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming the outer body region 21. Furthermore, n-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of source regions 23, 24.

[0431] Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of contact regions 25. Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a termination region 45. Furthermore, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation using a mask (not shown), thereby forming a plurality of field regions 47.

[0432] The steps of forming the body region 20, the outer body region 21, the source regions 23 and 24, the contact region 25, the termination region 45, and the field region 47 may be performed in any order.

[0433] The formation process of outer body region 21 may be performed simultaneously with the formation process of body region 20. The formation process of termination region 45 may be performed simultaneously with the formation process of body region 20 or outer body region 21. The formation process of field region 47 may be performed simultaneously with the formation process of body region 20, outer body region 21, or termination region 45.

[0434] 14C , a base insulating film 160 is formed to cover the first wafer main surface 151. The base insulating film 160 is a base for the insulating film 31 and the peripheral insulating film 51. The base insulating film 160 may be formed by a chemical vapor deposition (CVD) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0435] 14D , a base electrode 161 is formed on the base insulating film 160. The base electrode 161 is a base for the gate electrode 32 and the gate wiring 52. The base electrode 161 includes conductive polysilicon. The base electrode 161 may be formed by a CVD method. The base electrode 161 has a base electrode surface 162 that extends along the base insulating film 160.

[0436] 14E , a first mask 163 is formed on the base electrode 161 (base electrode surface 162). The first mask 163 is preferably an inorganic mask (i.e., a hard mask). The first mask 163 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first mask 163 is made of a silicon oxide film (insulating film). The first mask 163 may be formed by a CVD method. The first mask 163 may also be formed by an oxidation treatment (e.g., a thermal oxidation treatment) of the base electrode 161.

[0437] 14F, a second mask 164 having a predetermined layout is formed on the first mask 163. The second mask 164 exposes regions on the base electrode surface 162 where the plurality of first silicide portions 40 are to be formed, and covers regions on the base electrode surface 162 where the plurality of first polysilicon portions 41 are to be formed. The second mask 164 also exposes regions on the base electrode surface 162 where the plurality of second silicide portions 60 are to be formed, and covers regions on the base electrode surface 162 where the second polysilicon portions 61 are to be formed.

[0438] Next, unnecessary portions of the first mask 163 are removed by etching through the second mask 164. The etching may be wet etching and / or dry etching. As a result, the first mask 163 having a predetermined layout that selectively exposes the base electrode 161 is formed on the base electrode 161.

[0439] Specifically, the first mask 163 exposes the areas of the base electrode 161 (base electrode surface 162) where multiple first silicide portions 40 and second silicide portions 60 are to be formed, and covers the areas where multiple first polysilicon portions 41 and second polysilicon portions 61 are to be formed.

[0440] In the step of removing the first mask 163, a part (surface portion) of the base electrode 161 (base electrode surface 162) may be partially removed. In this case, recesses corresponding to the first electrode recess 42 and the second electrode recess 43 (see FIG. 10C ) of the gate electrode 32 are formed in the base electrode surface 162. In addition, recesses corresponding to the first wiring recess 62 and the second wiring recess 63 (see FIG. 11C ) of the gate wiring 52 are formed in the base electrode surface 162.

[0441] Of course, the material of the first mask 163, the type of etching process, process conditions, etc. may be adjusted so that a portion of the base electrode surface 162 is not removed. The second mask 164 is removed after the step of removing the first mask 163. The first mask 163 may be made of an organic mask (i.e., a soft mask) instead of an inorganic mask. For example, the first mask 163 may be a resist mask. In these cases, the first mask 163 may be shaped into a predetermined layout through an exposure step and a development step.

[0442] 14G , a metal film 165 is formed to partially cover the base electrode surface 162 of the base electrode 161. The metal film 165 may include at least one of a Ti film, a Ni film, a Co film, a Mo film, and a W film. The metal film 165 may be formed by a sputtering method, a vapor deposition method, or the like. The metal film 165 covers both the base electrode 161 and the first mask 163. The metal film 165 covers a plurality of portions of the base electrode surface 162 of the base electrode 161 that are exposed from the first mask 163.

[0443] Next, referring to FIG. 14H, metal film 165 reacts with polysilicon of base electrode 161 (silicide reaction), and a plurality of portions of base electrode surface 162 in contact with metal film 165 are silicided.

[0444] As a result, a plurality of first silicide portions 40 and second silicide portions 60 are partially formed on the base electrode surface 162. Portions of the base electrode surface 162 other than the first silicide portions 40 and the second silicide portions 60 are formed as polysilicon portions 166. The silicide reaction may be performed by an annealing method such as a rapid thermal annealing (RTA) method.

[0445] In this step, the plurality of first silicide portions 40 may be formed flat with respect to the base electrode surface 162 (polysilicon portion 166) (see FIG. 7 ). In this step, the plurality of first silicide portions 40 may be formed so as to protrude above the base electrode surface 162 (polysilicon portion 166) (see FIG. 10A ).

[0446] In this step, the second silicide portion 60 may be formed flat with respect to the base electrode surface 162 (polysilicon portion 166) (see FIG. 9 ). In this step, the second silicide portion 60 may be formed so as to protrude above the base electrode surface 162 (polysilicon portion 166) (see FIG. 11A ).

[0447] 14I, the unreacted portion of metal film 165 and first mask 163 are removed in this order from base electrode surface 162. Metal film 165 may be removed by etching. The etching may be wet etching and / or dry etching.

[0448] The first mask 163 may be removed by etching. The etching may be wet etching and / or dry etching. If the first mask 163 is made of an organic mask, the first mask 163 may be removed by ashing.

[0449] The plurality of first silicide portions 40 may be partially removed in the step of removing the metal film 165. In this case, the plurality of first silicide portions 40 may be removed until they are positioned on the base insulating film 160 side with respect to the height position of the base electrode surface 162 (polysilicon portion 166) (see FIG. 10B ).

[0450] The second silicide portion 60 may be partially removed in the step of removing the metal film 165. In this case, the second silicide portion 60 may be removed until it is positioned on the base insulating film 160 side with respect to the height position of the base electrode surface 162 (polysilicon portion 166) (see FIG. 11B).

[0451] 14J, a third mask 167 having a predetermined layout is formed on the base electrode 161 (base electrode surface 162). The third mask 167 may be an organic mask (e.g., a resist mask).

[0452] The third mask 167 has a plurality of mask portions 168 that cover regions where the plurality of gate electrodes 32 are to be formed, and has a plurality of openings 169 that expose regions other than the plurality of mask portions 168. Each mask portion 168 is formed wider than the corresponding first silicide portion 40, and partially covers the polysilicon portion 166 on both sides of the first silicide portion 40.

[0453] Specifically, each mask portion 168 has a first covering portion 171, a second covering portion 172, and a third covering portion 173. The first covering portion 171 covers the entire area of ​​the corresponding first silicide portion 40. The second covering portion 172 extends from the first covering portion 171 to one side and covers a part of the polysilicon portion 166 as a region where the first polysilicon portion 41 (41A) is to be formed. The third covering portion 173 extends from the first covering portion 171 to the other side and covers a part of the polysilicon portion 166 as a region where the first polysilicon portion 41 (41B) is to be formed.

[0454] Although specific illustration is omitted, the third mask 167 has a mask portion 168 that covers the region where the gate wiring 52 is to be formed. The mask portion 168 related to the gate wiring 52 is formed wider than the corresponding second silicide portion 60, and partially covers the polysilicon portion 166 on both sides of the second silicide portion 60. In other words, the mask portion 168 related to the gate wiring 52 has a first covering portion 171, a second covering portion 172, and a third covering portion 173, similar to the mask portion 168 related to the gate electrode 32.

[0455] The first covering portion 171 covers the entire second silicide portion 60. The second covering portion 172 extends from the first covering portion 171 to one side and covers a part of the polysilicon portion 166 as a region where the second polysilicon portion 61 (61A) is to be formed. The third covering portion 173 extends from the first covering portion 171 to the other side and covers a part of the polysilicon portion 166 as a region where the second polysilicon portion 61 (61B) is to be formed.

[0456] The plurality of openings 169 are defined in regions between the plurality of mask portions 168. The plurality of openings 169 are formed at intervals from the plurality of first silicide portions 40 and second silicide portions 60, and each exposes a part of the polysilicon portion 166. In other words, the plurality of openings 169 expose only the polysilicon portion 166, and do not expose the plurality of first silicide portions 40 or second silicide portions 60.

[0457] 14K, unnecessary portions of base electrode 161 are removed in the thickness direction. In this process, base electrode 161 is removed by etching using third mask 167. The etching may be wet etching and / or dry etching. Base electrode 161 is removed in the thickness direction from the portion of base electrode surface 162 where polysilicon portion 166 is exposed.

[0458] As a result, a plurality of gate electrodes 32 are formed, each having a first silicide portion 40 and a first polysilicon portion 41 as a part of the polysilicon portion 166. Also, a gate wiring 52 is formed, each having a second silicide portion 60 and a second polysilicon portion 61 as a part of the polysilicon portion 166. After the step of forming the gate electrodes 32 and the gate wiring 52, the third mask 167 is removed.

[0459] In this step, the first silicide portion 40 and the second silicide portion 60 are protected from the etchant by the third mask 167 and are therefore prevented from being etched. That is, in this step, only the polysilicon portion 166 is removed, and the first silicide portion 40 and the second silicide portion 60 are not removed.

[0460] This suppresses metal contamination (metal particle contamination) of other structures on the first wafer main surface 151 and metal contamination (metal particle contamination) of the manufacturing equipment (etching equipment for removing polysilicon) caused by etching the first silicide portion 40 and the second silicide portion 60.

[0461] The step of removing the base electrode 161 may include an over-etching step for the base electrode 161. In the over-etching step, the base electrode 161 is removed until the lower surface of the third mask 167 (mask portion 168) is exposed. The over-etching step is completed before the first silicide portion 40 and the second silicide portion 60 are exposed. That is, in the over-etching step, the etched surface (etching sidewall) of the base electrode 161 is maintained in a state facing the first silicide portion 40 and the second silicide portion 60 with part of the polysilicon sandwiched therebetween.

[0462] 14L, an interlayer film 70 is formed on the first wafer main surface 151. In this step, the interlayer film 70 is formed to have portions that directly cover the electrode surface 33, the first sidewall 34, and the second sidewall 35 of the gate electrode 32. The interlayer film 70 is also formed to have portions that directly cover the wiring surface 53, the first wiring sidewall 54, and the second wiring sidewall 55 of the gate wiring 52.

[0463] In this embodiment, the interlayer film 70 has a stacked structure including a first oxide film 72 and a second oxide film 73. The first oxide film 72 includes a silicon oxide film with no added impurities. The second oxide film 73 includes a silicon oxide film containing phosphorus. The first oxide film 72 may be formed by a CVD method. The second oxide film 73 may be formed by a CVD method. After the step of forming the second oxide film 73, a reflow step (heat treatment step) is performed on the interlayer film 70. This smoothes the corners and rough surfaces of the interlayer film 70.

[0464] 14M, a fourth mask 174 having a predetermined layout is placed on the interlayer film 70. The fourth mask 174 exposes regions where the plurality of source openings 90, the plurality of outer openings 92, and the plurality of gate openings 94 are to be formed, and covers the other regions.

[0465] Next, unnecessary portions of the interlayer film 70 and the base insulating film 160 are removed by etching via the fourth mask 174. In this process, the unnecessary portions of the second oxide film 73, the unnecessary portions of the first oxide film 72, and the unnecessary portions of the base insulating film 160 are removed in this order. The etching method may be wet etching and / or dry etching. The etching method is preferably anisotropic dry etching (e.g., RIE (Reactive Ion Etching)).

[0466] As a result, a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 are formed in the interlayer film 70. In addition, the insulating film 31 and the peripheral insulating film 51 are formed. This process may include the process of forming a plurality of source recesses 91 and the process of forming a plurality of outer recesses 93.

[0467] In this case, a step of further digging down the portions of the first wafer main surface 151 exposed from the source openings 90 and the outer openings 92 toward the second wafer main surface 152 is performed. The fourth mask 174 is then removed. The reflow step (heat treatment step) for the interlayer film 70 described above may be performed after the step of forming the source openings 90, etc.

[0468] 14N, a base underlying electrode film 175 is formed on the interlayer film 70. The base underlying electrode film 175 is a base for the first underlying electrode film 100 and the second underlying electrode film 120. The base underlying electrode film 175 has a laminated structure including a first base electrode film 176 and a second base electrode film 177. The first base electrode film 176 is a base for the first electrode film 103 and the first electrode film 123. The second base electrode film 177 is a base for the second electrode film 104 and the second electrode film 124.

[0469] In this embodiment, the first base electrode film 176 includes a Ti film. The first base electrode film 176 may be formed by sputtering or vapor deposition. The first base electrode film 176 is formed in a film shape along the insulating surface 71 of the interlayer film 70, the wall surfaces of the source openings 90, the wall surfaces of the outer openings 92, and the wall surfaces of the gate openings 94.

[0470] In this embodiment, the second base electrode film 177 includes a TiN film. The second base electrode film 177 may be formed by sputtering or vapor deposition. The second base electrode film 177 is formed in a film shape along the insulating surface 71 of the interlayer film 70, the wall surfaces of the source openings 90, the wall surfaces of the outer openings 92, and the wall surfaces of the gate openings 94.

[0471] After the step of forming the first base electrode film 176, the first base electrode film 176 reacts (silicide reaction) with SiC on the first wafer main surface 151 to form a plurality of first source silicide portions 108 and a plurality of second source silicide portions 111. The silicide reaction may be performed by an annealing method such as an RTA method.

[0472] The step of forming the first source silicide portion 108 (second source silicide portion 111) may be performed prior to the step of forming the second electrode film 104 (second electrode film 124). The step of forming the first source silicide portion 108 (second source silicide portion 111) may be performed after the step of forming the second electrode film 104 (second electrode film 124).

[0473] Of course, the first source silicide portion 108 (second source silicide portion 111) may be formed to include a silicide other than Ti silicide. In this case, prior to the step of forming the first base electrode film 176, a step of silicidating the wafer 150 with a metal film (not shown) is performed. The metal film may include at least one of a Ni film, a Co film, a Mo film, and a W film. The metal film may be formed by sputtering or vapor deposition.

[0474] 14O, a base intermediate electrode film 178 is formed on the base underlying electrode film 175. The base intermediate electrode film 178 includes at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the base intermediate electrode film 178 includes tungsten.

[0475] The base intermediate electrode film 178 may be formed by a CVD method (e.g., a low-pressure CVD method). The base intermediate electrode film 178 backfills the source openings 90, the outer openings 92, and the gate openings 94, and coats the insulating surface 71 of the interlayer film 70 in a film form.

[0476] 14P, an etching method (etch-back method) is used to remove unnecessary portions of the base intermediate electrode film 178. The etching method may be a wet etching method and / or a dry etching method.

[0477] Unnecessary portions of the base intermediate electrode film 178 are removed until the base underlying electrode film 175 is exposed. As a result, a plurality of first buried electrodes 101 are buried in the plurality of source openings 90. In addition, a plurality of first buried electrodes 101 are buried in the plurality of outer openings 92. In addition, a plurality of second buried electrodes 121 are buried in the plurality of gate openings 94.

[0478] The first buried electrode 101 according to the first to fifth examples (see FIGS. 9 and 12A to 12D) is formed in this process by adjusting the amount of etching for the base intermediate electrode film 178. The source intermediate electrode 107 according to the fifth example is formed by omitting the etching treatment for the base intermediate electrode film 178. The source intermediate electrode 107 according to the fifth example can also be formed by completing the etching treatment for the base intermediate electrode film 178 before the base underlying electrode film 175 is exposed.

[0479] 14Q, a base main electrode film 179 is formed on the base underlying electrode film 175, the plurality of first buried electrodes 101, and the plurality of second buried electrodes 121. The base main electrode film 179 is a base for the first main electrode film 102 and the second main electrode film 122.

[0480] The base main electrode film 179 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The base main electrode film 179 may be formed by sputtering or vapor deposition.

[0481] Next, the base main electrode film 179 is divided into the source pad electrode 95, the source finger electrodes 110, the gate finger electrodes 115, and the gate pad electrode 130. In this process, a mask (not shown) having a predetermined layout is formed on the base main electrode film 179. The mask (not shown) covers regions where the source pad electrode 95, the source finger electrodes 110, the gate finger electrodes 115, and the gate pad electrode 130 are to be formed, and leaves regions other than these regions exposed.

[0482] Next, unnecessary portions of the base main electrode film 179 are removed by etching using a mask (not shown). The unnecessary portions of the base main electrode film 179 are removed until the base underlying electrode film 175 is exposed. The etching method may be wet etching and / or dry etching. The mask (not shown) is removed after the etching step of the base main electrode film 179.

[0483] Next, unnecessary portions of the base underlying electrode film 175 are removed by etching via the base main electrode film 179. The unnecessary portions of the base underlying electrode film 175 are removed until the interlayer film 70 (insulating surface 71) is exposed. The process of removing the base underlying electrode film 175 includes a step of removing the second base electrode film 177 by etching and a step of removing the first base electrode film 176 by etching. The etching method may be a wet etching method and / or a dry etching method.

[0484] Of course, unnecessary portions of the base underlying electrode film 175 may be removed by etching through a mask (not shown) in the etching step of the base main electrode film 179. As a result, the source pad electrode 95, the source finger electrodes 110, the gate finger electrodes 115, and the gate pad electrode 130 are formed on the interlayer film 70.

[0485] 12R, a drain pad electrode 140 is formed on the second wafer main surface 152. The drain pad electrode 140 may be formed by sputtering or vapor deposition. Thereafter, the wafer 150 is cut along the cutting lines 156 to cut out a plurality of semiconductor devices 1. The semiconductor device 1 is manufactured through the steps including those described above.

[0486] The following describes modifications of the semiconductor device 1. Fig. 15 is a cross-sectional view showing a first modification of the semiconductor device 1. Fig. 16 is a cross-sectional view showing a second modification of the semiconductor device 1.

[0487] 15 , the semiconductor device 1 does not necessarily have to have the first silicide portion 40 (first polysilicon portion 41) in the gate electrode 32. Similarly, the semiconductor device 1 does not necessarily have to have the second silicide portion 60 (second polysilicon portion 61) in the gate interconnection 52.

[0488] The semiconductor device 1 may have the first silicide portion 40 (first polysilicon portion 41) but may not have the second silicide portion 60 (second polysilicon portion 61). The semiconductor device 1 may have the second silicide portion 60 (second polysilicon portion 61) but may not have the first silicide portion 40 (first polysilicon portion 41).

[0489] 16 , the semiconductor device 1 does not necessarily have to have the first buried electrode 101. In this case, the first main electrode film 102 associated with the source pad electrode 95 extends from above the interlayer film 70 into the plurality of source openings 90 and is electrically connected to the body region 20 and the like within the plurality of source openings 90. The first main electrode film 102 associated with the source finger electrode 110 extends from above the interlayer film 70 into the plurality of outer openings 92 and is electrically connected to the termination region 45 (overlap region 46) within the plurality of outer openings 92.

[0490] Similarly, the semiconductor device 1 does not necessarily have to have the second buried electrode 121. In this case, the gate finger electrode 115 enters the plurality of gate openings 94 from above the interlayer film 70, and is electrically connected to the gate wiring 52 within the plurality of gate openings 94.

[0491] The semiconductor device 1 may have the first buried electrode 101 associated with the source pad electrode 95, but may not have the first buried electrode 101 associated with the source finger electrode 110. The semiconductor device 1 may have the first buried electrode 101 associated with the source finger electrode 110, but may not have the first buried electrode 101 associated with the source pad electrode 95.

[0492] The semiconductor device 1 may have the first buried electrode 101 associated with the source pad electrode 95 but may not have the second buried electrode 121. The semiconductor device 1 may have the second buried electrode 121 but may not have the first buried electrode 101 associated with the source pad electrode 95. The semiconductor device 1 may have the first buried electrode 101 associated with the source finger electrode 110 but may not have the second buried electrode 121. The semiconductor device 1 may have the second buried electrode 121 but may not have the first buried electrode 101 associated with the source finger electrode 110.

[0493] The above-described embodiments (including variations) can be implemented in other forms. For example, the above-described embodiments may have a configuration in which the relationship between the a-axis direction and the m-axis direction is interchanged. A specific configuration in this case can be obtained by interchangeably positioning the "a-axis direction (off-direction)" and the "m-axis direction (direction perpendicular to the off-direction)" in the above description and accompanying drawings.

[0494] In the above-described embodiments, a structure may be adopted in which the conductivity type of the “n-type” semiconductor region is inverted to “p-type” and the conductivity type of the “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0495] In the above-described embodiment, the chip 2 includes a SiC single crystal. However, the chip 2 may include a wide bandgap semiconductor single crystal other than a SiC single crystal. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide bandgap semiconductor single crystals include gallium nitride, gallium oxide, and diamond. Of course, the chip 2 may also include a silicon single crystal.

[0496] Similarly, the first semiconductor region 6 (semiconductor layer) may contain a single crystal of a wide bandgap semiconductor other than SiC single crystal. The first semiconductor region 6 may contain gallium nitride, gallium oxide, diamond, etc. Of course, the first semiconductor region 6 may also contain silicon single crystal.

[0497] Similarly, the second semiconductor region 7 (semiconductor substrate) may contain a single crystal of a wide bandgap semiconductor other than SiC single crystal. The second semiconductor region 7 may contain gallium nitride, gallium oxide, diamond, etc. Of course, the second semiconductor region 7 may also contain silicon single crystal.

[0498] In the above-described embodiment, the n-type second semiconductor region 7 is shown. However, a p-type second semiconductor region 7 may be adopted instead of the n-type second semiconductor region 7. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into a surface layer of the second main surface 4 of the chip 2 (n-type chip 2) by ion implantation.

[0499] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0500] [A1] A semiconductor device (1) comprising: a chip (2) having a main surface (3); a gate electrode (32) arranged on the main surface (3), including polysilicon, and having an electrode surface (33); a silicide portion (40) partially formed on a surface portion of the electrode surface (33); and a polysilicon portion (41) formed on a portion of the surface portion of the electrode surface (33) other than the silicide portion (40).

[0501] [A2] The semiconductor device (1) described in A1, wherein the gate electrode (32) has sidewalls (34, 35), the silicide portion (40) is formed inwardly from the sidewalls (34, 35) at a distance, and the polysilicon portion (41) is exposed from the sidewalls (34, 35).

[0502] [A3] The semiconductor device (1) described in A2, wherein the sidewalls (34, 35) include a first sidewall (34) on one side and a second sidewall (35) on the other side, the silicide portion (40) is formed spaced inward from both the first sidewall (34) and the second sidewall (35), and the polysilicon portion (41) is exposed from both the first sidewall (34) and the second sidewall (35).

[0503] [A4] The semiconductor device (1) described in A3, wherein the silicide portion (40) is formed at an interval inward from both the first side wall (34) and the second side wall (35) over the entire surface area of ​​the electrode surface (33), and the polysilicon portion (41) is exposed from both the first side wall (34) and the second side wall (35) over the entire surface area of ​​the electrode surface (33).

[0504] [A5] The semiconductor device (1) according to any one of A1 to A4, wherein the polysilicon portion (41) forms the flat electrode surface (33) together with the silicide portion (40).

[0505] [A6] The semiconductor device (1) according to any one of A1 to A5, wherein the polysilicon portion (41) is recessed closer to the main surface (3) than the silicide portion (40).

[0506] [A7] The semiconductor device (1) according to any one of A1 to A6, wherein the polysilicon portion (41) protrudes upward beyond the silicide portion (40).

[0507] [A8] The semiconductor device (1) according to any one of A1 to A7, wherein the silicide portion (40) is formed at an interval from the middle of the gate electrode (32) toward the electrode surface (33) in the thickness direction.

[0508] [A9] The semiconductor device (1) according to any one of A1 to A8, further comprising: a gate wiring (52) selectively routed on the main surface (3) to be connected to the gate electrode (32), containing polysilicon and having a wiring surface (53); a second silicide portion (60) formed on a surface portion of the wiring surface (53); and a second polysilicon portion (61) formed on a portion of the surface portion of the wiring surface (53) outside the second silicide portion (60).

[0509] [A10] The semiconductor device (1) described in A9, wherein the second silicide portion (60) is connected to the silicide portion (40) at the connection portion of the gate electrode (32) and the gate wiring (52), and the second polysilicon portion (61) is connected to the polysilicon portion (41) at the connection portion.

[0510] [A11] The semiconductor device (1) described in A9 or A10, wherein the gate wiring (52) has wiring sidewalls (54, 55), the second silicide portion (60) is formed at a distance inward from the wiring sidewalls (54, 55), and the second polysilicon portion (61) is exposed from the wiring sidewalls (54, 55).

[0511] [A12] The semiconductor device (1) according to A11, wherein the wiring sidewalls (54, 55) include a first wiring sidewall (54) on one side and a second wiring sidewall (55) on the other side, the second silicide portion (60) is formed spaced inward from both the first wiring sidewall (54) and the second wiring sidewall (55), and the second polysilicon portion (61) is exposed from both the first wiring sidewall (54) and the second wiring sidewall (55).

[0512] [A13] The semiconductor device (1) according to any one of A9 to A12, wherein the gate electrode (32) extends in one direction (Y), and the gate wiring (52) has a portion extending in an intersecting direction (X) that intersects with the one direction (Y).

[0513] [A14] The semiconductor device (1) according to any one of A1 to A13, further comprising an interlayer film (70) covering the gate electrode (32) and having a portion in contact with the silicide portion (40) and a portion in contact with the polysilicon portion (41).

[0514] [A15] The semiconductor device (1) according to A14, wherein the interlayer film (70) includes a first oxide film (72) containing no impurities and having a portion in contact with the silicide portion (40) and a portion in contact with the polysilicon portion (41), and a second oxide film (73) containing phosphorus and covering the first oxide film (72).

[0515] [A16] The semiconductor device (1) according to any one of A1 to A15, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a body region (20) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6); impurity regions (23, 24) of the first conductivity type (n-type) formed in a surface layer portion of the body region (20); channels (26, 27) formed in a region between the semiconductor region (6) and the impurity regions (23, 24) in the surface layer portion of the body region (20); and an insulating film (31) covering the channels (26, 27) on the main surface (3), wherein the gate electrode (32) faces the channels (26, 27) across the insulating film (31).

[0516] [A17] The semiconductor device (1) according to any one of A1 to A16, wherein the chip (2) includes a wide band gap semiconductor.

[0517] [A18] A method for manufacturing a semiconductor device (1), comprising the steps of: forming a base electrode (161) containing polysilicon on a wafer (150); forming a metal film (165) that partially covers an electrode surface (162) of the base electrode (161); reacting the polysilicon with the metal film (165) to partially form a silicide portion (40) on the surface of the electrode surface (162); removing an unreacted portion of the metal film (165) from the electrode surface (162); and removing the base electrode (161) in the thickness direction from a polysilicon portion (166) outside the silicide portion (40), to form a gate electrode (32) having both the silicide portion (40) and the polysilicon portion (41, 166) on the surface of the electrode surface (33, 162).

[0518] [A19] A method for manufacturing a semiconductor device (1) according to A18, further comprising, prior to the step of forming the metal film (165), a step of forming a base mask (163) on the base electrode (161) that selectively exposes the base electrode (161), the step of forming the metal film (165) comprising a step of forming the metal film (165) that covers both the base electrode (161) and the base mask (163), and the step of forming the silicide portion (40) comprising a step of reacting the metal film (165) with the portion of the polysilicon exposed from the base mask (163).

[0519] [A20] A method for manufacturing a semiconductor device (1) according to A18 or A19, wherein the step of removing the base electrode (161) includes a step of removing only the polysilicon portion (166).

[0520] [A21] A method for manufacturing a semiconductor device (1) according to any one of A18 to A20, wherein the step of removing the base electrode (161) includes the steps of forming a mask (167) on the base electrode (161) that covers the silicide portion (40) and exposes the polysilicon portion (166), and removing the polysilicon portion (166) by an etching method using the mask (167).

[0521] [A22] A method for manufacturing a semiconductor device (1) according to any one of A18 to A21, wherein the wafer (150) includes a wide band gap semiconductor.

[0522] [B1] A semiconductor device (1) comprising: a chip (2) having a principal surface (3); a gate electrode (32) arranged on the principal surface (3); an interlayer film (70) covering the gate electrode (32) and having an insulating surface (71); an opening (90) formed in the interlayer film (70) spaced apart from the gate electrode (32) and exposing the principal surface (3); a buried electrode (101) buried in the opening (90), having an electrode surface (105) exposed from the opening (90), and electrically connected to the principal surface (3); and a main electrode (102) mechanically and electrically connected to the electrode surface (105) of the buried electrode (101).

[0523] [B2] The semiconductor device (1) described in B1, wherein the buried electrode (101) is buried in the opening (90) so as to expose the insulating surface (71), and the main electrode (102) covers both the insulating surface (71) and the electrode surface (105).

[0524] [B3] The semiconductor device (1) according to B2, wherein the electrode surface (105) is positioned closer to the main surface (3) than the insulating surface (71), and the main electrode (102) is connected to the electrode surface (105) on the main surface (3) side than the insulating surface (71).

[0525] [B4] The semiconductor device (1) according to B3, wherein the gate electrode (32) has a gate electrode surface (33), and the electrode surface (105) is positioned above the gate electrode surface (33).

[0526] [B5] The semiconductor device (1) according to any one of B2 to B4, wherein the electrode surface (105) has a recess (106) facing the chip (2).

[0527] [B6] The semiconductor device (1) according to B5, wherein the bottom of the recess (106) is positioned above the height position of the gate electrode (32).

[0528] [B7] The semiconductor device (1) according to any one of B1 to B6, wherein the opening (90) has an aspect ratio (D / W) of its length along the stacking direction.

[0529] [B8] The semiconductor device (1) according to any one of B1 to B7, wherein the buried electrode (101) contains tungsten and the main electrode (102) contains aluminum.

[0530] [B9] The semiconductor device (1) according to any one of B1 to B8, wherein the interlayer film (70) includes a first oxide film (72) with no added impurities that covers the gate electrode (32), and a second oxide film (73) that contains phosphorus and covers the first oxide film (72), and the opening (90) penetrates both the first oxide film (72) and the second oxide film (73).

[0531] [B10] A semiconductor device (1) according to any one of B1 to B9, further comprising a plurality of the gate electrodes (32) arranged at intervals on the main surface (3), and the opening (90) is defined in a region between the plurality of the gate electrodes (32).

[0532] [B11] The semiconductor device (1) according to any one of B1 to B10, further comprising an underlying electrode film (100) covering the wall surface of the opening (90) and having a portion electrically connected to the main surface (3), wherein the buried electrode (101) is buried in the opening (90) across the underlying electrode film (100) and is electrically connected to the main surface (3) via the underlying electrode film (100).

[0533] [B12] The semiconductor device (1) described in B11, wherein the base electrode film (100) has a portion covering the insulating surface (71) outside the opening (90), and the main electrode (102) has a portion covering the insulating surface (71) across the base electrode film (100).

[0534] [B13] The semiconductor device (1) according to B11 or 12, further comprising a surface silicide portion (108) formed on the surface portion of the main surface (3) exposed from the opening (90) and mechanically and electrically connected to the underlying electrode film (100).

[0535] [B14] A semiconductor device (1) according to any one of B11 to B13, further comprising a recess (91) formed in a portion of the main surface (3) exposed from the opening (90), and the underlying electrode film (100) has a portion located within the recess (91).

[0536] [B15] The semiconductor device (1) according to any one of B11 to B14, wherein the underlying electrode film (100) includes at least one of a Ti film and a TiN film.

[0537] [B16] The semiconductor device (1) according to any one of B1 to B15, further comprising a gate wiring (52) selectively routed on the main surface (3) and connected to the gate electrode (32).

[0538] [B17] The semiconductor device (1) according to B16, further comprising: a gate opening (94) formed in the interlayer film (70) so as to expose the gate wiring (52); a gate buried electrode (121) buried in the gate opening (94), having a gate buried electrode surface (125) exposed from the gate opening (94), and electrically connected to the gate wiring (52); and a gate main electrode (122) mechanically and electrically connected to the gate buried electrode surface (125) of the gate buried electrode (121).

[0539] [B18] A semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3), a body region (20) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6), impurity regions (23, 24) of the first conductivity type (n-type) formed in a surface layer portion of the body region (20), and a channel (2) formed in a region between the semiconductor region (6) and the impurity regions (23, 24) in the surface layer portion of the body region (20). The semiconductor device (1) according to any one of B1 to B17, further comprising: a gate electrode (32) facing the channel (26, 27) across the insulating film (31) and the channel (26, 27) on the main surface (3); the gate electrode (32) facing the channel (26, 27) across the insulating film (31); the opening (90) exposing the impurity region (23, 24); and the buried electrode (101) electrically connected to the impurity region (23, 24) within the opening (90).

[0540] [B19] The semiconductor device (1) described in B18 further includes a second impurity region (25) of a second conductivity type (p-type) formed in a surface portion of the body region (20) in a region different from the impurity regions (23, 24), the opening (90) exposing the second impurity region (25), and the buried electrode (101) electrically connected to the second impurity region (25) within the opening (90).

[0541] [B20] The semiconductor device (1) according to any one of B1 to B19, further comprising: a silicide portion (40) partially formed on a surface portion of the gate electrode (32); and a polysilicon portion (41) formed on a portion of the surface portion of the gate electrode (32) other than the silicide portion (40).

[0542] [B21] The semiconductor device (1) according to any one of B1 to B20, wherein the chip (2) includes a wide band gap semiconductor.

[0543] [B22] A method for manufacturing a semiconductor device (1), comprising the steps of: forming a gate electrode (32) on a wafer (150); forming an interlayer film (70) on the wafer (150) to cover the gate electrode (32); forming an opening (90) in the interlayer film (70) to expose the wafer (150) at a position spaced from the gate electrode (32); burying an electrode (178) in the opening (90) so as to be electrically connected to the wafer (150), thereby forming a buried electrode (101) having an electrode surface (105) exposed from the opening (90); and forming a main electrode (102) that directly covers the electrode surface (105) of the buried electrode (101).

[0544] [B23] A method for manufacturing a semiconductor device (1) according to B22, wherein the wafer (150) includes a wide band gap semiconductor.

[0545] The configurations according to [A1] to [A22] and the configurations according to [B1] to [B23] can be appropriately combined with each other. Specific embodiments have been described in detail above, but these are merely examples that clearly show the technical content. Various technical ideas extracted from this specification can be appropriately combined with each other without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0546] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 6 first semiconductor region 20 body region 23 first source region (impurity region) 24 second source region (impurity region) 26 first channel region 27 second channel region 31 insulating film 32 gate electrode 33 electrode surface 34 first sidewall 35 second sidewall 40 first silicide portion 41 first polysilicon portion 52 gate wiring 53 wiring surface 54 first wiring sidewall 55 second wiring sidewall 60 second silicide portion 61 second polysilicon portion 70 interlayer film 71 insulating surface 72 first oxide film 73 second oxide film 90 source opening 91 source recess 94 gate opening 100 first base electrode film (source base electrode film) 101 first buried electrode (source buried electrode) 102 first main electrode film (source main electrode film) 105 First buried electrode surface (source buried electrode surface) 106 Recess 108 First source silicide portion (surface silicide portion) 120 Second underlying electrode film (gate underlying electrode film) 121 Second buried electrode (gate buried electrode) 122 Second main electrode (gate main electrode film) 125 Second buried electrode surface (gate buried electrode surface) 150 Wafer 161 Base electrode 163 First mask 165 Metal film 166 Polysilicon portion 167 Third mask X First direction Y Second direction

Claims

1. a chip including SiC and having a main surface; a gate electrode disposed on the main surface, the gate electrode including polysilicon and having an electrode surface; a silicide portion partially formed on a surface portion of the electrode surface; a polysilicon portion formed on a surface portion of the electrode surface other than the silicide portion.

2. the gate electrode has a sidewall; the silicide portion is formed inwardly from the sidewall at a spaced interval, The semiconductor device according to claim 1 , wherein said polysilicon portion is exposed from said sidewall.

3. the side walls include a first side wall on one side and a second side wall on the other side; the silicide portion is formed inwardly from both the first sidewall and the second sidewall at a spaced interval; The semiconductor device according to claim 2 , wherein said polysilicon portion is exposed from both said first sidewall and said second sidewall.

4. the silicide portion is formed over the entire surface of the electrode surface at a distance inward from both the first side wall and the second side wall, 4. The semiconductor device according to claim 3, wherein said polysilicon portion is exposed from both said first sidewall and said second sidewall over the entire surface of said electrode surface.

5. 2. The semiconductor device according to claim 1, wherein said polysilicon portion and said silicide portion form a flat electrode surface.

6. 2. The semiconductor device according to claim 1, wherein said polysilicon portion is recessed toward said main surface side relative to said silicide portion.

7. 2. The semiconductor device according to claim 1, wherein said polysilicon portion protrudes upward beyond said silicide portion.

8. 2. The semiconductor device according to claim 1, wherein said silicide portion is formed at an interval from a middle portion of said gate electrode toward said electrode surface in the thickness direction.

9. a gate wiring line that is selectively routed on the main surface to be connected to the gate electrode, the gate wiring line including polysilicon and having a wiring surface; a second silicide portion formed on a surface portion of the wiring surface; 9. The semiconductor device according to claim 1, further comprising: a second polysilicon portion formed on a surface portion of said wiring surface outside said second silicide portion.

10. the second silicide portion is connected to the silicide portion at a connection portion between the gate electrode and the gate wiring; 10. The semiconductor device according to claim 9, wherein said second polysilicon portion is connected to said polysilicon portion at said connection portion.

11. the gate wiring has a wiring sidewall; the second silicide portion is formed inwardly from the wiring sidewall with a space therebetween, 10. The semiconductor device according to claim 9, wherein said second polysilicon portion is exposed from said wiring sidewall.

12. the wiring sidewalls include a first wiring sidewall on one side and a second wiring sidewall on the other side; the second silicide portion is formed at an interval inward from both the first wiring sidewall and the second wiring sidewall, 12. The semiconductor device according to claim 11, wherein said second polysilicon portion is exposed from both said first wiring sidewall and said second wiring sidewall.

13. The gate electrode extends in one direction, 10. The semiconductor device according to claim 9, wherein said gate wiring has a portion extending in an intersecting direction intersecting said one direction.

14. 9. The semiconductor device according to claim 1, further comprising an interlayer film covering said gate electrode and having a portion in contact with said silicide portion and a portion in contact with said polysilicon portion.

15. 15. The semiconductor device according to claim 14, wherein said interlayer film includes a first oxide film to which no impurities are added, said first oxide film having a portion in contact with said silicide portion and a portion in contact with said polysilicon portion, and a second oxide film containing phosphorus and covering said first oxide film.

16. a first conductivity type semiconductor region formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the semiconductor region; an impurity region of a first conductivity type formed in a surface layer portion of the body region; a channel formed in a region between the semiconductor region and the impurity region in a surface layer portion of the body region; an insulating film covering the channel on the main surface, 9. The semiconductor device according to claim 1, wherein the gate electrode faces the channel with the insulating film interposed therebetween.

17. forming a base electrode comprising polysilicon on a wafer comprising SiC; forming a metal film that partially covers an electrode surface of the base electrode; a step of reacting the polysilicon with the metal film to partially form a silicide portion on a surface of the electrode surface; removing unreacted portions of the metal film from the electrode surface; removing the base electrode in a thickness direction from the polysilicon portion outside the silicide portion, and forming a gate electrode having both the silicide portion and the polysilicon portion on the surface portion of the electrode surface.

18. The method further includes, prior to the step of forming the metal film, forming a base mask on the base electrode to selectively expose the base electrode; the forming of the metal film includes forming the metal film to cover both the base electrode and the base mask; 18. The method for manufacturing a semiconductor device according to claim 17, wherein said step of forming said silicide portion includes the step of reacting said metal film with a portion of said polysilicon exposed from said base mask.

19. 18. The method for manufacturing a semiconductor device according to claim 17, wherein said step of removing said base electrode includes the step of removing only said polysilicon portion.

20. The base electrode removing step includes: forming a mask over the base electrode, covering the silicide portion and exposing the polysilicon portion; The method for manufacturing a semiconductor device according to any one of claims 17 to 19, further comprising the step of removing the polysilicon portion by etching using the mask.