Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a first conductivity-type high-concentration region that is formed in a surface layer section of the main surface on the inner-part side of the chip; and a first conductivity-type low-concentration region that is formed in the surface layer section of the main surface on the peripheral edge-side of the chip, and that has an impurity concentration lower than the impurity concentration of the high concentration region.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-056618 filed with the Japan Patent Office on March 30, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2008 / 0277669A1) discloses a semiconductor device having a termination structure in the outer peripheral region of a drift layer.

[0003] US Patent Application Publication No. 2008 / 0277669

[0004] [Summary] The present disclosure provides a semiconductor device having a novel configuration.

[0005] The present disclosure provides a semiconductor device including a chip having a main surface, a high concentration region of a first conductivity type formed in a surface layer portion of the main surface on an inner side of the chip, and a low concentration region of the first conductivity type formed in a surface layer portion of the main surface on a peripheral side of the chip, the low concentration region having an impurity concentration lower than the impurity concentration of the high concentration region.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; an active region provided in an inner portion of the main surface; a peripheral region provided on a peripheral edge of the main surface; a high-concentration region of a first conductivity type formed in a surface layer portion of the main surface in the active region; and a low-concentration region of the first conductivity type formed in the surface layer portion of the main surface in the peripheral region, the low-concentration region having an impurity concentration lower than the impurity concentration of the high-concentration region.

[0007] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view obtained by removing structures outside the chip from the cross-sectional view shown in FIG. 2. FIG. 4 is a plan view showing an example layout of a first main surface. FIG. 5 is a plan view showing an example layout of a high-concentration region and a low-concentration region. FIG. 6 is an enlarged plan view showing a main portion of the first main surface. FIG. 7 is an enlarged plan view showing further main portions of the first main surface. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. FIG. 9 is an enlarged cross-sectional view showing a main portion of FIG. 8. FIG. 10 is a cross-sectional view taken along line XX in FIG. 7. FIG. 11 is an enlarged cross-sectional view showing a main portion of FIG. 10. FIG. 12 is a cross-sectional view showing a main portion of a semiconductor device according to a second embodiment. FIG. 13 is a cross-sectional view showing a main portion of a semiconductor device according to a third embodiment. FIG. 14 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 13. FIG. 15 is a cross-sectional view showing a main portion of a semiconductor device according to a fourth embodiment. FIG. 16 is an enlarged plan view showing a main portion of a semiconductor device according to a fifth embodiment. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16. FIG. 18 is a plan view showing a semiconductor device according to a sixth embodiment. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18. FIG. 20 is a cross-sectional view showing a semiconductor device according to a seventh embodiment. FIG. 21 is a cross-sectional view showing a semiconductor device according to an eighth embodiment. FIG. 22 is a cross-sectional view showing a semiconductor device according to a ninth embodiment. FIG. 23 is a cross-sectional view showing a modified outer body region. FIG. 24 is a cross-sectional view showing a modified field region. FIG. 25 is a cross-sectional view showing a first modified source pad electrode. FIG. 26 is a cross-sectional view showing a second modified source pad electrode.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a cross-sectional view obtained by removing structures outside the chip 2 from the cross-sectional view shown in Fig. 2. Fig. 4 is a plan view showing an example layout of a first main surface 3. Fig. 5 is a plan view showing an example layout of a high concentration region 10 and a low concentration region 11.

[0013] Fig. 6 is an enlarged plan view showing a main portion of the first main surface 3. Fig. 7 is an enlarged plan view showing further main portions of the first main surface 3. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 7. Fig. 9 is an enlarged cross-sectional view showing the main portion of Fig. 8. Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 7. Fig. 11 is an enlarged cross-sectional view showing the main portion of Fig. 10.

[0014] 1 to 11, semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip."

[0015] In this embodiment, the chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0020] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off-axis direction by the off-axis angle. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off-axis angle.

[0021] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0022] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0023] In this embodiment, the chip 2 has a stacked structure including a first semiconductor layer 6 and a second semiconductor layer 7. The first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the off direction and off angle described above. The first semiconductor layer 6 forms the second main surface 4 and forms parts of the first to fourth side surfaces 5A to 5D.

[0024] The first semiconductor layer 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0025] The second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and is stacked on the first semiconductor layer 6. The second semiconductor layer 7 has the off direction and off angle described above. The second semiconductor layer 7 forms the first main surface 3 and forms parts of the first to fourth side surfaces 5A to 5D. The second semiconductor layer 7 preferably has a thickness less than that of the first semiconductor layer 6. Of course, the thickness of the second semiconductor layer 7 may be greater than the thickness of the first semiconductor layer 6.

[0026] The thickness of the second semiconductor layer 7 may be 5 μm or more and 50 μm or less. The thickness of the second semiconductor layer 7 may have a value belonging to at least one of the ranges of 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or more and 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more, and 45 μm or more and 50 μm or less.

[0027] The semiconductor device 1A includes an active region 8 set on the chip 2 (first main surface 3). The active region 8 is set in an inner portion of the chip 2 (first main surface 3). The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.

[0028] The active region 8 is set in the interior of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view. The plane area of ​​the active region 8 is preferably 50% to 90% of the plane area of ​​the first main surface 3.

[0029] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set in the peripheral portion of the chip 2 (first main surface 3). That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in a planar view. The peripheral region 9 extends in a strip shape along the active region 8 in a planar view, and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0030] The semiconductor device 1A has a relatively high first impurity concentration and includes an n-type high-concentration region 10 formed in a surface layer portion of the first main surface 3. A drain potential as a high potential (first potential) is applied to the high-concentration region 10. The high-concentration region 10 may also be referred to as a "first region," a "first drift region," a "first high-concentration drift region," or the like. The first impurity concentration is 1×10 １６ cm －３ 5x10 or more １７ cm －３ It may be the following:

[0031] The high concentration region 10 is formed on the inner side of the chip 2. Specifically, the high concentration region 10 is formed in the surface layer of the first main surface 3 in the active region 8, and extends in a layer shape along the first main surface 3. The high concentration region 10 is formed as a low resistance region (first low resistance region) having a relatively low resistance value in the active region 8. The high concentration region 10 is preferably formed throughout the entire active region 8. The high concentration region 10 may extend approximately perpendicular to the first main surface 3 in a cross-sectional view.

[0032] In this embodiment, the high concentration region 10 extends from the active region 8 to the peripheral region 9, and has a portion in the peripheral region 9 that is located in a surface layer portion of the first main surface 3. The high concentration region 10 extends from the active region 8 to the peripheral region 9 along the entire periphery, and is formed at an interval inward from the periphery of the first main surface 3.

[0033] The high concentration region 10 is preferably formed at a distance inward from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the high concentration region 10 is formed at a distance inward from the entire periphery of the first to fourth side surfaces 5A to 5D, and has a peripheral portion surrounding the active region 8.

[0034] In this embodiment, the high concentration region 10 is formed in the second semiconductor layer 7. For example, the high concentration region 10 may be formed by introducing an n-type impurity into a surface layer portion of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7). The high concentration region 10 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 with a part of the second semiconductor layer 7 in between.

[0035] The high concentration region 10 is preferably formed at a distance from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface. In other words, the thickness of the high concentration region 10 is preferably less than half the thickness of the second semiconductor layer 7. Of course, the high concentration region 10 may cross the depth position of the intermediate portion of the second semiconductor layer 7 in the thickness direction. In other words, the thickness of the high concentration region 10 may be greater than half the thickness of the second semiconductor layer 7.

[0036] The high-concentration region 10 may have a thickness of 0.1 μm or more and 5 μm or less. The thickness of the high-concentration region 10 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or more, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or more, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0037] The semiconductor device 1A includes an n-type low-concentration region 11 formed in a surface layer portion of the first main surface 3 and having a second impurity concentration lower than the first impurity concentration of the high-concentration region 10. The low-concentration region 11 may be referred to as a "second region," a "second drift region," a "first low-concentration drift region," or the like. The second impurity concentration is 1×10 １５ cm －３ 5x10 or more １６ cm －３It may be the following:

[0038] The low concentration region 11 is formed closer to the peripheral edge of the chip 2 than the high concentration region 10. Specifically, the low concentration region 11 is formed in the surface layer of the first main surface 3 in the outer periphery region 9, and extends in a layer form along the first main surface 3. The low concentration region 11 is located in the region between the periphery of the first main surface 3 and the high concentration region 10. The low concentration region 11 is formed in the outer periphery region 9 as a high resistance region (first high resistance region) having a higher resistance value than the high concentration region 10.

[0039] The low-concentration region 11 extends in a band shape along the high-concentration region 10 (active region 8) in a plan view. The low-concentration region 11 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and partitions the high-concentration region 10 (active region 8) from multiple directions. In this embodiment, the low-concentration region 11 is formed in a ring shape (specifically, a quadrangular ring shape) surrounding the high-concentration region 10 (active region 8) in a plan view.

[0040] The low-concentration region 11 has an inner edge portion on the inward side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the low-concentration region 11 is connected to the peripheral edge portion of the high-concentration region 10. This electrically connects the low-concentration region 11 to the high-concentration region 10. In this embodiment, the low-concentration region 11 is connected to the high-concentration region 10 in the outer circumferential region 9. It is preferable that the outer edge portion of the low-concentration region 11 is exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the outer edge portion of the low-concentration region 11 is exposed from all of the first to fourth side surfaces 5A to 5D.

[0041] In this embodiment, the low-concentration region 11 crosses the depth position of the bottom of the high-concentration region 10 in the thickness direction and is formed deeper than the high-concentration region 10. In other words, the low-concentration region 11 has a bottom located lower (closer to the second main surface 4) than the bottom of the high-concentration region 10. The low-concentration region 11 and the high-concentration region 10 form a region boundary 12 extending in the thickness direction of the chip 2 (see FIG. 10 ). In this embodiment, the region boundary 12 is formed at a distance from the bottom of the low-concentration region 11 toward the first main surface 3.

[0042] The region boundary 12 is formed substantially perpendicular to the first main surface 3. Specifically, the region boundary 12 has an upper end, a lower end, and an extending portion. The upper end is located on the first main surface 3 side. The lower end is located on the second main surface 4 side and is located substantially on the same straight line as the upper end in the thickness direction. The extending portion extends substantially perpendicular to the first main surface 3 between the upper end and the lower end.

[0043] In this embodiment, the low concentration region 11 is formed in the second semiconductor layer 7. The low concentration region 11 preferably traverses the middle depth position of the second semiconductor layer 7 in the thickness direction. In other words, the thickness of the low concentration region 11 is preferably equal to or greater than half the thickness of the second semiconductor layer 7. In this embodiment, the low concentration region 11 is formed in the second semiconductor layer 7 throughout the entire thickness range between the first main surface 3 and the bottom of the second semiconductor layer 7 (first semiconductor layer 6), and is connected to the first semiconductor layer 6.

[0044] For example, the high concentration region 10 may be formed by introducing an n-type impurity into a surface layer portion of the second semiconductor layer 7 (e.g., an n-type second semiconductor layer 7). In this embodiment, the low concentration region 11 is formed by utilizing the n-type second semiconductor layer 7, and has a thickness corresponding to the thickness of the second semiconductor layer 7. In this embodiment, the semiconductor device 1A has a single layer structure made up of the low concentration region 11 in the peripheral portion (peripheral region 9) of the second semiconductor layer 7.

[0045] The semiconductor device 1A includes an n-type inner low-concentration region 13 formed in a region below the high-concentration region 10 in the surface layer portion of the first main surface 3. The inner low-concentration region 13 may be referred to as a "third region," a "third drift region," a "second low-concentration drift region," or the like. The third impurity concentration is 1×10 １５ cm －３ 5x10 or more １６ cm －３ It may be the following:

[0046] The inner low-concentration region 13 is formed on the inner side of the chip 2 relative to the low-concentration region 11. Specifically, the inner low-concentration region 13 is formed in a region below the high-concentration region 10 in the active region 8. The inner low-concentration region 13 is formed as a high-resistance region (second high-resistance region) in the active region 8 that has a higher resistance value than the high-concentration region 10. The inner low-concentration region 13 extends in a layered form along the high-concentration region 10 and is connected to the high-concentration region 10 in the thickness direction. As a result, the inner low-concentration region 13 is electrically connected to the high-concentration region 10.

[0047] The inner low-concentration region 13 is preferably formed over the entire region below the high-concentration region 10 and connected to the entire high-concentration region 10 in the thickness direction. In this embodiment, the inner low-concentration region 13 is formed over the entire active region 8. The inner low-concentration region 13 is further extended from the active region 8 to the peripheral region 9, where it is connected to a region on the bottom side of the low-concentration region 11.

[0048] As a result, the inner low-concentration region 13 is electrically connected to the low-concentration region 11. In this embodiment, the inner low-concentration region 13 is drawn out from the active region 8 to the outer peripheral region 9 along the entire periphery, and is connected to the inner edge of the low-concentration region 11 along the entire periphery. It is preferable that the third impurity concentration of the inner low-concentration region 13 is approximately equal to the second impurity concentration of the region on the bottom side of the low-concentration region 11.

[0049] In this embodiment, the inner low-concentration region 13 is formed in the second semiconductor layer 7. The inner low-concentration region 13 is formed in the second semiconductor layer 7 throughout the thickness range between the high-concentration region 10 and the bottom of the second semiconductor layer 7 (the first semiconductor layer 6), and is connected to the first semiconductor layer 6.

[0050] For example, the inner low-concentration region 13 may be formed by introducing an n-type impurity into a surface layer portion of the second semiconductor layer 7 (e.g., the n-type second semiconductor layer 7). In this embodiment, the inner low-concentration region 13 is formed by utilizing a part (a region on the bottom side) of the n-type second semiconductor layer 7. The semiconductor device 1A has a multilayer structure including the high-concentration region 10 and the inner low-concentration region 13 in the inner part (active region 8) of the second semiconductor layer 7.

[0051] The semiconductor device 1A includes an n-type base region 14 formed in a region (surface layer) on the second main surface 4 side of the chip 2. The base region 14 may also be referred to as a "fourth region," a "drain region," or the like. The base region 14 has a fourth impurity concentration higher than the first impurity concentration of the high-concentration region 10. The fourth impurity concentration is 5×10 １７ cm －３ 3x10 or more １９ cm －３ It may be the following:

[0052] The base region 14 is formed in a region below the high concentration region 10 on the inner side of the chip 2 and is electrically connected to the high concentration region 10. The base region 14 extends from the region below the high concentration region 10 to the peripheral side of the chip 2 and has a portion located in a region below the low concentration region 11. The base region 14 is electrically connected to the low concentration region 11 on the peripheral side of the chip 2.

[0053] That is, the base region 14 has a portion that is electrically connected to the high concentration region 10 in the active region 8. In this embodiment, the base region 14 is connected to the inner low concentration region 13 in the active region 8, and is electrically connected to the high concentration region 10 via the inner low concentration region 13. The base region 14 also has a portion that is drawn out from the active region 8 to the peripheral region 9, and is electrically connected to the low concentration region 11 in the peripheral region 9. The base region 14 is formed as a low resistance region that has a relatively low resistance value in both the active region 8 and the peripheral region 9.

[0054] The base region 14 extends in a layer shape along the second main surface 4, is exposed from the second main surface 4 of the chip 2, and is exposed from parts of the first side surfaces 5A to 5D of the chip 2. The base region 14 has a thickness greater than the thickness of the high concentration region 10, the thickness of the low concentration region 11, and the thickness of the inner low concentration region 13.

[0055] In this embodiment, the base region 14 is formed in the first semiconductor layer 6. The base region 14 is formed throughout the thickness range between the lower end (second major surface 4) of the first semiconductor layer 6 and the upper end (second semiconductor layer 7) of the first semiconductor layer 6, and is connected to the second semiconductor layer 7. In this embodiment, the base region 14 is formed using the n-type first semiconductor layer 6, and has a thickness corresponding to the thickness of the first semiconductor layer 6.

[0056] The semiconductor device 1A includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 in the active region 8. The plurality of body regions 20 are formed in a surface layer portion of the high-concentration region 10. A source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential).

[0057] The body regions 20 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the body regions 20 are arranged in stripes extending in the second direction Y. The extending direction of the body regions 20 also coincides with the off-direction of the SiC single crystal.

[0058] The body regions 20 are formed at intervals from the bottom of the high-concentration region 10 toward the first main surface 3, and face the inner low-concentration region 13 (base region 14) across a part of the high-concentration region 10. The body regions 20 are preferably formed at intervals from the middle of the high-concentration region 10 toward the first main surface 3. Of course, the body regions 20 may cross the depth position of the middle of the high-concentration region 10 in the thickness direction. The body regions 20 are exposed from the first main surface 3.

[0059] The body regions 20 may each have a width of 1 μm to 10 μm. The width of the body regions 20 may be a value belonging to at least one of the following ranges: 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the body region 20 is preferably 2 μm to 5 μm.

[0060] Each of the body regions 20 may have a thickness (depth) of 0.1 μm to 2.5 μm. The thickness of the body region 20 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, and 2 μm to 2.5 μm. The thickness of the body region 20 is preferably 0.5 μm to 1.5 μm.

[0061] The body regions 20 each form a pn junction (pn junction diode: body diode) with the high-concentration region 10. The body regions 20 spread a depletion layer into the high-concentration region 10 when a reverse bias voltage is applied to the pn junction. The depletion layer spreads from the high-concentration region 10 side toward the low-concentration region 11 side in the horizontal direction along the first main surface 3.

[0062] That is, the range of the depletion layer is expanded toward the peripheral edge of the chip 2 by the low concentration region 11. In the case of a device structure having a vertical structure, a lateral breakdown voltage is required on the peripheral edge side (peripheral region 9 side) of the chip 2. In this regard, the low concentration region 11 increases the breakdown voltage on the peripheral edge side (peripheral region 9 side) of the chip 2, thereby improving the breakdown voltage.

[0063] In this configuration, the depletion layer extends from the high concentration region 10 to the inner low concentration region 13 in the thickness direction of the chip 2. In other words, the range of the depletion layer is expanded by the inner low concentration region 13. In the case of a device structure having a vertical structure, a vertical breakdown voltage is required on the inner side (active region 8) of the chip 2. In this regard, the inner low concentration region 13 increases the breakdown voltage on the inner side (active region 8) of the chip 2, thereby improving the breakdown voltage.

[0064] The semiconductor device 1A includes a p-type outer body region 21 formed in a surface layer portion of the first main surface 3 in the peripheral region 9. The outer body region 21 is formed in one or both of the surface layer portion of the high concentration region 10 and the surface layer portion of the low concentration region 11. In this embodiment, the outer body region 21 is formed in the surface layer portion of the high concentration region 10.

[0065] The outer body region 21 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the outer body region 21 may be lower than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.

[0066] The outer body region 21 is formed in the surface layer portion of the high-concentration region 10 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a strip shape along the active region 8. The outer body region 21 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and partitions the active region 8 from multiple directions.

[0067] In this embodiment, the outer body region 21 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. In other words, the outer body region 21 forms the boundary between the active region 8 and the outer peripheral region 9. The outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 6 ).

[0068] The outer body region 21 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 21 is connected to the plurality of body regions 20 in a portion extending in the first direction X. In other words, the outer body region 21 is electrically connected to the plurality of body regions 20 in the surface layer portion of the high-concentration region 10.

[0069] The outer edge of the outer body region 21 is formed at a distance from the periphery of the high-concentration region 10 toward the active region 8. In other words, the outer edge of the outer body region 21 is formed at a distance from the low-concentration region 11. The entire outer body region 21 is located within the high-concentration region 10. The edge of the outer body region 21 is located in the surface layer of the high-concentration region 10.

[0070] The outer body region 21 preferably has a width greater than that of the body region 20. The width of the body region 20 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the outer body region 21 is the width in a direction perpendicular to the extending direction. Of course, the width of the outer body region 21 may be approximately equal to the width of the body region 20 or may be less than the thickness of the body region 20.

[0071] The ratio of the width of the outer body region 21 to the width of the body region 20 may be 1 or greater and 50 or less. The width ratio may have a value belonging to at least one of the ranges of 1 or greater and 10 or less, 10 or greater and 20 or less, 20 or greater and 30 or less, 30 or greater and 40 or less, and 40 or greater and 50 or less. The width ratio is preferably 10 or greater. The width ratio is preferably 20 or greater and 40 or less.

[0072] The outer body region 21 is formed at a distance from the bottom of the high-concentration region 10 toward the first main surface 3, and faces the inner low-concentration region 13 (base region 14) across a part of the high-concentration region 10. The outer body region 21 is preferably formed at a distance from the middle of the high-concentration region 10 toward the first main surface 3. Of course, the outer body region 21 may cross the depth position of the middle of the high-concentration region 10 in the thickness direction. The outer body region 21 is exposed from the first main surface 3.

[0073] The outer body region 21 preferably has a thickness (depth) approximately equal to the thickness (depth) of the body region 20. Of course, the thickness of the outer body region 21 may be less than the thickness of the body region 20 or may be greater than the thickness of the body region 20.

[0074] The outer body region 21 forms a pn junction (pn junction diode: body diode) with the high-concentration region 10. The outer body region 21 expands a depletion layer into the high-concentration region 10 when a reverse bias voltage is applied to the pn junction. The depletion layer in the outer body region 21 integrates with the depletion layers in the multiple body regions 20 and expands in the horizontal and thickness directions. The range of the depletion layer in the outer body region 21 is expanded toward the periphery of the chip 2 by the low-concentration region 11. This improves the breakdown voltage on the periphery (outer peripheral region 9) side of the chip 2.

[0075] In this configuration, the depletion layer of the outer body region 21 extends from the high concentration region 10 to the inner low concentration region 13 in the thickness direction of the chip 2. That is, the range of the depletion layer of the outer body region 21 is expanded by the inner low concentration region 13. This improves the breakdown voltage on the inner side (active region 8 side) of the chip 2.

[0076] The semiconductor device 1A includes a plurality of n-type surface drift regions 22 formed in a surface portion of the first main surface 3. The surface drift regions 22 are each defined in a region between a plurality of body regions 20 adjacent to each other in the first direction X in the surface portion of the high-concentration region 10. Specifically, the surface drift regions 22 are each defined by a plurality of body regions 20 and outer body regions 21 in the surface portion of the high-concentration region 10.

[0077] In this embodiment, each of the plurality of surface drift regions 22 is made up of a part of the high-concentration region 10. Of course, the plurality of surface drift regions 22 may have an n-type impurity concentration higher than that of the high-concentration region 10, or may have an n-type impurity concentration lower than that of the high-concentration region 10.

[0078] The multiple surface drift regions 22 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the multiple surface drift regions 22 are formed in stripes extending in the second direction Y. The multiple surface drift regions 22 form an n-type (pnp-type) JFET structure together with the multiple body regions 20 located on both sides. The JFET resistance component of the JFET structure is reduced by the high-concentration region 10.

[0079] The surface drift regions 22 may have a width of 0.1 μm to 5 μm. The width of the surface drift regions 22 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0080] The semiconductor device 1A includes a plurality of n-type source regions 23, 24 formed in the surface layer portions of the plurality of body regions 20. The plurality of source regions 23, 24 have an n-type impurity concentration higher than the n-type impurity concentration of the high-concentration region 10. A source potential is applied to the plurality of source regions 23, 24.

[0081] The plurality of source regions 23, 24 include a first source region 23 located on one side (the third side surface 5C side) in the first direction X and a second source region 24 located on the other side (the fourth side surface 5D side) in the first direction X in a surface layer portion of each body region 20. In this embodiment, one first source region 23 is formed on one end side of the body region 20 and one second source region 24 is formed on the other end side of the body region 20 in the first direction X.

[0082] The first source region 23 is formed at a distance from one end of the body region 20 to the other end, and extends in a strip shape along the extension direction of the body region 20. The first source region 23 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the first source region 23 is not formed in the outer body region 21. The first source region 23 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the high-concentration region 10 with a part of the body region 20 in between.

[0083] The second source region 24 is formed at a distance from the first source region 23 to the other end side of the body region 20. The second source region 24 is formed at a distance from the other end of the body region 20 to one end side, and extends in a strip shape along the extension direction of the body region 20. The second source region 24 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the second source region 24 is not formed in the outer body region 21. The second source region 24 is formed at a distance from the bottom of the body region 20 to the first main surface 3 side, and faces the high-concentration region 10 with a part of the body region 20 in between.

[0084] When a plurality of first source regions 23 are formed in one body region 20, the plurality of first source regions 23 may be formed at intervals in the extension direction of the body region 20. In this case, each first source region 23 may be formed in a strip shape extending in the second direction Y. Similarly, when a plurality of second source regions 24 are formed in one body region 20, the plurality of second source regions 24 may be formed at intervals in the extension direction of the body region 20. In this case, each second source region 24 may be formed in a strip shape extending in the second direction Y.

[0085] The semiconductor device 1A includes a plurality of p-type contact regions 25 formed in the surface layer portions of the plurality of body regions 20 in the active region 8. The contact regions 25 may also be referred to as "back gate regions." A source potential is applied to the plurality of contact regions 25. The contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0086] In this embodiment, one contact region 25 is interposed in a region between the first source region 23 and the second source region 24 in the surface layer portion of the corresponding body region 20. The contact region 25 extends in a strip shape along the extension direction of the body region 20 (the source regions 23, 24).

[0087] The contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the contact region 25 is not formed in the outer body region 21. The contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the high-concentration region 10 with a part of the body region 20 sandwiched therebetween.

[0088] When multiple contact regions 25 are formed in one body region 20, the multiple contact regions 25 may be formed at intervals in the extension direction of the body region 20. In this case, each contact region 25 may be formed in a strip shape extending in the second direction Y.

[0089] The semiconductor device 1A includes a plurality of p-type channel regions 26, 27 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 26, 27 are defined in the surface layer portions of the plurality of body regions 20, respectively, in regions between ends of the plurality of body regions 20 (a plurality of surface drift regions 22) and peripheral edges of the plurality of source regions 23, 24. In this embodiment, the plurality of channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 26, 27 are arranged in stripes extending in the second direction Y.

[0090] The plurality of channel regions 26, 27 includes a plurality of first channel regions 26 and a plurality of second channel regions 27. The plurality of first channel regions 26 are each defined as a region between one end of the plurality of body regions 20 (surface drift region 22) and the plurality of first source regions 23, and form a current path extending in the horizontal direction. The plurality of second channel regions 27 are each defined as a region between the other end of the plurality of body regions 20 (surface drift region 22) and the plurality of second source regions 24, and form a current path extending in the horizontal direction.

[0091] The semiconductor device 1A includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8. The plurality of gate structures 30 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y. The extending direction of the plurality of gate structures 30 also coincides with the off-direction of the SiC single crystal.

[0092] Each gate structure 30 is disposed on at least one channel region 26, 27. In this embodiment, each gate structure 30 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, covering a plurality of channel regions 26, 27.

[0093] Specifically, each gate structure 30 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0094] The configuration of one gate structure 30 will be described below. The gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32. The insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 include a silicon oxide film made of an oxide of the chip 2.

[0095] The insulating film 31 covers the first main surface 3 in a film-like manner and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, and covers the multiple channel regions 26, 27.

[0096] Specifically, the insulating film 31 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.

[0097] The insulating film 31 partially covers the first source region 23 at a distance from the contact region 25, and exposes a part of the first source region 23 and the contact region 25 from the first main surface 3. The insulating film 31 partially covers the second source region 24 at a distance from the contact region 25, and exposes a part of the second source region 24 and the contact region 25 from the first main surface 3.

[0098] The insulating film 31 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the insulating film 31 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. The thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.

[0099] The gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26 and 27 across the insulating film 31. A gate potential is applied to the gate electrode 32 as a control potential. The gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 32 is adjusted depending on the gate threshold voltage to be achieved.

[0100] The gate electrode 32 is formed in a strip shape extending in the second direction Y. In this embodiment, the gate electrode 32 is formed at a distance inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 so as to cross one surface drift region 22 and straddle two adjacent body regions 20, and faces the multiple channel regions 26, 27 with the insulating film 31 in between.

[0101] Specifically, the gate electrode 32 is arranged to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 across the insulating film 31.

[0102] The gate electrode 32 responds to a gate potential to control the inversion and non-inversion of the channel regions 26, 27. When a gate potential is applied to the gate electrode 32, the channel regions 26, 27 are turned on, and a drain current flows between the heavily doped region 10 and the source regions 23, 24 via the channel regions 26, 27 (body region 20). In this way, a planar gate type transistor structure Tr including the heavily doped region 10 is formed in the inner portion (active region 8) of the chip 2.

[0103] 6 to 11 , semiconductor device 1A includes a p-type termination region 40 formed on first main surface 3 in peripheral region 9. Termination region 40 may also be referred to as a "well region," a "termination well region," or the like. Termination region 40 is formed in either or both of a surface layer portion of high-concentration region 10 and a surface layer portion of low-concentration region 11 in peripheral region 9. In this embodiment, termination region 40 is formed in a surface layer portion of high-concentration region 10 in peripheral region 9.

[0104] The termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the body region 20. The p-type impurity concentration of the termination region 40 may be higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the termination region 40 may be lower than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the termination region 40 may be approximately equal to the p-type impurity concentration of the body region 20.

[0105] The termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the outer body region 21. The p-type impurity concentration of the termination region 40 may be higher than the p-type impurity concentration of the outer body region 21. The p-type impurity concentration of the termination region 40 may be lower than the p-type impurity concentration of the outer body region 21. Of course, the p-type impurity concentration of the termination region 40 may be approximately equal to the p-type impurity concentration of the outer body region 21.

[0106] Termination region 40 is spaced inward from the periphery of first main surface 3 and is formed in a region between the periphery of first main surface 3 and outer body region 21. Termination region 40 extends in a band shape along outer body region 21 in a plan view. Termination region 40 has a portion extending in a band shape in first direction X and a portion extending in a band shape in second direction Y in a plan view, and defines active region 8 from multiple directions.

[0107] In this embodiment, the termination region 40 surrounds the outer body region 21 in a plan view and is defined as a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The termination region 40 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 6 ).

[0108] Termination region 40 is formed at a distance from the bottom of high-concentration region 10 toward first main surface 3, and faces inner low-concentration region 13 across a portion of high-concentration region 10. Termination region 40 is preferably formed at a distance from the middle of high-concentration region 10 toward first main surface 3. Of course, termination region 40 may cross the depth position of the middle of high-concentration region 10 in the thickness direction. Termination region 40 may have a thickness (depth) approximately equal to the thickness (depth) of outer body region 21. The thickness of termination region 40 may be greater than or less than the thickness of outer body region 21.

[0109] Termination region 40 has an inner edge on the active region 8 side and an outer edge on the peripheral side of first main surface 3. The inner edge of termination region 40 is connected to the outer edge of outer body region 21 in the surface layer portion of high-concentration region 10. This electrically connects termination region 40 to outer body region 21. That is, in this embodiment, termination region 40 is electrically connected to multiple body regions 20 via outer body region 21.

[0110] In this embodiment, the inner edge of the termination region 40 is connected around the entire periphery to the outer edge of the outer body region 21. When the termination region 40 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the outer body region 21, the termination region 40 may be considered as part (a lead-out portion) of the outer body region 21.

[0111] The termination region 40 (inner edge portion) has an overlap region 41 that overlaps the outer edge portion of the outer body region 21 in the surface layer portion of the high-concentration region 10. The overlap region 41 is a high-concentration region that includes the outer edge portion of the outer body region 21 and the inner edge portion of the termination region 40. In other words, the overlap region 41 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 40, and has a p-type impurity concentration that is higher than both the p-type impurity concentrations of the outer body region 21 and the termination region 40.

[0112] The p-type impurity concentration of the overlap region 41 is higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the overlap region 41 may be lower than the p-type impurity concentration of the contact region 25. Of course, the p-type impurity concentration of the overlap region 41 may be higher than the p-type impurity concentration of the contact region 25.

[0113] The overlap region 41 extends in a band shape along the outer body region 21 in a plan view. The overlap region 41 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions. In this embodiment, the overlap region 41 is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0114] The overlap region 41 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 6 ). The width of the overlap region 41 is preferably greater than the width of the body region 20. Of course, the width of the overlap region 41 may be less than the width of the body region 20.

[0115] The termination region 40 forms a pn junction (pn junction diode: body diode) with the high-concentration region 10. The termination region 40 expands a depletion layer into the high-concentration region 10 when a reverse bias voltage is applied to the pn junction. The depletion layer in the termination region 40 integrates with the depletion layers in the multiple body regions 20 and the outer body region 21, and expands in the horizontal and thickness directions. The range of the depletion layer in the termination region 40 is expanded toward the periphery of the chip 2 by the low-concentration region 11. This improves the breakdown voltage on the periphery (outer peripheral region 9) side of the chip 2.

[0116] In this configuration, the depletion layer in termination region 40 extends from high concentration region 10 to inner low concentration region 13 in the thickness direction of chip 2. The range of the depletion layer in termination region 40 is also extended in peripheral region 9 by inner low concentration region 13. This improves the breakdown voltage on the peripheral edge (peripheral region 9) side of chip 2.

[0117] The outer edge of termination region 40 preferably crosses the periphery of high-concentration region 10 and is located in low-concentration region 11. That is, termination region 40 is preferably located in the surface layer of low-concentration region 11 in peripheral region 9 and has a portion (outer edge) that forms a pn junction with low-concentration region 11 (see FIG. 10 ). The edge of the outer edge of termination region 40 is located in the surface layer of low-concentration region 11.

[0118] With this configuration, the depletion layer extends directly from the termination region 40 to the low-concentration region 11. Therefore, the range of the depletion layer is appropriately expanded in the peripheral portion (peripheral region 9) of the chip 2. Of course, the outer edge of the termination region 40 may be formed at a distance from the peripheral portion of the high-concentration region 10 toward the active region 8, and may be located within the high-concentration region 10.

[0119] The semiconductor device 1A may have a relatively high-concentration p-type well region (46) instead of the overlap region 41. In this case, the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 40. The p-type impurity concentration of the well region (46) is higher than the p-type impurity concentration of the body region 20.

[0120] The p-type impurity concentration of the well region (46) may be approximately equal to the p-type impurity concentration of the contact region 25. Of course, the p-type impurity concentration of the well region (46) may be lower than the p-type impurity concentration of the contact region 25, or may be higher than the p-type impurity concentration of the contact region 25.

[0121] The well region (46) may be formed in either or both of the surface layer portion of the outer body region 21 and the surface layer portion of the termination region 40. Such a configuration is effective when the termination region 40 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the outer body region 21 and is formed as part (draw-out portion) of the outer body region 21.

[0122] The semiconductor device 1A includes at least one p-type field region 42 formed in the outer peripheral region 9 in a surface layer portion of the first main surface 3. The plurality of field regions 42 may be formed in an electrically floating state. The plurality of field regions 42 may be fixed to the source potential.

[0123] The number of field regions 42 is arbitrary. The number of field regions 42 may be 1 or more and 20 or less. The number of field regions 42 may have a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 42 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1A includes three field regions 42.

[0124] The plurality of field regions 42 are formed in the surface layer portion of the low-concentration region 11. The plurality of field regions 42 are formed inwardly from the periphery of the first main surface 3 at intervals in a region between the periphery of the first main surface 3 and the active region 8. The plurality of field regions 42 are formed in a region between the periphery of the first main surface 3 and the outer body region 21.

[0125] Specifically, the multiple field regions 42 are arranged in a region between the periphery of first main surface 3 and high concentration region 10, with a gap between high concentration region 10 and the periphery of first main surface 3. Even more specifically, the multiple field regions 42 are arranged in a region between the periphery of first main surface 3 and termination region 40, with a gap between termination region 40 and the periphery of first main surface 3. In other words, the multiple field regions 42 are not formed in high concentration region 10.

[0126] The plurality of field regions 42 are formed in strip shapes extending along the active region 8 (termination region 40) in plan view. Each of the plurality of field regions 42 has a portion extending in strip shape in the first direction X and a portion extending in strip shape in the second direction Y. In this embodiment, the plurality of field regions 42 are formed in polygonal ring shapes (square ring shapes in this embodiment) surrounding the active region 8 (termination region 40) in plan view.

[0127] The field regions 42 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) (see FIG. 6 ). The edge portions of the field regions 42 are located in the surface layer portion of the low-concentration region 11. The field regions 42 are formed at intervals from the bottom of the low-concentration region 11 toward the first main surface 3, and face the base region 14 with a portion of the low-concentration region 11 in between.

[0128] The plurality of field regions 42 are formed at intervals from the depth position of the bottom of the high-concentration region 10 toward the first main surface 3. It is preferable that the plurality of field regions 42 are formed at intervals from the depth position of the middle of the high-concentration region 10 toward the first main surface 3. Of course, the plurality of field regions 42 may cross the depth position of the middle of the high-concentration region 10 in the thickness direction.

[0129] The plurality of field regions 42 each form a pn junction (pn junction diode) with the low concentration region 11. The plurality of field regions 42 expand a depletion layer toward the low concentration region 11 when a reverse bias voltage is applied. The depletion layers of the plurality of field regions 42 merge with the depletion layer of the termination region 40 and expand in the horizontal and thickness directions. The range of the depletion layer of the plurality of field regions 42 is expanded by the low concentration region 11. This improves the breakdown voltage on the peripheral edge (peripheral region 9) side of the chip 2.

[0130] The low-concentration region 11 extends the range of the depletion layer, allowing the number of field regions 42 to be reduced. This reduces the area occupied by the peripheral region 9 in the chip 2 and increases the area occupied by the active region 8 in the chip 2. This improves the electrical characteristics of the transistor structure Tr (device structure) formed in the active region 8. This configuration is also effective in achieving a smaller chip 2.

[0131] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 42 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 42 may be approximately constant or may be non-uniform. The width of the multiple field regions 42 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 42 may gradually decrease toward the periphery of the first main surface 3.

[0132] The depth of the multiple field regions 42 may be approximately constant or may be non-uniform. The depth of the multiple field regions 42 may gradually increase toward the peripheral edge of the first main surface 3. The depth of the multiple field regions 42 may gradually decrease toward the peripheral edge of the first main surface 3. Of course, the multiple field regions 42 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion. The shallow portion may be formed on the inward side, and the deep portion may be formed on the peripheral edge side. The shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inward side.

[0133] The spacing between the multiple field regions 42 may be substantially uniform or may be non-uniform. The spacing between the multiple field regions 42 may gradually increase toward the periphery of the first main surface 3. The spacing between the multiple field regions 42 may gradually decrease toward the periphery of the first main surface 3.

[0134] The p-type impurity concentrations of the plurality of field regions 42 may be approximately constant or may be non-uniform. The p-type impurity concentrations of the plurality of field regions 42 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the plurality of field regions 42 may gradually decrease toward the periphery of the first main surface 3.

[0135] The p-type impurity concentrations of the multiple field regions 42 may be approximately equal to the p-type impurity concentration of the body region 20 (outer body region 21). The p-type impurity concentrations of the multiple field regions 42 may be higher than the p-type impurity concentration of the body region 20 (outer body region 21), or may be lower than the p-type impurity concentration of the body region 20 (outer body region 21). The p-type impurity concentrations of the multiple field regions 42 may be approximately equal to the p-type impurity concentration of the termination region 40. The p-type impurity concentrations of the multiple field regions 42 may be higher than the p-type impurity concentration of the termination region 40, or may be lower than the p-type impurity concentration of the termination region 40.

[0136] The semiconductor device 1A includes a peripheral insulating film 43 that covers the first main surface 3 in the peripheral region 9. The peripheral insulating film 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the peripheral insulating film 43 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 43 includes a silicon oxide film made of an oxide of the chip 2. The peripheral insulating film 43 is preferably made of the same type of insulating material as the insulating material of the insulating film 31. The peripheral insulating film 43 preferably has a thickness approximately equal to that of the insulating film 31.

[0137] The peripheral insulating film 43 covers the first main surface 3 in the peripheral region 9. The peripheral insulating film 43 collectively covers the high-concentration region 10, the low-concentration region 11, the outer body region 21, the termination region 40, and the plurality of field regions 42. The peripheral insulating film 43 is connected to the plurality of insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 43 is formed integrally with the plurality of insulating films 31, and together with the plurality of insulating films 31, forms a single insulating film.

[0138] The semiconductor device 1A includes a gate wiring 44 arranged on the first main surface 3 in the peripheral region 9. The gate wiring 44 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32. The gate wiring 44 is connected to the multiple gate electrodes 32 and applies gate signals to the multiple gate electrodes 32. The gate wiring 44 may also be referred to as a "second gate electrode" or the like.

[0139] The gate wiring 44 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 44 preferably has the same conductivity type as the gate electrode 32.

[0140] Gate wiring 44 is arranged on peripheral insulating film 43 in peripheral region 9 at a distance from the periphery of first main surface 3 toward active region 8. Specifically, gate wiring 44 is arranged at a distance from low concentration region 11 toward active region 8 in plan view. In this embodiment, gate wiring 44 is arranged at a distance from termination region 40 toward active region 8, and is arranged on a portion of peripheral insulating film 43 that covers outer body region 21.

[0141] That is, the gate wiring 44 faces the outer body region 21 across the peripheral insulating film 43. The gate wiring 44 faces the high concentration region 10 (inner low concentration region 13) in the stacking direction, but does not face the low concentration region 11 in the stacking direction. The gate wiring 44 may partially face the termination region 40 in the stacking direction.

[0142] The gate wiring 44 extends in a strip shape along the active region 8 in a plan view. The gate wiring 44 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions. In this embodiment, the gate wiring 44 surrounds the active region 8 in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The gate wiring 44 may be either ended or endless.

[0143] In this embodiment, the gate wiring 44 extends in a strip shape (annular shape in this embodiment) along the outer body region 21 in a plan view, and faces the outer body region 21 across the outer insulating film 43 in the stacking direction over the entire extension direction. The gate wiring 44 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 6 ).

[0144] The gate wiring 44 is formed to be narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21. That is, in this embodiment, the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 44 is connected to the multiple gate electrodes 32 above the outer body region 21.

[0145] The thickness of the gate wiring 44 is preferably approximately equal to the thickness of the gate electrode 32. The width of the gate wiring 44 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 44 is the width in a direction perpendicular to the extending direction. For example, the ratio of the width of the gate wiring 44 to the width of the gate electrode 32 may be 1 or more and 50 or less.

[0146] The width ratio may have a value belonging to at least one of the ranges of 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50. The width ratio may be 5 or greater. The width ratio may be 20 to 40. Of course, the width of the gate interconnection 44 may be equal to or less than the width of the gate electrode 32. The width of the gate interconnection 44 may be greater than the width of the outer body region 21.

[0147] The semiconductor device 1A includes an insulating interlayer film 50 covering the first main surface 3. The interlayer film 50 may also be referred to as an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 50 has an insulating surface 51 extending along the first main surface 3. The interlayer film 50 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.

[0148] The interlayer film 50 covers the multiple gate structures 30 in the active region 8. The interlayer film 50 collectively covers the high concentration region 10, the low concentration region 11, the outer body region 21, the termination region 40, and the multiple field regions 42 in the peripheral region 9, with the peripheral insulating film 43 sandwiched therebetween. The interlayer film 50 covers the gate wiring 44 in the peripheral region 9. The interlayer film 50 is continuous with the first to fourth side surfaces 5A to 5D. The interlayer film 50 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, and may expose the peripheral portion (low concentration region 11) of the first main surface 3.

[0149] In this embodiment, the interlayer film 50 has a layered structure including a first oxide film 52 (first insulating film) and a second oxide film 53 (second insulating film), which are layered in this order from the first main surface 3 side. That is, the interlayer film 50 has an insulating surface 51 formed by the second oxide film 53. The first oxide film 52 has a single-layer structure made of a silicon oxide film with no added impurities. The first oxide film 52 may also be referred to as an NSG film (nondoped silicate glass film). In this embodiment, the first oxide film 52 has a thickness less than that of the gate electrode 32. Of course, the thickness of the first oxide film 52 may be greater than that of the gate electrode 32.

[0150] The first oxide film 52 collectively covers the active region 8 and the peripheral region 9. The first oxide film 52 collectively covers the plurality of gate structures 30 in the active region 8. The first oxide film 52 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.

[0151] The first oxide film 52 has a portion that covers the insulating film 31 (first main surface 3) in a film-like manner along the horizontal direction. The first oxide film 52 covers the insulating film 31 at a distance from the height position of the electrode surface (upper end) of the gate electrode 32 toward the insulating film 31. The first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate electrode 32.

[0152] The first oxide film 52 has a portion that covers the electrode surface of the gate electrode 32 in a film-like manner along the horizontal direction. The first oxide film 52 preferably has arc corners that are curved in an arc shape in the portion that covers the corners of the gate electrode 32. The arc corners may have a center of curvature on the gate electrode 32 side.

[0153] In the peripheral region 9, the first oxide film 52 collectively covers the high concentration region 10, the low concentration region 11, the outer body region 21, the termination region 40, and the plurality of field regions 42, with the peripheral insulating film 43 sandwiched therebetween. The first oxide film 52 covers the gate wiring 44 in the peripheral region 9.

[0154] The first oxide film 52 has a portion that covers the peripheral insulating film 43 (first main surface 3) in a film-like manner along the horizontal direction. The first oxide film 52 covers the peripheral insulating film 43 at a distance from the height position of the wiring surface (upper end) of the gate wiring 44 toward the peripheral insulating film 43. The first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate wiring 44.

[0155] The first oxide film 52 has a portion that horizontally covers the wiring surface of the gate wiring 44 in a film-like manner. The first oxide film 52 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate wiring 44. The arc corner portion may have a center of curvature on the gate wiring 44 side.

[0156] The second oxide film 53 may have a single-layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass Film). The silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass Film).

[0157] The second oxide film 53 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 52. The second oxide film 53 may have a layered structure including a PSG film stacked on the first oxide film 52 and a BPSG film stacked on the PSG film. The second oxide film 53 may have a layered structure including a BPSG film stacked on the first oxide film 52 and a PSG film stacked on the BPSG film.

[0158] In this embodiment, the second oxide film 53 has a single-layer structure made of, for example, a PSG film. The thickness of the second oxide film 53 may be greater than the thickness of the first oxide film 52. The thickness of the second oxide film 53 may be less than the thickness of the first oxide film 52. The thickness of the second oxide film 53 may be greater than the thickness of the gate electrode 32. The thickness of the second oxide film 53 may be less than the thickness of the gate electrode 32.

[0159] The second oxide film 53 covers the first oxide film 52 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 collectively covers the plurality of gate structures 30 in the active region 8 with the first oxide film 52 sandwiched therebetween. Specifically, the second oxide film 53 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 52 sandwiched therebetween.

[0160] The second oxide film 53 has a portion that covers the insulating film 31 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the stacking direction along the sidewall of the gate electrode 32 in a film-like shape, and has a portion that covers the sidewall of the gate electrode 32 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the horizontal direction along the electrode surface of the gate electrode 32 in a film-like shape, and has a portion that covers the electrode surface of the gate electrode 32 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in a portion that covers the corner of the gate electrode 32. The arc corner portion may have a center of curvature on the gate electrode 32 side.

[0161] In the peripheral region 9, the second oxide film 53 collectively covers the high concentration region 10, the low concentration region 11, the outer body region 21, the termination region 40, and the plurality of field regions 42, sandwiching the peripheral insulating film 43 and the first oxide film 52. In the peripheral region 9, the second oxide film 53 covers the gate wiring 44, sandwiching the first oxide film 52 therebetween.

[0162] The second oxide film 53 has a portion that covers the peripheral insulating film 43 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the stacking direction along the sidewall of the gate wiring 44 in the form of a film, and has a portion that covers the sidewall of the gate wiring 44 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 extends in the horizontal direction along the wiring surface of the gate wiring 44 in the form of a film, and has a portion that covers the wiring surface of the gate wiring 44 with the first oxide film 52 sandwiched therebetween. The second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner of the gate wiring 44. The arc corner portion may have a center of curvature on the gate wiring 44 side.

[0163] The semiconductor device 1A includes a plurality of source openings 54 formed in the interlayer film 50 in the active region 8. The plurality of source openings 54 are formed in regions on the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2). Specifically, the plurality of source openings 54 penetrate the insulating film 31 and the interlayer film 50 in regions between the plurality of gate electrodes 32.

[0164] The plurality of source openings 54 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53. The plurality of source openings 54 each have an opening end defined by a circular arc corner portion of the interlayer film 50. The plurality of source openings 54 expose the corresponding plurality of source regions 23, 24 and contact region 25, respectively.

[0165] In this embodiment, the source openings 54 are formed at intervals in the first direction X and in the shape of bands extending in the second direction Y. That is, the source openings 54 are formed in the shape of stripes extending in the second direction Y. The source openings 54 are formed at intervals from the gate wiring 44 in the second direction Y. That is, the source openings 54 are formed in a region surrounded by the gate electrodes 32 and the gate wiring 44.

[0166] A plurality of source openings 54 may be formed in a region between two gate structures 30 adjacent to each other in the first direction X. In this case, the plurality of source openings 54 may be formed in a line at intervals in the second direction Y. Furthermore, in this case, each source opening 54 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.

[0167] The source opening 54 may have a width W of 0.1 μm or more and 3 μm or less. The width W of the source opening 54 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The width W of the source opening 54 is preferably 0.2 μm or more and 1 μm or less.

[0168] The source opening 54 may have a depth D of 0.1 μm or more and 2 μm or less. The depth D of the source opening 54 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or more, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The depth D of the source opening 54 is preferably 0.5 μm or more and 1 μm or less.

[0169] The source opening 54 preferably has an aspect ratio D / W of 0.5 to 3. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 54 to the width W of the source opening 54. The aspect ratio D / W may have a value belonging to at least one of the ranges of 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.

[0170] The aspect ratio D / W is preferably greater than 1. That is, the source openings 54 preferably have a depth D greater than their width W and are each formed in a vertically elongated shape in cross section. With this configuration, the gate structures 30 are arranged at a narrow pitch. The aspect ratio D / W of the vertically elongated source openings 54 is preferably greater than 1 and equal to or less than 2.

[0171] The semiconductor device 1A includes a plurality of source recesses 55 formed in the first main surface 3 in portions exposed from the plurality of source openings 54. The semiconductor device 1A does not necessarily have to have the source recesses 55. Therefore, a configuration not including the source recesses 55 may be employed.

[0172] The plurality of source recesses 55 each have a planar shape that matches the planar shape of the corresponding source opening 54, and are recessed from the first main surface 3 toward the second main surface 4. The plurality of source recesses 55 are formed at intervals from the bottoms of the corresponding body regions 20 toward the first main surface 3, and expose the corresponding plurality of source regions 23, 24 and contact regions 25. Specifically, the plurality of source recesses 55 are formed at intervals from the bottoms of the corresponding plurality of source regions 23, 24 (contact regions 25) toward the first main surface 3.

[0173] The semiconductor device 1A includes at least one (in this embodiment, multiple) outer openings 56 formed in the interlayer film 50 in the peripheral region 9. The multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the termination region 40. The multiple outer openings 56 penetrate the interlayer film 50 to expose the termination region 40. In this embodiment, the multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the overlap region 41 of the termination region 40 to expose the overlap region 41.

[0174] The outer openings 56 may expose the outer body region 21 instead of or in addition to the termination region 40 (overlap region 41). The outer openings 56 penetrate both the first oxide film 52 and the second oxide film 53 and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53. The outer openings 56 each have an opening end defined by a circular arc corner portion of the interlayer film 50.

[0175] The outer openings 56 are spaced apart along the termination region 40 (overlap region 41) (see FIGS. 6 and 7). The outer openings 56 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The outer openings 56 may be formed in a strip shape extending along the termination region 40 (overlap region 41) in a plan view. The outer openings 56 may have an aspect ratio D / W (= 0.5 to 3, preferably greater than 1), similar to the source openings 54.

[0176] The semiconductor device 1A may have a single outer opening 56. The single outer opening 56 may be formed in a strip shape extending along the termination region 40 (overlap region 41). The single outer opening 56 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0177] The single outer opening 56 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single outer opening 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the termination region 40 (overlapping region 41) in a plan view (see FIG. 6 ).

[0178] The semiconductor device 1A includes a plurality of outer recesses 57 formed in the portions of the first main surface 3 that are exposed from the plurality of outer openings 56. The semiconductor device 1A does not necessarily have to have the outer recesses 57. Therefore, a configuration that does not have the outer recesses 57 may be adopted.

[0179] The outer recesses 57 each have a planar shape that matches the planar shape of the corresponding outer opening 56, and are recessed from the first main surface 3 toward the second main surface 4. The outer recesses 57 are formed at intervals from the bottom of the termination region 40 (overlap region 41) toward the first main surface 3, and each exposes the termination region 40 (overlap region 41). The outer recesses 57 may have a depth approximately equal to the depth of the source recess 55. When a single outer opening 56 is formed, a single outer recess 57 that matches the planar shape of the single outer opening 56 is formed.

[0180] The semiconductor device 1A includes at least one gate opening 58 (in this embodiment, multiple gate openings 58) formed in the interlayer film 50 in the peripheral region 9. The multiple gate openings 58 are formed in a portion of the interlayer film 50 that covers the gate wiring 44. The multiple gate openings 58 penetrate the interlayer film 50 to expose the gate wiring 44. The multiple gate openings 58 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53. Each of the multiple gate openings 58 has an opening end defined by a circular arc corner portion of the interlayer film 50.

[0181] The multiple gate openings 58 are formed at intervals along the gate wiring 44 (see FIGS. 6 and 7). The multiple gate openings 58 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view. The multiple gate openings 58 may be formed in a strip shape extending along the gate wiring 44 in a plan view. Like the source openings 54, the gate openings 58 may have an aspect ratio D / W (= 0.5 to 3, preferably greater than 1).

[0182] The semiconductor device 1A may have a single gate opening 58. The single gate opening 58 may be formed in a strip shape extending along the gate wiring 44. The single gate opening 58 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0183] The single gate opening 58 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single gate opening 58 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in plan view, following the gate wiring 44 (see FIG. 6 ).

[0184] 1 and other figures, the semiconductor device 1A includes a source pad electrode 60 disposed on an interlayer film 50. The source pad electrode 60 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 60 may also be referred to as a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0185] The source pad electrode 60 is disposed on a portion of the interlayer film 50 that covers the active region 8. The source pad electrode 60 covers the plurality of gate electrodes 32 with the interlayer film 50 in between, and is electrically separated from the plurality of gate electrodes 32 by the interlayer film 50. The source pad electrode 60 is electrically connected to the plurality of body regions 20, the outer body region 21, the plurality of source regions 23 and 24, the contact region 25, etc. via the plurality of source openings 54.

[0186] In this embodiment, the source pad electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c. The first pad portion 60a has a relatively large planar area and forms the main body of the source pad electrode 60. In this embodiment, the first pad portion 60a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the active region 8. The first pad portion 60a covers the multiple gate electrodes 32 with the interlayer film 50 sandwiched therebetween, and is electrically connected to the multiple body regions 20 and the like via the multiple source openings 54.

[0187] The second pad portion 60b has a planar area smaller than that of the first pad portion 60a, and extends in a strip shape (rectangular shape) from one end of the first pad portion 60a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The second pad portion 60b covers the plurality of gate electrodes 32 with the interlayer film 50 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 54.

[0188] The third pad portion 60c has a planar area smaller than that of the first pad portion 60a, and is drawn out in a strip shape (rectangular shape) from the other end of the first pad portion 60a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 60b in the second direction Y. The third pad portion 60c covers the plurality of gate electrodes 32 with the interlayer film 50 sandwiched therebetween, and is electrically connected to the plurality of body regions 20 etc. via the plurality of source openings 54.

[0189] The planar area of ​​the third pad portion 60c may be approximately equal to the planar area of ​​the second pad portion 60b. Of course, the planar area of ​​the third pad portion 60c may be larger than the planar area of ​​the second pad portion 60b, or may be smaller than the planar area of ​​the second pad portion 60b. Either or both of the second pad portion 60b and the third pad portion 60c may be used as a terminal portion for monitoring a current.

[0190] The source pad electrode 60 does not necessarily have to have both the second pad portion 60b and the third pad portion 60c at the same time. The source pad electrode 60 may have only one of the second pad portion 60b and the third pad portion 60c. Of course, the source pad electrode 60 may be composed of only the first pad portion 60a, and may not have the second pad portion 60b or the third pad portion 60c.

[0191] 8 and 9, the source pad electrode 60 includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63. The first underlying electrode film 61 may be referred to as a "source underlying electrode film," the first buried electrodes 62 may be referred to as "source buried electrodes," and the first main electrode film 63 may be referred to as a "source main electrode film."

[0192] The first underlying electrode film 61 forms a lower layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c), and covers the interlayer film 50 in the active region 8. The first underlying electrode film 61 collectively covers the region of the interlayer film 50 where the multiple source openings 54 are formed, and extends from above the insulating surface 51 into the multiple source openings 54.

[0193] The first base electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the plurality of source openings 54 in a film-like manner. The first base electrode film 61 may have a portion that covers the gate wiring 44 with the interlayer film 50 sandwiched therebetween. The first base electrode film 61 may be formed at a distance inward from the gate wiring 44 in a plan view.

[0194] In this embodiment, the first underlying electrode film 61 has a layered structure including a first electrode film 64 layered on the interlayer film 50 and a second electrode film 65 layered on the first electrode film 64. In this embodiment, the first electrode film 64 includes a Ti film, and the second electrode film 65 includes a TiN film. The first underlying electrode film 61 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 64 (Ti film) or the second electrode film 65 (TiN film).

[0195] The thickness of the first electrode film 64 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 64 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0196] The thickness of the second electrode film 65 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 65 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the second electrode film 65 is preferably greater than the thickness of the first electrode film 64.

[0197] The first electrode film 64 collectively covers the region of the interlayer film 50 where the multiple source openings 54 are formed, and extends into the multiple source openings 54 from above the insulating surface 51. The first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner. The first electrode film 64 directly covers the insulating surface 51 (second oxide film 53), and faces the multiple gate electrodes 32 with the interlayer film 50 in between.

[0198] The first electrode film 64 covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner portion, and extends into the source opening 54. The first electrode film 64 has a portion that extends in an arc shape at the arc corner portion. This improves the film formability of the first electrode film 64 on the interlayer film 50 (wall surface of the source opening 54).

[0199] The first electrode film 64 extends along the wall surface of the source opening 54 and covers the insulating film 31, the first oxide film 52, and the second oxide film 53. The first electrode film 64 faces the side wall of the gate electrode 32 with the interlayer film 50 interposed therebetween. The first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the first main surface 3. Specifically, the first electrode film 64 has a portion that covers the source recess 55 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the plurality of source regions 23, 24 and the contact region 25.

[0200] The first electrode film 64 may cover the source recess 55 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the source recess 55. The first electrode film 64 may have a portion located on the bottom side of the source recess 55 relative to the height position of the first main surface 3, and a portion located on the insulating film 31 side relative to the height position of the first main surface 3.

[0201] The second electrode film 65 collectively covers the region of the interlayer film 50 on the first electrode film 64 where the plurality of source openings 54 are formed. The second electrode film 65 has a portion that covers the insulating surface 51 with the first electrode film 64 in between, and a portion that covers the wall surfaces of the plurality of source openings 54 with the first electrode film 64 in between.

[0202] The second electrode film 65, in a portion covering the insulating surface 51, faces the multiple gate electrodes 32 with the first electrode film 64 and the interlayer film 50 sandwiched therebetween. The second electrode film 65, following the first electrode film 64, covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the source opening 54. The second electrode film 65 has a portion that extends in an arc shape at the arc corner portion of the interlayer film 50. This improves the film formability of the second electrode film 65 on the interlayer film 50 (wall surface of the source opening 54).

[0203] The second electrode film 65 extends along the wall surface of the source opening 54 and covers the insulating film 31, the first oxide film 52, and the second oxide film 53 with the first electrode film 64 sandwiched between them. The second electrode film 65 faces the sidewall of the gate electrode 32 with the first electrode film 64 and the interlayer film 50 sandwiched between them. The second electrode film 65 has a portion at the bottom of each source opening 54 that covers the source recess 55 in a film-like manner with the first electrode film 64 sandwiched between them, and is electrically connected to the plurality of source regions 23, 24 and the contact region 25 via the first electrode film 64.

[0204] When the first electrode film 64 is located on the bottom side of the source recess 55 relative to the first main surface 3, the second electrode film 65 may have a portion located within the source recess 55. When the first electrode film 64 has a portion located above the first main surface 3, the entire second electrode film 65 is located above the source recess 55.

[0205] The multiple first buried electrodes 62 form an intermediate layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c) and are buried in the multiple source openings 54, respectively. The first buried electrodes 62 contain a conductive material different from the conductive material of the first underlying electrode film 61. The first buried electrodes 62 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the first buried electrodes 62 contain tungsten.

[0206] In this embodiment, the multiple first buried electrodes 62 are buried in a one-to-one correspondence with the multiple source openings 54 via a single first base electrode film 61. The multiple first buried electrodes 62 are electrically connected to the first main surface 3 (chip 2) within the multiple source openings 54. Specifically, the first buried electrodes 62 are electrically connected to the multiple source regions 23, 24 and contact regions 25 via the first base electrode film 61. The configuration of one first buried electrode 62 will be described below.

[0207] The first buried electrode 62 has a first buried electrode surface 66 exposed from the source opening 54, exposing the insulating surface 51. The first buried electrode surface 66 may be referred to as a "source buried electrode film." The first buried electrode 62 is buried in the source opening 54 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51.

[0208] The first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first base electrode film 61 sandwiched therebetween. The first buried electrode 62 faces the sidewall of the gate electrode 32 in the horizontal direction. When the first base electrode film 61 is located on the bottom side of the source recess 55 with respect to the first main surface 3, the first buried electrode 62 may have a portion located within the source recess 55. When the first base electrode film 61 has a portion located above the first main surface 3, the entire first buried electrode 62 is located above the source recess 55.

[0209] The first buried electrode surface 66 is located closer to the first main surface 3 than the insulating surface 51, and does not have a portion that faces the electrode surface of the gate electrode 32 with the interlayer film 50 sandwiched therebetween in the stacking direction (vertical direction Z). In this embodiment, the first buried electrode surface 66 has a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween.

[0210] Of course, the first buried electrode surface 66 may be located below the arc corner of the interlayer film 50. The first buried electrode surface 66 is located closer to the insulating surface 51 than the height position of the first oxide film 52. The first buried electrode surface 66 is preferably located above the electrode surface of the gate electrode 32.

[0211] The first buried electrode surface 66 has a recess in its center that recesses toward the first main surface 3 (chip 2). The bottom of the recess is preferably located closer to the insulating surface 51 than the height of the electrode surface of the gate electrode 32. Of course, a part (e.g., recess) or the entire first buried electrode surface 66 may be located lower than the electrode surface of the gate electrode 32. A part (e.g., recess) or the entire first buried electrode surface 66 may be located closer to the insulating surface 51 than the height of the first oxide film 52.

[0212] The first main electrode film 63 forms an upper layer of the source pad electrode 60 (the first pad portion 60 a, the second pad portion 60 b, and the third pad portion 60 c), and covers the first base electrode film 61 and the plurality of first buried electrodes 62 in a film form. The first main electrode film 63 contains a conductive material different from the conductive material of the first base electrode film 61 and the conductive material of the first buried electrodes 62.

[0213] The first main electrode film 63 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The first main electrode film 63 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 61. The first main electrode film 63 has a thickness greater than the thickness of the first buried electrode 62.

[0214] The thickness of the first main electrode film 63 may be 0.5 μm or more and 5 μm or less. The thickness of the first main electrode film 63 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0215] The first main electrode film 63 is mechanically and electrically connected to the first base electrode film 61 in a portion covering the insulating surface 51, and faces the plurality of gate electrodes 32 across the first base electrode film 61 and the interlayer film 50. The first main electrode film 63 is mechanically and electrically connected to the plurality of first buried electrodes 62 in a portion covering the plurality of source openings 54. As a result, the first main electrode film 63 is electrically connected to the plurality of body regions 20, the outer body region 21, the plurality of source regions 23 and 24, the contact region 25, etc. via both the first base electrode film 61 and the plurality of first buried electrodes 62.

[0216] The first main electrode film 63 is connected to the first buried electrode surface 66 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51. The first main electrode film 63 has a portion covering a recess in the first buried electrode surface 66. The first main electrode film 63 may have a portion covering a circular corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween.

[0217] The first main electrode film 63 is connected to the first buried electrode surface 66 above the height position of the first oxide film 52. In this embodiment, the first main electrode film 63 is connected to the first buried electrode surface 66 above the electrode surface of the gate electrode 32. In other words, the first main electrode film 63 does not have a portion that faces the gate electrode 32 in the horizontal direction. When the first buried electrode surface 66 is located below the height position of the electrode surface of the gate electrode 32 and the height position of the first oxide film 52, the first main electrode film 63 may have a portion that faces the gate electrode 32 in the horizontal direction.

[0218] The film formation properties of the first main electrode film 63 for the multiple source openings 54 are improved by the multiple first buried electrodes 62. This ensures an appropriate current path between the first main surface 3 and the first main electrode film 63. Such a configuration is effective in suppressing film formation defects caused by the multiple source openings 54 and reducing wiring resistance.

[0219] The semiconductor device 1A includes a plurality of first silicide portions 67 formed on the surface portions of the first main surface 3 that are exposed from the plurality of source openings 54. The plurality of first silicide portions 67 are formed in film form along the wall surfaces (side walls and bottom walls) of the plurality of source recesses 55, and are mechanically and electrically connected to the first base electrode film 61. In other words, the plurality of first silicide portions 67 are formed in the surface layer portions of the plurality of body regions 20, and electrically connect the plurality of first buried electrodes 62 to the plurality of body regions 20 via the first base electrode film 61.

[0220] The first silicide portion 67 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The first silicide portion 67 is preferably made of Ti silicide, Ni silicide, or Co silicide.

[0221] Semiconductor device 1A includes source finger electrodes 68 extending from source pad electrode 60 onto peripheral region 9. Source finger electrodes 68 transmit a source potential applied to source pad electrode 60 to peripheral region 9. In this embodiment, source finger electrodes 68 are routed from a portion of source pad electrode 60 (first pad portion 60 a) on the fourth side surface 5D side onto a portion of interlayer film 50 covering peripheral region 9.

[0222] The source finger electrodes 68 extend to above the termination region 40. In this embodiment, the source finger electrodes 68 are formed at an interval from the low concentration region 11 toward the active region 8 in a plan view, and face the high concentration region 10 (inner low concentration region 13) in the stacking direction. The source finger electrodes 68 do not face the low concentration region 11 in the stacking direction. Of course, the source finger electrodes 68 may be extended from the region above the high concentration region 10 to the region above the low concentration region 11, and may have a portion facing the low concentration region 11 in the stacking direction.

[0223] The source finger electrodes 68 are electrically connected to the termination region 40 via the outer openings 56. Specifically, the source finger electrodes 68 are electrically connected to the overlap region 41 of the termination region 40 via the outer openings 56. The source finger electrodes 68 extend in a strip shape along the termination region 40 (overlap region 41). The source finger electrodes 68 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0224] In this embodiment, the source finger electrode 68 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 60. The source finger electrode 68 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 6 ).

[0225] Like the source pad electrode 60, the source finger electrode 68 includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63. The first underlying electrode film 61 forms a lower layer portion of the source finger electrode 68 and covers the interlayer film 50 in the peripheral region 9. The first underlying electrode film 61 collectively covers the region of the interlayer film 50 in which the plurality of outer openings 56 are formed, and extends into the plurality of outer openings 56 from above the insulating surface 51. The first underlying electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the plurality of outer openings 56 in a film-like manner.

[0226] Similar to the source pad electrode 60, the first base electrode film 61 has a laminated structure including a first electrode film 64 and a second electrode film 65. The first electrode film 64 collectively covers the region of the interlayer film 50 where the multiple outer openings 56 are formed, and extends into the multiple outer openings 56 from above the insulating surface 51. The first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the multiple outer openings 56 in a film-like manner.

[0227] The first electrode film 64 covers the arcuate corners of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arcuate corners of the interlayer film 50 (second oxide film 53), and extends into the outer opening 56. The first electrode film 64 has a portion that extends in an arcuate shape at the arcuate corners. This improves the film-forming ability of the first electrode film 64 on the interlayer film 50 (wall surface of the outer opening 56). The first electrode film 64 extends along the wall surface of the outer opening 56 and covers the peripheral insulating film 43, the first oxide film 52, and the second oxide film 53.

[0228] The first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 64 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the termination region 40 (overlap region 41) within the outer recess 57.

[0229] The first electrode film 64 may cover the outer recess 57 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the outer recess 57. The first electrode film 64 may have a portion located on the bottom side of the outer recess 57 relative to the height position of the first main surface 3, and a portion located on the peripheral insulating film 43 side relative to the height position of the first main surface 3.

[0230] The second electrode film 65 is disposed on the first electrode film 64 and collectively covers the region of the interlayer film 50 where the multiple outer openings 56 are formed. The second electrode film 65 has a portion that covers the insulating surface 51 with the first electrode film 64 in between, and a portion that covers the wall surfaces of the multiple outer openings 56 with the first electrode film 64 in between.

[0231] The second electrode film 65, following the first electrode film 64, covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the outer opening 56. The second electrode film 65 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film formability of the second electrode film 65 on the interlayer film 50 (wall surface of the outer opening 56). The second electrode film 65 extends along the wall surface of the outer opening 56 and covers the peripheral insulating film 43, the first oxide film 52, and the second oxide film 53 with the first electrode film 64 sandwiched between them.

[0232] The second electrode film 65 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, sandwiching the first electrode film 64 therebetween, and is electrically connected to the termination region 40 (overlapping region 41) via the first electrode film 64. When the first electrode film 64 is located on the bottom side of the outer recess 57 with respect to the first main surface 3, the second electrode film 65 may have a portion that is located within the outer recess 57. When the first electrode film 64 has a portion that is located above the first main surface 3, the entire second electrode film 65 is located above the outer recess 57.

[0233] The multiple first buried electrodes 62 form middle layers of the source finger electrodes 68 and are buried in the multiple outer openings 56, respectively. In this embodiment, the multiple first buried electrodes 62 are buried in the multiple outer openings 56 in a one-to-one correspondence via a single first base electrode film 61. The multiple first buried electrodes 62 are electrically connected to the termination region 40 (overlap region 41) via the first base electrode film 61.

[0234] The first buried electrode 62 has a first buried electrode surface 66 exposed from the outer opening 56, exposing the insulating surface 51. Specifically, the first buried electrode 62 is buried in the outer opening 56 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51. In other words, the first buried electrode surface 66 is located closer to the first main surface 3 than the insulating surface 51.

[0235] The first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first base electrode film 61 sandwiched therebetween. The first buried electrode 62 has a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween. The first buried electrode 62 may be embedded at a distance from the arc corner portion of the interlayer film 50 toward the peripheral insulating film 43, with the entire arc corner portion exposed. The first buried electrode surface 66 is located closer to the insulating surface 51 than the height position of the first oxide film 52 in the outer opening 56. Of course, the first buried electrode surface 66 may also be located closer to the peripheral insulating film 43 than the height position of the first oxide film 52.

[0236] When the first underlying electrode film 61 is located on the bottom side of the outer recess 57 with respect to the first main surface 3, the first buried electrode 62 may have a portion located within the outer recess 57. When the first underlying electrode film 61 has a portion located above the first main surface 3, the entire first buried electrode 62 is located above the outer recess 57.

[0237] The first main electrode film 63 forms an upper layer of the source finger electrode 68 and covers the first base electrode film 61 and the plurality of first buried electrodes 62 in a film-like manner. The first main electrode film 63 is mechanically and electrically connected to the first base electrode film 61 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the plurality of first buried electrodes 62 in the portion covering the plurality of outer openings 56. The first main electrode film 63 is electrically connected to the termination region 40 (overlap region 41) via the first base electrode film 61 and the plurality of first buried electrodes 62.

[0238] The first main electrode film 63 is connected to the first buried electrode surface 66 at a height position closer to the first main surface 3 than the height position of the insulating surface 51. The first main electrode film 63 is connected to the first buried electrode surface 66 at a height position higher than the height position of the first oxide film 52. The first main electrode film 63 has a portion that covers the recess of the first buried electrode surface 66.

[0239] The first main electrode film 63 may have a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 sandwiched therebetween. When the first buried electrode 62 is located below the first oxide film 52, the first main electrode film 63 may be connected to the first buried electrode 62 in a region below the first oxide film 52.

[0240] The film formation properties of the first main electrode film 63 in the multiple outer openings 56 are improved by the multiple first buried electrodes 62. This ensures an appropriate current path between the termination region 40 (overlap region 41) and the first main electrode film 63. Such a configuration is effective in suppressing film formation defects caused by the multiple outer openings 56 and reducing wiring resistance.

[0241] The semiconductor device 1A includes a plurality of second silicide portions 69 formed on the surface portions of the first main surface 3 that are exposed from the plurality of outer openings 56. The plurality of second silicide portions 69 are formed in film form along the wall surfaces (side walls and bottom walls) of the plurality of outer recesses 57, and are mechanically and electrically connected to the first underlying electrode film 61. In other words, the plurality of second silicide portions 69 are formed in the surface layer portion of the termination region 40 (overlap region 41), and electrically connect the plurality of first buried electrodes 62 to the termination region 40 (overlap region 41) via the first underlying electrode film 61.

[0242] The second silicide portion 69 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide. The second silicide portion 69 is preferably made of Ti silicide, Ni silicide, or Co silicide. The second silicide portion 69 is particularly preferably made of the same type of silicide as the first silicide portion 67.

[0243] The semiconductor device 1A includes gate finger electrodes 70 selectively routed on the interlayer film 50. The gate finger electrodes 70 transmit a gate potential to the gate wiring 44. The gate finger electrodes 70 are routed on a portion of the interlayer film 50 that covers the gate wiring 44 (i.e., on the outer periphery region 9), and are electrically connected to the gate wiring 44 via a plurality of gate openings 58.

[0244] The gate finger electrode 70 is disposed in a region between the source pad electrode 60 and the source finger electrode 68 at a distance from the source pad electrode 60 and the source finger electrode 68. The gate finger electrode 70 extends in a strip shape along the gate wiring 44. The gate finger electrode 70 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0245] In this embodiment, the gate finger electrode 70 is formed in a band shape with four sides parallel to the periphery of the first main surface 3 and surrounds the source pad electrode 60. The gate finger electrode 70 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 6 ). The gate finger electrode 70 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 68 passes.

[0246] 10 and 11 , the gate finger electrode 70 includes a second underlying electrode film 71, at least one (in this embodiment, a plurality) second buried electrodes 72, and a second main electrode film 73. The second underlying electrode film 71 may be referred to as a "gate underlying electrode film," the second buried electrode 72 may be referred to as a "gate buried electrode," and the second main electrode film 73 may be referred to as a "gate main electrode film."

[0247] The second base electrode film 71 forms a lower layer of the gate finger electrode 70, and covers the interlayer film 50 in the peripheral region 9. The second base electrode film 71 collectively covers the region of the interlayer film 50 where the multiple gate openings 58 are formed, and extends into the multiple gate openings 58 from above the insulating surface 51. The second base electrode film 71 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.

[0248] The second base electrode film 71 has a layered structure including a first electrode film 74 layered on the interlayer film 50, and a second electrode film 75 layered on the first electrode film 74. It is preferable that the first electrode film 74 contains the same type of conductive material as the first electrode film 64 on the source side, and the second electrode film 75 contains the same type of conductive material as the second electrode film 65 on the source side. In this embodiment, the first electrode film 74 contains a Ti film, and the second electrode film 75 contains a TiN film.

[0249] The second base electrode film 71 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 74 (Ti film) or the second electrode film 75 (TiN film). The first electrode film 74 may have a thickness approximately equal to that of the first electrode film 64 on the source side. The second electrode film 75 may have a thickness approximately equal to that of the second electrode film 65 on the source side.

[0250] The first electrode film 74 collectively covers the region of the interlayer film 50 where the multiple gate openings 58 are formed, and extends into the multiple gate openings 58 from above the insulating surface 51. In other words, the first electrode film 74 has a portion that covers the insulating surface 51 in a film-like manner and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.

[0251] The first electrode film 74 covers the arcuate corners of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arcuate corners, and extends into the gate opening 58. The first electrode film 74 has a portion that extends in an arcuate shape at the arcuate corners. This improves the film-forming properties of the first electrode film 74 on the interlayer film 50 (wall surface of the gate opening 58).

[0252] The first electrode film 74 extends along the wall surface of the gate opening 58 and covers the first oxide film 52 and the second oxide film 53. The first electrode film 74 covers the gate wiring 44 at the bottom of each gate opening 58 in a film-like manner and is electrically connected to the gate wiring 44.

[0253] The second electrode film 75 collectively covers, in a film form, the region of the interlayer film 50 on the first electrode film 74 where the multiple gate openings 58 are formed. That is, the second electrode film 75 has a portion that covers the insulating surface 51 with the first electrode film 74 in between, and a portion that covers the wall surfaces of the multiple gate openings 58 with the first electrode film 74 in between.

[0254] The second electrode film 75, following the example of the first electrode film 74, covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the gate opening 58. The second electrode film 75 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film formability of the second electrode film 75 on the interlayer film 50 (wall surface of the gate opening 58).

[0255] The second electrode film 75 extends along the wall surface of the gate opening 58 and covers the first oxide film 52 and the second oxide film 53 with the first electrode film 74 sandwiched therebetween. The second electrode film 75 has a portion at the bottom of each gate opening 58 that covers the gate wiring 44 in a film-like manner with the first electrode film 74 sandwiched therebetween, and is electrically connected to the gate wiring 44 via the first electrode film 74.

[0256] The multiple second buried electrodes 72 form a middle layer of the gate finger electrode 70 and are buried in the multiple gate openings 58, respectively. The second buried electrodes 72 contain a conductive material different from the conductive material of the second base electrode film 71. The second buried electrodes 72 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. The second buried electrodes 72 preferably contain the same type of conductive material as the conductive material of the first buried electrodes 62. In this embodiment, the second buried electrodes 72 contain tungsten.

[0257] In this embodiment, the second buried electrodes 72 are buried in one-to-one correspondence with the gate openings 58 via a single second base electrode film 71. The second buried electrodes 72 are electrically connected to the gate wiring 44 via the second base electrode film 71 in the gate openings 58.

[0258] The second buried electrode 72 has a second buried electrode surface 76 exposed from the gate opening 58, exposing the insulating surface 51. The second buried electrode surface 76 may be referred to as a "gate buried electrode surface." The second buried electrode 72 is buried in the gate opening 58 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the second base electrode film 71 (second electrode film 75) that covers the insulating surface 51. In other words, the second buried electrode surface 76 is located closer to the first main surface 3 than the insulating surface 51.

[0259] The second buried electrode 72 covers the first oxide film 52 and the second oxide film 53 with the second base electrode film 71 sandwiched therebetween. The second buried electrode 72 has a portion that covers the arc corner portion of the interlayer film 50 with the second base electrode film 71 sandwiched therebetween. The second buried electrode 72 may be embedded at a distance from the arc corner portion of the interlayer film 50 toward the gate wiring 44, with the entire arc corner portion exposed. The second buried electrode surface 76 is located closer to the insulating surface 51 than the height position of the first oxide film 52. Of course, the second buried electrode surface 76 may also be located closer to the gate wiring 44 than the height position of the first oxide film 52.

[0260] The second main electrode film 73 forms an upper layer of the gate finger electrode 70, and covers the second base electrode film 71 and the plurality of second buried electrodes 72 in a film form. The second main electrode film 73 contains a conductive material different from the conductive material of the second base electrode film 71 and the conductive material of the second buried electrodes 72.

[0261] The second main electrode film 73 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The second main electrode film 73 preferably includes the same type of conductive material as the conductive material of the first main electrode film 63. The second main electrode film 73 may have a thickness approximately equal to that of the first main electrode film 63.

[0262] The second main electrode film 73 is mechanically and electrically connected to the second base electrode film 71 in a portion covering the insulating surface 51, and is mechanically and electrically connected to the plurality of second buried electrodes 72 in a portion covering the plurality of gate openings 58. As a result, the second main electrode film 73 is electrically connected to the gate wiring 44 via the second base electrode film 71 and the plurality of second buried electrodes 72.

[0263] The second main electrode film 73 is connected to the second buried electrode 72 at a height position closer to the first main surface 3 than the height position of the insulating surface 51. The second main electrode film 73 is connected to the second buried electrode surface 76 above the height position of the first oxide film 52. The second main electrode film 73 has a portion that covers the recess of the second buried electrode surface 76.

[0264] The second main electrode film 73 may have a portion that covers the arc corner portion of the interlayer film 50 with the second base electrode film 71 sandwiched therebetween. When the second buried electrode 72 is located below the first oxide film 52, the second main electrode film 73 may be connected to the second buried electrode 72 in a region below the first oxide film 52.

[0265] The film formation properties of the second main electrode film 73 for the multiple gate openings 58 are improved by the multiple second buried electrodes 72. This ensures an appropriate current path between the gate wiring 44 and the second main electrode film 73. This configuration is effective in suppressing film formation defects caused by the multiple gate openings 58 and reducing wiring resistance.

[0266] The semiconductor device 1A includes a gate pad electrode 80 disposed on the interlayer film 50. The gate pad electrode 80 is a terminal electrode to which a gate potential is applied from the outside. The gate pad electrode 80 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. The gate pad electrode 80 is disposed in a region between the source pad electrode 60 and the source finger electrodes 68 and spaced apart from the source pad electrode 60 and the source finger electrodes 68.

[0267] In this embodiment, the gate pad electrode 80 is disposed in a region on the third side surface 5C side of the first pad portion 60a, and is sandwiched between the second pad portion 60b and the third pad portion 60c. That is, the gate pad electrode 80 faces the first pad portion 60a in the first direction X, and faces the second pad portion 60b and the third pad portion 60c in the second direction Y.

[0268] The gate pad electrode 80 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate pad electrode 80 has a planar area less than that of the source pad electrode 60 (first pad portion 60a). The gate pad electrode 80 may have a planar area less than that of the second pad portion 60b (third pad portion 60c).

[0269] The gate pad electrode 80 is disposed on a portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 70. The gate pad electrode 80 may cover the plurality of gate electrodes 32 with the interlayer film 50 interposed therebetween, or may cover the gate wiring 44 with the interlayer film 50 interposed therebetween.

[0270] Similar to the gate finger electrode 70, the gate pad electrode 80 includes a second base electrode film 71 and a second main electrode film 73. The second base electrode film 71 forms a lower layer of the gate pad electrode 80 and covers the interlayer film 50 in a film-like manner. Similar to the gate finger electrode 70, the second base electrode film 71 has a layered structure including a first electrode film 74 and a second electrode film 75. The first electrode film 74 covers the interlayer film 50 in a film-like manner, and the second electrode film 75 covers the first electrode film 74 in a film-like manner. The second main electrode film 73 forms an upper layer of the gate pad electrode 80 and covers the second base electrode film 71 in a film-like manner.

[0271] Although not specifically shown in the drawings, the gate pad electrode 80 may have a plurality of second buried electrodes 72, similar to the gate finger electrode 70. In this case, the gate pad electrode 80 may be electrically connected to the gate wiring 44 via the plurality of second buried electrodes 72, similar to the gate finger electrode 70.

[0272] When a plurality of gate electrodes 32 are disposed below the gate pad electrode 80, the gate pad electrode 80 may be electrically connected to the plurality of gate electrodes 32 via a plurality of second buried electrodes 72. Of course, the gate pad electrode 80 does not have to have a plurality of second buried electrodes 72. In other words, the gate pad electrode 80 does not have to have an electrical connection portion to the plurality of gate electrodes 32 and an electrical connection portion to the gate wiring 44 in the region directly below it.

[0273] The gate potential applied to the gate pad electrode 80 is applied to the gate wiring 44 via the gate finger electrode 70. The gate potential is transmitted to the plurality of gate electrodes 32 via a wiring path (current path) along the gate wiring 44. This turns on the plurality of gate electrodes 32, controlling the on / off of the plurality of channel regions 26, 27.

[0274] The semiconductor device 1A includes a drain pad electrode 85 covering the second main surface 4. The drain pad electrode 85 is a terminal electrode to which a drain potential is applied from the outside. The drain pad electrode 85 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like. The drain pad electrode 85 is electrically connected to the base region 14.

[0275] The drain pad electrode 85 has a portion facing the high concentration region 10 (inner low concentration region 13) across the base region 14, and a portion facing the low concentration region 11 across the base region 14. The drain pad electrode 85 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain pad electrode 85 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0276] The breakdown voltage that can be applied between the source pad electrode 60 and the drain pad electrode 85 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0277] As described above, the semiconductor device 1A includes a chip 2, an n-type high-concentration region 10, and an n-type low-concentration region 11. The chip 2 has a first main surface 3. The high-concentration region 10 has a relatively high first impurity concentration, and is formed in a surface layer of the first main surface 3 on the inner side of the chip 2. The low-concentration region 11 has a second impurity concentration lower than the first impurity concentration of the high-concentration region 10, and is formed in a surface layer of the first main surface 3 on the peripheral side of the chip 2.

[0278] This configuration makes it possible to provide a semiconductor device 1A having a novel configuration, in which the resistance value on the inner side of the chip 2 can be reduced by utilizing the high concentration region 10, and the breakdown voltage on the periphery of the chip 2 can be improved by utilizing the low concentration region 11.

[0279] The chip 2 preferably includes SiC as an example of a wide bandgap semiconductor. In the case of a chip 2 including SiC, due to its characteristics (physical properties), an extremely high voltage is applied, and the breakdown voltage may decrease due to an electric field at the periphery of the chip 2. In this regard, in the case of the semiconductor device 1A, the breakdown voltage at the periphery side of the chip 2 including SiC is improved by utilizing the low concentration region 11.

[0280] The chip 2 may have first to fourth side surfaces 5A to 5D. In this case, the high-concentration region 10 may be formed at a distance from at least one of the first to fourth side surfaces 5A to 5D. The low-concentration region 11 may be exposed from at least one of the first to fourth side surfaces 5A to 5D. With this configuration, the formation region of the low-concentration region 11 is expanded to the extent that it is exposed from at least one of the first to fourth side surfaces 5A to 5D. This appropriately improves the breakdown voltage of the peripheral portion of the chip 2.

[0281] The low concentration region 11 preferably extends in a band shape along the high concentration region 10 in a plan view. With this configuration, the breakdown voltage on the peripheral side of the chip 2 is improved by utilizing the low concentration region 11 extending in a band shape. The low concentration region 11 preferably surrounds the high concentration region 10 in a plan view. With this configuration, the breakdown voltage on the peripheral side of the chip 2 is improved over the entire periphery of the high concentration region 10.

[0282] The low concentration region 11 is preferably connected to the high concentration region 10. This configuration ensures electrical continuity between the high concentration region 10 and the low concentration region 11. This suppresses discontinuity in the electric field between the high concentration region 10 and the low concentration region 11, thereby appropriately improving the breakdown voltage of the peripheral portion of the chip 2. In this case, the low concentration region 11 forms a region boundary 12 with the high concentration region 10 that extends in the thickness direction of the chip 2. The region boundary 12 may extend substantially perpendicular to the first main surface 3.

[0283] The semiconductor device 1A may include an n-type inner low-concentration region 13. The inner low-concentration region 13 may have a third impurity concentration lower than the first impurity concentration of the high-concentration region 10, and may be formed in a region below the high-concentration region 10 in the inner part of the chip 2. With this configuration, the resistance value on the inner side of the chip 2 can be reduced by utilizing the high-concentration region 10, and the withstand voltage on the inner side of the chip 2 can be improved by utilizing the inner low-concentration region 13.

[0284] In this case, it is preferable that the inner low-concentration region 13 is connected to the low-concentration region 11 at the periphery of the chip 2. This configuration ensures electrical continuity between the low-concentration region 11 and the inner low-concentration region 13. This suppresses discontinuity in the electric field between the low-concentration region 11 and the inner low-concentration region 13, and appropriately improves the breakdown voltage at the periphery of the chip 2.

[0285] The semiconductor device 1A may include a p-type body region 20 (first impurity region) formed in a surface layer portion of the high-concentration region 10 in a region on the inner side of the high-concentration region 10. The body region 20 forms a pn junction with the high-concentration region 10, and expands a depletion layer into the high-concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral edge side of the chip 2 by the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral edge side of the chip 2.

[0286] The semiconductor device 1A may include a p-type outer body region 21 (second impurity region) formed in one or both of the surface layer portion of the high concentration region 10 and the surface layer portion of the low concentration region 11 in a region on the peripheral edge side of the chip 2. The outer body region 21 may be formed in the surface layer portion of the high concentration region 10 and form a pn junction with the high concentration region 10.

[0287] In this case, the outer body region 21 expands the depletion layer into the high-concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral edge of the chip 2 by the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral edge side of the chip 2.

[0288] The outer body region 21 may be formed to expand a depletion layer that is integrated with the depletion layer of the body region 20. The outer body region 21 may be connected to the body region 20. The outer body region 21 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.

[0289] The semiconductor device 1A may include a p-type termination region 40 (third impurity region) formed in either or both of the surface layer portion of the high-concentration region 10 and the surface layer portion of the low-concentration region 11. The termination region 40 may be formed in the high-concentration region 10 and form a p-n junction with the high-concentration region 10. In this case, the termination region 40 expands the depletion layer into the high-concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral edge of the chip 2 by the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral edge side of the chip 2.

[0290] The termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the body region 20. The termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the outer body region 21. The termination region 40 may be connected to the outer body region 21. The termination region 40 may have a p-type impurity concentration that is different from the p-type impurity concentration of the body region 20.

[0291] The termination region 40 may have an extension portion extending from the high-concentration region 10 to the low-concentration region 11. The extension portion of the termination region 40 forms a pn junction with the low-concentration region 11, and spreads the depletion layer into the low-concentration region 11 when a reverse bias voltage is applied. With this configuration, the depletion layer spreads appropriately from the termination region 40 to the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral side of the chip 2.

[0292] The semiconductor device 1A may include a p-type field region 42 (fourth impurity region) formed in a surface layer portion of the low-concentration region 11. The field region 42 forms a pn junction with the low-concentration region 11, and expands a depletion layer into the low-concentration region 11 when a reverse bias voltage is applied. The range of the depletion layer in the field region 42 is expanded by the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral edge side of the chip 2.

[0293] The field region 42 is preferably formed at a distance from the high concentration region 10 toward the periphery of the chip 2. The field region 42 is preferably formed at a distance from the body region 20 toward the periphery of the chip 2. The field region 42 is preferably formed at a distance from the outer body region 21 toward the periphery of the chip 2. The field region 42 is preferably formed at a distance from the termination region 40 toward the periphery of the chip 2.

[0294] The semiconductor device 1A may include an n-type base region 14. The base region 14 may have a fourth impurity concentration lower than the first impurity concentration of the high-concentration region 10, and may be formed in a region below the high-concentration region 10 on the inner side of the chip 2. The base region 14 may have a portion extending from the inner side of the chip 2 toward the periphery and located in a region below the low-concentration region 11.

[0295] From another perspective, the semiconductor device 1A includes a chip 2, an active region 8, a peripheral region 9, a high-concentration region 10, and a low-concentration region 11. The chip 2 has a first main surface 3. The active region 8 is provided in an inner portion of the first main surface 3. The peripheral region 9 is provided in a peripheral portion of the first main surface 3.

[0296] The high-concentration region 10 has a first impurity concentration and is formed in the surface layer of the first main surface 3 in the active region 8. The low-concentration region 11 has a second impurity concentration lower than the first impurity concentration of the high-concentration region 10 and is formed in the surface layer of the first main surface 3 in the peripheral region 9. This configuration makes it possible to provide a semiconductor device 1A having a novel configuration. With this semiconductor device 1A, the resistance value on the active region 8 side can be reduced by utilizing the high-concentration region 10, and the breakdown voltage on the peripheral region 9 side can be improved by utilizing the low-concentration region 11.

[0297] The chip 2 preferably contains SiC as an example of a wide bandgap semiconductor. In the case of a chip 2 containing SiC, due to its characteristics (physical properties), an extremely high voltage is applied, and the breakdown voltage may decrease due to an electric field at the periphery of the chip 2. In this regard, in the case of the semiconductor device 1A, the breakdown voltage on the outer peripheral region 9 side of the chip 2 containing SiC is improved by utilizing the low concentration region 11.

[0298] The chip 2 may have first to fourth side surfaces 5A to 5D. In this case, the high-concentration region 10 may be formed at a distance from at least one of the first to fourth side surfaces 5A to 5D. The low-concentration region 11 may be exposed from at least one of the first to fourth side surfaces 5A to 5D. With this configuration, the formation region of the low-concentration region 11 is expanded to a range exposed from at least one of the first to fourth side surfaces 5A to 5D. This appropriately improves the breakdown voltage on the peripheral region 9 side.

[0299] It is preferable that the low concentration region 11 extends in a band shape along the high concentration region 10 in a plan view. With this configuration, the breakdown voltage on the outer peripheral region 9 side is improved by utilizing the low concentration region 11 extending in a band shape. It is preferable that the low concentration region 11 surrounds the high concentration region 10 in a plan view. With this configuration, the breakdown voltage on the outer peripheral region 9 side is improved all around the high concentration region 10.

[0300] The low concentration region 11 is preferably connected to the high concentration region 10. This configuration ensures electrical continuity between the high concentration region 10 and the low concentration region 11. This suppresses discontinuity of the electric field between the high concentration region 10 and the low concentration region 11, and appropriately improves the breakdown voltage on the peripheral region 9 side. In this case, the low concentration region 11 forms a region boundary 12 with the high concentration region 10 that extends in the thickness direction of the chip 2. The region boundary 12 may extend substantially perpendicular to the first main surface 3.

[0301] The semiconductor device 1A may include an n-type inner low-concentration region 13. The inner low-concentration region 13 may have a third impurity concentration lower than the first impurity concentration of the high-concentration region 10, and may be formed in a region below the high-concentration region 10 on the active region 8 side. With this configuration, the resistance value on the active region 8 side can be reduced by utilizing the high-concentration region 10, and the breakdown voltage on the active region 8 side can be improved by utilizing the inner low-concentration region 13.

[0302] In this case, it is preferable that the inner low-concentration region 13 is connected to the low-concentration region 11 on the side of the outer circumferential region 9. This configuration ensures electrical continuity between the low-concentration region 11 and the inner low-concentration region 13. This suppresses discontinuity of the electric field between the low-concentration region 11 and the inner low-concentration region 13, and appropriately improves the breakdown voltage on the side of the outer circumferential region 9.

[0303] The semiconductor device 1A may include a p-type body region 20 (first impurity region) formed in a surface layer portion of the high-concentration region 10 on the active region 8 side. The body region 20 forms a pn junction with the high-concentration region 10, and expands a depletion layer into the high-concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral region 9 side by the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.

[0304] The semiconductor device 1A may include a p-type outer body region 21 (second impurity region) formed in one or both of the surface layer portion of the high concentration region 10 and the surface layer portion of the low concentration region 11 in the region on the peripheral region 9 side. The outer body region 21 may be formed in the surface layer portion of the high concentration region 10 and form a pn junction with the high concentration region 10.

[0305] In this case, the outer body region 21 expands the depletion layer into the high concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward the peripheral region 9 by the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.

[0306] The outer body region 21 may be formed to expand a depletion layer that is integrated with the depletion layer of the body region 20. The outer body region 21 may be connected to the body region 20. The outer body region 21 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.

[0307] The semiconductor device 1A may include a p-type termination region 40 (third impurity region) formed in one or both of the surface layer portion of the high concentration region 10 and the surface layer portion of the low concentration region 11 in the region on the peripheral region 9 side. The termination region 40 may be formed in the high concentration region 10 and form a pn junction with the high concentration region 10.

[0308] In this case, termination region 40 expands the depletion layer into high-concentration region 10 when a reverse bias voltage is applied. With this configuration, the range of the depletion layer is expanded toward peripheral region 9 by low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.

[0309] The termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the body region 20. The termination region 40 may be formed to expand the depletion layer that is integrated with the depletion layer of the outer body region 21. The termination region 40 may be connected to the outer body region 21. The termination region 40 may have a p-type impurity concentration that is different from the p-type impurity concentration of the body region 20.

[0310] The termination region 40 may have an extension portion extending from the high-concentration region 10 to the low-concentration region 11. The extension portion of the termination region 40 forms a pn junction with the low-concentration region 11, and spreads the depletion layer into the low-concentration region 11 when a reverse bias voltage is applied. With this configuration, the depletion layer spreads appropriately from the termination region 40 to the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.

[0311] The semiconductor device 1A may include a p-type field region 42 (fourth impurity region) formed in the surface layer of the low-concentration region 11 in the peripheral region 9. The field region 42 forms a pn junction with the low-concentration region 11, and expands a depletion layer into the low-concentration region 11 when a reverse bias voltage is applied. The range of the depletion layer in the field region 42 is expanded by the low-concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.

[0312] The field region 42 is preferably formed at a distance from the high concentration region 10 toward the periphery of the chip 2. The field region 42 is preferably formed at a distance from the body region 20 toward the periphery of the chip 2. The field region 42 is preferably formed at a distance from the outer body region 21 toward the periphery of the chip 2. The field region 42 is preferably formed at a distance from the termination region 40 toward the periphery of the chip 2.

[0313] It is preferable that field region 42 extends in a band shape along high-concentration region 10 in a plan view. With this configuration, the depletion layer spreads in a band shape from field region 42 toward low-concentration region 11. This appropriately improves the breakdown voltage on the side of peripheral region 9. It is preferable that field region 42 surrounds high-concentration region 10 in a plan view. With this configuration, the depletion layer spreads from field region 42 toward low-concentration region 11 so as to surround high-concentration region 10. This appropriately improves the breakdown voltage on the side of peripheral region 9.

[0314] A plurality of field regions 42 may be formed at intervals in the surface layer portion of the low concentration region 11. With this configuration, a plurality of depletion layers spread from the plurality of field regions 42 toward the low concentration region 11. This appropriately improves the breakdown voltage on the peripheral region 9 side.

[0315] The semiconductor device 1A may include an n-type base region 14. The base region 14 may have a fourth impurity concentration lower than the first impurity concentration of the high-concentration region 10, and may be formed in a region below the high-concentration region 10 in the active region 8. The base region 14 may have a portion extending from the active region 8 toward the peripheral region 9 and located in a region below the low-concentration region 11.

[0316] The semiconductor device 1A may include a transistor structure Tr as an example of a device structure formed in the active region 8. In this case, the transistor structure Tr may include a high-concentration region 10. According to this configuration, the resistance value of the transistor structure Tr can be reduced by utilizing the high-concentration region 10, and the breakdown voltage of the transistor structure Tr can be improved by utilizing the low-concentration region 11.

[0317] 12 is a cross-sectional view showing a semiconductor device 1B according to a second embodiment. The semiconductor device 1B has a layout that is a modification of the high-concentration region 10 according to the semiconductor device 1A. Specifically, the high-concentration region 10 is formed in the second semiconductor layer 7 throughout the entire thickness range between the first major surface 3 and the bottom of the second semiconductor layer 7 (first semiconductor layer 6), and is connected to the first semiconductor layer 6. In other words, in this embodiment, the semiconductor device 1B does not have an inner low-concentration region 13.

[0318] In this embodiment, the high concentration region 10 is formed substantially perpendicular to the first main surface 3 in a cross-sectional view. For example, the high concentration region 10 may be formed by introducing n-type impurities into the entire thickness range of the n-type second semiconductor layer 7.

[0319] The low-concentration region 11 is formed in the same layout as in the semiconductor device 1A. In this embodiment, the inner edge of the low-concentration region 11 is connected to the periphery of the high-concentration region 10 throughout the entire thickness range of the high-concentration region 10. In other words, the region boundary 12 crosses the depth position of the middle part of the second semiconductor layer 7 in the thickness direction. In this embodiment, the lower end of the region boundary 12 is connected to the first semiconductor layer 6.

[0320] Fig. 13 is a cross-sectional view showing a semiconductor device 1C according to a third embodiment. Fig. 14 is a cross-sectional view showing a modified example of the semiconductor device 1C shown in Fig. 13. The semiconductor device 1C has a layout in which the high-concentration region 10 according to the semiconductor device 1B is modified.

[0321] Specifically, the highly doped region 10 is formed in a tapered shape in a cross-sectional view, with its horizontal width gradually increasing in the thickness direction from the first main surface 3. That is, the peripheral portion of the highly doped region 10 slopes obliquely downward from the inner portion (active region 8) of the chip 2 toward the peripheral portion (outer peripheral region 9) of the chip 2. The peripheral portion (inclined peripheral portion) of the highly doped region 10 is located in the outer peripheral region 9.

[0322] Such a configuration is effective in reducing the resistance of the current spreading path when considering the current flowing in an oblique direction (i.e., current spreading) between the inner portion of chip 2 and the peripheral portion of chip 2. For example, the inclined portion of high-concentration region 10 may be formed by introducing n-type impurities in a direction oblique to first main surface 3 by oblique ion implantation.

[0323] The low-concentration region 11 has an inner edge that slopes downward in accordance with the peripheral edge (inclined peripheral edge) of the high-concentration region 10. In other words, the low-concentration region 11 is formed in a tapered shape in which its horizontal width gradually decreases from the first main surface 3 toward the thickness direction in a cross-sectional view. This configuration is effective in reducing the resistance of the current spreading path while increasing the breakdown voltage on the peripheral side of the chip 2.

[0324] The low-concentration region 11 and the high-concentration region 10 form a region boundary 12 that slopes obliquely downward. The region boundary 12 has an upper end on the first main surface 3 side, a lower end on the second main surface 4 side, and a sloped portion between the upper and lower ends. The upper end is located on the inner side of the chip 2 in the outer peripheral region 9. The lower end is located on the peripheral edge side of the chip 2 in the outer peripheral region 9. The sloped portion slopes obliquely downward from the upper end to the lower end in the outer peripheral region 9.

[0325] The inclination angle θ (absolute value) of the inclined portion may be greater than 0° and equal to or less than 75°. The inclination angle θ is the angle formed by the inclined portion with a virtual vertical line L (virtual perpendicular line) that is perpendicular to the first main surface 3 in a cross-sectional view when the virtual vertical line L is set so as to pass through the upper end of the region boundary portion 12.

[0326] The tilt angle θ may have a value belonging to at least one of the ranges of more than 0° to 15°, 15° to 30°, 30° to 45°, 45° to 60°, and 60° to 75°. The tilt angle θ is preferably 20° to 60°. The tilt angle θ is particularly preferably 30° to 50°.

[0327] At least the innermost field region 42 of the plurality of field regions 42 is preferably formed in the surface layer of the low-concentration region 11 at a distance from the upper end of the high-concentration region 10 (the upper end of the region boundary 12) toward the periphery of the chip 2. The innermost field region 42 may face the inclined portion of the high-concentration region 10 (the inclined portion of the region boundary 12) in the thickness direction, with part of the low-concentration region 11 sandwiched between them.

[0328] It is particularly preferable that the plurality of field regions 42 be formed in the surface layer of the low-concentration region 11 at intervals from the lower end of the high-concentration region 10 (the lower end of the region boundary 12) toward the periphery of the chip 2. In other words, it is particularly preferable that the plurality of field regions 42 do not face the high-concentration region 10 in the thickness direction.

[0329] 14 , semiconductor device 1C may have inner low-concentration region 13. That is, similar to the case of semiconductor device 1A, high-concentration region 10 may be formed at an interval from the bottom of second semiconductor layer 7 toward the first main surface, and may face first semiconductor layer 6 across part of second semiconductor layer 7. In this case, inner low-concentration region 13 passes below the lower end of high-concentration region 10 (the lower end of region boundary portion 12) and is connected to a region on the bottom side of low-concentration region 11 in peripheral region 9.

[0330] 15 is a cross-sectional view showing a semiconductor device 1D according to a fourth embodiment. The semiconductor device 1D has a layout that is a modification of the layout within the chip 2 according to the semiconductor device 1C. Specifically, in this embodiment, the low-concentration region 11 is formed at a distance from the bottom of the second semiconductor layer 7 toward the first main surface 3, and has a bottom located within the second semiconductor layer 7.

[0331] The low concentration region 11 may cross the depth position of the intermediate portion of the second semiconductor layer 7 in the thickness direction. In other words, the thickness of the low concentration region 11 may be equal to or greater than half the thickness of the second semiconductor layer 7. Of course, the low concentration region 11 may be formed at an interval from the depth position of the intermediate portion of the second semiconductor layer 7 toward the first main surface 3. In other words, the thickness of the low concentration region 11 may be less than half the thickness of the second semiconductor layer 7.

[0332] In this embodiment, the semiconductor device 1D includes an n-type outer heavily doped region 15 formed in a region below the lightly doped region 11 in the surface layer portion of the first main surface 3. The outer heavily doped region 15 may also be referred to as a "fifth region," a "fourth drift region," a "second heavily doped drift region," or the like. The outer heavily doped region 15 has a fifth impurity concentration that is higher than the second impurity concentration of the lightly doped region 11. The fifth impurity concentration is 1×10 １５ cm －３ 5x10 or more １６cm －３ It may be the following:

[0333] The outer high-concentration region 15 is formed on the peripheral edge side of the chip 2 relative to the high-concentration region 10. The outer high-concentration region 15 extends in a layer shape along the low-concentration region 11 in the peripheral region 9 and is connected to the low-concentration region 11 in the thickness direction. As a result, the outer high-concentration region 15 is electrically connected to the low-concentration region 11.

[0334] The outer heavily doped region 15 is formed as a low resistance region (second low resistance region) in the peripheral region 9 that has a lower resistance value than the low concentration region 11. When taking into consideration the current flowing diagonally between the inner portion of the chip 2 and the peripheral portion of the chip 2 (i.e., current spreading), this configuration is effective in reducing the resistance value of the current spreading path.

[0335] The outer high-concentration region 15 is formed in the peripheral region 9 in a region between the periphery of the first main surface 3 and the high-concentration region 10, and extends in a band-like shape along the high-concentration region 10 (active region 8) in a planar view. The outer high-concentration region 15 has a portion extending in a band-like shape in the first direction X and a portion extending in a band-like shape in the second direction Y in a planar view, and partitions the high-concentration region 10 (active region 8) from multiple directions. In this embodiment, the outer high-concentration region 15 is formed in a ring-like shape (a quadrangular ring-like shape in this embodiment) surrounding the high-concentration region 10 (active region 8) in a planar view. The outer high-concentration region 15 is preferably formed in the entire region below the low-concentration region 11.

[0336] The outer high-concentration region 15 has an outer edge portion on the peripheral side of the first main surface 3 and an inner edge portion on the inward side of the first main surface 3. The inner edge portion of the outer high-concentration region 15 is connected to the peripheral edge portion of the high-concentration region 10. In this embodiment, the outer high-concentration region 15 is connected to the high-concentration region 10 in the outer peripheral region 9. As a result, the outer high-concentration region 15 is electrically connected to the high-concentration region 10.

[0337] The fifth impurity concentration of the outer high-concentration region 15 is preferably approximately equal to the first impurity concentration of the region on the bottom side of the high-concentration region 10. The outer edge of the outer high-concentration region 15 is preferably exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the outer edge of the outer high-concentration region 15 is exposed from all of the first to fourth side surfaces 5A to 5D.

[0338] In this embodiment, the outer heavily doped region 15 is formed in the second semiconductor layer 7. That is, the semiconductor device 1D has a multi-layer structure including the low-concentration region 11 and the outer heavily doped region 15 in the peripheral portion (peripheral region 9) of the second semiconductor layer 7. For example, the outer heavily doped region 15 may be formed by introducing n-type impurities into a portion (a region on the bottom side) of the n-type second semiconductor layer 7.

[0339] The outer heavily doped region 15 is formed in the second semiconductor layer 7 throughout the entire thickness range between the bottom of the second semiconductor layer 7 (first semiconductor layer 6) and the bottom of the low concentration region 11, and is connected to the first semiconductor layer 6. When the low concentration region 11 crosses the depth position of the intermediate portion of the second semiconductor layer 7 in the thickness direction, the thickness of the outer heavily doped region 15 is less than half the thickness of the second semiconductor layer 7. When the low concentration region 11 is formed closer to the first main surface 3 than the intermediate portion of the second semiconductor layer 7, the thickness of the outer heavily doped region 15 is greater than half the thickness of the second semiconductor layer 7.

[0340] Similar to the semiconductor device 1A, the plurality of field regions 42 are formed in the surface layer portion of the low concentration region 11. In this embodiment, the plurality of field regions 42 are formed at intervals from the bottom of the low concentration region 11 toward the first main surface 3, and face the outer high concentration region 15 with a part of the low concentration region 11 in between.

[0341] The multiple field regions 42 are preferably formed at intervals from the intermediate portion of the low-concentration region 11 toward the first main surface 3. In other words, the thickness of the multiple field regions 42 may be less than half the thickness of the low-concentration region 11. Of course, the multiple field regions 42 may cross the intermediate portion of the low-concentration region 11 in the thickness direction. In other words, the thickness of the multiple field regions 42 may be half or more the thickness of the low-concentration region 11.

[0342] In this embodiment, the drain pad electrode 85 has a portion facing the high concentration region 10 across the base region 14, and a portion facing the low concentration region 11 (outer high concentration region 15) across the base region 14.

[0343] Fig. 16 is an enlarged plan view showing a main portion of the active region 8 of a semiconductor device 1E according to the fifth embodiment. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 16. Fig. 17 shows an example in which the configuration of the semiconductor device 1A (high concentration region 10, low concentration region 11, etc.) is applied to the semiconductor device 1E. Of course, the configurations of the semiconductor devices 1B to 1D (high concentration region 10, low concentration region 11, outer high concentration region 15, etc.) may also be applied to the semiconductor device 1E.

[0344] 16 and 17, a semiconductor device 1E is a semiconductor switching device having a trench gate type transistor structure Tr as an example of a device structure in an active region 8 instead of a planar gate type transistor structure Tr.

[0345] The semiconductor device 1E has a single body region 20 instead of the multiple body regions 20. The single body region 20 is formed in the surface layer portion of the first main surface 3 throughout the entire active region 8. The single body region 20 is formed in the surface layer portion of the high-concentration region 10. The single body region 20 is formed at an interval from the bottom of the high-concentration region 10 toward the first main surface 3, and faces the inner low-concentration region 13 (base region 14) with a part of the high-concentration region 10 in between.

[0346] The single body region 20 is preferably formed at a distance from the intermediate portion of the high-concentration region 10 toward the first main surface 3. Of course, the single body region 20 may cross the depth position of the intermediate portion of the high-concentration region 10 in the thickness direction. The single body region 20 is exposed from the first main surface 3.

[0347] The single body region 20 forms a pn junction (pn junction diode: body diode) with the high-concentration region 10. The single body region 20 spreads a depletion layer into the high-concentration region 10 when a reverse bias voltage is applied. The depletion layer spreads from the high-concentration region 10 toward the low-concentration region 11 in the horizontal direction along the first main surface 3.

[0348] As in the case of the semiconductor device 1A, the aforementioned outer body region 21 is formed in the surface layer portion of the first main surface 3 (high concentration region 10) in the peripheral region 9. In this embodiment, the outer body region 21 is connected to the single body region 20 around the entire periphery of the active region 8. The outer body region 21 can be considered to be formed by the peripheral portion of the single body region 20.

[0349] The semiconductor device 1E has, in the active region 8, a plurality of trench electrode type gate structures 35 instead of the plurality of planar electrode type gate structures 30. The plurality of gate structures 35 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 35 are arranged in a stripe shape extending in the second direction Y. Furthermore, the extension direction of the plurality of gate structures 35 coincides with the off-direction of the SiC single crystal.

[0350] In this embodiment, the plurality of gate structures 35 are formed at intervals from the bottom of the high concentration region 10 toward the first main surface 3, and face the inner low concentration region 13 (base region 14) across a part of the high concentration region 10. In other words, the plurality of gate structures 35 are formed shallower than the high concentration region 10, and face the low concentration region 11 in the horizontal direction.

[0351] Each of the multiple gate structures 35 includes a trench 36, an insulating film 31, and a gate electrode 32. The trench 36 is formed in the first main surface 3 and defines the wall surfaces (side walls and bottom wall) of the gate structure 35. The insulating film 31 coats the wall surfaces of the trench 36 in a film-like manner. The gate electrode 32 is buried in the trench 36 with the insulating film 31 sandwiched therebetween.

[0352] The aforementioned multiple source regions 23, 24 are formed on both sides of multiple gate structures 35 in a surface layer portion of the single body region 20. The first source region 23 is formed along one sidewall of the corresponding gate structure 35 and faces the gate electrode 32 with the insulating film 31 interposed therebetween. The second source region 24 is formed along the other sidewall of the corresponding gate structure 35 and faces the gate electrode 32 with the insulating film 31 interposed therebetween.

[0353] The plurality of source regions 23, 24 each extend in a strip shape along the extension direction of the plurality of gate structures 35. The plurality of source regions 23, 24 are formed at intervals from the bottom of the single body region 20 toward the first main surface 3, and face the high-concentration region 10 with a part of the single body region 20 interposed therebetween.

[0354] The aforementioned plurality of contact regions 25 are respectively formed in regions between the plurality of source regions 23, 24 in the surface layer portion of the single body region 20. The plurality of contact regions 25 extend in strip shapes along the extension direction of the plurality of gate structures 35. The plurality of contact regions 25 are formed at intervals from the bottom of the single body region 20 toward the first main surface 3, and face the high-concentration region 10 with a part of the single body region 20 sandwiched therebetween.

[0355] The aforementioned multiple channel regions 26, 27 are defined in the bottom (high concentration region 10) of the single body region 20 and in the region between the multiple source regions 23, 24. The first channel region 26 is defined in the region between the bottom (high concentration region 10) of the single body region 20 and the first source region 23, and forms a current path extending in the stacking direction along the sidewall of the gate structure 35. The second channel region 27 is defined in the region between the bottom (high concentration region 10) of the single body region 20 and the second source region 24, and forms a current path extending in the stacking direction along the sidewall of the gate structure 35.

[0356] When a gate potential is applied to the gate electrode 32, the channel regions 26, 27 are turned on, and a drain current flows between the heavily doped region 10 and the source regions 23, 24 via the channel regions 26, 27 (body region 20). In this manner, a trench gate type transistor structure Tr including the heavily doped region 10 is formed in the inner part (active region 8) of the chip 2.

[0357] Similar to the semiconductor device 1A, the semiconductor device 1E includes a termination region 40 (overlap region 41), a plurality of field regions 42, a peripheral insulating film 43, a gate wiring 44, an interlayer film 50, a plurality of source openings 54, a plurality of source recesses 55, a plurality of outer openings 56, a plurality of outer recesses 57, a plurality of gate openings 58, a source pad electrode 60, a plurality of first silicide portions 67, a source finger electrode 68, a plurality of second silicide portions 69, a gate finger electrode 70, a gate pad electrode 80, and a drain pad electrode 85. Description of these configurations is omitted because they are similar to those of the semiconductor device 1A.

[0358] Fig. 18 is a plan view showing a semiconductor device 1F according to a sixth embodiment. Fig. 19 is a cross-sectional view taken along line XIX-XIX shown in Fig. 18. The semiconductor device 1F is a semiconductor rectifier having a diode structure Di as an example of a device structure instead of a transistor structure Tr. In this embodiment, the diode structure Di is a Schottky Barrier Diode structure (SBD structure).

[0359] 18 and 19, similarly to semiconductor device 1A, semiconductor device 1F includes chip 2, first semiconductor layer 6, second semiconductor layer 7, active region 8, peripheral region 9, high concentration region 10, low concentration region 11, region boundary 12, inner low concentration region 13, termination region 40, and a plurality of field regions 42. Description of these configurations will be omitted as they are similar to those of semiconductor device 1A.

[0360] The semiconductor device 1F includes an interlayer film 90 that selectively covers the first main surface 3. The interlayer film 90 may have a single layer structure or a multilayer structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer film 90 has a single layer structure including a silicon oxide film.

[0361] In the peripheral region 9, the interlayer film 90 covers the low concentration region 11, the termination region 40, and the plurality of field regions 42. In this embodiment, the interlayer film 90 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer film 90 may be formed at a distance inward from the periphery of the first main surface 3, exposing the second semiconductor layer 7 (low concentration region 11) from the periphery of the first main surface 3.

[0362] Semiconductor device 1F includes contact opening 91 that exposes high-concentration region 10 in interlayer film 90. In this embodiment, contact opening 91 has an opening wall located above termination region 40, exposing high-concentration region 10 and the inner edge of termination region 40. The opening wall is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of chip 2 in a plan view, exposing the entire inner periphery of termination region 40.

[0363] The semiconductor device 1F includes an anode pad electrode 92 disposed on the first main surface 3. The anode pad electrode 92 is a terminal electrode to which an anode potential is externally applied. The anode pad electrode 92 may also be referred to as a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like. The anode pad electrode 92 is disposed inward from the periphery of the chip 2 at a distance. The anode pad electrode 92 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the chip 2 in a plan view.

[0364] The anode pad electrode 92 extends into the contact opening 91 from above the interlayer film 90 and is electrically connected to the inner edge of the high-concentration region 10 and the termination region 40 within the contact opening 91. The anode pad electrode 92 forms a Schottky junction with the high-concentration region 10, thereby forming a diode structure Di including the high-concentration region 10. The anode pad electrode 92 has a portion within the contact opening 91 that faces the high-concentration region 10 with the termination region 40 in between.

[0365] The anode pad electrode 92 has a peripheral portion that covers the termination region 40 with the interlayer film 90 sandwiched therebetween. That is, the peripheral portion of the anode pad electrode 92 has a portion that faces the high-concentration region 10 in the stacking direction. The peripheral portion of the anode pad electrode 92 may have a portion that crosses the region boundary 12 in the horizontal direction and covers the low-concentration region 11 with the interlayer film 90 sandwiched therebetween.

[0366] The peripheral edge of the anode pad electrode 92 may be formed at a distance inward from the innermost field region 42. The peripheral edge of the anode pad electrode 92 may have a portion that covers the innermost field region 42 with the interlayer film 90 therebetween. The peripheral edge of the anode pad electrode 92 may cover multiple field regions 42 with the interlayer film 90 therebetween.

[0367] The semiconductor device 1F includes a cathode pad electrode 93 covering the second main surface 4. The cathode pad electrode 93 is a terminal electrode to which a cathode potential is applied from the outside. The cathode pad electrode 93 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. The cathode pad electrode 93 is electrically connected to the base region 14.

[0368] In this embodiment, the cathode pad electrode 93 has a portion facing the high-concentration region 10 across the base region 14, and a portion facing the low-concentration region 11 across the base region 14. The cathode pad electrode 93 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The cathode pad electrode 93 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0369] The breakdown voltage that can be applied between the anode pad electrode 92 and the cathode pad electrode 93 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0370] The configurations of semiconductor devices 1B to 1D according to the second to fourth embodiments (see FIGS. 12 to 15) described above can be applied to the configuration of semiconductor device 1F according to the sixth embodiment (see FIG. 19). In FIGS. 20 to 22, these configurations are shown as seventh to ninth embodiments. FIG. 20 is a cross-sectional view showing semiconductor device 1G according to the seventh embodiment. FIG. 21 is a cross-sectional view showing semiconductor device 1H according to the eighth embodiment. FIG. 22 is a cross-sectional view showing semiconductor device 1I according to the ninth embodiment.

[0371] 20, semiconductor device 1G has a configuration in which semiconductor device 1F is combined with high-concentration region 10 and low-concentration region 11 of semiconductor device 1B (see FIG. 12). With reference to FIG. 21, semiconductor device 1H has a configuration in which semiconductor device 1F is combined with high-concentration region 10 and low-concentration region 11 of semiconductor device 1C (see FIGS. 13 and 14). With reference to FIG. 22, semiconductor device 1I has a configuration in which semiconductor device 1F is combined with high-concentration region 10, low-concentration region 11, and outer high-concentration region 15 of semiconductor device 1D (see FIG. 15).

[0372] Modified examples that can be applied to the semiconductor devices 1A to 1I according to the first to ninth embodiments are shown below. Fig. 23 is a cross-sectional view showing a modified example of the outer body region 21. Fig. 23 illustrates a configuration in which the modified example is applied to the semiconductor device 1A (first embodiment), but the modified example can be applied to all of the semiconductor devices 1A to 1I (first to ninth embodiments).

[0373] In each of the above-described embodiments, the outer body region 21 is formed at a distance inward from the periphery of the high-concentration region 10. However, as shown in Fig. 23 , the outer edge of the outer body region 21 may cross the periphery of the high-concentration region 10 and be located in the low-concentration region 11.

[0374] That is, the outer body region 21 may be located in the surface layer of the low concentration region 11 in the peripheral region 9 and may have a portion (outer edge portion) that forms a pn junction with the low concentration region 11. In this configuration, the depletion layer extends directly from the outer body region 21 to the low concentration region 11. Therefore, the range of the depletion layer is appropriately expanded in the peripheral portion (peripheral region 9) of the chip 2.

[0375] In this case, termination region 40 is located on the peripheral side of chip 2 relative to the peripheral edge of high concentration region 10 in the surface layer portion of low concentration region 11. In other words, the entire termination region 40 is located in the surface layer portion of low concentration region 11. The inner edge of termination region 40 is connected to the outer edge of outer body region 21 in the surface layer portion of low concentration region 11. In other words, termination region 40 forms an overlap region 41 with outer body region 21 in the surface layer portion of low concentration region 11.

[0376] In this configuration, the depletion layer extends directly from the entire termination region 40 to the low-concentration region 11. Therefore, the range of the depletion layer is appropriately expanded in the peripheral portion (peripheral region 9) of the chip 2. Of course, the termination region 40 has a p-type impurity concentration approximately equal to the p-type impurity concentration of the outer body region 21, and may be formed as part (draw-out portion) of the outer body region 21.

[0377] FIG. 24 is a cross-sectional view showing a modified example of the field region 42. While FIG. 24 illustrates a configuration in which the modified example is applied to the semiconductor device 1A (first embodiment), the modified example is applicable to all of the semiconductor devices 1A to 1I (first to ninth embodiments). In each of the above-described embodiments, an example was shown in which multiple field regions 42 were formed in the surface layer portion of the low-concentration region 11. However, as shown in FIG. 24, a single field region 42 may also be formed in the surface layer portion of the low-concentration region 11.

[0378] The single field region 42 is formed in a region between the termination region 40 and the outer body region 21, spaced inward from the periphery of the first main surface 3. The single field region 42 extends in a band shape along the termination region 40 in a plan view. The single field region 42 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.

[0379] The single field region 42 surrounds the termination region 40 in plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single field region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in plan view in an arc shape (preferably a quadrant arc shape).

[0380] The ratio of the width of the single field region 42 to the width of the low-concentration region 11 may be 0.1 or more and less than 1. The width ratio may have a value belonging to at least one of the ranges of 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, and 0.8 or more and less than 1.

[0381] The single field region 42 is formed at a distance from the bottom of the low-concentration region 11 toward the first main surface 3, and faces the base region 14 across a part of the low-concentration region 11. The single field region 42 is formed at a distance from the depth position of the bottom of the high-concentration region 10 toward the first main surface 3. It is preferable that the single field region 42 is formed at a distance from the depth position of the middle of the high-concentration region 10 toward the first main surface 3. Of course, the single field region 42 may cross the depth position of the middle of the high-concentration region 10 in the thickness direction.

[0382] The single field region 42 has an inner edge on the termination region 40 side and an outer edge on the peripheral side of the first main surface 3. In this embodiment, the inner edge of the single field region 42 is connected to the outer edge of the termination region 40. This electrically connects the single field region 42 to the termination region 40. In this embodiment, the inner edge of the single field region 42 is connected to the outer edge of the termination region 40 around the entire periphery.

[0383] When the single field region 42 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the termination region 40, the single field region 42 may be extended from the termination region 40 to the surface layer of the low-concentration region 11 as an extension portion of the termination region 40. In other words, the termination region 40 may have the single field region 42 as an extension portion. Of course, the single field region 42 may be formed at a distance from the termination region 40.

[0384] Fig. 25 is a cross-sectional view showing a first modified example of the source pad electrode 60. Fig. 25 illustrates a configuration in which the configuration according to the modified example is applied to the semiconductor device 1A (first embodiment), but the configuration according to the modified example is applicable to all of the semiconductor devices 1A to 1E (first to fifth embodiments).

[0385] In the first to fifth embodiments described above, the plurality of first buried electrodes 62 are buried in the plurality of source openings 54 so as to expose the insulating surface 51. However, as shown in FIG. 25 , the source pad electrode 60 may have the plurality of first buried electrodes 62 that are drawn out from the plurality of source openings 54 onto the insulating surface 51 and cover the insulating surface 51.

[0386] The plurality of first buried electrodes 62 cover the first base electrode film 61 on the insulating surface 51, and have portions that cover the insulating surface 51 with the first base electrode film 61 sandwiched between them. That is, the plurality of first buried electrodes 62 each have a first buried electrode surface 66 that is exposed from the plurality of source openings 54 above the insulating surface 51. The plurality of first buried electrodes 62 have portions that face the gate electrode 32 with the first base electrode film 61 and the interlayer film 50 sandwiched between them in the stacking direction (vertical direction Z).

[0387] The multiple first buried electrodes 62 are integrated on the insulating surface 51 to form a single intermediate electrode 95. The intermediate electrode 95 (the multiple first buried electrodes 62) covers the entire area of ​​the first base electrode film 61. The electrode surface (first buried electrode surface 66) of the intermediate electrode 95 is located above the insulating surface 51.

[0388] In this embodiment, the first main electrode film 63 is mechanically and electrically connected to the first buried electrode surfaces 66 of the plurality of first buried electrodes 62 (intermediate electrodes 95) above the insulating surface 51. The first main electrode film 63 has a portion that faces the insulating surface 51 with the plurality of first buried electrodes 62 (intermediate electrodes 95) in between. In this embodiment, the first main electrode film 63 does not have a mechanical connection portion to the first base electrode film 61.

[0389] The configuration of the multiple first buried electrodes 62 (intermediate electrodes 95) according to the modified example is also applicable to the multiple first buried electrodes 62 of the source finger electrodes 68. Similarly, the configuration of the multiple first buried electrodes 62 (intermediate electrodes 95) according to the modified example is also applicable to the multiple second buried electrodes 72 of the gate finger electrodes 70.

[0390] Fig. 26 is a cross-sectional view showing a second modified example of the source pad electrode 60. Fig. 26 illustrates a configuration in which the configuration according to the modified example is applied to the semiconductor device 1A (first embodiment), but the configuration according to the modified example is applicable to all of the semiconductor devices 1A to 1E (first to fifth embodiments).

[0391] In the first to fifth embodiments described above, the source pad electrode 60 has a plurality of first buried electrodes 62. However, the source pad electrode 60 does not necessarily have to have the first buried electrodes 62. In this case, the first main electrode film 63 of the source pad electrode 60 extends from above the interlayer film 50 into the plurality of source openings 54 and is electrically connected to the body region 20 and the like within the plurality of source openings 54.

[0392] Similarly, the source finger electrodes 68 do not necessarily have to have the first buried electrodes 62. In this case, the first main electrode films 63 of the source finger electrodes 68 extend from above the interlayer film 50 into the outer openings 56, and are electrically connected to the termination region 40 (overlap region 41) within the outer openings 56.

[0393] Similarly, the gate finger electrode 70 does not necessarily have to have the second buried electrode 72. In this case, the second main electrode film 73 of the gate finger electrode 70 penetrates into the multiple gate openings 58 from above the interlayer film 50 and is electrically connected to the gate wiring 44 within the multiple gate openings 58.

[0394] The semiconductor devices 1A to 1E may have the first buried electrode 62 associated with the source pad electrode 60, but may not have the first buried electrode 62 associated with the source finger electrode 68. The semiconductor devices 1A to 1E may have the first buried electrode 62 associated with the source finger electrode 68, but may not have the first buried electrode 62 associated with the source pad electrode 60.

[0395] The semiconductor devices 1A to 1E may have the first buried electrode 62 associated with the source pad electrode 60, but may not have the second buried electrode 72. The semiconductor devices 1A to 1E may have the second buried electrode 72, but may not have the first buried electrode 62 associated with the source pad electrode 60. The semiconductor devices 1A to 1E may have the first buried electrode 62 associated with the source finger electrodes 68, but may not have the second buried electrode 72. The semiconductor devices 1A to 1E may have the second buried electrode 72, but may not have the first buried electrode 62 associated with the source finger electrodes 68.

[0396] The above-described embodiments (including variations) may be implemented in other forms. For example, the above-described embodiments may employ a configuration in which the relationship between the a-axis direction and the m-axis direction is interchanged. A specific configuration in this case can be obtained by interchangeably positioning the "a-axis direction (off-direction)" and the "m-axis direction (direction perpendicular to the off-direction)" in the above description and accompanying drawings.

[0397] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0398] In the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a wide bandgap semiconductor single crystal other than a SiC single crystal. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide bandgap semiconductor single crystals include gallium nitride, gallium oxide, and diamond. Of course, the chip 2 may also include a silicon single crystal.

[0399] Similarly, the first semiconductor layer 6 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal. The first semiconductor layer 6 may include gallium nitride, gallium oxide, diamond, etc. Of course, the first semiconductor layer 6 may also include a silicon single crystal.

[0400] Similarly, the second semiconductor layer 7 may contain a single crystal of a wide bandgap semiconductor other than a SiC single crystal. The second semiconductor layer 7 may contain gallium nitride, gallium oxide, diamond, etc. Of course, the second semiconductor layer 7 may also contain a silicon single crystal.

[0401] In the first to fifth embodiments described above, an n-type base region 14 is shown. However, a p-type base region 14 may be adopted instead of the n-type base region 14. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type base region 14 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 (n-type chip 2) by ion implantation.

[0402] In the sixth to ninth embodiments described above, an SBD structure (Schottky barrier diode) has been shown as an example of the diode structure Di. However, the diode structure Di may include at least one of a p-n junction diode, a pin junction diode, a Zener diode, and a fast recovery diode. In these cases, the diode structure Di may include one or more p-type anode regions that form a p-n junction with the high-concentration region 10 in a surface layer portion of the high-concentration region 10.

[0403] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in each of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc., as necessary.

[0404] [A1] A semiconductor device (1A-1I) including: a chip (2) having a main surface (3); a high concentration region (10) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3) on the inner side of the chip (2); and a low concentration region (11) of the first conductivity type (n-type) formed in a surface layer portion of the main surface (3) on the peripheral side of the chip (2) and having an impurity concentration lower than the impurity concentration of the high concentration region (10).

[0405] [A2] The semiconductor device (1A to 1I) according to A1, wherein the chip (2) includes SiC.

[0406] [A3] The semiconductor device (1A-1I) described in A1 or A2, wherein the chip (2) has side surfaces (5A-5D), the high concentration region (10) is formed at a distance from the side surfaces (5A-5D), and the low concentration region (11) is exposed from the side surfaces (5A-5D).

[0407] [A4] The semiconductor device (1A to 1I) according to any one of A1 to A3, wherein the low concentration region (11) extends in a strip shape along the high concentration region (10) in a plan view.

[0408] [A5] The semiconductor device (1A to 1I) according to any one of A1 to A4, wherein the low concentration region (11) surrounds the high concentration region (10) in a plan view.

[0409] [A6] The semiconductor device (1A to 1I) according to any one of A1 to A5, wherein the low concentration region (11) is connected to the high concentration region (10).

[0410] [A7] A semiconductor device (1A to 1I) described in any one of A1 to A6, further including an inner low concentration region (13) of a first conductivity type (n-type) formed in a region below the high concentration region (10) on the inner side of the chip (2) and having an impurity concentration lower than the impurity concentration of the high concentration region (10).

[0411] [A8] The semiconductor device (1A to 1I) according to A7, wherein the inner low concentration region (13) is connected to the low concentration region (11) on the peripheral edge side of the chip (2).

[0412] [A9] A semiconductor device (1A to 1I) described in any one of A1 to A8, further including an outer high concentration region (15) of a first conductivity type (n-type) formed in a region below the low concentration region (11) on the peripheral side of the chip (2) and having an impurity concentration higher than the impurity concentration of the low concentration region (11).

[0413] [A10] The semiconductor device (1A to 1I) according to A9, wherein the outer high concentration region (15) is connected to the high concentration region (10) on the inner side of the chip (2).

[0414] [A11] A semiconductor device (1A to 1I) described in any one of A1 to A10, further including a first conductivity type (n-type) base region (14) formed in a region below the high concentration region (10) on the inner side of the chip (2) and having an impurity concentration higher than the impurity concentration of the high concentration region (10).

[0415] [A12] A semiconductor device (1A to 1I) according to any one of A1 to A11, further comprising a second conductivity type (p-type) impurity region (20, 21, 40) formed in the surface layer portion of the high concentration region (10).

[0416] [A13] A semiconductor device (1A to 1I) according to any one of A1 to A12, further comprising a second conductivity type (p-type) field region (42) formed in the surface layer portion of the low concentration region (11).

[0417] [A14] A semiconductor device (1A-1I) including: a chip (2) having a main surface (3); an active region (8) provided in an inner portion of the main surface (3); a peripheral region (9) provided on the periphery of the main surface (3); a first conductivity type (n-type) high concentration region (10) formed in the active region (8) on the surface layer of the main surface (3); and a first conductivity type (n-type) low concentration region (11) formed in the surface layer of the main surface (3) in the peripheral region (9) and having an impurity concentration lower than the impurity concentration of the high concentration region (10).

[0418] [A15] The semiconductor device (1A to 1I) according to A14, wherein the chip (2) includes SiC.

[0419] [A16] The semiconductor device (1A to 1I) according to A14 or A15, further comprising a second conductivity type (p-type) field region (42) formed in the surface layer portion of the low concentration region (11) in the peripheral region (9).

[0420] [A17] The semiconductor device (1A to 1I) according to A16, wherein the field region (42) is formed in a surface layer portion of the low concentration region (11) at a distance from the high concentration region (10).

[0421] [A18] A semiconductor device (1A to 1I) according to any one of A14 to A17, further comprising a second conductivity type impurity region (20, 21, 40) formed in the surface layer portion of the high concentration region (10) in the active region (8).

[0422] [A19] The semiconductor device (1A to 1I) according to any one of A14 to A18, further comprising a second conductivity type (p-type) termination region (40) formed in either or both of a surface layer portion of the high concentration region (10) and a surface layer portion of the low concentration region (11) in the peripheral region (9).

[0423] [A20] A semiconductor device (1A to 1I) according to any one of A14 to A19, further comprising the high concentration region (10) and a device structure (Tr, Di) formed in the active region (8).

[0424] Although specific embodiments have been described in detail above, these are merely examples that clarify the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0425] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 1E Semiconductor device 1F Semiconductor device 1G Semiconductor device 1H Semiconductor device 1I Semiconductor device 2 Chip 3 First main surface 5A First side surface 5B Second side surface 5C Third side surface 5D Fourth side surface 8 Active region 9 Peripheral region 10 Highly doped region 11 Lowly doped region 13 Inner lowly doped region 14 Base region 15 Outer highly doped region 20 Body region (impurity region) 21 Outer body region (impurity region) 40 Termination region (impurity region) 42 Field region Tr Transistor structure (device structure) Di Diode structure (device structure)

Claims

1. a chip having a major surface; a first conductivity type high concentration region formed in a surface layer portion of the main surface on an inner portion side of the chip; a first conductivity type low concentration region formed in a surface layer of the main surface on the peripheral edge side of the chip, the low concentration region having an impurity concentration lower than the impurity concentration of the high concentration region.

2. The semiconductor device according to claim 1 , wherein the chip comprises SiC.

3. the tip has a side surface; the high concentration region is formed at a distance from the side surface, The semiconductor device according to claim 1 , wherein said low concentration region is exposed from said side surface.

4. The semiconductor device according to claim 1 , wherein said low concentration region extends in a strip shape along said high concentration region in a plan view.

5. The semiconductor device according to claim 4 , wherein said low concentration region surrounds said high concentration region in a plan view.

6. The semiconductor device according to claim 1 , wherein said low concentration region is connected to said high concentration region.

7. The semiconductor device according to any one of claims 1 to 6, further comprising an inner low concentration region of a first conductivity type formed in a region below the high concentration region on the inner side of the chip, the inner low concentration region having an impurity concentration lower than the impurity concentration of the high concentration region.

8. 8. The semiconductor device according to claim 7, wherein said inner low concentration region is connected to said low concentration region on said peripheral edge side of said chip.

9. The semiconductor device according to any one of claims 1 to 6, further comprising an outer high concentration region of a first conductivity type formed in a region below the low concentration region on the peripheral edge side of the chip, the outer high concentration region having an impurity concentration higher than the impurity concentration of the low concentration region.

10. 10. The semiconductor device according to claim 9, wherein said outer heavily doped region is connected to said heavily doped region on said inner side of said chip.

11. The semiconductor device according to any one of claims 1 to 6, further comprising a base region of a first conductivity type formed in a region below the high concentration region on the inner side of the chip, the base region having an impurity concentration higher than the impurity concentration of the high concentration region.

12. 7. The semiconductor device according to claim 1, further comprising a second conductivity type impurity region formed in a surface layer portion of said high concentration region.

13. 7. The semiconductor device according to claim 1, further comprising a field region of the second conductivity type formed in a surface layer portion of said low concentration region.

14. a chip having a major surface; an active region provided in an inner portion of the main surface; an outer peripheral region provided on a peripheral edge portion of the main surface; a first conductivity type high concentration region formed in a surface layer portion of the main surface in the active region; a first conductivity type low concentration region formed in a surface layer portion of the main surface in the peripheral region, the low concentration region having an impurity concentration lower than the impurity concentration of the high concentration region.

15. The semiconductor device of claim 14 , wherein the chip comprises SiC.

16. 15. The semiconductor device according to claim 14, further comprising a field region of the second conductivity type formed in a surface layer portion of said low concentration region in said peripheral region.

17. 17. The semiconductor device according to claim 16, wherein said field region is formed in a surface layer of said low concentration region at a distance from said high concentration region.

18. 18. The semiconductor device according to claim 14, further comprising an impurity region of a second conductivity type formed in a surface layer portion of said high concentration region in said active region.

19. The semiconductor device according to any one of claims 14 to 17, further comprising a second conductivity type termination region formed in one or both of a surface layer portion of the high concentration region and a surface layer portion of the low concentration region in the outer periphery region.

20. 18. The semiconductor device according to claim 14, further comprising a device structure including the high concentration region and formed in the active region.