Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device (100) comprises: a first nitride semiconductor layer (103); a second nitride semiconductor layer (104); a p-type third nitride semiconductor layer (106) and a p-type fourth nitride semiconductor layer (107) that are provided on the second nitride semiconductor layer (104) and are separated from one another; a source electrode (301) and a drain electrode (302); a first gate electrode (303) that is provided in contact with the third nitride semiconductor layer (106); and a second gate electrode (304) that is provided on the fourth nitride semiconductor layer (107) with a dielectric layer (201) interposed therebetween, wherein at least one of the following conditions is satisfied: the second gate length (L2) of the fourth nitride semiconductor layer (107) is less than the first gate length (L1) of the third nitride semiconductor layer (106); the fourth nitride semiconductor layer (107) is thinner than the third nitride semiconductor layer (106); and the p-type impurity concentration of the fourth nitride semiconductor layer (107) is lower than the p-type impurity concentration of the third nitride semiconductor layer (106).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device structure and a manufacturing method thereof, and more particularly to a semiconductor device using a semiconductor, particularly a nitride semiconductor, that can be used as a power transistor or the like, and a manufacturing method thereof.

[0002] Nitride semiconductors have a high breakdown voltage due to their wide band gap. Furthermore, nitride semiconductors can easily be formed into heterostructures such as AlGaN / GaN. The difference in band gap and the piezoelectric charge generated by the difference in lattice constant between the AlGaN barrier layer and the GaN channel layer can generate a high-mobility, high-concentration electron channel (two-dimensional electron gas, 2DEG) on the GaN layer side of the AlGaN / GaN interface. Controlling this 2DEG makes it possible to form a high-electron-mobility transistor (HEMT). Due to these characteristics of high breakdown voltage, high speed, and large current, Group III nitride semiconductors are applied to electronic devices such as field-effect transistors (FETs) and diodes for power applications.

[0003] When a nitride semiconductor (e.g., GaN) is used in a power FET, from the viewpoint of safety, it is required to operate normally-off, in which no current flows between the source and drain when the gate voltage is 0 V. Normally-off operation of a GaN-FET can be achieved by providing a p-type nitride semiconductor between the gate electrode and the AlGaN barrier layer, thereby forming a p-n junction under the gate and depleting the 2DEG channel only under the gate.

[0004] However, FETs using nitride semiconductors are prone to a phenomenon called current collapse, in which the drain current becomes difficult to flow for a certain period of time when the device is turned on again after being turned off. Poor current collapse characteristics make high-speed switching difficult, causing serious problems in the operation of the device.

[0005] Patent Document 1 discloses a structure in which p-type GaN (p-GaN) that is not electrically connected to an electrode is placed under the drain end of a source field plate (SFP) to neutralize tramp electrons.

[0006] Patent Document 2 discloses a structure in which a normally-on gate electrode, which serves as a second gate, is added between the gate and drain of an FET to improve the breakdown voltage.

[0007] JP 2019-192912 A JP 2013-69785 A

[0008] However, in the structure of Patent Document 1, the p-GaN under the SFP is close to the potential of the source (GND), which may lead to a problem of increased on-resistance.

[0009] Furthermore, in the structure of Patent Document 2, the potential of the second gate is the same as that of the source, so the second gate itself does not contribute to controlling the on / off operation of the transistor, and a problem can be conceived in that a leak path is formed between the source and drain, etc. via the second gate.

[0010] Therefore, the present disclosure provides a semiconductor device and a method for manufacturing the semiconductor device that can both reduce the gate leakage current during gate-off operation and suppress an increase in on-resistance due to electron traps.

[0011] A semiconductor device according to one aspect of the present disclosure is a semiconductor device comprising: a first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type third nitride semiconductor layer provided on the second nitride semiconductor layer; a p-type fourth nitride semiconductor layer provided on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer; a source electrode and a drain electrode provided in contact with the second nitride semiconductor layer at positions sandwiching the third nitride semiconductor layer and the fourth nitride semiconductor layer; a first gate electrode provided on the third nitride semiconductor layer and in contact with the third nitride semiconductor layer; and a second gate electrode having the same potential as the first gate electrode, and when a length over which the third nitride semiconductor layer is in contact with the second nitride semiconductor layer is a first gate length and a length over which the fourth nitride semiconductor layer is in contact with the second nitride semiconductor layer is a second gate length in a cross-sectional view including the source electrode and the drain electrode, at least one of the following is satisfied: (i) the second gate length is smaller than the first gate length, (ii) the thickness of the fourth nitride semiconductor layer is smaller than the thickness of the third nitride semiconductor layer, and (iii) the concentration of p-type impurities contained in the fourth nitride semiconductor layer is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer, and the threshold voltage of the semiconductor device is a positive value.

[0012] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes a first step of forming, on a first nitride semiconductor layer, a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer; a second step of forming, on a portion of the second nitride semiconductor layer, a p-type third nitride semiconductor layer and a p-type fourth nitride semiconductor layer; a third step of forming a dielectric layer so as to cover upper surfaces of the third nitride semiconductor layer, the fourth nitride semiconductor layer, and the second nitride semiconductor layer; a fourth step of forming a source electrode and a drain electrode at positions sandwiching the third nitride semiconductor layer and the fourth nitride semiconductor layer; a fourth step of forming a first gate electrode in an opening formed on the third nitride semiconductor layer in the dielectric layer, and forming a second gate electrode above the fourth nitride semiconductor layer; and a fifth step of forming a second gate electrode having the same potential as the first gate electrode via a first gate electrode, wherein, in a cross-sectional view including the source electrode and the drain electrode, when a first gate length is a length over which the third nitride semiconductor layer is in contact with the second nitride semiconductor layer and a second gate length is a length over which the fourth nitride semiconductor layer is in contact with the second nitride semiconductor layer, the third nitride semiconductor layer and the fourth nitride semiconductor layer are formed so as to satisfy at least one of the following: (i) the second gate length is smaller than the first gate length; (ii) the thickness of the fourth nitride semiconductor layer is smaller than the thickness of the third nitride semiconductor layer; and (iii) the concentration of p-type impurities contained in the fourth nitride semiconductor layer is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer.

[0013] According to one aspect of the present disclosure, it is possible to provide a semiconductor device or the like that can achieve both a reduction in gate leakage current during gate-off operation and suppression of an increase in on-resistance due to electron trapping.

[0014] FIG. 1A is a plan view showing the configuration of a semiconductor device according to a first embodiment. FIG. 1B is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment, taken along the Ib-Ib cutting line shown in FIG. 1A. FIG. 2 is a flowchart showing a manufacturing method of the semiconductor device according to the first embodiment. FIG. 3A is a plan view showing the configuration of a semiconductor device according to a second embodiment. FIG. 3B is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment, taken along the IIIb-IIIb cutting line shown in FIG. 3A. FIG. 4A is a plan view showing the configuration of a semiconductor device according to a third embodiment. FIG. 4B is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment, taken along the IVb-IVb cutting line shown in FIG. 4A. FIG. 5A is a plan view showing the configuration of a semiconductor device according to a fourth embodiment. FIG. 5B is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment, taken along the Vb-Vb cutting line shown in FIG. 5A. FIG. 6A is a plan view showing the configuration of a semiconductor device according to a fifth embodiment. FIG. 6B is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment, taken along the VIb-VIb cutting line shown in FIG. 6A. FIG. 7A is a plan view showing the configuration of a semiconductor device according to a sixth embodiment. Fig. 7B is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 6, taken along line VIIb-VIIb shown in Fig. 7A. Fig. 8 is a cross-sectional view showing the configuration of a semiconductor device according to a modification of embodiment 6, taken along a line corresponding to line VIIb-VIIb shown in Fig. 7A. Fig. 9 is a schematic view showing a manufacturing method of a semiconductor device according to a modification of embodiment 6.

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below represents a preferred specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, component placement and connection configurations, steps (processes), and the order of steps (processes) shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims that represent the highest concept of the present disclosure will be described as optional components.

[0016] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, the scales and the like do not necessarily match in each figure. In each figure, the same reference numerals are used to denote substantially the same components, and redundant explanations will be omitted or simplified.

[0017] In this specification, the terms "upper" and "lower" in the configuration of a semiconductor device do not refer to the upper direction (vertically upward) and lower direction (vertically downward) in absolute spatial recognition, but are terms defined by a relative positional relationship based on the stacking order in a stacked structure. Furthermore, the terms "upper" and "lower" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0018] In this specification and the drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a right-handed three-dimensional Cartesian coordinate system. In each embodiment, the stacking direction of each layer of the semiconductor device is defined as the Z-axis direction, and the X-axis and Y-axis are two axes parallel to the main surface of the semiconductor device. In this specification, the term "planar view" refers to viewing the semiconductor device from the Z-axis direction. In this specification, the term "cross-sectional view" refers to viewing the semiconductor device cut along a plane defined by the X-axis and Z-axis from the Y-axis direction.

[0019] Furthermore, in this specification, terms indicating relationships between elements such as equal and the same, terms indicating the shapes of elements such as rectangle and square, numerical values, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent (or about 10%).

[0020] Furthermore, in this specification, for convenience, the reference numerals of the components of the semiconductor device are used in common in each embodiment and the like.

[0021] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0022] (First Embodiment) [1-1. Configuration of Semiconductor Device] First, the configuration of a semiconductor device according to a first embodiment will be described with reference to Figures 1A and 1B. Figure 1A is a plan view showing the configuration of a semiconductor device 100 according to a first embodiment. Figure 1B is a cross-sectional view showing the configuration of the semiconductor device 100 according to the first embodiment taken along the Ib-Ib cutting line shown in Figure 1A.

[0023] As shown in FIGS. 1A and 1B , the semiconductor device 100 includes a substrate 101, a buffer layer 102, a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, a third nitride semiconductor layer 106, a fourth nitride semiconductor layer 107, a dielectric layer 201, an insulator layer 202, a source electrode 301, a drain electrode 302, a first gate electrode 303, a second gate electrode 304, a gate wiring 305 which is an extension portion common to the first gate electrode 303 and the second gate electrode 304, a source wiring layer 401, and a drain wiring layer 402.

[0024] In FIG. 1A, in order to make the wiring structure of the electrodes easier to see, the dielectric layer 201 and the insulator layer 202 are not shown, and the semiconductor layers are also not shown.

[0025] In plan view, semiconductor device 100 has an active region 601 and a non-active region 602. Active region 601 is a region sandwiched between source electrode 301 and drain electrode 302 in plan view, and in active region 601, two-dimensional electron gas layer 105 (see FIG. 1B ) is formed on the first nitride semiconductor layer 103 side of the heterointerface between second nitride semiconductor layer 104 and first nitride semiconductor layer 103.

[0026] The substrate 101 is, for example, a substrate made of Si. The substrate 101 is not limited to a substrate made of Si, but may be a substrate made of sapphire, SiC, GaN, AlN, or the like.

[0027] The buffer layer 102 is formed on the substrate 101. The buffer layer 102 is a nitride semiconductor layer having a thickness of, for example, 2 μm and made of a multi-layer structure of AlN and AlGaN. The buffer layer 102 may also be made of a single layer or multiple layers of a Group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN, or AlInGaN, or even SiC. The thickness refers to the length in the Z-axis direction.

[0028] The first nitride semiconductor layer 103 is formed on the substrate 101. In this embodiment, the first nitride semiconductor layer 103 is formed on the buffer layer 102. The first nitride semiconductor layer 103 is composed of, for example, undoped (i-type) GaN with a thickness of 200 nm. "Undoped (i-type)" means that impurities are not intentionally doped during epitaxial growth. The first nitride semiconductor layer 103 may be composed of a Group III nitride semiconductor such as AlGaN, InGaN, or AlInGaN, in addition to GaN. Furthermore, the first nitride semiconductor layer 103 may not only be undoped (i-type), but may also contain n-type impurities such as Si or p-type impurities such as Mg or C.

[0029] The second nitride semiconductor layer 104 is formed on the first nitride semiconductor layer 103. The second nitride semiconductor layer 104 is made of undoped (i-type) AlGaN with a thickness of 10 nm and an Al composition ratio of 25%, for example. The second nitride semiconductor layer 104 is not limited to AlGaN, and may be made of a Group III nitride semiconductor such as AlN, InGaN, or AlInGaN. The second nitride semiconductor layer 104 may be undoped (i-type) or may contain n-type impurities such as Si or p-type impurities such as Mg or C.

[0030] In this embodiment, the band gap of second nitride semiconductor layer 104 is larger than the band gap of first nitride semiconductor layer 103. In addition, second nitride semiconductor layer 104 made of undoped (i-type) AlGaN and first nitride semiconductor layer 103 made of undoped (i-type) GaN have a heterostructure. That is, the interface between second nitride semiconductor layer 104 and first nitride semiconductor layer 103 forms a heterojunction, and a heterobarrier is formed at the interface between second nitride semiconductor layer 104 and first nitride semiconductor layer 103.

[0031] As a result, a two-dimensional electron gas layer 105 is formed near the boundary between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104, for example, on the first nitride semiconductor layer 103 side of the heterointerface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103 (in other words, on the second nitride semiconductor layer 104 side (positive side of the Z axis) within the first nitride semiconductor layer 103).

[0032] A semiconductor layer made of AlN and having a thickness of about 1 to 2 nm may be provided as a spacer layer between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103 .

[0033] The source electrode 301 and the drain electrode 302 are provided on the second nitride semiconductor layer 104 exposed in openings provided at intervals in the dielectric layer 201. The source electrode 301 and the drain electrode 302 are each provided in contact with the second nitride semiconductor layer 104 and electrically connected to the first nitride semiconductor layer 103. The source electrode 301 and the drain electrode 302 are, for example, but not limited to, a multilayer electrode film having a layered structure in which a Ti film and an Al film are stacked in this order. The source electrode 301 and the drain electrode 302 are also electrically connected to the two-dimensional electron gas layer 105 through an ohmic connection.

[0034] Here, by using recesses formed by removing a portion of the second nitride semiconductor layer 104 and / or the first nitride semiconductor layer 103 as the source electrode 301 and the drain electrode 302, the ohmic contact resistance with the two-dimensional electron gas layer 105 can be reduced, and the resistance during on-operation can be more effectively reduced.

[0035] Note that a recess formed by removing a part of the second nitride semiconductor layer 104 and / or the first nitride semiconductor layer 103, a contact layer containing an n-type impurity including a donor such as Si, or the like may be provided below the source electrode 301 and the drain electrode 302. In this case, the contact layer functions as the source electrode 301 or the drain electrode 302 and is in contact with the first nitride semiconductor layer 103. That is, the source electrode 301 and the drain electrode 302 are connected to the side surfaces of the two-dimensional electron gas layer 105. The contact layer containing the n-type impurity may be formed by plasma treatment, ion implantation, regrowth, or the like.

[0036] The third nitride semiconductor layer 106 is provided on the second nitride semiconductor layer 104 at a position between the source electrode 301 and the drain electrode 302, and spaced apart from the source electrode 301 and the drain electrode 302. The third nitride semiconductor layer 106 has a width of, for example, 1.5 μm in the X-axis direction (the direction of the shortest distance connecting the source electrode 301 and the drain electrode 302), and is made of Mg-doped p-type GaN. Here, the Mg dopant concentration is, for example, 4.0E19 atoms / cm ３ However, 1.0E17 atoms / cm ３ More than 8.0E19atoms / cm ３ The p-type dopant is not limited to Mg. For example, Zn, C, etc. may be used as the p-type dopant.

[0037] The third nitride semiconductor layer 106 is not limited to GaN, and may be made of a Group III nitride semiconductor such as AlN, AlGaN, InGaN, AlInGaN, InN, etc. The third nitride semiconductor layer 106 may be not only a single p-type layer, but also a stacked structure of p-type layers with different concentrations, or a stacked structure including an i-type layer or an n-type layer.

[0038] In the first embodiment, the fourth nitride semiconductor layer 107 is provided at a position between the third nitride semiconductor layer 106 and the drain electrode 302, and the dielectric layer 201 is disposed on the fourth nitride semiconductor layer 107. The material of the fourth nitride semiconductor layer 107 may be the same as that of the third nitride semiconductor layer 106.

[0039] The fourth nitride semiconductor layer 107 is formed at a position several μm (e.g., 3 μm) away from the third nitride semiconductor layer 106. The width (length in the X-axis direction) of the fourth nitride semiconductor layer 107 is, for example, 1.2 μm (e.g., 80% of the width of the third nitride semiconductor layer 106), and the thickness is 100 nm.

[0040] Here, the width of fourth nitride semiconductor layer 107 may be 80% or less of the width of third nitride semiconductor layer 106 in the X-axis direction. Specifically, the width of fourth nitride semiconductor layer 107 may be 0.9 μm or less (e.g., 60% or less of the width of third nitride semiconductor layer 106) or 0.6 μm or less (e.g., 40% or less of the width of third nitride semiconductor layer 106). The smaller the width of fourth nitride semiconductor layer 107, the easier it is to obtain the effect of suppressing an increase in on-resistance without interfering with the on-operation of the transistor.

[0041] Here, the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 have the same thickness, for example, 100 nm, but the fourth nitride semiconductor layer 107 may be thinner than the third nitride semiconductor layer 106. For example, when the third nitride semiconductor layer 106 has a thickness of 100 nm, the fourth nitride semiconductor layer 107 may have a thickness of 80 nm or 50 nm. For example, the thickness of the fourth nitride semiconductor layer 107 may be 80% or less, 50% or less, or 30% or less of the thickness of the third nitride semiconductor layer 106.

[0042] The fourth nitride semiconductor layer 107 is made of p-type GaN doped with Mg. Here, the Mg dopant concentration is 4.0E19 atoms / cm ３The p-type dopant is not limited to Mg. For example, Zn, Cd, C, etc. may be used as the p-type dopant. The p-type dopant concentration may be equal to or lower than the p-type dopant concentration of the third nitride semiconductor layer 106. For example, the p-type dopant concentration of the fourth nitride semiconductor layer 107 may be lower than the p-type dopant concentration of the third nitride semiconductor layer 106. In other words, the p-type dopant concentration contained in the third nitride semiconductor layer 106 may be higher than the p-type dopant concentration contained in the fourth nitride semiconductor layer 107. The p-type dopant concentration is an example of a p-type impurity concentration.

[0043] The fourth nitride semiconductor layer 107 is not limited to being made of GaN, and may be made of a group III nitride semiconductor such as AlN, AlGaN, InGaN, AlInGaN, or InN.

[0044] Furthermore, fourth nitride semiconductor layer 107 may be not only a single p-type layer, but also a stacked structure of p-type layers with different concentrations, or a stacked structure including an i-type layer or an n-type layer.

[0045] Furthermore, there may be a plurality of pairs of third nitride semiconductor layers 106 and fourth nitride semiconductor layers 107 .

[0046] The dielectric layer 201 is disposed on the second nitride semiconductor layer 104, on a portion of the third nitride semiconductor layer 106, and on the fourth nitride semiconductor layer 107. The dielectric layer 201 is made of, for example, SiN having a thickness of 100 nm. Note that the dielectric layer 201 is not limited to SiN, and may be made of SiO2, Al2O3, C (diamond), AlN, or SiC. The dielectric layer 201 may contain impurities such as Si, O, or Se that impart n-type conductivity to the nitride semiconductor layers. In other words, the dielectric layer 201 may contain a dopant that exhibits a conductivity type opposite to that of the dopants contained in the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107.

[0047] The insulator layer 202 is formed on the dielectric layer 201, the source electrode 301, the drain electrode 302, the first gate electrode 303, and the second gate electrode 304, and is made of SiN with a thickness of 150 nm, for example. The insulator layer 202 is not limited to SiN, and may be made of SiO2, Al2O3, C (diamond), AlN, or SiC.

[0048] The insulator layer 202 has a source electrode connection opening 501 on the source electrode 301 and a drain electrode connection opening 502 on the drain electrode 302. In Fig. 1A, each opening is indicated by a dashed line. Each electrode is connected to a corresponding wiring.

[0049] The first gate electrode 303 is provided in contact with the upper surface of the third nitride semiconductor layer 106. The first gate electrode 303 is provided on the third nitride semiconductor layer 106 and the dielectric layer 201, and is provided in contact with the upper surface of the third nitride semiconductor layer 106 exposed by opening the dielectric layer 201. Here, the first gate electrode 303 is a multilayer electrode film having a layered structure in which a TiN film, an Al film, and a TiN film are stacked in this order, but is not limited to this. Metals such as Ti, TiN, TaN, W, Ni, Pd, Au, and Al may also be used as electrode materials. Furthermore, the structure may be a single metal layer or a layered structure of multiple metals.

[0050] The second gate electrode 304 is provided above the fourth nitride semiconductor layer 107 via the dielectric layer 201. The second gate electrode 304 is a multilayer electrode film having a laminated structure in which a TiN film, an Al film, and a TiN film are laminated in this order, but is not limited to this.

[0051] 1A, the gate wiring 305 connects the first gate electrode 303 and the second gate electrode 304 so that the first gate electrode 303 and the second gate electrode 304 are at the same potential. The gate wiring 305 is a multilayer electrode film having a laminated structure in which a TiN film, an Al film, and a TiN film are laminated in this order, but is not limited to this.

[0052] The threshold voltage Vth of the composite transistor (i.e., the threshold voltage of the semiconductor device 100) consisting of the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the third nitride semiconductor layer 106, the source electrode 301, the drain electrode 302, and the first gate electrode 303 and the second gate electrode 304, which are at the same potential via the gate wiring 305, is a positive value, and is 1.7 V in the first embodiment. The threshold voltage Vth of the composite transistor is equal to the threshold voltage Vth1 of the first transistor consisting of the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the third nitride semiconductor layer 106, the source electrode 301, the drain electrode 302, and the first gate electrode 303. The semiconductor device 100 is a semiconductor device that performs a normally-off operation. The threshold voltage Vth1 of the first transistor is a positive value, and the first transistor performs a normally-off operation.

[0053] The source wiring layer 401 is provided on the insulator layer 202 and contacts the upper surface of the insulator layer 202 and the upper surface of the source electrode 301 exposed by a source electrode connection opening 501 formed by opening the insulator layer 202. The source wiring layer 401 is a multilayer wiring film having a laminated structure in which a TiN film, an Al film, and a TiN film are laminated in this order, but is not limited to this. Metals such as Ti, TiN, TaN, W, Ni, Pd, Au, and Al may also be used as wiring materials. The structure may also be a single metal layer or a laminated structure of multiple metals.

[0054] The drain wiring layer 402 is provided on the insulator layer 202 and is in contact with the upper surface of the insulator layer 202 and the upper surface of the drain electrode 302 exposed by a drain electrode connection opening 502 formed by opening the insulator layer 202. The drain wiring layer 402 is a multilayer wiring film having a laminated structure in which a TiN film, an Al film, and a TiN film are laminated in this order, but is not limited to this. Metals such as Ti, TiN, TaN, W, Ni, Pd, Au, and Al may also be used as wiring materials. The structure may also be a single metal layer or a laminated structure of multiple metals.

[0055] In the semiconductor device 100 according to the first embodiment configured as described above, in the first transistor, the gate electrode (first gate electrode 303) is directly connected to the third nitride semiconductor layer 106, which is a p-type semiconductor. In other words, the first gate electrode 303 is provided on and in contact with the third nitride semiconductor layer 106.

[0056] Furthermore, in the second transistor composed of the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the fourth nitride semiconductor layer 107, the second gate electrode 304, and the dielectric layer 201, the dielectric layer 201 is located between (in the stacking direction) the fourth nitride semiconductor layer 107, which is a p-type semiconductor, and the second gate electrode 304, so that the threshold voltage Vth1 of the first transistor is equal to or greater than the threshold voltage Vth2 of the second transistor (for example, Vth1≧Vth2). In other words, the threshold voltage Vth2 of the second transistor is equal to or less than the threshold voltage Vth1 of the first transistor.

[0057] Therefore, in the transistors in the semiconductor device 100, for example, when a second transistor is added on the drain electrode 302 side, the depletion layer expands toward the drain electrode 302 side during gate-off operation due to the presence of the p-type fourth nitride semiconductor layer 107 added on the drain electrode 302 side compared to the first transistor.

[0058] Furthermore, the presence of the second gate electrode 304 reduces the electric field strength from the drain electrode 302 to the first gate electrode 303 in the vicinity of the first gate electrode 303, which can lead to the suppression of gate leakage current.

[0059] Furthermore, since the second transistor has a MIS (Metal Insulator Semiconductor) gate structure having the dielectric layer 201, there is almost no gate leakage current passing through the second gate electrode 304. Therefore, the semiconductor device 100 can reduce the gate leakage current from the first gate electrode 303 in the gate-off operation.

[0060] Here, for example, when the total number of holes in third nitride semiconductor layer 106 in the gate structure of the first transistor is the same as the total number of holes in fourth nitride semiconductor layer 107 in the gate structure of the second transistor, and when threshold voltage Vth1 of the first transistor is positive, threshold voltage Vth2 of the second transistor will be positively greater than threshold voltage Vth1 of the first transistor due to the presence of dielectric layer 201. In this case, when the voltage applied from gate wiring 305 to first gate electrode 303 and second gate electrode 304 is equal to or greater than threshold voltage Vth1 of the first transistor and less than threshold voltage Vth2 of the second transistor, the first transistor will be turned on, but a depletion layer will remain in the second transistor, causing it to be turned off, thereby preventing the transistor (semiconductor device 100) from being turned on.

[0061] On the other hand, semiconductor device 100 is configured so that the total number of holes in fourth nitride semiconductor layer 107 is less than the total number of holes in third nitride semiconductor layer 106 so that threshold voltage Vth2 of the second transistor is equal to or less than threshold voltage Vth1 of the first transistor (see (i) to (iii) described below), and therefore the second transistor does not interfere with the on-operation of the transistor (semiconductor device 100). For example, threshold voltage Vth2 of the second transistor is greater than 0 V and equal to or less than threshold voltage Vth1 of the first transistor.

[0062] Furthermore, since the fourth nitride semiconductor layer 107 below the second gate electrode 304 is p-type, holes injected from the fourth nitride semiconductor layer 107 can neutralize electrons trapped by levels generated by surface oxidation in the vicinity of the fourth nitride semiconductor layer 107 on the surface of the second nitride semiconductor layer 104 between the first gate electrode 303 and the drain electrode 302. This makes it possible to suppress an increase in on-resistance during continuous transistor operation.

[0063] Since the total number of holes in the fourth nitride semiconductor layer 107 is smaller than the total number of holes in the third nitride semiconductor layer 106, the extent of the depletion layer when the gate is off is larger in the first transistor than in the second transistor. For example, in a cross-sectional view, the area (cross-sectional area) of the depletion layer in the first transistor is larger than the area (cross-sectional area) of the depletion layer in the second transistor.

[0064] As described above, the threshold voltage Vth1 of the first transistor is 1.7V.

[0065] The threshold voltage Vth2 of the second transistor, which is composed of the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the third nitride semiconductor layer 106, the source electrode 301, the drain electrode 302, and the second gate electrode 304 via the dielectric layer 201, is smaller than the threshold voltage Vth1 of the first transistor, and is, for example, but not limited to, 1.0 V. For example, Vth1 > Vth2 > 0, but the threshold voltage Vth2 of the second transistor may be any value equal to or less than the threshold voltage Vth1 of the first transistor, and may be a negative value.

[0066] [1-2. Method of Manufacturing Semiconductor Device] A method of manufacturing the semiconductor device 100 according to the first embodiment will now be described with reference to Fig. 2. Fig. 2 is a flowchart showing the method of manufacturing the semiconductor device 100 according to the first embodiment.

[0067] As shown in Fig. 2, first, using metal organic chemical vapor deposition (MOCVD), a buffer layer 102 having a layer thickness of 2 µm and having a stacked structure of AlN and AlGaN, a first nitride semiconductor layer 103 having a layer thickness of 200 nm and made of GaN, and a second nitride semiconductor layer 104 having a layer thickness of 20 nm and made of AlGaN with an Al composition ratio of 25% and having a band gap larger than that of the first nitride semiconductor layer 103 are sequentially epitaxially grown in the +c-plane direction (<0001> direction) on a Si substrate 101 (S10). In this way, in step S10, the second nitride semiconductor layer 104 having a band gap larger than that of the first nitride semiconductor layer 103 is formed on the first nitride semiconductor layer 103. Step S10 is an example of a first process.

[0068] Next, a p-type nitride semiconductor layer (for example, see p-type nitride semiconductor layer 701 shown in (a) of FIG. 9 described later) is continuously formed on second nitride semiconductor layer 104. The p-type nitride semiconductor layer is formed in a region including third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107 in plan view.

[0069] Next, a mask is formed in regions where third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107 are to be formed, and the p-type nitride semiconductor layer in regions outside the mask is removed by dry etching to form third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107 (S20). In this way, in step S20, p-type third nitride semiconductor layer 106 and p-type fourth nitride semiconductor layer 107 are formed on parts of second nitride semiconductor layer 104. Step S20 is an example of the second step.

[0070] Here, in a cross-sectional view including the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107, a length over which the third nitride semiconductor layer 106 is in contact with the second nitride semiconductor layer 104 is defined as a first gate length L1 (see FIG. 1B ), and a length over which the fourth nitride semiconductor layer 107 is in contact with the second nitride semiconductor layer 104 is defined as a second gate length L2 (see FIG. 1B ). In this case, in the second step, the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 are formed so as to satisfy at least one of the following: (i) the second gate length L2 is smaller than the first gate length L1; (ii) the thickness of the fourth nitride semiconductor layer 107 is smaller than the thickness of the third nitride semiconductor layer 106; and (iii) the concentration of p-type impurities contained in the fourth nitride semiconductor layer 107 is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer 106.

[0071] For example, the above (i) can be achieved by using a mask in which the width (length in the same direction as the first gate length L1) of the mask portion for forming the third nitride semiconductor layer 106 is smaller than the width (length in the same direction as the second gate length L2) of the mask portion for forming the fourth nitride semiconductor layer 107. When the second gate length L2 is small, for example, even if a depletion layer of the second transistor remains when the transistor is turned on, the width is narrow, so that electrons can tunnel through the depletion layer and move in the X-axis direction. In other words, when the second gate length L2 is smaller than the first gate length L1, it is possible to further prevent the second gate electrode 304 and the fourth nitride semiconductor layer 107 from interfering with the on-operation of the transistor.

[0072] Furthermore, for example, after the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 are formed, the above (ii) can be realized by removing a part of the fourth nitride semiconductor layer 107 in the thickness direction by a dry etching method or the like.

[0073] In this way, for example, third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107 can be formed simultaneously using masks with different widths. In semiconductor device 100 including third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107 formed in this way, threshold voltage Vth2 of the second transistor can be set to be equal to or lower than threshold voltage Vth1 of the first transistor.

[0074] When condition (iii) is satisfied, for example, the cross-sectional areas of the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 may be equal. When condition (iii) is satisfied, for example, the first gate length L1 and the second gate length L2 may be equal, and the thicknesses of the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 may be equal.

[0075] It should be noted that (i), (ii), and (iii) only need to be realized when the semiconductor device 100 is completed, and are not necessarily realized in the second step.

[0076] In (iii), the concentration of p-type impurities contained in the fourth nitride semiconductor layer 107 may be 80% or less, 70% or less, 60% or less, 50% or less, or 40% or less of the concentration of p-type impurities contained in the third nitride semiconductor layer 106.

[0077] Next, after removing the mask (i.e., after forming the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 (e.g., immediately after forming them)), a dielectric layer 201 is formed so as to cover the upper surfaces of the third nitride semiconductor layer 106, the fourth nitride semiconductor layer 107, and the second nitride semiconductor layer 104 (S30). Here, the dielectric layer 201 is formed of SiN to a thickness of 100 nm by, for example, a P-CVD method (plasma CVD method). Note that the dielectric layer 201 may be formed by not only the P-CVD method but also an LP-SiN method or a sputtering method. Step S30 is an example of a third step.

[0078] In the third step, the dielectric layer 201 may be formed using a raw material containing an impurity that provides n-type conductivity.

[0079] Next, a mask is formed in areas other than those where the source electrode 301 and the drain electrode 302 are to be formed (positions that sandwich the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 in a plan view), the dielectric layer 201 is removed by dry etching, and the source electrode 301 and the drain electrode 302 are formed in the removed openings by sputtering (S40). That is, the source electrode 301 and the drain electrode 302 are formed in positions that sandwich the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 in a plan view. Step S40 is an example of a fourth step.

[0080] Furthermore, a mask is formed on the third nitride semiconductor layer 106 except for the location where the first gate electrode 303 is to be formed, and the dielectric layer 201 is removed by dry etching. As a result, an opening is formed in the dielectric layer 201. Here, dry etching means etching using a gas containing C, such as CHF3. For example, the opening is formed by dry etching using a gas containing an impurity that imparts p-type conductivity to the third nitride semiconductor layer 106.

[0081] At this time, carbon, which is an impurity that imparts p-type conductivity to the third nitride semiconductor layer 106, penetrates into the third nitride semiconductor layer 106. This allows the p-type dopant concentration of the third nitride semiconductor layer 106 to be higher than the p-type dopant concentration of the fourth nitride semiconductor layer 107. In other words, the total number of holes in the third nitride semiconductor layer 106 can be made larger than the total number of holes in the fourth nitride semiconductor layer 107. This also makes it possible to achieve the above (iii).

[0082] Here, an etching gas that does not contain carbon may be used, or wet etching may be used, or the dielectric layer 201 may be etched partway by dry etching, and then the dielectric layer 201 may be wet etched using a chemical solution such as hydrofluoric acid up to the contact region with the third nitride semiconductor layer 106.

[0083] In this way, at the start of step S50, at least a part of the upper surface of third nitride semiconductor layer 106 is exposed. At the start of step S50, the upper surface of fourth nitride semiconductor layer 107 is not exposed, but is covered with dielectric layer 201. The dry etching for exposing at least a part of the upper surface of third nitride semiconductor layer 106 may be performed as a fifth step described later.

[0084] Next, using a mask having openings at positions where the first gate electrode 303 and the second gate electrode 304 are to be formed, the first gate electrode 303 and the second gate electrode 304 are formed by sputtering (S50). In step S50, the first gate electrode 303 is formed in the opening formed in the dielectric layer 201 above the third nitride semiconductor layer 106, and the second gate electrode 304, which has the same potential as the first gate electrode 303 via the dielectric layer 201, is formed above the fourth nitride semiconductor layer 107. Step S50 is an example of the fifth step.

[0085] Here, the first gate electrode 303 is formed so as to be in contact with the third nitride semiconductor layer 106, and the second gate electrode 304 is formed on the fourth nitride semiconductor layer 107 via the dielectric layer 201. That is, the first gate electrode 303 and the third nitride semiconductor layer 106 are provided in direct contact with each other, and the second gate electrode 304 and the fourth nitride semiconductor layer 107 are provided in a non-contact state. In addition, in a plan view, the first gate electrode 303 and the second gate electrode 304 also extend outside the active region 601. A gate wiring 305 is also formed simultaneously with the formation of the first gate electrode 303 and the second gate electrode 304, and the gate wiring 305 is connected to the first gate electrode 303 and the second gate electrode 304 in a region other than the active region 601 (i.e., the non-active region 602).

[0086] When the first gate electrode 303, the second gate electrode 304, and the gate wiring 305 are formed simultaneously, the conductive film formation process is completed only once, and therefore the process cost can be reduced.

[0087] Here, the first gate electrode 303 and the second gate electrode 304 are formed simultaneously, but the first gate electrode 303 and the second gate electrode 304 may be formed twice using different materials. Specifically, after the first gate electrode 303 made of TiN is formed, an integrated layer of the second gate electrode 304 made of Cu and the gate wiring 305 may be formed in this order so as to be in contact with the first gate electrode 303.

[0088] In this way, when the process is divided into two steps and the second gate electrode 304 and the gate wiring 305 are formed using a material with higher conductivity than the first gate electrode 303, the resistance of the element can be reduced.

[0089] Next, an insulator layer 202 is formed (S60), covering the gate electrodes (first gate electrode 303 and second gate electrode 304) of the active region 601 and having openings (source electrode connection opening 501 and drain electrode connection opening 502, the boundaries of which are shown by dashed lines in FIG. 1B) for portions of the source electrode 301 and drain electrode 302, respectively. The insulator layer 202 is made of SiN with a thickness of 150 nm, for example. The insulator layer 202 is not limited to SiN, and may be made of SiO2, Al2O3, C (diamond), AlN, or SiC. Step S60 is an example of a sixth process.

[0090] Next, a source wiring layer 401 and a drain wiring layer 402 are formed in the opening of the insulator layer 202 above the source electrode 301 and the opening of the insulator layer 202 above the drain electrode 302, respectively (S70). The source wiring layer 401 may be connected to the source electrode 301 outside the active region 601, and the drain wiring layer 402 may be connected to the drain electrode 302 outside the active region 601. Step S70 is an example of a seventh step.

[0091] [1-3. Effects, etc.] As described above, semiconductor device 100 according to the first embodiment is a semiconductor device including first nitride semiconductor layer 103, second nitride semiconductor layer 104 provided on first nitride semiconductor layer 103 and having a band gap larger than that of first nitride semiconductor layer 103, p-type third nitride semiconductor layer 106 provided on second nitride semiconductor layer 104, p-type fourth nitride semiconductor layer 107 provided on second nitride semiconductor layer 104 and spaced apart from third nitride semiconductor layer 106, source electrode 301 and drain electrode 302 provided in contact with second nitride semiconductor layer 104 at positions sandwiching third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107, first gate electrode 303 provided on third nitride semiconductor layer 106, and dielectric layer 20 on fourth nitride semiconductor layer 107. and a second gate electrode 304 that is provided via the source electrode 301 and has the same potential as the first gate electrode 303, and in a cross-sectional view including the source electrode 301 and the drain electrode 302, when a length over which the third nitride semiconductor layer 106 is in contact with the second nitride semiconductor layer 104 is a first gate length L1 and a length over which the fourth nitride semiconductor layer 107 is in contact with the second nitride semiconductor layer 104 is a second gate length L2, at least one of the following is satisfied: (i) the second gate length L2 is smaller than the first gate length L1; (ii) the thickness t2 of the fourth nitride semiconductor layer 107 is smaller than the thickness t1 of the third nitride semiconductor layer 106; and (iii) the concentration of p-type impurities contained in the fourth nitride semiconductor layer 107 is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer 106, and the threshold voltage Vth of the semiconductor device 100 is a positive value.

[0092] As a result, a depletion layer is formed during gate-off operation due to the presence of the second gate electrode 304 and the fourth nitride semiconductor layer 107. This depletion layer can reduce gate leakage current flowing into the first gate electrode 303 during gate-off operation. Furthermore, since the conductivity type of the fourth nitride semiconductor layer 107 is p-type, electrons trapped by levels generated by surface oxidation in the vicinity of the fourth nitride semiconductor layer 107 on the surface of the second nitride semiconductor layer 104 between the first gate electrode 303 and another electrode (e.g., the source electrode 301 or the drain electrode 302) can be neutralized by holes injected from the fourth nitride semiconductor layer 107. This can suppress an increase in on-resistance during continuous transistor operation.

[0093] Therefore, the semiconductor device 100 according to the first embodiment can reduce the gate leakage current during the gate-off operation and suppress an increase in on-resistance due to electron traps.

[0094] Furthermore, for example, the fourth nitride semiconductor layer 107 may be located between the third nitride semiconductor layer 106 and the drain electrode 302 .

[0095] This reduces the electric field strength from the drain electrode 302 to the first gate electrode 303, thereby effectively suppressing gate leakage current. For example, in a typical FET, the gate-drain voltage is greater than the source-gate voltage. Therefore, a structure is often adopted in which the gate-drain distance is greater than the source-gate distance to reduce the difference in electric field. In particular, in a power semiconductor, the voltage difference is large, so even if a difference in distance is provided, the electric field strength between the gate and drain is greater than the electric field strength between the source and gate. Therefore, providing the fourth nitride semiconductor layer 107 between the gate and drain has a greater effect of alleviating the electric field.

[0096] Also, for example, the second gate length L2 may be 80% or less of the first gate length L1.

[0097] This makes it possible to more reliably make the threshold voltage Vth2 of the second transistor equal to or lower than the threshold voltage Vth1 of the first transistor when other parameters (e.g., thickness, hole density, etc.) of the fourth nitride semiconductor layer 107 are the same as those of the third nitride semiconductor layer 106. Therefore, it is possible to realize a semiconductor device 100 that can suppress an increase in on-resistance without interfering with the on-operation of the transistor.

[0098] Furthermore, for example, fourth nitride semiconductor layer 107 may be thinner than third nitride semiconductor layer 106. For example, thickness t2 of fourth nitride semiconductor layer 107 may be 80% or less of thickness t1 of third nitride semiconductor layer 106.

[0099] As a result, by making the thickness of fourth nitride semiconductor layer 107 thinner than that of third nitride semiconductor layer 106, for example, by making it 80% or less of the thickness of third nitride semiconductor layer 106, the total number of holes in fourth nitride semiconductor layer 107 becomes smaller than the total number of holes in third nitride semiconductor layer 106. Therefore, it is possible to more effectively suppress the threshold voltage Vth2 of the second transistor to be equal to or less than the threshold voltage Vth1 of the first transistor.

[0100] Furthermore, for example, the threshold voltage Vth2 of the second transistor formed of the source electrode 301, the drain electrode 302, and the second gate electrode 304 may be a positive value.

[0101] As a result, the threshold voltage Vth2 of the second transistor is equal to or lower than the threshold voltage Vth1 of the first transistor and is greater than 0 V, which makes it possible to more effectively reduce gate leakage to the first gate electrode 303 and suppress an increase in on-resistance due to electron traps during continuous transistor operation. For example, when the threshold voltage Vth2 of the second transistor is positive, the total number of holes contained in the fourth nitride semiconductor layer 107 is greater than when the threshold voltage Vth2 is negative, and electron traps can be effectively neutralized, thereby making it possible to effectively suppress an increase in on-resistance.

[0102] Furthermore, for example, the concentration of p-type impurities contained in the third nitride semiconductor layer 106 may be higher than the concentration of p-type impurities contained in the fourth nitride semiconductor layer 107. For example, the concentration of p-type impurities contained in the fourth nitride semiconductor layer 107 may be 80% or less of the concentration of p-type impurities contained in the third nitride semiconductor layer 106.

[0103] As a result, by making the p-type impurity concentration of fourth nitride semiconductor layer 107 less than the p-type impurity concentration of third nitride semiconductor layer 106, for example, 80% or less of the p-type impurity concentration of third nitride semiconductor layer 106, the total number of holes in fourth nitride semiconductor layer 107 becomes smaller than the total number of holes in third nitride semiconductor layer 106. As a result, it is possible to more effectively suppress the threshold voltage Vth2 of the second transistor to be equal to or less than the threshold voltage Vth1 of the first transistor.

[0104] Furthermore, for example, the threshold voltage Vth2 of the second transistor consisting of the source electrode 301, the drain electrode 302, and the second gate electrode 304 may be lower than the threshold voltage Vth1 of the first transistor consisting of the source electrode 301, the drain electrode 302, and the first gate electrode 303.

[0105] This makes it possible to realize the semiconductor device 100 in which the threshold voltage Vth2 of the second transistor is equal to or lower than the threshold voltage Vth1 of the first transistor.

[0106] As described above, the method for manufacturing semiconductor device 100 according to the first embodiment includes a first step (S10) of forming second nitride semiconductor layer 104 having a band gap larger than that of first nitride semiconductor layer 103 on first nitride semiconductor layer 103; a second step (S20) of forming p-type third nitride semiconductor layer 106 and p-type fourth nitride semiconductor layer 107 on a part of second nitride semiconductor layer 104; a third step (S30) of forming dielectric layer 201 so as to cover upper surfaces of third nitride semiconductor layer 106, fourth nitride semiconductor layer 107, and second nitride semiconductor layer 104; a fourth step (S40) of forming source electrode 301 and drain electrode 302 at positions sandwiching third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107; and a fourth step (S40) of forming first gate electrode 303 in the opening formed on third nitride semiconductor layer 106 relative to dielectric layer 201. and a fifth step (S50) of forming a second gate electrode 304 having the same potential as the first gate electrode 303 above the conductor layer 107 via the dielectric layer 201, wherein, in a cross-sectional view including the source electrode 301 and the drain electrode 302, when a first gate length L1 is a length over which the third nitride semiconductor layer 106 is in contact with the second nitride semiconductor layer 104 and a second gate length L2 is a length over which the fourth nitride semiconductor layer 107 is in contact with the second nitride semiconductor layer 104, the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 are formed so as to satisfy at least one of the following: (i) the second gate length L2 is smaller than the first gate length L1; (ii) the thickness t2 of the fourth nitride semiconductor layer 107 is smaller than the thickness t1 of the third nitride semiconductor layer 106; and (iii) the concentration of p-type impurities contained in the fourth nitride semiconductor layer 107 is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer 106.

[0107] This makes it possible to realize the above-described semiconductor device 100.

[0108] Furthermore, for example, in the fifth step (S50), the opening may be formed by dry etching using a gas containing a p-type impurity.

[0109] As a result, when an opening is formed in the dielectric layer 201 by dry etching using a gas containing a p-type impurity, such as CHF3, the third nitride semiconductor layer 106 exposed after the dielectric layer 201 is removed is doped with C as a p-type impurity. By forming the opening by dry etching using a gas containing C in addition to CHF3, the p-type impurity can be implanted into the third nitride semiconductor layer 106 during dry etching. This process can increase the concentration of p-type semiconductor holes in the third nitride semiconductor layer 106, thereby changing the threshold voltage Vth1 of the first transistor to a higher value. Therefore, the threshold voltage Vth2 of the second transistor can be more effectively suppressed to be equal to or lower than the threshold voltage Vth1 of the first transistor.

[0110] Furthermore, for example, in the third step (S30), the dielectric layer 201 may be formed using a raw material containing an impurity that provides n-type conductivity.

[0111] As a result, dielectric layer 201 contains a material (such as Si or O) that acts as an n-type impurity in third nitride semiconductor layer 106, and the material that acts as an n-type impurity can be diffused into fourth nitride semiconductor layer 107 due to a temperature rise during deposition of dielectric layer 201, a subsequent thermal history, and the like. That is, a part of the p-type impurity in fourth nitride semiconductor layer 107 is compensated for, and the concentration of holes in fourth nitride semiconductor layer 107 is reduced. This makes it possible to more effectively suppress threshold voltage Vth2 of the second transistor to be equal to or lower than threshold voltage Vth1 of the first transistor.

[0112] (Embodiment 2) [2-1. Configuration of Semiconductor Device] Next, the configuration of a semiconductor device according to embodiment 2 will be described with reference to Figures 3A and 3B. Figure 3A is a plan view showing the configuration of a semiconductor device 100A according to embodiment 2. Figure 3B is a cross-sectional view showing the configuration of semiconductor device 100A according to embodiment 2 taken along line IIIb-IIIb shown in Figure 3A.

[0113] The second embodiment differs from the first embodiment in that a gate electrode connection portion 306 is provided between the first gate electrode 303 and the second gate electrode 304, and the manufacturing method differs in the fifth step. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0114] 3A and 3B , the gate electrode connection portion 306 is a wiring region that directly connects the first gate electrode 303 and the second gate electrode 304 on the active region 601. In other words, the first gate electrode 303 and the second gate electrode 304 are connected via the gate electrode connection portion 306. The gate electrode connection portion 306 can also be said to be a wiring layer (metal layer) that connects the first gate electrode 303 and the second gate electrode 304, and that is provided in a region that overlaps with the active region 601 in a plan view between the first gate electrode 303 and the second gate electrode 304. The gate electrode connection portion 306 is an example of a gate electrode connection region.

[0115] Here, the first gate electrode 303, the second gate electrode 304, and the gate electrode connection portion 306 may be an integral member. For example, the first gate electrode 303 (first gate electrode region) may be formed including a region of a metal layer provided across the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 that overlaps with the third nitride semiconductor layer 106 in a planar view, the second gate electrode 304 (second gate electrode region) may be formed including a region of the metal layer constituting the gate electrode that overlaps with the fourth nitride semiconductor layer 107, and the gate electrode connection portion 306 may be formed by a region therebetween of the metal layer constituting the gate electrode (a region sandwiched between the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 in a planar view).

[0116] [2-2. Manufacturing Method of Semiconductor Device] Next, a description will be given of a manufacturing method of the semiconductor device 100A in embodiment 2. The flowchart of the manufacturing method may be the same as the flowchart shown in Fig. 2, and the following description will mainly focus on the differences from the flowchart shown in Fig. 2.

[0117] In the fifth step, the shape of the mask used when forming the gate electrodes is different from that in the first embodiment, and a mask having an opening that encompasses both the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 is used. The opening has a position and size corresponding to the first gate electrode 303, the second gate electrode 304, and the gate electrode connecting portion 306. Note that this opening may extend to the outside of the active region 601, or there may be a plurality of openings according to each pair of the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107.

[0118] In the fifth step, a gate electrode (integrated with the first gate electrode 303, gate electrode connecting portion 306, and second gate electrode 304) is formed in this opening by sputtering. The first gate electrode 303, second gate electrode 304, and gate electrode connecting portion 306 are integrally formed. When the gate electrode is formed, the gate wiring 305 is also formed at the same time, and the gate wiring 305 is connected to the gate electrode in a region other than the active region 601.

[0119] [2-3. Effects, etc.] As described above, in the semiconductor device 100A according to the second embodiment, the first gate electrode 303 and the second gate electrode 304 are connected to each other via a metal layer (e.g., gate electrode connection portion 306) provided between the first gate electrode 303 and the second gate electrode 304.

[0120] As a result, a gate field plate structure is formed in the gate region of the first transistor, extending from the first gate electrode 303 to the second gate electrode 304. Therefore, when the source electrode 301 is set to zero potential and a potential is applied to the drain electrode 302, it is possible to reduce the intensity of the electric field that the third nitride semiconductor layer 106 receives from the electric field generated between the source electrode 301 and the drain electrode 302, and it is possible to further suppress the gate leakage current during FET operation.

[0121] The gate electrode connection portion 306 may have, for example, a lattice or strip shape, as long as it is connected to the gate wiring 305 and covers at least a part of the active region 601 between the first gate electrode 303 and the second gate electrode 304. Even with this configuration, it is possible to further suppress the gate leakage current during FET operation.

[0122] (Third Embodiment) [3-1. Configuration of Semiconductor Device] Next, the configuration of a semiconductor device according to a third embodiment will be described with reference to Figures 4A and 4B. Figure 4A is a plan view showing the configuration of a semiconductor device 100B according to the third embodiment. Figure 4B is a cross-sectional view showing the configuration of the semiconductor device 100B according to the third embodiment taken along the line IVb-IVb shown in Figure 4A.

[0123] It should be noted that the third embodiment differs from the first embodiment in the positional relationship of the second gate electrode 304. The manufacturing method differs from the fifth step onwards (for example, the fifth to seventh steps). The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0124] 4A and 4B , in semiconductor device 100B, second gate electrode 304 is provided on fourth nitride semiconductor layer 107 via dielectric layer 201 and insulator layer 202, and is arranged on and in contact with gate wiring 305 in a region other than active region 601. Electrical connection between second gate electrode 304 and gate wiring 305 is made through an opening (gate wiring connection opening 503, the boundary of which is shown by a dashed line in FIG. 4B ) in insulator layer 202 arranged on first gate electrode 303.

[0125] By configuring the semiconductor device 100B with such a structure, it is possible to use a low-resistance material for the second gate electrode 304 without being bound by restrictions on connection with the fourth nitride semiconductor layer 107. As the material, a low-resistance material such as Cu or Al can be used.

[0126] The second gate electrode 304 may be provided on the fourth nitride semiconductor layer 107 via three or more layers including the dielectric layer 201 and the insulator layer 202 .

[0127] [3-2. Manufacturing Method of Semiconductor Device] Next, a description will be given of a manufacturing method of the semiconductor device 100B in embodiment 3. The flowchart of the manufacturing method may be the same as the flowchart shown in Fig. 2, and the following description will mainly focus on the differences from the flowchart shown in Fig. 2.

[0128] In the fifth step, the second gate electrode 304 is not formed, and the first gate electrode 303 and the gate wiring 305 are simultaneously formed in the opening of the mask. The gate wiring 305 is connected to the first gate electrode 303 in a region other than the active region 601.

[0129] In the sixth step, the insulator layer 202 is formed to cover the first gate electrode 303 in the active region 601, and to have a source electrode connection opening 501 in a portion overlapping with the source electrode 301 in a plan view, a drain electrode connection opening 502 in a portion overlapping with the drain electrode 302 in a plan view, and a gate wiring connection opening 503 in a portion overlapping with the gate wiring 305 in a plan view. All of these openings are indicated by dashed lines in FIG. 4A . At this point, the portion of the source electrode 301 corresponding to the source electrode connection opening 501, the portion of the drain electrode 302 corresponding to the drain electrode connection opening 502, and the portion of the gate wiring 305 corresponding to the gate wiring connection opening 503 are exposed.

[0130] Next, in a seventh step, a source wiring layer 401 and a drain wiring layer 402 are formed in the source electrode connection opening 501 and the drain electrode connection opening 502, respectively, and a second gate electrode 304 is formed on the fourth nitride semiconductor layer 107. The source wiring layer 401 and the drain wiring layer 402 may be connected outside the active region 601, and the second gate electrode 304 is in contact with the gate wiring 305 in the gate wiring connection opening 503 in a region other than the active region 601.

[0131] As described above, in the third embodiment, the second gate electrode 304, the source wiring layer 401, and the drain wiring layer 402 are simultaneously formed in the seventh step. In this case, the second gate electrode 304, the source wiring layer 401, and the drain wiring layer 402 are made of a common material.

[0132] [3-3. Effects, etc.] As described above, second gate electrode 304 of semiconductor device 100B according to the third embodiment is provided on fourth nitride semiconductor layer 107 via dielectric layer 201 and insulator layer 202 different from dielectric layer 201.

[0133] As a result, two layers, namely, the dielectric layer 201 and the insulator layer 202, are disposed between the second gate electrode 304 and the fourth nitride semiconductor layer 107, thereby further suppressing the gate leakage current passing through the second gate electrode 304.

[0134] (Fourth Embodiment) [4-1. Configuration of Semiconductor Device] Next, the configuration of a semiconductor device according to a fourth embodiment will be described with reference to Figures 5A and 5B. Figure 5A is a plan view showing the configuration of a semiconductor device 100C according to the fourth embodiment. Figure 5B is a cross-sectional view showing the configuration of the semiconductor device 100C according to the fourth embodiment taken along the Vb-Vb line shown in Figure 5A.

[0135] Note that compared to embodiment 1, embodiment 4 differs in the shape of fourth nitride semiconductor layer 107 in a plan view and in the second step of the manufacturing method. The following description will focus on the differences from embodiment 1, and description of commonalities will be omitted or simplified.

[0136] As shown in Figures 5A and 5B, in the semiconductor device 100C, the fourth nitride semiconductor layer 107 includes a plurality of portions 107a spaced apart from one another along the extension direction (Y-axis direction) of the third nitride semiconductor layer 106. The plurality of portions 107a are discontinuously arranged with a constant distance d between their ends. Figure 5A shows a state in which a plurality of rectangular portions 107a are formed on the second nitride semiconductor layer 104, and the boundaries between the first gate electrode 303, the second gate electrode 304, and the gate wiring 305 are indicated by dashed lines to visualize the fourth nitride semiconductor layer 107. Note that the planar shape of the plurality of portions 107a is not limited to a rectangular shape and may be, for example, a square shape or another shape.

[0137] In this embodiment, the distance d between the ends of each portion 107a is 0.6 μm or more, but it has been confirmed that a distance of 0.3 μm or more is effective in reducing the on-resistance. In other words, from the viewpoint of obtaining the effect of reducing the on-resistance, the distance d should be 0.3 μm or more, and more preferably 0.6 μm or more. Note that the distance d is the average value of the distances between the ends of each portion 107a, but may also be other statistical values ​​such as the maximum value, minimum value, mode, or median.

[0138] The length of each portion 107a in the arrangement direction (Y-axis direction) is, for example, 1.2 μm, but is not limited to this. For example, the value obtained by dividing the representative value (e.g., average value) of the distances d between the ends of the multiple portions 107a by the representative value (e.g., average value) of the lengths of the multiple portions 107a in the arrangement direction (Y-axis direction) is 0.5 or less, but may be 0.4 or less, 0.3 or less, or 0.6 or less. The representative value is the average value of the multiple distances d or the lengths of the multiple portions 107a in the arrangement direction, but may also be other statistical values ​​such as the maximum value, minimum value, mode, or median.

[0139] The end of the outermost fourth nitride semiconductor layer 107 is located outside the active region 601 (that is, in the non-active region 602). The number of the plurality of portions 107a is not particularly limited as long as it is two or more.

[0140] The second gate electrode 304 is provided above each of the plurality of portions 107a with the dielectric layer 201 interposed therebetween so as to cover all of the plurality of portions 107a.

[0141] A cross section of the semiconductor device 100C taken along a cutting line in a direction different from the X-axis direction and passing through the gaps between the portions 107a (areas in the fourth nitride semiconductor layer 107 where the portions 107a are not formed) has a configuration in which the fourth nitride semiconductor layer 107 (portions 107a) is excluded from that in FIG. 5B.

[0142] [4-2. Manufacturing Method of Semiconductor Device] Next, a description will be given of a manufacturing method of the semiconductor device 100C in embodiment 4. The flowchart of the manufacturing method may be the same as the flowchart shown in Fig. 2, and the following description will mainly focus on the differences from the flowchart shown in Fig. 2.

[0143] In the second step, a mask is formed in the regions where third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107 including multiple portions 107a are to be formed, and the regions outside the mask are removed by dry etching to form third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107. Specifically, the opening for forming third nitride semiconductor layer 106 has a width of, for example, 1.5 μm and a rectangular shape whose length exceeds active region 601, and the opening for forming fourth nitride semiconductor layer 107 has a width of 1.2 μm and a length of 1.2 μm and is arranged at 0.6 μm intervals in the length direction (Y-axis direction). Note that the mask is not limited to this, and a mask having openings of a size and position appropriate for the product may be used.

[0144] The other steps are the same as those in the first embodiment.

[0145] [4-3. Effects, etc.] As described above, the fourth nitride semiconductor layer 107 of the semiconductor device 100C according to the fourth embodiment is made up of a plurality of portions 107a that are arranged apart from each other along the extension direction of the third nitride semiconductor layer 106, and the second gate electrode 304 is provided above each of the plurality of portions 107a with the dielectric layer 201 interposed therebetween.

[0146] As a result, gaps are formed between the p-type semiconductors, and the depletion layer varies in size spatially. For example, when the gate voltage slightly exceeds the threshold voltage, the depletion layer that is generated becomes locally smaller than when the fourth nitride semiconductor layer 107 is formed continuously. This increases the electron concentration in the two-dimensional electron gas layer 105, and the on-resistance can be reduced without changing the threshold voltage Vth2 of the second transistor.

[0147] Furthermore, for example, the distance d between the ends of the multiple portions 107a may be 0.3 μm or more, and the value obtained by dividing the average value of the distance d between the ends of the multiple portions 107a by the average value of the length of the multiple portions 107a in the arrangement direction may be 0.5 or less.

[0148] This provides the second gate electrode 304 with a collapse reducing effect.

[0149] (Fifth Embodiment) [5-1. Configuration of Semiconductor Device] Next, the configuration of a semiconductor device according to a fifth embodiment will be described with reference to Figures 6A and 6B. Figure 6A is a plan view showing the configuration of a semiconductor device 100D according to a fifth embodiment. Figure 6B is a cross-sectional view showing the configuration of the semiconductor device 100D according to the fifth embodiment taken along line VIb-VIb shown in Figure 6A.

[0150] The fifth embodiment differs from the first embodiment in that there are a plurality of fourth nitride semiconductor layers 107 between the gate and drain, and the second step in the manufacturing method is different. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0151] 6A and 6B , in semiconductor device 100D, fifth nitride semiconductor layer 108, which is a p-type semiconductor, is provided on second nitride semiconductor layer 104, between fourth nitride semiconductor layer 107 and drain electrode 302, and is spaced apart from third nitride semiconductor layer 106 and fourth nitride semiconductor layer 107. In addition, third gate electrode 307 is disposed on fifth nitride semiconductor layer 108 with dielectric layer 201 interposed therebetween.

[0152] The second gate electrode 304 and the third gate electrode 307 are arranged, for example, on the same side of the source electrode 301 side or the drain electrode 302 side with respect to the first gate electrode 303, and are arranged on the drain electrode 302 side in this embodiment. Also, for example, the fourth nitride semiconductor layer 107 and the fifth nitride semiconductor layer 108 are each arranged between the third nitride semiconductor layer 106 and the drain electrode 302, closer to the third nitride semiconductor layer 106 than the center between them. In other words, the distance between the fourth nitride semiconductor layer 107 and the third nitride semiconductor layer 106 is shorter than the distance between the fourth nitride semiconductor layer 107 and the drain electrode 302, and the distance between the fifth nitride semiconductor layer 108 and the third nitride semiconductor layer 106 is shorter than the distance between the fifth nitride semiconductor layer 108 and the drain electrode 302.

[0153] The third gate length L3, which is the width of the fifth nitride semiconductor layer 108, is smaller than the first gate length L1 and is, for example, 1.5 μm. The third gate length L3 is the length over which the fifth nitride semiconductor layer 108 contacts the second nitride semiconductor layer 104 in a cross-sectional view including the source electrode 301 and the drain electrode 302. Since the third gate length L3 is smaller than the first gate length L1, the fifth nitride semiconductor layer 108 is prevented from affecting the threshold voltage of the semiconductor device 100D during on-operation, as in the first embodiment. Note that the third gate length L3 is not limited to being smaller than the first gate length L1 and may be, for example, the same as the first gate length L1. Furthermore, the third gate length L3 may be the same as the second gate length L2, or may be larger than the second gate length L2 and smaller than the first gate length L1, or may be smaller than the second gate length L2.

[0154] The thickness of the fifth nitride semiconductor layer 108 is, for example, 100 nm. The thickness of the fifth nitride semiconductor layer 108 may be smaller than the thickness of the third nitride semiconductor layer 106. That is, the thickness of the fifth nitride semiconductor layer 108 may be thinner than the third nitride semiconductor layer 106. For example, when the thickness of the third nitride semiconductor layer 106 is 100 nm, the thickness of the fifth nitride semiconductor layer 108 may be specifically 80 nm or less (80% or less of the thickness of the third nitride semiconductor layer 106) or 50 nm or less (50% or less of the thickness of the third nitride semiconductor layer 106).

[0155] The fifth nitride semiconductor layer 108 is made of p-type GaN doped with Mg. Here, the Mg dopant concentration is 4.0E19 atoms / cm ３The p-type dopant is not limited to Mg. For example, Zn, Cd, C, etc. may be used as the p-type dopant. The p-type dopant concentration may be equal to or lower than the p-type dopant concentration of the third nitride semiconductor layer 106. For example, the p-type dopant concentration of the fifth nitride semiconductor layer 108 may be lower than the p-type dopant concentration of the third nitride semiconductor layer 106. In other words, the p-type dopant concentration contained in the third nitride semiconductor layer 106 may be higher than the p-type dopant concentration contained in the fifth nitride semiconductor layer 108. The p-type dopant concentration is an example of a p-type impurity concentration.

[0156] The fifth nitride semiconductor layer 108 is not limited to being made of GaN, and may be made of a group III nitride semiconductor such as AlN, AlGaN, InGaN, AlInGaN, or InN.

[0157] Furthermore, the fifth nitride semiconductor layer 108 may be not only a single p-type layer, but also a stacked structure of p-type layers with different concentrations, or a stacked structure including an i-type layer or an n-type layer.

[0158] The third gate electrode 307 is connected to the gate wiring 305 and has the same potential as the first gate electrode 303 and the second gate electrode 304 .

[0159] Here, compared to doubling the width of the fourth nitride semiconductor layer 107, by adding a fifth nitride semiconductor layer 108 having the same width as the fourth nitride semiconductor layer 107 and spaced apart from the fourth nitride semiconductor layer 107 on the drain side, the electric field strength is further alleviated, which can lead to further suppression of gate leakage current.

[0160] Furthermore, when the thickness of fifth nitride semiconductor layer 108 is thinner than the thickness of third nitride semiconductor layer 106 and the widths and acceptor concentrations of third nitride semiconductor layer 106 and fifth nitride semiconductor layer 108 are the same, the total number of holes in fifth nitride semiconductor layer 108 becomes smaller than the total number of holes in third nitride semiconductor layer 106.

[0161] The fifth nitride semiconductor layer 108 and the third gate electrode 307 with the dielectric layer 201 interposed therebetween are not limited to being configured as a single pair, but may be configured as a plurality of pairs.

[0162] [5-2. Manufacturing Method of Semiconductor Device] Next, a description will be given of a manufacturing method of the semiconductor device 100D in embodiment 5. The flowchart of the manufacturing method may be the same as the flowchart shown in Fig. 2, and the following description will mainly focus on the differences from the flowchart shown in Fig. 2.

[0163] In the second step, a mask is formed on the region where the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 are to be formed, as well as the region where the fifth nitride semiconductor layer 108 is to be formed. The regions outside the mask are then removed by dry etching to form the third nitride semiconductor layer 106, the fourth nitride semiconductor layer 107, and the fifth nitride semiconductor layer 108. Specifically, the opening for forming the third nitride semiconductor layer 106 has a width of 1.5 μm and a rectangular shape whose length exceeds the active region 601. The opening for forming the fourth nitride semiconductor layer 107 is 3.0 μm away from the opening for forming the third nitride semiconductor layer 106 and has an opening width of 1.2 μm. The opening for forming the fifth nitride semiconductor layer 108 is 3.0 μm away from the opening for forming the fourth nitride semiconductor layer 107 and has an opening width of 1.2 μm. Note that the values ​​of the distance (e.g., 3.0 μm) and the opening width (e.g., 1.2 μm) are merely examples and are not limiting.

[0164] Here, in the second step, the fifth nitride semiconductor layer 108 is formed so as to satisfy at least one of the following: (iv) the third gate length L3 is smaller than the first gate length L1, (v) the thickness of the fifth nitride semiconductor layer 108 is smaller than the thickness of the third nitride semiconductor layer 106, and (vi) the concentration of p-type impurities contained in the fifth nitride semiconductor layer 108 is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer 106. Note that (iv), (v), and (vi) only need to be realized when the semiconductor device 100D is completed, and are not limited to being realized in the second step.

[0165] The other steps are the same as those in the first embodiment.

[0166] [5-3. Effects, etc.] As described above, the semiconductor device 100D according to the fifth embodiment further includes a p-type fifth nitride semiconductor layer 108 provided on the second nitride semiconductor layer 104 at a distance from the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107, and a third gate electrode 307 provided on the fifth nitride semiconductor layer 108 with the dielectric layer 201 interposed therebetween and having the same potential as the first gate electrode 303. When the length of contact between the fifth nitride semiconductor layer 108 and the second nitride semiconductor layer 104 is defined as a third gate length L3 in a cross-sectional view, the semiconductor device 100D satisfies at least one of the following conditions: (iv) the third gate length L3 is shorter than the first gate length L1; (v) the thickness of the fifth nitride semiconductor layer 108 is shorter than the thickness of the third nitride semiconductor layer 106; and (vi) the concentration of p-type impurities contained in the fifth nitride semiconductor layer 108 is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer 106.

[0167] As a result, fifth nitride semiconductor layer 108, which is a p-type semiconductor, is connected to third gate electrode 307 via dielectric layer 201, which can further reduce the electric field strength near second gate electrode 304 in off operation, thereby further suppressing gate leakage current.

[0168] Furthermore, for example, the second gate electrode 304 and the third gate electrode 307 may be located on the same side of the first gate electrode 303 , either the source electrode 301 side or the drain electrode 302 side.

[0169] As a result, for example, when the fourth nitride semiconductor layer 107 and the fifth nitride semiconductor layer 108 are disposed between the first gate electrode 303 and the drain electrode 302, the fourth nitride semiconductor layer 107 and the fifth nitride semiconductor layer 108, which are p-type layers, are disposed between the first gate electrode 303 and the drain electrode 302, so that the number of injected holes increases and electron traps can be neutralized more efficiently during continuous transistor operation. Therefore, an increase in on-resistance during continuous transistor operation can be more efficiently suppressed.

[0170] (Sixth Embodiment) [6-1. Configuration of Semiconductor Device] Next, the configuration of a semiconductor device according to a sixth embodiment will be described with reference to Figures 7A and 7B. Figure 7A is a plan view showing the configuration of a semiconductor device 100E according to the sixth embodiment. It is a cross-sectional view showing the configuration of the semiconductor device 100E according to the sixth embodiment taken along the VIIb-VIIb cutting line shown in Figure 7A.

[0171] Note that compared to embodiment 1, embodiment 6 differs in the height and width of fourth nitride semiconductor layer 107 and in the second step of the manufacturing method. The following description will focus on the differences from embodiment 1, and the description of the commonalities will be omitted or simplified.

[0172] 7A and 7B , in semiconductor device 100E, upper surface 107b of fourth nitride semiconductor layer 107 is lower than upper surface 106b of third nitride semiconductor layer 106. In other words, thickness t2 of fourth nitride semiconductor layer 107 is smaller than thickness t1 of third nitride semiconductor layer 106. Note that the height is higher as the layer is located closer to the positive side of the Z axis.

[0173] In this way, by making fourth nitride semiconductor layer 107 thinner than third nitride semiconductor layer 106, the total number of holes in fourth nitride semiconductor layer 107 becomes smaller than the total number of holes in third nitride semiconductor layer 106. Therefore, it is possible to more effectively suppress threshold voltage Vth2 of the second transistor to be equal to or less than threshold voltage Vth1 of the first transistor.

[0174] The width (second gate length L2) of the fourth nitride semiconductor layer 107 may be the same as the width (first gate length L1) of the third nitride semiconductor layer 106, for example, 1.5 μm. The width of the fourth nitride semiconductor layer 107 may be smaller than the width of the third nitride semiconductor layer 106.

[0175] The parameters of the other components are the same as those in the first embodiment.

[0176] [6-2. Manufacturing Method of Semiconductor Device] Next, a description will be given of a manufacturing method of the semiconductor device 100E in embodiment 6. The flowchart of the manufacturing method may be the same as the flowchart shown in Fig. 2, and the following description will mainly focus on the differences from the flowchart shown in Fig. 2.

[0177] In the first step, similarly to the first embodiment, a buffer layer 102 , a first nitride semiconductor layer 103 , a second nitride semiconductor layer, and a p-type nitride semiconductor layer are formed in this order on a substrate 101 .

[0178] In the second step, a first mask is formed to cover the area slightly inside the area where the third nitride semiconductor layer 106 is to be formed, and the area outside the first mask is removed by dry etching to a point halfway through the p-type nitride semiconductor layer.

[0179] Next, a second mask is additionally formed in a second region where the fourth nitride semiconductor layer 107 is to be formed, and the p-type nitride semiconductor layer in the region not covered by the first mask and the second mask is completely removed by dry etching. The lower surface exposed by this removal becomes the second nitride semiconductor layer 104. By removing the first mask and the second mask, the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 that is thinner than the third nitride semiconductor layer 106 are formed. This process allows the height of the upper surface 107b of the fourth nitride semiconductor layer 107 to be lower than the height of the upper surface 106b of the third nitride semiconductor layer 106.

[0180] In the third step, the dielectric layer 201 is formed by P-CVD, as in the first embodiment.

[0181] The other steps are the same as those in the first embodiment.

[0182] (Modification of Sixth Embodiment) [7-1. Configuration of Semiconductor Device] Next, the configuration of a semiconductor device according to a modification of the sixth embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view showing the configuration of a semiconductor device 100F according to a modification of the sixth embodiment, taken along a cutting line corresponding to the VIIb-VIIb cutting line shown in Fig. 7A.

[0183] The modification of the sixth embodiment differs from the sixth embodiment in that the cross-sectional shape of the third nitride semiconductor layer 106 is different and that a barrier layer 308 is provided on the upper surface of the third nitride semiconductor layer 106. The following description will focus on the differences from the sixth embodiment, and the description of the commonalities will be omitted or simplified.

[0184] 8 , in the semiconductor device 100F, the third nitride semiconductor layer 106 has a stepped shape in a cross-sectional view, and has an upper surface (first upper surface 106b1) of the upper portion (portion on the first gate electrode 303 side) of the steps of the third nitride semiconductor layer 106 and an upper surface (second upper surface 106b2) of the lower portion (portion on the second nitride semiconductor layer 104 side). The cross-sectional shape of the third nitride semiconductor layer 106 is, for example, a convex shape. The height of the upper surface 107b of the fourth nitride semiconductor layer 107 is lower than the height of the first upper surface 106b1 of the third nitride semiconductor layer 106 and is equal to the height of the second upper surface 106b2 of the third nitride semiconductor layer 106. In other words, the thickness t2 of the fourth nitride semiconductor layer 107 (see (c) of Figure 9) is smaller than the thickness t11 (see (c) of Figure 9) of the third nitride semiconductor layer 106 up to the first upper surface 106b1, and is equal to the thickness t12 (see (c) of Figure 9) of the third nitride semiconductor layer 106 up to the second upper surface 106b2.

[0185] Furthermore, a conductive barrier layer 308 is disposed on the first upper surface 106b1 of the third nitride semiconductor layer 106. The barrier layer 308 is a layer having barrier properties that is provided to prevent a gas that is used when forming the dielectric layer 201 and that inactivates the p-type dopant in the third nitride semiconductor layer 106 from penetrating into the third nitride semiconductor layer 106.

[0186] In this modification, the barrier layer 308 is a hydrogen barrier layer that prevents hydrogen from penetrating into the third nitride semiconductor layer 106. The barrier layer 308 has greater hydrogen permeability and / or hydrogen occlusion properties than the third nitride semiconductor layer 106. The barrier layer 308 is configured to include a material (e.g., a metal material) having greater hydrogen permeability and / or hydrogen occlusion properties than the third nitride semiconductor layer 106. An example of a material having hydrogen permeability barrier properties is TiN, but the barrier layer 308 may be configured to include other metal materials that prevent hydrogen permeation. Examples of materials having hydrogen occlusion properties include metal materials such as Pd, Ni, Ti, Al, Ag, and Ta. When the barrier layer 308 has hydrogen occlusion properties, the barrier layer 308 is configured to include a single layer of these metal materials, an alloy made of these metal materials, or a laminate thereof. Thus, in this modification, the barrier layer 308 is a metal layer having hydrogen barrier properties.

[0187] The permeation barrier property means a barrier property (difficulty of permeation) against a desired gas (here, hydrogen). For example, high permeation barrier property means that the desired gas is less likely to permeate. Furthermore, occlusion property means the ability to occlude (ease of absorption) a desired gas (here, hydrogen). For example, high occlusion property means that the desired gas is more easily absorbed, that is, the desired gas can be prevented from penetrating into the third nitride semiconductor layer 106.

[0188] The barrier layer 308 has the same dimensions as the first upper surface 106b1 of the third nitride semiconductor layer 106. The thickness of the barrier layer 308 is, for example, 30 nm, but is not limited to this. The first gate electrode 303 is in contact with the top of the barrier layer 308. The barrier layer 308 may be configured as a part of the first gate electrode 303. In other words, the first gate electrode 303 may have the barrier layer 308.

[0189] Although the example in which the barrier layer 308 is formed only on the first upper surface 106b1 has been described, it may also be formed on the second upper surface 106b2, for example. Furthermore, although the example in which the barrier layer 308 is formed on the third nitride semiconductor layer 106 has been described, the barrier layer 308 does not necessarily have to be formed. In other words, the semiconductor device 100F may have a configuration in which the first gate electrode 303 is directly connected to the convex-shaped third nitride semiconductor layer 106.

[0190] It should be noted that no barrier layer is formed on the fourth nitride semiconductor layer 107 .

[0191] The other structures are the same as those in the sixth embodiment.

[0192] In this way, the semiconductor device 100F is configured such that the third nitride semiconductor layer 106 has a first upper surface 106b1 that contacts the first gate electrode 303 via the barrier layer 308, and a second upper surface 106b2 that is located at a height position lower than the first upper surface 106b1, and the second upper surface 106b2 and the upper surface 107b of the fourth nitride semiconductor layer 107 are located at the same height position.

[0193] [7-2. Manufacturing Method of Semiconductor Device] Next, a manufacturing method of a semiconductor device according to a modification of the sixth embodiment will be described with reference to Fig. 9. Fig. 9 is a schematic diagram showing a manufacturing method of a semiconductor device 100F according to a modification of the sixth embodiment.

[0194] The modified example of the sixth embodiment differs from the sixth embodiment in the first, second, and fifth steps. The following description will focus on the differences from the sixth embodiment, and the description of the commonalities will be omitted or simplified. The flowchart of the manufacturing method may be the same as the flowchart shown in FIG.

[0195] 9A, in the second step, following the formation of the p-type nitride semiconductor layer 701, a TiN layer serving as the conductive layer 702 is formed by sputtering or the like. Here, instead of TiN, a conductive material having barrier or absorbing properties against hydrogen may be used. Specifically, the conductive layer 702 may be a single layer of a metal material having the ability to absorb hydrogen, such as Pd, Ni, Ti, Al, Ag, or Ta, or an alloy or laminate thereof. It is preferable to use a material that can form a Schottky contact with the third nitride semiconductor layer 106.

[0196] Next, a first mask M1 is formed in a region (first gate electrode region 701a) slightly inside the region where the third nitride semiconductor layer 106 is to be formed.

[0197] Next, the p-type nitride semiconductor layer 701 in the region outside the first mask M1 is removed by dry etching to a point halfway in the stacking direction.

[0198] As shown in (b) of Figure 9, next, after removing the first mask M1, a second mask M2 is formed on the first region R1 including the region (unetched region) left by the first mask M1 and the second region R2 where the fourth nitride semiconductor layer 107 is to be formed.

[0199] Next, the p-type nitride semiconductor layer 701 in the region outside the second mask M2 is completely removed by dry etching. The lower surface exposed by the removal becomes the second nitride semiconductor layer 104.

[0200] Next, the second mask M2 is removed to form the fourth nitride semiconductor layer 107 and the third nitride semiconductor layer 106 having stepped upper surfaces (first upper surface 106b1 and second upper surface 106b2). This process makes it possible to make the height of the upper surface 107b of the fourth nitride semiconductor layer 107 lower than the height of the first upper surface 106b1 of the third nitride semiconductor layer 106 and equal to the height of the second upper surface 106b2 of the third nitride semiconductor layer 106. The width of the first region R1 (the length in the X-axis direction) is the first gate length L1, and the width of the second region R2 (the length in the X-axis direction) is the second gate length L2.

[0201] In this manner, the barrier layer 308 (in this modification, the hydrogen barrier layer) is formed before the dielectric layer 201 is formed.

[0202] As shown in FIG. 9C, next, in the third step, a dielectric layer 201 is formed by P-CVD, as in the sixth embodiment.

[0203] The other steps are the same as those in the sixth embodiment.

[0204] [7-3. Effects, etc.] As described above, in semiconductor device 100F according to the modification of the sixth embodiment, third nitride semiconductor layer 106 has first upper surface 106b1 in contact with first gate electrode 303 and second upper surface 106b2 located at a height position lower than first upper surface 106b1, and second upper surface 106b2 and upper surface 107b of fourth nitride semiconductor layer 107 are located at the same height position.

[0205] As a result, the area of ​​the lower surface of the third nitride semiconductor layer 106 (the contact surface between the third nitride semiconductor layer 106 and the second nitride semiconductor layer 104) is larger than the area of ​​the first upper surface 106b1 of the third nitride semiconductor layer 106, and therefore the depletion layer formed under the third nitride semiconductor layer 106 during off operation is more likely to spread, and therefore the threshold voltage Vth2 of the second transistor can be more effectively suppressed to be equal to or lower than the threshold voltage Vth1 of the first transistor.

[0206] As described above, the second step (S20) of the method for manufacturing the semiconductor device 100F according to the modification of the sixth embodiment includes the steps of forming the p-type nitride semiconductor layer 701 on the second nitride semiconductor layer 104, forming the conductive layer 702 on the nitride semiconductor layer 701, and successively removing the conductive layer 702 and a part of the nitride semiconductor layer 701 in a region other than the gate electrode region (for example, the first gate electrode region 701a). When a region including the gate electrode region 701 a) is defined as a first region R1 and a region adjacent to and spaced from the first region R1 is defined as a second region R2, the nitride semiconductor layer 701 is completely removed by etching that covers the first region R1 and the second region R2, and the conductive layer 702 remaining in the first region R1 is defined as the first gate electrode 303, the nitride semiconductor layer 701 remaining in the first region R1 is defined as the third nitride semiconductor layer 106, and the nitride semiconductor layer 701 remaining in the second region R2 is defined as the fourth nitride semiconductor layer 107.

[0207] As a result, by using these steps, it is possible to form fourth nitride semiconductor layer 107 that is shorter in height than third nitride semiconductor layer 106, and to form third nitride semiconductor layer 106 that has a two-stage structure with a lower stage that is the same height as fourth nitride semiconductor layer 107 and is wider than the upper stage (in other words, third nitride semiconductor layer 106 whose lower surface area is wider than its upper surface). Furthermore, this manufacturing method allows this structure to be formed at lower cost.

[0208] Furthermore, for example, in the third step (S30), after the formation of the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107, the dielectric layer 201 may be formed on the upper surfaces of the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 by a plasma CVD method, and the first gate electrode 303 may be formed using a material having a higher hydrogen permeation barrier property than the third nitride semiconductor layer 106, or a material having a higher hydrogen absorption property than the third nitride semiconductor layer 106.

[0209] By using these steps, the barrier layer 308 can suppress the penetration of hydrogen into the third nitride semiconductor layer 106 when the dielectric layer 201 is formed by plasma CVD. This can prevent the p-type dopant, such as Mg, in the third nitride semiconductor layer 106 from being inactivated. As a result, the total number of holes in the third nitride semiconductor layer 106 can be made larger than the total number of holes in the fourth nitride semiconductor layer 107, and the threshold voltage Vth2 of the second transistor can be more effectively suppressed to be equal to or lower than the threshold voltage Vth1 of the first transistor.

[0210] (Other Embodiments) As described above, semiconductor devices etc. according to one or more aspects have been described based on the respective embodiments etc., but the present disclosure is not limited to these respective embodiments etc. As long as they do not deviate from the spirit of the present disclosure, various modifications that a person skilled in the art can conceive of to the present embodiment and embodiments constructed by combining components of different embodiments may also be included in the present disclosure.

[0211] For example, the second gate electrode 304 and the fourth nitride semiconductor layer 107 in the above-described embodiments may be disposed between the first gate electrode 303 and the source electrode 301. In this case, the second gate electrode 304 and the fourth nitride semiconductor layer 107 can suppress gate leakage current from the source electrode 301.

[0212] Furthermore, in the above-described embodiments, an example has been described in which the barrier layer 308 is formed on the first upper surface 106b1 of the convex-shaped third nitride semiconductor layer 106, but the present invention is not limited to this. The barrier layer 308 may be provided regardless of the cross-sectional shape of the third nitride semiconductor layer 106. For example, the barrier layer 308 may be provided on the upper surface 106b of the third nitride semiconductor layer 106 of any of the semiconductor devices according to Embodiments 1 to 6 in which the cross-sectional shape of the third nitride semiconductor layer 106 is rectangular. Furthermore, the barrier layer 308 may be provided on the entire upper surface 106b of the third nitride semiconductor layer 106, or on only a part of the upper surface 106b.

[0213] Furthermore, the numerical values ​​of thickness, length, distance, cross-sectional area, p-type impurity concentration, etc. shown in the above embodiments may be values ​​at any position in third nitride semiconductor layer 106, fourth nitride semiconductor layer 107, and fifth nitride semiconductor layer 108, or may be statistical values ​​of values ​​at multiple positions. The statistical value is an average value, but may also be, for example, a maximum value, minimum value, median value, mode value, etc.

[0214] Furthermore, the threshold voltage, the total number of holes, the impurity concentration, and the like in the above-described embodiments may be values ​​measured using a gate electrode and a nitride semiconductor layer formed on a dedicated evaluation substrate.

[0215] Furthermore, the order of the steps in the semiconductor device manufacturing method described in the above embodiments may be interchanged. Furthermore, the steps in the semiconductor device manufacturing method described in the above embodiments may be performed in a single process or in separate processes. Note that "performed in a single process" is intended to include the cases where each process is performed using a single device, where each process is performed consecutively, or where each process is performed at the same location. Furthermore, "separate processes" is intended to include the cases where each process is performed using a separate device, where each process is performed at a different time (e.g., on a different day), or where each process is performed at a different location.

[0216] The present disclosure is useful for a semiconductor device using a nitride semiconductor and a method for manufacturing the same.

[0217] 100, 100A, 100B, 100C, 100D, 100E, 100F Semiconductor device 101 Substrate 102 Buffer layer 103 First nitride semiconductor layer 104 Second nitride semiconductor layer 105 Two-dimensional electron gas layer 106 Third nitride semiconductor layer 106b, 107b Upper surface 106b1 First upper surface 106b2 Second upper surface 107 Fourth nitride semiconductor layer 107a Portion 108 Fifth nitride semiconductor layer 201 Dielectric layer 202 Insulator layer 301 Source electrode 302 Drain electrode 303 First gate electrode 304 Second gate electrode 305 Gate wiring 306 Gate electrode connection portion 307 Third gate electrode 308 Barrier layer 401 Source wiring layer 402 Drain wiring layer 501 Source electrode connection opening 502 Drain electrode connection opening 503 Gate wiring connection opening 601 Active region 602 Inactive region 701 Nitride semiconductor layer 701a First gate electrode region 702 Conductive layer d Distance L1 First gate length L2 Second gate length L3 Third gate length M1 First mask M2 Second mask R1 First region R2 Second region t1, t2, t11, t12 Thickness

Claims

1. A semiconductor device comprising: A first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a p-type third nitride semiconductor layer provided on the second nitride semiconductor layer; a p-type fourth nitride semiconductor layer provided on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer; a source electrode and a drain electrode provided in contact with the second nitride semiconductor layer at positions sandwiching the third nitride semiconductor layer and the fourth nitride semiconductor layer; a first gate electrode provided on and in contact with the third nitride semiconductor layer; a second gate electrode provided on the fourth nitride semiconductor layer via a dielectric layer and having the same potential as the first gate electrode; In a cross-sectional view including the source electrode and the drain electrode, when a length of the third nitride semiconductor layer in contact with the second nitride semiconductor layer is defined as a first gate length and a length of the fourth nitride semiconductor layer in contact with the second nitride semiconductor layer is defined as a second gate length, (i) the second gate length is smaller than the first gate length, (ii) the thickness of the fourth nitride semiconductor layer is smaller than the thickness of the third nitride semiconductor layer, and (iii) the concentration of p-type impurities contained in the fourth nitride semiconductor layer is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer; The threshold voltage of the semiconductor device is a positive value. Semiconductor device.

2. The fourth nitride semiconductor layer is located between the third nitride semiconductor layer and the drain electrode. The semiconductor device according to claim 1 .

3. The second gate length is 80% or less of the first gate length.

3. The semiconductor device according to claim 1 or 2.

4. The fourth nitride semiconductor layer is thinner than the third nitride semiconductor layer.

3. The semiconductor device according to claim 1 or 2.

5. The thickness of the fourth nitride semiconductor layer is 80% or less of the thickness of the third nitride semiconductor layer. The semiconductor device according to claim 4.

6. the third nitride semiconductor layer has a first upper surface in contact with the first gate electrode and a second upper surface located at a height position lower than the first upper surface; The second upper surface and the upper surface of the fourth nitride semiconductor layer are at the same height. The semiconductor device according to claim 4.

7. The first gate electrode and the second gate electrode are connected to each other via a metal layer provided between the first gate electrode and the second gate electrode.

3. The semiconductor device according to claim 1 or 2.

8. The second gate electrode is provided on the fourth nitride semiconductor layer via the dielectric layer and an insulator layer different from the dielectric layer.

3. The semiconductor device according to claim 1 or 2.

9. The threshold voltage of a second transistor formed of the source electrode, the drain electrode, and the second gate electrode is a positive value.

3. The semiconductor device according to claim 1 or 2.

10. A concentration of a p-type impurity contained in the third nitride semiconductor layer is higher than a concentration of a p-type impurity contained in the fourth nitride semiconductor layer.

3. The semiconductor device according to claim 1 or 2.

11. A p-type impurity concentration contained in the fourth nitride semiconductor layer is 80% or less of a p-type impurity concentration contained in the third nitride semiconductor layer. The semiconductor device according to claim 10.

12. the fourth nitride semiconductor layer is composed of a plurality of portions spaced apart from each other along an extension direction of the third nitride semiconductor layer, The second gate electrode is provided above each of the plurality of portions via the dielectric layer.

3. The semiconductor device according to claim 1 or 2.

13. The distance between the ends of the plurality of portions is 0.3 μm or more. The semiconductor device according to claim 12.

14. The average value of the distance between the ends of the plurality of portions divided by the average value of the lengths of the plurality of portions in the arrangement direction is 0.5 or less. The semiconductor device according to claim 12.

15. A threshold voltage of a second transistor formed of the source electrode, the drain electrode, and the second gate electrode is equal to or lower than a threshold voltage of a first transistor formed of the source electrode, the drain electrode, and the first gate electrode.

3. The semiconductor device according to claim 1 or 2.

16. a p-type fifth nitride semiconductor layer provided on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer and the fourth nitride semiconductor layer; a third gate electrode provided on the fifth nitride semiconductor layer via the dielectric layer and having the same potential as the first gate electrode; When a length of the fifth nitride semiconductor layer in contact with the second nitride semiconductor layer in the cross-sectional view is defined as a third gate length, (iv) the third gate length is smaller than the first gate length, (v) the thickness of the fifth nitride semiconductor layer is smaller than the thickness of the third nitride semiconductor layer, and (vi) the concentration of p-type impurities contained in the fifth nitride semiconductor layer is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer.

3. The semiconductor device according to claim 1 or 2.

17. The second gate electrode and the third gate electrode are on the same side of the source electrode side and the drain electrode side with respect to the first gate electrode. The semiconductor device according to claim 16.

18. a first step of forming a second nitride semiconductor layer on a first nitride semiconductor layer, the second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer; a second step of forming a p-type third nitride semiconductor layer and a p-type fourth nitride semiconductor layer on a portion of the second nitride semiconductor layer; a third step of forming a dielectric layer so as to cover upper surfaces of the third nitride semiconductor layer, the fourth nitride semiconductor layer, and the second nitride semiconductor layer; a fourth step of forming a source electrode and a drain electrode at positions sandwiching the third nitride semiconductor layer and the fourth nitride semiconductor layer; a fifth step of forming a first gate electrode in an opening formed on the third nitride semiconductor layer with respect to the dielectric layer, and forming a second gate electrode having the same potential as the first gate electrode above the fourth nitride semiconductor layer via the dielectric layer; In a cross-sectional view including the source electrode and the drain electrode, when a length of the third nitride semiconductor layer in contact with the second nitride semiconductor layer is defined as a first gate length and a length of the fourth nitride semiconductor layer in contact with the second nitride semiconductor layer is defined as a second gate length, The third nitride semiconductor layer and the fourth nitride semiconductor layer are formed so as to satisfy at least one of the following: (i) the second gate length is smaller than the first gate length; (ii) the thickness of the fourth nitride semiconductor layer is smaller than the thickness of the third nitride semiconductor layer; and (iii) the concentration of p-type impurities contained in the fourth nitride semiconductor layer is smaller than the concentration of p-type impurities contained in the third nitride semiconductor layer. A method for manufacturing a semiconductor device.

19. In the fifth step, the opening is formed by dry etching using a gas containing a p-type impurity. The method for manufacturing a semiconductor device according to claim 18.

20. The second step is forming a p-type nitride semiconductor layer on the second nitride semiconductor layer; forming a conductive layer on the nitride semiconductor layer; and continuously removing a portion of the conductive layer and the nitride semiconductor layer in a region other than a gate electrode region; A region including the gate electrode region is defined as a first region, and a region adjacent to and spaced from the first region is defined as a second region. The nitride semiconductor layer is completely removed by etching that covers the first region and the second region, and the conductive layer remaining in the first region is defined as the first gate electrode, the nitride semiconductor layer remaining in the first region is defined as the third nitride semiconductor layer, and the nitride semiconductor layer remaining in the second region is defined as the fourth nitride semiconductor layer. The method for manufacturing a semiconductor device according to claim 18 or 19.

21. in the third step, after the third nitride semiconductor layer and the fourth nitride semiconductor layer are formed, the dielectric layer is formed on upper surfaces of the third nitride semiconductor layer and the fourth nitride semiconductor layer by a plasma CVD method; The first gate electrode is formed using a material having a hydrogen permeation barrier property greater than that of the third nitride semiconductor layer, or a material having a hydrogen occlusion property greater than that of the third nitride semiconductor layer. The method for manufacturing a semiconductor device according to claim 18 or 19.

22. In the third step, the dielectric layer is formed using a raw material containing an impurity that provides n-type conductivity. The method for manufacturing a semiconductor device according to claim 18 or 19.

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