Semiconductor device and method for producing semiconductor device

Abstract

A semiconductor device (1) comprises: an electron transit layer (103); an electron supply layer (104) that is provided on the electron transit layer (103) and that has a band gap greater than that of the electron transit layer (103); a gate electrode (303) that is provided on the electron supply layer (104); contact layers (212) that are embedded, at positions between which the gate electrode (303) is sandwiched, in a through-recessed part (211) which passes through the electron supply layer (104); a first insulation layer (201) that is provided on a part of the electron supply layer (104) to which the gate electrode (303) is not provided; and a second insulation layer (202) that is provided on the first insulation layer (201) such that the second insulation layer (202) is in contact with the contact layers (212) but is not in contact with the gate electrode (303), wherein the coefficient of linear thermal expansion of the second insulation layer (202) is higher than the coefficient of linear thermal expansion of the electron supply layer (104).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a Group III nitride semiconductor device using a Group III nitride semiconductor and a manufacturing method thereof.

[0002] Group III nitride semiconductors, particularly those using gallium nitride (GaN) or aluminum gallium nitride (AlGaN), have high breakdown voltages due to the wide band gaps of the materials. Furthermore, heterostructures such as AlGaN / GaN can be easily formed in Group III nitride semiconductor devices.

[0003] In an AlGaN / GaN heterostructure, the difference between the piezoelectric polarization caused by the difference in lattice constant between the materials and the spontaneous polarization of AlGaN and GaN generates a high concentration of electrons (two-dimensional electron gas) on the GaN layer side of the interface between the AlGaN layer and the GaN layer, forming a channel of the two-dimensional electron gas layer. Group III nitride semiconductor devices that utilize this two-dimensional electron gas channel have a relatively high electron saturation velocity, relatively high insulation resistance, and relatively high thermal conductivity, and are therefore applied to high-frequency power devices, etc.

[0004] In order to improve the characteristics of these Group III nitride semiconductor devices, it is advisable to reduce as much as possible parasitic resistance components such as the contact between the ohmic electrode and the two-dimensional electron gas layer in the Group III nitride semiconductor device (hereinafter referred to as "ohmic contact") and the channel resistance due to the two-dimensional electron gas.

[0005] Conventionally, techniques for reducing ohmic contact resistance have been proposed for Group III nitride semiconductor devices that utilize a channel formed by two-dimensional electron gas. For example, Patent Document 1 discloses a technique for reducing ohmic contact resistance by forming a recess (hereinafter referred to as a "through recess") that penetrates an electron supply layer made of AlGaN in a portion of a Group III nitride semiconductor device where an ohmic electrode is to be formed, and then selectively regrowing a low-energy barrier material such as n-GaN or n-InGaN to form a contact layer.

[0006] Japanese Patent Application Laid-Open No. 2019-114581

[0007] However, when a through recess is formed in the electron supply layer as in the technology disclosed in Patent Document 1, it is inevitable that the two-dimensional electron gas layer and the contact layer embedded in the through recess will essentially be connected at a point. Furthermore, when a through recess is formed in the electron supply layer, not only do crystal defects occur at the interface between the two-dimensional electron gas layer (channel layer) made of GaN and the contact layer when the through recess is formed, but also atmospheric pollutants and bond defects cause a region of reduced carrier (electron) concentration in the electron supply layer adjacent to the side surface of the through recess, resulting in a decrease in the maximum drain current.

[0008] The present disclosure has been made in view of the above-described problems, and aims to provide a semiconductor device capable of suppressing a decrease in maximum drain current, and a method for manufacturing the same.

[0009] In order to achieve the above object, one aspect of a first semiconductor device according to the present disclosure includes an electron transit layer, an electron supply layer provided on the electron transit layer and having a band gap larger than that of the electron transit layer, a gate electrode provided on the electron supply layer, source-side contact layers and drain-side contact layers embedded in recesses that penetrate the electron supply layer at positions on either side of the gate electrode, a first insulating layer provided on a portion of the electron supply layer where the gate electrode is not provided, and a second insulating layer provided on the first insulating layer in contact with the source-side contact layer and / or drain-side contact layer but not in contact with the gate electrode, wherein the linear thermal expansion coefficient of the second insulating layer is larger than the linear thermal expansion coefficient of the electron supply layer.

[0010] Furthermore, one aspect of a second semiconductor device according to the present disclosure includes an electron transit layer, an electron supply layer provided on the electron transit layer and having a band gap larger than that of the electron transit layer, a gate electrode provided on the electron supply layer, contact layers embedded in recesses that penetrate the electron supply layer at positions on either side of the gate electrode, a source electrode or a drain electrode provided on the contact layer, a first insulating layer provided on a portion of the electron supply layer where the gate electrode is not provided, and a second insulating layer provided on the first insulating layer in contact with the contact layer but not in contact with the gate electrode, wherein the second insulating layer includes an oxynitride layer or a composite layer of oxide and nitride.

[0011] a first insulating layer on the first insulating layer, the first insulating layer having a band gap larger than that of the electron transit layer; a second insulating layer on the first insulating layer, the second insulating layer having a band gap larger than that of the electron transit layer; a first insulating layer on the first insulating layer, the first insulating layer having a band gap larger than that of the electron transit layer; a first insulating layer on the first insulating layer, the second insulating layer having a band gap larger than that of the electron transit layer; a first insulating layer on the first insulating layer, the second insulating layer having a band gap larger than that of the electron transit layer; a first insulating layer on the first insulating layer, the second insulating layer having a band gap larger than that of the electron transit layer; a first insulating layer on the first insulating layer, the second insulating layer having a band gap larger than that of the electron transit layer; a first insulating layer on the first insulating layer, the second insulating layer having a band gap larger than that of the electron transit layer; a second ...

[0012] According to the present disclosure, a semiconductor device capable of suppressing a decrease in maximum drain current can be obtained.

[0013] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. FIG. 2 is a schematic diagram showing the conduction band of the energy band of the semiconductor device according to the first embodiment. FIG. 3A is a cross-sectional view showing a step of forming a semiconductor stacked structure and a first insulating layer and a second insulating layer in a manufacturing method of a semiconductor device according to the first embodiment. FIG. 3B is a cross-sectional view showing a step of forming a through-hole recess in a manufacturing method of a semiconductor device according to the first embodiment. FIG. 3C is a cross-sectional view showing a step of forming a contact layer in a manufacturing method of a semiconductor device according to the first embodiment. FIG. 3D is a cross-sectional view showing a step of forming a source electrode and a drain electrode in a manufacturing method of a semiconductor device according to the first embodiment. FIG. 3E is a cross-sectional view showing a step of patterning a second insulating layer in a manufacturing method of a semiconductor device according to the first embodiment. FIG. 3F is a cross-sectional view showing a step of forming a gate electrode in a manufacturing method of a semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device according to a modification of the first embodiment. FIG. 5 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. FIG. 6 is a schematic diagram showing the conduction band of the energy band of the semiconductor device according to the second embodiment. FIG. 7A is a cross-sectional view showing a step of forming a semiconductor stacked structure and a first insulating layer in a manufacturing method of a semiconductor device according to the second embodiment. FIG. 7B is a cross-sectional view showing a step of forming a through recess portion in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 7C is a cross-sectional view showing a step of forming a contact layer in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 7D is a cross-sectional view showing a step of forming a second insulating layer in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 7E is a cross-sectional view showing a step of forming a source electrode and a drain electrode in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 7F is a cross-sectional view showing a step of patterning the second insulating layer in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 7G is a cross-sectional view showing a step of forming a gate electrode in the method for manufacturing a semiconductor device according to the second embodiment.

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Each embodiment shown here represents a specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangement and connection of the components, steps (processes), and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in the following embodiments, components that are not described in the independent claims that represent the superordinate concept of the present disclosure will be described as optional components.

[0015] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, the scales and the like do not necessarily match in each figure. In each figure, the same reference numerals are used to denote substantially the same components, and redundant explanations will be omitted or simplified.

[0016] Furthermore, in this specification, the terms "above," "upper," "below," and "belower" in the configuration of a semiconductor device do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are terms defined by a relative positional relationship based on the stacking order in a stacked structure. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0017] In addition, in this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In each embodiment, the two axes parallel to the top surface of the substrate of the semiconductor device are defined as the x-axis and y-axis, and the direction perpendicular to this top surface is defined as the z-axis direction. In the embodiments described below, the positive direction of the z-axis may be referred to as "up" and the negative direction of the z-axis may be referred to as "down." Note that in this specification, "planar view" refers to the substrate of the semiconductor device viewed from the positive direction of the z-axis.

[0018] First Embodiment First, a semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing the configuration of the semiconductor device 1 according to the first embodiment.

[0019] In this embodiment, a case will be described in which the semiconductor device 1 is a high electron mobility transistor (HEMT) having a Schottky junction gate structure.

[0020] 1, the semiconductor device 1 includes a substrate 101, a buffer layer 102, an electron transit layer 103, an electron supply layer 104, a first insulating layer 201, a second insulating layer 202, a source electrode 301, a drain electrode 302, and a gate electrode 303. The buffer layer 102, the electron transit layer 103, and the electron supply layer 104 form a semiconductor stacked structure 100 made of semiconductor materials.

[0021] The substrate 101 is, for example, a silicon substrate made of Si. In this embodiment, the substrate 101 is a silicon substrate made of single-crystal Si with a (111) plane as its main surface. The substrate 101 is not limited to a silicon substrate, and may be a substrate made of sapphire, SiC, GaN, AlN, or the like, which serves as a base for forming a nitride semiconductor layer. The resistivity of the substrate 101 is, for example, 1 kΩ or more. The substrate 101 may have a resistivity of 20 Ω or less.

[0022] The buffer layer 102 is provided on the substrate 101. The buffer layer 102 is, for example, a 2 μm-thick Group III nitride semiconductor layer made of a multi-layer structure of AlN and AlGaN. In this case, 20 to 100 pairs of AlN and AlGaN may be stacked. １－α Ga α The buffer layer 102 may have a structure in which multiple N (0≦α<0.8) layers are stacked, and may include a superlattice structure. Alternatively, the buffer layer 102 may be composed of a single layer or multiple layers of a group III nitride semiconductor such as InGaN or AlInGaN. The carbon concentration of the buffer layer 102 may be 1×10 １９ atoms / cm ３ As described above, the resistance of the buffer layer 102 may be increased.

[0023] The electron transit layer 103 is provided on the buffer layer 102. In this embodiment, the electron transit layer 103 is, for example, a GaN layer made of GaN with a thickness of 150 nm. The Group III nitride semiconductor making up the electron transit layer 103 is not limited to GaN. The electron transit layer 103 may be made of a Group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN. The electron transit layer 103 may also contain n-type impurities.

[0024] The electron supply layer 104 is provided on the electron transit layer 103. The electron supply layer 104 has a larger band gap than the electron transit layer 103. In this embodiment, the electron supply layer 104 is, for example, a 13-nm-thick AlGaN layer made of AlGaN with an Al composition ratio of 30%. A high concentration of two-dimensional electron gas is generated on the electron transit layer 103 side of the heterointerface between the electron supply layer 104 and the electron transit layer 103, forming a channel of the two-dimensional electron gas layer 105. Therefore, the semiconductor device 1 has the two-dimensional electron gas layer 105. As will be described in detail later, the two-dimensional electron gas layer 105 is composed of a first two-dimensional electron gas layer 105A and a second two-dimensional electron gas layer 105B having different electron concentrations of the two-dimensional electron gas.

[0025] The Al composition ratio of the electron supply layer 104 made of AlGaN is not limited to 30%. The Al composition ratio of the electron supply layer 104 may be 20 to 100%. Furthermore, the group III nitride semiconductor constituting the electron supply layer 104 is not limited to AlGaN. The electron supply layer 104 may be composed of a group III nitride semiconductor containing In, such as AlInGaN. Furthermore, the electron supply layer 104 may contain n-type impurities.

[0026] A cap layer may be provided on the electron supply layer 104. The cap layer may be, for example, a GaN layer made of GaN and having a thickness of about 1 to 2 nm. A spacer layer may be provided between the electron transit layer 103 and the electron supply layer 104. The spacer layer may be, for example, an AlN layer made of AlN and having a thickness of about 1 nm.

[0027] The first insulating layer 201 is provided on the electron supply layer 104. The first insulating layer 201 is a SiN layer made of SiN. In this embodiment, the first insulating layer 201 is a SiN layer made of in-situ SiN and having a thickness of 2 nm. Note that "in-situ" means that it is formed without exposure to the atmosphere. Therefore, the first insulating layer 201 made of in-situ SiN is a SiN layer formed without exposure to the atmosphere after the electron supply layer 104 is formed.

[0028] By forming the first insulating layer 201 from in-situ SiN in this way, it is possible to eliminate uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104. Eliminating uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104 suppresses the generation of interface states. This makes it possible to avoid an increase in the potential at the interface and suppress a decrease in the electron concentration of the two-dimensional electron gas.

[0029] The thickness of the first insulating layer 201 is preferably 2 nm or more and 30 nm or less. By making the thickness of the first insulating layer 201 2 nm or more, it is possible to suppress uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104 due to natural oxidation. On the other hand, if the thickness of the first insulating layer 201 exceeds 30 nm, the wafer will warp when the semiconductor device 1 is fabricated, degrading the quality of the semiconductor device 1. For this reason, it is preferable that the thickness of the first insulating layer 201 be 30 nm or less. In other words, by making the thickness of the first insulating layer 201 30 nm or less, it is possible to suppress warping of the wafer.

[0030] It is also preferable that the first insulating layer 201 does not contain oxygen. If the first insulating layer 201 contains oxygen, the interface state at the interface between the first insulating layer 201 and the electron supply layer 104 increases, the potential at the interface between the first insulating layer 201 and the electron supply layer 104 increases, and the electron concentration of the two-dimensional electron gas decreases. If the first insulating layer 201 does not contain oxygen, it is possible to suppress a decrease in the electron concentration of the two-dimensional electron gas.

[0031] An opening 201a is provided in the first insulating layer 201. The opening 201a is formed in a region of the first insulating layer 201 where the gate electrode 303 is to be provided. Therefore, the first insulating layer 201 is provided on a portion of the electron supply layer 104 where the gate electrode 303 is not provided. In this embodiment, the gate electrode 303 provided in the opening 201a of the first insulating layer 201 reaches the electron supply layer 104. In other words, the gate electrode 303 is in contact with the electron supply layer 104.

[0032] The electron supply layer 104 has a through-hole recess 211. In the present embodiment, the through-hole recess 211 is provided so as to penetrate through the first insulating layer 201 and the electron supply layer 104 and reach the electron transit layer 103. The through-hole recess 211 reaches the inside of the electron transit layer 103, and a recess is provided in the electron transit layer 103.

[0033] The distance from the upper surface of the electron transit layer 103 to the lowest part of the bottom surface of the through-hole recess 211 is preferably 10 nm or less. As an example, the distance from the upper surface of the electron transit layer 103 to the lowest part of the bottom surface of the through-hole recess 211 is 5 nm. The angle of elevation from the center to the side of the bottom surface of the through-hole recess 211 is preferably 10 degrees or less, and more preferably 5 degrees or less. This can reduce the occurrence of crystal defects on the side surface of the through-hole recess 211 when forming the through-hole recess 211 by dry etching, and can suppress a decrease in the maximum drain current.

[0034] The through-hole recess 211 is provided in a region corresponding to the region where the source electrode 301 and the drain electrode 302 are provided. Specifically, a pair of through-hole recesses 211 are provided so as to face each other with the gate electrode 303 interposed therebetween.

[0035] A contact layer 212 is provided in the through-hole recess 211. The contact layer 212 is provided so as to fill the through-hole recess 211. The contact layer 212 provided in one of the pair of through-hole recesses 211 is a source-side contact layer 212A, and the contact layer 212 provided in the other of the pair of through-hole recesses 211 is a drain-side contact layer 212B. The source-side contact layer 212A and the drain-side contact layer 212B are provided at positions sandwiching the gate electrode 303.

[0036] The contact layer 212 is, for example, an n-GaN layer made of n-type GaN. The material constituting the contact layer 212 is not limited to n-type GaN. It may be made of a group III nitride semiconductor such as InGaN, AlGaN, or AlInGaN containing a donor such as Si or Ge as an n-type impurity, or may be made of a multilayer electrode film having a stacked structure in which Ti and Al are stacked in order. The material constituting the contact layer 212 may also be made of Ti, Ta, Al, Au, Hf, Ru, and Cu.

[0037] A source electrode 301 or a drain electrode 302 is provided on the contact layer 212. Specifically, the source electrode 301 is provided on the source-side contact layer 212A, and the drain electrode 302 is provided on the drain-side contact layer 212B. The source electrode 301 and the drain electrode 302 are provided to face each other with the gate electrode 303 interposed therebetween. The source electrode 301 and the drain electrode 302 are, for example, multilayer electrode films having a laminated structure in which a 30-nm-thick Ti film and a 200-nm-thick Al film are laminated in this order, but are not limited to this. The source electrode 301 and the drain electrode 302 may also be formed using Ti, Ta, W, Al, Au, Hf, Ru, and Cu.

[0038] The gate electrode 303 is provided on the electron supply layer 104. Specifically, the gate electrode 303 is provided on the electron supply layer 104 via an opening 201a provided in the first insulating layer 201.

[0039] The gate electrode 303 is a multilayer electrode film having a laminated structure in which, for example, a TiN film and an Al film are laminated in order. The gate electrode 303 is not limited to a laminated structure of a TiN film and an Al film, and may be composed of a transition metal nitride or carbide. Specifically, the gate electrode 303 may be composed of TiN, WN, TaN, or HfN. The gate electrode 303 may also be composed of Ti, Ta, W, Al, Pd, Pt, Hf, Ru, and Cu, or may be a compound containing these elements, or may be a multilayer electrode film having a laminated structure of multiple elements. Another insulating layer or a p-type nitride semiconductor layer may be provided between the electron supply layer 104 and the gate electrode 303.

[0040] The second insulating layer 202 is provided on the first insulating layer 201. In this embodiment, the second insulating layer 202 is in contact with the first insulating layer 201.

[0041] The second insulating layer 202 is provided so as to be in contact with the contact layer 212. Specifically, the second insulating layer 202 is in contact with the source-side contact layer 212A and / or the drain-side contact layer 212B. That is, the second insulating layer 202 may be in contact with either the source-side contact layer 212A or the drain-side contact layer 212B. In this embodiment, the second insulating layer 202 is in contact with each of the source-side contact layer 212A and the drain-side contact layer 212B. The second insulating layer 202 may be divided into multiple layers. In this case, one of the multiple second insulating layers 202 may be in contact with the source-side contact layer 212A, and another of the multiple second insulating layers 202 may be in contact with the drain-side contact layer 212B.

[0042] Furthermore, the second insulating layer 202 is provided without contacting the gate electrode 303. In other words, the second insulating layer 202 is provided at a distance from the gate electrode 303. In other words, it is better not to provide the second insulating layer 202 too close to the gate electrode 303.

[0043] In a cross-sectional view, the width of the second insulating layer 202 in contact with one of the source-side contact layer 212A and the drain-side contact layer 212B is preferably smaller than the distance between the gate-side end of the second insulating layer 202 and the second insulating layer 202-side end of the gate electrode 303. Specifically, the width of the second insulating layer 202 is preferably 1 μm or less. In particular, the width of the second insulating layer 202 in contact with the drain-side contact layer 212B (the second insulating layer 202 on the drain electrode 302 side) is preferably 1 μm or less. This can suppress leakage current between the gate electrode 303 and the drain electrode 302. Note that, as long as the second insulating layer 202 on the drain electrode 302 side and the gate electrode 303 are spaced apart, the second insulating layer 202 on the source electrode 301 side may be in contact with the gate electrode 303. This can reduce the access resistance between the source electrode 301 and the gate electrode 303, thereby increasing the maximum drain current.

[0044] An opening 202a is provided in the second insulating layer 202. The opening 202a is formed in a region of the second insulating layer 202 where the gate electrode 303 is to be provided. The opening width of the opening 202a in the second insulating layer 202 is larger than the opening width of the opening 201a in the first insulating layer 201.

[0045] The linear thermal expansion coefficient of the second insulating layer 202 is greater than the linear thermal expansion coefficient of the electron supply layer 104. Furthermore, the tensile stress of the second insulating layer 202 is greater than the tensile stress of the first insulating layer 201. In this embodiment, the density of the second insulating layer 202 is greater than the density of the first insulating layer 201. That is, the density of the first insulating layer 201 is smaller than the density of the second insulating layer 202. Note that in this embodiment, the first insulating layer 201 and the second insulating layer 202 are made of the same material, but the density of the second insulating layer 202 is greater than the density of the first insulating layer 201.

[0046] In this embodiment, the second insulating layer 202 is a SiN layer made of SiN, similar to the first insulating layer 201. Specifically, the second insulating layer 202 is, for example, a 10 nm thick SiN layer made of SiN. The thickness of the second insulating layer 202 is not limited to 10 nm. For example, the thickness of the second insulating layer 202 may be 10 nm or more and 30 nm or less. In this embodiment, the thickness of the second insulating layer 202 is thicker than the thickness of the first insulating layer 201, but is not limited to this. That is, the thickness of the second insulating layer 202 may be thinner than the thickness of the first insulating layer 201. The thickness of the second insulating layer 202 may increase from the gate electrode 303 toward the contact layer 212. In this case, the increase in the thickness of the second insulating layer 202 may be continuous or discontinuous. In this embodiment, the second insulating layer 202 is a single layer, but may be multiple layers.

[0047] By configuring the semiconductor device 1 with such a structure, the electron concentration of the two-dimensional electron gas layer 105 can be made different between a portion where the second insulating layer 202 is present and a portion where the second insulating layer 202 is not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A in a portion not located below the second insulating layer 202 and a second two-dimensional electron gas layer 105B in a portion located below the second insulating layer 202, and the electron concentration of the second two-dimensional electron gas layer 105B is higher than the electron concentration of the first two-dimensional electron gas layer 105A. Note that the contact layer 212 in contact with the second insulating layer 202 and the second two-dimensional electron gas layer 105B are electrically ohmically connected.

[0048] Here, the mechanism by which the electron concentration of the second two-dimensional electron gas layer 105B becomes higher than the electron concentration of the first two-dimensional electron gas layer 105A will be described with reference to Fig. 2. Fig. 2 is a schematic diagram showing the conduction band of the energy band of the semiconductor device 1 according to the first embodiment.

[0049] 2, solid line A is a diagram of a portion corresponding to dashed-dotted line A in FIG. 1, and dashed line B is a diagram of a portion corresponding to dashed-dotted line B in FIG. 1. That is, solid line A in FIG. 2 is a diagram of a gate-adjacent portion adjacent to gate electrode 303 (i.e., a portion where only first insulating layer 201 is provided, without second insulating layer 202 being provided on first insulating layer 201). Also, dashed line B in FIG. 2 is a diagram of a contact-adjacent portion adjacent to contact layer 212 (i.e., a portion where second insulating layer 202 is provided on first insulating layer 201).

[0050] As described above, in the semiconductor device 1 according to the present embodiment, the linear thermal expansion coefficient of the second insulating layer 202 is greater than that of the electron supply layer 104. By providing the second insulating layer 202 with a linear thermal expansion coefficient greater than that of the electron supply layer 104, the tensile stress applied to the electron supply layer 104 at the contact-adjacent portion increases. This increases the piezoelectric polarization of the electron supply layer 104, reducing the potential at the interface between the electron supply layer 104 and the electron transit layer 103. As a result, the electron concentration of the second two-dimensional electron gas layer 105B increases. That is, the electron concentration of the second two-dimensional electron gas layer 105B located below the second insulating layer 202 becomes higher relative to the electron concentration of the first two-dimensional electron gas layer 105A not located below the second insulating layer 202.

[0051] In this way, the electron concentration of the second two-dimensional electron gas layer 105B is higher than the electron concentration of the first two-dimensional electron gas layer 105A, thereby preventing a decrease in the electron concentration in the electron supply layer 104 adjacent to the side surface of the through-hole recess 211. As a result, a decrease in the maximum drain current can be suppressed. Moreover, since the electron concentration in the gate-adjacent portion corresponding to the first two-dimensional electron gas layer 105A is maintained, the leakage current between the gate electrode 303 and the drain electrode 302 can also be reduced. In other words, the configuration of the semiconductor device 1 according to this embodiment can achieve both a suppression of a decrease in the maximum drain current and a reduction in the leakage current between the gate and the drain. Furthermore, the large contribution of the increase in the two-dimensional electron gas by the second insulating layer 202 can also reduce variations in the drain current caused by variations in the side surface condition of the through-hole recess 211 (variations in etching conditions).

[0052] In the semiconductor device 1 according to the present embodiment, the second insulating layer 202 may contain oxygen. For example, the second insulating layer 202 containing oxygen may be made of SiON or SiO ２ It can be configured as follows.

[0053] In this way, the second insulating layer 202 is made of SiON or SiO ２ By using an oxygen-containing layer (such as an oxide layer) such as SiN, the thermal expansion coefficient of the second insulating layer 202 can be increased, and the tensile stress of the second insulating layer 202 can be further increased, compared to when the second insulating layer 202 is a nitrogen-containing nitride layer such as SiN. This makes it possible to further increase the electron concentration of the second two-dimensional electron gas layer 105B relative to the electron concentration of the first two-dimensional electron gas layer 105A. This further reduces the decrease in electron concentration in the portion of the electron supply layer 104 adjacent to the side surface of the through-hole recess 211, and further suppresses a decrease in the maximum drain current.

[0054] In the semiconductor device 1 according to the present embodiment, the first insulating layer 201 and the second insulating layer 202 may contain halogen such as fluorine (F) or chlorine (Cl), but the halogen concentration in the first insulating layer 201 and the second insulating layer 202 is 1×10 １８atoms / cm ３ This is because halogen contained in the semiconductor layer or insulating layer has high electronegativity and becomes a negative fixed charge. Therefore, the halogen concentration of the first insulating layer 201 is preferably 1×10 or less. １８ atoms / cm ３ or less, it is possible to reduce the negative fixed charges in the first insulating layer 201. This makes it possible to prevent an increase in the potential at the interface between the electron supply layer 104 and the electron transit layer 103, and to prevent a decrease in the electron concentration in the second two-dimensional electron gas layer 105B due to the halogen.

[0055] Furthermore, in the semiconductor device 1 according to the present embodiment, the tensile stress of the second insulating layer 202 is greater than the tensile stress of the first insulating layer 201. This allows the electron concentration of the second two-dimensional electron gas layer 105B to be higher than the electron concentration of the first two-dimensional electron gas layer 105A. This further reduces the decrease in the electron concentration in the portion of the electron supply layer 104 adjacent to the side surface of the through-hole recess 211, thereby further suppressing a decrease in the maximum drain current. Furthermore, the thicker the second insulating layer 202, the greater the tensile stress of the second insulating layer 202. For example, it is preferable that the thickness of the second insulating layer 202 be greater than the thickness of the first insulating layer 201.

[0056] Furthermore, in the semiconductor device 1 according to the present embodiment, the first insulating layer 201 and the second insulating layer 202 are made of the same material, and the density of the second insulating layer 202 is greater than the density of the first insulating layer 201. The higher the density of the second insulating layer 202, the higher the mechanical strength, and therefore the stronger the tensile stress of the second insulating layer 202 on the electron supply layer 104. Therefore, by making the density of the second insulating layer 202 greater than the density of the first insulating layer 201, the electron concentration of the second two-dimensional electron gas layer 105B can be made higher than the electron concentration of the first two-dimensional electron gas layer 105A. This further reduces the decrease in the electron concentration in the portion of the electron supply layer 104 adjacent to the side surface of the through-hole recess 211, and further suppresses a decrease in the maximum drain current.

[0057] Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. 3A to 3F. FIGS. 3A to 3F are cross-sectional views illustrating steps in the method for manufacturing the semiconductor device 1 according to the first embodiment. FIG. 3A illustrates a step for forming the semiconductor stack 100, the first insulating layer 201, and the second insulating layer 202. FIG. 3B illustrates a step for forming the through-hole recess 211. FIG. 3C illustrates a step for forming the contact layer 212. FIG. 3D illustrates a step for forming the source electrode 301 and the drain electrode 302. FIG. 3E illustrates a step for patterning the second insulating layer 202. FIG. 3F illustrates a step for forming the gate electrode 303.

[0058] First, as shown in FIG. 3A , a semiconductor stacked structure 100 including a buffer layer 102, an electron transit layer 103, and an electron supply layer 104 is formed on a substrate 101 by metal organic chemical vapor deposition (MOCVD) (semiconductor stacked structure formation step).

[0059] In this embodiment, a semiconductor laminated structure 100 is formed on a substrate 101 made of Si by epitaxially growing, in the +c-plane direction (<0001> direction), a buffer layer 102 having a layer thickness of 2 μm and made of a laminated structure of AlN and AlGaN, an electron transit layer 103 having a layer thickness of 200 nm and made of GaN, and an electron supply layer 104 having a layer thickness of 20 nm and made of AlGaN with an Al composition ratio of 25%.

[0060] Next, a first insulating layer 201 made of SiN and a second insulating layer 202 made of SiN are sequentially formed on the semiconductor stack 100 (first insulating layer and second insulating layer forming process). In this embodiment, after the semiconductor stack 100 is formed, the first insulating layer 201 and the second insulating layer 202 are successively formed in the same semiconductor crystal growth apparatus (MOCVD furnace). That is, the first insulating layer 201 is formed on the electron supply layer 104 without exposure to the atmosphere, and the second insulating layer 202 is formed on the first insulating layer 201 without exposure to the atmosphere. In this manner, by forming the first insulating layer 201 directly on the electron supply layer 104 without exposure to the atmosphere, oxygen is not unevenly distributed between the electron supply layer 104 and the first insulating layer 201. In this structure, a high concentration of two-dimensional electron gas is generated on the electron transit layer 103 side of the heterointerface between the electron supply layer 104 and the electron transit layer 103, forming a two-dimensional electron gas layer 105.

[0061] The film formation conditions for forming the first insulating layer 201 and the second insulating layer 202 are, for example, a growth temperature of 900 to 1150° C. and a source gas of SiH ４ and N.H. ３ In addition, in order to prevent halogen from being mixed as an impurity into the first insulating layer 201 and the second insulating layer 202, it is better not to use halogen when dry cleaning the inside of the MOCVD furnace. Even if halogen is used during dry cleaning, N ２ and NH ３ It is advisable to remove halogens from the MOCVD furnace by using a method such as the above.

[0062] 3B , a portion of the semiconductor stack 100 is removed to form a through-hole recess 211 (through-hole recess forming step). In this embodiment, since the first insulating layer 201 and the second insulating layer 202 are formed on the semiconductor stack 100, portions of the first insulating layer 201 and the second insulating layer 202 are also removed together with the semiconductor stack 100.

[0063] Specifically, first, a resist is applied onto the second insulating layer 202, and then the resist is patterned by lithography to form a mask (resist mask) on the second insulating layer 202 except for the region where the contact layer 212 is to be formed (i.e., the region where the source electrode 301 and the drain electrode 302 are to be formed). That is, the resist has openings in the region where the contact layer 212 is to be formed. Specifically, the resist has openings in each of the regions where the source-side contact layer 212A and the drain-side contact layer 212B are to be formed.

[0064] Next, dry etching is performed using the resist with the openings as a mask to form through-hole recesses 211 that penetrate the first insulating layer 201, the second insulating layer 202, and the electron supply layer 104 and reach the electron transit layer 103. Specifically, as shown in FIG. 3B , two through-hole recesses 211 are formed corresponding to the regions where the source-side contact layer 212A and the drain-side contact layer 212B are to be formed. By forming the through-hole recesses 211, part of the electron transit layer 103 is exposed. Thereafter, the mask (resist) and the polymer generated by the dry etching are removed.

[0065] In this embodiment, the through-hole recess 211 is formed by dry etching, but the method is not limited to this. Specifically, the through-hole recess 211 may be formed by wet etching.

[0066] Next, as shown in FIG. 3C, a contact layer 212 is formed by filling the through-hole recess portion 211 (contact layer forming step).

[0067] Specifically, the second insulating layer 202 is used as a mask to form a n-type silicon nitride film by MOCVD so as to fill the two through-hole recess portions 211. ＋ -GaN is then regrown, thereby forming n-GaN in each of the two through recesses 211. ＋The contact layer 212 made of -GaN can be selectively embedded and formed. The contact layer 212 embedded in one of the two through-hole recesses 211 is a source-side contact layer 212A, and the contact layer 212 embedded in the other of the two through-hole recesses 211 is a drain-side contact layer 212B.

[0068] In this embodiment, Si is doped as an n-type impurity, and the n-type ＋ The contact layer 212 was formed by regrowing GaN. The Si doping concentration of the contact layer 212 was, for example, 2×10 １９ / cm ３ The contact layer 212 may be formed by sputtering instead of regrowth, or may be formed by ion implantation and plasma treatment without forming the penetrating recess portion 211.

[0069] Next, as shown in FIG. 3D, a source electrode 301 and a drain electrode 302 are formed on the contact layer 212 so as to be in contact with the contact layer 212 (source electrode / drain electrode forming step).

[0070] Specifically, a 30 nm thick Ti film and a 200 nm thick Al film are sequentially deposited by vapor deposition or sputtering to form a laminated film, and then unnecessary laminated film is removed by lift-off to form source electrode 301 and drain electrode 302 of predetermined shapes made of a laminated film of Ti film and Al film on contact layer 212. In this embodiment, source electrode 301 is formed on source-side contact layer 212A, and drain electrode 302 is formed on drain-side contact layer 212B. Then, the resist mask and polymer are removed.

[0071] Subsequently, a heat treatment is performed, which forms an ohmic electrical connection between the two-dimensional electron gas layer 105 and the contact layer 212.

[0072] In this embodiment, the source electrode 301 and the drain electrode 302 are formed by vapor deposition and lift-off, but the method is not limited to this. For example, a Ti film and an Al film may be deposited in this order by sputtering to form a laminated film, and then the laminated film may be patterned by lithography and dry etching to form the source electrode 301 and the drain electrode 302 in a predetermined shape.

[0073] Next, as shown in FIG. 3E, the second insulating layer 202 is patterned to remove the second insulating layer 202 from the portion where the gate electrode 303 is to be provided (second insulating layer patterning step).

[0074] Specifically, after applying resist, the resist is patterned into a predetermined shape by lithography to form a continuous mask (resist mask) in the region where the source electrode 301 and the drain electrode 302 are formed and in a region spaced from the region where the gate electrode 303 is to be formed (the region where the gate electrode 303 is to be formed). In this case, in a planar view, the end of the patterned resist on the drain electrode 302 side is located between the gate electrode 303 and the contact layer 212, and the end of the patterned resist on the gate electrode 303 side is located between the gate electrode 303 and the contact layer 212. Then, by dry etching, the second insulating layer 202 is removed except for the portion in contact with the contact layer 212, thereby exposing the first insulating layer 201 and forming the first insulating layer exposed portion 201s. At this time, the second insulating layer 202 located below the patterned resist (resist mask) is left unremoved. That is, the portion of the second insulating layer 202 in contact with the contact layer 212 remains. The resist and polymer are then removed. This makes it possible to form the second insulating layer 202 having the opening 202 a in the region where the gate electrode 303 is to be formed. At this time, the electron concentration of the two-dimensional electron gas located below the portion where the second insulating layer 202 is not formed becomes low, so that the two-dimensional electron gas layer 105 generates a first two-dimensional electron gas layer 105A having a relatively low electron concentration of the two-dimensional electron gas and a second two-dimensional electron gas layer 105B having a relatively high electron concentration of the two-dimensional electron gas.

[0075] Next, as shown in FIG. 3F, the first insulating layer 201 is removed from the exposed portion 201s of the first insulating layer 201 that is spaced apart from the second insulating layer 202 to form a gate electrode 303 (gate electrode formation process).

[0076] Specifically, a resist is applied to the exposed portion 201s of the first insulating layer 201, and then a mask (resist mask) is formed by lithography in an area other than the area where the gate electrode 303 is to be formed (the area where the gate electrode 303 is to be formed). Next, the first insulating layer 201 is selectively removed by dry etching to form an opening 201a in the first insulating layer 201 so that the electron supply layer 104 is exposed. Next, the mask (resist mask) and polymer generated by the dry etching are removed. Thereafter, the gate electrode 303 is formed in the opening 201a. Specifically, a stacked film is formed by sequentially depositing a 50-nm-thick TiN film and a 450-nm-thick Al film by sputtering, and then the stacked film is patterned by lithography and dry etching to form the gate electrode 303 having the predetermined shape shown in FIG. 3F. Then, the polymer generated by the mask and dry etching is removed.

[0077] In this way, the semiconductor device 1 having the structure shown in FIG. 1 is completed through the series of steps shown in FIGS. 3A to 3F.

[0078] 3A , when the second insulating layer 202 is formed, it is preferable that the second insulating layer 202 is formed at a higher temperature than the first insulating layer 201. In other words, the formation temperature of the second insulating layer 202 is preferably higher than the formation temperature of the first insulating layer 201. In other words, the formation temperature of the first insulating layer 201 is preferably lower than the formation temperature of the second insulating layer 202. This makes it possible to further increase the tensile stress of the second insulating layer 202 relative to the first insulating layer 201, even if the first insulating layer 201 and the second insulating layer 202 are made of the same material, such as SiN, and therefore the electron concentration of the second two-dimensional electron gas layer 105B can be further increased.

[0079] (Modification of First Embodiment) Next, a modification of the first embodiment will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view showing the configuration of a semiconductor device 1A according to a modification of the first embodiment.

[0080] As shown in FIG. 4 , the semiconductor device 1A according to this modification differs from the semiconductor device 1 according to the first embodiment in the configuration of the first insulating layer 201A and the second insulating layer 202A. Specifically, in the semiconductor device 1 according to the first embodiment, the first insulating layer 201 and the second insulating layer 202 are separate bodies. However, in the semiconductor device 1A according to this modification, the first insulating layer 201A and the second insulating layer 202A are made of the same material and are integrated into the insulating layer 203. That is, in this modification, the first insulating layer 201A and the second insulating layer 202A are part of the insulating layer 203. Therefore, the first insulating layer 201A is a first insulating layer portion of the insulating layer 203, and the second insulating layer 202A is a second insulating layer portion of the insulating layer 203.

[0081] Specifically, the insulating layer 203 has a recessed portion 203A. The portion of the insulating layer 203 where the recessed portion 203A is provided (i.e., the portion where the gate electrode 303 is formed) is composed only of the first insulating layer 201A (first insulating layer portion), while the portion where the recessed portion 203A is not provided is composed of the first insulating layer 201A (first insulating layer portion) and the second insulating layer 202 (second insulating layer portion). Therefore, the portion of the insulating layer 203 where the second insulating layer 202A (second insulating layer portion) is present has a thickness greater than the portion of the insulating layer 203 where the first insulating layer 201A (first insulating layer portion) is present. As an example, the thickness of the portion of the insulating layer 203 where the recessed portion 203A is formed is 5 nm, and the thickness of the portion of the insulating layer 203 where the recessed portion 203A is not formed is 25 nm. In view of damage to the electron supply layer 104 caused by dry etching, the thickness of the insulating layer 203 at the portion where the recessed portion 203A is formed is preferably 2 nm or more.

[0082] Furthermore, when manufacturing the semiconductor device 1A according to this modification, the first insulating layer 201A and the second insulating layer 202A are formed using the same material. Specifically, an insulating layer 203 made of in-situ SiN and having a thickness of 25 nm is formed on the electron supply layer 104, and then a recessed portion 203A is formed in the insulating layer 203 by dry etching so as to be spaced apart from the gate electrode 303. This allows the insulating layer 203 to have the shape shown in FIG. 4 to be formed.

[0083] The semiconductor device 1A according to this modification can also achieve the same effects as those of the first embodiment. Specifically, in this modification, the electron concentration of the second two-dimensional electron gas layer 105B is greater than the electron concentration of the first two-dimensional electron gas layer 105A. This can prevent the electron concentration in the electron supply layer 104 adjacent to the side surface of the through-hole recess 211 from decreasing, thereby suppressing a decrease in the maximum drain current.

[0084] Furthermore, in this modification, the first insulating layer 201A and the second insulating layer 202A can be integrally formed from the same material, so that the semiconductor device 1A can be manufactured more easily than in the first embodiment.

[0085] Second Embodiment Next, a semiconductor device 2 according to a second embodiment will be described with reference to Fig. 5. Fig. 5 is a cross-sectional view showing the configuration of the semiconductor device 2 according to the second embodiment. Note that the following description will focus on differences from the first embodiment, and description of commonalities will be omitted or simplified.

[0086] The semiconductor device 2 according to the present embodiment is different from the semiconductor device 1 according to the first embodiment in the configuration of the second insulating layer 202B. Specifically, the second insulating layer 202 of the semiconductor device 1 according to the first embodiment is made of SiN, whereas the second insulating layer 202B of the semiconductor device 2 according to the present embodiment is made of an oxynitride layer such as SiON. Note that the semiconductor device 2 according to the present embodiment is also a HEMT having a Schottky junction gate structure, similar to the first embodiment.

[0087] In this embodiment, the second insulating layer 202B is made of SiON and has a thickness of 20 nm. However, the thickness of the second insulating layer 202B is not limited to 20 nm. As an example, the thickness of the second insulating layer 202B is 2 nm or more and 200 nm or less.

[0088] In addition, the second insulating layer 202B in this embodiment is provided on the first insulating layer 201 in contact with the contact layer 212 but not in contact with the gate electrode 303, similar to the second insulating layer 202 in the first embodiment.

[0089] By configuring the semiconductor device 2 with such a structure, it is possible to make the electron concentration of the two-dimensional electron gas layer 105 different between the portion where the second insulating layer 202B is present and the portion where the second insulating layer 202B is not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A in a portion that is not located below the second insulating layer 202B, and a second two-dimensional electron gas layer 105B in a portion that is located below the second insulating layer 202B, and the electron concentration of the second two-dimensional electron gas layer 105B is higher than the electron concentration of the first two-dimensional electron gas layer 105A.

[0090] By providing the semiconductor device 2 with this structure, it is possible to make the electron concentration of the two-dimensional electron gas layer 105 different between the portion where the second insulating layer 202B is present and the portion where the second insulating layer 202B is not present, as in the above-described embodiment 1. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A in a portion that is not located below the second insulating layer 202B, and a second two-dimensional electron gas layer 105B in a portion that is located below the second insulating layer 202B, and the electron concentration of the second two-dimensional electron gas layer 105B is higher than the electron concentration of the first two-dimensional electron gas layer 105A.

[0091] Here, the mechanism by which the electron concentration of the second two-dimensional electron gas layer 105B becomes higher than the electron concentration of the first two-dimensional electron gas layer 105A in this embodiment will be described with reference to Fig. 6. Fig. 6 is a schematic diagram showing the conduction band of the energy band of the semiconductor device 2 according to the second embodiment.

[0092] 6, solid line A is a diagram of a portion corresponding to dashed-dotted line A in FIG. 5, and dashed line B is a diagram of a portion corresponding to dashed-dotted line B in FIG. 5. That is, solid line A in FIG. 6 is a diagram of a gate-adjacent portion adjacent to gate electrode 303 (i.e., a portion where second insulating layer 202B is not provided on first insulating layer 201 and only first insulating layer 201 is provided). Also, dashed line B in FIG. 2 is a diagram of a contact-adjacent portion adjacent to contact layer 212 (i.e., a portion where second insulating layer 202B is provided on first insulating layer 201).

[0093] In this embodiment, the second insulating layer 202B is formed of an oxynitride layer such as SiON, and therefore has a positive fixed charge. The positive fixed charge of the second insulating layer 202B reduces the potential of the electron supply layer 104, thereby reducing the potential at the interface between the electron supply layer 104 and the electron transit layer 103. This increases the electron concentration of the second two-dimensional electron gas layer 105B located below the second insulating layer 202B. In other words, the electron concentration of the second two-dimensional electron gas layer 105B becomes higher relative to the first two-dimensional electron gas layer 105A.

[0094] As described above, in the semiconductor device 2 according to the present embodiment, the electron concentration of the second two-dimensional electron gas layer 105B can be made higher than the electron concentration of the first two-dimensional electron gas layer 105A. This reduces the decrease in the electron concentration in the electron supply layer 104 adjacent to the side surface of the through-hole recess 211, thereby suppressing a decrease in the maximum drain current. Furthermore, in the present embodiment, the electron concentration in the gate-adjacent portion corresponding to the first two-dimensional electron gas layer 105A is maintained, thereby reducing the leakage current between the gate electrode 303 and the drain electrode 302. In other words, in the semiconductor device 2 according to the present embodiment, similar to the first embodiment, it is possible to simultaneously suppress a decrease in the maximum drain current and reduce the leakage current between the gate and the drain. Furthermore, because the second insulating layer 202 significantly contributes to an increase in the two-dimensional electron gas, variations in the drain current due to variations in the side surface condition of the through-hole recess 211 (variations in etching conditions) can also be reduced.

[0095] In this embodiment, the second insulating layer 202B is configured as an oxynitride layer, but this is not limiting. Specifically, the second insulating layer 202B may be a composite layer of an oxide and a nitride. In other words, the second insulating layer 202B may be a composite layer of an oxide layer and a layer of the same material as the first insulating layer 201. For example, the second insulating layer 202B may be a composite layer of SiN and SiO ２ In this way, even if the second insulating layer 202B is a composite layer with an oxide layer rather than an oxynitride layer, it will have a positive fixed charge, and therefore the electron concentration of the second two-dimensional electron gas layer 105B located below the second insulating layer 202B increases, which can prevent a decrease in the maximum drain current.

[0096] In this case, the SiO 2 that constitutes a part of the second insulating layer 202B ２ The film is preferably an extremely thin interfacial oxide layer having a thickness of 1 nm or less. ２ Since SiON has a positive fixed charge induced by the nitride, the same effect as that obtained when SiON having a positive fixed charge is used can be obtained.

[0097] Furthermore, in the semiconductor device 2 according to this embodiment, the second insulating layer 202B may include an n-type semiconductor layer. The n-type semiconductor layer included in the second insulating layer 202B may be, for example, a Group III semiconductor such as n-type GaN, or a Group IV semiconductor such as n-type polysilicon. When the second insulating layer 202B includes an n-type semiconductor layer, the electron concentration of the second two-dimensional electron gas layer 105B is higher than that of the first two-dimensional electron gas layer 105A. This can prevent a decrease in the electron concentration in the portion of the electron supply layer 104 adjacent to the side surface of the through-hole recess 211, thereby suppressing a decrease in the maximum drain current.

[0098] In the semiconductor device 2 of this embodiment, similarly to the first embodiment, the halogen concentration of the first insulating layer 201 is 1×10 １８ atoms / cm ３This can reduce the negative fixed charges in the first insulating layer 201, prevent an increase in the potential at the interface between the electron supply layer 104 and the electron transit layer 103, and prevent a decrease in the electron concentration in the first two-dimensional electron gas layer 105A and the second two-dimensional electron gas layer 105B due to halogen.

[0099] Next, a method for manufacturing the semiconductor device 2 according to the second embodiment will be described with reference to FIGS. 7A to 7G. FIGS. 7A to 7G are cross-sectional views illustrating steps in the method for manufacturing the semiconductor device 2 according to the second embodiment. FIG. 7A illustrates a step for forming the semiconductor stack 100 and the first insulating layer 201. FIG. 7B illustrates a step for forming the through-hole recess 211. FIG. 7C illustrates a step for forming the contact layer 212. FIG. 7D illustrates a step for forming the second insulating layer 202B. FIG. 7E illustrates a step for forming the source electrode 301 and the drain electrode 302. FIG. 7F illustrates a step for patterning the second insulating layer 202B. FIG. 7G illustrates a step for forming the gate electrode 303.

[0100] First, as shown in FIG. 7A, similarly to the first embodiment, a semiconductor laminated structure 100 including a buffer layer 102, an electron transit layer 103, and an electron supply layer 104 is formed on a substrate 101 by MOCVD.

[0101] Next, a first insulating layer 201 is formed on the semiconductor stacked structure 100 (first insulating layer forming step). In this embodiment, after the semiconductor stacked structure 100 is formed, the first insulating layer 201 is continuously formed in the same semiconductor crystal growth apparatus (MOCVD furnace). That is, the first insulating layer 201 is formed on the electron supply layer 104 without exposure to the atmosphere. By forming the first insulating layer 201 on the electron supply layer 101 without exposure to the atmosphere in this manner, oxygen is not unevenly distributed between the electron supply layer 104 and the first insulating layer 201. In this structure, a high concentration of two-dimensional electron gas is generated on the electron transit layer 103 side of the heterointerface between the electron supply layer 104 and the electron transit layer 103, forming a two-dimensional electron gas layer 105.

[0102] 7B , a portion of the semiconductor stack 100 is removed to form a penetrating recess 211 (a penetrating recess forming step). In this embodiment, since the first insulating layer 201 is formed on the semiconductor stack 100, a portion of the first insulating layer 201 is also removed together with the semiconductor stack 100.

[0103] Specifically, a resist is applied onto the first insulating layer 201, and then the resist is patterned by lithography to form a mask in the area excluding the area where the contact layer 212 is to be formed (i.e., the area where the source electrode 301 and the drain electrode 302 are to be formed). That is, openings are formed in the resist in the area where the contact layer 212 is to be formed. Specifically, openings are formed in each of the areas where the source-side contact layer 212A and the drain-side contact layer 212B are to be formed.

[0104] Next, dry etching is performed using a resist having openings as a mask to form through-hole recesses 211 that penetrate the first insulating layer 201 and the electron supply layer 104 and reach the electron transit layer 103. Specifically, as shown in FIG. 7B , two through-hole recesses 211 are formed corresponding to the regions where the source-side contact layer 212A and the drain-side contact layer 212B are to be formed. By forming the through-hole recesses 211, part of the electron transit layer 103 is exposed. After that, the mask (resist) and the polymer generated by the dry etching are removed.

[0105] Next, as shown in FIG. 7C, a contact layer 212 is formed by filling the through-hole recess 211 (contact layer forming step).

[0106] Specifically, similarly to the first embodiment, the first insulating layer 201 is used as a mask to form a n-type silicon nitride film by MOCVD so as to fill the two through-hole recess portions 211. ＋ -GaN is then regrown, thereby forming n-GaN in each of the two through recesses 211. ＋The contact layer 212 made of -GaN can be selectively embedded and formed. The contact layer 212 embedded in one of the two through-hole recesses 211 is a source-side contact layer 212A, and the contact layer 212 embedded in the other of the two through-hole recesses 211 is a drain-side contact layer 212B.

[0107] Next, as shown in FIG. 7D, a second insulating layer 202B is formed on the first insulating layer 201 (second insulating layer forming step).

[0108] Specifically, a second insulating layer 202B made of SiON as an oxynitride and having a thickness of 20 nm is formed on the first insulating layer 201. The film formation conditions for forming the second insulating layer 202B are, for example, a growth temperature of 900 to 1150° C. and a source gas of SiH ４ and N.H. ３ It is recommended to use

[0109] The second insulating layer 202B made of SiON is made of SiO ２ After forming the insulating layer 202B, heat treatment can be performed at a temperature of 800° C. or less in an atmosphere of oxygen and nitrogen. In this case, the second insulating layer 202B can be formed by forming the insulating layer 202B using SiON having a positive fixed charge. Alternatively, the second insulating layer 202B can be formed by forming the insulating layer 202B using SiON instead of performing heat treatment. ２ After forming NH ３ The second insulating layer 202B made of SiON having a positive fixed charge may be formed by performing a plasma nitriding process using plasma.

[0110] Next, as shown in FIG. 7E, a source electrode 301 and a drain electrode 302 are formed on the contact layer 212 so as to be in contact with the contact layer 212 (source electrode / drain electrode forming step).

[0111] Specifically, after removing a portion of the second insulating layer 202B to expose the contact layer 212, a Ti film and an Al film are sequentially deposited by vapor deposition to form a laminated film, as in the first embodiment, and then unnecessary laminated film is removed by a lift-off method, thereby forming the source electrode 301 and the drain electrode 302, each having a predetermined shape and made of a laminated film of a Ti film and an Al film, on the contact layer 212. In this embodiment, the source electrode 301 is formed on the source-side contact layer 212A, and the drain electrode 302 is formed on the drain-side contact layer 212B.

[0112] Thereafter, heat treatment is performed to electrically connect the two-dimensional electron gas layer 105 and the contact layer 212 to each other through ohmic contact.

[0113] Next, as shown in FIG. 7F, the second insulating layer 202B is patterned to remove the second insulating layer 202B from the portion where the gate electrode 303 is to be provided (second insulating layer patterning step).

[0114] Specifically, similar to the first embodiment, a resist is applied and then patterned into a predetermined shape by lithography to form a continuous mask (resist mask) in the region where the source electrode 301 and the drain electrode 302 are formed and in a region spaced from the region where the gate electrode 303 is to be formed (the region where the gate electrode 303 is to be formed). Then, by dry etching, the second insulating layer 202B is removed except for the portion in contact with the contact layer 212, thereby exposing the first insulating layer 201 and forming the first insulating layer exposed portion 201s. At this time, the second insulating layer 202B located below the patterned resist (resist mask) is left unremoved. That is, the portion of the second insulating layer 202B in contact with the contact layer 212 remains. The resist and polymer are then removed. This allows the second insulating layer 202B to have an opening 202a in the region where the gate electrode 303 is to be formed. At this time, the electron concentration of the two-dimensional electron gas located below the portion where the second insulating layer 202B is not formed becomes low, and therefore a first two-dimensional electron gas layer 105A having a relatively low electron concentration of the two-dimensional electron gas and a second two-dimensional electron gas layer 105B having a relatively high electron concentration of the two-dimensional electron gas are generated in the two-dimensional electron gas layer 105.

[0115] 7G, the first insulating layer 201 is removed from the exposed portion 201s of the first insulating layer 201 that is spaced apart from the second insulating layer 202B to form the gate electrode 303 (gate electrode formation step). Specifically, the gate electrode 303 can be formed in the same manner as in the first embodiment.

[0116] In this way, through the series of steps shown in FIGS. 7A to 7G, the semiconductor device 2 having the structure shown in FIG. 4 is completed.

[0117] 7D, the formation temperature of second insulating layer 202 is preferably higher than the formation temperature of first insulating layer 201. In other words, the formation temperature of first insulating layer 201 is preferably lower than the formation temperature of second insulating layer 202B. This makes it possible to increase the tensile stress of second insulating layer 202B relative to first insulating layer 201, thereby further increasing the electron concentration of second two-dimensional electron gas layer 105B.

[0118] (Other Modifications) Although the semiconductor device according to the present disclosure has been described above based on the first and second embodiments, the present disclosure is not limited to the first and second embodiments.

[0119] For example, in the first and second embodiments, the electron transit layer 103 and the electron supply layer 104 are made of a group III nitride semiconductor, but this is not limiting. Specifically, the electron transit layer 103 and the electron supply layer 104 may be made of other semiconductor materials, such as a group III arsenide semiconductor.

[0120] In the first embodiment, the second insulating layer 202 is made of SiN, but the present invention is not limited to this. For example, in the first embodiment, the second insulating layer 202 may be made of SiON or SiO ２ The second insulating layer 202 may be a layer containing oxygen, such as SiON. This allows the thermal expansion coefficient of the second insulating layer 202 to be larger than when the second insulating layer 202 is made of SiN. This further increases the tensile stress of the second insulating layer 202, thereby making the electron concentration of the second two-dimensional electron gas layer 105B higher than that of the first two-dimensional electron gas layer 105A. This further reduces the decrease in electron concentration in the portion of the electron supply layer 104 adjacent to the side surface of the through-hole recess 211, thereby further suppressing a decrease in the maximum drain current. Furthermore, in the first embodiment, by using SiON for the second insulating layer 202, the second insulating layer 202 can be made into a layer having a positive fixed charge, as in the second embodiment. This further increases the electron concentration of the second two-dimensional electron gas layer 105B located below the second insulating layer 202, thereby further suppressing a decrease in the maximum drain current.

[0121] Furthermore, in the second embodiment, similarly to the first embodiment, the linear thermal expansion coefficient of the second insulating layer 202B may be set to be larger than the linear thermal expansion coefficient of the electron supply layer 104, or the tensile stress of the second insulating layer 202B may be set to be larger than the tensile stress of the first insulating layer 201. This makes it possible to further increase the electron concentration of the second two-dimensional electron gas layer 105B, thereby further suppressing a decrease in the maximum drain current.

[0122] In addition, the present disclosure also includes forms obtained by applying various modifications to the above-described embodiments that would occur to those skilled in the art, and forms realized by arbitrarily combining the components and functions of the embodiments within the scope of the present disclosure. Furthermore, the present disclosure also includes any combination of two or more claims from among the multiple claims set forth in the claims at the time of filing, within the scope of technical compatibility. For example, when a dependent claim set forth in the claims at the time of filing is made into a multiple claim or multiple multiple claims that cite all of the superordinate claims within the scope of technical compatibility, the present disclosure also includes all combinations of claims included in that multiple claim or multiple multiple multiple claims.

[0123] The technology disclosed herein can be used in semiconductor devices such as switching transistors used in communication equipment and inverters that require high-speed operation, and power supply circuits, etc. Among these, the technology disclosed herein is particularly useful for high-frequency power devices that have a significant impact on heat generation due to ohmic contact resistance.

[0124] 1, 1A, 2 Semiconductor device 100 Semiconductor laminated structure 101 Substrate 102 Buffer layer 103 Electron transit layer 104 Electron supply layer 105 Two-dimensional electron gas layer 105A First two-dimensional electron gas layer 105B Second two-dimensional electron gas layer 201, 201A First insulating layer 201a Opening 201s First insulating layer exposed portion 202, 202A, 202B, 203 Second insulating layer 202a Opening 203A Recess portion 211 Penetrating recess portion 212 Contact layer 212A Source side contact layer 212B Drain side contact layer 301 Source electrode 302 Drain electrode 303 Gate electrode

Claims

1. An electron transport layer, An electron supply layer provided on the electron transport layer and having a larger band gap than the electron transport layer, A gate electrode provided on the electron supply layer, A source-side contact layer and a drain-side contact layer embedded in a recess portion penetrating the electron supply layer at a position sandwiching the gate electrode, A first insulating layer provided on a portion of the electron supply layer where the gate electrode is not provided, A second insulating layer provided on the first insulating layer in contact with the source-side contact layer and / or the drain-side contact layer and not in contact with the gate electrode, The linear thermal expansion coefficient of the second insulating layer is larger than that of the electron supply layer, Both the first insulating layer and the second insulating layer have a halogen concentration of 1×10 18 atoms / cm 3 or less, A semiconductor device

2. There is no uneven distribution of oxygen between the first insulating layer and the electron supply layer, The semiconductor device according to claim 1.

3. The first insulating layer does not contain oxygen, The semiconductor device according to claim 1 or 2.

4. The second insulating layer contains oxygen, The semiconductor device according to claim 1 or 2.

5. In a cross-sectional view, the width of the second insulating layer is 1 μm or less, The semiconductor device according to claim 1 or 2.

6. The tensile stress of the second insulating layer is larger than that of the first insulating layer, The semiconductor device according to claim 1 or 2.

7. The first insulating layer and the second insulating layer are made of the same material, The density of the first insulating layer is smaller than that of the second insulating layer, The semiconductor device according to claim 1 or 2.

8. The electron transport layer and the electron supply layer are made of a group III nitride semiconductor, The semiconductor device according to claim 1 or 2.

9. An electron transport layer, An electron supply layer provided on the electron transport layer and having a larger band gap than the electron transport layer, A gate electrode provided on the electron supply layer, A contact layer embedded in a recess portion penetrating the electron supply layer at a position sandwiching the gate electrode, A source electrode or a drain electrode provided on the contact layer, A first insulating layer provided on a portion of the electron supply layer where the gate electrode is not provided, A second insulating layer provided on the first insulating layer in contact with the contact layer and not in contact with the gate electrode, The second insulating layer has an oxynitride layer or a composite layer of an oxide and a nitride. The semiconductor device, wherein the halogen concentration of the first insulating layer is 1×10 18 atoms / cm 3 or less. Semiconductor device.

10. The semiconductor device according to claim 9, wherein the second insulating layer contains an n-type semiconductor layer. Semiconductor device according to claim 9.

11. The semiconductor device according to claim 9 or 10, wherein the electron transport layer and the electron supply layer are made of a group III nitride semiconductor. Semiconductor device according to claim 9 or 10.

12. An electron transport layer, an electron supply layer provided on the electron transport layer and having a larger bandgap than the electron transport layer, a gate electrode provided on the electron supply layer, a source-side contact layer and a drain-side contact layer embedded in a recess portion penetrating the electron supply layer at a position sandwiching the gate electrode, a first insulating layer provided on a portion of the electron supply layer where the gate electrode is not provided, a second insulating layer provided on the first insulating layer in contact with the source-side contact layer and / or the drain-side contact layer and not in contact with the gate electrode, The linear thermal expansion coefficient of the second insulating layer is larger than that of the electron supply layer, In a cross-sectional view, the width of the second insulating layer is 1 μm or less. Semiconductor device.

13. There is no uneven distribution of oxygen between the first insulating layer and the electron supply layer. Semiconductor device according to claim 12.

14. The first insulating layer does not contain oxygen. Semiconductor device according to claim 12 or 13.

15. The second insulating layer contains oxygen. Semiconductor device according to claim 12 or 13.

16. The halogen concentration of both the first insulating layer and the second insulating layer is 1×10 18 atoms / cm 3 or less. Semiconductor device according to claim 12 or 13.

17. The tensile stress of the second insulating layer is larger than that of the first insulating layer. Semiconductor device according to claim 12 or 13.

18. The first insulating layer and the second insulating layer are made of the same material, and the density of the first insulating layer is smaller than that of the second insulating layer. Semiconductor device according to claim 12 or 13.

19. The electron transport layer and the electron supply layer are made of a group III nitride semiconductor. Semiconductor device according to claim 12 or 13.