Semiconductor light receiving element and method for manufacturing the same

Abstract

The semiconductor light receiving element (100) of the present disclosure comprises a semiconductor substrate (2), a digital alloy type multiplication layer (4) formed on the semiconductor substrate (2) and having a digital alloy structure in which a first semiconductor layer made of a superlattice layer composed of Group IV atoms and a second semiconductor layer having a larger band gap energy than the first semiconductor layer are alternately stacked, an electric field relaxation layer (5) formed on the digital alloy type multiplication layer (4) for relaxing the electric field, and a light absorption layer (6) formed on the electric field relaxation layer (5) for absorbing incident light.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor light receiving element and a method for manufacturing the semiconductor light receiving element. [Background technology]

[0002] In recent years, the data center market has made remarkable progress due to the spread of businesses that handle large volumes of data and video content. Accordingly, the demand for optical communication devices required for large-volume data communication is increasing. Avalanche photodiodes (APDs), which have excellent performance, are indispensable as optical communication devices on the receiving side of communication data, not only for short-distance communication but also for long-distance communication between data centers.

[0003] The APD used on the receiving side generates photocarriers consisting of electron-hole pairs from the optical signal received during data communication, and is capable of amplifying the photocarriers themselves. Therefore, by using an APD, it is possible to restore an accurate optical signal at the receiving side even in long-distance transmissions where the signal strength deteriorates. In addition, the use of an APD eliminates the need for an external carrier amplifier on the receiving side, which was necessary when using a normal photodetector, making it possible to miniaturize communication equipment. For this reason, APDs are used as semiconductor photodetectors even for short-distance communications.

[0004] The main element structure of APDs used in current optical communications is the SACM type APD structure (Separate Absorption, Charge and Multiplication Avalanche Photodiode), in which a layer that receives signal light and generates photocarriers is separated from a layer that multiplies the generated photocarriers. As the SACM type APD structure, in particular, one formed on an InP substrate and composed of an InGaAs absorption layer that receives signal light and generates photocarriers, an AlInAs multiplication layer that multiplies the generated carriers, and an electric field relaxation layer that controls the electric field intensity of the multiplication layer so that the photocarriers can be avalanche multiplied is used. The photocarriers generated in the InGaAs absorption layer are reverse-biased to conduct electrons into the AlInAs multiplication layer, and the photocarriers are avalanche-amplified in the multiplication layer, making it possible to amplify the optical signal (Patent Document 1).

[0005] As communication speeds increase, there is a demand for APDs that can operate with even lower noise than current APDs. In order to reduce the noise of APDs, it is necessary to reduce the Hall noise generated in the multiplication layer. For this purpose, APDs that suppress the Hall noise during multiplication by using a germanium (Ge) absorption layer and a Si multiplication layer formed on a silicon (Si) substrate have recently begun to be used (Non-Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 4166560 [Patent Document 2] Patent Publication No. 61-276272 [Patent Document 3] Patent No. 2730472 [Non-patent literature]

[0007] [Non-Patent Document 1] M. Huang,et.al.,”Germanium on Silicon Avalanche Photodiode.”IEEE Journal of Selected Topics In Quantum Electronics,Vol.24,No.2,3800911,2018. [Non-Patent Document 2] M. Daoudi, et.al., “Si-delta doping and spacer thickness effects on the electronic properties in Si-delta-doped AlGaAs / GaAs HEMT structures,” Superlattices and Microstructures, Vol. 51, pp. 497-505, 2012. [Non-Patent Document 3] J. Zheng,et.al.,”Digital Alloy InAlAs Avalanche Photodopdes,”IEEE Journal of Lightwave Technology,Vol.36,No.17,pp.3580-3585,2018. [Non-Patent Document 4] DCHoughton, et.al., “Comparison of chemical beam epitaxy and metalorganic chemical vapor deposition for highly strained multiple quantum well InGaAsP / InP 1.5μm lasers.”J.Crystal Growth,Vol.136,pp.56-63,1994. Summary of the Invention [Problem to be solved by the invention]

[0008] However, even now, it is extremely difficult to obtain a high-quality Ge absorption layer thicker than 1 μm due to the mismatch of the lattice constant when growing the Ge absorption layer on a Si substrate. In other words, SiGe-APDs using Si substrates have problems with reliability and manufacturing technology. From the viewpoint of high reliability, an AlInAs multiplication layer on an InP substrate, which is a III-V mixed crystal semiconductor material, is excellent as a multiplication layer for electron multiplication type APDs, but its noise performance is inferior to that of APDs with a Si multiplication layer.

[0009] For this reason, in order to form a Si multiplication layer on an InP substrate that is expected to reduce noise, for example, in the APD described in Patent Document 2, an attempt is made to use an InP substrate, form a light absorption layer using a III-V group mixed crystal semiconductor having a lattice constant that is an integer ratio to the lattice constant of Si, and form a Si multiplication layer on top of the InP substrate. However, in such a structure, not only the Si multiplication layer but also the light absorption layer of the III-V group mixed crystal semiconductor itself is lattice mismatched, making it difficult to obtain a high level of crystal quality that functions as a multiplication layer, and there are concerns about the reliability of the APD.

[0010] Furthermore, the semiconductor photodetector described in Patent Document 3 does not use an InP substrate, but instead forms an amorphous InGaAs layer as a light absorption layer after growing a high-quality Si multiplication layer on a Si substrate. However, in such an element structure and manufacturing method, the amorphous InGaAs layer has a high density of crystal defects, so dark current caused by the crystal defects is large, and there are concerns about the reliability of the APD.

[0011] In addition to the above, devices (particularly RF devices) that exhibit excellent characteristics have been realized by depositing Si itself two-dimensionally using a technology called delta doping, which is a two-dimensional high-concentration doping of Si, as in the invention described in Non-Patent Document 2. However, since APDs require a film thickness on the order of several tens of nm as a region in which avalanche amplification occurs, there was a problem that δ doping could not achieve a thicker film due to deterioration of the surface condition, etc.

[0012] Recently, a paper was published stating that a technology called Digital Alloy, which makes it possible to control crystal growth at the atomic layer level, can be used to obtain semiconductors with material properties different from those of conventional materials, for alloy semiconductor materials made of III-V alloy semiconductors (Non-Patent Document 3). By applying the Digital Alloy technology, it is possible to realize structures with material properties that have never been seen before by controlling the layer thickness of two materials with different lattice constants at the atomic layer level.

[0013] However, simply selecting and laminating crystalline materials does not provide good crystalline quality due to crystal defects that occur as a result of structural stress caused by lattice mismatch, etc. In order to obtain a high-quality APD that is capable of high-speed operation, it is necessary to form a silicon (Si) layer with a thickness that allows avalanche multiplication on an alloy semiconductor substrate, and this is possible by appropriately selecting materials to be laminated at the atomic layer level.

[0014] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor light-receiving element that is low-noise and highly reliable, and a method for manufacturing the same. [Means for solving the problem]

[0015] The semiconductor light receiving element according to the present disclosure comprises: A semiconductor substrate; A layer having a thickness of N times (1≦N≦20) the thickness of a silicon monolayer is formed on the semiconductor substrate. Si layer a digital alloy type multiplication layer having a digital alloy structure in which a first semiconductor layer made of the above-mentioned and a second semiconductor layer made of a semiconductor having a lattice constant larger than that of Si and having a layer thickness M times (1≦M≦20) a monoatomic layer having a band gap energy larger than that of the first semiconductor layer are alternately laminated; an electric field relaxation layer formed on the digital alloy type multiplication layer and mitigating an electric field; a light absorbing layer formed on the electric field relaxation layer and configured to absorb incident light; Equipped with.

[0016] A method for manufacturing a semiconductor light receiving element according to the present disclosure includes: epitaxially growing, on an n-type InP substrate, an n-type AlInAs buffer layer, a digital alloy multiplication layer having a digital alloy structure in which a Si layer or a layer containing Si having a layer thickness N times (1≦N≦20) a monolayer, and an AlAs layer having a layer thickness M times (1≦M≦20) a monolayer are alternately stacked multiple times, a p-type AlInAs electric field relaxation layer, an n-type InGaAs light absorption layer, an i-type AlInAs window layer, an n-type InP window layer, and a p-type InGaAs contact layer, in that order by MOVPE; and forming a Zn selective diffusion region in a portion of the n-type InP window layer and the i-type AlInAs window layer. Effect of the Invention

[0017] According to the semiconductor light receiving element and the manufacturing method of the semiconductor light receiving element disclosed herein, it is possible to form a high-quality digital alloy type multiplication layer containing group IV atoms on a semiconductor substrate, thereby achieving the effects of obtaining a semiconductor light receiving element with low noise and excellent reliability, and of easily manufacturing such a semiconductor light receiving element. [Brief description of the drawings]

[0018] [Figure 1] 1 is a cross-sectional view illustrating a device structure of a semiconductor light receiving device according to a first embodiment. [Diagram 2] FIG. 13 is a diagram showing the relationship between the excess noise factor and the multiplication factor. [Diagram 3] 11 is a cross-sectional view illustrating a device structure of a semiconductor light receiving device according to a second embodiment. [Figure 4] FIG. 11 is a diagram showing calculation results of effective stress τ when the composition ratio of Si and AlAs is changed in a digital alloy type stacked structure of Si and AlAs in a semiconductor light receiving element according to the second embodiment. [Diagram 5] 11 is a cross-sectional view illustrating a device structure of a semiconductor light receiving device according to a third embodiment. [Figure 6] FIG. 11 is a cross-sectional view illustrating a device structure of a semiconductor light receiving device according to a fourth embodiment. [Figure 7] FIG. 13 is a diagram showing the relationship between the Si sheet carrier concentration and the Si material supply amount. [Figure 8] 13 is a cross-sectional view illustrating a device structure of a semiconductor light receiving device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Embodiment 1 <Element structure of semiconductor light receiving element according to the first embodiment> 1 is a cross-sectional view showing the device structure of a semiconductor light receiving element 100 according to the embodiment 1. As an example of the semiconductor light receiving element 100 according to the embodiment 1, a SACM type APD is given.

[0020] The semiconductor light receiving element 100 according to the first embodiment is made up of an n-type InP substrate 2 and a carrier concentration of 1 to 5×10 18 cm -3 an n-type AlInAs buffer layer 3 having a thickness of 0.1 to 0.5 μm; an i-type Si-AlAs digital alloy multiplication layer 4 having a thickness of 0.05 to 0.2 μm and a digital alloy structure in which an i-type Si layer (e.g., a thickness of 2 ML) and an i-type AlAs layer (e.g., a thickness of 2 ML) are alternately laminated multiple times; and a carrier concentration of 0.5 to 1×10 18 cm -3 and a p-type AlInAs electric field relaxation layer 5 having a thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm -3 The n-type InGaAs light absorption layer 6 has a thickness of 1.0 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm -3 and an n-type InP window layer 8 having a thickness of 0.5 to 1.0 μm and a carrier concentration of 1 to 5×10 18 cm -3 and a p-type InGaAs contact layer 9 having a circular ring shape and a layer thickness of 0.1 to 0.5 μm.

[0021] The semiconductor photodetector 100 according to the first embodiment further includes a Zn selective diffusion region 10 (p-type conductive region) provided in a part of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protective film 11 provided on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 provided on the back surface side of the n-type InP substrate 2, and a p-type electrode 12 provided on the surface of the p-type InGaAs contact layer 9 having a circular ring shape.

[0022] The semiconductor light receiving element 100 according to the first embodiment is characterized in that it is configured as a multiplication layer using an i-type Si-AlAs digital alloy type multiplication layer 4 having a digital alloy structure in which an i-type Si layer and an i-type AlAs layer are alternately laminated multiple times. In the explanation of each embodiment, the composition ratio of AlInAs and InGaAs constituting each layer except the multiplication layer is not specified, but it is desirable that both have a composition ratio that lattice matches with the n-type InP substrate 2.

[0023] The above-mentioned i-type Si layer refers to a silicon superlattice layer having a layer thickness N times (1≦N≦20) that of a silicon monoatomic layer. The i-type Si layer is also called the first semiconductor layer 30a, the i-type AlAs layer is also called the second semiconductor layer 30b, and the i-type Si-AlAs digital alloy type multiplication layer 4 is also simply called the digital alloy type multiplication layer.

[0024] In the above description, the i-type Si-AlAs digital alloy multiplication layer 4 is an example of a multiplication layer in which the layer thickness is two monolayers (ML), that is, an i-type Si layer having a layer thickness of 2ML and an i-type AlAs layer having a layer thickness of 2ML are alternately stacked multiple times. However, the layer thickness of the i-type Si layer may be within a range of N times the monolayer (1≦N≦20), and the layer thickness of the i-type AlAs layer may be within a range of M times the monolayer (1≦M≦20). It is more preferable that the layer thickness of the i-type Si layer is within a range of N times the monolayer (1≦N≦6), and the layer thickness of the i-type AlAs layer is within a range of M times the monolayer (1≦M≦6). For the i-type Si-AlAs digital alloy multiplication layer 4, when the i-type Si layer and the i-type AlAs layer are alternately stacked multiple times, the number of stacking times is preferably within a range of 5 times or more and 300 times or less.

[0025] <Method of Manufacturing Semiconductor Light-Receiving Element According to First Embodiment> The semiconductor light receiving element 100 according to the first embodiment can be manufactured by forming each semiconductor layer on an InP substrate using a crystal growth method such as metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE). A method for manufacturing a SACM type APD, which is an example of the semiconductor light receiving element 100 according to the first embodiment, will be described below.

[0026] On the surface of an n-type InP substrate 2, an n-type AlInAs buffer layer 3, an i-type Si-AlAs digital alloy type multiplication layer 4 having a digital alloy structure in which i-type Si layers (2 ML thick) and i-type AlAs layers (2 ML thick) are alternately stacked multiple times, a p-type AlInAs electric field relaxation layer 5, an n-type InGaAs light absorption layer 6, an i-type AlInAs window layer 7, an n-type InP window layer 8, and a p-type InGaAs contact layer 9 are sequentially crystal-grown by MOVPE.

[0027] When the MOVPE method is used as the epitaxial crystal growth method, the crystal growth temperature is preferably about 550°C, but may be within the temperature range of 500°C to 600°C.

[0028] In the wafer process after epitaxial crystal growth, reactive ion etching, CVD (Chemical Vapor Deposition), deposition, and other processes are used to process and form films in the element area, and electrodes are formed to form the element structure required for functioning as a SACM-type APD. The wafer process is described in detail below.

[0029] After epitaxial crystal growth, a SiOx film is formed on the surface of the wafer by a method such as CVD. The SiOx film is an insulating film and functions as a diffusion mask.

[0030] Using photolithography and etching techniques, a circular pattern mask with a diameter of 20 μm is used for patterning to provide a circular opening in the SiOx film. Using the SiOx film as a diffusion mask, zinc (Zn) is diffused from the opening into the semiconductor layer to form a Zn selective diffusion region 10 in a part of the n-type InP window layer 8 and the i-type AlInAs window layer 7. The tip portion of the Zn selective diffusion region 10 in the semiconductor layer is located in the i-type AlInAs window layer 7. The Zn selective diffusion region 10 functions as a p-type conductive region. After the Zn selective diffusion region 10 is formed, the SiOx film is removed by wet etching or dry etching.

[0031] Next, photolithography and etching techniques are used to process the p-type InGaAs contact layer 9 by reactive ion etching or the like so that the p-type InGaAs contact layer 9 remains in a ring shape with a width of about 3.0 to 5.0 μm on the Zn selective diffusion region 10.

[0032] After processing the p-type InGaAs contact layer 9, a SiNx surface protective film 11 is formed on the wafer surface by a CVD method or the like. Then, photolithography and etching techniques are used to remove only the SiNx surface protective film 11 on the surface of the p-type InGaAs contact layer 9. The SiNx surface protective film 11 also functions as an anti-reflection film.

[0033] On the surface of the p-type InGaAs contact layer 9, a metal material such as Ti / Au is deposited by evaporation or the like to form a p-type electrode 12.

[0034] Finally, the back surface of the n-type InP substrate 2 is ground, and then a film of a metal material such as AuGeNi is formed by vapor deposition or the like to form the n-type electrode 1. The above is the method for manufacturing the SACM type APD, which is an example of the semiconductor light receiving element 100 according to the first embodiment.

[0035] <Operation of the semiconductor light receiving element according to the first embodiment> The operation of the SACM APD, which is an example of the semiconductor light receiving element 100 according to the first embodiment manufactured by the above-mentioned manufacturing method, will be described below.

[0036] First, a reverse bias voltage is applied from the outside so that the n-type electrode 1 provided on the back side of the n-type InP substrate 2 of the SACM APD, which is an example of the semiconductor light receiving element 100, is positive and the p-type electrode 12 provided on the front side is negative. The reverse bias voltage is set to a voltage value that sufficiently generates avalanche amplification.

[0037] When light with a wavelength of 1.3 μm or 1.55 μm, which is a wavelength band used in optical communications, is incident on the Zn selective diffusion region 10, which is a p-type conductive region, from the p-type electrode 12 side of the SACM-type APD to which a reverse bias voltage is applied, the light is absorbed in the n-type InGaAs light absorption layer 6 and photocarriers (electron-hole pairs) are generated; with a reverse bias voltage applied, the electrons move to the n-type electrode 1 side and the holes move to the p-type electrode 12 side.

[0038] In a SACM APD to which a reverse bias voltage is applied, the electric field strength is controlled by the p-type AlInAs electric field relaxation layer 5 so that avalanche amplification occurs when electrons are conducted into the i-type Si-AlAs digital alloy multiplication layer 4. In the i-type Si-AlAs digital alloy multiplication layer 4, electrons are ionized to generate new electron-hole pairs, and the newly generated electrons and holes further cause a chain reaction of ionization, resulting in avalanche amplification of the electrons and holes, that is, avalanche amplification. In other words, electrons, which are photocarriers, are multiplied by the avalanche amplification effect in the i-type Si-AlAs digital alloy multiplication layer 4, making it possible to amplify the received optical signal.

[0039] <Function of the semiconductor light receiving element according to the first embodiment> The characteristics of a semiconductor photodetector can be expressed by the S / N ratio, which is the ratio of signal to noise. APDs with excellent receiving sensitivity have a large S / N ratio. The signal strength of the photocurrent generated by light absorption is expressed as i sThe shot noise, which is a noise component generated inside the semiconductor photodetector such as dark current, is i Ns , the thermal noise generated by the thermal noise amplitude due to the peripheral circuits is i Nt In this case, the S / N ratio of the semiconductor light receiving element is expressed by the following formula (1).

[0040]

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[0041] Next, the elementary charge of electrons is q, the avalanche multiplication factor is M, and the average current flowing through the avalanche region of the APD is I p , the dark current multiplied in the avalanche region is I dM , excess noise figure x, bandwidth B, Boltzmann constant k, temperature T, external circuit resistance R L Then, the above S / N ratio is calculated using the following equation (2).

[0042]

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[0043] In equation (2), the main factor that deteriorates the S / N ratio is the multiplied dark current I dM and the excess noise factor x contained in the power of the multiplication factor M. Dark current I dM is a dark current that occurs when photocarriers are multiplied, so it depends heavily on the crystal quality of the APD. In particular, in SiGe-APDs, dark current increases due to crystal defects that occur in the Ge absorption layer due to the difference in lattice constant with Si, which is a factor that deteriorates the S / N ratio of the APD.

[0044] Regarding the excess noise factor x, which affects another characteristic of the APD, the relationship expressed by the following equation (3) holds between the excess noise factor F and the multiplication factor M.

[0045]

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[0046]

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[0047] From equation (4), we can see that the smaller the impact ionization rate ratio k, the smaller the excess noise factor F and the smaller the excess noise exponent x, which results in a larger S / N ratio and therefore superior noise characteristics. Figure 2 is a diagram showing the relationship between the excess noise factor F and the multiplication factor M. In general, the impact ionization rate ratio k is a value specific to the material, and for Si, k=0.1 is a smaller value than for AlInAs, k=0.2, so as shown in Figure 2, Si is more advantageous when noise characteristics are taken into consideration.

[0048] However, since SiGe-APDs use Ge for the absorption layer, as mentioned above, shot noise (I dM As a result, variations in crystal quality or characteristics during manufacturing can often result in failure to obtain the desired S / N ratio.

[0049] In contrast, in electron multiplying APDs using InP substrates, InGaAs is used for the absorption layer and AlInAs for the multiplication layer. Both crystals are materials that are lattice-matched to the InP substrate, making it difficult for crystal defects to occur, it is possible to manufacture APDs that are low noise and have excellent reliability.

[0050] In order to further improve the S / N ratio of the APD, the digital alloy technology disclosed in Non-Patent Document 2, that is, a technology for stacking different materials at atomic layer level thicknesses, is used to stack a III-V group alloy semiconductor, such as AlAs or InAs, in an atomic layer level thickness while containing Si in the multiplication layer, which makes it possible to grow a multiplication layer with a smaller impact ionization rate ratio k than conventional materials.

[0051] Since Si has a smaller lattice constant than InP or GaAs substrates, which are semiconductor materials used in the optical communication band, when growing a stacked structure such as a multiplication layer containing Si, the lattice constant of the III-V mixed crystal semiconductor material must be larger than that of Si. In addition, since a high-quality absorption layer can be realized simultaneously with the formation of the multiplication layer, shot noise can be suppressed, making it possible to stably manufacture APDs with higher sensitivity than conventional SACM-type APDs.

[0052] In the first embodiment, a case where a material containing Si and an AlAs layer, which is a semiconductor material different from Si, are laminated in the multiplication layer, has been described as an example. If a mixed crystal semiconductor material consisting of a group III atomic material and a group V atomic material, such as InP, GaP, AlP, InAs, GaAs, InSb, GaSb, or AlSb, is used as the material for the multiplication layer, a similar effect can be obtained. In addition, the crystal material is not limited to a binary compound, and a similar effect can be obtained by laminating a ternary or quaternary mixed crystal semiconductor material, for example, a mixed crystal semiconductor such as InGaAs, AlInAs, GaAsSb, AlGaInAs, or AlGaAsSb, at the atomic level.

[0053] As an example of the thickness of the layers constituting the digital alloy structure, a structure in which layers are stacked in units of 2ML is given. However, the layer thickness is a critical thickness that allows crystal growth without generating crystal defects on the base substrate, for example, a layer thickness up to 5 nm, and any combination of layer thicknesses may be used as long as the required multiplication layer constituent materials can be crystal grown. In addition, the Si-AlAs digital alloy type multiplication layer may not be i-type, i.e., undoped, as shown in the above example, but may be an n-type Si-AlAs digital alloy type multiplication layer or a p-type Si-AlAs digital alloy type multiplication layer by doping the entire Si-AlAs digital alloy type multiplication layer with n-type or p-type impurities.

[0054] In the above example, the case where the Zn selective diffusion region 10, which is a p-type conductive region, is formed by Zn diffusion has been described. However, any atom that imparts p-type conductivity may be used other than Zn, for example, Cd or Be. The Zn diffusion method may be a solid-phase diffusion method using ZnO, or a Zn vapor-phase diffusion method using a crystal growth furnace. Alternatively, instead of the Zn selective diffusion region 10, a p-type contact layer may be grown by crystal growth.

[0055] In the above example, a front-illuminated structure has been described in which light to be detected is incident on the Zn selective diffusion region 10, which is a p-type conductive region, from the p-electrode 12 side. Conversely to the front-illuminated structure, a back-illuminated structure in which the n-electrode 1 on the back side of the n-type InP substrate 2 is opened using a circular pattern and light is incident from the n-type InP substrate 2 side can also have the same effect. Furthermore, an edge-illuminated structure in which light is incident from the edge side of the n-type light absorption layer can also have the same effect.

[0056] <Advantages of the First Embodiment> As described above, according to the semiconductor photodetector and the manufacturing method of the semiconductor photodetector of the first embodiment, the multiplication layer is made of a Si-AlAs digital alloy type multiplication layer having a digital alloy structure in which Si layers made of Si superlattice layers and AlAs layers are alternately laminated multiple times, thereby achieving the effects of obtaining a semiconductor photodetector with low noise and excellent reliability, and of easily manufacturing such a semiconductor photodetector.

[0057] Embodiment 2 <Element structure of semiconductor light receiving element according to the second embodiment> 3 is a cross-sectional view showing the device structure of a semiconductor light receiving element 110 according to the second embodiment. As an example of the semiconductor light receiving element 110 according to the second embodiment, a SACM type APD is given.

[0058] The semiconductor light receiving element 110 according to the second embodiment is a semiconductor device having a carrier concentration of 1 to 5×10 18 cm -3 an n-type AlInAs buffer layer 3 having a thickness of 0.1 to 0.5 μm; an i-type Si-AlAs digital alloy multiplication layer 4a having a thickness of 0.05 to 0.2 μm and consisting of a digital alloy structure in which an i-type Si layer (e.g., a thickness of 2 ML) and an i-type AlAs layer (e.g., a thickness of 4 ML) are alternately laminated multiple times; and a carrier concentration of 0.5 to 1×10 18 cm -3 and a p-type AlInAs electric field relaxation layer 5 having a thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm -3 The n-type InGaAs light absorption layer 6 has a thickness of 1.0 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm -3 and an n-type InP window layer 8 having a thickness of 0.5 to 1.0 μm and a carrier concentration of 1 to 5×10 18 cm -3 and a p-type InGaAs contact layer 9 having a circular ring shape and a layer thickness of 0.1 to 0.5 μm.

[0059] The semiconductor light-receiving element 110 according to the second embodiment further includes a Zn selective diffusion region 10 (p-type conductive region) provided in a part of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protective film 11 provided on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 provided on the back surface side of the n-type InP substrate 2, and a p-type electrode 12 provided on the surface of the p-type InGaAs contact layer 9 having a circular ring shape.

[0060] The semiconductor light-receiving element 110 according to Embodiment 2 is composed of a digital alloy structure in which a multiplication layer is formed by alternately stacking a plurality of times an i-type Si layer having a layer thickness of N times (1 ≤ N ≤ 20) of a single atomic layer and an i-type AlAs layer having a layer thickness of M times (1 ≤ M ≤ 20) of a single atomic layer, and is characterized in that it is composed of an i-type Si-AlAs digital alloy type multiplication layer 4a having a relationship (N < M) in which the number of single atomic layers M constituting the i-type AlAs layer is larger than the number of single atomic layers N constituting the i-type Si layer.

[0061] The above-mentioned i-type Si layer refers to a silicon superlattice layer having a layer thickness of N times (1 ≤ N ≤ 20) of a single silicon atomic layer. The i-type Si layer is also referred to as the first semiconductor layer 31a, the i-type AlAs layer is also referred to as the second semiconductor layer 31b, and the i-type Si-AlAs digital alloy type multiplication layer 4a is also simply referred to as a digital alloy type multiplication layer.

[0062] In the above description, as the i-type Si-AlAs digital alloy type multiplication layer 4a, a multiplication layer in which a plurality of i-type Si layers having a layer thickness of two single atomic layers (ML), that is, an i-type Si layer having a layer thickness of 2ML, and an i-type AlAs layer having a layer thickness of 4ML are alternately stacked a plurality of times is given as an example. The relationship (N < M) in which the number of single atomic layers M constituting the i-type AlAs layer is larger than the number of single atomic layers N constituting the i-type Si layer is satisfied, and the layer thickness of the i-type Si layer may be within the range of N times (1 ≤ N ≤ 20) of a single atomic layer, and the layer thickness of the i-type AlAs layer may be within the range of M times (1 ≤ M ≤ 20) of a single atomic layer. If the layer thickness of the i-type Si layer is within the range of N times (1 ≤ N ≤ 6) of a single atomic layer and the layer thickness of the i-type AlAs layer is within the range of M times (1 ≤ M ≤ 6) of a single atomic layer, it is more preferable. Regarding the i-type Si-AlAs digital alloy type multiplication layer 4, the number of stacking times when the i-type Si layer and the i-type AlAs layer are alternately stacked a plurality of times is preferably in the range of 5 times or more and 300 times or less.

[0063] <Method for manufacturing a semiconductor light-receiving element according to Embodiment 2> The method for manufacturing the semiconductor light-receiving element 110 according to Embodiment 2 is substantially the same as the method for manufacturing the semiconductor light-receiving element 100 according to Embodiment 1, and thus a detailed description of the manufacturing method is omitted.

[0064] <Function of the semiconductor light receiving element according to the second embodiment> In APDs, generally, a layer structure with a total thickness of about 2 μm is grown on the upper side of the multiplication layer, from the electric field relaxation layer to the p-type contact layer. If crystal defects occur inside the crystals that make up the layer structure, the dark current increases and the shot noise increases, deteriorating the S / N ratio of the APD and raising concerns about its reliability.

[0065] The multiplication layer formed by the digital alloy technology disclosed in this application is formed by repeatedly stacking Si and other semiconductor materials, which have a lattice constant that does not match that of the semiconductor substrate, at the atomic layer level, alternately, so it is necessary to reduce stress in the entire crystal growth layer by repeatedly stacking layers of compressive strain and layers of tensile strain.

[0066] In a structure in which two different materials are alternately and repeatedly laminated, the effective stress τ according to the mechanical equilibrium model, which serves as a guideline for when dislocations occur, can be calculated using the following formula (5) based on the description in Non-Patent Document 4.

[0067]

number

[0068] The meanings of the symbols in formula (5) are as follows: Ψ: Angle between the interface and the slip surface λ: Angle between the dislocation line and the Burgers spectrum ν: Poisson's ratio μ x : Shear coefficient of compressively strained layer μ y : Shear coefficient of tensile strain layer μ xy : Average shear modulus of repeated laminated parts b : Burger spectrum θ: Angle between the dislocation line and Burgers spectrum β: Core parameter x: Strain amount of the compressive strain layer h: thickness of the compressively strained layer y: Strain in the tensile strain layer H: Thickness of the tensile strain layer Z: Thickness of the strain relaxation layer N: Number of compressively strained layers L: Calculated value of Nh+(N-1)H

[0069] If the calculated effective stress τ is normalized and the layer structure is constructed so that the effective stress τ is 0 or less, a high-quality APD without dislocations can be grown. Figure 4 shows the calculation results of the effective stress τ when the composition ratio of the Si layer to the AlAs layer is changed in a digital alloy type layer structure made of Si layers and AlAs layers. When the Si layer is one atomic layer and the atomic layer of the AlAs layer is changed to 1 to 3 atomic layers, it can be seen that the effective stress τ decreases when the layer composition ratio of the AlAs layer to the Si layer is increased. In Figure 4, the vertical axis is the effective stress τ in arbitrary units, and the horizontal axis is the film thickness of the layer structure.

[0070] The effective stress τ during crystal growth of a digital alloy type multiplication layer containing Si acts in the direction of reducing the stress of the entire laminate structure by stacking a material with a larger lattice constant than Si. However, since the materials that make up the laminate structure are themselves lattice mismatched, the effective stress τ applied to the entire semiconductor light receiving element gradually increases, so it is necessary to control the film thickness of the entire laminate structure to be below the critical film thickness at which crystal defects do not occur.

[0071] In the second embodiment, a combination of a Si layer and an AlAs layer has been described as an example of the digital alloy multiplication layer. Instead of the AlAs layer, other III-V alloy semiconductor materials other than AlAs may be applied. Furthermore, the III-V alloy semiconductor material may be a ternary alloy semiconductor or a quaternary alloy semiconductor. The digital alloy multiplication layer may not be undoped, but may be doped, for example, p-type or n-type.

[0072] <Advantages of the second embodiment> As described above, according to the semiconductor photodetector of the second embodiment, the multiplication layer has a digital alloy structure in which Si layers, each having a thickness N times that of a monolayer, and AlAs layers, each having a thickness M times that of a monolayer, are alternately stacked multiple times, and the multiplication layer is configured as a Si-AlAs digital alloy type multiplication layer in which the number of monolayers M constituting the AlAs layer is greater than the number of monolayers N constituting the Si layer. This makes it possible to alleviate stress generated in the multiplication layer containing Si, thereby providing an effect of providing a semiconductor photodetector that is low noise and has excellent reliability.

[0073] Embodiment 3 <Element structure of semiconductor light receiving element according to the third embodiment> 5 is a cross-sectional view showing the device structure of a semiconductor light receiving element 120 according to the embodiment 3. As an example of the semiconductor light receiving element 120 according to the embodiment 3, a SACM type APD is given.

[0074] The semiconductor light receiving element 120 according to the third embodiment is a semiconductor device having a carrier concentration of 1 to 5×10 18 cm -3 The n-type AlInAs buffer layer 3 has a thickness of 0.1 to 0.5 μm, the i-type Si-AlAs digital alloy multiplication layer 4 has a thickness of 0.05 to 0.2 μm and is made of a digital alloy structure in which an i-type Si layer (for example, a thickness of 2 ML) and an i-type AlAs layer (for example, a thickness of 2 ML) are alternately laminated multiple times, and the i-type AlAs layer has a thickness of 15 nm. x Ga y In 1-x-y As (x=0.25, y=0.218) transition layer 22 and a carrier concentration of 0.5 to 1×10 18 cm -3 and a p-type AlInAs electric field relaxation layer 5 having a thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm -3 The n-type InGaAs light absorption layer 6 has a thickness of 1 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm -3 and an n-type InP window layer 8 having a thickness of 0.5 to 1 μm and a carrier concentration of 1 to 5×1018 cm -3 and a p-type InGaAs contact layer 9 having a circular ring shape and a layer thickness of 0.1 to 0.5 μm.

[0075] The semiconductor light-receiving element 120 according to the third embodiment further includes a Zn selective diffusion region 10 provided in a part of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protective film 11 provided on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 provided on the back surface side of the n-type InP substrate 2, and a p-type electrode 12 provided on the surface of the p-type InGaAs contact layer 9 having a circular ring shape.

[0076] The semiconductor light receiving element 120 according to the third embodiment has a multiplication layer made of an i-type Si-AlAs digital alloy type multiplication layer 4 having a digital alloy structure, and has an i-type AlInAs layer having a thickness of 15 nm between the i-type Si-AlAs digital alloy type multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5. x Ga y In 1-x-y The feature is that an As transition layer 22 is provided. x Ga y In 1-x-y The layers other than the As transition layer 22 are the same as the layers of the semiconductor light receiving device 100 according to the first embodiment.

[0077] <Method of Manufacturing Semiconductor Light-Receiving Element According to Third Embodiment> The method for manufacturing the semiconductor light receiving element 120 according to the third embodiment further comprises, during epitaxial crystal growth, forming an i-type Al layer between the i-type Si-AlAs digital alloy type multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5 having a digital alloy structure. x Ga y In 1-x-y The manufacturing method differs from that of the semiconductor light receiving element 100 according to the first embodiment only in that the As transition layer 22 is crystal-grown, and therefore a detailed description of the manufacturing method will be omitted.

[0078] <Function of the semiconductor light receiving element according to the third embodiment> In electron multiplying APDs, photocarriers are generated when light is incident on the APD. Electrons are conducted from the absorption layer to the multiplication layer through the layer to which a reverse bias is applied, and when they reach the multiplication layer, the carriers are avalanche multiplied and amplified. By applying a multiplication layer containing Si, the amount of band discontinuity that occurs between the absorption layer and the multiplication layer changes, which may become a band barrier and inhibit high-speed response. Band discontinuity is an obstacle to high-speed response, especially when the multiplication factor is small and the voltage is low.

[0079] For this reason, in the semiconductor light receiving element 120 according to the third embodiment, an AlInAs quaternary alloy semiconductor material having a band gap energy value intermediate between the band gap energy of the multiplication layer and the band gap energy of the relaxation layer is provided between the i-type Si-AlAs digital alloy type multiplication layer 4 and the p-type AlInAs electric field relaxation layer 5. x Ga y In 1-x-y By inserting a transition layer of about 15 nm thickness using As (x=0.25, y=0.22), the band barrier when electrons are conducted to the multiplication layer can be reduced. As a result, high-speed response of the semiconductor light receiving element 120 is possible. In addition to this effect, by growing a crystal layer with a different composition from the multiplication layer above the multiplication layer, it is expected that the effective stress τ of the entire layer structure can be partially alleviated.

[0080] In the third embodiment, an i-type Al is used as an example of the transition layer. x Ga y In 1-x-y Although an As layer was used, other alloy semiconductor materials may be used as long as they have an intermediate band gap energy value relative to the band gap energies of the absorption layer, the relaxation layer, and the multiplication layer. In addition, if the transition layer is composed of layers of the same composition as the layers that make up the digital alloy structure, it becomes easier to control the crystal growth. The transition layer may be other than undoped, and may be doped, for example, p-type or n-type.

[0081] <Advantages of the Third Embodiment> As described above, according to the semiconductor light receiving element of the third embodiment, an i-type AlInAs layer is provided between the Si-AlAs digital alloy type multiplication layer and the p-type AlInAs electric field relaxation layer. x Ga y In 1-x-y The provision of the As transition layer effectively reduces the band barrier that occurs between the Si-AlAs digital alloy type multiplication layer and the p-type AlInAs electric field relaxation layer, improving carrier conductivity and resulting in a semiconductor photodetector capable of high-speed operation.

[0082] Embodiment 4 <Element structure of semiconductor light receiving element according to the fourth embodiment> 6 is a cross-sectional view showing the device structure of a semiconductor light receiving element 130 according to the embodiment 4. As an example of the semiconductor light receiving element 130 according to the embodiment 4, a SACM type APD is given.

[0083] The semiconductor light receiving element 130 according to the fourth embodiment is a semiconductor device having a carrier concentration of 1 to 5×10 18 cm -3 an n-type AlInAs buffer layer 3 having a thickness of 0.1 to 0.5 μm; an i-type SiAs-AlAs digital alloy type multiplication layer 4b having a thickness of 0.05 to 0.2 μm and consisting of a digital alloy structure in which an i-type SiAs layer (e.g., a thickness of 2 ML) and an i-type AlAs layer (e.g., a thickness of 2 ML) are alternately laminated multiple times; and a carrier concentration of 0.5 to 1×10 18 cm -3 and a p-type AlInAs electric field relaxation layer 5 having a thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm -3 The n-type InGaAs light absorption layer 6 has a thickness of 1.0 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm -3 and an n-type InP window layer 8 having a thickness of 0.5 to 1.0 μm and a carrier concentration of 1 to 5×10 18 cm -3 and a p-type InGaAs contact layer 9 having a circular ring shape and a layer thickness of 0.1 to 0.5 μm.

[0084] The semiconductor light-receiving element 130 according to the fourth embodiment further includes a Zn selective diffusion region 10 (p-type conductive region) provided in a part of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protective film 11 provided on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 provided on the back surface side of the n-type InP substrate 2, and a p-type electrode 12 provided on the surface of the p-type InGaAs contact layer 9 having a circular ring shape.

[0085] The semiconductor light receiving element 130 according to the fourth embodiment is characterized in that the multiplication layer is composed of an i-type SiAs-AlAs digital alloy type multiplication layer 4b having a digital alloy structure in which i-type SiAs layers and i-type AlAs layers are alternately laminated multiple times.

[0086] The above-mentioned i-type SiAs layer refers to a SiAs superlattice layer having a layer thickness of N times (1≦N≦20) that of a SiAs monoatomic layer made of a compound of Si and As. The i-type SiAs layer is also called the first semiconductor layer 32a, the i-type AlAs layer is also called the second semiconductor layer 32b, and the i-type SiAs-AlAs digital alloy type multiplication layer 4b is also simply called the digital alloy type multiplication layer.

[0087] In the above description, the i-type SiAs-AlAs digital alloy type multiplication layer 4b is an example of a multiplication layer in which an i-type SiAs layer having a layer thickness of two monolayers (ML), that is, an i-type AlAs layer having a layer thickness of 2ML, is alternately stacked multiple times. The thickness of the i-type SiAs layer may be within a range of N times the monolayer (1≦N≦20), and the thickness of the i-type AlAs layer may be within a range of M times the monolayer (1≦M≦20). It is more preferable that the thickness of the i-type SiAs layer is within a range of N times the monolayer (1≦N≦6), and the thickness of the i-type AlAs layer is within a range of M times the monolayer (1≦M≦6). For the i-type SiAs-AlAs digital alloy type multiplication layer 4b, when the i-type SiAs layer and the i-type AlAs layer are alternately stacked multiple times, the number of stacking times is preferably within a range of 5 times or more and 300 times or less.

[0088] <Method of Manufacturing Semiconductor Light-Receiving Element According to Fourth Embodiment> The semiconductor light receiving element 130 according to the fourth embodiment can be manufactured by forming each semiconductor layer on an InP substrate by MOVPE. A method for manufacturing a SACM type APD, which is an example of the semiconductor light receiving element 130 according to the fourth embodiment, will be described below.

[0089] Using MOVPE at a growth temperature of 550° C., an n-type AlInAs buffer layer 3, an i-type SiAs-AlAs digital alloy type multiplication layer 4b having a digital alloy structure in which i-type SiAs layers (layer thickness 2 ML) and i-type AlAs layers (layer thickness 2 ML) are alternately stacked multiple times, a p-type AlInAs electric field relaxation layer 5, an n-type InGaAs light absorption layer 6, an i-type AlInAs window layer 7, an n-type InP window layer 8, and a p-type InGaAs contact layer 9 are sequentially crystal-grown on the surface of an n-type InP substrate 2.

[0090] When growing the i-type SiAs layer using MOVPE, silane (SiH4), a Si source, and arsine (AsH3), an As source, are used as source gases.

[0091] When the MOVPE method is used as the epitaxial crystal growth method, the crystal growth temperature is preferably about 550°C, but may be within the temperature range of 500°C to 600°C.

[0092] The wafer process after the epitaxial crystal growth is the same as in the first embodiment, and therefore a detailed description thereof will be omitted.

[0093] <Function of the semiconductor light receiving element according to the fourth embodiment> When stacking a multiplication layer containing Si at the atomic layer level, it may be difficult to form a film of simple Si depending on the crystal growth method. In particular, with the MOVPE method, it is difficult to form a film of simple Si in a crystal growth furnace. To address this issue, for example, not only silane (SiH4), which is the source gas for Si material, but also arsine (AsH3) or phosphine (PH3), which is the source gas for V-group atomic material, can be introduced into the crystal growth furnace at the same time and reacted to form a layer made of compounds such as a SiAs layer or a SiP layer, which can be made into a structure that is easier to form a film than a layer made of simple Si.

[0094] As an example, the relationship between the Si sheet carrier concentration and the supply amount of the Si material is shown in Fig. 7. By controlling the crystal growth temperature and the supply amount of the semiconductor material in this way, it becomes possible to form a structure in which semiconductor layers made of Si and other elements are stacked, instead of a Si layer stacked at the atomic layer level, and therefore it is possible to obtain the same effect as in the first embodiment.

[0095] In the fourth embodiment, silane (SiH4) is used as the Si material. However, any material containing Si can be used as a material for crystal growth regardless of whether it is solid, liquid, or gas. In the fourth embodiment, arsine (AsH3) is used as the V group atomic material, but any material, whether solid or liquid, can be used as a material for crystal growth as long as it contains As. Furthermore, if a compound with Si can be formed using a raw material containing a V group atomic material other than As, such as P or Sb, a similar effect can be obtained. In addition, the crystal growth method can be not only the MOVPE method, but also the MBE method.

[0096] <Advantages of the Fourth Embodiment> As described above, according to the semiconductor photodetector and the manufacturing method of the semiconductor photodetector of the fourth embodiment, a SiAs-AlAs digital alloy type multiplication layer having a digital alloy structure in which SiAs layers and AlAs layers are alternately stacked multiple times is provided as the multiplication layer, which has the effect of providing a semiconductor photodetector with low noise and excellent reliability, and the effect of making it easier to manufacture such a semiconductor photodetector.

[0097] Embodiment 5. <Element structure of semiconductor light receiving element according to the fifth embodiment> 8 is a cross-sectional view showing the device structure of a semiconductor light receiving element 140 according to the fifth embodiment. As an example of the semiconductor light receiving element 140 according to the fifth embodiment, a SACM type APD is given.

[0098] The semiconductor light receiving element 140 according to the fifth embodiment is a semiconductor device having a carrier concentration of 1 to 5×10 18 cm -3 an n-type AlInAs buffer layer 3 having a thickness of 0.1 to 0.5 μm; an i-type Si-Ge digital alloy multiplication layer 4c having a thickness of 0.05 to 0.2 μm and a digital alloy structure in which an i-type Si layer (e.g., a thickness of 2 ML) and an i-type Ge layer (e.g., a thickness of 2 ML) are alternately laminated multiple times; and a carrier concentration of 0.5 to 1×10 18 cm -3 and a p-type AlInAs electric field relaxation layer 5 having a thickness of 0.05 to 0.15 μm and a carrier concentration of 1 to 5×10 15 cm -3 The n-type InGaAs light absorption layer 6 has a thickness of 1.0 to 1.5 μm, the i-type AlInAs window layer 7 has a thickness of 0.05 to 1 μm, and the carrier concentration is 0.1 to 5×10 15 cm -3 and an n-type InP window layer 8 having a thickness of 0.5 to 1.0 μm and a carrier concentration of 1 to 5×10 18 cm -3 and a p-type InGaAs contact layer 9 having a circular ring shape and a layer thickness of 0.1 to 0.5 μm.

[0099] The semiconductor light-receiving element 140 according to the fifth embodiment further includes a Zn selective diffusion region 10 (p-type conductive region) provided in a part of the n-type InP window layer 8 and the i-type AlInAs window layer 7, a SiNx surface protective film 11 provided on the surface of the n-type InP window layer 8 including the surface of the Zn selective diffusion region 10, an n-type electrode 1 provided on the back surface side of the n-type InP substrate 2, and a p-type electrode 12 provided on the surface of the p-type InGaAs contact layer 9 having a circular ring shape.

[0100] The semiconductor light receiving element 140 according to the fifth embodiment is characterized in that the multiplication layer is composed of an i-type Si-Ge digital alloy type multiplication layer 4c having a digital alloy structure in which i-type Si layers and i-type Ge layers are alternately stacked multiple times.

[0101] The above-mentioned i-type Si layer refers to a silicon superlattice layer having a layer thickness N times (1≦N≦20) that of a silicon monoatomic layer, and the i-type Ge layer refers to a silicon superlattice layer having a layer thickness M times (1≦M≦20) that of a germanium monoatomic layer. The i-type Si layer is also called the first group IV atomic superlattice layer 33a, the i-type Ge layer is also called the second group IV atomic superlattice layer 33b, and the i-type Si-Ge digital alloy type multiplication layer 4c is also simply called the digital alloy type multiplication layer.

[0102] In the above description, the i-type Si-Ge digital alloy multiplication layer 4c is an example of a multiplication layer in which the layer thickness is two monolayers (ML), that is, an i-type Si layer having a layer thickness of 2ML and an i-type Ge layer having a layer thickness of 2ML are alternately stacked multiple times. However, the layer thickness of the i-type Si layer may be within a range of N times the monolayer (1≦N≦20), and the layer thickness of the i-type Ge layer may be within a range of M times the monolayer (1≦M≦20). It is more preferable if the layer thickness of the i-type Si layer is within a range of N times the monolayer (1≦N≦6), and the layer thickness of the i-type Ge layer is within a range of M times the monolayer (1≦M≦6). For the i-type Si-Ge digital alloy multiplication layer 4c, the number of times of stacking when the i-type Si layer and the i-type Ge layer are alternately stacked multiple times is preferably within a range of 5 times or more and 300 times or less.

[0103] <Method of Manufacturing Semiconductor Light-Receiving Element According to Fifth Embodiment> The semiconductor light receiving element 140 according to the fifth embodiment can be manufactured by forming each semiconductor layer on an InP substrate by MOVPE. A method for manufacturing a SACM type APD, which is an example of the semiconductor light receiving element 140 according to the fifth embodiment, will be described below.

[0104] Using MOVPE at a growth temperature of 550° C., an n-type AlInAs buffer layer 3, an i-type Si-Ge digital alloy type multiplication layer 4c having a digital alloy structure in which i-type Si layers (layer thickness 2 ML) and i-type Ge layers (layer thickness 2 ML) are alternately stacked multiple times, a p-type AlInAs electric field relaxation layer 5, an n-type InGaAs light absorption layer 6, an i-type AlInAs window layer 7, an n-type InP window layer 8, and a p-type InGaAs contact layer 9 are sequentially crystal-grown on the surface of an n-type InP substrate 2.

[0105] When growing the i-type Si layer using the MOVPE method, silane (SiH4), a Si source, is used as the source gas. When growing the i-type Ge layer using the MOVPE method, germane (GeH4), a Ge source, is used as the source gas.

[0106] When the MOVPE method is used as the epitaxial crystal growth method, the crystal growth temperature is preferably about 550°C, but may be within the temperature range of 500°C to 600°C.

[0107] The wafer process after the epitaxial crystal growth is the same as in the first embodiment, and therefore a detailed description thereof will be omitted.

[0108] <Function of the semiconductor light receiving element according to the fifth embodiment> In addition to the combination of Si and group V atomic material shown in the first embodiment, the same effect as the APD can be expected even if the group V atomic material is replaced with group IV atomic material Ge or carbon (C). Since Ge or C is the same group IV atomic material as Si, it is expected that the effect of partially improving interface control during crystal growth can be achieved. Furthermore, if Ge or C is used, the band gap value can be changed more than with the above-mentioned Si material, so it is also possible to control the energy barrier of electrons in the conduction band as explained in the third embodiment.

[0109] <Effects of the semiconductor light receiving element according to the fifth embodiment> As described above, according to the semiconductor photodetector of the fifth embodiment, a Si-Ge digital alloy type multiplication layer having a digital alloy structure in which Si layers and Ge layers are alternately stacked multiple times is provided as the multiplication layer. This reduces the energy barrier when carriers are conducted from the absorption layer to the multiplication layer containing Si, thereby providing an effect of obtaining a semiconductor photodetector capable of high-speed operation.

[0110] Although the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.

[0111] Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0112] 1 n-type electrode, 2 n-type InP substrate, 3 n-type AlInAs buffer layer, 4 i-type Si-AlAs digital alloy type multiplication layer, 4a i-type Si-AlAs digital alloy type multiplication layer, 4b i-type SiAs-AlAs digital alloy type multiplication layer, 4c i-type Si-Ge digital alloy type multiplication layer, 5 p-type AlInAs field relaxation layer, 6 n-type InGaAs light absorption layer, 7 i-type AlInAs window layer, 8 n-type InP window layer, 9 p-type InGaAs contact layer, 10 Zn selective diffusion region, 12 p-type electrode, 22 i-type Al x Ga y In 1-x-y As transition layer, 30a, 31a, 32a first semiconductor layer, 30b, 31b, 32b second semiconductor layer, 33a first group IV atomic superlattice layer, 33b second group IV atomic superlattice layer, 100, 110, 120, 130, 140 semiconductor light receiving element

Claims

1. A semiconductor substrate; a digital alloy type multiplication layer having a digital alloy structure in which a first semiconductor layer is formed on the semiconductor substrate and is made of a Si superlattice layer having a layer thickness N times (1≦N≦20) a Si monolayer, and a second semiconductor layer having a band gap energy larger than that of the first semiconductor layer, a layer thickness M times (1≦M≦20) a monolayer, and made of a semiconductor having a lattice constant larger than that of Si, are alternately stacked; an electric field relaxation layer formed on the digital alloy type multiplication layer and mitigating an electric field; a light absorbing layer formed on the electric field relaxation layer and configured to absorb incident light; A semiconductor light receiving element comprising:

2. 2. The semiconductor light-receiving element according to claim 1, wherein the second semiconductor layer has a thickness greater than that of the first semiconductor layer.

3. A semiconductor substrate; a digital alloy type multiplication layer having a digital alloy structure in which a first semiconductor layer is formed on the semiconductor substrate, the first semiconductor layer being made of Si and group V atoms and being a Si-containing superlattice layer having a layer thickness N times (1≦N≦20) that of a monoatomic layer, and a second semiconductor layer having a band gap energy larger than that of the first semiconductor layer, being made of a group III-V mixed crystal semiconductor and having a layer thickness M times (1≦M≦20) that of a monoatomic layer, are alternately laminated; an electric field relaxation layer formed on the digital alloy type multiplication layer and mitigating an electric field; a light absorbing layer formed on the electric field relaxation layer and configured to absorb incident light; A semiconductor light receiving element comprising:

4. 3. The semiconductor light-receiving element according to claim 1, wherein the second semiconductor layer is made of a III-V mixed crystal semiconductor.

5. 4. The semiconductor light-receiving element according to claim 1, further comprising a transition layer for relaxing distortion between the digital alloy type multiplication layer and the electric field relaxation layer.

6. epitaxially growing, on an n-type InP substrate, an n-type AlInAs buffer layer, a digital alloy multiplication layer having a digital alloy structure in which a Si layer or a layer containing Si having a layer thickness N times (1≦N≦20) a monolayer and an AlAs layer having a layer thickness M times (1≦M≦20) a monolayer are alternately stacked a plurality of times, a p-type AlInAs electric field relaxation layer, an n-type InGaAs light absorption layer, an i-type AlInAs window layer, an n-type InP window layer, and a p-type InGaAs contact layer, in that order by MOVPE; forming a Zn selective diffusion region in a portion of the n-type InP window layer and the i-type AlInAs window layer; A method for manufacturing a semiconductor light receiving element comprising the steps of:

7. 7. The method for producing a semiconductor light-receiving element according to claim 6, wherein the crystal growth temperature by the MOVPE method is within a range of 500° C. to 600° C.

8. 8. The method for producing a semiconductor light-receiving element according to claim 6, wherein silane is used as a source gas for Si during crystal growth of the Si layer or the layer containing Si by the MOVPE method.

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