Semiconductor device

Abstract

A semiconductor device (1) includes a vertical MOS transistor (10) having: a plurality of first trenches (17) which are formed so as to pass through a body region (18) from the upper surface of a low-concentration impurity layer (33), and which extend in a first direction; and a plurality of second trenches (27) which are formed so as to pass through the body region (18) from the upper surface of the low-concentration impurity layer (33) and so as to be deeper than the plurality of first trenches (17), and which extend in the first direction. The plurality of first trenches (17) and the plurality of second trenches (27) are alternately disposed in a second direction. A first conductor (15) connected to a gate electrode (19) is formed on the inside of the plurality of first trenches (17) and on the upper side inside the plurality of second trenches (27). A second conductor (25) connected to a source electrode (11) is formed on the lower side inside the plurality of second trenches (27). The interval between the second conductors (25) is twice the interval of the first conductors (15) in the second direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] 2. Description of the Related Art Conventionally, semiconductor devices have been known (see, for example, Japanese Patent Application Laid-Open No. 2003-144998).

[0003] JP 2021-40105 A

[0004] There is a demand for vertical MOS transistors that have improved breakdown voltage and reduced conduction resistance (on-resistance). An object of the present disclosure is to provide a semiconductor device including a vertical MOS transistor that can reduce conduction resistance while improving breakdown voltage.

[0005] In order to solve the above-described problems, a semiconductor device according to the present disclosure includes a semiconductor substrate of a first conductivity type; a low-concentration impurity layer of the first conductivity type formed on and in contact with the semiconductor substrate and containing an impurity at a concentration lower than a predetermined concentration of an impurity of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer; a source region of the first conductivity type formed in the body region; a source electrode electrically connected to the body region and the source region; a plurality of first trenches formed from an upper surface of the low-concentration impurity layer, penetrating the body region to a depth to a part of the low-concentration impurity layer, the source electrode having a portion in contact with the source region and extending in a first direction parallel to the upper surface of the low-concentration impurity layer; a plurality of second trenches extending in the first direction, the plurality of first trenches and the plurality of second trenches being alternately arranged in a second direction parallel to an upper surface of the low-concentration impurity layer and perpendicular to the first direction; a first conductor connected to a gate electrode of the vertical MOS transistor is formed inside the plurality of first trenches and on an upper side of the plurality of second trenches; a second conductor separated from the first conductor and connected to the source electrode is formed on a lower side of the plurality of second trenches; and a spacing between the second conductors in the second direction is twice the spacing between the first conductors in the second direction.

[0006] According to the above configuration, in the vertical MOS transistor, the conduction resistance can be reduced while the breakdown voltage is improved.

[0007] Another semiconductor device according to the present disclosure is a semiconductor device including a vertical MOS transistor having: a semiconductor substrate of a first conductivity type; a low-concentration impurity layer of the first conductivity type formed on and in contact with the semiconductor substrate and containing an impurity at a concentration lower than a predetermined concentration of an impurity of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer; a source region of the first conductivity type formed in the body region; a source electrode electrically connected to the body region and the source region; and a plurality of trenches formed to a depth from an upper surface of the low-concentration impurity layer, penetrating the body region to a portion of the low-concentration impurity layer, having a portion in contact with the source region, and extending in a first direction parallel to the upper surface of the low-concentration impurity layer. In a second direction that is parallel to and perpendicular to the first direction, the plurality of trenches are arranged at equal intervals, a first conductor connected to a gate electrode of the vertical MOS transistor is formed on an upper side inside the plurality of trenches, and a second conductor separated from the first conductor and connected to the source electrode is formed on a lower side inside the plurality of trenches, the plurality of trenches periodically have relatively shallow portions and relatively deep portions whose depths from a top surface of the low-concentration impurity layer are the same in the first direction, the first conductor has a constant length in a third direction perpendicular to both the first direction and the second direction in the first direction, and the length of the second conductor in the third direction changes periodically in the first direction.

[0008] According to the above configuration, in the vertical MOS transistor, the conduction resistance can be reduced while the breakdown voltage is improved.

[0009] Another semiconductor device according to the present disclosure includes a semiconductor substrate of a first conductivity type, a low-concentration impurity layer of the first conductivity type formed on and in contact with the semiconductor substrate and containing an impurity at a concentration lower than a predetermined concentration of an impurity of the semiconductor substrate, a body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer, a source region of the first conductivity type formed in the body region, a source electrode electrically connected to the body region and the source region, and a portion formed from an upper surface of the low-concentration impurity layer, penetrating the body region, to a depth to a part of the low-concentration impurity layer, the source electrode being in contact with the source region, a semiconductor device including a vertical MOS transistor having a plurality of first trenches extending in a first direction parallel to an upper surface of a pure material layer; and a plurality of second trenches formed from an upper surface of the low-concentration impurity layer, penetrating the body region, to a depth deeper than the plurality of first trenches, and extending in a second direction parallel to the upper surface of the low-concentration impurity layer and perpendicular to the first direction, wherein a first conductor connected to a gate electrode of the vertical MOS transistor is formed inside the plurality of first trenches, and a second conductor connected to the source electrode is formed inside the plurality of second trenches.

[0010] According to the above configuration, in the vertical MOS transistor, the conduction resistance can be reduced while the breakdown voltage is improved.

[0011] The present disclosure can provide a semiconductor device including a vertical MOS transistor with reduced conduction resistance (on-resistance) and improved breakdown voltage.

[0012] FIG. 1A is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 1. FIG. 1B is a schematic plan view showing an example of the structure of a semiconductor device according to embodiment 1. FIG. 2A is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 1. FIG. 2B is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 1. FIG. 3A is a schematic plan view showing an example of the structure of a semiconductor device according to embodiment 1. FIG. 3B is a schematic plan view showing an example of the internal structure of the semiconductor device according to embodiment 1, with a portion of the structure exposed on the surface removed. FIG. 4A is a schematic plan view showing an example of a schematic unit configuration of a transistor according to embodiment 1. FIG. 4B is a schematic perspective view showing an example of a schematic unit configuration of a transistor according to embodiment 1. FIG. 5A is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 1. FIG. 5B is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 1. FIG. 5C is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 1. FIG. 5D is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 1. FIG. 5E is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 1. FIG. 5F is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5G is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5H is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5I is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5J is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5K is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5L is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view schematically illustrating an example of the structure of a semiconductor device of Comparative Example 1 according to the first embodiment. FIG. 7A is a cross-sectional view schematically illustrating the effect of the semiconductor device according to the first embodiment. FIG. 7B is a cross-sectional view schematically illustrating the semiconductor device of Comparative Example 1 according to the first embodiment in comparison with the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view schematically illustrating a modification of the semiconductor device according to the first embodiment. FIG. 9A is a cross-sectional view schematically illustrating an example of the structure of a semiconductor device according to the second embodiment. FIG. 9B is a plan view schematically illustrating an example of the structure of a semiconductor device according to the second embodiment.9C is a cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 2. FIG. 9D is a cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 2. FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 2. FIG. 11A is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11B is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11C is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11D is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11E is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11F is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11G is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11H is a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11I is a schematic plan view and a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11J is a schematic plan view and a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 11K is a schematic plan view and a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 2. FIG. 12A is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 3. FIG. 12B is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 3. FIG. 12C is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 3. FIG. 12D is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 3. FIG. 12E is a schematic plan view showing an example of the structure of a semiconductor device according to embodiment 3. FIG. 13A is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. FIG. 13B is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. FIG. 13C is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. FIG. 13D is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. 13E is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the third embodiment. FIG. 13F is a cross-sectional view schematically illustrating a manufacturing process of the semiconductor device according to the third embodiment.Fig. 13G is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. Fig. 13H is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. Fig. 13I is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. Fig. 13J is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. Fig. 13K is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to embodiment 3. Fig. 14A is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 3. Fig. 14B is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to embodiment 3.

[0013] Specific examples of semiconductor devices according to one aspect of the present disclosure will be described below with reference to the drawings. Each embodiment shown here represents a specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangements of components, and connection forms shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations will be omitted or simplified.

[0014] (Embodiment 1) [1. Structure of Semiconductor Device] Fig. 1A is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to this embodiment 1. Fig. 1B is a plan view of the semiconductor device 1, and Fig. 1A is a cross section taken along line I-I in Fig. 1B. Note that Fig. 1B shows a passivation layer 35, an interlayer insulating layer 34, and a source electrode 11, which will be described later, as if they were transparent, allowing the underlying structure to be seen through.

[0015] 1A and 1B, the semiconductor device 1 includes a semiconductor substrate 32, a metal layer 30, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0016] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of a first conductivity type containing impurities. The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 32. The low-concentration impurity layer 33 is of the first conductivity type and contains impurities at a concentration lower than the predetermined impurity concentration of the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0017] As shown in FIG. 1A, the semiconductor device 1 has a vertical MOS transistor 10 (hereinafter also referred to as “transistor 10 ”) formed in a semiconductor layer 40 .

[0018] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40 (semiconductor substrate 32) and is made of, for example, silver (Ag) or copper (Cu). Note that the metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material. The metal layer 30 may or may not be formed over the entire back surface of the semiconductor layer 40 (semiconductor substrate 32). The thickness of the metal layer 30 is, for example, 3 μm or more and 50 μm or less.

[0019] 1A and 1B, a body region 18 of a second conductivity type different from the first conductivity type is formed in the semiconductor layer 40 (low-concentration impurity layer 33). A source region 14 of the first conductivity type is formed above the body region 18.

[0020] A plurality of first trenches 17 are formed, each penetrating from the upper surface of the semiconductor layer 40 through the source region 14 and the body region 18 to a depth D1 [μm] of a portion of the low-concentration impurity layer 33. Similarly, a plurality of second trenches 27 are formed, each penetrating from the upper surface of the semiconductor layer 40 through the source region 14 and the body region 18 to a depth D2 [μm] of a portion of the low-concentration impurity layer 33. D2 is greater than D1 (D1<D2).

[0021] The plurality of first trenches 17 and the plurality of second trenches 27 both extend in the Y direction and are arranged side by side parallel to the X direction. The Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the plurality of first trenches 17 extend. The X direction is parallel to the upper surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction is perpendicular to both the X direction and the Y direction and indicates the height direction of the semiconductor device. In this disclosure, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction.

[0022] The plurality of first trenches 17 and the plurality of second trenches 27 are arranged in stripes alternately at equal intervals W1 [μm] in the X direction.

[0023] A gate insulating film 16 is formed on the inner surfaces of the plurality of first trenches 17, and a gate conductor 15 is formed on the gate insulating film 16 inside the first trench 17. The gate conductor 15 is a buried electrode buried inside the semiconductor layer 40. Since only the gate conductor 15 is formed in the plurality of first trenches 17, the first trenches 17 are sometimes referred to as gate trenches 17.

[0024] The plurality of second trenches 27 have a so-called split structure, and inside thereof, a gate conductor 15 is buried in the upper part, and a shield conductor 25 is buried in the lower part. Since the shield conductor 25 is formed in the plurality of second trenches 27, the second trenches 27 are sometimes referred to as shield trenches 27.

[0025] A shield insulating film 26 is formed on the inner surfaces of the second trenches 27, which are located deeper than the first trenches 17, and the shield conductor 25 is formed on the shield insulating film 26 inside the second trench 27. The shield conductor 25 is a buried electrode buried inside the semiconductor layer 40.

[0026] Inside the second trenches 27, an intermediate insulating film 36 is formed on the shield conductor 25 and the shield insulating film 26. The intermediate insulating film 36 is formed at a position where the depth from the top surface of the semiconductor layer 40 is D1. That is, inside the second trenches 27, the shield conductor 25 is formed only at a position deeper than the first trenches 17.

[0027] Inside the second trenches 27, a gate insulating film 16 is formed on the inner surface (part of the side surface) at a position shallower than the depth D1 (above the intermediate insulating film 36), and the gate conductor 15 is formed on the intermediate insulating film 36 inside the second trenches 27. As in the first trenches 17, in the second trenches 27, the gate conductor 15 is a buried electrode buried inside the semiconductor layer 40.

[0028] The gate conductors 15 are formed in the plurality of first trenches 17 and also in the plurality of second trenches 27. Therefore, the gate conductors 15 are disposed at equal intervals of W1 [μm] in the X direction. In contrast, the shield conductors 25 are formed only in the plurality of second trenches 27. The shield conductors 25 are disposed at equal intervals of W2 [μm] in the X direction, so that the relationship W1 = W2 / 2 holds.

[0029] 2A is a schematic cross-sectional view of the YZ plane at a location where one of the plurality of first trenches 17 extends in the Y direction and terminates, and FIG. 2B is a schematic cross-sectional view of the YZ plane at a location where one of the plurality of second trenches 27 extends in the Y direction and terminates.

[0030] The gate conductor 15 formed inside the plurality of first trenches 17 and the gate conductor 15 formed inside the plurality of second trenches 27 are both connected to the gate electrode 19 (shown in FIG. 3B) shown in FIGS. 2A and 2B and are at the same potential as the gate electrode 19. The shield conductor 25 formed in the plurality of second trenches 27 is connected to the portion 13 of the source electrode 11 shown in FIGS. 1A and 2B and is at the same potential as the source electrode 11.

[0031] The source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the source region 14 and the body region 18, and further to the shield conductor 25, via the portion 13. The portion 12 of the source electrode 11 is a layer that is joined with solder during reflow in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of the portion 12 may be plated with gold or the like.

[0032] Portion 13 of source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver. The thickness of source electrode 11, including portions 12 and 13, is, for example, 2 μm or more and 13 μm or less.

[0033] With the above-described configuration of the transistor 10, the semiconductor substrate 32 functions as a drain region of the transistor 10. A part of the low-concentration impurity layer 33 on the side in contact with the semiconductor substrate 32 may also function as a drain region. Note that the low-concentration impurity layer 33 also serves as a drift layer of the transistor 10, and may be referred to as the drift layer 33 in this specification.

[0034] The metal layer 30 also functions as a drain electrode of the transistor 10. Therefore, hereinafter, the metal layer 30 will also be referred to as a drain electrode 30.

[0035] 1A , the body region 18 is covered with an interlayer insulating layer 34 having an opening, and a portion 13 of the source electrode 11 connected to the source region 14 is provided through the opening in the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the source electrode 11 are covered with a passivation layer 35 having an opening, and a portion 12 of the passivation layer 35 is provided through the opening to connect to the portion 13 of the source electrode 11.

[0036] Therefore, each of the multiple source pads 111 refers to a region where the source electrode 11 is partially exposed on the surface of the semiconductor device 1, that is, a so-called terminal portion. Similarly, each of the one or more gate pads 119 (shown in FIG. 3A) refers to a region where the gate electrode 19 (shown in FIG. 3B) is partially exposed on the surface of the semiconductor device 1, that is, a so-called terminal portion.

[0037] Fig. 3A is a schematic plan view of semiconductor device 1. Fig. 3B is a schematic plan view of semiconductor device 1 with passivation layer 35 and interlayer insulating layer 34 removed, exposing and showing portion 13 of source electrode 11 and gate electrode 19 that are actually located directly under passivation layer 35. For ease of understanding, body region 18, source pad 111, and gate pad 119, which would not be visible in this state, are shown by dashed lines in Fig. 3B.

[0038] The schematic plan view shown in Fig. 1B may be considered to be an extracted rectangular region surrounded by dotted lines in Fig. 3A and Fig. 3B, and the schematic cross-sectional views shown in Fig. 2A and Fig. 2B may be considered to be enlarged cross-sectional views of a portion near the end in the Y direction in Fig. 3A.

[0039] 3B is an example, in which the gate electrode 19 substantially surrounds the entire periphery of the body region 18, and the gate electrode 19 is further surrounded by the portion 13 of the source electrode 11. With this arrangement, as shown in FIGS. 2A and 2B, no matter in what direction the multiple first trenches 17 and the multiple second trenches 27 extend, they can be connected to the portion 13 of the source electrode 11 and the gate electrode 19, respectively, at their end portions in that direction.

[0040] In the semiconductor device 1, for example, the first conductivity type may be N-type and the second conductivity type may be P-type, with the source region 14, the semiconductor substrate 32, and the low-concentration impurity layer 33 being N-type semiconductors and the body region 18 being P-type semiconductors.

[0041] In addition, in the semiconductor device 1, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, with the source region 14, the semiconductor substrate 32, and the low-concentration impurity layer 33 being P-type semiconductors and the body region 18 being N-type semiconductors.

[0042] 2. Operation of Vertical MOS Transistor In the following description, the conduction operation of the semiconductor device 1 will be described assuming that the transistor 10 is a so-called N-channel transistor, in which the first conductivity type is N-type and the second conductivity type is P-type.

[0043] 4A and 4B are a plan view and a perspective view, respectively, of a general unit configuration of a transistor 10 repeatedly formed in the X direction and the Y direction of the semiconductor device 1. For ease of understanding, the semiconductor substrate 32, the metal layer 30, the passivation layer 35, the source electrode 11, and the interlayer insulating layer 34 are not shown in FIGS.

[0044] 4A and 4B , the transistor 10 includes a connection portion 18a that electrically connects the body region 18 and the source electrode 11. The connection portion 18a is a region of the body region 18 in which the source region 14 is not formed, and has the same second conductivity type as the body region 18. The source regions 14 and the connection portions 18a are alternately and periodically arranged in the Y direction.

[0045] In the semiconductor device 1, when a high voltage is applied to the drain electrode 30 and a low voltage is applied to the source electrode 11, and a voltage equal to or greater than the threshold value is applied to the gate electrode 19 relative to the source electrode 11, a conductive channel is formed in the body region 18 near the gate insulating film 16. As a result, a main current flows through the path of the metal layer 30 - semiconductor substrate 32 - low-concentration impurity layer 33 - conductive channel formed in the body region 18 - source region 14 - source electrode 11, bringing the semiconductor device 1 into a conductive state. In this conductive path, a PN junction is present at the contact surface between the body region 18 and the low-concentration impurity layer 33, which functions as a body diode.

[0046] When a high voltage is applied to the source electrode 11 and a low voltage is applied to the drain electrode 30, a main current flows through the body diode along the path of the source electrode 11-connection portion 18a-body region 18-low-concentration impurity layer 33-semiconductor substrate 32-metal layer 30.

[0047] 3. Method for Manufacturing Semiconductor Device An example of a method for manufacturing the transistor 10 according to the first embodiment will be described.

[0048] As shown in FIG. 5A, a mask layer 38 made of oxide or the like is formed on the upper surface of the semiconductor layer 40 (semiconductor substrate 32 and low-concentration impurity layer 33) in which the body region 18 is selectively formed.

[0049] 5B, the resist applied to the mask layer 38 is patterned to provide openings at regular intervals in the X direction. At this time, the width of the resist openings in the X direction will ultimately become the width of the second trench 27.

[0050] Next, as shown in FIG. 5C, the openings in the resist are etched and the mask layer 38 is removed.

[0051] 5D, the remaining resist is patterned again to provide new exposed portions of mask layer 38 periodically in the X direction. The width of the newly provided openings in the resist in the X direction will ultimately be the width of first trench 17.

[0052] Next, as shown in FIG. 5E, the portions of the mask layer 38 newly exposed in the step of FIG. 5D are etched to remove the mask layer 38, leaving a certain thickness on the semiconductor layer 40.

[0053] Next, the resist is removed as shown in Fig. 5F. At the end of the process shown in Fig. 5F, the mask layer 38 is selectively and thinly deposited only in the areas that will later become the first trenches 17.

[0054] 5G, the mask layer 38 and the semiconductor layer 40 are etched using the partially remaining mask layer 38 as a mask. When the etching process shown in FIG. 5G is performed, etching of the semiconductor layer 40 proceeds from the beginning in areas where the mask layer 38 was originally completely removed. On the other hand, in areas where a thin layer of the mask layer 38 was left, the mask layer 38 is first completely removed, and then etching of the semiconductor layer 40 directly below it begins. However, at this point, etching of the semiconductor layer 40 has already progressed in areas where the mask layer 38 was originally completely removed, so trenches of different depths are formed alternately in the semiconductor layer 40.

[0055] The difference in depth between the first trench 17 and the second trench 27 can be controlled by manipulating the thickness of the mask layer 38, the etching conditions, the remaining thickness of the mask layer 38 left on the top surface of the semiconductor layer 40 in the process shown in FIG. 5E, and the like.

[0056] Furthermore, the width of the first trench 17 and the width of the second trench 27, or the spacing between the first trenches 17, the spacing between the second trenches 27, and the spacing between the first trench 17 and the second trench 27 can be freely designed by controlling the dimensions for patterning the resist. In the first embodiment, control is performed so that the relationship W1 = W2 / 2 is established.

[0057] 5H, an insulating film (oxide film) is formed on the inner surfaces of the plurality of first trenches 17 and the plurality of second trenches 27. The insulating film formed here serves as the gate insulating film 16 in the plurality of first trenches 17, and serves as the shield insulating film 26 in the lower portion and the gate insulating film 16 in the upper portion of the plurality of second trenches 27. The mask layer 38 may remain. Typically, the mask layer 38 and the insulating film are made of the same oxide.

[0058] 5I, the insides of the formed first trenches 17 and second trenches 27 are filled with a conductive material, such as polysilicon, and then a certain amount of etching is performed. At this time, adjustments are made so that no polysilicon remains inside the first trenches 17. The polysilicon remaining only in the lower parts inside the second trenches 27 is the shield conductor 25.

[0059] Next, as shown in Fig. 5J, an intermediate insulating film 36 is formed on the upper surface of the shield conductor 25, and then, as shown in Fig. 5K, the interiors of the first trenches 17 and the upper portions of the interiors of the second trenches 27 (above the intermediate insulating film 36) are filled with polysilicon again, and then a certain amount is etched away. The polysilicon formed at this time is the gate conductor 15.

[0060] Next, as shown in FIG. 5L, an oxide film is formed on the entire upper surface of the semiconductor layer 40, including the upper surface of the gate conductor 15, to form the interlayer insulating layer .

[0061] Next, an opening is provided in the interlayer insulating layer 34, and the source electrode 11 is formed on the interlayer insulating layer 34 so as to connect to the source region 14, the body region 18, and the shield conductor 25 through the opening. Furthermore, the gate electrode 19 (not shown) is formed on the interlayer insulating layer 34 so as to connect to the gate conductor 15 through the opening in the interlayer insulating layer 34.

[0062] Next, a passivation layer 35 is formed so as to cover the source electrode 11, the gate electrode 19, and the interlayer insulating layer 34, and openings are further provided in the passivation layer 35, where a source pad 111 and a gate pad 119 are formed.

[0063] The above steps form a grid of transistors 10 on the silicon wafer, which will be individually separated later. Details of the formation of source regions 14, the impurity implantation into gate conductors 15, shield conductors 25, and other processes, as well as heat treatment, are omitted here, but these processes can be performed at any of the steps shown in FIGS. 5A to 5L.

[0064] Next, the back side of the silicon wafer (corresponding to the semiconductor substrate 32 in terms of each transistor 10 to be subsequently separated) is thinned. In the thinning process, the thickness of the semiconductor layer 40 is preferably controlled to be 15 μm or more and 100 μm or less, and more preferably, 15 μm or more and 75 μm or less.

[0065] Next, a metal layer 30 is formed on the thinned backside of the silicon wafer. The metal layer 30 may have a multi-layer structure including, for example, multiple metal layers. The multiple metal layers may be individually formed by any method, such as vapor deposition, sputtering, or plating.

[0066] Next, the silicon wafer is diced to separate each transistor 10 into individual pieces.

[0067] [4. Discussion] The following describes the effects achieved by the semiconductor device 1 according to the first embodiment.

[0068] For the transistor 10 in the semiconductor device 1, the potential difference between the drain electrode 30 and the source electrode 11 is referred to as the drain-source voltage, or simply the drain voltage (VDS [V]). Although typically stated in the product specifications, the maximum specified voltage (BVDS [V]) that guarantees safe use of the transistor 10 even when applied between the drain and source is sometimes referred to as the drain breakdown voltage, or simply the breakdown voltage, in this disclosure.

[0069] A PN junction is provided at the boundary between the body region 18 and the low-concentration impurity layer 33, and a depletion layer is generated across the PN junction. In order to increase the drain breakdown voltage, a structure is required in which the depletion layer can be sufficiently expanded when the transistor 10 is off, thereby reducing the electric field strength generated within the depletion layer.

[0070] For example, in order to sufficiently expand the depletion layer, it is effective to lower the carrier concentration (increase the resistivity) or increase the thickness of the low-concentration impurity layer 33. However, such measures are not preferable because they increase the conduction resistance of the current path from the tip of the gate trench 17 to the drain electrode 30.

[0071] The transistor 10 according to the first embodiment has a shield trench 27 that is deeper than the gate trench 17. Therefore, the shield trench 27 physically pushes down the expansion of the depletion layer, thereby reducing the electric field strength generated near the tip of the gate trench 17. In addition, since the buried shield conductor 25 has the same potential as the source electrode 11, it also has the effect of reducing the gate-drain capacitance. Therefore, the breakdown voltage of the transistor 10 is improved compared to when the shield trench 27 is not provided.

[0072] On the other hand, since the shield trench 27 is generally formed deeper than the gate trench 17, it has the side effect of impeding the current that attempts to flow toward the drain electrode 30 via the tip of the adjacent gate trench 17 by spreading in the X direction in the low-concentration impurity layer 33.

[0073] 6 shows a schematic cross-sectional view of a transistor 10A in a semiconductor device 1A according to Comparative Example 1 of Embodiment 1. Compared to the transistor 10 according to Embodiment 1, the transistor 10A has a structure in which all of the multiple first trenches 17 are replaced with multiple second trenches 27. In other words, the transistor 10A has a structure in which only split-type shield trenches 27 exist.

[0074] 7A and 7B show, with white arrows, the flow of current from the source electrode 11 to the drain electrode 30 in the transistor 10 and the transistor 10A. Fig. 7A is a schematic cross-sectional view of the transistor 10, and Fig. 7B is a schematic cross-sectional view of the transistor 10A of Comparative Example 1. Each shows an enlarged portion of the structure to show the flow of current through a conduction channel formed along one second trench 27.

[0075] 7A , in the transistor 10 of the first embodiment, the current that has passed through the conduction channel formed along the upper portion of the second trench 27 in the body region 18 tends to spread in the X direction due to the high resistivity of the low-concentration impurity layer 33. The shallow first trench 17 is adjacent to both sides of the second trench 27, allowing the current to spread sufficiently widely. This effectively reduces the conduction resistance when the current passes through the low-concentration impurity layer 33 and the semiconductor substrate 32.

[0076] 7B , in the transistor 10A of Comparative Example 1, because the transistor 10A is provided with only the deep second trench 27, the current that has passed through the conduction channel formed along the upper portion of the second trench 27 in the body region 18 cannot sufficiently spread in the X direction in the low-concentration impurity layer 33. Therefore, the conduction resistance when the current passes through the low-concentration impurity layer 33 is relatively high compared to when the current spreads and flows.

[0077] Therefore, in the transistor 10 according to the first embodiment, the effect of reducing the conduction resistance when a current passes through the low-concentration impurity layer 33 and the semiconductor substrate 32 can be obtained.

[0078] In the transistor 10A according to Comparative Example 1, if the spacing between the second trenches 27 in the X direction is increased, the effect of spreading the current flow in the low-concentration impurity layer 33 and the semiconductor substrate 32 can be obtained, as in the transistor 10 according to Embodiment 1. However, in that case, the spacing between the gate conductors 15 in the X direction also increases, reducing the total gate width and resulting in an increase in the conduction resistance when the current passes through the body region 18 (conduction channel).

[0079] In the transistor 10 according to the first embodiment, the total gate width is not reduced, and therefore, the effect of reducing the conduction resistance when a current passes through the body region 18, the low-concentration impurity layer 33, and the semiconductor substrate 32 can be obtained.

[0080] Therefore, the semiconductor device 1 according to the first embodiment includes a semiconductor substrate 32 of a first conductivity type, a low-concentration impurity layer 33 of the first conductivity type formed on and in contact with the semiconductor substrate 32 and containing an impurity at a concentration lower than a predetermined concentration of the impurity of the semiconductor substrate 32, a body region 18 of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer 33, a source region 14 of the first conductivity type formed in the body region 18, a source electrode 11 electrically connected to the body region 18 and the source region 14, a plurality of first trenches 17 formed from an upper surface of the low-concentration impurity layer 33, penetrating the body region 18 to a depth up to a part of the low-concentration impurity layer 33, having a portion in contact with the source region 14, and extending in a first direction parallel to the upper surface of the low-concentration impurity layer 33, and a plurality of first trenches 17 formed from an upper surface of the low-concentration impurity layer 33, penetrating the body region 18, and deeper than the plurality of first trenches 17, and in contact with the source region 14. and a plurality of second trenches 27 extending in a first direction, the plurality of first trenches 17 and the plurality of second trenches 27 being alternately arranged in a second direction that is parallel to an upper surface of a low-concentration impurity layer 33 and perpendicular to the first direction, first conductors 15 (gate conductors 15) connected to gate electrodes 19 of the vertical MOS transistor 10 are formed inside the plurality of first trenches 17 and on upper sides of the plurality of second trenches 27, second conductors 25 (shield conductors 25) separated from the first conductors 15 and connected to source electrodes 11 are formed on lower sides of the plurality of second trenches 27, and the spacing (W2) between the second conductors 25 in the second direction is twice the spacing (W1) between the first conductors 15 in the second direction (W2 = 2 × W1).

[0081] Incidentally, since the first trenches 17 function when formed to a position (D1) shallower than the second trenches 27, the width of the first trenches 17 may be formed narrower than the width of the second trenches 27. If only the width of the first trenches 17 can be formed narrower, it is possible to form many gate conductors 15 embedded in a limited area, and the total gate width can be increased. Increasing the total gate width is advantageous for reducing the conduction resistance of the current passing through the body region 18 (channel).

[0082] 8 shows a schematic cross-sectional view when the width of the plurality of first trenches 17 is formed narrower than the width of the plurality of second trenches 27. In the transistor 10 according to the first embodiment, a first gate conductor 15 is formed in the upper part of each pair of the first trench 17 and the second trench 27 that are adjacent to each other in the X direction. The position of the midpoint of the closest distance between the first gate conductors 15 adjacent to each other in the X direction (● in the figure) is closer to the first trench 17 than the position of the midpoint of the spacing between the first gate conductors 15 adjacent to each other in the X direction (◯ in the figure).

[0083] If the width of the plurality of first trenches 17 and the width of the plurality of second trenches 27 are the same, the positions of both are in the same place. The position of the midpoint of the closest distance between adjacent first gate conductors 15 in the X direction (● in the figure) is closer to the first trench 17 than the position of the midpoint of the interval between adjacent first gate conductors 15 in the X direction (◯ in the figure), so that the number of first gate conductors 15 to be installed increases.

[0084] Therefore, it is desirable that the midpoint of the closest distance between a pair of gate conductors 15 adjacent in the X direction is closer to the first trench 17 than the midpoint of the interval between the gate conductors 15 adjacent in the X direction.

[0085] Second Embodiment Hereinafter, a semiconductor device 1B (transistor 10B) according to a second embodiment will be described, which is configured by partially changing the configuration of the semiconductor device 1 (transistor 10) according to the first embodiment.

[0086] Here, for the transistor 10B of embodiment 2, the components that are similar to those of the transistor 10 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from the transistor 10.

[0087] The transistor 10B according to the second embodiment is an example of a configuration in which the plurality of first trenches 17 and the plurality of second trenches 27 in the transistor 10 according to the first embodiment are all changed to a plurality of third trenches 37.

[0088] 9A, 9C, and 9D are cross-sectional schematic diagrams showing an example of the structure of a semiconductor device 1B (transistor 10B) according to the second embodiment. FIG. 9B is a plan view of the semiconductor device 1B, where FIG. 9A is a cross-sectional surface taken along line II-II in FIG. 9B, FIG. 9C is a cross-sectional surface taken along line III-III in FIG. 9B, and FIG. 9D is a cross-sectional surface taken along line IV-IV in FIG. 9B. In FIG. 9B, a passivation layer 35, an interlayer insulating layer 34, and a source electrode 11, which will be described later, are shown as if they were transparent, allowing the underlying structure to be seen through.

[0089] The plurality of third trenches 37 penetrate from the upper surface of the semiconductor layer 40 through the source region 14 and the body region 18 to a depth reaching a part of the low-concentration impurity layer 33. The plurality of third trenches 37 extend in the Y direction and are arranged in parallel to each other at equal intervals W1 [μm] in the X direction.

[0090] The plurality of third trenches 37 have a structure in which relatively shallow portions and relatively deep portions appear periodically from the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33). Therefore, as can be seen by comparing Figures 9A, 9C, and 9D, even one third trench 37 appears to have a different depth depending on the position when viewed cross-sectionally in the XZ plane.

[0091] The plurality of third trenches 37 have a so-called split structure, and inside thereof, the gate conductor 15 is buried in the upper part, and the shield conductor 25 is buried in the lower part.

[0092] A shield insulating film 26 is formed on the lower side of the inner surfaces (part of the bottom surface and side surfaces) of the third trenches 37, and the shield conductor 25 is formed on the shield insulating film 26 inside the lower side of the third trenches 37. The shield conductor 25 is a buried electrode buried inside the semiconductor layer 40. Note that since the depth of the third trenches 37 changes periodically, the length of the shield conductor 25 in the Z direction also changes periodically depending on the position when viewed cross-sectionally in the XZ plane.

[0093] Inside the plurality of third trenches 37, an intermediate insulating film 36 is formed on top of the shield conductor 25 and the shield insulating film 26. The intermediate insulating film 36 is formed at a position having a depth D1 [μm] from the top surface of the semiconductor layer 40. That is, inside the plurality of third trenches 37, the intermediate insulating film 36 is formed at a position having the same depth as the plurality of first trenches 17 of the transistor 10 according to the first embodiment.

[0094] Inside the plurality of third trenches 37, a gate insulating film 16 is formed on the inner surface (part of the side surface) at a position shallower than depth D1 (above the intermediate insulating film 36), and the gate conductor 15 is formed on the intermediate insulating film 36 inside the third trench 37. In the plurality of third trenches 37, the gate conductor 15 is a buried electrode buried inside the semiconductor layer 40. Note that the length of the gate conductor 15 in the Z direction is constant and does not change regardless of the position when viewed cross-sectionally in the XZ plane.

[0095] Each third trench 37 periodically has relatively shallow portions and relatively deep portions along the Y direction, the depth of which is from the top surface of the semiconductor layer 40 (low-concentration impurity layer 33). The interval at which the relatively deep portions are formed in the Y direction is W2 [μm]. The depth of the relatively deep portions from the top surface of the semiconductor layer 40 (low-concentration impurity layer 33) is D2 [μm]. The length of the relatively deep portion in the Y direction is, for example, the same as the width of the third trench 37 in the X direction.

[0096] The relatively shallow portion has a depth from the top surface of the semiconductor layer 40 (low-concentration impurity layer 33) that is greater than D1 and smaller than D2. The length of the relatively shallow portion in the Y direction is, for example, equal to the length W2 minus the width of the third trench 37 in the X direction.

[0097] Therefore, the gate conductors 15 are arranged at equal intervals of W1 in the X direction. Meanwhile, the portions of the shield conductor 25 that reach the depth D2 are arranged at equal intervals of W2 in the Y direction. Note that, similar to the transistor 10 according to the first embodiment, it is safe to assume that the relationship W1<W2 also holds true in the transistor 10B.

[0098] The relatively deep portions of the third trenches 37 are regularly arranged in the XY plane. As an example, they are formed at positions corresponding to the vertices of an imaginary triangle, part of which is shown by a dashed line in FIG. 9B . That is, in a plan view of the semiconductor layer 40, in a pair (two) of adjacent third trenches 37 among the plurality of third trenches 37, the three closest relatively deep portions are arranged so as to correspond to the vertices of an equilateral triangle. Therefore, between W1 and W2, The following relationship is established.

[0099] 10 is a schematic cross-sectional view of the YZ plane at a location where one of the plurality of third trenches 37 extends in the Y direction and terminates. The gate conductor 15 formed inside the plurality of third trenches 37 is connected to the gate electrode 19 shown in Fig. 10 and has the same potential as the gate electrode 19. The shield conductor 25 formed in the plurality of third trenches 37 is connected to the source electrode 11 shown in Figs. 9A and 10 and has the same potential as the source electrode 11.

[0100] 2. Method for Manufacturing Semiconductor Device An example of a method for manufacturing the transistor 10B according to the second embodiment will be described.

[0101] 11A to 11K are schematic diagrams showing a part of the manufacturing process of the transistor 10B. The top diagram is a schematic plan view (XY plane) when viewed from above, the middle diagram is a schematic cross-sectional view (XZ plane) taken along line a-a in the plan view, and the bottom diagram is a schematic cross-sectional view (XZ plane) taken along line bb in the plan view.

[0102] First, as shown in FIG. 11A , a mask layer 38 made of oxide or the like is formed on the upper surface of the semiconductor layer 40 (semiconductor substrate 32 and low-concentration impurity layer 33) in which the body region 18 is selectively formed. Next, as shown in FIG. 11B , a resist applied to the mask layer 38 is patterned to form openings. At this time, the openings in the resist correspond to the locations of the plurality of third trenches 37 that will later reach a depth of D2. Next, as shown in FIG. 11C , the mask layer 38 in the openings in the resist is removed.

[0103] Next, as shown in Fig. 11D, additional patterning is performed on the resist to open the resist at positions that will later become the widths of the plurality of third trenches 37. Next, as shown in Fig. 11E, the mask layer 38 in the openings of the resist is removed, leaving a certain thickness. Next, as shown in Fig. 11F, the resist is removed.

[0104] Next, as shown in FIG. 11G, the mask layer 38 and the semiconductor layer 40 are etched using the partially remaining mask layer 38 as a mask. At this time, etching of the semiconductor layer 40 proceeds from the beginning in the areas where the mask layer 38 was completely removed in the process shown in FIG. 11C. On the other hand, in the areas where a thin layer of the mask layer 38 was left in the process shown in FIG. 11E, the mask layer 38 is completely removed first, and then etching of the semiconductor layer 40 directly below it begins. However, at that point, etching of the semiconductor layer 40 has already progressed in the areas where the mask layer 38 was originally completely removed, resulting in trenches of different depths being formed in the semiconductor layer 40. In this manner, the depths of the multiple third trenches 37 are controlled.

[0105] 11H, an insulating film (oxide film) is formed on the inner surfaces of the formed third trenches 37. At this time, the oxide film formed on the bottom and lower side surfaces of the third trenches 37 is the shield insulating film 26. Next, as shown in FIG. 11I, the interiors of the third trenches 37 are filled with a conductive material, such as polysilicon, and then a certain amount of etching is performed to adjust the polysilicon to remain only on the lower sides of the interiors of the third trenches 37. The remaining polysilicon is the shield conductor 25.

[0106] Next, as shown in Fig. 11J, an intermediate insulating film 36 is formed on the upper surface of the shield conductor 25. Next, as shown in Fig. 11K, polysilicon is again filled in, and then a certain amount of etching is performed. At this time, the gate conductor 15 is formed.

[0107] The subsequent steps are omitted because they are the same as the manufacturing method ( FIG. 5L and subsequent steps) described in embodiment 1. In the manufacturing process of semiconductor device 1B of embodiment 2, details of the formation of source region 14 included in semiconductor layer 40, and the implantation of impurities into gate conductor 15, shield conductor 25, and the like, and heat treatment have been omitted, but these steps can be performed at any of the steps shown in FIGS.

[0108] [3. Consideration] The following describes the effects achieved by the semiconductor device 1B according to the second embodiment.

[0109] Like the transistor 10 according to the first embodiment, the transistor 10B also includes a shield conductor 25 that reaches a position deeper than the intermediate insulating film 36. In particular, the relatively deep portion of the third trench 37 physically pushes down the expansion of the depletion layer, thereby reducing the electric field strength generated near the gate conductor 15 and the intermediate insulating film 36. Furthermore, because the buried shield conductor 25 has the same potential as the source electrode 11, it also has the effect of reducing the gate-drain capacitance. Therefore, the transistor 10B has improved breakdown voltage compared to a transistor that does not include the relatively deep portion of the third trench 37.

[0110] The relatively deep portion of the third trench 37 may hereinafter be referred to as a shield trench.

[0111] 9B , the relatively deep portions (shield trenches) of the third trench 37 are disposed at equal intervals W2 in the Y direction in plan view. Furthermore, if there is a relationship of W1<W2, the effect of physically pushing down the expansion of the depletion layer between the nearest shield trenches is almost the same as that of the transistor 10 according to the first embodiment.

[0112] While the effect of improving the breakdown voltage is almost the same, the transistor 10B according to the second embodiment has significantly fewer shield trenches in plan view than the transistor 10 according to the first embodiment. As can be seen from Figures 9B and 9D , in a cross-sectional view of the XZ plane, the third trench 37 does not reach the depth D2 in most parts along the Y direction. Therefore, there is almost no obstruction in the low-concentration impurity layer 33 and the semiconductor substrate 32 from spreading in the X direction toward the drain electrode 30 via the tip of the adjacent gate conductor 15.

[0113] Therefore, the transistor 10B according to the second embodiment can achieve an effect of further reducing the conduction resistance when a current passes through the low-concentration impurity layer 33 and the semiconductor substrate 32, compared to the transistor 10 according to the first embodiment. This is even clearer when Fig. 9D is compared with Fig. 7A showing the transistor 10 according to the first embodiment.

[0114] Furthermore, similar to the second trenches 27 (FIG. 2B) in the transistor 10 according to the first embodiment, the transistor 10B according to the second embodiment is also easy to form in terms of structure, since the gate conductors 15 and the shield conductors 25 embedded in the plurality of third trenches 37 can be easily connected to the gate electrode 19 and the portion 13 of the source electrode 11, respectively, at their terminal ends in the Y direction, as shown in FIG.

[0115] That is, the semiconductor device 1B according to the second embodiment is a semiconductor device 1B including a vertical MOS transistor 10B having: a semiconductor substrate 32 of a first conductivity type; a low-concentration impurity layer 33 of the first conductivity type formed on and in contact with the semiconductor substrate 32 and containing an impurity at a concentration lower than a predetermined concentration of the impurity of the semiconductor substrate 32; a body region 18 of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer 33; a source region 14 of the first conductivity type formed in the body region 18; a source electrode 11 electrically connected to the body region 18 and the source region 14; and a plurality of third trenches 37 formed from an upper surface of the low-concentration impurity layer 33 to a depth extending through the body region 18 to a part of the low-concentration impurity layer 33, having a portion in contact with the source region 14, and extending in a first direction (Y direction) parallel to the upper surface of the low-concentration impurity layer 33. In a second direction perpendicular to the first direction, the plurality of third trenches 37 are arranged at equal intervals W1, a first conductor 15 (gate conductor 15) connected to the gate electrode 19 of the vertical MOS transistor 10B is formed on the upper side of the plurality of third trenches 37, and a second conductor 25 (shield conductor 25) separated from the first conductor 15 and connected to the source electrode 11 is formed on the lower side of the plurality of third trenches 37, the plurality of third trenches 37 periodically have relatively shallow portions and relatively deep portions whose depths from the top surface of the low-concentration impurity layer 33 are different in the first direction, the first conductor 15 has a constant length in a third direction perpendicular to both the first direction and the second direction, and the length of the second conductor 25 in the third direction changes periodically (at intervals W2) in the first direction.

[0116] The effect of improving the breakdown voltage is most effectively achieved when the shield trenches of transistor 10B are arranged so that they correspond to the vertices of an equilateral triangle in plan view. This is because the shield trenches are arranged at equal intervals two-dimensionally in the XY plane, not just in the Y direction. Within the area inside the equilateral triangle, the effect of physically pushing down the expansion of the depletion layer can be enjoyed almost uniformly. Furthermore, equilateral triangles with their vertices at the positions where the shield trenches are arranged in plan view are arranged without gaps within the plane, as shown in Fig. 9B, where a portion of the triangle is virtually shown by the dashed lines, so that the breakdown voltage can be improved uniformly throughout the plane.

[0117] Therefore, in the semiconductor device 1B according to this embodiment 2, in a planar view of the semiconductor layer 40, it is desirable that the three closest relatively deep portions (shield trenches) in a set of adjacent trenches among the plurality of third trenches 37 are arranged so as to correspond to the vertices of an equilateral triangle.

[0118] In the semiconductor device 1B according to the second embodiment, when the interval between the plurality of third trenches 37 in the second direction (X direction) is defined as W1 and the interval between the plurality of third trenches 37 at which relatively deep portions (shield trenches) are formed in the first direction (Y direction) is defined as W2, The following relationship may be established.

[0119] If the above geometric relationship is established, even if the three relatively deep portions (shield trenches) adjacent to each other are not arranged so as to correspond to the vertices of an equilateral triangle, the closest distance between two pairs of three pairs of two points formed by the three shield trenches in plan view can be set to W2 or less, thereby achieving the effect of improving the breakdown voltage of transistor 10B by a certain percentage.

[0120] Third Embodiment Hereinafter, a semiconductor device 1C (transistor 10C) according to a third embodiment will be described, which is obtained by partially modifying the configuration of the semiconductor device 1 (transistor 10) according to the first embodiment.

[0121] Here, for the transistor 10C of embodiment 3, the components that are similar to those of the transistor 10 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from the transistor 10.

[0122] In the transistor 10C according to the third embodiment, the plurality of first trenches 17 extending in the Y direction, as described in the transistor 10 according to the first embodiment, are arranged at equal intervals in the X direction. In addition, the plurality of second trenches 27 are replaced by a plurality of fourth trenches 47, which are modified to extend in a direction perpendicular to the direction in which the plurality of first trenches 17 extend.

[0123] [1. Structure of the Semiconductor Device] Figures 12A, 12B, 12C, and 12D are cross-sectional schematic diagrams showing an example of the structure of a semiconductor device 1C (transistor 10C) according to the third embodiment. Figure 12E is a plan view of the semiconductor device 1C (transistor 10C), with Figure 12A being a cross-section taken along line V-V in Figure 12E, Figure 12B being a cross-section taken along line VI-VI in Figure 12E, Figure 12C being a cross-section taken along line VII-VII in Figure 12E, and Figure 12D being a cross-section taken along line VIII-VIII in Figure 12E. Note that in Figure 12E, a passivation layer 35, an interlayer insulating layer 34, and a source electrode 11 (described later) are shown as if they were transparent, allowing the underlying structure to be seen through.

[0124] The first trenches 17 extend in the Y direction and are arranged in parallel stripes at equal intervals W1 [μm] in the X direction, while the fourth trenches 47 extend in the X direction and are arranged in parallel stripes at equal intervals W2 [μm] in the Y direction. The interval W2 between the fourth trenches 47 extending in the X direction may or may not match the repetition period of the connection portions 18 a and the source regions 14. Figures 12C and 12E show the case where the repetition period and W2 match.

[0125] The plurality of first trenches 17 are formed to penetrate from the upper surface of the semiconductor layer 40 through the source region 14 and the body region 18, and reach a depth D1 [μm] to a part of the low-concentration impurity layer 33. Similarly, the plurality of fourth trenches 47 are formed to penetrate from the upper surface of the semiconductor layer 40 through the body region 18, and reach a depth D2 [μm] to a part of the low-concentration impurity layer 33. D2 is larger than D1 (D1<D2).

[0126] A gate conductor 15 is buried inside the plurality of first trenches 17 , and a shield conductor 25 is buried inside the plurality of fourth trenches 47 .

[0127] 2. Method for Manufacturing Semiconductor Device An example of a method for manufacturing the transistor 10C according to the third embodiment will be described.

[0128] 13A to 13K are cross-sectional diagrams illustrating a manufacturing process of the transistor 10C. The first and second columns from the left are cross-sectional diagrams in the XZ plane, with the first column being a cross-section taken along V-V in FIG. 12E (with the source region 14 omitted), and the second column being a cross-section taken along VI-VI in FIG. 12E. The third and fourth columns from the left are cross-sectional diagrams in the YZ plane, with the third column being a cross-section taken along VII-VII in FIG. 12E (with the source region 14 omitted), and the fourth column being a cross-section taken along VIII-VIII in FIG. 12E.

[0129] As in the manufacturing method of Embodiment 1, a mask layer 38 is formed on the upper surface of the semiconductor layer 40 in which the body region 18 is selectively formed, and then the mask layer 38 is partially removed using openings in a resist applied to the mask layer 38. The state at this time is shown in FIG. 13A . The mask layer 38 is removed from a region that extends in the X direction and has a constant interval in the Y direction. In this case, the constant interval is the interval W2 between adjacent fourth trenches 47, which will be described later, and the width of the openings in the mask layer 38 in the Y direction ultimately becomes the width of the fourth trench 47.

[0130] Next, the resist is removed, and as shown in Fig. 13B, the semiconductor layer 40 is etched using the partially remaining mask layer 38 as a mask. By performing the etching process shown in Fig. 13B, a plurality of fourth trenches 47 extending in the X direction are formed in the semiconductor layer 40 to a depth of D2 [μm] from the top surface of the semiconductor layer 40.

[0131] Next, as shown in Fig. 13C, an insulating film (oxide film) is formed on the inner surfaces of the plurality of fourth trenches 47. The insulating film formed here is the shield insulating film 26 of the plurality of fourth trenches 47. At this time, the mask layer 38 may remain, but after forming the shield insulating film 26, the mask layer 38 is removed so that the top surface of the semiconductor layer 40 is just exposed. Fig. 13C shows the state at this time. Typically, the mask layer 38 and the shield insulating film 26 are made of the same oxide.

[0132] Next, as shown in FIG. 13D, the insides of the fourth trenches 47 are filled with a conductive material, such as polysilicon.

[0133] Next, the polysilicon is etched until the top surface of the semiconductor layer 40 is exposed. At this time, it is desirable that the top surface of the polysilicon filled inside the fourth trenches 47 is flush with the top surface of the semiconductor layer 40. The polysilicon remaining inside the fourth trenches 47 is the shield conductor 25. After the shield conductor 25 is formed inside the fourth trenches 47, a mask layer 38 is formed on the semiconductor layer 40 and the shield conductor 25. Figure 13E shows the state at this time.

[0134] 13F, the mask layer 38 is removed using openings in the resist applied to the mask layer 38. The mask layer 38 is removed in regions that extend in the Y direction and have a fixed interval in the X direction. In this case, the fixed interval is the interval W1 between adjacent first trenches 17, which will be described later, and the width of the openings in the mask layer 38 in the X direction will ultimately be the width of the first trenches 17.

[0135] 13G, the semiconductor layer 40 is etched using the partially remaining mask layer 38 as a mask. By performing the etching process shown in Fig. 13G, a plurality of first trenches 17 extending in the Y direction are formed in the semiconductor layer 40 to a depth of D1 [μm] from the top surface of the semiconductor layer 40.

[0136] 13H, an insulating film (oxide film) is formed on the inner surfaces of the plurality of first trenches 17. The insulating film formed here is the gate insulating film 16 of the plurality of first trenches 17. At this time, the mask layer 38 may remain. Typically, the mask layer 38 and the gate insulating film 16 are made of the same oxide.

[0137] Next, as shown in FIG. 13I, the inside of the first trenches 17 is filled with a conductive material, for example, polysilicon.

[0138] 13J, the polysilicon is etched so that it does not remain on the top surface of the semiconductor layer 40. The polysilicon remaining inside the plurality of first trenches 17 is the gate conductor 15.

[0139] Next, as shown in FIG. 13K, an oxide film is formed on the upper surface of the semiconductor layer 40 to form the interlayer insulating layer 34 .

[0140] The subsequent steps are the same as those in the manufacturing method described in the first embodiment (after FIG. 5L), and therefore will not be described again.

[0141] In the manufacturing process of the semiconductor device 1C of embodiment 3, details of the formation of the source region 14 included in the semiconductor layer 40, and the impurity injection and heat treatment into the gate conductor 15, the shield conductor 25, and the like are omitted, but these can be performed at any of the steps shown in Figures 13A to 13K.

[0142] The width of the first trench 17 and the width of the fourth trench 47, or the spacing between the first trenches 17, the spacing between the fourth trenches 47, and the spacing between the first trench 17 and the fourth trench 47, etc. can be freely designed by controlling the dimensions for patterning the resist.

[0143] [3. Discussion] The following describes the effects achieved by the semiconductor device 1C according to the third embodiment.

[0144] In the transistor 10C, the first trench 17 is referred to as a gate trench 17, and the fourth trench 47 is referred to as a shield trench 47.

[0145] The multiple shield trenches 47 reach a position (D2) deeper than the multiple gate trenches 17 and physically push down the expansion of the depletion layer, thereby reducing the electric field strength generated near the tips of the multiple gate trenches 17. In addition, since the buried shield conductor 25 has the same potential as the source electrode 11, it also has the effect of reducing the gate-drain capacitance. Therefore, the breakdown voltage of the transistor 10C can be improved compared to when the multiple shield trenches 47 are not provided.

[0146] 12C, 12D, and 12E, the shield trenches 47 are arranged in a striped pattern at equal intervals W2. Therefore, the effect of physically pushing down the expansion of the depletion layer by the shield trenches 47 is the same as that of the transistor 10 according to the first embodiment.

[0147] However, the multiple shield trenches 47 of the transistor 10C according to the third embodiment extend in the X direction. That is, they are arranged perpendicular to the direction in which the multiple gate trenches 17 extend. Therefore, there is almost no obstruction in the low-concentration impurity layer 33 and the semiconductor substrate 32 from spreading and flowing in the X direction when the current attempts to escape to the drain electrode 30 side via the tips of the multiple gate trenches 17.

[0148] 12A , which shows the transistor 10 according to the first embodiment, it is clear that the transistor 10C according to the third embodiment does not appear to have multiple shield trenches 47 at most positions in the cross-sectional view taken along the XZ plane. Therefore, the transistor 10C according to the third embodiment can achieve the effect of lowering the conduction resistance when a current passes through the low-concentration impurity layer 33 and the semiconductor substrate 32 compared to the transistor 10 according to the first embodiment.

[0149] That is, the semiconductor device 1C according to the third embodiment includes a semiconductor substrate 32 of a first conductivity type, a low-concentration impurity layer 33 of the first conductivity type formed on and in contact with the semiconductor substrate 32 and containing an impurity at a concentration lower than a predetermined concentration of the impurity of the semiconductor substrate 32, a body region 18 of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer 33, a source region 14 of the first conductivity type formed in the body region 18, a source electrode 11 electrically connected to the body region 18 and the source region 14, and a plurality of source electrodes 11 formed at a depth from an upper surface of the low-concentration impurity layer 33 to a part of the low-concentration impurity layer 33, which penetrate the body region 18 and have a portion in contact with the source region 14 and extend in a first direction (Y direction) parallel to the upper surface of the low-concentration impurity layer 33. The semiconductor device 1C includes a vertical MOS transistor 10C having a first trench (gate trench) 17 and a plurality of fourth trenches (shield trenches) 47 that are formed from an upper surface of a low-concentration impurity layer 33, penetrate through a body region 18, and are deeper than the first trenches 17, and extend in a second direction (X direction) that is parallel to the upper surface of the low-concentration impurity layer 33 and perpendicular to the first direction, wherein a first conductor 15 (gate conductor 15) connected to a gate electrode 19 of the vertical MOS transistor 10C is formed inside the plurality of first trenches 17, and a second conductor 25 (shield conductor 25) connected to a source electrode 11 is formed inside the plurality of fourth trenches 47.

[0150] Note that, if the interval W1 between the multiple first trenches (gate trenches) 17 is reduced, the total gate width increases, and the conduction resistance when passing through the body region 18 (conduction channel) decreases. For this reason, it is preferable to make W1 as small as possible.

[0151] On the other hand, if the interval W2 between the multiple shield trenches 47 is too narrow, the current attempting to escape to the drain electrode 30 side via the tips of the multiple gate trenches 17 will be hindered from spreading in the X direction in the low-concentration impurity layer 33 and the semiconductor substrate 32. Therefore, as a guideline, it is desirable that the interval W2 between the multiple shield trenches 47 be larger than the interval W1 between the multiple gate trenches 17.

[0152] Therefore, it is desirable that the multiple first trenches (gate trenches) 17 are arranged at equal intervals W1 in the second direction (X direction), the multiple fourth trenches (shield trenches) 47 are arranged at equal intervals W2 in the first direction (Y direction), and the interval W1 between the multiple first trenches 17 in the second direction is smaller than the interval W2 between the multiple fourth trenches 47 in the first direction (W1<W2).

[0153] Furthermore, the plurality of first trenches (gate trenches) 17 and the plurality of fourth trenches (shield trenches) 47 can be easily connected to the gate electrode 19 or the source electrode 11 at their respective ends.

[0154] 14A, the gate conductor 15 embedded in the first trenches 17 is connected to the gate electrode 19 at its end in the Y direction. Similarly, as shown in FIG. 14B, the shield conductor 25 embedded in the fourth trenches 47 can be connected to the source electrode 11 at its end in the X direction. Therefore, the structure according to the third embodiment is advantageous in that it allows easy connection with an electrode.

[0155] As a modification of the third embodiment, the plurality of fourth trenches 47 of the transistor 10C may be replaced with the plurality of second trenches 27 (split type with a gate conductor 15 provided at the top) described in the first embodiment. In other words, this structure is the same as the structure of the transistor 10 according to the first embodiment, in which the direction in which the plurality of second trenches 27 extend is changed, the second trenches 27 extend in a direction (X direction) perpendicular to the plurality of first trenches 17, and are arranged at equal intervals W2 in the Y direction, and the plurality of first trenches 17 are arranged at equal intervals W1.

[0156] In the structure of the above modification, the plurality of first trenches 17 and the plurality of second trenches 27 are arranged in a lattice pattern in a plan view, and both contribute to the conduction of the body region 18. Since the total gate width is significantly increased, the effect of significantly reducing the conduction resistance can be obtained.

[0157] The current that attempts to escape to the drain electrode 30 side via the vicinity of the gate conductor 15 at the top of the plurality of second trenches 27 is hardly able to spread and flow in the Y direction in the low-concentration impurity layer 33 and the semiconductor substrate 32, but the current that attempts to escape to the drain electrode 30 side via the tips of the plurality of first trenches (gate trenches) 17 is hardly hindered from spreading and flowing in the X direction in the low-concentration impurity layer 33 and the semiconductor substrate 32. Therefore, the conduction resistance of the current flowing through the low-concentration impurity layer 33 and the semiconductor substrate 32 can be reduced.

[0158] While the semiconductor device according to one aspect of the present disclosure has been described above based on the first to third embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the spirit of the present disclosure, various modifications that would occur to a person skilled in the art to these embodiments and configurations constructed by combining components of different embodiments and modifications may also be included within the scope of one or more aspects of the present disclosure.

[0159] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path.

[0160] 1, 1A, 1B, 1C Semiconductor device 2 Power supply 3 Load 10, 10A, 10B, 10C Transistor (first vertical MOS transistor) 11 Source electrode 12, 13 Portion 14 Source region 15 Gate conductor (first conductor) 16 Gate insulating film 17 First trench (gate trench) 18 Body region 18a Connection portion 19 Gate electrode 25 Shield conductor (second conductor) 26 Shield insulating film 27 Second trench (shield trench) 30 Metal layer (drain electrode) 32 Semiconductor substrate 33 Lightly doped layer (drift layer) 34 Interlayer insulating layer 35 Passivation layer 36 Intermediate insulating film 37 Third trench 38 Mask layer 40 Semiconductor layer 47 Fourth trench (shield trench) 111 Source pad 119 Gate pad

Claims

1. a semiconductor substrate of a first conductivity type; a low-concentration impurity layer of the first conductivity type formed on and in contact with the semiconductor substrate and containing an impurity at a concentration lower than a predetermined impurity concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type formed in the low concentration impurity layer; a source region of the first conductivity type formed in the body region; a source electrode electrically connected to the body region and the source region; a plurality of first trenches formed to a depth from an upper surface of the lightly doped impurity layer through the body region to a portion of the lightly doped impurity layer, the first trenches having a portion in contact with the source region and extending in a first direction parallel to the upper surface of the lightly doped impurity layer; a plurality of second trenches extending in the first direction, the second trenches being formed deeper than the plurality of first trenches from an upper surface of the lightly doped impurity layer through the body region and having a portion in contact with the source region; A semiconductor device including a vertical MOS transistor having the first trenches and the second trenches are alternately arranged in a second direction that is parallel to an upper surface of the low concentration impurity layer and perpendicular to the first direction; a first conductor connected to a gate electrode of the vertical MOS transistor is formed inside the first trenches and on an upper side of the second trenches; a second conductor is formed on a lower side of the second trenches, the second conductor being separated from the first conductor and connected to the source electrode; a spacing between the second conductors in the second direction is twice the spacing between the first conductors in the second direction; A midpoint of the closest distance between a pair of the first conductors adjacent in the second direction is closer to the first trench than a midpoint of the distance between the first conductors adjacent in the second direction. Semiconductor device.

2. In a third direction perpendicular to the first direction and the second direction, an insulating film is provided inside the second trenches to separate the first conductor from the second conductor at the same position as the depth of the first trenches. The semiconductor device according to claim 1 .

3. a semiconductor substrate of a first conductivity type; a low-concentration impurity layer formed on and in contact with the semiconductor substrate and containing an impurity at a concentration lower than a predetermined impurity concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type formed in the low concentration impurity layer; a source region of the first conductivity type formed in the body region; a source electrode electrically connected to the body region and the source region; a plurality of trenches formed to a depth from an upper surface of the lightly doped impurity layer through the body region to a portion of the lightly doped impurity layer, the trenches having a portion in contact with the source region, and extending in a first direction parallel to the upper surface of the lightly doped impurity layer; A semiconductor device including a vertical MOS transistor having the plurality of trenches are disposed at equal intervals in a second direction that is parallel to an upper surface of the low concentration impurity layer and perpendicular to the first direction; a first conductor connected to a gate electrode of the vertical MOS transistor is formed on an upper side inside the plurality of trenches; a second conductor is formed on a lower side inside the plurality of trenches, the second conductor being separated from the first conductor and connected to the source electrode; In the first direction, the plurality of trenches periodically have relatively shallow portions and relatively deep portions from an upper surface of the low concentration impurity layer, In the first direction, the first conductor has a constant length in a third direction perpendicular to both the first direction and the second direction; In the first direction, the second conductor has a length that changes periodically in the third direction. Semiconductor device.

4. When the interval between the plurality of trenches in the second direction is W1 and the interval at which the relatively deep portions of the plurality of trenches are formed in the first direction is W2, [0010] The relationship is The semiconductor device according to claim 3 .

5. In a plan view of the semiconductor substrate, the three closest relatively deep portions of a pair of adjacent trenches among the plurality of trenches are arranged so as to correspond to vertices of an equilateral triangle. The semiconductor device according to claim 3 .

6. a semiconductor substrate of a first conductivity type; a low-concentration impurity layer of the first conductivity type formed on and in contact with the semiconductor substrate and containing an impurity at a concentration lower than a predetermined impurity concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type formed in the low concentration impurity layer; a source region of the first conductivity type formed in the body region; a source electrode electrically connected to the body region and the source region; a plurality of first trenches formed to a depth from an upper surface of the lightly doped impurity layer through the body region to a portion of the lightly doped impurity layer, the first trenches having a portion in contact with the source region and extending in a first direction parallel to the upper surface of the lightly doped impurity layer; a plurality of second trenches formed from an upper surface of the low concentration impurity layer through the body region to be deeper than the plurality of first trenches, the second trenches extending in a second direction parallel to the upper surface of the low concentration impurity layer and perpendicular to the first direction; A semiconductor device including a vertical MOS transistor having a first conductor connected to a gate electrode of the vertical MOS transistor is formed inside the first trenches; a second conductor connected to the source electrode is formed inside the second trenches; In a plan view of the low concentration impurity layer, the source regions are periodically and repeatedly arranged in the first direction on an upper surface of the low concentration impurity layer, In the first direction, the period at which the source regions are arranged is synchronized with the interval between the second trenches. Semiconductor device.

7. the first trenches are equally spaced apart in the second direction; the second trenches are equally spaced apart in the first direction; The spacing between the first trenches in the second direction is smaller than the spacing between the second trenches in the first direction. The semiconductor device according to claim 6.

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