Semiconductor device and power conversion device

Abstract

The purpose is to provide an art capable of improving reliability of a semiconductor device during an operation. When a first heat generation amount on an inverse region side located on a side opposite to an active region with respect to a gate electrode is larger than a second heat generation amount on the active region side, a dimension of a first part on the inverse region side of the gate electrode in an interlayer insulation film is larger than the dimension of a second part on the active region side of the gate electrode in the interlayer insulation film, and when the second heat generation amount is larger than the first heat generation amount, the dimension of the second part is larger than the dimension of the first part.

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

[0002] To enable semiconductor devices to have higher breakdown voltages, lower loss, and be used in high-temperature environments, silicon carbide (SiC), which has superior breakdown voltage, low resistance, and heat resistance compared to silicon (Si), is being applied to power semiconductor devices. Known power semiconductor devices include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). For example, a SiC MOSFET with a breakdown voltage of 1 to 1.2 kV has a resistance of 2 mΩcm. ２ The on-resistance of a SiC semiconductor device can be significantly reduced compared to a Si semiconductor device because the SiC semiconductor device has a high breakdown field, the breakdown voltage layer (i.e., the drift layer) for achieving the same breakdown voltage can be made thinner compared to a Si semiconductor device, and the impurity doping amount of the breakdown voltage layer can be increased.

[0003] Increasing the current density flowing through a semiconductor device can reduce the size of the semiconductor device, and using a parasitic diode in a MOSFET can reduce the manufacturing cost of the semiconductor device. For these reasons, it is expected that SiC semiconductor devices will become mainstream in inverter components in the future.

[0004] However, when a forward current, i.e., a bipolar current, continues to flow through a SiC PN diode, the recombination energy increases when minority carriers injected by the current flow through the PN diode recombine with majority carriers. As a result, stacking faults, which are planar defects, expand, starting from basal plane dislocations and other defects present in the SiC substrate. When stacking faults expand, the current decreases and the forward voltage increases, i.e., the forward voltage shifts, causing a reliability problem that reduces the reliability of the semiconductor device.

[0005] In order to suppress the deterioration of reliability due to the flow of a forward current through the parasitic PN diode as described above, various techniques have been proposed. For example, Patent Document 1 discloses a semiconductor substrate including an n-type SiC substrate and an epitaxial growth layer on the SiC substrate, in which a p-type hole extraction region is formed so as to surround an active region in which a MOSFET is provided. ＋ Furthermore, Patent Documents 2 and 3 propose incorporating a Schottky Barrier Diode (SBD) as a unipolar diode in the same semiconductor chip as a MOSFET.

[0006] JP 2019-75411 A Japanese Patent No. 7078226 A Japanese Patent No. 7170781 A

[0007] However, as semiconductor devices become smaller and more efficient, the current density increases when current is passed through the semiconductor device, causing the temperature to rise during operation. This temperature rise causes thermal stress, which makes the gate electrodes provided in the termination region more susceptible to damage, resulting in a problem of impaired reliability of the semiconductor device.

[0008] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can improve the reliability of a semiconductor device during operation.

[0009] The semiconductor device according to the present disclosure is a semiconductor device having an active region and a termination region defined therein, comprising a first interlayer insulating film provided in the termination region and a gate electrode provided on the first interlayer insulating film, wherein when a first amount of heat generated on the reverse region side, which is located on the opposite side of the gate electrode from the active region, is greater than a second amount of heat generated on the active region side, a dimension of a first portion of the first interlayer insulating film on the reverse region side of the gate electrode is greater than a dimension of a second portion of the first interlayer insulating film on the active region side of the gate electrode, and when the second amount of heat generated is greater than the first amount of heat generated, a dimension of the second portion is greater than a dimension of the first portion.

[0010] According to the present disclosure, when the first heat generation amount is greater than the second heat generation amount, the dimension of the first portion is greater than the dimension of the second portion, and when the second heat generation amount is greater than the first heat generation amount, the dimension of the second portion is greater than the dimension of the first portion. With this configuration, the reliability of the semiconductor device during operation can be improved.

[0011] 1 is a top view showing a configuration of a semiconductor device according to a first embodiment. FIG. 2 is a top view showing a configuration of a semiconductor device according to a first embodiment. FIG. 3 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. FIG. 4 is a flowchart showing a manufacturing method of a semiconductor device according to a first embodiment. FIG. 5 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 7 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 8 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 9 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 10 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 11 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment. FIG. 10 is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to a fourth modification of the first embodiment. FIG. 11 is a top view showing a configuration of a semiconductor device according to a second embodiment. FIG. 12 is a top view showing a configuration of a semiconductor device according to the second embodiment. FIG. 13 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment. FIG. 14 is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 15 is a top view showing a configuration of a semiconductor device according to a fourth embodiment. FIG. 16 is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to the fourth embodiment. FIG. 17 is a flowchart showing a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 18 is a cross-sectional view schematically illustrating a configuration of a semiconductor device according to a first modification of the fourth embodiment. FIG. 19 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fifth embodiment is applied.

[0012] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In the following description, specific positions and directions such as "upper" or "lower" do not necessarily correspond to the positions and directions in actual implementation. A portion having a higher density than another portion means, for example, that the average density of the portion is higher than the average density of the other portion. Conversely, a portion having a lower density than another portion means, for example, that the average density of the portion is lower than the average density of the other portion.

[0013] First Embodiment An example will be described in which a semiconductor device according to the first embodiment is a power semiconductor device, which is made of an n-type SiC substrate and is a planar gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a built-in SBD (Schottky Barrier Diode). However, the semiconductor device is not limited to this, and may be, for example, a trench gate semiconductor device, an IGBT (Insulated Gate Bipolar Transistor), or an RC-IGBT (Reverse Conducting IGBT).

[0014] 1 is a top view showing the configuration of a semiconductor device 1 according to a first embodiment. A source electrode 3 located in the center and a gate wiring 2 surrounding the source electrode 3 are provided on the upper part of the semiconductor device 1. A gate pad 4 is provided between the center and an end of the upper part of the semiconductor device 1 and is electrically connected to the gate wiring 2. The gate wiring 2 and the gate pad 4 are spaced apart from and insulated from the source electrode 3. In this specification, the region where unit cells are periodically arranged is defined as an active region, and the region other than the active region is defined as a termination region.

[0015] 2 is an enlarged top view showing a portion between the active region and the termination region indicated by the dashed dotted line in FIG. 1. In the first embodiment, the active region includes an SBD region 20 in which an SBD is provided, and a MOS region 22 in which a MOSFET is provided. As shown in FIG. 2, the SBD regions 20 are periodically provided in a striped pattern, and the MOS regions 22 are periodically provided in a striped pattern, with the SBD regions 20 and the MOS regions 22 being provided alternately one by one.

[0016] The second interlayer insulating film 5 is provided in a region other than the active region including the plurality of SBD regions 20 and the plurality of MOS regions 22, i.e., in the termination region. The gate wiring 2 and the source electrode 3 are provided on the second interlayer insulating film 5, and the second interlayer insulating film 5 has a gate contact hole 5a covered by the gate wiring 2 and a contact hole 5b covered by the source electrode 3. As will be described later, an SBD is provided below the contact hole 5b in the termination region, similar to the SBD region 20 in the active region.

[0017] Fig. 3 is a cross-sectional view showing the configuration of a portion taken along line a-a' in Fig. 2. As described above, the second interlayer insulating film 5 is provided in the termination region, and therefore Fig. 3 shows the configuration of the termination region in general. Since line a-a' in Fig. 2 crosses over the contact hole 5b in the second interlayer insulating film 5, Fig. 3 shows the second interlayer insulating film 5 at two locations on either side of the contact hole 5b.

[0018] As shown in FIG. 3 , the semiconductor device 1 according to the first embodiment includes, in a termination region, an n-type SiC substrate 13, an n-type epitaxial growth layer 12, an n-type well region 11, a p-type well region 15, a p-type potential fixed layer 10, an n-type source region 16, a contact region 9, a first interlayer insulating film 7, a gate electrode 6, a second interlayer insulating film 5, a barrier metal layer 8, a source electrode 3, a gate wiring 2, and a drain electrode 14.

[0019] The epitaxial growth layer 12 is uniformly provided on a first main surface (top surface in FIG. 3 ) of the SiC substrate 13, and the n-type well region 11 is provided on the epitaxial growth layer 12. In the first embodiment, the portion including the SiC substrate 13, the epitaxial growth layer 12, and the n-type well region 11 is a combination of the SiC substrate and the epitaxial growth layer, but it may be the SiC substrate alone or the epitaxial growth layer alone.

[0020] The p-type well region 15 is selectively provided above the n-type well region 11. The sides and bottom of the potential fixed layer 10 are provided so as to be covered with the p-type well region 15, and the sides and bottom of the source region 16 are provided so as to be covered with the p-type well region 15.

[0021] The first interlayer insulating film 7 is selectively provided on the potential fixed layer 10, the n-type well region 11, the p-type well region 15, and the source region 16 in the termination region. The first interlayer insulating film 7 has contact holes 5b, similar to the second interlayer insulating film 5, and therefore, in FIG. 3, the first interlayer insulating film 7 is shown in two locations, similar to the second interlayer insulating film 5.

[0022] The gate electrode 6 is provided on a first interlayer insulating film 7. In the following description, of the two first interlayer insulating films 7 shown in FIG. 3 , the region located on the opposite side of the active region with respect to the gate electrode 6 provided on the first interlayer insulating film 7 on the active region side will be referred to as an opposite region.

[0023] The gate electrode 6 is electrically connected to a gate electrode (not shown) provided in the MOS region 22 in Fig. 2 and is at the same potential as the gate electrode in the MOS region 22. When a voltage equal to or greater than the threshold voltage is applied to the gate electrode in the MOS region 22, the conductivity type of a portion of the p-type semiconductor layer sandwiched between the n-type semiconductor layers is inverted, and a channel is formed in that portion. Since the configuration in Fig. 3 is not a MOS region 22, the gate electrode 6 in Fig. 3 indirectly forms a channel in the p-type semiconductor layer in the MOS region, but does not directly form a channel in the p-type semiconductor layer in Fig. 3.

[0024] The second interlayer insulating film 5 is provided so as to cover the gate electrode 6 and the first interlayer insulating film 7. The second interlayer insulating film 5 has a gate contact hole 5a that partially exposes the gate electrode 6 provided on the first interlayer insulating film 7 on the reverse region side, and a contact hole 5b that partially exposes the n-type well region 11 in the termination region.

[0025] The barrier metal layer 8 covers the potential fixed layer 10, the n-type well region 11, the p-type well region 15, the source region 16, the second interlayer insulating film 5, and the gate electrode 6 exposed from the gate contact hole 5 a. The barrier metal layer 8 covering the gate electrode 6 is separated and insulated from the barrier metal layer 8 covering the n-type well region 11 and the like.

[0026] The contact region 9 is provided between the barrier metal layer 8 and one of the source region 16, the p-type well region 15, and the potential fixing layer 10 provided closer to the active region than the first interlayer insulating film 7, and provides an ohmic connection between them.

[0027] On the other hand, no contact region 9 is provided between the n-type well region 11 in the contact hole 5b and the barrier metal layer 8, and the n-type well region 11 is Schottky-connected to the barrier metal layer 8. As a result, an SBD is provided below the contact hole 5b, similar to the SBD region 20 in the active region of FIG.

[0028] The gate wiring 2 is electrically connected to the gate electrode 6 via a barrier metal layer 8 that covers the gate electrode 6 exposed from the gate contact hole 5 a. The source electrode 3 is electrically connected to the n-type well region 11 and the like via the barrier metal layer 8 that covers the n-type well region 11 and the like. The drain electrode 14 is provided on a second main surface (the lower surface in FIG. 3 ) of the SiC substrate 13 that is opposite to the first main surface on which the epitaxial growth layer 12 is provided.

[0029] Here, the SBD provided in the SBD region 20 in the active region and the SBD provided below the contact hole 5b on the reverse region side generate heat during operation. In the first embodiment, a first amount of heat generated on the reverse region side is configured to be larger than a second amount of heat generated on the active region side. Regarding the first interlayer insulating film 7 on the active region side, which is an interlayer insulating film, the dimension of a first portion of the first interlayer insulating film 7 on the reverse region side of the gate electrode 6 is larger than the dimension of a second portion of the first interlayer insulating film 7 on the active region side of the gate electrode 6. As an example, when the distance between the end of the upper portion of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side is D1 and the distance between the end of the upper portion of the second portion on the active region side and the end of the gate electrode 6 on the active region side is D2, the gate electrode 6 is biased toward the active region side with respect to the first interlayer insulating film 7 so that D1 > 0, D2 > 0, and D1 - D2 > 0 are satisfied. This will be described in detail later.

[0030] 4 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment 1. Each of the steps from the semiconductor substrate preparation step S1 to the drain electrode formation step S13 will be described below.

[0031] First, in a semiconductor substrate preparation step S1, an epitaxial growth layer 12 made of n-type SiC is formed by CVD (Chemical Vapor Deposition) on a first main surface of an n-type SiC substrate 13 having a polytype of 4H, as shown in FIG. 5. The n-type impurity concentration of the epitaxial growth layer 12 is, for example, 1×10 １５ cm －３ From 1 x 10 １７ cm －３ The thickness of the epitaxial growth layer 12 is, for example, 5 μm to 50 μm.

[0032] 6, in the n-type well region formation step S2, impurities are ion-implanted into the upper part of the epitaxial growth layer 12 to form the n-type well region 11. The impurity concentration of the n-type well region 11 is higher than the impurity concentration of the epitaxial growth layer 12.

[0033] 7, an implantation mask is formed in a predetermined region of the n-type well region 11 using a photoresist or the like, and then p-type impurities are ion-implanted to form the p-type well region 15. The p-type impurities are, for example, B (boron) and Al (aluminum). The implantation depth of the p-type well region 15 is shallower than the depth of the n-type well region 11. The impurity concentration of the p-type well region 15 is, for example, 1×10 １７ cm －３ From 1 x 10 １９ cm －３ is.

[0034] 8 , an implantation mask is formed using photoresist or the like in a predetermined region of the p-type well region 15, and then n-type impurities are ion-implanted to form the source region 16. The n-type impurities are, for example, phosphorus and nitrogen. The implantation depth of the source region 16 is shallower than that of the p-type well region 15.

[0035] Next, in the potential fixed layer formation step S5, as shown in Fig. 9, an implantation mask is formed using photoresist or the like in a predetermined region of the p-type well region 15, and then p-type impurities are ion-implanted to form the potential fixed layer 10. The impurity concentration of the potential fixed layer 10 is higher than the impurity concentration of the p-type well region 15. Thereafter, the structure obtained in the step of Fig. 9 is annealed in a heat treatment device in an inert gas atmosphere such as Ar (argon) gas at a temperature of 1300 to 1900°C for 30 seconds to 1 hour. This annealing electrically activates the implanted p-type and n-type impurities.

[0036] Then, in a first interlayer insulating film forming step S6, an insulating film that will become the first interlayer insulating film 7 is formed using a CVD method, and then the insulating film is patterned using photolithography and dry or wet etching. As a result, as shown in Fig. 10, the first interlayer insulating film 7 is formed, remaining in predetermined regions on the potential fixed layer 10, the n-type well region 11, the p-type well region 15, and the source region 16. The material of the first interlayer insulating film 7 is, for example, TEOS (Tetra Ethoxy Silane).

[0037] Subsequently, in a gate oxide film forming step S7, a gate oxide film (not shown) is formed in the active region.

[0038] Next, in the gate electrode formation step S8, a conductive film is deposited on the first interlayer insulating film 7 or the like by thermal oxidation or CVD, and then the conductive film is patterned using photolithography and dry or wet etching. As a result, as shown in FIG. 11 , a gate electrode 6 is formed having a portion that is unevenly distributed on the active region side of the first interlayer insulating film 7. The material of the conductive film that becomes the gate electrode 6 may be, for example, polycrystalline Si or polysilicon deposited by chemical vapor deposition or the like, or, when higher speed operation is required in the semiconductor device 1, tungsten or tungsten silicide (WSi ｘ ) may also be used.

[0039] Then, in a second interlayer insulating film forming step S9, an insulating film that will become the second interlayer insulating film 5 is formed using a CVD method, and then the insulating film is patterned using photolithography and dry or wet etching. As a result, as shown in Fig. 12, the second interlayer insulating film 5 that covers the gate electrode 6 and the first interlayer insulating film 7 and has gate contact holes 5a and contact holes 5b is formed. The material of the second interlayer insulating film 5 is, for example, TEOS (tetra ethoxy silane) and BPSG (boro-phospho silicate glass).

[0040] 13, in a contact region formation step S10, the contact region 9 is formed as shown in Fig. 13. The contact region 9 is a silicide layer formed by depositing a metal film containing Ni (nickel) as a main component in an opening of a photoresist or the like, and performing a heat treatment at a temperature in the range of 600°C to 1100°C.

[0041] 14, a barrier metal layer 8 made of titanium or a titanium compound such as titanium nitride (TiN) is formed. Then, a film of aluminum, an aluminum alloy made of aluminum and silicon, or nickel is formed to form the gate wiring 2 and the source electrode 3.

[0042] Then, in the SiC substrate thinning step S12, as shown in FIG. 15 , the second main surface of the SiC substrate 13 is machined using a grinding wheel to thin the SiC substrate 13.

[0043] Next, in the drain electrode formation step S13, as shown in FIG. 16 , a nickel film, for example, approximately 600 nm thick, is formed on the machined second main surface by appropriately using a sputtering method or the like to form the drain electrode 14. Note that oxidation of the outermost surface of the nickel film reduces the wettability of the solder alloy to the nickel film, deteriorating the bonding condition during chip bonding. For this reason, a protective film containing a metal with poor external reactivity, such as gold (Au) or silver (Ag), may be formed on the surface of the nickel film. In other words, the drain electrode 14 may be a laminated film consisting of a nickel film and a protective film.

[0044] Summary of First Embodiment In semiconductor devices such as power semiconductor devices, current typically flows through the BD (body diode) region and the SBD region during reflux operation, causing the semiconductor device itself to generate heat due to these resistance components. In semiconductor devices in which a region for flowing current during reflux operation is provided in the termination region, heat is also generated in the termination region. In particular, in semiconductor devices in which current during reflux is actively flowed to the SBD below contact hole 5b in the termination region, as in the semiconductor device according to the first embodiment, the amount of heat generated in the termination region is relatively large.

[0045] Here, the linear expansion coefficients of the first interlayer insulating film 7 and the second interlayer insulating film 5 differ from the linear expansion coefficient of the source electrode 3, and therefore thermal stress resulting from these is generated at the interface between each interlayer insulating film and the source electrode 3. This thermal stress deteriorates each interlayer insulating film, reducing the insulating performance of each interlayer insulating film and damaging the gate electrode 6 in the termination region, resulting in problems with the semiconductor device.

[0046] Furthermore, in a configuration in which a semiconductor device is assembled into a power module or a discrete package, the semiconductor device is generally sealed with a sealing material such as resin or gel. Since the thermal expansion coefficient of the semiconductor device and the linear expansion coefficient of the sealing material in contact with the semiconductor device are different from each other, the thermal stress resulting from these causes the same problems as those described above.

[0047] Therefore, in this embodiment 1, when the first heat generation amount on the reverse region side is larger than the second heat generation amount on the active region side, the dimension of the first portion of the first interlayer insulating film 7 on the reverse region side of the gate electrode 6 is larger than the dimension of the second portion of the first interlayer insulating film 7 on the active region side of the gate electrode 6.

[0048] As an example, as shown in the schematic diagram of FIG. 17 , when the distance between the end of the upper portion of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side is D1, and the distance between the end of the upper portion of the second portion on the active region side and the end of the gate electrode 6 on the active region side is D2, the gate electrode 6 is unevenly distributed toward the active region side with respect to the first interlayer insulating film 7 so that D1 > 0, D2 > 0, and D1 - D2 > 0 are satisfied. The SEM photograph of FIG. 17 shows a scanning electron microscope (SEM) image of a semiconductor device manufactured by the manufacturing method according to the first embodiment. In the semiconductor device in the SEM photograph, D1 is approximately 1 μm and D2 is approximately 0.5 μm.

[0049] 18 is a diagram showing the results of trial calculation of the thermal stress applied to the gate electrode 6 in the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment, in which D1-D2>0, is able to reduce the thermal stress applied to the gate electrode 6 by about 30% compared to the semiconductor device (comparison example) in which D2-D1>0. Therefore, according to the semiconductor device according to the first embodiment, the thermal stress applied to the gate electrode 6 can be reduced and damage to the gate electrode 6 can be suppressed, thereby improving the reliability of the semiconductor device during operation.

[0050] In particular, in wide bandgap semiconductor devices that are being made smaller and more efficient by taking advantage of the high breakdown field of wide bandgap semiconductors, the temperature rise during operation is large, so it is effective to improve the reliability of the semiconductor device as described above. Wide bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), and diamond.

[0051] <Modification 1> FIG. 19 is a cross-sectional view illustrating a semiconductor device according to Modification 1 of Embodiment 1. D3 and D4 are illustrated in FIG. 19 . D3 is the distance between the end of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side in a plan view. D4 is the distance between the end of the second portion on the active region side and the end of the gate electrode 6 on the active region side in a plan view. When the first amount of heat generated on the reverse region side is greater than the second amount of heat generated on the active region side, the gate electrode 6 may be located closer to the active region side with respect to the first interlayer insulating film 7 so that D3 > 0, D4 > 0, and D3 - D4 > 0 are satisfied. Even with this configuration, the reliability of the semiconductor device during operation can be improved, similar to Embodiment 1.

[0052] <Modification 2> The heat generation amounts and dimensions of the first embodiment and modification 1 may be reversed from those described above. That is, when the second heat generation amount on the active region side is greater than the first heat generation amount on the reverse region side, the dimension of a second portion of the first interlayer insulating film 7 closer to the active region than the gate electrode 6 may be greater than the dimension of a first portion of the first interlayer insulating film 7 closer to the reverse region than the gate electrode 6. The gate electrode 6 may be unevenly located on the reverse region side relative to the first interlayer insulating film 7 so that D1 > 0, D2 > 0, D2 - D1 > 0, or D3 > 0, D4 > 0, or D4 - D3 > 0 is satisfied. Even with this configuration, the reliability of the semiconductor device during operation can be improved, as in the first embodiment.

[0053] <Modification 3> In a power semiconductor device, current usually flows through the BD region on the active region side and the SBD region on the reverse region side during reflux operation, and the semiconductor device itself generates heat due to these resistance components. Therefore, if the resistance value of the SBD region on the reverse region side in the power semiconductor device is set to a first resistance value (R1) and the resistance value of the BD region on the active region side is set to a second resistance value (R2), D1 and D2, or D3 and D4, may be set according to the first resistance value (R1) and the second resistance value (R2).

[0054] That is, when the first resistance value (R1) on the reverse region side is larger than the second resistance value (R2) on the active region side, the dimension of a first portion of the first interlayer insulating film 7 on the reverse region side of the gate electrode 6 may be larger than the dimension of a second portion of the first interlayer insulating film 7 on the active region side of the gate electrode 6. Then, the gate electrode 6 may be unevenly distributed toward the active region side with respect to the first interlayer insulating film 7 so that D1>0, D2>0, D1-D2>0, or D3>0, D4>0, D3-D4>0 is satisfied.

[0055] Alternatively, when the second resistance value (R2) on the active region side is larger than the first resistance value (R1) on the reverse region side, the dimension of a second portion of the first interlayer insulating film 7 closer to the active region than the gate electrode 6 may be larger than the dimension of a first portion of the first interlayer insulating film 7 closer to the reverse region than the gate electrode 6. Then, the gate electrode 6 may be unevenly located on the reverse region side with respect to the first interlayer insulating film 7 so that D1>0, D2>0, D2-D1>0, or D3>0, D4>0, D4-D3>0 is satisfied. Even with such a configuration, the reliability of the semiconductor device during operation can be improved, as in the first embodiment.

[0056] 20 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth modification of the first embodiment. As shown in FIG. 20 , a protective film may be provided, including a first protective film 17 covering the source electrode 3 and the gate line 2 and a second protective film 18 covering the first protective film 17. The material of the first protective film 17 is preferably an insulating material or a semi-insulating material, such as SOG (Spin On Glass). The material of the second protective film 18 is preferably an insulating material or a semi-insulating material, such as a polyimide film.

[0057] <Modification 5> In the first embodiment, the semiconductor device 1 is described in which an SBD is provided in the termination region. However, as long as a configuration for passing current during reflux operation is provided in the termination region, an SBD need not be provided in the termination region. For example, a diode such as a PN diode may be provided in the termination region instead of an SBD. Note that the above modifications may also be applied to the second and subsequent embodiments.

[0058] 21 is a top view showing the configuration of a semiconductor device 1 according to a second embodiment. A source electrode 3 and a gate wiring 2 surrounding the source electrode 3 are provided on the upper part of the semiconductor device 1. A gate pad 4 electrically connected to the gate wiring 2 is also provided on a part of the upper part of the semiconductor device 1. The gate wiring 2 and the gate pad 4 are spaced apart from and insulated from the source electrode 3.

[0059] 22 is an enlarged top view of a portion between the active region and the termination region indicated by the dashed-dotted line in FIG. 21 . In the second embodiment, the active region includes not only a plurality of SBD regions 20 and a plurality of MOS regions 22, but also a plurality of BD (body diode) regions 23 periodically arranged in a stripe pattern. A body diode is provided in the BD region 23. In the example of FIG. 22 , the SBD regions 20 and the BD regions 23 are alternately arranged. This makes it possible to reduce the on-resistance in the active region.

[0060] 22, the configuration of the portion along line aa' is the same as the configuration of FIG. 3 described in embodiment 1, and an SBD is provided below contact hole 5b in the termination region. In this second embodiment, as in embodiment 1, gate electrode 6 is unevenly distributed with respect to first interlayer insulating film 7, so that damage to gate electrode 6 in the termination region can be suppressed and the reliability of the semiconductor device during operation can be improved.

[0061] 23 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment. The method for manufacturing a semiconductor device according to the second embodiment is similar to the method in which the thinning step S12 of the SiC substrate is moved to after the semiconductor substrate preparation step S1 in the flowchart of FIG. 4 showing the method for manufacturing a semiconductor device according to the first embodiment. In this way, the manufacturing method may be such that the step S2 of forming the n-type well region 11 and subsequent steps are performed after the SiC substrate 13 is thinned. Note that the semiconductor device according to the first embodiment may also be formed according to the order of steps shown in the flowchart of FIG. 23.

[0062] 1, a source electrode 3 located in the center and a gate wiring 2 surrounding the source electrode 3 are provided on the top of the semiconductor device 1. A gate pad 4 is provided between the center and the end of the top of the semiconductor device 1, and is electrically connected to the gate wiring 2. The gate wiring 2 and the gate pad 4 are spaced apart from and insulated from the source electrode 3.

[0063] The configuration between the active region and the termination region according to the third embodiment is also similar to the configuration of the semiconductor device 1 according to the first embodiment shown in the top view of Fig. 2, and the active region includes an SBD region 20 in which an SBD is provided and a MOS region 22 in which a MOSFET is provided. As shown in Fig. 2, the plurality of SBD regions 20 are periodically provided in a striped pattern, and the plurality of MOS regions 22 are periodically provided in a striped pattern, with the SBD regions 20 and the MOS regions 22 being provided alternately one by one.

[0064] 24 is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment, taken along line a-a' in FIG. 2. As described above, the second interlayer insulating film 5 is provided in the termination region, and therefore FIG. 24 generally shows the configuration of the termination region. Since line a-a' in FIG. 2 crosses over the contact hole 5b in the second interlayer insulating film 5, in FIG. 24, the second interlayer insulating film 5 is shown at two locations on either side of the contact hole 5b.

[0065] Here, the SBD provided in the SBD region 20 of the active region and the SBD provided below the contact hole 5b on the reverse region side generate heat during operation. In the third embodiment, the first heat generation amount on the reverse region side is configured to be greater than the second heat generation amount on the active region side. As a first example of calculating the first heat generation amount and the second heat generation amount, the first heat generation amount and the second heat generation amount may be calculated from the conduction loss value in the on-state of the semiconductor device when current is applied, or the switching loss value of the semiconductor device when switching between the on-state and the off-state. As a second example, the first heat generation amount and the second heat generation amount may be calculated from the temperature distribution inside the semiconductor device based on images captured using an infrared camera. Furthermore, the first heat generation amount and the second heat generation amount may be calculated by combining the first and second examples, and various measurement and analysis methods can be used to calculate the first and second heat generation amounts.

[0066] In the third embodiment, when the thickness of the first interlayer insulating film 7 is defined as h, the distance between the end of the upper part of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side is defined as D1, and the distance between the end of the upper part of the second portion on the active region side and the end of the gate electrode 6 on the active region side is defined as D2, the following holds: D1>0, D2>0, D1-D2>0, and h>min(D1,D2). Note that the value of min(D1,D2) is the smaller of D1 and D2. Here, since D1-D2>0, min(D1,D2)=D2.

[0067] <Manufacturing Method> The semiconductor device according to the third embodiment is manufactured, for example, according to the flowchart shown in Fig. 4. The steps of the third embodiment are generally the same as those of the first embodiment, and therefore detailed description thereof will be omitted. However, in the third embodiment, when forming an insulating film to become the first interlayer insulating film 7 using a CVD method in the first interlayer insulating film forming step S6, an insulating film having a thickness h greater than the smaller of the dimensions of the first portion and the second portion described above is formed.

[0068] Summary of Third Embodiment In the third embodiment, the thickness h of the first interlayer insulating film 7 is larger than the smaller of the dimensions of the first portion and the second portion, so that the thermal stress applied to the gate electrode 6 can be shared not only by the gate electrode 6 but also by the first interlayer insulating film 7. This reduces the thermal stress applied to the gate electrode 6, i.e., leads to suppression of damage to the gate electrode 6, and therefore improves the reliability of the semiconductor device during operation. Note that it is more preferable to make the thickness of the first interlayer insulating film 7 larger than the dimensions of both the first portion and the second portion, because this reduces the thermal stress applied to both ends of the gate electrode 6 from the surroundings.

[0069] 25 is a top view showing the configuration of a semiconductor device according to a fourth embodiment. In this fourth embodiment, a second gate wiring 32 is provided on the gate wiring 2, and a second source electrode 33 is provided on the source electrode 3. The second gate wiring 32 and the second source electrode 33 in Fig. 25 have substantially the same shapes as the gate wiring 2 and the source electrode 3 in Fig. 1.

[0070] The configuration between the active region and the termination region according to the fourth embodiment is also similar to the configuration of the semiconductor device 1 according to the first embodiment shown in the top view of Fig. 2, and the active region includes an SBD region 20 in which an SBD is provided and a MOS region 22 in which a MOSFET is provided. As shown in Fig. 2, the plurality of SBD regions 20 are periodically provided in a striped pattern, and the plurality of MOS regions 22 are periodically provided in a striped pattern, with the SBD regions 20 and the MOS regions 22 being provided alternately one by one.

[0071] 26 is a cross-sectional view showing the configuration of a semiconductor device according to the fourth embodiment, taken along line a-a' in FIG. 2. As described above, the second interlayer insulating film 5 is provided in the termination region, and therefore FIG. 26 generally shows the configuration of the termination region. Since line a-a' in FIG. 2 crosses over the contact hole 5b in the second interlayer insulating film 5, in FIG. 26, the second interlayer insulating film 5 is shown at two locations on either side of the contact hole 5b.

[0072] Here, the SBD provided in the SBD region 20 in the active region and the SBD provided below the contact hole 5b on the reverse region side generate heat during operation. Also in the fourth embodiment, the first amount of heat generated on the reverse region side is configured to be larger than the second amount of heat generated on the active region side.

[0073] In the fourth embodiment, similarly to the first embodiment, the source electrode 3, which is a first electrode, covers the second interlayer insulating film 5. Furthermore, in the fourth embodiment, a second gate wiring 32 is provided on the gate wiring 2, and a second source electrode 33, which is a second electrode, is provided on the source electrode 3. The thermal conductivity of the second source electrode 33 is higher than the thermal conductivity of the semiconductor layer on which the first interlayer insulating film 7 is provided. The semiconductor layer here includes, for example, at least one of the SiC substrate 13, the epitaxial growth layer 12, the n-type well region 11, the p-type well region 15, the potential fixed layer 10, and the source region 16.

[0074] Furthermore, if the distance between the end of the upper part of the first portion on the reverse region side and the end of the gate electrode 6 on the reverse region side is defined as D1, the distance between the end of the upper part of the second portion on the active region side and the end of the gate electrode 6 on the active region side is defined as D2, the width of the second interlayer insulating film 5 is defined as w, the thickness of the portion of the source electrode 3 above the gate electrode 6 is defined as ts1, and the thickness of the portion of the second source electrode 33 above the gate electrode 6 is defined as ts2, then D1>0, D2>0, D1-D2>0, and ts2>w>ts1 hold.

[0075] <Manufacturing Method> Fig. 27 is a flowchart showing a method for manufacturing a semiconductor device according to the fourth preferred embodiment. The manufacturing method shown in Fig. 27 is similar to the manufacturing method shown in Fig. 4, except that a second source electrode forming step S14 following the drain electrode forming step S13 is added. Therefore, the following description will mainly focus on the second source electrode forming step S14.

[0076] In the second source electrode formation step S14, a conductive film that becomes the second source electrode 33 is formed and patterned. The second source electrode 33 is made of a material with a higher thermal conductivity than the materials of the source electrode 3 and the semiconductor layer described above. For example, if the source electrode 3 is made of either an aluminum alloy containing aluminum and silicon, or nickel, it is suitable to form the second source electrode 33 from copper, silver, or gold. However, from an economical standpoint, it is preferable to form the second source electrode 33 from copper or an alloy mainly containing copper. The second source electrode 33 may be formed by either a physical vapor deposition (PVD) method or a plating method. The PVD method may be, for example, a sputtering method, and the plating method may be, for example, an electrolytic plating method or an electroless plating method.

[0077] The following describes an example in which electroless plating is used to form the second source electrode 33. Before forming the second source electrode 33 on the source electrode 3, the surface of the source electrode 3 is cleaned to remove oxide films, organic substances, foreign substances, etc. For cleaning, acid cleaning or plasma treatment is used, for example.

[0078] Since the material of the source electrode 3 is a metal whose main component is aluminum, such as aluminum, an aluminum-silicon alloy, or an aluminum-copper alloy, it is difficult to perform electroless plating of copper in this state. For this reason, the source electrode 3 is immersed in a zincate bath to perform a zincate treatment, which replaces the aluminum of the source electrode 3 with zinc, thereby replacing the surface of the source electrode 3 with zinc. Then, the second source electrode 33 can be easily formed by performing an electroless plating treatment using, for example, a copper sulfate bath maintained at approximately 60 to 80°C. Note that although the formation of the second source electrode 33 has been described above, the formation of the second gate wiring 32 is similar.

[0079] <Summary of Fourth Embodiment> In the fourth embodiment, the thickness ts2 of the portion of the second source electrode 33 above the gate electrode 6 is larger than the width w of the second interlayer insulating film 5, the width w of the second interlayer insulating film 5 is larger than the thickness ts1 of the portion of the source electrode 3 above the gate electrode 6, and the thermal conductivity of the second source electrode 33 is higher than the thermal conductivity of the semiconductor layer.

[0080] According to this configuration, heat generated in the semiconductor device due to current flow can not only be suppressed from increasing in temperature by the heat capacity of the second source electrode 33, but also the heat can be transferred to the outside via the second source electrode 33. This reduces the thermal stress on the gate electrode 6 and suppresses damage to the gate electrode 6, thereby improving the reliability of the semiconductor device during operation. Note that it is more preferable if the difference in the linear expansion coefficients of the second source electrode 33 and the gate electrode 6 is smaller than the difference in the linear expansion coefficients of the source electrode 3 and the gate electrode 6, as this further reduces the thermal stress on the gate electrode 6. Note that the content of the fourth embodiment may also be applied to, for example, Modification 2 of the first embodiment.

[0081] 28 is a schematic cross-sectional view showing the configuration of a semiconductor device according to Modification 1 of Embodiment 4. In Modification 1, the gate line 2 and the source electrode 3 are omitted, and the second gate line 32 and the second source electrode 33 are directly connected to the barrier metal layer 8. With this configuration, the source electrode formation step S11 in the flowchart of FIG. 27 can be omitted, and the second gate line 32 and the second source electrode 33 can be formed by a PVD method or a plating method, thereby simplifying the manufacturing process.

[0082] In this first modification, the thickness ts2 of the portion of the second source electrode 33 above the gate electrode 6 is greater than the width w of the second interlayer insulating film 5, and the thermal conductivity of the second source electrode 33 is higher than the thermal conductivity of the semiconductor layer. With this configuration, heat generated in the semiconductor device due to current flow can be transferred to the outside via the second source electrode 33. This reduces the thermal stress on the gate electrode 6 and suppresses damage to the gate electrode 6, thereby improving the reliability of the semiconductor device during operation.

[0083] Fifth Embodiment In this fifth embodiment, the semiconductor device according to the above-described first to fourth embodiments is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the following will describe the fifth embodiment in the case where the present disclosure is applied to a three-phase inverter.

[0084] FIG. 29 is a block diagram showing the configuration of a power conversion system to which a power conversion apparatus 200 according to the third embodiment is applied. The power conversion system shown in FIG. 29 includes a power supply 100, a power conversion apparatus 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion apparatus 200. The power supply 100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into predetermined power.

[0085] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300. The power conversion device 200 converts DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 29 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals that control the drive circuit 202 to the drive circuit 202.

[0086] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0087] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). By switching the switching elements, the main conversion circuit 201 converts DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. While the main conversion circuit 201 can have a variety of specific circuit configurations, the main conversion circuit 201 according to the fifth embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. The semiconductor device 1 according to any of the first to fourth embodiments and their modifications is used as at least one of the switching elements and freewheel diodes of the main conversion circuit 201. The six switching elements are connected in series with two switching elements to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0088] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is greater than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is smaller than the threshold voltage of the switching element.

[0089] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (ON time) that each switching element of the main conversion circuit 201 should be in the ON state, based on the power to be supplied to the load 300. For example, the control circuit 203 calculates the time so that the main conversion circuit 201 can be controlled by pulse width modulation (PWM) control, which modulates the ON time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each time point, and an OFF signal is output to the switching elements that should be in the OFF state. In accordance with this control signal, the drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0090] The manufacturing method of the power conversion device 200 includes the following steps. The semiconductor device 1 is manufactured by the manufacturing method described in the above-mentioned embodiment or its modified example. A main conversion circuit 201 having the semiconductor device 1 is formed, and a drive circuit 202 and a control circuit 203 are formed. This results in the power conversion device 200. When the main conversion circuit 201 is formed, the drain electrode of the semiconductor device 1 is bonded onto a mounting substrate, and the source electrode of the semiconductor device 1 is bonded to the mounting substrate via a wire.

[0091] In the power conversion device of this embodiment 5, the semiconductor device 1 of embodiments 1 to 4 is used as the semiconductor device that constitutes the main conversion circuit 201, thereby improving the reliability of the main conversion circuit 201 and the power conversion device during operation.

[0092] In the fifth embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. The power conversion device according to the fifth embodiment is a two-level power conversion device, but it may be a three-level or multi-level power conversion device. In addition, when supplying power to a single-phase load, the present disclosure may be applied to a single-phase inverter. Furthermore, when supplying power to a DC load or the like, the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0093] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0094] It should be noted that the embodiments (and their modifications) can be freely combined, and the embodiments and modifications can be modified or omitted as appropriate.

[0095] Various aspects of the present disclosure are summarized below as appendices.

[0096] (Supplementary Note 1) A semiconductor device having an active region and a termination region defined therein, comprising: a first interlayer insulating film provided in the termination region; and a gate electrode provided on the first interlayer insulating film, wherein when a first amount of heat generated on a reverse region side located on the opposite side of the gate electrode from the active region is larger than a second amount of heat generated on the active region side, a dimension of a first portion of the first interlayer insulating film on the reverse region side of the gate electrode is larger than a dimension of a second portion of the first interlayer insulating film on the active region side of the gate electrode, and when the second amount of heat generated is larger than the first amount of heat generated, a dimension of the second portion is larger than a dimension of the first portion.

[0097] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein when a distance between an end of an upper portion of the first portion on the reverse region side and an end of the gate electrode on the reverse region side is D1, and a distance between an end of an upper portion of the second portion on the active region side and an end of the gate electrode on the active region side is D2, if the first amount of heat generation is greater than the second amount of heat generation, D1>0, D2>0, and D1-D2>0 hold true, and if the second amount of heat generation is greater than the first amount of heat generation, D1>0, D2>0, and D2-D1>0 hold true.

[0098] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1, wherein, when a distance between an end of the first portion on the reverse region side and an end of the gate electrode on the reverse region side in a plan view is D3, and a distance between an end of the second portion on the active region side and an end of the gate electrode on the active region side is D4, if the first amount of heat generation is greater than the second amount of heat generation, D3>0, D4>0, and D3-D4>0 hold true, and if the second amount of heat generation is greater than the first amount of heat generation, D3>0, D4>0, and D4-D3>0 hold true.

[0099] (Additional Note 4) A semiconductor device having an active region and a termination region defined therein, comprising: a first interlayer insulating film provided in the termination region; and a gate electrode provided on the first interlayer insulating film, wherein when a first resistance value of an SBD region on a reverse region side located on the opposite side of the active region with respect to the gate electrode is larger than a second resistance value of a BD region on the active region side, a dimension of a first portion of the first interlayer insulating film on the reverse region side of the gate electrode is larger than a dimension of a second portion of the first interlayer insulating film on the active region side of the gate electrode, and when the second resistance value is larger than the first resistance value, a dimension of the second portion is larger than a dimension of the first portion.

[0100] (Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein when a distance between an end of an upper portion of the first portion on the reverse region side and an end of the gate electrode on the reverse region side is D1, and a distance between an end of an upper portion of the second portion on the active region side and an end of the gate electrode on the active region side is D2, if the first resistance value is larger than the second resistance value, D1>0, D2>0, and D1-D2>0 hold, and if the second resistance value is larger than the first resistance value, D1>0, D2>0, and D2-D1>0 hold.

[0101] (Supplementary Note 6) The semiconductor device according to Supplementary Note 4, wherein, when a distance between an end of the first portion on the reverse region side and an end of the gate electrode on the reverse region side in a planar view is D3, and a distance between an end of the second portion on the active region side and an end of the gate electrode on the active region side is D4, when the first resistance value is larger than the second resistance value, D3>0, D4>0, and D3-D4>0 hold, and when the second resistance value is larger than the first resistance value, D3>0, D4>0, and D4-D3>0 hold.

[0102] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, wherein the active region includes an SBD region.

[0103] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, wherein the active region includes: a plurality of SBD regions periodically arranged in a stripe pattern; and a plurality of MOS regions periodically arranged in a stripe pattern.

[0104] (Supplementary Note 9) The semiconductor device according to Supplementary Note 8, wherein the active region further includes a plurality of BD regions periodically provided in a stripe pattern.

[0105] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, wherein a thickness of the first interlayer insulating film is greater than the smaller of the dimensions of the first portion and the second portion.

[0106] (Appendix 11) A semiconductor device described in any one of Appendices 1 to 10, further comprising: a second interlayer insulating film covering the first interlayer insulating film and the gate electrode; a first electrode covering the second interlayer insulating film; and a second electrode covering the first electrode, wherein the thermal conductivity of the second electrode is higher than the thermal conductivity of a semiconductor layer on which the first interlayer insulating film is provided; the thickness of a portion of the second electrode above the gate electrode is greater than the width of the second interlayer insulating film; and the width of the second interlayer insulating film is greater than the thickness of a portion of the first electrode above the gate electrode.

[0107] (Supplementary Note 12) The semiconductor device according to Supplementary Note 11, wherein a difference in linear expansion coefficient between the second electrode and the gate electrode is smaller than a difference in linear expansion coefficient between the first electrode and the gate electrode.

[0108] (Supplementary Note 13) A power conversion device comprising: a main conversion circuit having the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 12, which converts input power and outputs the converted power; a drive circuit which outputs a drive signal to the semiconductor device for driving the semiconductor device; and a control circuit which outputs a control signal to the drive circuit for controlling the drive circuit.

[0109] REFERENCE SIGNS LIST 1 semiconductor device, 3 source electrode, 5 second interlayer insulating film, 6 gate electrode, 7 first interlayer insulating film, 20 SBD region, 22 MOS region, 23 BD region, 33 second source electrode, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit.

Claims

1. 1. A semiconductor device having an active region and a termination region defined therein, a first interlayer insulating film provided in the termination region; a gate electrode provided on the first interlayer insulating film; Equipped with when a first amount of heat generated on a reverse region side located on an opposite side of the active region with respect to the gate electrode is larger than a second amount of heat generated on the active region side, a dimension of a first portion of the first interlayer insulating film located on the reverse region side of the gate electrode is larger than a dimension of a second portion of the first interlayer insulating film located on the active region side of the gate electrode, When the second amount of heat generation is greater than the first amount of heat generation, a dimension of the second portion is greater than a dimension of the first portion.

2. 2. The semiconductor device according to claim 1, When a distance between an end of an upper portion of the first portion on the side of the reverse region and an end of the gate electrode on the side of the reverse region is D1, and a distance between an end of the upper portion of the second portion on the side of the active region and an end of the gate electrode on the side of the active region is D2, When the first heat generation amount is greater than the second heat generation amount, D1>0, D2>0, and D1-D2>0 are satisfied; When the second amount of heat generation is larger than the first amount of heat generation, D1>0, D2>0, and D2-D1>0 are satisfied.

3. 2. The semiconductor device according to claim 1, When a distance between an end of the first portion on the reverse region side and an end of the gate electrode on the reverse region side in a plan view is D3, and a distance between an end of the second portion on the active region side and an end of the gate electrode on the active region side is D4, When the first heat generation amount is greater than the second heat generation amount, D3>0, D4>0, and D3-D4>0 are satisfied; When the second amount of heat generation is larger than the first amount of heat generation, D3>0, D4>0, and D4-D3>0 are satisfied.

4. 1. A semiconductor device having an active region and a termination region defined therein, a first interlayer insulating film provided in the termination region; a gate electrode provided on the first interlayer insulating film; Equipped with When a first resistance value of an SBD region on a reverse region side located on an opposite side of the active region with respect to the gate electrode is larger than a second resistance value of a BD region on the active region side, a dimension of a first portion of the first interlayer insulating film on the reverse region side of the gate electrode is larger than a dimension of a second portion of the first interlayer insulating film on the active region side of the gate electrode, When the second resistance value is greater than the first resistance value, a dimension of the second portion is greater than a dimension of the first portion.

5. 5. The semiconductor device according to claim 4, When a distance between an end of an upper portion of the first portion on the side of the reverse region and an end of the gate electrode on the side of the reverse region is D1, and a distance between an end of the upper portion of the second portion on the side of the active region and an end of the gate electrode on the side of the active region is D2, When the first resistance value is greater than the second resistance value, D1>0, D2>0, and D1-D2>0 are satisfied; When the second resistance value is larger than the first resistance value, D1>0, D2>0, and D2-D1>0 are satisfied.

6. 5. The semiconductor device according to claim 4, When a distance between an end of the first portion on the reverse region side and an end of the gate electrode on the reverse region side in a plan view is D3, and a distance between an end of the second portion on the active region side and an end of the gate electrode on the active region side is D4, When the first resistance value is greater than the second resistance value, D3>0, D4>0, and D3-D4>0 are satisfied; When the second resistance value is larger than the first resistance value, D3>0, D4>0, and D4-D3>0 are satisfied.

7. 5. The semiconductor device according to claim 1, The active region includes an SBD region.

8. 5. The semiconductor device according to claim 1, The active region comprises: A plurality of SBD regions periodically provided in a stripe shape; A plurality of MOS regions periodically arranged in a stripe pattern; 13. A semiconductor device comprising:

9. 9. The semiconductor device according to claim 8, The active region further includes a plurality of BD regions periodically provided in a stripe pattern.

10. 5. The semiconductor device according to claim 1, a thickness of the first interlayer insulating film is greater than the smaller of a dimension of the first portion and a dimension of the second portion.

11. 5. The semiconductor device according to claim 1, a second interlayer insulating film covering the first interlayer insulating film and the gate electrode; a first electrode covering the second interlayer insulating film; A second electrode covering the first electrode; Further equipped with the second electrode has a thermal conductivity higher than a thermal conductivity of a semiconductor layer on which the first interlayer insulating film is provided, a thickness of the second electrode above the gate electrode is greater than a width of the second interlayer insulating film; a width of the second interlayer insulating film is greater than a thickness of a portion of the first electrode above the gate electrode.

12. 12. The semiconductor device according to claim 11, a difference in linear expansion coefficient between the second electrode and the gate electrode is smaller than a difference in linear expansion coefficient between the first electrode and the gate electrode.

13. a main conversion circuit having the semiconductor device according to claim 1 or 4, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal to the drive circuit; A power conversion device comprising: